Processor, method, device and storage medium for data processing

Abstract

According to an embodiment of the present invention, a processor, a method for data processing, a device, and a storage medium are provided. The processor includes a plurality of processor cores, and each of the plurality of processor cores includes a data cache for reading and writing data and an instruction cache separated from the data cache for reading instructions. The processor further includes a distributor communicatively coupled to the plurality of processor cores. The distributor is configured to distribute data to be processed to a corresponding data cache of at least one of the plurality of processor cores and distribute instructions associated with the data to be processed to a corresponding instruction cache of at least one of the plurality of processor cores for execution. Thereby, the efficiency of data transmission and vector calculation can be significantly improved.

Description

[Technical Field]

[0001] [Cross-Citation of Related Applications] This application claims priority to a Chinese patent application for invention entitled "Processor, method, device, and storage medium for data processing" filed on June 14, 2022, with application number 202210674851.9, the entire contents of which are incorporated herein by reference.

[0002] [Technical field] FIELD OF THE INVENTION Exemplary embodiments of the present invention relate generally to the field of computers, and more particularly to processors, methods, devices, and computer-readable storage media for data processing. [Background technology]

[0003] With the development of information technology, various data processing services are placing increasing requirements on the computing power and computing resources of computing systems. Currently, it has been proposed to use multi-core processors to improve the overall computing power and computing throughput of systems through parallel computing. For some vector calculations that involve many instruction repetitions and large data volumes, how to fully utilize the limited bandwidth of multi-core processors to process such vector calculations has become a hot topic. Summary of the Invention

[0004] In a first aspect of the present invention, a processor is provided, the processor comprising a plurality of processor cores, each comprising a data cache for reading and writing data and an instruction cache, separate from the data cache, for reading instructions. The processor further comprises a distributor communicatively coupled to the plurality of processor cores, the distributor configured to distribute data to be processed to a corresponding data cache of at least one of the plurality of processor cores and to distribute instructions associated with the data to a corresponding instruction cache of at least one of the processor cores for execution.

[0005] In a second aspect of the present invention, a method for data processing is provided, the method including distributing, by a distributor of a processor, data to be processed to a corresponding data cache of at least one processor core among a plurality of processor cores of the processor, the distributor being communicatively coupled to the plurality of processor cores, the method further including distributing instructions associated with the data to be processed to a corresponding instruction cache of the at least one processor core for execution.

[0006] In a third aspect of the present invention, there is provided an electronic device, the electronic device comprising at least the processor of the first aspect.

[0007] In a fourth aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements the method of the second aspect.

[0008] It should be understood that the contents described in this Summary of the Invention are not intended to limit the main or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will be readily apparent from the following description. [Brief explanation of the drawings]

[0009] The above-mentioned and other features, advantages, and aspects of the embodiments of the present invention will become more apparent from the following detailed description taken in conjunction with the drawings, in which like or similar symbols indicate like or similar elements, and in which: [Figure 1] 1 shows a schematic diagram of an exemplary environment in which embodiments of the present invention may be implemented; [Figure 2] 1 shows a schematic diagram of an architecture for distribution of instructions and data according to some embodiments of the present invention; [Figure 3] 1 shows a schematic diagram for broadcasting instructions to multiple processor cores according to some embodiments of the present invention; [Figure 4] 1 shows a schematic diagram of cyclical data writing, execution, and reading by a processor core according to some embodiments of the present invention; [Figure 5] 1 illustrates a flowchart of a process for data processing according to some embodiments of the present invention; [Figure 6] 1 illustrates a block diagram of an electronic device that may include a processor in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the drawings. Although the drawings show specific embodiments of the present invention, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, but rather, these embodiments are provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes and are not used to limit the protection scope of the present invention.

[0011] In describing embodiments of the present invention, the term "comprising" and similar terms are intended to be open-ended inclusions, including, but not limited to, the term "based on" should be understood as "based at least in part on." The terms "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The term "some embodiments" should be understood as "at least some embodiments." Other explicit and implicit definitions may be included below.

[0012] It is understood that data related to the present technical solution (including but not limited to the data itself, the acquisition of data, or the use of data) should comply with applicable laws and regulations and related specified requirements.

[0013] As mentioned above, with the development of information technology, various data processing services are placing increasing requirements on the computing power and computing resources of computing systems. Currently, it has been proposed to use multi-core processors to improve the overall computing power and computing throughput of a system through parallel computing. Generally, each processor core in a multi-core processor is an independent and complete instruction execution unit. When multiple processor cores work together, for example, when multiple processor cores need to access the same storage address, instruction or data conflicts may occur.

[0014] A conventional solution to address the instruction or data conflict problem described above is to use a mailbox policy for instructions. For example, multiple processor cores send instructions to each other through mailboxes when they need to perform operations synchronously. For data, a conventional solution is to use a cache coherency policy, such as modified exclusive shared invalidation (MESI) technology, to ensure that data in the cache is the same as data in main memory. An example of a multi-core processor architecture that uses the conventional policy described above is the big.LITTLE architecture.

[0015] Research has shown that some vector calculations with high instruction repetition rates and large data volumes often use single instruction, multiple data (SIMD) processors in multi-core architectures. On the one hand, using traditional multi-core processor architectures based on cache coherency results in small first-level caches for SIMD processors. Also, the large amount of calculation data and low locality result in a large number of cache misses, reducing data read and write efficiency. On the other hand, such typical vector calculations rarely require complex thread switching tasks, making traditional multi-core processor control modes appear bloated and redundant.

[0016] In summary, for some vector calculations with high instruction repetition and large data volume, how to make multi-core processors fully utilize their limited bandwidth to process such vector calculations has become a hot topic.

[0017] According to an embodiment of the present invention, an improved solution for a processor is proposed, in which a distributor is provided within the processor to distribute data and / or instructions to each processor core of the processor. By using the distributor to centrally schedule the distribution of data and / or instructions instead of using a traditional cache coherency design, many cache coherency issues in multi-core processors are avoided.

[0018] On the other hand, in conventional processors based on cache coherency, data transmission and processing are often highly complex, resulting in limited data storage capacity and making it difficult to increase clock frequencies. In this solution, a distributor distributes data to the data caches of each processor core for data read and write. By directly transmitting data using each processor core's data cache and the distributor, a large data cache can be used and data exchange with the outside world can be minimized.

[0019] On the other hand, in conventional multi-core scheduling methods, processors typically initiate data transmission requests proactively, making it difficult for a single processor to know the data requests of other processors. This means that data cannot be transmitted in a broadcast manner. The present solution uses a centralized data scheduling mechanism, making it easy to transmit data in a broadcast manner, further improving data transmission efficiency. In this way, the present solution can fully utilize limited bandwidth resources and further improve the efficiency of vector computation, especially vector computation for neural networks.

[0020] In the following, several exemplary embodiments of the present invention will be described with continued reference to the drawings.

[0021] 1 illustrates a schematic diagram of an exemplary environment 100 in which embodiments of the present invention can be implemented. In the exemplary environment 100, a processor 101 is a multi-core processor including processor cores 120-1, 120-2, ..., 120-N, where N is an integer greater than 1. For ease of explanation, processor cores 120-1, 120-2, ..., 120-N are hereinafter referred to collectively or individually as processor cores 120. Each processor core 120 may be a SIMD processor core. In some embodiments, the processor 101 may include four processor cores 120 (i.e., the value of N may be 4).

[0022] Of course, unless otherwise specified, it should be understood that any specific numerical values ​​appearing here and elsewhere herein are exemplary. For example, in other embodiments, there may be a correspondingly different number of processor cores 120 according to different metrics, such as, for example, process levels, line widths, etc. of the flow chip.

[0023] Processor 101 further includes a distributor 110. Distributor 110 is communicatively coupled to each processor core 120. That is, distributor 110 and each processor core 120 can communicate with each other according to an appropriate data transmission protocol and / or standard. In operation, distributor 110 can distribute data 140 and / or instructions 130 to each processor core 120. Note that distributor 110 is sometimes referred to as a "scheduler," and the terms are sometimes used interchangeably in this context.

[0024] In some embodiments, distributor 110 may be implemented as a hardware circuit, which may be integrated into or embedded in processor 101. Alternatively or additionally, distributor 110 may be implemented in whole or in part by software modules, which may be implemented, for example, as executable instructions and stored in a memory (not shown).

[0025] Distributor 110 is configured to distribute instructions 130 and / or data 140 received by processor 101 from other devices (not shown) within environment 100 to each processor core 120. A device that sends instructions 130 and / or data 140 to distributor 110 is also referred to as a source device of a data processing request. In some embodiments, processor 101 receives data 140 and / or instructions 130 transmitted by a storage device or other external device within environment 100, for example, via a bus, and distributes the received data 140 and / or instructions 130 via distributor 110 to each processor core 120. The distribution process for data 140 and / or instructions 130 is described below in conjunction with FIG. 2.

[0026] It should be understood that the configuration and functionality of the environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of the present invention. For example, the processor 101 may be applied to various existing or future computing platforms or computing systems. The processor 101 may be implemented in various embedded applications (e.g., data processing systems such as mobile network base stations) to provide services such as large-scale vector calculations. The processor 101 may be integrated or embedded in various electronic or computing devices to provide various computational services. The application environments and application scenarios of the processor 101 are not limited herein.

[0027] 2 illustrates a schematic diagram of an exemplary architecture 200 for distribution of instructions 130 and data 140 according to some embodiments of the present invention. For ease of explanation, the architecture 200 will be described with reference to the environment 100 of FIG.

[0028] 2, each of the multiple processor cores 120 includes a data cache for reading and writing data and an instruction cache, separate from the data cache, for reading instructions. For example, processor core 120-1 includes instruction cache 220-1 and data cache 230-1, processor core 120-2 includes instruction cache 220-2 and data cache 230-2, ..., processor core 120-N includes instruction cache 220-N and data cache 230-N. For ease of explanation, hereinafter, instruction caches 220-1, 220-2, ..., 220-N will be collectively or individually referred to as instruction cache 220, and data caches 230-1, 230-2, ..., 230-N will be collectively or individually referred to as data cache 230.

[0029] Note that instruction cache 220 is not typically implemented as a cache. From the perspective of processor 101, instruction cache 220 is read-only. Data cache 230 may include a Vector Closely-coupled Memory (VCCM). Like instruction cache 220, data cache 230 is not typically implemented as a cache. However, unlike instruction cache 220, data cache 230 is readable and writable. Using a VCCM as data cache 230 instead of a cache can reduce the design complexity of processor 101 and allow for increased processor cache capacity and clock frequency. In this way, data transfer efficiency of processor 101 can be improved.

[0030] In some embodiments, distributor 110 is configured to distribute received instructions 130 and / or data 140 to at least one processor core 120 of the plurality of processor cores 120. For example, distributor 110 may be configured to distribute received instructions 130 and / or data 140 to only first processor core 120-1. Also, for example, distributor 110 may distribute received instructions 130 and / or data 140 to first processor core 120-1 and second processor core 120-2. Alternatively, distributor 110 may distribute instructions 130 and / or data 140 to each processor core 120 of the plurality of processor cores 120. In some embodiments, distributor 110 may receive configuration information 210. The configuration information 210 may instruct the distributor 110 to distribute the instructions 130 and / or data 140 to one or some of the multiple processor cores 120. For example, the configuration information 210 may instruct the distributor 110 to distribute the instructions 130 and / or data 140 to only the first processor core 120-1. Also, for example, the configuration information 210 may instruct the distributor 110 to distribute the instructions 130 and / or data 140 to each processor core 120 of the multiple processor cores 120. Alternatively or additionally, the distributor 110 may be pre-programmed to distribute the instructions 130 and / or data 140 to one or some of the processor cores 120, or to all of the processor cores 120.

[0031] In some embodiments, distributor 110 may receive a data set and an instruction set to be processed by processor 101. Configuration information 210 received by distributor 110 may indicate at least an association between data to be processed (also referred to as data 140) in the data set and instructions 130 in the instruction set. For example, the association between data 140 and instructions 130 may indicate that data 140 in the data set is to be processed according to instructions 130 in the instruction set. Distributor 110 may distribute data 140 and instructions 130 based at least in part on the association. For example, distributor 110 distributes data 140 to a corresponding data cache 230 of at least one processor core 120 among multiple processor cores 120, and distributes instructions 130 associated with data 140 to a corresponding instruction cache 220 of at least one processor core 120 for execution.

[0032] In some embodiments, distributor 110 may broadcast the same instruction 130 to at least one processor core. FIG. 3 illustrates a schematic diagram for broadcasting instructions 130 to multiple processor cores according to some embodiments of the present invention. As illustrated in FIG. 3, instructions 130 may include instruction 0, instruction 1, ..., instruction M (where M is an integer greater than or equal to 1). Instruction 130 may be broadcast to processor cores 120-1, 120-2, ..., 120-J (where J is an integer greater than 1) via distributor 110. For example, instructions 310-1, 310-2, ..., 310-J identical to instruction 130 are broadcast to processor cores 120-1, 120-2, ..., 120-J. For ease of explanation, instructions 310-1, 310-2, ..., 310-J will hereinafter be collectively or individually referred to as instructions 310. It should be understood that there may be a delay 320 between the time that the instruction 310 is received at the processor core 120 and the time that the instruction 130 is received at the distributor 110 .

[0033] 3 illustrates broadcasting the instruction 130 to processor cores 120-1, 120-2, ..., 120-J, it should be understood that in some embodiments, distributor 110 may broadcast the instruction 130 to more or fewer of the multiple processor cores 120. For example, distributor 110 may broadcast the instruction 130 to only one processor core 120. Also, for example, distributor 110 may broadcast the instruction 130 to all processor cores 120 (i.e., J equals N). The processor cores 120 or some of the processor cores 120 to which distributor 110 broadcasts the instruction 130 may be preset or may be set based on received configuration information 210.

[0034] Alternatively, in some embodiments, distributor 110 may use other transmission methods to distribute instructions 130 to each processor core 120. For example, distributor 110 may first send instructions 130 to processor core 120-1, and then send instructions 130 to processor core 120-2, and so on. Compared to such a sequential distribution method, distributing instructions using a broadcast method can reduce the overhead of repeatedly reading instructions, and thus can significantly reduce the overhead of instruction transmission.

[0035] In the above example of broadcasting the same instruction to each processor core, distributor 110 may send different data to be processed that is associated with the instruction to each of the different processor cores 120. For example, distributor 110 may broadcast or send first data of data 140 to first processor core 120-1 for processing and may broadcast or send second data, different from the first data of data 140, to second processor core 120-2 for processing.

[0036] Such an arrangement is beneficial because, for example, in many computing scenarios such as neural network inference, there are many scenarios in which the same instruction is used to operate on different data, and in such scenarios, by broadcasting the same instruction and different data to different processor cores 120 in a broadcast manner, the overhead of instruction and data transmission can be significantly reduced, and thus data processing efficiency can be improved.

[0037] 3 only illustrates an example of broadcasting the same instruction 130 to each processor core 120, it should be understood that, alternatively or additionally, in some embodiments, the same data may be broadcast to each processor core 120 using a process similar to that of FIG. 3. For example, data 140 may be broadcast to at least one processor core 120 of the multiple processor cores 120. In such an example, different instructions associated with data 140 may be distributed to different processor cores 120. For example, a first instruction of instructions 130 may be sent or broadcast to processor core 120-1, causing processor core 120 to process data 130 based on the first instruction, and a second instruction of instructions 130 may be sent or broadcast to processor core 120-2, causing processor core 120-2 to process data 140 based on the second instruction.

[0038] This method of distributing the same data and different instructions to each processor core 120 is applicable to many data processing scenarios, such as specific data processing processes that involve a small amount of data but a complex processing process. For example, in neural network computing, there are often scenarios in which different calculation processes are used for the same data. The above-described method of distributing the same data and different instructions to each processor core 120 can be well applied to such scenarios. This can significantly reduce the overhead of such data and instruction transmission processes, thereby improving data processing efficiency.

[0039] 2 , each processor core 120 is configured to execute instructions according to an associated execution pipeline 240-1, 240-2, ..., 240-N. For ease of explanation, execution pipelines 240-1, 240-2, ..., 240-N are hereinafter referred to collectively or individually as execution pipelines 240. Execution pipelines 240 are configured to process data in data cache 230 using instructions in instruction cache 220. For example, execution pipeline 240 may process data written into data cache 230 according to instructions in instruction cache 220 and send the processed results to data cache 230. Alternatively or additionally, each processor core 120 may send the processed results from data cache 230 to distributor 110.

[0040] In some embodiments, the distributor 110 may receive the processing results from the corresponding data cache 230 of at least one processor core 120. Additionally, the distributor 110 may transmit the processing results of the received data to other devices, such as the device that originated the data processing request. This allows the distributor 110 to handle the exchange of external data with data in the data cache 230 of the processor core 120, thereby reducing data exchange with the outside of the processor core 120.

[0041] In some embodiments, distributor 110 may distribute instructions 130 and data 140 associated with the instructions to each processor core 120. Each processor core 120 may process the received data 140 in accordance with instructions 130 and send the processing results to distributor 110.

[0042] In some embodiments, distributor 110 may employ a cyclical approach to read and write data from data cache 230. For example, distributor 110 may distribute third data of data to be processed (e.g., data 140) to a first processor core 120-1 among at least one processor core 120 for processing. In response to receiving a first result obtained by processing the third data from processor core 120-1, distributor 110 distributes fourth data of the data to be processed, which is different from the third data, to first processor core 120-1.

[0043] FIG. 4 is a schematic diagram illustrating cyclic data writing, instruction execution, and data reading by the processor core 120 according to some embodiments of the present invention. As shown in FIG. 4, the distributor 110 transmits data 410-1 to the processor core 120. The processor core 120 writes the received data 410-1 to the data cache 230 by performing data write 430-1 on the data 410-1. The processor core 120 performs instruction execution 440-1 using the execution pipeline 240 shown in FIG. 2 or the like according to the instruction associated with the received data 410-1. The processor core 120 then performs data read 450-1 from the data cache 230 to obtain the results obtained by the instruction execution 440-1. The processor core 120 transmits the read data 420-1 to the distributor 110.

[0044] In response to receiving data 420-1 from processor core 120, distributor 110 transmits data 410-2 to processor core 120. Processor core 120 further performs processes such as data write 430-2, instruction execution 440-2, and data read 450-2 on data 410-2, and transmits processed data 420-2 corresponding to read data 410-2 to distributor 110.

[0045] Similarly, in response to receiving the previous data processing result from the processor core 120, the distributor 110 may send data 410-K (where K is an integer greater than 1) to the processor core 120. The processor core 120 may further perform processes on the data 410-K, such as data write 430-K, instruction execution 440-K, and data read 450-K, and send processing result data 420-K corresponding to the read data 410-K to the distributor 110. The instructions associated with the data 410-1, 410-2, ..., 410-K may be the same instruction, and the instruction may be transmitted to the processor core 120 only once by the distributor 110. In some embodiments, the number K of times the data is read, written, and processed periodically may be preset. Alternatively or additionally, the number K of times the data is read, written, and processed periodically may be set based on the configuration information 210 received by the distributor 110.

[0046] 4 illustrates the process of periodically reading, writing, and processing data for only one processor core 120, it should be understood that a similar process can be followed to periodically read, write, and process data for the other processor cores 120. Such a periodic approach facilitates loading large amounts of data into the data cache 230 of the processor core 120. In this manner, instructions are distributed only once, and the data associated with the instructions is periodically read, written, and processed, further reducing instruction and data transmission overhead.

[0047] It should be understood that, unless otherwise specified, the above-described processes of data distribution, command distribution, etc. may be performed in any suitable order. The above-described embodiments of data distribution, command distribution, and the embodiments of data reading, writing, and processing may be implemented in combination.

[0048] 2 to 4, various embodiments have been described in which instructions and / or data are distributed to each processor core 120 using the distributor 110. By employing an embodiment of the present invention, on the one hand, the distributor distributes data to the data cache of each processor core, and the data cache of each processor core directly transmits data to the distributor, allowing each processor core to use a large-capacity data cache and minimizing data exchange with the outside of the processor core.

[0049] On the other hand, the embodiment of the present solution uses a centralized data scheduling or distribution mechanism, and easily applies a broadcast method to transmit data and / or instructions, which can further improve the transmission efficiency of data and instructions, thereby enabling the present solution to fully utilize limited bandwidth resources and further improve the efficiency of vector calculations, etc.

[0050] For computations such as neural network training and / or inference, the bandwidth required by the underlying computing unit is often several times, or even tens of times, the bandwidth that can be provided externally. The solution of the present invention can fully utilize limited bandwidth resources, thereby improving the computing efficiency of neural network accelerators and the like.

[0051] 5 shows a flowchart of a process 500 for data processing according to some embodiments of the present invention. Process 500 may be implemented in distributor 110 of processor 101. For ease of explanation, process 500 will be described with reference to environment 100 of FIG.

[0052] At block 510, distributor 110 distributes data to be processed (e.g., data 140) to a corresponding data cache 230 of at least one processor core 120 of the multiple processor cores 120. For example, distributor 110 may distribute data 140 to each processor core 120 of the multiple processor cores 120 or to one or more processor cores 120 among the multiple processor cores 120. At block 520, distributor 110 distributes instructions 130 associated with the data to be processed (e.g., data 140) to a corresponding instruction cache 220 of at least one processor core 120 for execution. For example, distributor 110 may distribute instructions 130 to each processor core 120 of the multiple processor cores 120 or to one or more processor cores 120 among the multiple processor cores 120.

[0053] In some embodiments, distributor 110 may distribute instructions 130 to at least one processor core 120 by broadcasting instructions 130 to at least one processor core 120. In such an example, distributor 110 may send first data of data 140 to a first processor core 120-1 of at least one processor core 120 for processing and send second data of data 140, different from the first data, to a second processor core 120-2 of at least one processor core 120 for processing.

[0054] Additionally or alternatively, in some embodiments, distributor 110 may distribute data 140 to at least one processor core 120 by broadcasting data 140 to at least one processor core 120. In such an example, distributor 110 may send a first instruction of instructions 130 to a first processor core 120-1 of at least one processor core 120, thereby enabling the first processor core 120-1 to process data 140 based on the first instruction. Distributor 110 may send a second instruction, different from the first instruction of instructions 130, to a second processor core 120-2 of at least one processor core 120, thereby enabling the second processor core 120-2 to process data 140 based on the second instruction.

[0055] In some embodiments, at block 530, distributor 110 is further configured to receive processing results from corresponding data caches 230 of at least one processor core 120, respectively. The processing results are obtained by at least one processor core 120 processing the received data 140 in accordance with instructions 130. For example, distributor 110 may distribute third data of data 140 to a first processor core 120-1 of at least one processor core 120 for processing. In response to receiving a first result obtained by processing the third data from first processor core 120-1, distributor 110 distributes fourth data, different from the third data of data 140, to first processor core 120-1 for processing.

[0056] In some embodiments, distributor 110 further receives a data set and an instruction set to be processed by processor 101. Distributor 110 also receives configuration information, which indicates at least an association between data to be processed (e.g., data 140) in the data set and instructions 130 in the instruction set. For example, the association between data 140 and instructions 130 indicates that data 140 is to be processed by instructions 130. In such examples, the distribution of data 140 and instructions 130 can depend, at least in part, on the association.

[0057] 5 depicts the steps in a particular order, it should be understood that some or all of these steps may be performed in other orders or in parallel. For example, box 510 in FIG. 5 may be performed before or after block 520. The scope of the present invention is not limited in this respect.

[0058] 6 shows a block diagram of an electronic device 600 including a processor 101 in accordance with one or more embodiments of the present invention. It should be understood that the electronic device 600 shown in FIG. 6 is exemplary only and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0059] 6, electronic device 600 is in the form of a general-purpose electronic or computing device. Components of electronic device 600 may include, but are not limited to, one or more processors 101, memory 620, storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. In some embodiments, processor 101 may perform various processes based on programs stored in memory 620. Each processor core 120 of processor 101 may execute computer-executable instructions in parallel, thereby enhancing the parallel processing capabilities of electronic device 600.

[0060] The electronic device 600 typically includes multiple computer storage media. Such media may be any obtainable media accessible by the electronic device 600, including, but not limited to, volatile and nonvolatile media, removable and non-removable media. The memory 620 may be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 630 may be removable or non-removable media and may include machine-readable media, such as a flash memory drive, a magnetic disk, or any other media, that may be used to store information and / or data (e.g., training data for training) and accessible within the electronic device 600.

[0061] The electronic device 600 may further include other removable / non-removable, volatile / non-volatile storage media. Although not shown in FIG. 6 , a magnetic disk drive for reading from or writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”) and an optical disk drive for reading from or writing to a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to a path (not shown) by one or more data media interfaces. The memory 620 may include a computer program product 625 having one or more program modules configured to perform various methods or operations of various embodiments of the present invention. For example, these program modules may be configured to implement various functions or operations of the distributor 110.

[0062] The communication unit 640 implements communication with other computing devices over a communication medium. Additionally, the functionality of the components of the electronic device 600 may be implemented as a single computing cluster or multiple computing machines, which can communicate over a communication connection. Thus, the electronic device 600 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or other network nodes.

[0063] The input device(s) 650 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device(s) 660 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 600 may further communicate with one or more external devices (not shown) such as a storage device, a display device, etc. via the communication unit 640, as needed, to communicate with one or more devices that allow a user to interact with the electronic device 600, or with any device (net card, modem, etc.) that communicates with one or more other electronic or computing devices. Such communication may be performed via an input / output (I / O) interface (not shown).

[0064] According to an exemplary implementation of the present invention, a computer-readable storage medium having stored thereon one or more computer instructions, the one or more computer instructions being executed by a processor to implement the above-described method, is provided. According to an exemplary implementation of the present invention, a computer program product is further provided, the computer program product being tangibly stored on a non-transitory computer-readable medium and including computer-executable instructions being executed by a processor to implement the above-described method.

[0065] Aspects of the present invention have been described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems), and computer program products implemented by the present invention. It will be understood that each box in the flowchart and / or block diagrams, and combinations of boxes in the flowchart and / or block diagrams, can all be implemented by computer-readable program instructions.

[0066] These computer-readable program instructions may be provided to a processing unit of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to generate a machine such that, when the instructions are executed by the processing unit of the computer or other programmable data processing apparatus, it generates an apparatus for implementing the functions / acts specified in one or more boxes in the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium such that the instructions cause the computer, programmable data processing apparatus, and / or other device to operate in a particular manner such that the computer-readable medium on which the instructions are stored constitutes an article of manufacture containing instructions that implement each aspect of the functions / acts specified in one or more boxes in the flowcharts and / or block diagrams.

[0067] Loading the computer-readable program instructions into a computer, other programmable data processing apparatus, or other device causes the computer, other programmable data processing apparatus, or other device to perform a series of operational steps to produce a computer-implemented process, such that the instructions executing on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes in the flowcharts and / or block diagrams.

[0068] According to one or more embodiments of the present invention, Example 1 describes a processor including a plurality of processor cores. Each of the plurality of processor cores includes a data cache for reading and writing data and an instruction cache for reading instructions, the data cache being separate from the data cache. The processor further includes a distributor communicatively coupled to the plurality of processor cores. The distributor is configured to distribute data to be processed to a corresponding data cache of at least one of the plurality of processor cores and to distribute instructions associated with the data to a corresponding instruction cache of at least one of the processor cores for execution.

[0069] According to one or more embodiments of the invention, Example 2 includes the processor described above with reference to Example 1, wherein distributing the instructions to the at least one processor core includes broadcasting the instructions to the at least one processor core.

[0070] According to one or more embodiments of the invention, Example 3 includes the processor as described above for Example 2, wherein distributing the data to be processed to the at least one processor core includes transmitting first data of the data to be processed to the first processor core for processing and transmitting second data of the data to be processed to the second processor core for processing, the second data being different from the first data.

[0071] According to one or more embodiments of the invention, Example 4 includes the processor described above with reference to Example 1, wherein distributing the data to be processed to the at least one processor core includes broadcasting the data to be processed to the at least one processor core.

[0072] According to one or more embodiments of the invention, Example 5 includes the processor described above with respect to Example 4, where distributing the instructions to the at least one processor core includes sending a first instruction to a first processor core such that the first processor core processes the data to be processed according to the first instruction, and sending a second instruction to a second processor core such that the second processor core processes the data to be processed according to the second instruction, wherein the first instruction is different from the second instruction.

[0073] According to one or more embodiments of the invention, Example 6 includes the processor described above with reference to Example 1, wherein the distributor further receives processing results from a corresponding data cache of each of the at least one processor core, the processing results being obtained by processing the received data to be processed by the at least one processor core in accordance with the instructions.

[0074] According to one or more embodiments of the invention, Example 7 includes the processor described above with respect to Example 6, wherein distributing the data to be processed to the at least one processor core includes distributing third data of the data to be processed to a first processor core of the at least one processor core for processing, and distributing fourth data of the data to be processed to the first processor core for processing in response to receiving a first result obtained by processing the third data from the first processor core, wherein the third data is different from the fourth data.

[0075] According to one or more embodiments of the invention, Example 8 includes the processor described under Example 1, wherein the distributor further receives a data set and an instruction set to be processed by the processor, and receives configuration information, the configuration information indicating at least an association between data to be processed in the data set and instructions in the instruction set, and distribution of the data to be processed and instructions is at least partially dependent on the association.

[0076] Example 9 describes a method of processing data, according to one or more embodiments of the invention. The method includes distributing, by a distributor of a processor, data to be processed to a corresponding data cache of at least one processor core among a plurality of processor cores of the processor. The distributor is communicatively coupled to the plurality of processor cores. The method further includes distributing instructions associated with the data to be processed to a corresponding instruction cache of the at least one processor core for execution.

[0077] According to one or more embodiments of the invention, Example 10 includes the method described above with reference to Example 9, wherein distributing the instructions to the at least one processor core includes broadcasting the instructions to the at least one processor core.

[0078] According to one or more embodiments of the invention, Example 11 includes the method as described above with respect to Example 10, wherein distributing the data to be processed to the at least one processor core includes distributing first data of the data to be processed to the first processor core for processing and distributing second data of the data to be processed to the second processor core for processing, wherein the first data is different from the second data.

[0079] According to one or more embodiments of the invention, Example 12 includes the method described above with reference to Example 9, wherein distributing the data to be processed to the at least one processor core includes broadcasting the data to be processed to the at least one processor core.

[0080] According to one or more embodiments of the invention, Example 13 includes the method described above with respect to Example 12, where distributing instructions to at least one processor core includes sending a first instruction to a first processor core such that the first processor core processes the data to be processed according to the first instruction, and sending a second instruction to a second processor core such that the second processor core processes the data to be processed according to the second instruction, wherein the first instruction is different from the second instruction.

[0081] According to one or more embodiments of the invention, Example 14 includes the method described above with respect to Example 9. The method further includes receiving processing results from a corresponding data cache of each of the at least one processor core, the processing results being obtained by processing the received data to be processed by the at least one processor core in accordance with the instructions.

[0082] According to one or more embodiments of the invention, Example 15 includes the method described above with respect to Example 14, where distributing the data to be processed to the at least one processor core includes distributing third data of the data to be processed to a first processor core of the at least one processor core for processing, and in response to receiving a first result obtained by processing the third data from the first processor core, distributing fourth data of the data to be processed to the first processor core for processing, wherein the third data is different from the fourth data.

[0083] According to one or more embodiments of the invention, Example 16 includes the method described above with respect to Example 9. The method further includes receiving a data set and an instruction set to be processed by the processor, and receiving configuration information, the configuration information indicating at least an association between data to be processed in the data set and instructions in the instruction set, and distribution of the data to be processed and the instructions depending at least in part on the association.

[0084] Example 17 describes an electronic device, according to one or more embodiments of the present invention, including at least the processor of any one of Examples 1 to 8.

[0085] According to one or more embodiments of the present invention, Example 18 describes a computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements a method as described in any one of Examples 9 to 16.

[0086] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of various possible systems, methods, and computer program products according to the present invention. In this regard, each box in the flowcharts or block diagrams may represent a module, program segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions depicted in the boxes may occur in a different order than depicted in the figures. For example, two consecutive boxes may actually be executed substantially in parallel, or may be executed in the reverse order, depending on the functionality involved. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, may be implemented by a special-purpose hardware-based system that performs the specified function(s) or operation(s), or by a combination of special-purpose hardware and computer instructions.

[0087] Although various implementations of the present invention have been described above, the above descriptions are illustrative and not exhaustive, and are not limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is intended to best interpret the principles, practical applications, or improvements to commercially available technologies of the implementations, or to enable those skilled in the art to understand the implementations disclosed herein.

Claims

1. a plurality of processor cores each including a data cache for reading and writing data and an instruction cache separate from said data cache for reading instructions; a distributor communicatively coupled to the plurality of processor cores and configured to distribute data to be processed to a corresponding data cache of at least one processor core of the plurality of processor cores and to distribute instructions associated with the data to a corresponding instruction cache of the at least one processor core for execution; The distributor: configured to receive processing results from a corresponding data cache of the at least one processor core, and the processing results are obtained by the at least one processor core processing the received processing target data based on the instruction, Processor.

2. Distributing the instructions to the at least one processor core comprises: broadcasting the instruction to the at least one processor core. The processor of claim 1 .

3. Distributing the processing target data to the at least one processor core includes: transmitting first data of the data to be processed to a first processor core for processing; transmitting second data, which is different from the first data, of the data to be processed to a second processor core for processing; The processor of claim 2 .

4. Distributing the processing target data to the at least one processor core includes: broadcasting the data to be processed to the at least one processor core; The processor of claim 1 .

5. Distributing the instructions to the at least one processor core comprises: transmitting a first instruction to a first processor core so that the first processor core processes the process target data based on the first instruction; transmitting a second instruction different from the first instruction to a second processor core, so that the second processor core processes the data to be processed based on the second instruction; The processor of claim 4 .

6. Distributing the processing target data to the at least one processor core includes: distributing third data of the data to be processed to a first processor core of the at least one processor core for processing; in response to receiving a first result obtained by processing the third data from the first processor core, distributing fourth data, which is different from the third data, from the data to be processed to the first processor core for processing; The processor of claim 1 .

7. The distributor: receiving a data set and an instruction set to be processed by said processor; configured to receive configuration information indicating at least an association between the data to be processed in the data set and the instructions in the instruction set; the distribution of the data to be processed and the instructions is arranged to depend at least in part on the association; The processor of claim 1 .

8. distributing, by a distributor of a processor, data to be processed to a corresponding data cache of at least one processor core among a plurality of processor cores of the processor, the distributor being communicatively coupled to the plurality of processor cores; Distributing instructions associated with the data to be processed to a corresponding instruction cache of the at least one processor core for execution; receiving a processing result from a corresponding data cache of the at least one processor core, the processing result being obtained by the at least one processor core processing the processing target data received based on the instruction, Data processing methods.

9. Distributing the instructions to the at least one processor core comprises: broadcasting the instruction to the at least one processor core.

9. The data processing method according to claim 8.

10. Distributing the processing target data to the at least one processor core includes: distributing first data of the data to be processed to a first processor core for processing; and distributing second data of the processing target data, the second data being different from the first data, to a second processor core for processing.

10. The data processing method according to claim 9.

11. Distributing the processing target data to the at least one processor core includes: broadcasting the data to be processed to the at least one processor core; 9. The data processing method according to claim 8.

12. Distributing the instructions to the at least one processor core comprises: transmitting a first instruction to a first processor core so that the first processor core processes the process target data based on the first instruction; transmitting a second instruction different from the first instruction to a second processor core, so that the second processor core processes the data to be processed based on the second instruction; The data processing method according to claim 11.

13. Distributing the processing target data to the at least one processor core includes: distributing third data of the data to be processed to a first processor core of the at least one processor core for processing; in response to receiving a first result obtained by processing the third data from the first processor core, distributing fourth data, which is different from the third data, from the data to be processed to the first processor core for processing; 9. The data processing method according to claim 8.

14. receiving a data set and an instruction set to be processed by the processor; receiving configuration information indicating at least an association between the data to be processed in the data set and the instructions in the instruction set; the distribution of the data to be processed and the instructions is at least partially dependent on the association; 9. The data processing method according to claim 8.

15. 8. A method for manufacturing a computer system comprising: Electronic devices.

16. A computer program is stored, and the computer program is executed by a processor to implement the method according to any one of claims 8 to 14. A computer-readable storage medium.

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