Motion Model Signaling

Abstract

A method for determining one or more candidate prediction modes is provided. [Solution] The method includes: deriving, by a processor, a first indicator by analyzing a bitstream, the first indicator specifying whether any affine model is a candidate motion model for an image block within a predetermined region; determining, by the processor, that the first indicator is set to 1; deriving, by the processor, based on the determination that the first index is set to 1, a second indicator by analyzing the bitstream, the second indicator specifying whether a six-parameter affine model is a candidate motion model for the image block; and determining, by the processor, one or more candidate prediction modes for the image block based on the first index and the second index.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional application of Japanese Patent Application No. 2021-502562, filed March 5, 2019, which claims priority to U.S. Provisional Patent Application No. 62 / 699,554, entitled "Affine Mode Signaling," filed July 17, 2018, by Futurewei Technologies, Inc., U.S. Provisional Patent Application No. 62 / 725,684, entitled "Affine Motion Signaling," filed August 31, 2018, by Futurewei Technologies, Inc., and U.S. Provisional Patent Application No. 62 / 732,343, entitled "Affine Mode Signaling," filed September 17, 2018, by Futurewei Technologies, Inc. All of the foregoing patent applications are incorporated herein by reference in their entireties. The disclosed embodiments relate generally to video coding and, more particularly, to motion model signaling. [Background technology]

[0002] Video uses a relatively large amount of data, and therefore, video transmission uses a relatively large amount of bandwidth. However, many networks operate at or near their bandwidth capacity. In addition, customers demand high video quality, requiring even more data usage. Therefore, it is desirable to both reduce the amount of data used by video and improve video quality. One solution is to compress the video during the encoding process and decompress the video during the decoding process. Summary of the Invention [Means for solving the problem]

[0003] A first aspect relates to a method for determining one or more candidate prediction modes, the method including: deriving, by a processor, a first indicator by analyzing a bitstream, the first indicator specifying whether any affine model is a candidate motion model for an image block within a predetermined region; determining, by the processor, to set the first indicator to 1; deriving, by the processor, a second indicator by analyzing the bitstream based on the determination that the first indicator is set to 1, the second indicator specifying whether a six-parameter affine model is a candidate motion model for the image block; and determining, by the processor, one or more candidate prediction modes for the image block based on the first indicator and the second indicator. The method provides more efficient coding of the affine model and coding of the translational motion model.

[0004] As such, in a first implementation form of the method according to the first aspect, before deriving the second indicator, the method further includes determining that the affine model is a candidate motion model, and the method further includes deriving the second indicator in response to determining that the affine model is a candidate motion model.

[0005] As such, in a second implementation form of the method according to the first aspect or any preceding implementation form of the first aspect, deriving the first indicator comprises analyzing an SPS of a sequence of the bitstream, and the predetermined region comprises the sequence, any slice in the sequence, or any CU in the sequence, and deriving the second indicator comprises analyzing the SPS.

[0006] In a third implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, the method further includes, in response to the affine model being a candidate motion model, deriving a sixth indicator by analyzing slice headers of slices in the sequence, the sixth indicator specifying whether any affine model is a candidate motion model for an image block in the slice.

[0007] In a fourth implementation form of the method according to the first aspect or any preceding implementation form of the first aspect as such, the method further includes, in response to the six-parameter affine model being a candidate motion model, deriving a seventh indicator by analyzing slice headers of slices in the sequence, the seventh indicator specifying whether the six-parameter affine model is a candidate prediction model for image blocks in the slice.

[0008] As such, in a fifth implementation form of the method according to the first aspect or any preceding implementation form of the first aspect, the method further includes deriving a first indicator by parsing a slice header of a slice of the bitstream, wherein the predetermined region includes the slice or any coding unit within the slice, further deriving the first indicator, and further deriving a second indicator by parsing the slice header.

[0009] In a sixth implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, the method further includes, in response to the affine model being a candidate motion model, deriving a third indicator by analyzing the bitstream, wherein the third indicator specifies whether the prediction mode of the image block is an affine merge mode.

[0010] In a seventh implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, in response to the affine model being the candidate motion model, the method further includes: deriving a fourth indicator by analyzing the bitstream; determining that the prediction mode of the image block is not affine inter mode in response to the fourth indicator being a first value; and determining that the prediction mode is affine inter mode in response to the fourth indicator being a second value, wherein the affine inter mode specifies that the affine model mode is a 6-parameter affine model mode or a 4-parameter affine model mode.

[0011] In an eighth implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, in response to the prediction mode being affine inter mode, the method further includes deriving a fifth indicator by analyzing the bitstream, and in response to the fifth indicator being a third value, determining that the prediction mode is a six-parameter affine model mode, and in response to the fifth indicator being a fourth value, determining that the prediction mode is a four-parameter affine model mode.

[0012] As such, in a ninth implementation form of the method according to the first aspect or any preceding implementation form of the first aspect, in response to the first value being 1, the second value being 0, the third value being 0, and the fourth value being 1, the method further includes: deriving a sum value by adding the value of the fourth index and the value of the fifth index; in response to the sum value being greater than 0, deriving a first set of MVD information by analyzing the bitstream; and in response to the sum value being greater than 1, deriving a second set of MVD information by analyzing the bitstream.

[0013] A second aspect relates to an apparatus for determining one or more candidate prediction modes, the apparatus comprising: a memory; and a processor coupled to the memory and configured to perform the first aspect as such or any preceding implementation of the first aspect.

[0014] A third aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the first aspect as such or any of the preceding implementations of the first aspect.

[0015] A fourth aspect relates to a method that includes determining a first value for an SPS affine inter flag that specifies whether an affine inter flag is present in coding unit level syntax, encoding the first value for the SPS affine inter flag into a bitstream, determining a second value for an SPS affine type flag that specifies whether an affine type flag is present in coding unit level syntax, and encoding the second value for the SPS affine type flag into the bitstream, which method provides more efficient coding of the affine model and coding of the translational motion model.

[0016] As such, in a first implementation of the method according to the fourth aspect, the SPS affine type flag is conditionally signaled based on the first value.

[0017] In such a second implementation form of the method according to the fourth aspect or any preceding implementation form of the fourth aspect, the method further includes determining a third value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, encoding the third value for the affine inter flag into the bitstream, determining a fourth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and encoding the fourth value for the affine type flag into the bitstream.

[0018] As such, in the third implementation of the method according to the fourth aspect or any preceding implementation of the fourth aspect, the affine inter flag is conditionally signaled based on the first value, and the affine type flag is conditionally signaled based on the second value.

[0019] A fifth aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the fourth aspect as such or any preceding implementation of the fourth aspect.

[0020] A sixth aspect relates to a computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the fourth aspect as such or any of the preceding implementations of the fourth aspect.

[0021] A seventh aspect relates to a method including receiving a bitstream including an SPS affine inter flag and an SPS affine type flag, determining whether the affine inter flag is present in a coding unit level syntax based on a first value of the SPS affine inter flag, and determining whether the affine type flag is present in a coding unit level syntax based on a second value of the SPS affine type flag, the method providing more efficient coding of an affine model and coding of a translational motion model.

[0022] As such, in a first implementation of the method according to the seventh aspect, the SPS affine type flag is conditionally signaled based on the first value.

[0023] As such, in a second implementation form of the method according to the seventh aspect or any preceding implementation form of the first aspect, the bitstream further includes an affine inter flag and an affine type flag, and the method further includes determining, based on a third value of the affine inter flag, whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and determining, based on a fourth value of the affine type flag, whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit.

[0024] As such, in the third implementation form of the method according to the seventh aspect or any preceding implementation form of the first aspect, the affine inter flag is conditionally signaled based on the first value, and the affine type flag is conditionally signaled based on the second value.

[0025] An eighth aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the seventh aspect as such or any preceding implementation of the seventh aspect.

[0026] A ninth aspect relates to a computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the seventh aspect as such or any of the preceding implementations of the seventh aspect.

[0027] A tenth aspect relates to a method including: determining a first value for a slice affine inter flag that specifies whether syntax elements of a current picture are constrained to use an affine inter mode in decoding the current picture; encoding the first value for the slice affine inter flag into a bitstream; determining a second value for a slice affine type flag that specifies whether syntax elements of the current picture are constrained to use a six-parameter affine mode in decoding the current picture; and encoding the second value for the slice affine type flag into a bitstream. The method provides more efficient coding of the affine model and coding of the translational motion model.

[0028] As such, in a first implementation of the method according to the tenth aspect, the slice affine type flag is conditionally signaled based on the first value.

[0029] In such a second implementation form of the method according to the tenth aspect or any preceding implementation form of the tenth aspect, the method further includes determining a third value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, encoding the third value for the affine inter flag into the bitstream, determining a fourth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and encoding the fourth value for the affine type flag into the bitstream.

[0030] As such, in the third implementation of the method according to the tenth aspect or any preceding implementation of the tenth aspect, the affine inter flag is conditionally signaled based on the first value, and the affine type flag is conditionally signaled based on the second value.

[0031] An eleventh aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the tenth aspect as such or any preceding implementation of the tenth aspect.

[0032] A twelfth aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the tenth aspect as such or any of the preceding implementations of the tenth aspect.

[0033] A thirteenth aspect relates to a method including receiving a bitstream including a slice affine inter flag and a slice affine type flag, determining whether syntax elements of a current picture are constrained to use an affine inter mode in decoding the current picture based on a first value of the slice affine inter flag, and determining whether syntax elements of the current picture are constrained to use a six-parameter affine mode in decoding the current picture based on a second value of the slice affine type flag, which method provides more efficient coding of the affine model and coding of the translational motion model.

[0034] As such, in a first implementation of the method according to the thirteenth aspect, the slice affine type flag is conditionally signaled based on the first value.

[0035] As such, in a second implementation form of the method according to the thirteenth aspect or any preceding implementation form of the thirteenth aspect, the bitstream further includes an affine inter flag and an affine type flag, and the method further includes determining, based on a third value of the affine inter flag, whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and determining, based on a fourth value of the affine type flag, whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit.

[0036] As such, in the third implementation form of the method according to the thirteenth aspect or any preceding implementation form of the thirteenth aspect, the affine inter flag is conditionally signaled based on the first value, and the affine type flag is conditionally signaled based on the second value.

[0037] A fourteenth aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the thirteenth aspect as such or any preceding implementation of the thirteenth aspect.

[0038] A fifteenth aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the thirteenth aspect as such or any of the preceding implementations of the thirteenth aspect.

[0039] A sixteenth aspect relates to a method including: determining a first value for an SPS Affine Inter flag that specifies whether a slice affine inter flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use an affine inter mode in decoding the video sequence; encoding the first value for the SPS Affine Inter flag into a bitstream; determining a second value for an SPS Affine Type flag that specifies whether a slice affine type flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use a six-parameter affine mode in decoding the video sequence; and encoding the second value for the SPS Affine Type flag into a bitstream. The method provides more efficient coding of the affine model and coding of the translational motion model.

[0040] As such, in a first implementation form of the method according to the sixteenth aspect, the SPS affine type flag is conditionally signaled based on the first value.

[0041] In such a second implementation form of the method according to the 16th aspect or any preceding implementation form of the 16th aspect, the method further includes determining a third value for a slice affine inter flag that specifies whether syntax elements of the current picture are constrained so that affine inter mode is used in decoding the current picture, encoding the third value for the slice affine inter flag into the bitstream, determining a fourth value for a slice affine type flag that specifies whether syntax elements of the current picture are constrained so that six-parameter affine mode is used in decoding the current picture, and encoding the second value for the slice affine type flag into the bitstream.

[0042] As such, in the third implementation form of the method according to the sixteenth aspect or any preceding implementation form of the sixteenth aspect, the slice affine inter flag is conditionally signaled based on the first value, and the slice affine type flag is conditionally signaled based on the second value.

[0043] In such a fourth implementation form of the method according to the sixteenth aspect or any preceding implementation form of the sixteenth aspect, the method further includes determining a fifth value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, encoding the fifth value for the affine inter flag into the bitstream, determining a sixth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and encoding the sixth value for the affine type flag into the bitstream.

[0044] As such, in the fifth implementation form of the method according to the sixteenth aspect or any preceding implementation form of the sixteenth aspect, the affine inter flag is conditionally signaled based on the third value, and the affine type flag is conditionally signaled based on the fourth value.

[0045] A seventeenth aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform any of the preceding implementations of the first aspect or the sixteenth aspect as such.

[0046] An eighteenth aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform any of the preceding implementations of the first aspect or the sixteenth aspect as such.

[0047] A nineteenth aspect relates to a method including receiving a bitstream including an SPS Affine Inter flag and an SPS Affine Type flag, determining, based on a first value of the SPS Affine Inter flag, whether a slice affine inter flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use an affine inter mode in decoding the video sequence, and determining, based on a second value of the SPS Affine Type flag, whether a slice affine type flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use a six-parameter affine mode in decoding the video sequence. The method provides more efficient coding of the affine model and coding of the translational motion model.

[0048] As such, in a first implementation form of the method according to the nineteenth aspect, the SPS affine type flag is conditionally signaled based on the first value.

[0049] In such a second implementation form of the method according to the 19th aspect or any preceding implementation form of the 19th aspect, the bitstream further includes a slice affine inter flag and a slice affine type flag, and the method further includes determining, based on a third value of the slice affine inter flag, whether syntax elements of the current picture are constrained so that affine inter mode is used in decoding the current picture, and determining, based on a fourth value of the slice affine type flag, whether syntax elements of the current picture are constrained so that 6-parameter affine mode is used in decoding the current picture.

[0050] As such, in a third implementation form of the method according to the 19th aspect or any preceding implementation form of the 19th aspect, the slice affine inter flag is conditionally signaled based on the first value, and the slice affine type flag is conditionally signaled based on the second value.

[0051] As such, in a fourth implementation form of the method according to the 19th aspect or any preceding implementation form of the 19th aspect, the bitstream further includes an affine inter flag and an affine type flag, and the method further includes determining, based on a fifth value of the affine inter flag, whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and determining, based on a sixth value of the affine type flag, whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit.

[0052] As such, in the fifth implementation form of the method according to the 19th aspect or any preceding implementation form of the 19th aspect, the affine inter flag is conditionally signaled based on the third value, and the affine type flag is conditionally signaled based on the fourth value.

[0053] A twentieth aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the nineteenth aspect as such or any preceding implementation of the nineteenth aspect.

[0054] A twenty-first aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the nineteenth aspect as such or any of the preceding implementations of the nineteenth aspect.

[0055] A twenty-second aspect relates to a method including: determining a first value for a motion model indicator variable that specifies a motion model to be used to generate predictive samples for a current coding unit, the motion model being one of a translational motion model, a four-parameter affine model, or a six-parameter affine model; determining a second value for an affine inter flag based on the first value; encoding the second value for the affine inter flag into a bitstream; determining a third value for an affine type flag based on the first value; and encoding the third value for the affine type flag into the bitstream. This method provides more efficient coding of the affine model and coding of the translational motion model.

[0056] A twenty-third aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the twenty-second aspect as such or any preceding implementation of the twenty-second aspect.

[0057] A twenty-fourth aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the twenty-second aspect as such or any of the preceding implementations of the twenty-second aspect.

[0058] A twenty-fifth aspect relates to a method including receiving a bitstream including an affine inter flag and an affine type flag, determining a third value of a motion model indicator variable based on a first value of the affine inter flag and a second value of the affine type flag, and determining whether the motion model is a translational motion model, a four-parameter affine model, or a six-parameter affine model based on the third value. The method provides more efficient coding of the affine model and coding of the translational motion model.

[0059] A 26th aspect relates to an apparatus comprising a memory and a processor coupled to the memory and configured to perform the 25th aspect as such or any preceding implementation of the 25th aspect.

[0060] A twenty-seventh aspect relates to a computer program product including computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes an apparatus to perform the twenty-fifth aspect as such or any of the preceding implementations of the twenty-fifth aspect.

[0061] Any of the above embodiments may be combined with any of the other embodiments described above to create new embodiments. These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

[0062] For a more complete understanding of the present disclosure, reference is now made to the following brief description taken in conjunction with the accompanying drawings and detailed description, in which like numerals represent like parts. [Brief explanation of the drawings]

[0063] [Figure 1] FIG. 1 is a schematic diagram of a coding system. [Figure 2A] FIG. 1 is a schematic diagram of the current block showing a four-parameter affine model. [Figure 2B] FIG. 1 is a schematic diagram of the current block showing a six-parameter affine model. [Figure 3] FIG. 1 is a schematic diagram of a video stream. [Figure 4A] FIG. 1 illustrates an SPS syntax according to an embodiment of the present disclosure. [Figure 4B] FIG. 10 illustrates an SPS syntax according to another embodiment of the present disclosure. [Figure 4C] FIG. 1 illustrates a coding unit syntax according to an embodiment of the present disclosure. [Figure 5A] FIG. 10 illustrates a slice segment header syntax according to an embodiment of the present disclosure. [Figure 5B] FIG. 10 illustrates a slice segment header syntax according to another embodiment of the present disclosure. [Figure 5C] FIG. 1 illustrates a coding unit syntax according to an embodiment of the present disclosure. [Figure 6A] FIG. 1 illustrates an SPS syntax according to an embodiment of the present disclosure. [Figure 6B] FIG. 10 illustrates an SPS syntax according to another embodiment of the present disclosure. [Figure 6C] FIG. 10 illustrates a slice segment header syntax according to an embodiment of the present disclosure. [Figure 6D] FIG. 1 illustrates a coding unit syntax according to an embodiment of the present disclosure. [Figure 7] FIG. 1 illustrates a coding unit syntax according to an embodiment of the present disclosure. [Figure 8] 1 is a flowchart illustrating a method for determining one or more candidate prediction modes according to an embodiment of the present disclosure. [Figure 9]1 is a flowchart illustrating a method for encoding a bitstream according to one embodiment of the present disclosure. [Figure 10] 1 is a flowchart illustrating a method for decoding a bitstream according to one embodiment of the present disclosure. [Figure 11] 1 is a flowchart illustrating a method for encoding a bitstream according to one embodiment of the present disclosure. [Figure 12] 1 is a flowchart illustrating a method for decoding a bitstream according to one embodiment of the present disclosure. [Figure 13] 1 is a flowchart illustrating a method for encoding a bitstream according to one embodiment of the present disclosure. [Figure 14] 1 is a flowchart illustrating a method for decoding a bitstream according to one embodiment of the present disclosure. [Figure 15] 1 is a flowchart illustrating a method for encoding a bitstream according to one embodiment of the present disclosure. [Figure 16] 1 is a flowchart illustrating a method for decoding a bitstream according to one embodiment of the present disclosure. [Figure 17] FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the present disclosure. [Figure 18] FIG. 2 is a schematic diagram of a coding means; DETAILED DESCRIPTION OF THE INVENTION

[0064] Initially, while exemplary implementations of one or more embodiments are presented below, it should be understood that the disclosed systems and / or methods may be implemented using any number of currently known or existing technologies. The present disclosure should in no way be limited to the exemplary implementations, drawings, and technologies illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with the full range of equivalents.

[0065] The following abbreviations apply: ASIC: Application Specific Integrated Circuit CPU: Central Processing Unit DSP: Digital Signal Processor EO: Electric-Optical FPGA: Field Programmable Gate Array Idc:Indicator MVD: Motion Vector Difference OE: Optical-electrical PPS: Picture Parameter Set RAM: Random Access Memory RBSP: Raw Byte Sequence Payload RF: Radio Frequency ROM: Read-Only Memory RX: Receiver unit SPS: Sequence Parameter Set SRAM: static RAM TCAM: Ternary Content Addressable Memory TX: Transmitter unit VPS: Video Parameter Set

[0066] 1 is a schematic diagram of a coding system 100. The coding system 100 includes a source device 110, a medium 150, and a destination device 160. The source device 110 and the destination device 160 may be a mobile phone, a tablet computer, a desktop computer, a notebook computer, or other devices. The medium 150 may be a local network, a wireless network, the Internet, or other communication medium.

[0067] Source device 110 includes video generator 120, encoder 130, and output interface 140. Video generator 120 is a camera or another device that generates video. Encoder 130 may be referred to as a codec. Encoder 130 encodes video and other data into a bitstream according to a set of rules. Output interface 140 is an antenna or another component that transmits the bitstream to destination device 160. Alternatively, video generator 120, encoder 130, and output interface 140 are a combination of devices.

[0068] Destination device 160 includes input interface 170, decoder 180, and display 190. Input interface 170 is an antenna or another component that receives the bitstream from source device 110. Decoder 180 may also be referred to as a codec. Decoder 180 decodes video and other data from the bitstream according to a set of rules. Encoding and decoding together are referred to as coding. Display 190 displays the video. Alternatively, input interface 170, decoder 180, and display 190 are a combination of devices.

[0069] The bitstream contains data defined at various levels, including slices and blocks. A slice is a spatially distinct region of a video frame that is coded separately from any other region within the video frame. A block is a rectangularly arranged group of pixels and is the smallest coding unit. Blocks within a slice may be coded in a dependent manner. Although video is described, video is a series of single frames, and the same concepts apply to single frames as well.

[0070] As objects move between frames, the blocks of those objects move in a corresponding manner. There are two main methods for representing that motion: intra-prediction and inter-prediction. Intra-prediction represents a current block in a current frame based on its relationship to a reference block in the current frame. Inter-prediction represents a current block in a current frame based on its relationship to a reference block in a reference frame. A motion vector describes that relationship. The process of determining these motion vectors is motion estimation, and the process of using these motion vectors in coding is motion compensation. A reference frame can be a previous frame or a forward frame. P slices use a previous frame for coding, while B slices use both a previous and forward frame for coding.

[0071] Translational inter prediction, or conventional inter prediction, is used when an object simply moves from one position to another. The translational motion model implements translational inter prediction. Affine inter prediction is used when an object changes shape between frames due to camera zoom, rotation, perspective motion, or other irregular motion. Various affine models implement affine inter prediction. The translational motion model and the affine model are types of motion models.

[0072] A prediction mode is a coding mode that codes a coding unit using either intra prediction or inter prediction. An intra mode is a coding mode that uses intra prediction, and an inter mode is a coding mode that uses inter prediction. An affine merge mode, or affine inter mode, is a type of merge mode that implements affine inter prediction using an affine model.

[0073] 2A is a schematic diagram of a current block 210 illustrating a four-parameter affine model. The current block 210 is located in the upper left corner and has a motion vector

number

number

number

number

number

[0074] 2B is a schematic diagram of a current block 220 illustrating a six-parameter affine model. The current block 220 comprises a zeroth control point at the top left corner corresponding to motion vector mv0, a first control point at the top right corner corresponding to motion vector mv1, and a second control point at the top left corner corresponding to motion vector mv2. mv0, mv1, and mv2 have x and y positions, and are therefore respectively

number

number

number

[0075] 2A-2B show an affine model that uses multiple motion vectors in the motion vector fields (1) and (2). However, the translational motion model uses a single motion vector. Therefore, the translational motion model is simply

number

[0076] 3 is a schematic diagram of a video bitstream 300. The video bitstream 300 includes a VPS 305, an SPS 310, a PPS 315, and at least four slices 320, 325, 330, and 335. Slice 320 includes a header 340 and data 345. Slices 325, 330, and 335 are similar to slice 320. Data 345 includes at least three blocks 350, 355, and 360. Although four slices 320-335 are shown, the video bitstream 300 may include any suitable number of slices. Although three blocks 350-360 are shown, the data 345 may include any suitable number of blocks. In addition, each remaining slice 325, 330, and 335 also includes a block. Thus, although video bitstream 300 contains many blocks, video bitstream 300 contains one SPS 310 and significantly fewer slice headers than blocks.

[0077] One approach is to always code two flags in each block 350-360. The first flag specifies whether the block 350-360 uses an affine model. The second flag specifies whether the affine model is a four-parameter affine model or a six-parameter affine model. However, always including the first and second flags in each block 350-360 requires excessive bits because there are many such blocks and not all blocks use the affine model. Therefore, it is desirable to code the affine model more efficiently. It is also desirable to code the translational motion model.

[0078] Disclosed herein are embodiments for motion model signaling. The motion models include a translational motion model, a four-parameter affine model, and a six-parameter affine model. The motion model signaling is at higher levels of the video bitstream, including the SPS and slice header. When higher-level signaling specifies that a motion model is not used, then lower-level signaling does not need to specify the motion model. By reducing the lower-level signaling, fewer bits are required in the video bitstream to signal or not signal the motion model. As a result, less bandwidth is required for communication of the video bitstream. While the SPS and slice header are described, the same concepts apply to other higher levels of the video bitstream. Although the translational motion model, the four-parameter affine model, and the six-parameter affine model are described, the same concepts apply to other motion models in particular and other context models in general.

[0079] 4A is a diagram illustrating an SPS syntax 410 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the SPS 310 using the SPS syntax 410. The SPS syntax 410 includes an SPS affine inter flag, Sps_affine_inter_flag, and an SPS affine type flag, Sps_affine_type_flag.

[0080] Sps_affine_inter_flag specifies whether the affine inter flag, affine_inter_flag, is present in the coding unit level syntax. Sps_affine_inter_flag equal to 0 specifies that affine_inter_flag is not present in the coding unit level syntax. Sps_affine_inter_flag equal to 1 specifies that affine_inter_flag is present in the coding unit level syntax.

[0081] Sps_affine_type_flag specifies whether the affine type flag, affine_type_flag, is present in the coding unit level syntax. Sps_affine_type_flag equal to 0 specifies that affine_inter_flag is not present in the coding unit level syntax. Sps_affine_type_flag equal to 1 specifies that affine_type_flag is present in the coding unit level syntax. Sps_affine_type_flag is conditionally signaled such that when Sps_affine_inter_flag is equal to 0, Sps_affine_type_flag is not signaled, and when Sps_affine_inter_flag is equal to 1, Sps_affine_type_flag is signaled.

[0082] 4B is a diagram illustrating an SPS syntax 420 according to another embodiment of the present disclosure. The SPS syntax 420 is similar to the SPS syntax 410 in FIG. 4A. However, unlike the SPS syntax 410, the Sps_affine_type_flag in the SPS syntax 420 is not conditionally signaled. Instead, the Sps_affine_type_flag is always signaled, even when the Sps_affine_inter_flag is equal to 0.

[0083] 4C is a diagram illustrating a coding unit syntax 430 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the blocks 350-360 using the coding unit syntax 430. The coding unit syntax 430 includes an affine inter flag, affine_inter_flag, and an affine type flag, affine_type_flag.

[0084] affine_inter_flag specifies, for the current coding unit, whether affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_inter_flag equal to 0 specifies, for the current coding unit, that affine model-based motion compensation is not used to generate predicted samples for the current coding unit when decoding P or B slices. affine_inter_flag equal to 1 specifies, for the current coding unit, that affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. The affine_inter_flag is conditionally signaled such that when Sps_affine_inter_flag in SPS syntax 410 or SPS syntax 420 is equal to 0, the affine_inter_flag is not signaled, and when Sps_affine_inter_flag in SPS syntax 410 or SPS syntax 420 is equal to 1, the affine_inter_flag is signaled.

[0085] affine_type_flag specifies, for the current coding unit, whether 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 0 specifies, for the current coding unit, that 4-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 1 specifies, for the current coding unit, that 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. The affine_type_flag is conditionally signaled such that the affine_type_flag is not signaled when Sps_affine_type_flag in the SPS syntax 410 or the SPS syntax 420 is equal to 0 or when the affine_inter_flag in the coding unit syntax 430 is equal to 0, and the affine_type_flag is signaled when the Sps_affine_inter_flag in the SPS syntax 410 or the SPS syntax 420 is equal to 1 and when the affine_inter_flag in the coding unit syntax 430 is equal to 1.

[0086] 5A illustrates a slice segment header syntax 510 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the header 340 using the slice segment header syntax 510. The slice segment header syntax 510 includes a slice affine inter flag, Slice_affine_inter_flag, and a slice affine type flag, Slice_affine_type_flag.

[0087] Slice_affine_inter_flag specifies whether the syntax elements of the current picture are constrained so that affine inter modes are used in decoding the current picture. Slice_affine_inter_flag equal to 0 specifies that the syntax elements of the current picture are constrained so that affine inter modes are not used in decoding the current picture. Slice_affine_inter_flag equal to 1 specifies that the syntax elements of the current picture are constrained so that affine inter modes are used in decoding the current picture.

[0088] Slice_affine_type_flag specifies whether the syntax elements of the current picture are constrained so that the 6-parameter affine mode is used in decoding the current picture. Slice_affine_type_flag equal to 0 specifies that the syntax elements of the current picture are constrained so that the 6-parameter affine mode is not used in decoding the current picture either. Slice_affine_type_flag equal to 1 specifies that the syntax elements of the current picture are constrained so that the 6-parameter affine mode is used in decoding the current picture. Slice_affine_type_flag is conditionally signaled such that when Slice_affine_inter_flag is equal to 0, Slice_affine_type_flag is not signaled, and when Slice_affine_inter_flag is equal to 1, Slice_affine_type_flag is signaled.

[0089] 5B illustrates a slice segment header syntax 520 according to another embodiment of the present disclosure. The slice segment header syntax 520 is similar to the slice segment header syntax 510 in FIG. 5A. However, unlike the slice segment header syntax 510, the Slice_affine_type_flag in the slice segment header syntax 520 is not conditionally signaled. Instead, the Slice_affine_type_flag is always signaled, even when the Slice_affine_inter_flag is equal to 0.

[0090] 5C is a diagram illustrating a coding unit syntax 530 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the blocks 350 to 360 using the coding unit syntax 530. The coding unit syntax 530 includes an affine inter flag, affine_inter_flag, and an affine type flag, affine_type_flag.

[0091] affine_inter_flag specifies, for the current coding unit, whether affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_inter_flag equal to 0 specifies, for the current coding unit, that affine model-based motion compensation is not used to generate predicted samples for the current coding unit when decoding P or B slices. affine_inter_flag equal to 1 specifies, for the current coding unit, that affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. The affine_inter_flag is conditionally signaled such that when Slice_affine_inter_flag in slice segment header syntax 510 or slice segment header syntax 520 is equal to 0, the affine_inter_flag is not signaled, and when Slice_affine_inter_flag in slice segment header syntax 510 or slice segment header syntax 520 is equal to 1, the affine_inter_flag is signaled.

[0092] affine_type_flag specifies, for the current coding unit, whether 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 0 specifies, for the current coding unit, that 4-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 1 specifies, for the current coding unit, that 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. The affine_type_flag is conditionally signaled such that the affine_type_flag is not signaled when Slice_affine_type_flag in slice segment header syntax 510 or slice segment header syntax 520 is equal to 0 or when affine_inter_flag in coding unit syntax 530 is equal to 0, and the affine_type_flag is signaled when Slice_affine_type_flag in slice segment header syntax 510 or slice segment header syntax 520 is equal to 1 and when affine_inter_flag in coding unit syntax 530 is equal to 1.

[0093] 6A-6D illustrate a semi-hybrid between FIGS. 4A-4C and 5A-5C. FIG. 6A illustrates an SPS syntax 610 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the SPS 310 using the SPS syntax 610. The SPS syntax 610 includes an SPS affine inter flag, Sps_affine_inter_flag, and an SPS affine type flag, Sps_affine_type_flag.

[0094] Sps_affine_inter_flag specifies the slice affine inter flag, whether Slice_affine_inter_flag is present in the slice segment header level syntax and whether the syntax elements of the video sequence are constrained to use affine inter mode in decoding the video sequence. Sps_affine_inter_flag equal to 0 specifies that Slice_affine_inter_flag is not present in the slice segment header level syntax and the syntax elements of the video sequence are constrained to not use affine inter mode in decoding the video sequence. Sps_affine_inter_flag equal to 1 specifies that Slice_affine_inter_flag is present in the slice segment header level syntax and the syntax elements of the video sequence are constrained to use affine inter mode in decoding the video sequence.

[0095] Sps_affine_type_flag specifies whether the slice affine type flag, Slice_affine_type_flag, is present in the slice segment header level syntax and whether the syntax elements of the video sequence are constrained to use the six-parameter affine mode when decoding the video sequence. Sps_affine_type_flag equal to 0 specifies that Slice_affine_type_flag is not present in the slice segment header level syntax and the syntax elements of the video sequence are constrained to not use the six-parameter affine mode when decoding the video sequence. Sps_affine_type_flag equal to 1 specifies that Slice_affine_type_flag is present in the slice segment header level syntax and the syntax elements of the video sequence are constrained to use the six-parameter affine mode when decoding the video sequence. Sps_affine_type_flag is conditionally signaled such that when Sps_affine_inter_flag is equal to 0, Sps_affine_type_flag is not signaled, and when Sps_affine_inter_flag is equal to 1, Sps_affine_type_flag is signaled.

[0096] 6B is a diagram illustrating an SPS syntax 620 according to another embodiment of the present disclosure. The SPS syntax 620 is similar to the SPS syntax 610 in FIG. 6A. However, unlike the SPS syntax 610, the Sps_affine_type_flag in the SPS syntax 620 is not conditionally signaled. Instead, the Sps_affine_type_flag is always signaled, even when the Sps_affine_inter_flag is equal to 0.

[0097] 6C illustrates a slice segment header syntax 630 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the header 340 using the slice segment header syntax 630. The slice segment header syntax 630 includes a slice affine inter flag, Slice_affine_inter_flag, and a slice affine type flag, Slice_affine_type_flag.

[0098] Slice_affine_inter_flag specifies whether the syntax elements of the current picture are constrained so that affine inter modes are used in decoding the current picture. Slice_affine_inter_flag equal to 0 specifies that the syntax elements of the current picture are constrained so that affine inter modes are not used in decoding the current picture. Slice_affine_inter_flag equal to 1 specifies that the syntax elements of the current picture are constrained so that affine inter modes are used in decoding the current picture. Slice_affine_inter_flag is conditionally signaled such that Slice_affine_inter_flag is not signaled when Sps_affine_inter_flag in SPS syntax 610 or SPS syntax 620 is equal to 0, and Slice_affine_inter_flag is signaled when SPS syntax 610 or SPS syntax 620 is equal to 1.

[0099] Slice_affine_type_flag specifies whether the syntax elements of the current picture are constrained so that the 6-parameter affine mode is used in decoding the current picture. Slice_affine_type_flag equal to 0 specifies that the syntax elements of the current picture are constrained so that the 6-parameter affine mode is not used in decoding the current picture. Slice_affine_type_flag equal to 1 specifies that the syntax elements of the current picture are constrained so that the 6-parameter affine mode is used in decoding the current picture. Slice_affine_type_flag is conditionally signaled such that when Sps_affine_type_flag in SPS syntax 610 or SPS syntax 620 is equal to 0, Slice_affine_type_flag is not signaled, and when Sps_affine_type_flag in SPS syntax 610 or SPS syntax 620 is equal to 1, Slice_affine_type_flag is signaled.

[0100] 6D is a diagram illustrating a coding unit syntax 640 according to one embodiment of the present disclosure. The encoder 130 encodes and the decoder 180 decodes the blocks 350-360 using the coding unit syntax 640. The coding unit syntax 640 includes an affine inter flag, affine_inter_flag, and an affine type flag, affine_type_flag.

[0101] affine_inter_flag specifies, for the current coding unit, whether affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_inter_flag equal to 0 specifies that affine model-based motion compensation is not used to generate predicted samples for the current coding unit when decoding P or B slices for the current coding unit. affine_inter_flag equal to 1 specifies that affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices for the current coding unit. affine_inter_flag is conditionally signaled, such that affine_inter_flag is not signaled when Slice_affine_inter_flag in the slice segment header syntax 630 is equal to 0, and affine_inter_flag is signaled when Slice_affine_inter_flag in the slice segment header syntax 630 is equal to 1.

[0102] affine_type_flag specifies, for the current coding unit, whether 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 0 specifies, for the current coding unit, that 4-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. affine_type_flag equal to 1 specifies, for the current coding unit, that 6-parameter affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding P or B slices. The affine_type_flag is conditionally signaled such that the affine_type_flag is not signaled when Slice_affine_type_flag in the slice segment header syntax 630 is equal to 0 or the affine_inter_flag in the coding unit syntax 640 is equal to 0, and the affine_type_flag is signaled when Slice_affine_type_flag in the slice segment header syntax 630 is equal to 1 and when the affine_inter_flag in the coding unit syntax 640 is equal to 1.

[0103] 7 illustrates a coding unit syntax 700 according to one embodiment of the present disclosure. Encoder 130 encodes and decoder 180 decodes blocks 350-360 using coding unit syntax 700. Coding unit syntax 700 includes a motion model indicator variable, motion_model_indicator[x0][y0], and an MVD coding instruction, mvd_coding(x0,y0,refList,cpIdx).

[0104] motion_model_indicator[x0][y0] specifies the motion model used to generate the predicted samples for the current coding unit. Syntax 700 sets motion_model_indicator[x0][y0] equal to the sum of the affine inter flag, affine_inter_flag, and the affine type flag, affine_type_flag. affine_inter_flag and affine_type_flag may come from coding unit syntax 430, 530, 640, or elsewhere. As shown in Table 1, motion_model_indicator[x0][y0] has a value of 0, 1, or 2. A value of 0 specifies the translational motion model, a value of 1 specifies the four-parameter affine mode, and a value of 2 specifies the six-parameter affine model. [Table 1] Alternatively, the values ​​for motion_model_indicator[x0][y0] specify the translational motion model, the four-parameter affine model, and the six-parameter affine model in another suitable manner.

[0105] mvd_coding(x0, y0, refList, cpIdx) specifies how to code the MVD for the current coding unit. The MVD is the difference between a predicted motion vector and a current motion vector. Therefore, the encoder 130 encodes, and the decoder 180 decodes, the MVD instead of a complete motion vector field such as motion vector fields (1) and (2). x0 and y0 specify the location of the current coding unit. refList specifies the reference picture list List0 or List1. The availability of List0 and List1 allows bi-prediction with a first reference block in List0 and a second reference block in List1. cpIdx specifies a control point index indicating a control point, for example, one of the control points in FIG. 2A or 2B. In coding unit syntax 700, mvd_coding(x0,y0,refList,cpIdx) takes the form mvd_coding(x0,y0,0,1) indicating an MVD coding instruction for List0 and control point 1, mvd_coding(x0,y0,0,2) indicating an MVD coding instruction for List0 and control point 2, mvd_coding(x0,y0,1,1) indicating an MVD coding instruction for List1 and control point 1, and mvd_coding(x0,y0,1,2) indicating an MVD coding instruction for List1 and control point 2.

[0106] 8 is a flowchart illustrating a method 800 for determining one or more candidate prediction modes according to one embodiment of the present disclosure. The encoder 130 or the decoder 180 performs the method 800. The encoder 130 or the decoder 180 may reside in a processor, as described below. In step 810, a first indicator is derived by analyzing the bitstream. The first indicator specifies whether any affine model is a candidate motion model for image blocks within a predetermined region. For example, the first indicator may be Sps_affine_inter_flag in the SPS syntax 410, 420, 610, or 620, affine_inter_flag in the coding unit syntax 430, 530, 640, or 700, or Slice_affine_inter_flag in the slice segment header syntax 510, 520, or 630. In step 820, the presence of the first indicator is determined. For example, Sps_affine_inter_flag in SPS syntax 410, 420, 610, or 620, affine_inter_flag in coding unit syntax 430, 530, 640, or 700, or Slice_affine_inter_flag in slice segment header syntax 510, 520, or 630 is set to 1. In step 830, in response to determining the presence of the first indicator, a second indicator is derived by parsing the bitstream. The second indicator specifies whether the six-parameter affine model is a candidate motion model for the image block. For example, the second indicator is Sps_affine_type_flag in the SPS syntax 410, 420, 610, or 620, affine_type_flag in the coding unit syntax 430, 530, 640, or 700, or Slice_affine_type_flag in the slice segment header syntax 510, 520, or 630.Finally, in step 840, one or more candidate motion models are determined for the image block based on the first indicator and the second indicator. For example, the encoder 130 or the decoder 180 determines a translational motion model, a four-parameter affine model, or a six-parameter affine model. The method 800 may include additional steps such as:

[0107] Prior to deriving the second indicator, the method 800 further includes determining that the affine model is a candidate motion model. The method 800 further includes deriving the second indicator in response to determining that the affine model is a candidate motion model.

[0108] In method 800, deriving the first indicator includes analyzing an SPS of a sequence of bitstreams. The predetermined region includes the sequence, any slice in the sequence, or any coding unit in the sequence. Deriving the second indicator includes analyzing the SPS. Optionally, method 800 further includes, in response to the affine model being a candidate motion model, deriving a sixth indicator by analyzing slice headers of slices in the sequence. The sixth indicator specifies whether any affine model is a candidate motion model for image blocks in the slice. Optionally, method 800 further includes, in response to the six-parameter affine model being a candidate motion model, deriving a seventh indicator by analyzing slice headers of slices in the sequence. The seventh indicator specifies whether the six-parameter affine model is a candidate prediction model for image blocks in the slice.

[0109] The method 800 further includes deriving the first indicator by parsing a slice header of a slice of the bitstream. The predetermined region includes the slice or any coding unit within the slice. The method 800 further includes deriving the second indicator by parsing the slice header.

[0110] The method 800 further includes deriving a third indicator by analyzing the bitstream in response to the affine model being the candidate motion model, the third indicator specifying whether a prediction mode of the image block is an affine merge mode.

[0111] In response to the affine model being the candidate motion model, the method 800 further includes: deriving a fourth indicator by analyzing the bitstream; determining that the prediction mode of the image block is not an affine inter mode in response to the fourth indicator being a first value; and determining that the prediction mode is an affine inter mode in response to the fourth indicator being a second value. The affine inter mode is a six-parameter affine model mode or a four-parameter affine model mode. In response to the prediction mode being an affine inter mode, the method 800 further includes: deriving a fifth indicator by analyzing the bitstream; determining that the prediction mode is a six-parameter affine model mode in response to the fifth indicator being a third value; and determining that the prediction mode is a four-parameter affine model mode in response to the fifth indicator being a fourth value. In response to the first value being 1, the second value being 0, the third value being 0, and the fourth value being 1, the method further includes adding the values ​​of the fourth index and the fifth index to derive a sum value; in response to the sum value being greater than 0, deriving a first set of MVD information by parsing the bitstream; and in response to the sum value being greater than 1, deriving a second set of MVD information by parsing the bitstream.

[0112] 9 is a flowchart illustrating a method 900 for encoding a bitstream according to one embodiment of the present disclosure. Encoder 130 performs method 900. In step 910, a first value for an SPS affine inter flag is determined, which specifies whether an affine inter flag is present in the coding unit level syntax. For example, the SPS affine inter flag is Sps_affine_inter_flag in SPS syntax 410 or 420. In step 920, the first value for the SPS affine inter flag is encoded into the bitstream. In step 930, a second value for an SPS affine type flag is determined, which specifies whether an affine type flag is present in the coding unit level syntax. For example, the SPS affine type flag is Sps_affine_type_flag in SPS syntax 410 or 420. Finally, in step 940, the second value for the SPS affine type flag is encoded into the bitstream.

[0113] 10 is a flowchart illustrating a method 1000 for decoding a bitstream according to one embodiment of the present disclosure. Decoder 180 performs method 1000. At step 1010, a bitstream including an SPS affine inter flag and an SPS affine type flag is received. For example, the SPS affine inter flag is Sps_affine_inter_flag in SPS syntax 410 or 420, and the SPS affine type flag is Sps_affine_type_flag in SPS syntax 410 or 420. At step 1020, it is determined whether an affine inter flag is present in the coding unit level syntax based on a first value of the SPS affine inter flag. Finally, at step 1030, it is determined whether an affine type flag is present in the coding unit level syntax based on a second value of the SPS affine type flag.

[0114] 11 is a flowchart illustrating a method 1100 for encoding a bitstream according to one embodiment of the present disclosure. Encoder 130 performs method 1100. In step 1110, a first value for a slice affine inter flag is determined, which specifies whether syntax elements of the current picture are constrained so that affine inter mode is used in decoding the current picture. For example, the slice affine inter flag is Slice_affine_inter_flag in slice segment header syntax 510 or 520. In step 1120, the first value for the slice affine inter flag is encoded into the bitstream. In step 1130, a second value for a slice affine type flag is determined, which specifies whether syntax elements of the current picture are constrained so that 6-parameter affine mode is used in decoding the current picture. For example, the slice affine type flag is Slice_affine_type_flag in slice segment header syntax 510 or 520. Finally, in step 1140, the second value for the slice affine type flag is encoded into the bitstream.

[0115] 12 is a flowchart illustrating a method 1200 for decoding a bitstream according to one embodiment of the present disclosure. The decoder 180 executes the method 1200. At step 1210, a bitstream including a slice affine inter flag and a slice affine type flag is received. For example, the slice affine inter flag is Slice_affine_inter_flag in the slice segment header syntax 510 or 520, and the slice affine type flag is Slice_affine_type_flag in the slice segment header syntax 510 or 520. At step 1220, it is determined whether the syntax elements of the current picture are constrained to use the affine inter mode in decoding the current picture based on a first value of the slice affine inter flag. Finally, at step 1230, it is determined whether the syntax elements of the current picture are constrained to use the six-parameter affine mode in decoding the current picture based on a second value of the slice affine type flag.

[0116] 13 is a flowchart illustrating a method 1300 for encoding a bitstream according to one embodiment of the present disclosure. The encoder 130 executes the method 1300. In step 1310, a first value for an SPS affine inter flag is determined, which specifies whether a slice affine inter flag is present in the slice segment header level syntax and whether syntax elements of the video sequence are constrained so that the affine inter mode is used in decoding the video sequence. For example, the SPS affine inter flag is Sps_affine_inter_flag in the SPS syntax 610 or 620. In step 1320, the first value for the SPS affine inter flag is encoded into the bitstream. In step 1330, a second value for the SPS affine type flag is determined, which specifies whether the slice affine type flag is present in the slice segment header level syntax and whether the syntax elements of the video sequence are constrained so that the six-parameter affine mode is used in decoding the video sequence, for example, the SPS affine type flag is Sps_affine_type_flag in SPS syntax 610 or 620. Finally, in step 1340, the second value for the SPS affine type flag is encoded into the bitstream.

[0117] 14 is a flowchart illustrating a method 1400 for decoding a bitstream according to one embodiment of the present disclosure. The decoder 180 executes the method 1400. At step 1410, a bitstream including an SPS affine inter flag and an SPS affine type flag is received. For example, the SPS affine inter flag is Sps_affine_inter_flag in the SPS syntax 610 or 620, and the SPS affine type flag is Sps_affine_type_flag in the SPS syntax 610 or 620. At step 1420, based on a first value of the SPS affine inter flag, it is determined whether a slice affine inter flag is present in the slice segment header level syntax and whether syntax elements of the video sequence are constrained to use the affine inter mode in decoding the video sequence. Finally, in step 1430, based on the second value of the SPS affine type flag, it is determined whether a slice affine type flag is present in the slice segment header level syntax and whether syntax elements of the video sequence are constrained so that the six-parameter affine mode is used in decoding the video sequence.

[0118] FIG. 15 is a flowchart illustrating a method 1500 for encoding a bitstream according to one embodiment of the present disclosure. Encoder 130 performs method 1500. In step 1510, a first value for a motion model indicator variable specifying a motion model to be used to generate prediction samples for the current coding unit is determined. The motion model is one of a translational motion model, a four-parameter affine model, or a six-parameter affine model. For example, the motion model indicator variable is motion_model_indicator[x0][y0] in coding unit syntax 700. In step 1520, a second value for an affine inter flag is determined based on the first value. For example, the affine inter flag is affine_inter_flag in coding unit syntax 700. In step 1530, the second value for the affine inter flag is encoded into the bitstream. In step 1540, a third value for an affine type flag is determined based on the first value. For example, the affine type flag is affine_type_flag in coding unit syntax 700. Finally, in step 1550, the third value for the affine type flag is encoded into the bitstream.

[0119] FIG. 16 is a flowchart illustrating a method 1600 for decoding a bitstream according to one embodiment of the present disclosure. The decoder 180 performs the method 1600. At step 1610, a bitstream including an affine inter flag and an affine type flag is received. For example, the affine inter flag is affine_inter_flag in the coding unit syntax 700, and the affine type flag is affine_type_flag in the coding unit syntax 700. At step 1620, a third value of a motion model indicator variable is determined based on the first value of the affine inter flag and the second value of the affine type flag. For example, the motion model indicator variable is motion_model_indicator[x0][y0] in the coding unit syntax 700. Finally, at step 1630, it is determined whether the motion model is a translational motion model, a four-parameter affine model, or a six-parameter affine model based on the third value.

[0120] 17 is a schematic diagram of an apparatus 1700 according to an embodiment of the present disclosure. The apparatus 1700 may implement the disclosed embodiments. The apparatus 1700 includes an input port 1710 and an RX 1720 for receiving data, a processor, logic unit, baseband unit, or CPU 1730 for processing the data, a TX 1740 and an output port 1750 for transmitting data, and a memory 1760 for storing data. The apparatus 1700 may also include optical, electrical, or RF components coupled to the input port 1710, the RX 1720, the TX 1740, and the output port 1750 to provide input or output of optical, electrical, or RF signals.

[0121] The processor 1730 is any combination of hardware, middleware, firmware, or software. The processor 1730 includes any combination of one or more CPU chips, cores, FPGAs, ASICs, or DSPs. The processor 1730 communicates with an input port 1710, an RX 1720, a TX 1740, an output port 1750, and a memory 1760. The processor 1730 includes a motion model signaling component 1770 that implements the disclosed embodiments. Thus, including the motion model signaling component 1770 provides substantial improvements to the functionality of the device 1700 and causes the device 1700 to transition to another state. Alternatively, the memory 1760 stores the motion model signaling component 1770 as instructions, and the processor 1730 executes those instructions.

[0122] Memory 1760 includes any combination of disks, tape drives, or solid state drives. Device 1700 may use memory 1760 as an overflow data storage device to store programs when device 1700 selects them to execute, and to store instructions and data that device 1700 reads when executing those programs. Memory 1760 may be volatile or non-volatile and may be any combination of ROM, RAM, TCAM, or SRAM.

[0123] 18 is a schematic diagram of a coding means 1800. The coding means 1800 is implemented in a video coding device 1802 (e.g., encoder 130 or decoder 180). The video coding device 1802 includes a receiving means 1801. The receiving means 1801 is configured to receive pictures for encoding or a bitstream for decoding. The video coding device 1802 includes a transmitting means 1807 coupled to the receiving means 1801. The transmitting means 1807 is configured to transmit the bitstream to a decoder or transmit decoded images to a display means (e.g., display 190).

[0124] The video coding device 1802 includes a storage means 1803. The storage means 1803 is coupled to at least one of the receiving means 1801 or the transmitting means 1807. The storage means 1803 is configured to store instructions. The video coding device 1802 also includes a processing means 1805. The processing means 1805 is coupled to the storage means 1803. The processing means 1805 is configured to execute instructions stored in the storage means 1803 in order to perform the disclosed embodiments.

[0125] The apparatus comprises a memory element; and a processor element coupled to the memory element and configured to execute a method of determining one or more candidate prediction modes; deriving a first indicator by analyzing a bitstream, the first indicator specifying whether any affine model is a candidate motion model for an image block within a predetermined region; deriving a second indicator by analyzing the bitstream, the second indicator specifying whether a six-parameter affine model is a candidate motion model for the image block; and determining one or more candidate prediction modes for the image block based on the first indicator and the second indicator.

[0126] The present invention may refer to one or more of the following embodiments:

[0127] 1. A method for determining one or more candidate prediction modes, the method comprising: deriving, by a processor, a first indicator by analyzing a bitstream, the first indicator specifying whether any affine model is a candidate motion model for an image block within a predetermined region; determining, by the processor, the first indicator being set to 1; deriving, by the processor, a second indicator by analyzing the bitstream based on the determination that the first indicator is set to 1, the second indicator specifying whether a six-parameter affine model is a candidate motion model for the image block; and determining, by the processor, one or more candidate prediction modes for the image block based on the first indicator and the second indicator. 2. The method of embodiment 1, wherein prior to deriving the second indicator, the method further includes determining that an affine model is a candidate motion model, and the method further includes deriving the second indicator in response to determining that the affine model is the candidate motion model. 3. The method of any one of embodiments 1 to 2, wherein deriving the first indicator comprises analyzing an SPS of the sequence of bitstreams, wherein the predetermined region comprises the sequence, any slice in the sequence, or any CU in the sequence, and deriving the second indicator comprises analyzing the SPS. 4. The method of any one of embodiments 1 to 3, further comprising, in response to an affine model being a candidate motion model, deriving a sixth indicator by analyzing slice headers of slices in the sequence, wherein the sixth indicator specifies whether any affine model is a candidate motion model for image blocks in the slice. 5. The method of any one of embodiments 1 to 4, further comprising, in response to a six-parameter affine model being a candidate motion model, deriving a seventh indicator by analyzing slice headers of slices in the sequence, wherein the seventh indicator specifies whether the six-parameter affine model is a candidate prediction model for image blocks in the slice.6. The method of any one of embodiments 1 to 5, further comprising: deriving a first indicator by analyzing a slice header of a slice of the bitstream, wherein the predetermined region includes the slice or any coding unit within the slice; and further comprising: deriving a second indicator by analyzing the slice header. 7. The method of any one of embodiments 1 to 6, further comprising: deriving a third indicator by analyzing the bitstream in response to the affine model being the candidate motion model, wherein the third indicator specifies whether a prediction mode of the image block is an affine merge mode. 8. The method of any one of embodiments 1 to 7, wherein in response to the affine model being the candidate motion model, the method further comprises: deriving a fourth indicator by analyzing the bitstream; determining that the prediction mode of the image block is not an affine inter mode in response to the fourth indicator being a first value; and determining that the prediction mode is an affine inter mode in response to the fourth indicator being a second value, wherein the affine inter mode specifies a six-parameter affine model mode or a four-parameter affine model mode. 9. The method of any one of embodiments 1 to 9, wherein in response to the prediction mode being an affine inter mode, the method further comprises: deriving a fifth indicator by analyzing the bitstream; determining that the prediction mode is a six-parameter affine model mode in response to the fifth indicator being a third value; and determining that the prediction mode is a four-parameter affine model mode in response to the fifth indicator being a fourth value.10. The method of any one of embodiments 1-9, wherein in response to the first value being 1, the second value being 0, the third value being 0, and the fourth value being 1, the method further comprises: deriving a sum value by adding the value of the fourth index and the value of the fifth index; in response to the sum value being greater than 0, deriving a first set of MVD information by analyzing the bitstream; and in response to the sum value being greater than 1, deriving a second set of MVD information by analyzing the bitstream. 11. An apparatus for determining one or more candidate prediction modes, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 1-10. 12. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by a processor, causes the apparatus to perform any one of embodiments 1-10.

[0128] 13. A method comprising: determining a first value for an SPS affine inter flag that specifies whether an affine inter flag is present in coding unit level syntax, encoding the first value for the SPS affine inter flag into a bitstream, determining a second value for an SPS affine type flag that specifies whether an affine type flag is present in coding unit level syntax, and encoding the second value for the SPS affine type flag into the bitstream. 14. The method of embodiment 13, wherein the SPS affine type flag is conditionally signaled based on the first value. 15. The method of any one of embodiments 13 to 14, further comprising: determining a third value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the prediction samples of the current coding unit, encoding the third value for the affine inter flag into the bitstream, determining a fourth value for the affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the prediction samples of the current coding unit, and encoding the fourth value for the affine type flag into the bitstream. 16. The method of any one of embodiments 13 to 15, wherein the affine inter flag is conditionally signaled based on a first value and the affine type flag is conditionally signaled based on a second value. 17. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 13 to 16. 18. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 13 to 16.

[0129] 19. A method comprising receiving a bitstream including an SPS Affine Inter flag and an SPS Affine Type flag, and determining whether the Affine Inter flag is present in coding unit level syntax based on a first value of the SPS Affine Inter flag and determining whether the Affine Type flag is present in coding unit level syntax based on a second value of the SPS Affine Type flag. 20. The method of embodiment 19, wherein the SPS Affine Type flag is conditionally signaled based on the first value. 21. The method of any one of embodiments 19 to 20, wherein the bitstream further includes an Affine Inter flag and an Affine Type flag, and further comprising determining whether affine model-based motion compensation is used to generate the prediction samples of the current coding unit based on a third value of the Affine Inter flag and determining whether six-parameter affine model-based motion compensation is used to generate the prediction samples of the current coding unit based on a fourth value of the Affine Type flag. 22. The method of any one of embodiments 19 to 21, wherein the affine inter flag is conditionally signaled based on a first value and the affine type flag is conditionally signaled based on a second value. 23. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 19 to 22. 24. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 19 to 22.

[0130] 25. The method, further comprising: determining a first value for a slice affine inter flag that specifies whether syntax elements of the current picture are constrained so that affine inter mode is used in decoding the current picture; encoding the first value for the slice affine inter flag into a bitstream; determining a second value for a slice affine type flag that specifies whether syntax elements of the current picture are constrained so that six-parameter affine mode is used in decoding the current picture; and encoding the second value for the slice affine type flag into a bitstream. 26. The method of embodiment 24, wherein the slice affine type flag is conditionally signaled based on the first value. 27. The method of any one of embodiments 25-26, further comprising: determining a third value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit; encoding the third value for the affine inter flag into a bitstream; determining a fourth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit; and encoding the fourth value for the affine type flag into the bitstream. 28. The method of any one of embodiments 25-27, wherein the affine inter flag is conditionally signaled based on the first value and the affine type flag is conditionally signaled based on the second value. 29. An apparatus comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 25-28. 30. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform any one of embodiments 25-28.

[0131] 31. A method comprising receiving a bitstream including a slice affine inter flag and a slice affine type flag; and determining, based on a first value of the slice affine inter flag, whether syntax elements of the current picture are constrained to use affine inter mode in decoding the current picture; and determining, based on a second value of the slice affine type flag, whether syntax elements of the current picture are constrained to use 6-parameter affine mode in decoding the current picture. 32. The method of embodiment 30, in which the slice affine type flag is conditionally signaled based on the first value. 33. The method of any one of embodiments 31 to 32, in which the bitstream further includes an affine inter flag and an affine type flag, and further comprising determining, based on a third value of the affine inter flag, whether affine model-based motion compensation is used to generate prediction samples for the current coding unit, and determining, based on a fourth value of the affine type flag, whether 6-parameter affine model-based motion compensation is used to generate prediction samples for the current coding unit. 34. The method of any one of embodiments 31 to 33, wherein the affine inter flag is conditionally signaled based on a first value and the affine type flag is conditionally signaled based on a second value. 35. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 31 to 34. 36. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 31 to 34.

[0132] 37. A method comprising: determining a first value for an SPS Affine Inter flag that specifies whether a slice affine inter flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use affine inter mode in decoding the video sequence; encoding the first value for the SPS Affine Inter flag into a bitstream; determining a second value for an SPS Affine Type flag that specifies whether a slice affine type flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use six-parameter affine mode in decoding the video sequence; and encoding the second value for the SPS Affine Type flag into the bitstream. 38. The method of embodiment 37, in which the SPS Affine Type flag is conditionally signaled based on the first value. 39. The method of any one of embodiments 37-38, further comprising: determining a third value for a slice affine inter flag that specifies whether syntax elements of the current picture are constrained to use affine inter mode in decoding the current picture; encoding the third value for the slice affine inter flag into the bitstream; determining a fourth value for a slice affine type flag that specifies whether syntax elements of the current picture are constrained to use six-parameter affine mode in decoding the current picture; and encoding the second value for the slice affine type flag into the bitstream. 40. The method of any one of embodiments 37-39, wherein the slice affine inter flag is conditionally signaled based on the first value and the slice affine type flag is conditionally signaled based on the second value.41. The method of any one of embodiments 37-40, further comprising: determining a fifth value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit; encoding the fifth value for the affine inter flag into a bitstream; determining a sixth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit; and encoding the sixth value for the affine type flag into the bitstream. 42. The method of any one of embodiments 37-41, wherein the affine inter flag is conditionally signaled based on the third value and the affine type flag is conditionally signaled based on the fourth value. 43. An apparatus comprising: a memory; and a processor coupled to the memory, configured to perform any one of embodiments 37-42. 44. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform any one of embodiments 37-42.

[0133] 45. A method comprising receiving a bitstream including an SPS Affine Inter flag and an SPS Affine Type flag; determining, based on a first value of the SPS Affine Inter flag, whether a Slice Affine Inter flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use affine inter mode in decoding the video sequence; and determining, based on a second value of the SPS Affine Type flag, whether a Slice Affine Type flag is present in slice segment header level syntax and whether syntax elements of the video sequence are constrained to use 6-parameter affine mode in decoding the video sequence. 46. The method of embodiment 44, in which the SPS Affine Type flag is conditionally signaled based on the first value. 47. The method of any one of embodiments 45-46, wherein the bitstream further includes a slice affine inter flag and a slice affine type flag, and the method further includes determining, based on a third value of the slice affine inter flag, whether syntax elements of the current picture are constrained to use an affine inter mode in decoding the current picture, and determining, based on a fourth value of the slice affine type flag, whether syntax elements of the current picture are constrained to use a six-parameter affine mode in decoding the current picture. 48. The method of any one of embodiments 45-47, wherein the slice affine inter flag is conditionally signaled based on the first value and the slice affine type flag is conditionally signaled based on the second value.49. The method of any one of embodiments 45-48, wherein the bitstream further includes an affine inter flag and an affine type flag, and wherein the method further includes determining, based on a fifth value of the affine inter flag, whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit, and determining, based on a sixth value of the affine type flag, whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit. 50. The method of any one of embodiments 45-49, wherein the affine inter flag is conditionally signaled based on a third value, and the affine type flag is conditionally signaled based on a fourth value. 51. An apparatus comprising: a memory; and a processor coupled to the memory, configured to perform any one of embodiments 45-50. 52. A computer program product comprising computer-executable instructions stored on a non-transitory medium, which, when executed by the processor, causes the apparatus to perform any one of embodiments 45-50.

[0134] 53. A method comprising: determining a first value for a motion model indicator variable that specifies a motion model to be used to generate predicted samples for a current coding unit, wherein the motion model is one of a translational motion model, a four-parameter affine model, or a six-parameter affine model; determining a second value for an affine inter flag based on the first value; encoding the second value for the affine inter flag into a bitstream; determining a third value for an affine type flag based on the first value; and encoding the third value for the affine type flag into the bitstream. 54. An apparatus comprising: a memory; and a processor coupled to the memory and configured to perform embodiment 53. 55. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform embodiment 53.

[0135] 56. A method comprising: receiving a bitstream including an affine inter flag and an affine type flag; determining a third value of a motion model indicator variable based on a first value of the affine inter flag and a second value of the affine type flag; and determining whether the motion model is a translational motion model, a four-parameter affine model, or a six-parameter affine model based on the third value. 57. An apparatus comprising: a memory; and a processor coupled to the memory and configured to perform embodiment 56. 58. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform embodiment 56.

[0136] 1. A method for determining one or more candidate prediction modes, the method comprising: deriving, by a processor, a first indicator by analyzing a bitstream, the first indicator specifying whether any affine model is allowed to be a candidate motion model for an image block within a predetermined region; deriving, by the processor, a second indicator by analyzing the bitstream when the first indicator is equal to a first value indicating that an affine model is allowed to be a candidate motion model, the second indicator specifying whether a six-parameter affine model is allowed to be a candidate motion model for the image block; and determining, by the processor, one or more candidate prediction modes for the image block based on the first indicator and the second indicator. 2. The method of any one of embodiments 1, wherein deriving the first indicator includes analyzing an SPS of a sequence of the bitstream, the predetermined region including the sequence, any slice within the sequence, or any CU within the sequence, and deriving the second indicator includes analyzing the SPS to derive the second indicator. 3. The method of any one of embodiments 1 to 2, further comprising, in response to an affine model being allowed to be a candidate motion model, deriving a sixth indicator by analyzing a picture / tile / tile group header of a group of image blocks in the sequence, the sixth indicator specifying whether any affine model is allowed to be a candidate motion model for the image blocks in the group. 4. The method of any one of embodiments 1 to 3, further comprising, in response to a six-parameter affine model being allowed to be a candidate motion model, deriving a seventh indicator by analyzing a picture / tile / tile group header of a group of image blocks in the sequence, the seventh indicator specifying whether the six-parameter affine model is a candidate prediction model for the image blocks in the group. 5. The method of any one of embodiments 1 to 4, wherein the first indicator and / or the second indicator are carried in a picture header of the group of image blocks.6. The method of any one of embodiments 1 to 5, further comprising: in response to the affine model being allowed to be the candidate motion model, deriving a third indicator by analyzing the bitstream, the third indicator specifying whether a prediction mode of the image block is an affine merge mode. 7. The method of any one of embodiments 1 to 6, in response to the affine model being allowed to be the candidate motion model, further comprising: deriving a fourth indicator by analyzing the bitstream, and determining that the prediction mode of the image block is not an affine inter mode in response to the fourth indicator being a second value, and determining that the prediction mode is an affine inter mode in response to the fourth indicator being a first value, wherein the affine inter mode is a six-parameter affine model mode or a four-parameter affine model mode in response to the second indicator being the first value, or the affine inter mode is a four-parameter affine model mode in response to the second indicator being a second value. 8. The method of any one of embodiments 1 to 7, wherein in response to the prediction mode being an affine inter mode, the second indicator indicates that a six-parameter affine model is allowed to be a candidate motion model for the image block, the method further comprising: deriving a fifth indicator by analyzing the bitstream; determining that the prediction mode is a six-parameter affine model mode in response to the fifth indicator being a first value; and determining that the prediction mode is a four-parameter affine model mode in response to the fifth indicator being a second value. 9. The method of any one of embodiments 1 to 8, further comprising: in response to the sum value being greater than 0, deriving a first set of MVD information by analyzing the bitstream, the sum value being a sum of the value of the fourth indicator and the value of the fifth indicator. 10. The method of any one of embodiments 1 to 9, further comprising: in response to the sum value being greater than 1, deriving a second set of MVD information by analyzing the bitstream, the sum value being a sum of the value of the fourth indicator and the value of the fifth indicator.11. An apparatus for determining one or more candidate prediction modes, the apparatus comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 1 to 10. 12. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform any one of embodiments 1 to 10.

[0137] 13. A method comprising: encoding into a bitstream a value of an Affine Inter flag in an SPS, wherein the value of the Affine Inter flag in the SPS specifies whether the Affine Inter flag is present in coding unit level syntax; and encoding into the bitstream a value of an SPS Affine Type flag, wherein the value Affine Type Flag specifies that the Affine Type flag is present in coding unit level syntax. 14. The method of embodiment 13, wherein the SPS Affine Type flag is conditionally signaled / encoded based on the value of the SPS Affine Type flag being a first value or a second value. 15. The method of any one of embodiments 13 to 14, further comprising encoding a value for an Affine Inter flag that specifies whether affine model-based motion compensation is allowed to generate prediction samples for the current coding unit, and encoding a value for an Affine Type flag that specifies whether 6-parameter affine model-based motion compensation is allowed to generate prediction samples for the current coding unit. 16. The method of embodiment 15, wherein the affine inter flag is conditionally signaled based on the value of the affine inter flag being a first value or a second value, and the affine type flag is conditionally signaled based on the value of the affine type flag being the first value or the second value. 17. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 13 to 16. 18. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 13 to 16.

[0138] 19. A method comprising: extracting an SPS Affine Inter flag and an SPS Affine Type flag from a bitstream; determining whether the Affine Inter flag is present in a coding unit level syntax based on a value of the SPS Affine Inter flag; and determining whether the Affine Type flag is present in a coding unit level syntax based on a value of the SPS Affine Type flag and the Affine Inter flag in the coding unit level syntax. 20. The method of embodiment 19, in which the SPS Affine Type flag is inferred to be a second value if the SPS Affine Type flag cannot be successfully extracted from the bitstream. 21. The method of any one of embodiments 19 to 20, further comprising extracting an Affine Inter flag and an Affine Type flag from the bitstream; determining whether affine model-based motion compensation is allowed to generate prediction samples for the current coding unit based on the value of the Affine Inter flag; and determining whether 6-parameter affine model-based motion compensation is allowed to generate prediction samples for the current coding unit based on the value of the Affine Type flag. 22. The method of any one of embodiments 19-21, wherein the affine inter flag is inferred to be a second value if the affine inter flag cannot be successfully retrieved from the bitstream, and the affine type flag is inferred to be a second value if the affine type flag cannot be successfully retrieved from the bitstream. 23. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 19-22. 24. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 19-22.

[0139] 25. A method comprising: determining a first value for a slice affine inter flag that specifies whether syntax elements of a current slice in the current picture are constrained to use affine inter mode in decoding of a slice associated with the slice affine inter flag; encoding the first value for the slice affine inter flag into a bitstream; determining a second value for a slice affine type flag that specifies whether syntax elements of a current slice in the current picture are constrained to use six-parameter affine mode in decoding of a slice associated with the slice affine type flag; and encoding the second value for the slice affine type flag into a bitstream. 26. The method of embodiment 25, wherein the slice affine type flag is conditionally signaled / encoded based on the first value. 27. The method of any one of embodiments 25-26, further comprising: determining a third value for an affine inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit; encoding the third value for the affine inter flag into a bitstream; determining a fourth value for an affine type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit; and encoding the fourth value for the affine type flag into the bitstream. 28. The method of any one of embodiments 25-27, wherein the affine inter flag is conditionally signaled based on the first value and the affine type flag is conditionally signaled based on the second value. 29. An apparatus comprising: a memory; and a processor coupled to the memory, configured to perform any one of embodiments 26-29. 30. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform any one of embodiments 26-28.

[0140] 31. A method comprising: extracting a slice affine inter flag and a slice affine type flag from a bitstream; determining, based on the value of the slice affine inter flag, whether an affine inter mode is allowed to be used in decoding the current picture; and determining, based on the value of the slice affine type flag, whether a six-parameter affine mode is allowed to be used in decoding the current picture. 32. The method of embodiment 31, in which the slice affine type flag is inferred to be a second value when the slice affine type flag cannot be successfully extracted from the bitstream. 33. The method of any one of embodiments 31 to 32, further comprising extracting an affine inter flag and an affine type flag from the bitstream; determining, based on the value of the affine inter flag, whether affine model-based motion compensation is allowed to be used to generate prediction samples for the current coding unit; and determining, based on the value of the affine type flag, whether six-parameter affine model-based motion compensation is allowed to be used to generate prediction samples for the current coding unit. 34. The method of any one of embodiments 31-33, wherein the affine inter flag is inferred to be a second value if the affine inter flag cannot be successfully retrieved from the bitstream, and the affine type flag is inferred to be a second value if the affine type flag cannot be successfully retrieved from the bitstream. 35. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 32-34. 36. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 32-34.

[0141] 37. A method comprising: signaling a value for an Affine Inter flag in an SPS, the value for the Affine Inter flag specifying whether Affine Inter modes are allowed to be used in decoding the video sequence or whether syntax elements of the video sequence shall constrain Affine Inter modes from being used in decoding the video sequence; and, if the value of the Affine Inter flag specifies that Affine Inter modes are allowed to be used in decoding the video sequence, signaling a value for an SPS Affine Type flag specifying whether a 6-parameter Affine mode is allowed to be used in decoding the video sequence or whether syntax elements of the video sequence shall constrain Affine modes from being used in decoding the video sequence. 38. The method of embodiment 37, wherein the SPS Affine Type flag is conditionally signaled based on the value for the Affine Inter flag in the SPS being a first value or a second value, the first value being different from the second value.39. A method according to any one of embodiments 37 to 38, comprising signaling a value for a slice affine inter flag in a slice header, wherein the value for the slice affine inter flag specifies whether affine inter mode is allowed to be used in decoding the slice associated with the slice affine inter flag or whether syntax elements of the video sequence shall be constrained so that affine inter mode is not used in decoding the slice; and, if the value of the slice affine inter flag specifies that affine inter mode is allowed to be used in decoding the slice, signaling a value for a slice affine type flag, wherein the value for the slice affine type flag specifies whether 6-parameter affine mode is allowed to be used in decoding the slice or whether syntax elements of the video sequence shall be constrained so that 6-parameter affine mode is not used in decoding the slice. 40. A method according to any one of embodiments 37 to 39, wherein the slice affine inter flag is conditionally signaled based on the value for the slice affine inter flag in the SPS being a third value or a fourth value, the third value being different from the fourth value, and the slice affine type flag is conditionally signaled based on the value for the slice affine type flag in the SPS being a fifth value or a sixth value, the fifth value being different from the sixth value.41. The method of any one of embodiments 37-40, comprising signaling a value for an Affine Inter flag that specifies whether affine model-based motion compensation is used to generate the predicted samples of the current coding unit by encoding a value for an Affine Inter flag into the bitstream, and signaling a value for an Affine Type flag that specifies whether six-parameter affine model-based motion compensation is used to generate the predicted samples of the current coding unit by encoding a value for an Affine Type flag into the bitstream. 42. The method of any one of embodiments 37-41, wherein the Affine Inter flag is conditionally signaled based on the value for the Affine Inter flag being a first value or a second value, and the Affine Type flag is conditionally signaled based on the value for the Affine Type flag being the first value or the second value. 43. An apparatus comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 37-42. 44. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform any one of embodiments 37-42.

[0142] 45. A method comprising: extracting an SPS Affine Inter flag from a bitstream; and determining, based on the value of the SPS Affine Inter flag, whether affine inter modes are allowed to be used in decoding the video sequence or whether syntax elements of the video sequence shall constrain the use of affine inter modes in decoding the video sequence; and, in the case of the Affine Inter flag, extracting an SPS Affine Type flag from the bitstream; and determining, based on the value of the SPS Affine Type flag, whether six-parameter affine modes are used in decoding the video sequence or whether syntax elements of the video sequence shall constrain the use of six-parameter affine modes in decoding the video sequence. 46. The method of embodiment 45, in which the SPS Affine Type flag is conditionally signaled based on the value of the SPS Affine Type flag being a first value or a second value. 47. A method according to any one of embodiments 45 to 46, further comprising: extracting a slice affine inter flag from the bitstream; and determining, based on the value of the slice affine inter flag, whether affine inter mode is allowed to be used in decoding the slice associated with the slice affine inter flag or whether the slice's syntax elements shall be constrained so that affine inter mode is not used in decoding the slice; and, in the case of the value of the affine inter flag, extracting a slice affine type flag from the bitstream; and determining, based on the value of the slice affine type flag, whether six-parameter affine mode is used in decoding the slice or whether the slice's syntax elements shall be constrained so that six-parameter affine mode is not used when decoding the slice.48. The method of any one of embodiments 45 to 46, wherein the slice affine inter flag is conditionally signaled based on the value of the slice affine inter flag being the third value or the fourth value, and the slice affine type flag is conditionally signaled based on the value of the slice affine type flag being the fifth value or the sixth value. 49. The method of any one of embodiments 45 to 46, wherein the method further comprises: extracting an affine inter flag from the bitstream; determining, based on the value of the affine inter flag, whether affine model-based motion compensation is used to generate the prediction samples of the current coding unit; extracting an affine type flag from the bitstream if affine-affine model-based motion compensation is used to generate the prediction samples of the current coding unit; and determining, based on the value of the affine type flag, whether six-parameter affine model-based motion compensation is used to generate the prediction samples of the current coding unit. 50. The method of any one of embodiments 45-49, wherein the affine inter flag is inferred to be a second value if the affine inter flag cannot be successfully retrieved, and the affine type flag is inferred to be a second value if the affine type flag cannot be successfully retrieved. 51. An apparatus, comprising: a memory; and a processor, coupled to the memory, configured to perform any one of embodiments 45-50. 52. A computer program product, comprising computer-executable instructions stored on a non-transitory medium, that when executed by the processor causes the apparatus to perform any one of embodiments 45-50.

[0143] 53. A method comprising: determining a second value for an affine inter flag; encoding the second value for the affine inter flag into a bitstream; determining a third value for an affine type flag; encoding the third value for the affine type flag into the bitstream; and determining a first value for a motion model indicator variable that specifies a motion model to be used to generate predicted samples of a current coding unit, wherein the motion model is one of a translational motion model, a four-parameter affine model, or a six-parameter affine model, and the first value for the motion model indicator variable is determined by a sum of the second value for the affine inter flag and the third value for the affine type flag. 54. An apparatus comprising: a memory; and a processor coupled to the memory and configured to perform embodiment 53. 55. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform embodiment 53.

[0144] 56. A method comprising receiving a bitstream including an affine inter flag and an affine type flag; determining a third value of a motion model indicator variable based on a first value of the affine inter flag and a second value of the affine type flag; and determining whether the motion model is a translational motion model, a four-parameter affine model, or a six-parameter affine model based on the third value. 57. The method of embodiment 56, wherein determining the third value of the motion model indicator variable based on the first value of the affine inter flag and the second value of the affine type flag comprises determining the third value of the motion model indicator variable based on a sum of the first value of the affine inter flag and the second value of the affine type flag. 58. An apparatus comprising: a memory; and a processor coupled to the memory and configured to perform embodiment 56 or 57. 59. A computer program product comprising computer-executable instructions stored on a non-transitory medium that, when executed by the processor, causes the apparatus to perform embodiment 56 or 57.

[0145] While several embodiments are provided in this disclosure, it will be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of the disclosure. The examples of the present invention should be considered illustrative and not restrictive, and the present invention should not be limited to the details set forth in the specification. For example, various elements or components may be combined or integrated in another system, or certain features may be omitted or not implemented.

[0146] Additionally, techniques, systems, subsystems, and methods described and illustrated in various embodiments as being discrete or separate may be combined or integrated with other systems, components, techniques, or methods without departing from the scope of the present disclosure. Other items shown or described as being coupled may be directly coupled or indirectly coupled or in communication through some interface, device, or intermediate component, whether electrical, mechanical, or otherwise. Other examples of changes, substitutions, and alterations may be ascertainable by those skilled in the art and may be made without departing from the spirit and scope disclosed herein. [Explanation of symbols]

[0147] 100 Coding Systems 110 Source Devices 120 Video Generator 130 Encoder 140 Output Interface 150 Medium 160 Destination Devices 170 Input Interface 180 decoder 190 displays 210 current block 220 current block 300 Video Bitstreams 305 VPS 310 SPS 315 PPS 320, 325, 330, 335 slices 340 Header 345 Data Blocks 350, 355, and 360 410 SPS Syntax 420 SPS Syntax 430 Coding Unit Syntax 510 Slice Segment Header Syntax 520 Slice Segment Header Syntax 530 Coding Unit Syntax 610 SPS Syntax 620 SPS Syntax 630 Slice Segment Header Syntax 640 Coding Unit Syntax 700 Coding Unit Syntax 800 ways 900 ways 1000 ways 1100 methods 1200 methods 1300 methods 1400 methods 1500 ways 1600 methods 1700 equipment 1710 input port 1720RX 1730 CPU, Processor 1740 TX 1750 output port 1760 memory 1770 Motion Model Signaling Component 1800 Coding Methods 1801 Receiving means 1802 Video Coding Device 1803 Storage means 1805 Processing means 1807 Means of transmission

Claims

1. 1. A method implemented by a video decoder, comprising: receiving, by the video decoder, a video bitstream including a Sequence Parameter Set (SPS) Raw Byte Sequence Payload (RBSP), the SPS RBSP including a first SPS level flag, the first SPS level flag equal to 1 specifying that an affine inter flag is present in a coding unit syntax, the first SPS level flag equal to 0 specifying that the affine inter flag is not present in the coding unit syntax, and the affine inter flag equal to 1 specifying that, for a current coding unit, affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding a P or B slice; decoding a video sequence from the video bitstream based on the first SPS level flag; A method comprising:

2. 2. The method of claim 1, wherein the SPS RBSP further includes a second SPS level flag, wherein the second SPS level flag equal to 1 specifies that affine_type_flag is present in the coding unit syntax, and the second SPS level flag equal to 0 specifies that affine_type_flag is not present in the coding unit syntax.

3. The method of claim 1 or 2, wherein the video bitstream further includes the coding unit syntax.

4. The method of claim 3 , wherein the coding unit syntax includes the affine inter flag.

5. The method of any one of claims 1 to 4, wherein the affine inter flag equal to 0 specifies that the current coding unit is not predicted by affine model-based motion compensation.

6. 1. A method implemented by a video encoder, comprising: generating, by the video encoder, a first sequence parameter set (SPS) level flag, wherein the first SPS level flag equal to 1 specifies that an affine inter flag is present in a coding unit syntax, the first SPS level flag equal to 0 specifies that the affine inter flag is not present in the coding unit syntax, and the affine inter flag equal to a first value specifies, for a current coding unit, that affine model-based motion compensation is used to generate predicted samples for the current coding unit when decoding a P or B slice; encoding the first SPS level flag into an SPS Raw Byte Sequence Payload (RBSP); encoding the SPS RBSP into a video bitstream; A method comprising:

7. The method of claim 6 , wherein the affine inter flag equal to 0 specifies that the current coding unit is not predicted by affine model-based motion compensation.

8. 1. An encoding device, comprising: Memory and a processor coupled to the memory and configured to perform the method of claim 6 or 7; an encoding device comprising:

9. A decoding device, comprising: Memory and a processor coupled to said memory and configured to execute the method of any one of claims 1 to 5; A decoding device comprising:

10. A non-transitory computer-readable medium carrying computer-executable instructions that, when executed by a computing device or processor, cause the computing device or processor to perform the method of any one of claims 1 to 7.

11. A computer program comprising program code for performing the method according to any one of claims 1 to 7 when the computer program is run on a computer or processor.

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