Semiconductor detector and its manufacturing method

Abstract

To provide: a semiconductor detector capable of raising an operating voltage (Vth) while suppressing an increase in dark current; and a method of manufacturing the semiconductor detector.SOLUTION: The semiconductor detector comprises: an N-type semiconductor substrate 2; a detection electrode 3 that is formed on a first surface of the semiconductor substrate and that collects charges generated by incidence of a radiant ray X1; a plurality of drift electrodes 4 that are formed to surround the detection electrode and applied with a voltage so as to cause a potential changes toward the detection electrode so that the charges can move to the detection electrode; a radiation incidence window 5 that is provided on a second surface of the semiconductor substrate; a P-type semiconductor region 6 that is formed by adding B to a surface of the second surface in the incidence window; and a depletion electrode BC that is formed on the second surface and that causes a reverse bias between the P-type semiconductor region and an N-type semiconductor region inside the semiconductor substrate. Furthermore, F is added to the P-type semiconductor region, with a region where the concentration of F is highest, is located on the surface side of the second surface with respect to a region where the concentration of B is highest.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor detector capable of detecting radiation and a method for manufacturing the same. [Background technology]

[0002] Silicon drift detectors (hereinafter referred to as SDDs) are used as semiconductor detectors for X-rays or electron beams that are applied to XRF (X-ray fluorescence analyzer) products that detect fluorescent X-rays, SEM-EDS (energy dispersive X-ray spectroscopy) products, and X-ray detectors for synchrotron radiation. This SDD has a p-type semiconductor region formed by implanting boron (B) into the first surface (window surface side) of an n-type high-resistivity substrate, forming a p-n junction.

[0003] Conventionally, to adjust the operating voltage (threshold voltage: hereinafter referred to as Vth) of an SDD, P (phosphorus) or As (arsenic) was additionally implanted as a counter into the region to which B was added, and Vth was adjusted by changing the implantation conditions (implantation amount and implantation depth) (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] European Patent No. 3907533 Summary of the Invention [Problem to be solved by the invention]

[0005] The above-mentioned conventional techniques still have the following problems. Since the EDS characteristics of an SDD are significantly affected by the magnitude of the dark current, there is a demand for increasing Vth without increasing the dark current. However, in conventional semiconductor detectors, Vth is adjusted by additionally implanting P or As, but this has the disadvantage of simultaneously increasing the dark current. This is thought to be due to the increase in crystal defects and the sharpening of the pn junction caused by the additional implantation of P counters, as shown in Figure 3. That is, in comparison with the profile B of "(1) without counters" in Figure 3, in "(2) with counters A", the additional injection of P counters causes a sudden decrease in the effective carriers, making it possible to change the pn junction depth to a shallower one, but this results in a sharp pn junction and causes crystal defects, which leads to an increase in dark current. In particular, if the P counter amount is increased to increase Vth, more crystal defects will occur, as shown in "(3) B with counter in FIG. 3", which will lead to a further increase in dark current. In addition, the Vth of the SDD can be adjusted by changing the substrate resistance or the SDD element design, but in this case, the change is not easy, and even if it is changed, there is a risk that other characteristics (dark current, EDS characteristics, etc.) may also change.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a semiconductor detector that can increase the operating voltage (Vth) while suppressing an increase in dark current, and a method for manufacturing the same. [Means for solving the problem]

[0007] In order to solve the above problems, the present invention employs the following configuration: That is, a semiconductor detector according to a first invention includes an n-type semiconductor substrate, a detection electrode formed on a first surface of the semiconductor substrate and collecting charges generated by incidence of radiation, a plurality of drift electrodes formed to surround the detection electrode and moving the charges toward the detection electrode when a voltage is applied so as to generate a potential gradient in which the potential changes toward the detection electrode, a radiation entrance window provided on a second surface of the semiconductor substrate, a P-type semiconductor region formed within the entrance window on the surface side of the second surface by doping with boron, and a depletion electrode formed on the second surface and applying a reverse bias between the P-type semiconductor region and an N-type semiconductor region in the semiconductor substrate, wherein fluorine is further doped into the P-type semiconductor region, and the region with the highest fluorine concentration is located closer to the surface of the second surface than the region with the highest boron concentration.

[0008] In this semiconductor detector, fluorine is further added to the P-type semiconductor region, and the region with the highest fluorine concentration is located closer to the surface of the second surface than the region with the highest boron concentration, making it possible to adjust the Vth (threshold voltage) while suppressing the effect on dark current. In other words, the effect of B (boron) carriers in the P-type semiconductor region is offset by the F (fluorine) added as a counter, which changes the position of the pn junction and suppresses the expansion of the depletion layer, thereby increasing Vth. In this way, F becomes a negative charge (negatively charged) in the semiconductor substrate and behaves like an n-type carrier, thereby increasing Vth. Furthermore, Vth can be adjusted by controlling the amount and depth of F implantation. In particular, because the region with the highest fluorine concentration is closer to the surface of the second face than the region with the highest boron concentration, the high concentration of F added to the surface side makes it possible to change the depth of the pn junction shallower than when only B is added, thereby adjusting Vth. In addition, because a large amount of F is added to the surface side and less in the deeper region, there are fewer crystal defects due to the addition, and an increase in dark current is also suppressed.

[0009] The semiconductor detector according to the second invention is the same as that of the first invention, and is characterized in that it has a first concentration decrease portion in which the concentration of fluorine decreases in a depth direction from the surface of the second face, and a second concentration decrease portion in a region deeper than the first concentration decrease portion in which the concentration of fluorine decreases in a depth direction more gradually than in the first concentration decrease portion, and the fluorine is distributed deeper in the second concentration decrease portion than in the first concentration decrease portion. That is, in this semiconductor detector, the fluorine concentration in the second concentration decrease section decreases more gradually than in the first concentration decrease section, and fluorine is distributed deeper than boron, so the distribution of effective carriers does not become steep, and the pn junction is not made steep either, thereby suppressing an increase in dark current.

[0010] A manufacturing method of a semiconductor detector according to a third invention is the manufacturing method of a semiconductor detector of the first or second invention, characterized in that it comprises a P-type semiconductor region formation step of forming a P-type semiconductor region by adding boron to the surface side of an n-type semiconductor substrate, the P-type semiconductor region formation step further comprising a fluorine addition step of adding fluorine to the surface side of the semiconductor substrate, and the fluorine addition step comprises a fluorine injection step of injecting the fluorine and a heat treatment step of performing heat treatment after the fluorine injection step. That is, this method of manufacturing a semiconductor detector includes a heat treatment step in which heat treatment is performed after the fluorine implantation step, so that the added F diffuses and moves toward the surface side by the heat treatment, forming a high concentration distribution of F on the surface side, and the depth of the pn junction can be changed to a shallower depth by the deep concentration distribution of B and the shallow concentration distribution of F.

[0011] A fourth aspect of the present invention provides a method for manufacturing a semiconductor detector according to the third aspect of the present invention, characterized in that the heat treatment step is a heat treatment at 800° C. or less. That is, in this method for manufacturing a semiconductor detector, the heat treatment step is performed at a temperature of 800°C or less, so that the diffusion and activation of F can be carried out sufficiently by low-temperature heat treatment at 800°C or less. However, if the heat treatment temperature exceeds 800°C, F will diffuse too much, making it difficult to obtain the effect of F. [Effects of the Invention]

[0012] According to the present invention, the following effects are achieved. That is, according to the semiconductor detector and the manufacturing method thereof of the present invention, fluorine is further added to the P-type semiconductor region, and the region with the highest fluorine concentration is located closer to the surface of the second surface than the region with the highest boron concentration, so that it is possible to adjust Vth (threshold voltage) while suppressing the effect on dark current according to the F implantation amount, implantation depth, etc. Therefore, the semiconductor detector and the manufacturing method thereof of the present invention make it possible to adjust the Vth while suppressing an increase in dark current, and to obtain an SDD with improved EDS characteristics. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing a semiconductor detector in an embodiment of a semiconductor detector and a method for manufacturing the same according to the present invention. [Figure 2] 1A is a graph showing the B concentration distribution, the F concentration distribution, and the pn junction depth before the F implantation heat treatment (FIG. 1A) and after the F implantation heat treatment (FIG. 1B) estimated from SIMS analysis and SRA analysis (Spreading resistance analysis) in this embodiment. [Figure 3] 1 is a graph showing the B concentration distribution, effective carrier distribution, counter concentration distribution, and pn junction depth for "(1) no counter," "(2) counter A," and "(3) counter B," estimated from SIMS analysis, SIMS analysis, and SRA analysis, in the semiconductor detector according to the present invention and the prior art of its manufacturing method. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an embodiment of a semiconductor detector and a method for manufacturing the same according to the present invention will be described with reference to FIGS.

[0015] The semiconductor detector 1 of this embodiment is a silicon drift detector (SDD), and as shown in FIG. 1 , includes an n-type semiconductor substrate 2, a detection electrode 3 formed on a first surface of the semiconductor substrate 2 and collecting charges generated by the incidence of radiation X1, a plurality of drift electrodes 4 formed to surround the detection electrode 3 and causing charges to move toward the detection electrode 3 when a voltage is applied so as to generate a potential gradient in which the potential changes toward the detection electrode 3, an entrance window 5 for radiation X1 provided on a second surface of the semiconductor substrate 2, a P-type semiconductor region 6 formed by adding B (boron) to the surface side of the second surface within the entrance window 5, and a depletion electrode BC formed on the second surface and applying a reverse bias between the P-type semiconductor region 6 and an N-type semiconductor region 2 a in the semiconductor substrate 2.

[0016] The P-type semiconductor region 6 is further doped with F (fluorine), and as shown in Fig. 2, the region with the highest concentration of F is closer to the surface of the second surface than the region with the highest concentration of B. That is, the peak of the concentration profile of F is located closer to the surface of the second surface than the peak of the concentration profile of B. In this embodiment, the peak of the concentration profile of F is located on or near the surface of the second surface. The addition of F may be a dopant of a compound containing F, such as BF2.

[0017] It also has a first concentration decrease portion 7a in which the concentration of F decreases in the depth direction from the surface of the second face, and a second concentration decrease portion 7b in a region deeper than the first concentration decrease portion 7a in which the concentration of F decreases in the depth direction more than in the first concentration decrease portion 7a. In the second concentration decreasing portion 7b, the concentration of F decreases more gradually than in the first concentration decreasing portion 7a, and F is distributed deeper than B. The second reduced concentration portion 7b extends from the P-type semiconductor region 6 to the N-type semiconductor region 2a of the semiconductor substrate 2.

[0018] The semiconductor substrate 2 is a Si substrate doped with n-type impurities, and is a high resistance substrate of 5 kΩ or more. The detection electrode 3 is +It is a signal output electrode made of a semiconductor and functions as an anode electrode. An amplifier 17 is electrically connected to the detection electrode 3 . The amplifier 17 includes, for example, a field effect transistor or a CMOS amplifier, and its gate electrode and the detection electrode 3 are connected.

[0019] The P-type semiconductor region 6 is doped with both B and F. + The semiconductor substrate 2 is made of Si, and a pn junction is formed between the semiconductor substrate 2 and the N-type semiconductor region 2a. The P-type semiconductor region 6 functions as a cathode, and the detection electrode 3 functions as an anode. On the surface of the P-type semiconductor region 6, an oxide film (SiO2) 6a is formed.

[0020] The depletion electrode BC is a back contact connected to the P-type semiconductor region 6, and by adjusting the voltage applied to this depletion electrode BC, a reverse bias is applied to the pn junction, causing a depletion layer to expand from the pn junction and depleting the semiconductor substrate 2. In addition, a plurality of ring-shaped protective electrodes 8 are formed on the outer periphery of the depletion electrode BC, and are set to a floating potential in order to prevent dielectric breakdown between the edge of the semiconductor substrate 2 and the P-type semiconductor region 6.

[0021] The plurality of drift electrodes 4 are concentric ring electrodes centered on the detection electrode 3, and are formed at intervals from one another. The drift electrodes 4 include an inner electrode R1 formed on the inner periphery and an outer electrode RX formed on the outer periphery. Different voltages are applied to the inner electrode R1 and the outer electrode RX, thereby forming a drift electric field in the semiconductor substrate 2 having a depletion layer. That is, the voltage is applied so that the innermost drift electrode 4 has the highest potential and the outermost drift electrode 4 has the lowest potential. The outermost electrode 4a is a ground electrode.

[0022] The first surface is a surface on which a plurality of ring-shaped drift electrodes 4 are formed, that is, a so-called ring surface. The second surface is a surface on which an entrance window 5 is provided, that is, a so-called window surface. On the outer periphery of the entrance window 5, a second surface side insulating film 9 made of an oxide film (SiO2) is formed as a guard ring. The protection electrode 8 and the depletion electrode BC are connected to the semiconductor substrate 2 and the P-type semiconductor region 6 by metal electrodes 9 a that penetrate the second-surface-side insulating film 9 .

[0023] On the first surface, a first surface-side insulating film 10 made of an oxide film (SiO2) is formed. The detection electrode 3 and the plurality of drift electrodes 4 are connected to the N-type semiconductor region 2a of the semiconductor substrate 2 by metal electrodes 10a that penetrate the first surface side insulating film 10, respectively.

[0024] The semiconductor detector 1 of this embodiment operates as follows. First, when radiation X1 such as X-rays, photons, electron beams, or other charged particle beams is incident on the semiconductor substrate 2 through the entrance window 5, charges (holes H and electrons e) corresponding to the energy of the radiation X1 absorbed in the semiconductor substrate 2 are generated in the semiconductor substrate 2. These charges are moved by the electric field in the semiconductor substrate 2, and electrons e flow into and are collected by the central detection electrode 3. The electrons e thus collected by the detection electrode 3 are output as an electric signal via an amplifier 17.

[0025] Next, a method for manufacturing the semiconductor detector 1 of this embodiment will be described. The method for manufacturing the semiconductor detector 1 of this embodiment includes a P-type semiconductor region forming step of forming a P-type semiconductor region 6 by adding B (boron) to the surface of an n-type semiconductor substrate 2. This P-type semiconductor region forming step further includes a fluorine doping step of doping the surface of the semiconductor substrate 2 with F (fluorine).

[0026] The fluorine doping step includes a fluorine implantation step of implanting F and a heat treatment step of performing heat treatment after the fluorine implantation step. The implantation conditions for the fluorine implantation step are appropriately set depending on the concentration of the P-type semiconductor region 6, the pn junction depth, the thickness of the oxide film 6a, and the like. The heat treatment step is preferably a furnace heat treatment at 800°C or less. In addition, when RTA (Rapid Thermal Annealing) is assumed, the temperature may exceed 800 degrees, for example, 850 degrees for 1 minute.

[0027] The diffusion of F is adjusted by lengthening the heat treatment time when the temperature is low and shortening the time when the temperature is high. Vth can also be adjusted by changing the conditions of this heat treatment. Specifically, for example, furnace heat treatment is carried out at 800 degrees for several minutes, 750 degrees for 60 minutes, 650 degrees for 4 hours, 600 degrees for 8 hours, and 500 degrees for 12 to 16 hours. After the heat treatment, hydrogen annealing is preferably performed at 400 to 450° C. for the purpose of H termination. Therefore, the heat treatment is preferably performed at 500° C. or higher. That is, the heat treatment conditions are preferably set to 500 to 800° C. and 1 minute to 12 hours.

[0028] In this way, in the semiconductor detector 1 of this embodiment, fluorine is further added to the P-type semiconductor region 6, and the region with the highest fluorine concentration is located closer to the surface of the second surface than the region with the highest boron concentration. This makes it possible to adjust the Vth (threshold voltage) while suppressing the effect on dark current. That is, the effect of B (boron) carriers in the P-type semiconductor region 6 is offset by F (fluorine), which is further added as a counter, thereby changing the position of the pn junction and suppressing the expansion of the depletion layer, thereby increasing Vth. In this way, F becomes a negative charge (negatively charged) in the semiconductor substrate 2 and behaves like an n-type carrier, thereby increasing Vth. Furthermore, Vth can be adjusted by controlling the amount and depth of F implantation.

[0029] In particular, because the region with the highest fluorine concentration is closer to the surface of the second face than the region with the highest boron concentration, the high concentration of F added to the surface side makes it possible to change the depth of the pn junction shallower than when only B is added, thereby adjusting Vth. In addition, because a large amount of F is added to the surface side and less in the deeper region, there are fewer crystal defects due to the addition, and an increase in dark current is also suppressed.

[0030] Furthermore, the fluorine concentration in the second concentration decreasing portion 7b decreases more gradually than in the first concentration decreasing portion 7a, and fluorine is distributed deeper than boron, so the distribution of effective carriers does not become steep, and the pn junction is not made steep either, thereby suppressing an increase in dark current.

[0031] The method for manufacturing the semiconductor detector 1 of this embodiment includes a heat treatment step in which heat treatment is performed after the fluorine implantation step. This causes the added F to diffuse and migrate to the surface side of the second surface by the heat treatment, forming a high concentration distribution of F on the surface side of the second surface, and the depth of the pn junction can be changed to a shallower depth by the deep B concentration distribution and the shallow F concentration distribution. Furthermore, since the heat treatment step is performed at a temperature of 800° C. or less, the diffusion and activation of F can be carried out sufficiently by the low-temperature heat treatment at 800° C. or less. [Example]

[0032] A number of examples of the semiconductor detector of the present invention were fabricated based on the above-described embodiment by changing the injection conditions of F. The results of measuring the dark current and Vth (threshold voltage) for these examples of the present invention (A to D in Table 1) are shown in Table 1. The range of F implantation conditions is 1×10 12 / cm 2 ~1×10 15 / cm 2 The implantation energy of F was set to 2 KeV to 30 KeV. The heat treatment conditions were all set to 750°C and 60 minutes.

[0033] As Comparative Example 1 of the present invention, a sample was also produced in which no F implantation or heat treatment was performed (Ref in Table 1). In addition, F implantation was performed, but the F implantation energy was set high to implant F deeply, so that the region with the highest F concentration was located deeper on the first surface side than the region with the highest B concentration, which was produced as Comparative Example 2 (E in Table 1). For these Comparative Examples 1 and 2, the same measurements as those for the Examples of the present invention were carried out.

[0034] [Table 1]

[0035] As can be seen from these results, compared to Comparative Example 1 (Ref in Table 1) in which no F implantation was performed, Examples A to D of the present invention have almost no change in dark current, but the threshold voltage (Vth) is higher than that of Comparative Example 1. In Comparative Example 2 (E in Table 1), the F implantation energy was large and F was deeply doped, so the threshold voltage increased significantly, but the dark current also increased.

[0036] The technical scope of the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the spirit of the present invention. [Explanation of symbols]

[0037] 1...semiconductor detector, 2...semiconductor substrate, 3...detection electrode, 4...drift electrode, 5...entrance window, 6...p-type semiconductor region, 7a...first concentration decrease portion, 7b...second concentration decrease portion, BC...depletion electrode, X1...radiation

Claims

1. an n-type semiconductor substrate; a detection electrode formed on a first surface of the semiconductor substrate for collecting charges generated by incidence of radiation; a plurality of drift electrodes formed around the detection electrode, the drift electrodes being configured to move the charges toward the detection electrode by applying a voltage thereto so as to generate a potential gradient in which the potential changes toward the detection electrode; a radiation entrance window provided on a second surface of the semiconductor substrate; a P-type semiconductor region formed by adding boron to a surface side of the second surface within the entrance window; a depletion electrode formed on the second surface for applying a reverse bias between the P-type semiconductor region and an N-type semiconductor region in the semiconductor substrate; the P-type semiconductor region is further doped with fluorine, the region where the concentration of fluorine is highest is located closer to the surface of the second surface than the region where the concentration of boron is highest; and a first concentration decreasing portion in which the concentration of fluorine decreases from the surface of the second surface in a depth direction; a second concentration decrease portion in which the concentration of fluorine decreases in a depth direction in a region deeper than the first concentration decrease portion, 10. The semiconductor detector according to claim 9, wherein the second concentration decrease portion has a fluorine concentration that decreases more gradually than the first concentration decrease portion, and the fluorine is distributed deeper than the boron.

2. A method for manufacturing the semiconductor detector according to claim 1, comprising: a P-type semiconductor region forming step of forming a P-type semiconductor region by adding boron to a surface side of an n-type semiconductor substrate; the P-type semiconductor region forming step includes a fluorine doping step of further doping fluorine to the surface side of the semiconductor substrate, the fluorine addition step includes a fluorine injection step of injecting the fluorine; After the fluorine injection step, a first concentration decreasing portion in which the concentration of fluorine decreases from the surface of the second surface in a depth direction; a second concentration decrease portion in which the concentration of fluorine decreases in a depth direction in a region deeper than the first concentration decrease portion, and a heat treatment step of performing heat treatment so that the concentration of the fluorine in the second concentration decrease portion decreases more slowly than in the first concentration decrease portion and so that the fluorine is distributed deeper than the boron.

3. 3. The method for manufacturing a semiconductor detector according to claim 2, The method for manufacturing a semiconductor detector, wherein the heat treatment step is a heat treatment at 800° C. or less.

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