Semiconductor detector

Abstract

A semiconductor detector 1 includes a first semiconductor region 11, a plurality of second semiconductor regions 14, an electrode 21, a plurality of electrodes 15, an electrode 13, and a circuit 30. The plurality of second semiconductor regions 14 are formed in a first direction D1 with respect to the first semiconductor region 11, and are provided side by side in a second direction D2 intersecting the first direction D1. The electrode 21 is connected to the first semiconductor region 11. Each of the plurality of electrodes 15 is connected to the corresponding one of the plurality of second semiconductor regions 14. The circuit 30 applies a voltage to each of the electrode 21, the electrode 15, and the electrode 13. The first semiconductor region 11 has a groove 112 positioned between the plurality of second semiconductor regions 14 when viewed from the first direction D1. The electrode 13 is disposed in the groove 112 and faces the first semiconductor region 11. The circuit 30 sets the potential of the electrode 13 to a magnitude between the potential of the electrode 21 and the potential of the plurality of electrodes 15.

Description

Semiconductor detector

[0001] This application claims priority to Japanese Patent Application No. 2024-098627, filed on June 19, 2024, and incorporates by reference all of the contents of said Japanese application.

[0002] Patent Document 1 discloses an avalanche photodiode, which includes a SiGeC mixed crystal layer serving as a light absorption layer and a Si layer serving as a carrier multiplication layer.

[0003] Japanese Patent Application Laid-Open No. 2001-313415

[0004] Avalanche diodes are known that enhance light-receiving sensitivity by avalanche-multiplying carriers generated by photoelectric conversion. Avalanche diodes typically have a drift region and a multiplication region. The drift region is a region where carriers are generated by ionization and move. The multiplication region is a region where a large electric field is formed within the semiconductor, resulting in avalanche multiplication. To create a large electric field in the multiplication region, the boundary between the drift region and the multiplication region is heavily doped with impurities.

[0005] The carrier transport speed in the drift region depends on the electric field strength in the drift region. The gain in the multiplication region depends on the electric field strength in the multiplication region. Conventionally, the ratio of the electric field strength in the drift region to the electric field strength in the multiplication region is determined mainly by the impurity concentration at the boundary between these regions, and is a value specific to each avalanche diode. Therefore, there is a problem in that the gain and the response speed cannot be controlled separately. For example, if the bias voltage is lowered to reduce the gain, the response speed also decreases.

[0006] Furthermore, if the impurity is a specific element such as boron (B), a portion of the impurity disappears each time radiation is incident on the avalanche diode. This causes the impurity concentration to decrease over time. This results in a gradual decrease in the gain of the avalanche diode. To obtain a predetermined gain, it is possible to increase the bias voltage applied to the avalanche diode. However, in this case, the avalanche diode would easily be destroyed when light with excessive intensity is incident on it.

[0007] An object of the present disclosure is to provide a semiconductor detector in which the gain can be controlled independently of the response speed.

[0008] [1] A first semiconductor detector according to an embodiment of the present disclosure is a semiconductor detector for detecting light or radiation, comprising: a first semiconductor region, a plurality of second semiconductor regions, a first electrode, a plurality of second electrodes, a third electrode, an insulating region, and a circuit. The first semiconductor region has a first conductivity type. The plurality of second semiconductor regions are formed in a first direction relative to the first semiconductor region, arranged side by side in a second direction intersecting the first direction, and have a second conductivity type. The first electrode is connected to the first semiconductor region. The plurality of second electrodes are connected to the plurality of second semiconductor regions, respectively. The circuit applies voltages to the first electrode, the second electrode, and the third electrode, respectively. The first semiconductor region has a trench located between the plurality of second semiconductor regions when viewed from the first direction, and whose depth direction is in a direction opposite to the first direction. The third electrode and the insulating region are disposed in the trench, the third electrode facing the first semiconductor region, and the insulating region insulates the third electrode from the first semiconductor region. The circuit sets the potential of the third electrode to a magnitude that is between the potential of the first electrode and the potential of the plurality of second electrodes and that is different from the potential of the first electrode and the potential of the plurality of second electrodes.

[0009] [2] A second semiconductor detector according to an embodiment of the present disclosure is a semiconductor detector for detecting light or radiation, comprising: a first semiconductor region, a plurality of second semiconductor regions, a first electrode, a plurality of second electrodes, a third electrode, and an insulating region. The first semiconductor region has a first conductivity type. The plurality of second semiconductor regions are formed in a first direction relative to the first semiconductor region, arranged side by side in a second direction intersecting the first direction, and have a second conductivity type. The first electrode is connected to the first semiconductor region. The plurality of second electrodes are connected to the plurality of second semiconductor regions, respectively. The first semiconductor region has a trench located between the plurality of second semiconductor regions as viewed from the first direction, with the depth direction being opposite to the first direction. The third electrode and the insulating region are disposed in the trench, the third electrode facing the first semiconductor region, and the insulating region insulates the third electrode from the first semiconductor region. The trench includes a first portion and a second portion closer to the second semiconductor region than the first portion in the first direction. The width of the second portion is greater than the width of the first portion. The third electrode is disposed mainly in the first portion of the first and second portions.

[0010] [3] A third semiconductor detector according to an embodiment of the present disclosure is a semiconductor detector for detecting light or radiation, comprising: a first semiconductor region, a plurality of second semiconductor regions, a first electrode, a plurality of second electrodes, a third electrode, and an insulating region. The first semiconductor region has a first conductivity type. The plurality of second semiconductor regions are formed in a first direction relative to the first semiconductor region, arranged side by side in a second direction intersecting the first direction, and have a second conductivity type. The first electrode is connected to the first semiconductor region. The plurality of second electrodes are connected to the plurality of second semiconductor regions, respectively. The first semiconductor region has a trench located between the plurality of second semiconductor regions as viewed from the first direction, with the depth direction being opposite to the first direction. The third electrode and the insulating region are disposed in the trench, the third electrode facing the first semiconductor region, and the insulating region insulates the third electrode from the first semiconductor region. The distance between the second semiconductor region and the third electrode in a direction perpendicular to the first direction is greater than the minimum width of the trench in the same direction.

[0011] When using the semiconductor detectors described above in [1] to [3], a bias voltage is applied between the first electrode and each second electrode, and the potential difference between each second electrode and the third electrode is set smaller than the potential difference between the first electrode and the third electrode. This results in a multiplication region formed on the second semiconductor region side of the third electrode, and a drift region formed on the opposite side of the second semiconductor region, causing the semiconductor detector to operate as an avalanche diode. These semiconductor detectors allow for flexible control of the potential difference between each second electrode and the third electrode. This allows for control of the electric field strength in the multiplication region independently of the bias voltage applied between the first electrode and each second electrode. Therefore, the gain of the semiconductor detector can be controlled independently of the electric field strength in the drift region, i.e., the response speed.

[0012] In addition, as in the semiconductor detector of [1] above, the semiconductor detector may include a circuit that sets the potential of the third electrode to a magnitude between the potentials of the first electrode and the second electrode, but different from the potentials of the first electrode and the plurality of second electrodes, thereby easily applying the potential difference to the first electrode, the second electrode, and the third electrode. As in the semiconductor detector of [2] above, the groove may include a first portion and a second portion that is closer to the second semiconductor region than the first portion in the first direction, the width of the second portion may be greater than the width of the first portion, and the third electrode may be disposed mainly in the first portion of the first and second portions. In this case, the distance from the third electrode to the multiplication region is increased, thereby improving the uniformity of the electric field intensity in the multiplication region and reducing edge breakdown. As in the semiconductor detector of [3] above, the distance between the second semiconductor region and the third electrode in a direction perpendicular to the first direction may be greater than the minimum width of the groove in the same direction. In this case, the distance from the third electrode to the multiplication region is increased, so that the uniformity of the electric field strength in the multiplication region can be improved and edge breakdown can be reduced.

[0013] [4] In the semiconductor detector of [1] above, the circuit may set a potential difference between each of the second electrodes and the third electrode to be smaller than a potential difference between the first electrode and the third electrode. In this case, carriers are more likely to drift toward the multiplication region, making avalanche multiplication more likely to occur.

[0014] [5] In the semiconductor detector of [1] or [4] above, the groove may include a first portion and a second portion that is closer to the second semiconductor region than the first portion in the first direction, the width of the second portion is greater than the width of the first portion, and the third electrode may be disposed mainly in the first portion of the first and second portions. In this case, the distance from the third electrode to the multiplication region is increased, thereby improving the uniformity of the electric field strength in the multiplication region and reducing edge breakdown.

[0015] [6] In the semiconductor detector of [3] above, the groove may include a first portion and a second portion that is closer to the second semiconductor region than the first portion in the first direction, the width of the second portion may be greater than the width of the first portion, the third electrode may be disposed mainly in the first portion of the first and second portions, and the minimum width may be the width of the first portion. In this case, the distance from the third electrode to the multiplication region is increased, thereby improving the uniformity of the electric field strength in the multiplication region and reducing edge breakdown.

[0016] [7] In the semiconductor detectors of [1] to [6] above, the third electrode may extend in the depth direction of the groove. In this case, the surface of the third electrode facing the first semiconductor region becomes longer in the depth direction. By increasing the electric field strength in the multiplication region, a high electron gain can be obtained at a lower voltage.

[0017] [8] In the semiconductor detectors of [1] to [7] above, the third electrode may surround each of the second semiconductor regions when viewed from the first direction. In this case, the uniformity of the electric field strength in the multiplication region can be further improved. Therefore, the occurrence of edge breakdown can be further reduced.

[0018] [9] In the semiconductor detectors of [1] to [8] above, the distance between each of the second semiconductor regions and the third electrode in a direction perpendicular to the first direction may be 0.5 μm or more. In this case, the electric field is less likely to concentrate at the edge of the second semiconductor region, thereby reducing edge breakdown.

[0019]

[10] In the semiconductor detectors of [1] to [9] above, the distance between the plurality of second semiconductor regions and the third electrode in the first direction may be 0.1 μm or more. In this case, the multiplication region is elongated in the first direction, making it easy to obtain a high gain.

[0020]

[11] In the semiconductor detectors of the above [1] to

[10] , the impurity concentration may be uniform in each of the plurality of second semiconductor regions. In this case, it becomes easier to control the gain of the multiplication region.

[0021] According to the present disclosure, it is possible to provide a semiconductor detector in which the gain can be controlled independently of the response speed.

[0022] FIG. 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor detector according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view illustrating a detailed enlargement of a portion of FIG. 1. FIG. 3 is a plan view illustrating a first semiconductor region, a third electrode, and a plurality of second semiconductor regions as viewed from a first direction. FIG. 4 is a perspective view illustrating an enlargement of the first semiconductor region, the second semiconductor region, and the third electrode. FIG. 5 is a diagram illustrating a conventional avalanche diode. FIG. 6 is a graph illustrating an example of the relationship between the multiplication factor (M value) and the cutoff frequency in an avalanche diode. FIG. 7 is a graph illustrating the relationship between the intensity (fluence) of radiation irradiated to a semiconductor and the boron concentration in the semiconductor. FIG. 8 is a graph illustrating the relationship between the bias voltage applied to an avalanche diode and the gain. FIG. 9 is a diagram illustrating differences in carrier migration paths due to differences in the shapes of the first semiconductor region and the electrodes. FIG. 10 is a diagram illustrating differences in carrier migration paths due to differences in the shapes of the first semiconductor region and the electrodes. FIG. 11 shows cross-sectional structures of semiconductor detectors along the first and second directions used in simulations. Fig. 12 is a graph showing the voltage value and output current value of the third electrode of the semiconductor detector. Fig. 13 is a graph showing the electric field intensity profile at the A-B intercept of Fig. 11. Fig. 14 is a graph showing the results of evaluation of an actually fabricated semiconductor detector of one embodiment. Fig. 15 is a graph showing the results of evaluation of the response characteristics of the semiconductor detector. Fig. 16 is a graph showing the results of evaluation of the response characteristics of the semiconductor detector.

[0023] Hereinafter, embodiments of the semiconductor detector according to the present disclosure will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0024] FIG. 1 is a cross-sectional view schematically illustrating the configuration of a semiconductor detector 1 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view enlarging and showing a portion of FIG. 1 in detail. The semiconductor detector 1 of this embodiment detects light (visible light, infrared light, etc.) or radiation (X-rays, gamma rays, alpha rays, beta rays, etc.). As shown in FIGS. 1 and 2 , the semiconductor detector 1 of this embodiment includes a semiconductor substrate 10, a first semiconductor region 11, an insulating region 12, an electrode 13, a plurality of second semiconductor regions 14, a plurality of electrodes 15, an insulating film 16, a semiconductor region 17, an insulating film 18, an insulating film 19, wiring 20, an electrode 21, and a circuit 30.

[0025] The semiconductor substrate 10 has a main surface 101 facing in a first direction D1 and a back surface 102 facing away from the main surface 101. The main surface 101 and the back surface 102 are parallel to each other and are both flat. The semiconductor substrate 10 mainly contains a semiconductor material such as silicon (Si). The semiconductor substrate 10 is doped with an impurity that gives it a first conductivity type (p-type in one embodiment). The p-type impurity is, for example, boron (B). The thickness of the semiconductor substrate 10 is, for example, 200 μm. The resistivity of the semiconductor substrate 10 is, for example, not less than 0.01 Ω·cm and not more than 0.02 Ω·cm.

[0026] The first semiconductor region 11 is provided on the major surface 101 of the semiconductor substrate 10. The first semiconductor region 11 primarily contains a semiconductor material, such as silicon (Si). The semiconductor material of the first semiconductor region 11 may be the same as or different from the semiconductor material of the semiconductor substrate 10. The first semiconductor region 11 is doped with an impurity that imparts a first conductivity type (p-type in one embodiment). The p-type impurity is, for example, boron (B). The impurity concentration of the first semiconductor region 11 is lower than the impurity concentration of the semiconductor substrate 10. The impurity concentration is uniform in the first semiconductor region 11. Here, a uniform impurity concentration means, for example, that the variation in the impurity concentration is within ±200% throughout the entire first semiconductor region 11. Generally, when a gradient is applied to the impurity concentration, a concentration difference greater than ±200% is applied. The thickness of the first semiconductor region 11 is, for example, 50 μm. The resistivity of the first semiconductor region 11 is, for example, 1.5 kΩ·cm to 4.5 kΩ·cm.

[0027] The multiple second semiconductor regions 14 are formed in a first direction D1 relative to the first semiconductor region 11. The multiple second semiconductor regions 14 are arranged side by side in a second direction D2 intersecting the first direction D1. FIG. 3 is a plan view showing the first semiconductor region 11, the electrode 13, and the multiple second semiconductor regions 14 as viewed from the first direction D1. In the example shown in FIG. 3, the multiple second semiconductor regions 14 are arranged two-dimensionally along two directions: the second direction D2 and a third direction D3 perpendicular to both the first direction D1 and the second direction D2. Specifically, the multiple second semiconductor regions 14 are located on lattice points of a virtual square lattice along the main surface 101. The number of the multiple second semiconductor regions 14 is, for example, 160,000, with 400 rows and 400 columns. The multiple second semiconductor regions 14 are divided into two or more groups, and within each group, the multiple electrodes 15 are connected to each other by wiring 20. The number of second semiconductor regions 14 included in each group is, for example, 5 rows and 5 columns, totaling 25. As a result, each group forms a unit cell, and in the entire semiconductor detector 1, for example, 6,400 unit cells are arranged, and the semiconductor detector 1 forms a unit cell array.

[0028] Each second semiconductor region 14 primarily contains a semiconductor material such as silicon (Si). The semiconductor material of each second semiconductor region 14 may be the same as or different from the semiconductor material of the first semiconductor region 11. Each second semiconductor region 14 is doped with an impurity that imparts a second conductivity type (n-type in one embodiment). The impurity of each second semiconductor region 14 may be added by ion implantation into the same semiconductor material as the first semiconductor region 11. In one example, each second semiconductor region 14 is in contact with the first semiconductor region 11. The planar shape of each second semiconductor region 14 as viewed in the first direction D1 is, for example, circular or polygonal. The outer diameter of each second semiconductor region 14 in the second direction D2 is, for example, 0.5 μm or more and 5.0 μm or less, and in one example, is 1.6 μm, 2.0 μm, or 3.0 μm. The outer diameter of each second semiconductor region 14 in the second direction D2 refers to the diameter of the second semiconductor region 14 when the planar shape of the second semiconductor region 14 is circular.

[0029] The electrode 21 is a first electrode in this embodiment. The electrode 21 is provided over the entire back surface 102 of the semiconductor substrate 10 and forms ohmic contact with the back surface 102. As a result, the electrode 21 is connected to the first semiconductor region 11 via the semiconductor substrate 10. When the first conductivity type is p-type, the electrode 21 functions as an anode electrode of the semiconductor detector 1. When the first conductivity type is n-type, the electrode 21 functions as a cathode electrode of the semiconductor detector 1. The electrode 21 includes a material that can form ohmic contact with the semiconductor material of the semiconductor substrate 10. In one example, the electrode 21 has a layered structure of titanium (Ti) / nickel (Ni) / gold (Au).

[0030] Each of the multiple electrodes 15 is a second electrode in this embodiment. Each of the multiple electrodes 15 is provided on each of the multiple second semiconductor regions 14. Each electrode 15 forms ohmic contact with the corresponding second semiconductor region 14. This connects each electrode 15 to the corresponding second semiconductor region 14. When the second conductivity type is n-type, each electrode 15 serves as a cathode electrode of the semiconductor detector 1. When the second conductivity type is p-type, each electrode 15 serves as an anode electrode of the semiconductor detector 1. Each electrode 15 includes a material capable of making ohmic contact with the semiconductor material of the second semiconductor region 14. In one example, each electrode 15 is made of tungsten (W).

[0031] The semiconductor region 17 is formed in the first direction D1 relative to the first semiconductor region 11. The semiconductor region 17 is formed in a frame-shaped region in a plan view and surrounds a plurality of second semiconductor regions 14. The semiconductor region 17 mainly contains a semiconductor material such as silicon (Si). The semiconductor material of the semiconductor region 17 may be the same as or different from the semiconductor material of the first semiconductor region 11. The semiconductor region 17 is doped with an impurity that gives it a first conductivity type (p-type in one embodiment). The impurity concentration of the semiconductor region 17 is higher than the impurity concentration of the first semiconductor region 11. As a result, the semiconductor region 17 confines carriers within the frame.

[0032] The insulating film 18 is provided on the semiconductor region 17. The insulating film 18 is formed in a frame-shaped region in a plan view, and surrounds the plurality of electrodes 15. The insulating film 18 is made of an insulating material, and in one example, is SiO２ It consists of silicon compounds such as

[0033] The insulating film 19 covers the first semiconductor region 11 and the insulating film 18. Furthermore, the insulating film 19 covers the portion of the surface of each second semiconductor region 14 that is not covered by the electrode 15. The insulating film 19 is made of an insulating material, and in one example, is made of tetraethoxysilane (TEOS). Each of the multiple electrodes 15 penetrates the insulating film 19 on the second semiconductor region 14.

[0034] The wiring 20 is provided on the insulating film 19. The wiring 20 is in contact with and connected to the plurality of electrodes 15. This causes the plurality of electrodes 15 to be at the same potential. The wiring 20 is made of a conductive material, and includes, for example, aluminum (Al) or an Al alloy such as AlSiCu.

[0035] The insulating film 16 covers the wiring 20. The insulating film 16 is made of an insulating material, and in one example, is made of a silicon compound such as SiN.

[0036] The circuit 30 applies a voltage to each of the electrode 13, the plurality of electrodes 15, and the electrode 21. The circuit 30 may be provided on the semiconductor substrate 10, or may be provided on a substrate separate from the semiconductor substrate 10. The circuit 30 sets the potential of the electrode 13 to a magnitude between the potential of the electrode 21 and the potential of the electrode 15, but different from the potential of the electrode 21 and the potential of the plurality of electrodes 15. The circuit 30 may set the potential difference between each electrode 15 and the electrode 13 to be smaller than the potential difference between the electrode 21 and the electrode 13. In one example, the potential of the electrode 21 is set to −200 V, the potential of the electrode 15 is set to 0 V (reference potential), and the potential of the electrode 13 is set to any magnitude within a range of −70 V to 0 V.

[0037] A plurality of grooves 112 are formed in the first semiconductor region 11, with the depth direction being the opposite direction to the first direction D1. The plurality of grooves 112 are located between the plurality of second semiconductor regions 14 when viewed from the first direction D1. The depth of the grooves 112 is, for example, 1 μm or more and 10 μm or less, and in one example, 5.5 μm. The electrode 13 and the insulating region 12 are disposed in the grooves 112. The electrode 13 is a third electrode in this embodiment. The electrode 13 is made of a conductive material. In one example, the electrode 13 is made of polysilicon. The electrode 13 faces the side surface of the groove 112 in the first semiconductor region 11. The insulating region 12 is interposed between the electrode 13 and the first semiconductor region 11, and the insulating region 12 insulates the electrode 13 from the first semiconductor region 11. The insulating region 12 is made of an insulating material, and in one example, SiO ２ The upper surface of the electrode 13 is in contact with the insulating film 19, and the other surfaces of the electrode 13 are all in contact with the insulating region 12. In other words, the electrode 13 is surrounded by an insulator, and is not in contact with other conductors or semiconductors except for the wiring for connection to the circuit 30.

[0038] 3 , the multiple grooves 112 include two or more grooves extending along the third direction D3 and aligned in the second direction D2, and two or more grooves extending along the second direction D2 and aligned in the third direction D3. This divides the first semiconductor region 11 into multiple rectangular portions (cells) in a plan view. Each portion of the first semiconductor region 11 corresponds one-to-one with each of the multiple second semiconductor regions 14. The electrode 15 on each second semiconductor region 14 is located at the center of the corresponding portion of the first semiconductor region 11. When viewed from the first direction D1, the electrode 13 surrounds each of the multiple second semiconductor regions 14.

[0039] As shown in FIG. 2 , each groove 112 includes a first portion 112a and a second portion 112b aligned along the first direction D1. The first portion 112a includes the bottom of the groove 112. The second portion 112b is closer to the second semiconductor region 14 in the first direction D1 than the first portion 112a. In this embodiment, the second portion 112b includes the upper end of the groove 112. The width W2 of the second portion 112b is greater than the width W1 of the first portion 112a. As a result, the first semiconductor region 11 includes a region 114 whose side surface is formed by the first portion 112a and a region 115 whose side surface is formed by the second portion 112b. The regions 114 and 115 are aligned along the first direction D1, and the region 115 is closer to the second semiconductor region 14 than the region 114. The width W3 of the region 114 is greater than the width W4 of the region 115. This allows the electric field from the electrode 13 to be efficiently concentrated toward the second semiconductor region 14. The side surfaces of the first portion 112a and the second portion 112b are covered with the insulating region 12.

[0040] The depth of the first portion 112a (in other words, the thickness of the region 114) is, for example, 1 μm or more and 5 μm or less, and is, for example, 4.0 μm. The depth of the second portion 112b (in other words, the thickness of the region 115) is, for example, 1 μm or more and 5 μm or less, and is, for example, 1.5 μm. The width W1 of the first portion 112a is, for example, 0.1 μm or more and 1 μm or less, and is, for example, 0.8 μm. The width W2 of the second portion 112b is, for example, 2 μm or more and 20 μm or less. The width W3 of the region 114 is, for example, 2 μm or more and 20 μm or less. The width W4 of the region 115 is, for example, 0.5 μm or more and 5.0 μm or less. The ratio of the width W3 to the width W4 (W3 / W4) is, for example, 2 or more and 10 or less.

[0041] 4 is an enlarged perspective view of the first semiconductor region 11, the second semiconductor region 14, and the electrode 13. As shown in FIG. 4, the region 114 is defined by the first portions 112a of the multiple grooves 112, and thus has a quadrangular prism (e.g., a cube) shape. The shape of the region 114 is not limited to this, and may be other shapes such as a triangular prism or a hexagonal prism. The region 115 is defined by the second portions 112b of the multiple grooves 112, and thus has a cylindrical shape. In one example, the diameter of the region 115 (same value as the width W4 described above) is the same as the diameter of the second semiconductor region 14.

[0042] 2 and 4 , the electrode 13 is disposed mainly in the first portion 112a of the first portion 112a and the second portion 112b of the groove 112. In other words, the electrode 13 faces mainly the region 114 of the region 114 and the region 115 of the first semiconductor region 11. Here, "disposed mainly in the first portion 112a" means, for example, that 90% or more of the electrode 13 is disposed in the first portion 112a. However, the electrode 13 may also extend up to the bottom surface of the second portion 112b of the groove 112.

[0043] 2, the electrode 13 extends in the depth direction of the groove 112. In other words, the length of the electrode 13 in the first direction D1 is greater than the width of the electrode 13 in the second direction D2.

[0044] In this embodiment, the distance L1 between the second semiconductor region 14 and the electrode 13 in a direction perpendicular to the first direction D1 (e.g., the second direction D2 and the third direction D3) is greater than the minimum width of the groove 112 in the same direction. In this embodiment, the minimum width of the groove 112 is the width W1 of the first portion 112a. The distance L1 is, for example, 0.5 μm or more. The distance L2 between the second semiconductor region 14 and the electrode 13 in the first direction D1 is, for example, 0.1 μm or more.

[0045] When using the semiconductor detector 1 of this embodiment, a bias voltage is applied between the electrode 21 and the electrode 15, and the potential difference between the electrode 15 and the electrode 13 is made smaller than the potential difference between the electrode 21 and the electrode 13. As a result, a multiplication region is formed in the first semiconductor region 11 on the second semiconductor region 14 side across the electrode 13, and a drift region is formed on the opposite side of the second semiconductor region 14, so that the semiconductor detector 1 operates as an avalanche diode. The drift region is a region where carriers are generated by ionization and where the carriers move. The multiplication region is a region where a large electric field is formed in the semiconductor to perform avalanche multiplication of carriers. As in the example described above, when the first conductivity type is p-type and the second conductivity type is n-type, the multiplication region multiplies electrons as carriers.

[0046] The effects obtained by the semiconductor detector 1 of this embodiment having the above configuration will be described along with the problems associated with conventional avalanche diodes. Part (a) of FIG. 5 is a diagram schematically illustrating the cross-sectional structure of a conventional avalanche diode 200. As shown in the figure, the conventional avalanche diode 200 includes a heavily doped semiconductor substrate 201 of a first conductivity type (e.g., p-type), a first conductivity type semiconductor region 202, a heavily doped semiconductor region 203 of the first conductivity type, and a heavily doped semiconductor region 204 of a second conductivity type (e.g., n-type). When a bias voltage is applied between an electrode (not shown) provided on the back surface of the semiconductor substrate 201 and an electrode (not shown) provided on the upper surface of the semiconductor region 204, a high electric field region 205 is formed between the semiconductor region 203 and the semiconductor region 204, and this high electric field region 205 serves as a multiplication region. Part (b) of FIG. 5 is a graph illustrating the distribution of electric field strength in the thickness direction of the avalanche diode 200. In the figure, arrow A1 indicates the drift region, and arrow A2 indicates the multiplication region.

[0047] Thus, the avalanche diode 200 has a drift region and a multiplication region. In order to generate a large electric field in the multiplication region, the semiconductor region 203 located at the boundary between the drift region and the multiplication region is heavily doped with impurities.

[0048] The carrier transport speed in the drift region depends on the electric field strength in the drift region. The gain in the multiplication region depends on the electric field strength in the multiplication region. Conventionally, the ratio of the electric field strength in the drift region to the electric field strength in the multiplication region is primarily determined by the impurity concentration of the semiconductor region 203 and is a value specific to each avalanche diode. This poses a problem in that the gain and the response speed cannot be controlled independently. For example, lowering the bias voltage to reduce the gain also reduces the response speed. FIG. 6 is a graph showing an example of the relationship between the multiplication factor (M value) and the cutoff frequency in an avalanche diode 200. As shown in FIG. 6, in an avalanche diode 200 designed to have an optimal response speed at M=100, for example, a decrease in the M value (i.e., a decrease in gain) significantly deteriorates the frequency characteristics.

[0049] In addition, if the impurity is a specific element such as boron (B), a portion of the impurity in the semiconductor region 203 disappears each time radiation is incident on the avalanche diode 200. This causes the impurity concentration in the semiconductor region 203 to decrease over time. This results in a problem of a gradual decrease in the gain of the avalanche diode 200. FIG. 7 is a graph showing the relationship between the intensity (fluence) of radiation irradiated onto the semiconductor and the boron concentration Neff in the semiconductor. In the figure, graphs G11 to G14 show the change in the boron concentration Neff when the initial boron concentration Neff of the semiconductor is a value corresponding to a resistivity of 10 Ω·cm, 50 Ω·cm, 250 Ω·cm, and 1000 Ω·cm, respectively. Each of graphs G21 to G24 in the figure is a curve obtained by fitting each of graphs G11 to G14 using a specific function. Referring to FIG. 7, it can be seen that the stronger the radiation irradiated onto the semiconductor, the lower the boron concentration Neff in the semiconductor.

[0050] 8 is a graph showing the relationship between the bias voltage applied to an avalanche diode and its gain. In the graph, circular plot G31, square plot G32, diamond plot G33, and triangular plot G34 each correspond to a different radiation intensity. The radiation intensity increases in the order of plot G34, G33, G32, and G31, with plot G34 having the strongest radiation intensity and plot G31 having the weakest radiation intensity. Referring to FIG. 8, it can be seen that the stronger the intensity of radiation irradiated onto the semiconductor, the lower the gain value according to the bias voltage.

[0051] In order to obtain a predetermined gain, it is conceivable to increase the bias voltage applied to the avalanche diode 200. However, in this case, the avalanche diode 200 is easily destroyed when light with excessive intensity is incident thereon.

[0052] To address these problems, in the semiconductor detector 1 of this embodiment, the potential difference between the electrode 15 and the electrode 13 can be freely controlled, and therefore the electric field strength in the multiplication region can be controlled independently of the bias voltage applied between the electrode 21 and the electrode 15. Therefore, the gain of the semiconductor detector 1 can be controlled independently of the electric field strength in the drift region, i.e., the response speed. Even if the impurity concentration in the semiconductor detector 1 decreases over time, the decrease in gain can be suppressed by controlling the potential of the electrode 13.

[0053] As in this embodiment, the semiconductor detector 1 may include a circuit 30 that sets the potential of the electrode 13 to a magnitude between the potentials of the electrodes 21 and 15 and different from the potentials of the electrodes 21 and the plurality of electrodes 15. This makes it possible to easily apply the above-mentioned potential differences to the electrodes 21, 15, and 13.

[0054] As in this embodiment, the circuit 30 may set the potential difference between the electrode 15 and the electrode 13 to be smaller than the potential difference between the electrode 21 and the electrode 13. In this case, carriers tend to drift more easily toward the multiplication region, making avalanche multiplication more likely to occur.

[0055] As in this embodiment, the groove 112 may include a first portion 112a and a second portion 112b, the width of the second portion 112b being greater than the width of the first portion 112a, and the electrode 13 may be disposed mainly in the first portion 112a of the first and second portions 112a and 112b. Here, FIGS. 9 and 10 are diagrams for explaining differences in the movement path of the carriers 36 due to differences in the shapes of the first semiconductor region 11 and the electrodes. Parts (a) and (b) of FIG. 9 show a comparative example. In the example shown in part (a) of FIG. 9, a pair of electrodes 33 and 34 are arranged side by side along the first direction D1, each surrounding the first semiconductor region 11. A potential difference is applied between the electrodes 33 and 34. The potential of the electrode 33 is, for example, −200 V, and the potential of the electrode 34 closer to the second semiconductor region 14 is, for example, +10 V. As a result, a leakage electric field 37 is formed inside the first semiconductor region 11, and this leakage electric field 37 forms a multiplication region 35 in the first semiconductor region 11. Carriers 36 then pass through the multiplication region 35. However, in this configuration, the strength of the leakage electric field 37 is small, which poses a problem in that the gain of the multiplication region 35 cannot be increased sufficiently.

[0056] 9(b), the first semiconductor region 11 is also disposed around the second semiconductor region 14 in a plan view, and a ring-shaped electrode 38 is provided on the first semiconductor region 11 to surround the second semiconductor region 14. The potential of the electrode 38 is set to a potential (e.g., −50 V) between the potentials of the electrodes 21 and 15. In this case, an electric field 39 from the electrode 38 forms a multiplication region 35 around the second semiconductor region 14. However, in this configuration, it is unclear into which position in the multiplication region 35 the carriers 36 will penetrate, which poses a problem of unstable multiplication.

[0057] To address these problems, as shown in part (a) of FIG. 10 , for example, a groove 113 surrounding the second semiconductor region 14 in a plan view is formed in the first semiconductor region 11, and the electrode 13 is disposed in the groove 113. The potential of the electrode 13 is set to a potential (e.g., −50 V) between the potentials of the electrodes 21 and 15. In this case, an electric field 41 from the electrode 13 forms a multiplication region 35 in a region of the first semiconductor region 11 located closer to the second semiconductor region 14 than the electrode 13. Because the multiplication region 35 is limited to the region surrounded by the groove 113, the carriers 36 always enter the multiplication region 35 from the bottom surface and travel in the thickness direction of the multiplication region 35. Therefore, the carriers 36 can stably enter the multiplication region 35, stabilizing the multiplication effect.

[0058] However, in this configuration, the multiplication region 35 is formed near the electrode 13, which raises concerns about the uniformity of the electric field strength in the multiplication region 35. If the electric field strength in the multiplication region 35 is non-uniform, edge breakdown is more likely to occur, potentially preventing stable multiplication. Therefore, as shown in part (b) of FIG. 10 , a groove 112 including a first portion 112a and a second portion 112b is formed instead of the groove 113. The electrode 13 is then placed within the first portion 112a. In this case, the electric field 41 from the electrode 13 forms the multiplication region 35 in the region of the first semiconductor region 11 surrounded by the second portion 112b of the groove 112. Because the multiplication region 35 is limited to the region surrounded by the second portion 112b, the carriers 36 always enter the multiplication region 35 from the bottom surface and travel in the thickness direction of the multiplication region 35. Therefore, the carriers 36 can enter the multiplication region 35 more stably, stabilizing the multiplication effect. In addition, since the distance from the electrode 13 to the multiplication region is increased, the uniformity of the electric field strength in the multiplication region 35 can be improved and edge breakdown can be reduced. By providing the semiconductor detector 1 of this embodiment with the configuration shown in part (b) of Figure 10, it is possible to stabilize the multiplication action, increase the uniformity of the electric field strength in the multiplication region, and reduce edge breakdown.

[0059] 11 to 13 are graphs showing simulation results for the semiconductor detector 1 of this embodiment. FIG. 11 shows the cross-sectional structure (half of each cell) of the semiconductor detector 1 along the first direction D1 and the second direction D2 used in the simulation. FIG. 12 is a graph showing the voltage value of the electrode 13 of the semiconductor detector 1 and the output current value of the semiconductor detector 1. In FIG. 12, graph G41 shows the output current value when light is incident, and graph G42 shows the output current value when no light is irradiated, i.e., the dark current value. FIG. 13 is a graph showing the electric field intensity profile at the A-B intercept of FIG. 11, illustrating how the electric field intensity in the multiplication region increases with increasing voltage applied to the electrode 13. As shown in these figures, with the semiconductor detector 1 of this embodiment, the electric field intensity in the multiplication region becomes nearly uniform, the current path expands in the second direction D2, and carriers can be efficiently multiplied.

[0060] FIG. 14 is a graph showing the results of an evaluation of an actual semiconductor detector 1 according to this embodiment. Part (a) of FIG. 14 shows the change in gain when the semiconductor detector 1 is operated as a normal photodiode with no voltage applied to the electrode 13 (open state) and the potential difference (bias voltage) between the electrodes 15 and 21 is varied between 0 V and 400 V. Part (b) of FIG. 14 shows the change in gain when the potentials of the electrodes 21 and 15 are fixed at −200 V and 0 V, respectively, and the potential of the electrode 13 is varied between −70 V and 0 V. When the semiconductor detector 1 is operated as a normal photodiode, as shown in part (a) of FIG. 14 , the gain saturated at a low value when the bias voltage exceeded a certain value. In contrast, as shown in part (b) of FIG. 14 , when the potential difference (bias voltage) between the electrodes 15 and 21 was kept constant and the potential difference between the electrodes 15 and 13 was varied, the gain increased exponentially. From this, it can be seen that with the semiconductor detector 1 of this embodiment, the gain can be freely controlled by controlling the potential of the electrode 13.

[0061] 15 and 16 are graphs showing the results of a response characteristic evaluation of the semiconductor detector 1 of this embodiment, in which a pulsed laser with a wavelength of 905 nm was incident on the semiconductor detector 1 and the potential difference (bias voltage) between the electrode 21 and the electrode 15 was varied in 50 V increments from 50 V to 250 V. FIG. 15 shows the case where one side of the cell was 10 μm and the potential difference between the electrode 13 and the electrode 15 was 72.5 V, while FIG. 16 shows the case where one side of the cell was 5 μm and the potential difference between the electrode 13 and the electrode 15 was 44.6 V. In this evaluation, the pulse width of the light pulse was 30 nanoseconds and the frequency was 10 kHz. The results were obtained by measuring with an oscilloscope probe directly applied to the wiring 20. As shown in these graphs, the semiconductor detector 1 of this embodiment amplifies the pulse current corresponding to the light pulse depending on the bias voltage, similar to a typical avalanche photodiode.

[0062] As in the present embodiment, the distance L1 between the second semiconductor region 14 and the electrode 13 in the second direction D2 may be greater than the minimum width of the groove 112 in the second direction D2. In this case, the distance from the electrode 13 to the multiplication region is increased, thereby improving the uniformity of the electric field strength in the multiplication region and reducing edge breakdown. The minimum width of the groove 112 may be, for example, the width W1 of the first portion 112a.

[0063] As in this embodiment, the electrode 13 may extend in the depth direction of the groove 112. In this case, the surface of the electrode 13 facing the first semiconductor region 11 becomes longer in the depth direction. By increasing the electric field strength in the multiplication region, a high electron gain can be obtained at a lower voltage.

[0064] As in the present embodiment, the electrode 13 may surround each of the second semiconductor regions 14 when viewed from the first direction D1. In this case, the uniformity of the electric field strength in the multiplication region can be further improved, thereby further reducing the occurrence of edge breakdown.

[0065] As in the present embodiment, the distance between each of the second semiconductor regions 14 and the electrode 13 in the direction perpendicular to the first direction D1 may be 0.5 μm or more. In this case, the electric field is less likely to concentrate at the end of the second semiconductor region 14, which further reduces the occurrence of edge breakdown.

[0066] As in the present embodiment, the distance between the plurality of second semiconductor regions 14 and the electrode 13 in the first direction D1 may be 0.1 μm or more. In this case, the multiplication region becomes longer in the first direction D1, so that a high gain can be easily obtained.

[0067] As in this embodiment, the impurity concentration may be uniform in the first semiconductor region 11. In this case, it becomes easier to control the gain of the multiplication region.

[0068] As in this embodiment, the region 115 may have a cylindrical outer shape. In this case, the uniformity of the electric field strength in the multiplication region can be further improved, thereby further reducing the occurrence of edge breakdown.

[0069] The semiconductor detector according to the present disclosure is not limited to the above-described embodiment, and various other modifications are possible. For example, the first conductivity type may be n-type and the second conductivity type may be p-type. In this case, the multiplication region multiplies holes as carriers.

[0070] While the principles of the present invention have been illustrated and described in preferred embodiments, it will be recognized by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the particular constructions disclosed herein. We therefore claim all modifications and variations that come within the scope and spirit of the following claims.

[0071] DESCRIPTION OF SYMBOLS 1...Semiconductor detector, 10...Semiconductor substrate, 11...First semiconductor region, 12...Insulating region, 13...Electrode (third electrode), 14...Second semiconductor region, 15...Electrode (second electrode), 16, 18, 19...Insulating film, 17...Semiconductor region, 20...Wiring, 21...Electrode (first electrode), 30...Circuit, 33, 34, 38...Electrode, 35...Multiplication region, 36...Carrier, 37, 39, 41 ...electric field, 101...main surface, 102...rear surface, 112, 113...groove, 112a...first portion, 112b...second portion, 114, 115...region, 200...avalanche diode, 201...semiconductor substrate, 202, 203, 204...semiconductor region, 205...high electric field region, D1...first direction, D2...second direction, D3...third direction, L1, L2...distance, W1 to W4...width.

Claims

1. A semiconductor detector for detecting light or radiation, comprising: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type, formed in a first direction relative to the first semiconductor region and arranged side by side in a second direction intersecting the first direction; a first electrode connected to the first semiconductor region; a plurality of second electrodes connected to each of the plurality of second semiconductor regions; a third electrode; an insulating region; and a circuit for applying voltages to the first electrode, the plurality of second electrodes, and the third electrode, respectively; wherein the first semiconductor region has a groove located between the plurality of second semiconductor regions when viewed from the first direction, and whose depth direction is in a direction opposite to the first direction; the third electrode and the insulating region are disposed in the groove, the third electrode facing the first semiconductor region, and the insulating region insulates the third electrode from the first semiconductor region; and the circuit sets the potential of the third electrode to a magnitude that is between the potential of the first electrode and the potential of the plurality of second electrodes and that is different from the potential of the first electrode and the potential of the plurality of second electrodes.

2. The semiconductor detector according to claim 1, wherein the circuit sets the potential difference between each of the plurality of second electrodes and the third electrode to be smaller than the potential difference between the first electrode and the third electrode.

3. The semiconductor detector of claim 1, wherein the groove includes a first portion and a second portion that is closer to the second semiconductor region in the first direction than the first portion, the width of the second portion is greater than the width of the first portion, and the third electrode is disposed mainly in the first portion of the first and second portions.

4. A semiconductor detector for detecting light or radiation, comprising: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type, formed in a first direction relative to the first semiconductor region and arranged side by side in a second direction intersecting the first direction; a first electrode connected to the first semiconductor region; a plurality of second electrodes connected to each of the second semiconductor regions; a third electrode; and an insulating region, wherein the first semiconductor region has a groove located between the second semiconductor regions when viewed from the first direction, the groove having a depth direction in a direction opposite to the first direction, the third electrode and the insulating region being disposed in the groove, the third electrode facing the first semiconductor region, and the insulating region insulating the third electrode from the first semiconductor region, the groove including a first portion and a second portion closer to the second semiconductor region than the first portion in the first direction, the width of the second portion being greater than the width of the first portion, and the third electrode being disposed mainly in the first portion of the first and second portions.

5. A semiconductor detector for detecting light or radiation, comprising: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type, formed in a first direction relative to the first semiconductor region and arranged side by side in a second direction intersecting the first direction; a first electrode connected to the first semiconductor region; a plurality of second electrodes connected to the plurality of second semiconductor regions, respectively; a third electrode; and an insulating region, wherein the first semiconductor region has a groove located between the plurality of second semiconductor regions when viewed from the first direction, the groove having a depth direction in a direction opposite to the first direction, the third electrode and the insulating region being disposed in the groove, the third electrode facing the first semiconductor region, and the insulating region insulating the third electrode from the first semiconductor region, and the distance between the second semiconductor region and the third electrode in a direction perpendicular to the first direction is greater than the minimum width of the groove in the same direction.

6. The semiconductor detector according to claim 5, wherein the groove includes a first portion and a second portion that is closer to the second semiconductor region in the first direction than the first portion, the width of the second portion is greater than the width of the first portion, the third electrode is disposed mainly in the first portion of the first and second portions, and the minimum width is the width of the first portion.

7. The semiconductor detector according to any one of claims 1 to 6, wherein the third electrode extends in the depth direction of the groove.

8. The semiconductor detector according to any one of claims 1 to 7, wherein the third electrode surrounds each of the plurality of second semiconductor regions when viewed from the first direction.

9. A semiconductor detector according to any one of claims 1 to 8, wherein the distance between the plurality of second semiconductor regions and the third electrode in a direction perpendicular to the first direction is 0.5 μm or more.

10. A semiconductor detector according to any one of claims 1 to 9, wherein the distance between each of the plurality of second semiconductor regions and the third electrode in the first direction is 0.1 μm or more.

11. The semiconductor detector according to any one of claims 1 to 10, wherein the impurity concentration in the first semiconductor region is uniform.

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