quantum error correction

Abstract

The present disclosure relates to a quantum processor including a plurality of patches of digital qubits and a quantum bus of the digital qubits. The quantum bus connects the plurality of patches of digital qubits and is configured to transmit quantum information comprising long-range interactions between the patches of digital qubits. The quantum processor is controlled by a first error correction method for each of the patches connected by the bus to reduce a relatively high error rate of the digital qubits to a relatively low error rate for each patch, and a second error correction method for the plurality of patches to correct the relatively low error rate. In this manner, the final error rate can be reduced by increasing the number of patches and the distance of the second method. The quantum bus allows the patches to be arranged so that there is sufficient space between the patches for control circuitry.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Australian Provisional Application No. 2020903848 and Australian Provisional Application No. 2021901279, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to quantum processors and methods for operating quantum processors, and in particular to layout designs and physical architectures for quantum processors that support error correction with current quantum technology. [Background technology]

[0003] Quantum computers are difficult to build due to the inherent instability of quantum information in quantum physical systems ("qubits"). One proposed approach is a quantum error-correcting code called a surface code. Surface codes are built on arrays of closely packed qubits. In some implementations, each qubit is only about 100 nm × 100 nm or smaller in size. The distance between qubits is typically within this size to allow for interactions between neighboring qubits. As a result, the overall area of ​​the array used for surface codes is small. However, each qubit must be connected to control circuitry by "wires," implemented, for example, as metal lines across a silicon substrate. The small size of the qubit array means that the connecting wires must also be densely packed. However, with current hardware technology, it is difficult to fabricate wires small enough to connect all the qubits, especially those in the center of the qubit array.

[0004] Any discussion of documents, acts, materials, devices, articles or the like which has been included in this specification should not be construed as an admission that any or all of such matters form part of the prior art or were common general knowledge in the art relevant to the present disclosure by virtue of existing prior to the priority date of each claim.

[0005] Throughout this specification, the words "comprise" or variations such as "comprises" or "comprising" will be understood to imply the inclusion of the specified elements, integers or steps, or groups of elements, integers or steps, but not the exclusion of other elements, integers or steps, or groups of other elements, integers or steps. Summary of the Invention [Means for solving the problem]

[0006] This disclosure provides a quantum processor architecture that facilitates fabrication of quantum processors using current hardware technology. In particular, the proposed architecture includes small patches of qubits controlled by a surface code. The patches are connected by a quantum bus, allowing long-range interactions between qubits in different patches. A second error-correcting code is run on top of the surface code using the patches as logical qubits.

[0007] Quantum processors are multiple patches of digital qubits; a digital qubit quantum bus configured to connect a plurality of patches of digital qubits and to transmit quantum information comprising long-range interactions between the patches of digital qubits; The quantum processor is controlled by a first error correction method for each of the patches connected by the bus to reduce a relatively high error rate of the digital qubits to a relatively low error rate for each patch, and a second error correction method for the plurality of patches to correct the relatively low error rate.

[0008] Advantageously, a quantum processor may include patches of qubits, controlled by a first error correction method, and then controlled by a second error correction method for the patches. In this way, the final error rate can be reduced by increasing the number of patches and the distance of the second method. Advantageously, the quantum bus allows the patches to be arranged so that there is enough space between them for control circuitry. This is an advantage over large, square qubit arrays, which are difficult to connect in practice.

[0009] The quantum bus may have qubits of a fixed width.

[0010] The patch may be square.

[0011] The plurality of patches may form a plurality of arrays of the plurality of patches, each connected by a quantum bus. The plurality of arrays may be linear arrays. Each linear array may have the same width. Each linear array may have an array width defined by one of the plurality of patches and the quantum bus, the array width being 15 or 20. Each linear array may have an array length defined by several of the plurality of patches and the quantum bus, the array length being 120 or 160.

[0012] The quantum processor may further include regions between the patches that include connections to the digital qubits of the patches.

[0013] The digital qubits of the bus may be controlled by a first error correction method. The first error correction method may include a surface code. The second error correction method may include a block code. The block code may include a Steane code.

[0014] A relatively low error rate of 10 -5 A relatively low error rate can be less than 10 -8 Correcting for a relatively low error rate can result in a corrected error rate of 10 -9 It can be less than.

[0015] The quantum processor may further include control circuitry that performs the first error correction method and the second error correction method.

[0016] The patch may be rectangular and may have a first dimension greater than a second dimension to reduce the error rate of a first type of error associated with the first dimension more than the error rate of a second type of error associated with the second dimension.

[0017] The first error correction method may be an asymmetric surface code for reducing the error rate of the first type of error more than the error rate of the second type of error.

[0018] The second error correction method may be a repetition code to reduce the error rate of the second type of error.

[0019] The second error correction method may reduce the error rate of only the second type of error.

[0020] The first type of error may be one of a bit flip error and a phase flip error, and the second type of error may be another of a bit flip error and a phase flip error.

[0021] A method of operating a quantum processor is provided, the quantum processor including a plurality of patches of digital qubits and a quantum bus of digital qubits connecting the plurality of patches of digital qubits and configured to transmit quantum information comprising long-range interactions between the patches of digital qubits, the method comprising: applying a first error correction method to each of the patches connected by the bus to reduce the relatively high error rate of the digital qubits to a relatively low error rate for each patch; and applying a second error correction method to the plurality of patches to correct a relatively low error rate.

[0022] A method for manufacturing a quantum processor includes: creating a plurality of patches of digital qubits to form a first array of the plurality of patches; connecting the plurality of patches of the first array by a quantum bus of digital qubits configured to connect the plurality of patches of digital qubits and to transmit quantum information comprising long-range interactions between the patches of digital qubits; creating a plurality of further arrays having the same number of patches as the first array; connecting a plurality of further arrays to the first array by quantum buses; and creating a control circuit that controls the quantum processor with a first error correction method for each of the patches connected by the bus to reduce a relatively high error rate of the digital qubits to a relatively low error rate for each patch, and a second error correction method for the plurality of patches to correct the relatively low error rate.

[0023] The number of multiple additional arrays may be based on a desired error rate after correction of the relatively low error rate. [Brief explanation of the drawings]

[0024] [Figure 1] 1 shows a quantum processor. [Figure 2] The connection of a rotating surface cord patch with a distance of 7 is shown. [Figure 3] Shown is a stabilizer for a rotating surface chord with a distance of 7. [Figure 4a] A square surface code patch is shown. [Figure 4b]1 shows a rectangular surface-coded patch containing a single qubit. [Figure 5] A rectangular surface-coded patch containing two qubits is shown. [Figure 6] 1 shows an exemplary structure of a square patch in a linear array. [Figure 7] 1 shows an exemplary structure of rectangular patches in a linear array. [Figure 8] An example is shown of two linear arrays of square patches arranged perpendicular to each other. [Figure 9] 1 shows a parity measurement gadget. [Figure 10] The results of the proposed method are shown. [Figure 11] A method for operating a quantum processor is shown. [Figure 12] A method for fabricating a quantum processor is presented. [Figure 13] A rectangular planar surface code with d_z=3 and d_x=7 is shown, containing an array of physical qubits 13 deep and 5 wide. [Figure 14] 14 shows the Z-stabilizer quantum circuit for use with the surface code from FIG. 13. [Figure 15] 14 shows the X-stabilizer quantum circuit for use with the surface code from FIG. 13. [Figure 16] 1 shows a quantum circuit that performs a parity check. [Figure 17] A series of error correction operations is shown below. DETAILED DESCRIPTION OF THE INVENTION

[0025] quantum processor 1 illustrates a quantum processor 100 that includes multiple digital qubits, shown as small rounded squares, such as exemplary qubit 101. Digital qubits may be qubits that represent quantum information in a digital sense, such as electron or nuclear spin, or superconducting digital qubits using Josephson junctions. Digital qubits are in contrast to analog qubits used in adiabatic quantum computers. Digital qubits may serve a variety of functions, such as data qubits or auxiliary qubits.

[0026] The qubits are arranged in multiple patches of digital qubits, such as exemplary patch 102. Each patch may be referred to as a subset, group, or region of qubits. The bold lines in FIG. 1 indicate logical groupings of qubits and do not necessarily represent hardware functionality. The patches of qubits are shown in FIG. 1 as square patches for clarity, although rectangular patches or other shapes are also possible. In the example of FIG. 1, the patch has a size of 10×10 qubits, meaning that the bold square representing patch 102 contains 100 rounded squares (i.e., qubits).

[0027] Quantum processor 100 also includes quantum buses of digital qubits, including intraqubit bus 103 and main quantum bus 104. Quantum buses 103 / 104 connect multiple patches of digital qubits 102 and transmit quantum information that constitutes long-range interactions between patches of digital qubits. References herein to "quantum buses" refer collectively to intraqubit bus 103 and quantum bus 104 as one "bus."

[0028] Quantum processor 100 is controlled by a first error correction method, such as a surface code, for each of the patches 102 connected by the bus. The surface code reduces the relatively high error rate of the digital qubits to a relatively low error rate for each patch. Quantum processor 100 is further controlled by a second error correction method, such as a block code or a Steane code, for the multiple patches. The block code corrects the relatively low error rate of the patches to ultimately provide a sufficiently low error rate for the desired operation of quantum processor 100.

[0029] Quantum Bus The quantum bus 103 / 104 can be used to perform fault-tolerant long-distance parity check operations. Long-distance parity checks provide a recipe for performing fault-tolerant parity checks of any length. The operation of the quantum bus 103 / 104 may include the following steps: 1. Generate a Greenberger-Horn-Zeilinger state (GHZ state) using N data qubits (in 4 time steps) and maintain the state corrected for bit-flip errors (for d cycles). 2. Perform transversal CNOT operations between all connected surface code patches and their parts of the GHZ state. Since CNOT can be applied in parallel, only one time step is required. 3. All data qubits in the complete chain of GHZ states are measured (in one time step) without measuring any further stabilizers. 4. Repeat steps 1-3 d times, using majority voting on the individual measurements, to calculate the total time O(d 2 ) to obtain the error-corrected measurement results.

[0030] In the example of FIG. 1 , the main quantum bus 104 is five qubits wide, although other widths are possible as well. Furthermore, as can be seen, the quantum bus has a constant width. This means that the bus is five qubits wide throughout the quantum processor 100. The main quantum bus 104 connects columns, also called “arrays” or, in the example of FIG. 1 , “linear arrays,” because all patches in the array are arranged in a line. Therefore, each linear array has the same width, which in this example is 15 physical qubits wide, including 10 patch qubits and 5 bus qubits. The width of the array is defined by the size of one patch and the width of the quantum bus. In FIG. 1 , each linear array is 75 physical qubits long, thus having dimensions of 15×75. Other configurations may be 15×120 or 20×160, with each column containing seven or 15 logical qubits (i.e., patches); note that FIG. 1 shows only four patches per column. The exact dimensions may vary and depend on code or design choices.

[0031] In one example, the dimension depends on the details of the second-level code and the size of each patch 102. In particular, the width of the patch 102 can be twice the code distance. Thus, the example in Figure 1 shows a code with a patch width of 10 and a distance of 5. Note that Figure 1 shows unrotated surface code patches, while Figure 2 shows a rotated structure. In Figure 1, the bus is 5 qubits wide, the same as the code distance in this example. While Figure 1 shows only four patches per linear array, other implementations can include more patches, for example, 11 (Steane code, 7 + 2 + 2 = 11) or 19 ([[15,7,3]] code, 15 + 2 + 2 = 19) patches per linear array. Other configurations of the code can also be used. The sum includes ancillary qubits for syndrome extraction and implementation of the CNOT gadget. The notation [[n,k,d]] denotes a quantum error-correcting code that encodes k logical qubits into n physical qubits at quantum code distance d. Thus, a [[15,7,3]] code encodes seven logical qubits into 15 physical qubits at a distance of 3 and corrects at least one quantum error. In other words, each linear array represents the output of a selected code and ancillary qubit / gadget ("output" here means the result of multiplying the input and code matrix, as in classical information theory). For example, if a code encodes seven logical qubits into 15 physical qubits, there is one patch per physical qubit and ancillary / gadget qubit. That is, each patch represents one qubit (or ancillary / gadget) of the second-level code, and each linear array represents the code output. Furthermore, if a larger first-level code distance is required, additional physical qubits can be added to the design of each patch, as in the code with a distance of 11 shown below.

[0032] Note that the width of each logical qubit 102 determines the maximum possible distance of surface code error correction. In other words, wider logical qubits provide better error correction, while narrower logical qubits provide worse error correction. Surface error codes are applied to individual physical qubits, which have a relatively high error rate. Meanwhile, block codes, such as the Steane (7-qubit) code [[7,1,3]] or [[15,7,3]] code and other Calderbank-Shor-Steane (CSS) codes, are applicable to lower error rates. Therefore, the width of each logical qubit is selected so that the error rate obtained from the surface code is low enough to apply the block code in a second-level error correction to provide a sufficiently low error rate for the target quantum computation. In some examples, the width is 15 or 20 physical qubits, although other values ​​are also selected. Wider logical qubits reduce the error rate at the first level, but as long as the width exceeds a threshold, the second-level error correction code can correct the remaining errors, increasing manufacturing costs without any direct benefit.

[0033] Also, the bottom horizontal region 104 is a master bus system that can be used to interact with logical qubits at the highest level of encoding. This allows each logical qubit to interact and execute algorithms. The bus is again fully error corrected and has a finite width and length proportional to the number of logical qubit "forks" / arrays in the overall computer.

[0034] The physical arrangement of the logical qubits and bus system allows the chipset to be highly distributed. The white space in Figure 1 represents the area where control electronics can be placed and wired to each physical qubit in the system for operation and control of computer 100. The size and density of these control electronics dictates the precise geometric layout of the forks and bus system that make up the chipset.

[0035] Error correction Most current quantum computing architectures assume that computations are performed using large 2D square lattices of qubits with single-qubit gates and nearest-neighbor interactions. In these architectures, logical qubits are typically represented using surface codes in roughly square patches, where one dimension determines the susceptibility to X-type errors and the other dimension determines the susceptibility to Z-type errors (more precisely, the minimum Manhattan distance between the rough and smooth boundaries determines the code distance, which is minimized for rotated squares). Many quantum computations require a logical error rate of

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[0036] However, in many architectures, the cost and difficulty per qubit increases (often nonlinearly) with the distance between a particular qubit and the edge of the array due to the cost and challenges of qubit control interconnects. Thus, the present disclosure provides a scalable architecture that can perform computations at much narrower widths than this, at the expense of additional time and qubits.

[0037] This disclosure provides a hybrid multi-layer error correcting code, where there are two main layers. 1. A first level code that is a base rotated surface code with code distance d. This code uses a rotated 2D square lattice patch 102 of qubits, which is then used as the substrate for the second layer of the code. Multi-qubit operations occur using the surface code bus 103 / 104. The distance d is chosen to be as small as possible to provide sufficient error reduction in the second level code as described above. In one example, the first level code reduces the error rate to 10 -5 From 10 -7 Reduce to. 2. A second level code that provides qubits with the required error rate of the final logical qubit. This code may be a block code. The surface code bus 103 / 104 provides a method of long-distance interaction that allows any block code to be implemented without moving the qubits to enable the interaction. In one example, the error rate applying the second level code is 10 -9 is less than.

[0038] If the level 2 code is a singly concatenated [[7,1,3]] Steane code with a base layer of distance 11, the logical error rate is 10 -15 It may be better than.

[0039] Surface cord layer In one example, the first level code is implemented using a collection of rotated surface code patches at a distance d, which are adjacent on at least two edge segments to a surface code bus 103 / 104. This bus in some implementations may be implemented by a folded surface code bus as shown in Figure 1, with an inter-qubit bus 103 and a main bus 104, collectively referred to as the "bus." Patches 102 are the first layer of logical qubits, or L1, which is then used as the substrate for the second layer.

[0040] Rotating surface codes operate on a square lattice of qubits similar to Figure 2. In this figure, open circles are data qubits and filled circles are measurement auxiliary qubits (auxiliaries), representing pairs of qubits that can interact directly. Figure 3 shows an example layout of a stabilizer code, with hatched areas representing the Z stabilizer for the data qubit at that corner and unhatched areas representing the X stabilizer for the data qubit at that corner. Logical operators are represented by strings that span from one boundary to another. The distance of a surface code is the number of data qubits on the shortest path between two matching edges. These patches are represented as squares with marked edges (by convention, smooth edges are z-edges and rough edges are x-edges), as in Figures 4a, 4b, and 5, where rough edges are indicated by diagonals. Patches can be squares or other larger shapes, and patches can contain a single qubit or, if larger, multiple qubits. For example, Figure 4a shows a square patch containing one qubit, Figure 4b shows a larger patch (double length) containing one qubit, and Figure 5 shows a larger patch (double length) containing two qubits, "1" and "2."

[0041] Single-qubit Clifford operations in the base layer proceed via edge tracking, while two-qubit operations are performed using adaptive two-qubit parity measurements and corrections, with the possibility of adding logic auxiliary systems. Because the bus can perform these parity measurements fault-tolerantly at any distance, entanglement operations (including CNOT gates) can also be performed at any distance.

[0042] Individual surface code patches 102 are connected together by qubit buses 103 / 104. The qubit buses can be thought of as extensions of the surface code that are similar to the encoded qubit patches 102 but do not encode any information. For example, the bus itself has a fixed width of 5 qubits and extends as long as necessary to connect the encoded qubit regions. The buses are connected to the logical qubit patches by measuring coupling operators along their boundaries, which temporarily "connect" the bus to the interacting logical qubits. This connection is maintained for multiple cycles of the surface code error correction (a number of cycles equal to the distance d of the underlying code). This is called a merge operation.

[0043] Once the merge operation is complete, qubits along the boundary where the bus connects to the logical qubit patch are measured. This disconnects the bus from each logical qubit patch and is called a split operation. The combination of merge and split completes a logic gate between the bused patches. The bus can facilitate interaction between any number of logical patches.

[0044] Figure 6 shows an example where square patches of size d qubits are in an array (also called a "module") and connected by a bus of width w qubits in a linear array of patches of constant width w+d, such as one rough edge and one smooth edge of each patch, with enough additional qubits to connect to qubit bus 103.

[0045] Figure 7 shows another example of a linear array of patches where the bus width remains w qubits but is twice as long, i.e., 2d qubits long. Note that in the example of Figure 7, the patches have a rough and smooth bottom boundary on the bus; that is, the bus connects to only one side of the boundary. The gaps between qubits are only small, sometimes only one lattice period, to allow logical qubits to be separated and distinguishable.

[0046] Figure 8 shows a more complex example where the bus branches to connect further patches. Here, a first set of patches A1-An are arranged as a first linear subarray 801, and a second set of patches B1-Bn are arranged as a second linear subarray 802 perpendicular to the first linear subarray. Note that the bus has a width w across the entire structure. Potentially, multiple further subarrays arranged perpendicular or at different angles at some branching points can be used to enable a range of different structures. Note again that each subarray can represent the output of a level 2 code and an ancillary qubit, as described above.

[0047] The patches may be close to each other in a continuous rectangle, as shown for four patches in Figure 1, or they may be spaced apart with long spans of buses only between them to spread out the densely packed area of ​​qubits. They may be connected in a line, or there may be a more elaborate branching pattern that is better suited to higher-layer coding structures or algorithms. Advantageously, there is sufficient space around the patches and buses for qubit driving circuitry or equipment, etc., and the distance from any internal qubits and boundaries is below the required limit.

[0048] The first level code converts the physical qubit error rate into a logical error rate that is sufficiently low for the second level code. phys =10 -3 If , the logical error rate of the surface code patch at distance d is

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[0049] Second-level block code To achieve the computational fidelity required for the final calculation, a second-level quantum error-correcting code is implemented using the logical qubits (i.e., patches) of the first-level (L1) surface code as a substrate without further increasing the patch width. The bus architecture allows the long-range gates to be performed natively using long-range parity measurements and several additional auxiliary systems (one per parallel CNOT gate). Figure 9 shows the parity measurement gadget that can be used, a Pauli measurement CNOT gadget.

[0050] This second level code may be any suitable quantum code, such as a block-based quantum error correcting code, which is advantageous given the availability of long-range gates and the parity measurements provided by the L1 code substrate. Examples of codes that may be used are the [[5,1,3]] Shor code, the [[7,1,3]] Steane code, the [[15,7,3]] Hamming code, or any of the various quantum low-density product codes (LDPC).

[0051] Control circuit Some examples disclosed above utilize codes and other quantum algorithms that include quantum operations. These operations are typically controlled by external control circuitry, such as electron spin resonance (ESR) lines, or radiation sources such as microwaves or light sources, or metal pads or lines for static fields, that provide control pulses and fields to the qubits. A classical computer calculates the pulses and other control and readout signals that result in the desired quantum code and operation. Thus, the classical computer includes a processor and memory and executes software instructions stored on a non-volatile computer-readable medium that cause the computer to perform the methods described herein. The classical computer is optionally connected to the quantum processor 100 via a signal generator so that it can control the quantum processor by applying first and second error correction methods to the qubits.

[0052] How quantum processors work 11 illustrates a method 1100 of operating quantum processor 100. As described above, the quantum processor includes multiple patches of digital qubits and a quantum bus of digital qubits. The quantum bus connects the multiple patches of digital qubits and transmits quantum information that constitutes long-range interactions between the patches of digital qubits. In one example, the method is performed by a classical processor in a classical computer executing a software program.

[0053] In that sense, the processor applies a first error correction method to each of the patches connected by the bus to reduce the relatively high error rate of the digital qubits to a relatively low error rate for each patch, at 1101. As explained above, this may include a surface code applied to each patch to reduce the natural error rate of the physical qubits to a reduced error rate for the logical qubits formed by the patch.

[0054] Additionally, the processor applies a second error correction method to the multiple patches to correct for relatively low error rates, which may include a block code, such as a Steane code, that operates on logical qubits rather than physical qubits to correct for remaining error rates from the surface code.

[0055] The first and second error correction methods may be performed sequentially or simultaneously, either by applying the same method to all patches or by applying the first method to some patches and the second method to other patches.

[0056] How to make a quantum processor 12 shows a method 1200 of fabricating quantum processor 100. Method 1200 includes, at 1201, creating a plurality of patches of digital qubits to form a first array of multiple patches. In this context, "creating" may relate to creating a physical device, such as fabricating qubits, including, for example, creating a crystal structure, implanting dopant atoms, and depositing metal wires. However, "creating" may equally relate to creating a digital representation of what is to be created, such as a digital mask layout of the structure to be fabricated, or creating a higher-level and / or more abstract representation of the device, as shown in FIG. 1.

[0057] Method 1200 further includes, at 1202, connecting a plurality of patches of the first array by a quantum bus of digital qubits. The quantum bus is configured to connect the plurality of patches of digital qubits and transmit quantum information constituting long-range interactions between the patches of digital qubits. In that sense, method 1200 may further include configuring the quantum bus to connect the plurality of patches of digital qubits and transmit quantum information constituting long-range interactions between the patches of digital qubits.

[0058] Further, method 1200 includes, at 1203, creating multiple additional arrays. These additional arrays have the same number of patches as the first array, meaning that adding additional arrays only affects one dimension of the quantum processor. In other words, the width of the quantum processor remains constant as additional arrays are added. This is a significant advantage in ease of manufacturing, as it allows for wiring of all qubits. The number of arrays may depend on the error rate required for a particular application. In that sense, by lengthening quantum processor 100 while keeping the width constant, nearly any error rate reduction can be achieved. Because each array provides sufficient space for its own wiring, adding additional arrays does not exacerbate the wiring problem.

[0059] The next step in method 1200 is to connect multiple additional arrays to the first array by a quantum bus, at 1204, for example, by extending the main bus 104 shown in FIG. 1 . Finally, method 1200 includes creating a control circuit, at 1205. The control circuit controls the quantum processor with a first error correction method at each patch connected by the bus, thereby reducing a relatively high error rate of the digital qubits to a relatively low error rate for each patch. The control circuit further controls the quantum processor with a second error correction method for the multiple patches to correct the relatively low error rate. The control circuit may include ESR lines or other interconnects and controls. The control circuit may further include a signal generator or driver and a classical computer that calculates control pulses to implement the first and second error control methods.

[0060] Note that quantum processor 100 may be implemented in silicon and may be implemented on the same silicon die as a classical processor, such as an ARM processor core. In that sense, quantum processor 100 constitutes a hardware augmentation or hardware accelerator, performing calculations that are virtually impossible for a classical computer to perform due to their complexity in the classical setting.

[0061] result Simulations are performed on the Steane code implemented on this board using a flag qubit-based fault-tolerant implementation. The measured error rate results are shown in the graph in Figure 10. An estimate of the logic error rate after one level of this implementation of Steane is:

[0062]

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[0063]

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[0064] Further grid width reduction with highly asymmetric low-level surface codes. In some of the above examples, the surface code is defined by a square patch of qubits 2d-1 wide and 2d-1 deep, where d is the distance of the code itself. In these examples, each dimension serves to correct bit-flip and phase-flip errors separately. Logical errors in planar surface codes arise when physical errors in the constituent qubits create chains that traverse the lattice from left to right or from top to bottom. Which chains cause logical bit errors and which chains cause logical phase errors are defined with respect to the orientation of the stabilizers in the lattice.

[0065] Since the number of physical qubits in the horizontal dimension of the lattice (2d-1) is the same as the number of vertical dimensions of the lattice (2d-1) for square planar codes, the error correction capabilities for bit and phase errors are identical and are specified by d.

[0066] However, in other examples, the planar surface code becomes asymmetric by choosing two new distances \(d_x\) and \(d_z\) such that the dimensions of the physical lattice are currently \((W)\text{idth} \times (D)\text{epth}=(2d_x - 1)\times(2d_z - 1)\). The logical chain operator defining the bit flip is assumed to span the width of the lattice. The asymmetric lattice becomes more vulnerable to certain types of errors than others. If \(d_x < d_z\), the code has a lower ability to tolerate logical bit flips, and conversely if \(d_x>d_z\), the code has a lower ability to tolerate phase errors.

[0067] Figure 13 shows a rectangular planar surface code with \(d_z = 3\) and \(d_x = 7\), including an array of physical qubits with depth 13 and width 5. The quantum circuits used to extract the two types of stabilizer operators are also shown in Figures 14 and 15 respectively. These circuits are the same as in the case of the square planar surface code.

[0068] In one example, the quantum processor, in the case of Figure 13, includes a long and thin rectangular surface code designed to minimize the width of the physical array while providing a minimum amount of error correction for phase \((X)\) flips. The other dimensions are designed to significantly suppress one type of error. In Figure 13, bit \((Z)\) flips are significantly suppressed, while in other examples, the surface code significantly suppresses phase flips. In this architecture, since the length of the physical array of qubits is not a constraint, the encoded patch can have a very large value of \(d_z\) that is large enough to create a very large error bias at the logically encoded level.

[0069] The proposed architecture uses an asymmetric surface code structure to artificially create an error bias in the logical layer, and the architecture exploits it using a simpler error-correction code structure. The physical error rate of each constituent qubit is below the fault-tolerant threshold of the surface code and can be considered balanced (physical X errors are as likely to occur as physical Z errors). For the logical qubits, logical Z errors are virtually nonexistent, and logical X errors are only slightly suppressed. Once this is done, it becomes possible to effectively concatenate a classical iteration code on top of the logical surface code, designed to correct the now very dominant X errors. In other words, the first error-correction method described above is now an asymmetric surface code, and the second error-correction method is an iteration code.

[0070] Repetition codes can correct for either bit-flip errors or phase-flip errors (although they cannot simultaneously correct them, so they are not perfect quantum codes).

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[0071] Between each logical qubit in the repetition code, an auxiliary system is used to compare the bit value between qubit (j) and (j+1). If an error occurs, this measured parity will be odd.

[0072] With this adjacent code, syndrome extraction of the iterative code can be executed very fast and can be executed in a fixed time regardless of the code distance of the iterative code. This fast syndrome extraction and high distance mean that the threshold of the code is very high (~50%). However, the code cannot correct both types of errors simultaneously. Other classical codes may be used.

[0073] The new microarchitecture structure utilizes these two independent characteristics to enable a very small, physically fixed-width array that can effectively implement fault-tolerant error correction.

[0074] The physical layer of qubits is arranged in a collection of rectangular patches encoded with a (d_x << d_z) surface code. In one example of the technology, the minimum executable width is d_x = 3, which corresponds to the physical width of a lattice of 5 physical qubits.

[0075] The length of the array is assumed to be arbitrary, and these rectangular surface plane code patches can be "encoded" by the computational algorithm as many as needed.

[0076] On top of this surface code layer, the quantum processor executes encoding into the iterative code. To enable the quantum processor to perform fault-tolerant error correction in a second layer, the total width of the array is doubled, so that two planar surface codes are arranged in the vertical direction of the lattice. This is used to make this second row or planar surface code identical (with respect to the error correction of the underlying planar code) and physically interactable along the long boundary of the rectangular surface code. Thus, the minimum width used in this example is 5 + 5 + 1 physical qubits. The width of each rectangular planar surface code is 5 physical qubits, and an additional 1 physical qubit serves as a spacer between the two logically encoded blocks. Also, the width of the entire array is assumed to be arbitrarily long.

[0077] Error correction at the top layer of the code uses a series of lattice surgery-enabled logic operations between the top row and the second auxiliary row of the planar surface code patch. This series of operations is shown in Figure 17.

[0078] In step 1, each of the rectangular logical qubits in the repetition code is expanded into the physical space of the qubits in row 2. This simply doubles the error correction strength from d_x=3 to d_x=6.

[0079] In step 2, the quantum processor performs a Lattice surgery splitting operation, which generates an entangled state between two separate rectangular surface code patches, each of which now reduces to a d_x=3 planar surface code.

[0080] In step 3, the quantum processor merges the operations between the ancillary qubits along the width, which now store information related to the pairwise logical Z parity of the data qubits. The planar surface code qubits in the second row now encode the syndrome information in the iterative code.

[0081] Next, in step 4, we measure each of these auxiliary planar surface code qubits by measuring all of their physical constituent qubits. Measuring these patches yields classical syndrome information of logical parity Z(j)Z(j+1).

[0082] Because the repetition code uses measurements of all pairwise operations, this first block measures the non-overlapping pairs Z(1)Z(2) and Z(3)Z(4), etc. The quantum processor now repeats the sequence again with adjacent non-overlapping repetition code qubits Z(2)Z(3), Z(4)Z(5), etc. This completes the party check of the repetition code.

[0083] If the physical error rate is below the fault-tolerant threshold of the surface code (about 0.6%), the underlying surface code layer will produce a logical Z error rate << 1, but a logical X error rate of only > 0.6% (asymmetric codes effectively eliminate one type of quantum error but slightly amplify the other type).

[0084] The initialization of the higher level repeat code simply prepares all planar surface code patches to a logic 0 state, which automatically creates a logic 0 state at the repeat code level.

[0085] The repeat code layer acts as a repeat code, filtering out any X errors that remain uncorrected from the surface code layer, allowing effective quantum error correction for both types of errors (X and Z) at the top logic layer while maintaining the small, fixed width of the entire array required for the microarchitecture.

[0086] It will be appreciated by those skilled in the art that many changes and / or modifications may be made to the above-described embodiments without departing from the broad general scope of the present disclosure, and the present embodiments are therefore considered in all respects to be illustrative and not restrictive.

Claims

1. 1. A quantum processor, comprising: multiple patches of digital qubits; a quantum bus of digital qubits connecting a plurality of patches of said digital qubits and configured to transmit quantum information constituting interactions between digital qubits of different patches; a control circuit that performs the first error correction method and the second error correction method; the quantum processor is controlled by the first error correction method for each of the patches connected by the bus to reduce a qubit error rate of the digital qubit to a patch error rate of each patch, and the second error correction method using the patches as logical qubits to correct the patch error rate, the qubit error rate being higher than the patch error rate, and the second error correction method being different from the first error correction method.

2. The quantum processor of claim 1 , wherein the quantum bus has qubits of constant width.

3. 3. The quantum processor of claim 1, wherein the plurality of patches form a plurality of arrays of patches each connected by the quantum bus.

4. The quantum processor of claim 3 , wherein the plurality of arrays are linear arrays.

5. The quantum processor of claim 4 , wherein each linear array has the same width.

6. 6. The quantum processor of claim 5, wherein each linear array has an array width defined by one of the plurality of patches and the quantum bus, the array width being 15 qubits or 20 qubits.

7. 7. The quantum processor of claim 4, wherein each linear array has an array length defined by a plurality of the plurality of patches and the quantum bus, the array length being 120 qubits or 160 qubits.

8. 8. The quantum processor of claim 1, further comprising areas between the patches that include connections of the patches to the digital qubits.

9. 9. A quantum processor according to claim 1, wherein the digital qubits of the bus are controlled by the first error correction method.

10. The quantum processor of claim 1 , wherein the first error correction method comprises a surface code.

11. 11. The quantum processor of claim 1, wherein the second error correction method comprises a block code.

12. The quantum processor of claim 11 , wherein the block code comprises a Steane code.

13. The patch error rate is 10 －５ 13. The quantum processor of claim 1, wherein the quantum number is less than 1.

14. The patch error rate is 10 －８ 14. The quantum processor of claim 1 , wherein the quantum processor has a capacitance greater than 100 Ω.

15. When the patch error rate is corrected, the corrected error rate is 10 －９ 15. The quantum processor of claim 1, wherein:

16. 16. A quantum processor according to any one of claims 1 to 15, wherein the patches are square.

17. 16. The quantum processor of claim 1, wherein the patch is rectangular and has a first dimension that is greater than a second dimension to reduce an error rate of a first type of error associated with the first dimension to an error rate that is lower than an error rate of a second type of error associated with the second dimension.

18. 18. The quantum processor of claim 17, wherein the first error correction method is an asymmetric surface code for reducing the error rate of the first type of error to an error rate that is lower than the error rate of the second type of error.

19. 20. The quantum processor of claim 18, wherein the second error correction method is a repetition code that reduces the error rate of the second type of error.

20. 20. The quantum processor of claim 17, wherein the second error correction method reduces the error rate of only the second type of error.

21. 21. The quantum processor of claim 17, wherein the first type of error is one of a bit flip error and a phase flip error, and the second type of error is another one of a bit flip error and a phase flip error.

22. 1. A method of operating a quantum processor, the quantum processor including a plurality of patches of digital qubits and a quantum bus of digital qubits connecting the plurality of patches of digital qubits and configured to transmit quantum information configuring interactions between digital qubits in different patches, the method comprising: applying a first error correction method to each of the patches connected by the bus to reduce a qubit error rate of the digital qubits to a patch error rate of each patch, the qubit error rate being higher than the patch error rate; applying a second error correction method using the plurality of patches as logical qubits to correct the patch error rate, the second error correction method being different from the first error correction method; The method, wherein the first error correction method and the second error correction method are performed by a control circuit.

23. 1. A method of manufacturing a quantum processor, comprising: creating a plurality of patches of digital qubits to form a first array of the plurality of patches; connecting the plurality of patches of the first array by a quantum bus of digital qubits configured to connect the plurality of patches of digital qubits and to transmit quantum information configuring interactions between digital qubits in different patches; creating a plurality of further arrays having the same number of patches as the first array; connecting the plurality of further arrays to the first array by the quantum bus; creating control circuitry to control the quantum processor with a first error correction method for each of the patches connected by the bus to reduce a qubit error rate of the digital qubit to a patch error rate of each patch, and a second error correction method using the patches as logical qubits to correct the patch error rate, wherein the qubit error rate is higher than the patch error rate and the second error correction method is different from the first error correction method.

24. 24. The method of claim 23, wherein the number of the plurality of further arrays is based on an error rate sufficient for operation of the quantum processor after correction for the patch error rate.

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