Gate driver and display device using the same

Abstract

To provide a gate drive unit making it possible to diminish the size of a buffer transistor.SOLUTION: A gate drive unit includes plural signal transmission blocks that are cascaded. An n-th (where n denotes a positive integer) signal transmission block includes a first output section that outputs a carry signal to a first output node according to a voltage at a first control node which pulls up an output voltage, and a voltage at a second control node which pulls down the output voltage, a second output section that outputs a boosting carry signal to a second output node according to the voltage at the first control node and the voltage at the second control node, and a third output section that outputs a gate signal to a third output node according to the voltage at the first control node and the voltage at the second control node. Further, the n-th signal transmission block includes a pull-up transistor that applies a high gate voltage to the second output node, a pull-down transistor that applies a low gate voltage to the second output node, and a first capacitor coupled between a gate of the pull-up transistor and the second output node.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a gate driver and a display device using the same. [Background technology]

[0002] The display devices include a liquid crystal display (LCD), an electroluminescence display (ELD), a field emission display (FED), a plasma display panel (PDP), and the like.

[0003] Electroluminescent displays are divided into inorganic light-emitting displays and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays reproduce input images using self-emitting elements, such as organic light-emitting diodes (OLEDs). Organic light-emitting displays have the advantages of fast response speed, luminous efficiency, brightness, and a wide viewing angle.

[0004] Some display devices, such as liquid crystal display devices and organic light emitting display devices, include a display panel including a plurality of subpixels, a driver that outputs drive signals for driving the display panel, and a power supplier that generates power to be supplied to the display panel or the driver, etc. The driver includes a gate driver that supplies gate signals such as scan signals and light emission control signals to the display panel, and a data driver that supplies data signals to the display panel.

[0005] Such a display device can display an image by transmitting light or directly emitting light when drive signals, such as gate signals and data signals, are supplied to a plurality of sub-pixels formed on a display panel.

[0006] At this time, the gate driver boosts the Q node with the output gate signal. However, as the buffer transistor deteriorates, the rising speed of the output gate signal slows down, which in turn slows down the boosting speed of the Q node, causing a vicious cycle that further slows down the rising speed of the gate signal, resulting in a significant degradation of output performance.

[0007] To overcome this problem, there is a method of changing the size of the buffer transistor, but this method also has the problem of requiring the buffer transistor to be designed to be large in size. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention is directed to solving the needs and / or problems mentioned above.

[0009] The present invention provides a gate driver and a display device using the same.

[0010] The objects of the present invention are not limited to those mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] A gate driver according to an embodiment of the present invention includes a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a previous signal transmission unit, and the nth (n is a positive integer) signal transmission unit includes: a first output unit that outputs a carry signal to a first output node in response to voltages of a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; a second output unit that outputs a carry signal for boosting to a second output node in response to voltages of the first control node and the second control node; and a third output unit that outputs a gate signal to a third output node in response to voltages of the first control node and the second control node, and the second output unit includes a pull-up transistor that applies a gate high voltage to the second output node in response to a charging voltage of the first control node; a pull-down transistor that applies a gate low voltage to the second output node in response to a charging voltage of the second control node; and a first capacitor connected between a gate of the pull-up transistor and the second output node.

[0012] A gate driver according to an embodiment of the present invention includes a plurality of signal transmission units cascaded via a carry line to which a carry signal is applied from a previous signal transmission unit, and the nth (n is a positive integer) signal transmission unit includes a first output unit outputting a carry signal to a first output node in response to voltages of a first control node for pulling up an output voltage and a second control node for pulling down the output voltage; and a second output unit outputting a gate signal to a second output node in response to voltages of the first control node and the second control node, and the first output unit may include a pull-up transistor applying a gate high voltage to the first output node in response to a charging voltage of the first control node; a pull-down transistor applying a gate low voltage to the first output node in response to a charging voltage of the second control node; a first capacitor connected between a gate of the pull-up transistor and the first output node; and a second capacitor connected between the first output node and a low potential voltage line.

[0013] In the present invention, a capacitor is connected to the output node where the carry signal is output, but by connecting capacitors between the gate electrode of the pull-up transistor and the output node and between the output node and the low potential voltage line, the rising speed of the gate signal does not slow down even if the pull-up transistor that outputs the gate signal deteriorates, thereby improving the output characteristics.

[0014] In the present invention, since capacitors are connected between the gate electrode of the pull-up transistor and the output node and between the output node and the low potential voltage line, respectively, output loss of the carry signal can be reduced.

[0015] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram illustrating a display device according to an embodiment of the present invention. [Figure 2] 2 is a diagram showing the layout structure of the pixel array shown in FIG. 1; [Figure 3] 2 is a diagram illustrating a gate driver according to an embodiment of the present invention; [Figure 4] 1 is a diagram showing a gate driver according to a first embodiment of the present invention. [Figure 5] 5 is a waveform diagram showing input / output signals and voltages of control nodes of the gate driver shown in FIG. 4. [Figure 6a] 10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 6b] 10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 6c] 10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 6d] 10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 6e]10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 6f] 10 is a diagram for comparing and explaining boosting performance between an example and a comparative example. [Figure 7a] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 7b] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 7c] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 7d] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 7e] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 7f] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 8a] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 8b] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 8c] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 8d] 10 is a diagram for explaining and comparing output characteristics of an example and a comparative example. [Figure 9] 10 is a diagram showing a gate driver according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] The advantages and features of the present invention, as well as methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. However, the present invention is only defined by the scope of the claims, and the present invention is not limited to the embodiments disclosed below.

[0018] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. Furthermore, in the description of the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0019] When the terms "comprise," "have," "consist of," etc. are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it also includes the plural unless otherwise expressly stated.

[0020] In interpreting elements, it is understood that a margin of error is included even if there is no other explicit description.

[0021] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0022] In the description of the embodiments, terms such as "first," "second," etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of the present invention.

[0023] Like reference numbers refer to like elements throughout the specification.

[0024] The features of the various embodiments may be partially or fully combined or combined with each other, and various technical linkages and operations may be possible, and each embodiment may be implemented independently of the others, or may be implemented together in a linked relationship.

[0025] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the display panel shown in FIG.

[0027] Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply unit 140 for generating power required to drive the pixels and the display panel driving circuit.

[0028] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix.

[0029] The pixel array AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel line share a gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period (1H) is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0030] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a separate touch sensor or through a pixel. The touch sensor may be an on-cell type or an add-on type disposed on the screen of the display panel, or may be an in-cell type touch sensor incorporated into the pixel array AA.

[0031] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be manufactured using a plastic EL panel. An organic thin film may be disposed on a back plate of the plastic EL panel, and a pixel array AA may be formed on the organic thin film.

[0032] The back plate of the plastic EL may be a PET (Polyethylene terephthalate) substrate. An organic thin film may be formed on the back plate. A pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture so that the pixel array AA is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multi-layer buffer film made of an insulating material (not shown) may be formed on the organic thin film. The pixel array AA and wiring for supplying power and signals to the touch sensor array may be formed on the organic thin film.

[0033] Each pixel may be divided into a red subpixel (hereinafter referred to as an "R subpixel"), a green subpixel (hereinafter referred to as a "G subpixel"), and a blue subpixel (hereinafter referred to as a "B subpixel") for color implementation. Each pixel may further include a white subpixel. Each subpixel 101 includes a pixel circuit. The pixel circuit is connected to a data line 102 and a gate line 103.

[0034] In the following, pixel may be construed as being synonymous with subpixel.

[0035] As shown in FIG. 2, the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10, when viewed from a cross-sectional view.

[0036] The circuit layer 12 may include pixel circuits connected to wiring such as data lines, gate lines, and power lines, a gate driver GIP connected to the gate lines, a demultiplexer array 112, and a circuit for auto-probe testing (not shown). The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by insulating layers, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as oxide TFTs including n-channel oxide semiconductors.

[0037] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered with a protective layer including an organic film and a protective film.

[0038] The encapsulation layer 16 covers the light emitting device layer 14 to seal the circuit layer 12 and the light emitting device layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the path for moisture and oxygen to travel is longer than in a single layer, and the penetration of moisture and oxygen that affects the light emitting device layer 14 can be effectively blocked.

[0039] A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form a capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer may convert the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12 to improve visibility and contrast ratio. The polarizer may be embodied as a polarizer in which a linear polarizer and a phase delay film are bonded, or a circular polarizer. A cover glass may be attached to the polarizer.

[0040] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer absorbs some of the wavelengths of light reflected from the circuit layer and the touch sensor layer, replacing the polarizer and improving color purity. In this embodiment, a color filter layer 20 with higher light transmittance than a polarizer is applied to the display panel to improve the light transmittance of the display panel PNL and improve the thickness and flexibility of the display panel PNL. A cover glass may be bonded onto the color filter layer.

[0041] The power supply unit 140 uses a DC-DC converter to generate DC power required to drive the pixel array AA and the display panel driving circuit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 adjusts the DC input voltage from a host system (not shown) to generate DC voltages such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, a pixel driving voltage EVDD, and a pixel low-potential power supply voltage EVSS. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driver 120. The pixel driving voltage EVDD and the pixel low-potential power supply voltage EVSS are commonly supplied to the pixels.

[0042] The display panel driver circuit writes pixel data (digital data) of an input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0043] The display panel driving circuit includes a data driver 110 and a gate driver 120 .

[0044] A demultiplexer (DEMUX) array 112 may be disposed between the data driver 110 and the data lines 102. The demultiplexer array 112 sequentially connects one channel of the data driver 110 to a plurality of data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 may be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0045] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in Fig. 1. In a mobile device, the timing controller 130, power supply unit 140, data driving unit 110, etc. may be integrated into a single drive IC (Integrated Circuit).

[0046] The data driver 110 uses a DAC (Digital to Analog Converter) to convert pixel data of an input image received from the timing controller 130 into a gamma compensation voltage every frame period to generate a data voltage Vdata. The gamma reference voltage VGMA is divided by a voltage divider circuit for each gray scale. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer AMP.

[0047] The output buffer AMP included in one channel of the data driver 110 may be connected to adjacent data lines 102 through a demultiplexer array 112. The demultiplexer array 112 may be formed directly on the substrate of the display panel 100 or may be integrated with the data driver 110 into one drive IC.

[0048] The gate driver 120 may be implemented as a GIP (Gate in Panel) circuit formed directly on a bezel (BZ) of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the signals to the gate lines 103 by shifting the gate signals using a shift register.

[0049] The gate signal may include a scan signal for selecting pixels of a line to which data is written in synchronization with the data voltage, and an EM signal for defining the light emission time of pixels charged with the data voltage.

[0050] The gate driver 120 may include a scan driver 121 and an EM driver 122 .

[0051] The scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from the timing controller 130, and shifts the scan signal SCAN in accordance with the shift clock timing. The EM driver 122 outputs an EM signal EM in response to the start pulse and the shift clock from the timing controller 130, and sequentially shifts the EM signal EM according to the shift clock. Therefore, the scan signal SCAN and the EM signal EM are sequentially supplied to the gate lines 103 of the pixel lines L1 to Ln. In the case of a model without a bezel, at least some of the transistors constituting the gate driver 120 and clock wiring may be distributed within the pixel array AA.

[0052] The timing controller 130 receives digital video data (DATA) of input images from a host system (not shown) and timing signals synchronized therewith. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, and a data enable signal (Data Enable, DE). The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted because the vertical and horizontal periods can be determined by counting the data enable signal DE. The data enable signal DE has a period of one horizontal period (1H).

[0053] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a vehicle system, and a mobile device system.

[0054] The timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driving circuit at an input frame frequency of XI Hz (i is a positive integer greater than 0). The input frame frequency is 60 Hz for the NTSC (National Television Standards Committee) system and 50 Hz for the PAL (Phase-Alternating Line) system.

[0055] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a MUX signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on timing signals (Vsync, Hsync, DE) received from the host system.

[0056] The voltage levels of the gate timing control signals output from the timing controller 130 may be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level shifter (not shown) and supplied to the gate driver 120. That is, the level shifter converts the low level voltage of the gate timing control signals into gate low voltages VGL and VEL, and converts the high level voltage of the gate timing control signals into gate high voltages VGH and VEH. The gate timing control signals include a start pulse and a shift clock.

[0057] FIG. 3 is a diagram illustrating a gate driver according to an embodiment of the present invention.

[0058] Referring to FIG. 3, the gate driver according to the embodiment includes a plurality of signal processing units (.., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ..) cascaded via a carry line (CL) through which a carry signal is transmitted.

[0059] Each of the signal processing units (ST1,..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2),...) receives a start pulse Vst or a carry signal (C1,..., C(n-3), C(n-2), C(n-1), C(n), C(n+1),...) output from the previous signal processing unit, and also receives a shift clock CLK. The first signal processing unit (ST1) (not shown) begins to operate in response to the start pulse Vst, and the other signal processing units (..., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2),...) begin to operate in response to a carry signal (..., C(n-3), C(n-2), C(n-1), C(n), C(n+1),...) input from the previous signal processing unit.

[0060] Each of the multiple signal transmission units (.., ST(n-2), ST(n-1), ST(n), ST(n+1), ST(n+2), ..) configured in this manner can generate an output signal [EMOUT(n)] using the clock signal CLK.

[0061] Figure 4 is a diagram showing a gate driver according to a first embodiment of the present invention. Figure 5 is a waveform diagram showing input / output signals and control node voltages of the gate driver shown in Figure 4. Here, an example in which the gate driver is implemented as an EM driver will be described.

[0062] 4 and 5, the gate driver 122 according to the first embodiment of the present invention may include a first control node (hereinafter referred to as the "Q node") that pulls up the output voltage, a second control node (hereinafter referred to as the "Qb node") that pulls down the output voltage, a first circuit unit 122-1, a second circuit unit 122-2, a first output unit 122-3, and a second output unit 122-4.

[0063] The first circuit unit 122-1 controls the charging and discharging of the Q node Q. When the shift clock CLK1 is at a high voltage VGH2 that is greater than or equal to the gate-on voltage VEH, the first circuit unit 122-1 supplies the voltage of the (n-1)th carry signal C(n-1) from the (n-1)th signal processing unit ST(n-1), which is the previous signal processing unit, to the Q node Q(n), thereby charging the Q node Q(n). The first circuit unit 122-1 includes a plurality of transistors T1, T1A, and T3q.

[0064] When the shift clock CLK1 is at a high voltage VGH2 that is greater than or equal to the gate-on voltage VEH, the first transistor T1 is turned on to supply the voltage of the carry signal C(n-1) to the Qh node Qh. The first transistor T1 includes a gate to which the shift clock CLK1 is applied, a first electrode connected to the (N-1)th carry signal line C(n-1), and a second electrode connected to the Qh node Qh.

[0065] The high voltage VGH2 of the shift clock CLK1 may be set to a voltage lower than the second high voltage VGH1. The high voltage VGH1 of the carry signal C(n-1) and the first gate signal EMOUT(n) is the same voltage as the second high voltage VGH1. If the high voltage VGH2 of the shift clock CLK1 is set to be lower than the second high voltage VGH1, when the threshold voltage Vth of the first transistor T1 is shifted to a negative polarity (-Vth) during charging of the Q node Q(n), the Q node Q(n) may float, thereby improving the voltage boosting of the Q node Q(n).

[0066] When the shift clock CLK1 is at a voltage VGH2 greater than or equal to the gate-on voltage VEH, the first A transistor T1A is turned on to supply the voltage of the Qh node Qh to the Q node Q(n), thereby charging or discharging the Q node Q(n). The first A transistor T1A includes a gate to which the shift clock CLK1 is applied, a first electrode connected to the Qh node Qh, and a second electrode connected to the Q node Q(n).

[0067] At this time, the plurality of transistors T1 and T1A are connected in series between the (N-1)th carry signal line C(n-1) and the Qh node Qh.

[0068] The third q transistor T3q is turned on when the Q node Q(n) is charged and supplies a second high voltage to the Qh node Qh through the second high voltage line GVDD1. The second high voltage GVDD1 is supplied to the Qh node Qh through the second high voltage line GVDD1. The third q transistor T3q has a gate connected to the Q node Q(n), a first electrode connected to the second high voltage line GVDD1, and a second electrode connected to the Qh node Qh.

[0069] The second circuit unit 122-2 includes an inverter circuit that inverts the voltage of the Q node Q(n) and applies it to the Qb node Qb(n). The inverter circuit of the second circuit unit 122-2 includes a Qb node charging unit and a Qb node discharging unit.

[0070] The Qb node charging unit includes a plurality of transistors T4 and T41, and the Qb node discharging unit includes a plurality of transistors T4q and T5q, which are connected in series.

[0071] The Qb node charging unit switches the current path between the second high potential voltage line GVDD1 and the Qb node Qb(n) according to the voltage of the (n-1)th Qb node Qb(n-1) from the (n-1)th signal transmission unit ST(n-1).

[0072] The fourth transistor T4 is turned on when the voltage at the first node n1 is a high voltage equal to or greater than the gate-on voltage VEH, and connects the second high-potential voltage line GVDD1 to the Qb node Qb(n), thereby charging the Qb node Qb(n) to a high voltage equal to or greater than the gate-on voltage VEH. The fourth transistor T4 has a gate connected to the first node n1, a first electrode connected to the second high-potential voltage line GVDD1, and a second electrode connected to the Qb node Qb(n). The third capacitor C3 is connected between the gate and the second electrode of the fourth transistor T4. The third capacitor C3 allows the voltage at the first node n1 to be boosted when the fourth transistor T4 is turned on.

[0073] The 41st transistor T41 is turned on when the voltage at the (n-1)th Qb node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1) is a high voltage equal to or higher than the gate-on voltage VEH, and supplies the second high potential voltage GVDD1 to the first node n1, thereby charging the first node n1 to a voltage equal to or higher than the gate-on voltage VEH. The 41st transistor T41 includes a gate connected to the (n-1)th Qb node (Qb(N-1)) of the (n-1)th signal transmission unit ST(n-1), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the first node n1.

[0074] The Qb node discharge unit is turned on to discharge the Qb node Qb(n) when the voltage of the Qh node Qh is a high voltage higher than the gate high voltage VEH.

[0075] The fourth q transistor T4q is turned on when the voltage at the Qh node Qh is a high voltage equal to or higher than the gate-on voltage VEH, connecting the first node n1 to the Qb node Qb(n). The fourth q transistor T4q includes a first electrode connected to the first node n1, a gate electrode connected to the Qh node Qh, and a second electrode connected to the Qb node Qb(n).

[0076] The fifth q transistor T5q is turned on when the voltage of the Qh node Qh is a high voltage equal to or higher than the gate-on voltage VEH, and connects the Qb node Qb(n) to the second low voltage line GVSS1, thereby discharging the voltage of the Qb node Qb(n) to the second low voltage. The fifth q transistor T5q has an electrode connected to the Qb node Qb(n), a gate electrode connected to the Qh node Qh, and a second electrode connected to the second low voltage line GVSS1.

[0077] The first output unit 122-3 can output a carry signal C(n) corresponding to the potentials of the Q node Q(n) and the Qb node Qb(n). The first output unit 122-3 includes a first output unit 122-3a that outputs the carry signal C(n) and a second output unit 122-3b that outputs a boosting carry signal. The first output unit 122-3a includes a plurality of buffer transistors T6cr and T7cr, and the first output unit 122-3b includes a plurality of buffer transistors T6b and T7b.

[0078] In this case, the carry signal and the boosting carry signal may be the same signal having the same phase.

[0079] The buffer transistors T6cr and T7cr may be divided into a first pull-up transistor T6r that turns on based on the potential of the Q node Q(n) and a third pull-down transistor T7cr that turns on based on the potential of the Qb node Qb(n). The first pull-up transistor T6cr has a gate electrode connected to the Q node Q(n), a first electrode connected to a second high voltage line GVDD2, and a second electrode connected to a first output node. The first pull-down transistor T7cr has a gate electrode connected to the Qb node Qb(n), a first electrode connected to the first output node, and a second electrode connected to a second low voltage line GVSS2. The buffer transistors T6cr and T7cr may output a carry signal C(n) to the first output node based on a second high voltage applied through a second high voltage line GVDD1 and a second low voltage applied through a second low voltage line GVSS1.

[0080] The buffer transistors T6b and T7b may be divided into a second pull-up transistor T6b that turns on based on the potential of the Q node Q(n) and a second pull-down transistor T7b that turns on based on the potential of the Qb node Qb(n). The second pull-up transistor T6b has a gate electrode connected to the Q node Q(n), a first electrode connected to a second high-potential voltage line GVDD2, and a second electrode connected to a second output node. The second pull-down transistor T7b has a gate electrode connected to the Qb node Qb(n), a first electrode connected to the second output node, and a second electrode connected to a second low-potential voltage line GVSS2. The buffer transistors T6b and T7b may output a boosting carry signal CB(n) to the second output node based on a second high voltage applied through a second high-potential voltage line GVDD1 and a second low-potential voltage applied through a second low-potential voltage line GVSS1.

[0081] A first capacitor C1 and a second capacitor C2 may be provided for boosting the Q node Q(n). The first capacitor may be connected between a second high potential voltage line and a second output node, and the second capacitor may be connected between the second output node and a second low potential voltage line GVSS2.

[0082] The first capacitor C1 and the second capacitor C2 may be designed to have different capacitances. The second capacitor C2 is preferably designed to have a smaller capacitance than the first capacitor C1. In other words, the larger the capacitance of the second capacitor C2, the better the boosting characteristics of the Q node Q(n). However, since the size of the second pull-down transistor increases and the bezel increases, the second capacitor C2 serves to support the operation of the first capacitor C1, so a large capacitance is not necessary.

[0083] The second output unit 122-4 may output an EM signal EMOUT(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n). The second output unit 122-4 may include a plurality of buffer transistors T6 and T7 that output the EM signal EMOUT(n).

[0084] The plurality of buffer transistors T6 and T7 may be divided into a third pull-up transistor T6 that turns on based on the potential of the Q node Q(n) and a third pull-down transistor T7 that turns on based on the potential of the Qb node Qb(n). The third pull-up transistor T6 has a gate electrode connected to the Q node Q(n), a first electrode connected to a first high potential voltage line GVDD0, and a second electrode connected to a third output node. The third pull-down transistor T7 has a gate electrode connected to the Qb node Qb(n), a first electrode connected to the third output node, and a second electrode connected to a first low potential voltage line GVSS0. The plurality of buffer transistors T6 and T7 may output an EM signal EMOUT(n) based on a high potential voltage applied through the first high potential voltage line GVDD0 and a first low potential voltage applied through the first low potential voltage line GVSS0.

[0085] In this embodiment, the boosting performance of the Q node Q(n) can be improved by connecting a capacitor to the output node from which the carry signal with a small load is output.

[0086] 6a to 6f are diagrams for comparing and explaining the boosting performance of the example and the comparative example.

[0087] 6a to 6c show the configuration of a gate driver according to a comparative example, the voltage of the Q node Q(n), the voltage of the EM signal EMOUT(n), and the voltage of the carry signal C(n), respectively.

[0088] In the comparative example, a capacitor is connected to the output node where the EM signal is output, as shown in FIG. 6a. This increases the rising time of the EM signal EMOUT(n) as shown in FIG. 6b, slowing down the boosting speed of the Q node Q(n), resulting in an output loss of the carry signal C(n) as shown in FIG. 6c.

[0089] 6d to 6f show the configuration of the gate driver according to the embodiment, the voltage of the Q node Q(n), the voltage of the EM signal EMOUT(n), and the voltage of the carry signal C(n), respectively.

[0090] In this embodiment, a capacitor is connected to the output node where the carry signal is output, as shown in FIG. 6d, and the rising time of the EM signal EMOUT(n) is reduced, as shown in FIG. 6e, and the boosting speed of the Q node Q(n) is increased, thereby reducing the output loss of the carry signal C(n), as shown in FIG. 6f.

[0091] In the embodiment, the buffer transistor for outputting the carry signal and the buffer transistor for boosting are configured separately, thereby preventing sinking of the Q node Q(n) and improving the output characteristics.

[0092] 7a to 7f are diagrams for comparing and explaining the output characteristics of the example and the comparative example.

[0093] 7a to 7c show the configuration of a gate driver according to a comparative example, the voltage of the Q node Q(n), the voltage of the EM signal EMOUT(n), and the voltage of the carry signal C(n), respectively.

[0094] In the comparative example, as shown in FIG. 7a, a capacitor is connected to the output node from which the carry signal is output. As shown in FIG. 7b, sinking occurs in the carry signal output when Q node Q(n) is charged. The sinking is transmitted to Q node Q(n) by the capacitor, and as shown in FIG. 7c, the rising speed of the EM signal EMOUT(n) is slowed down by Q node Q(n), resulting in output loss.

[0095] That is, when the Q node Q(n) is charged, a sinking occurs in the carry signal output due to the instantaneous movement of charge, and this sinking affects boosting.

[0096] 7d to 7f show the configuration of the gate driver according to the embodiment, the voltage of the Q node Q(n), the voltage of the EM signal EMOUT(n), the carry signal C(n), and the voltage of the boosting carry signal CB(n), respectively.

[0097] In this embodiment, as shown in FIG. 7d, a second output node is provided that outputs a carry signal for boosting, separate from the first output node that outputs the carry signal, and a capacitor is connected to the second output node that outputs the carry signal for boosting. As shown in FIG. 7e, sinking occurs in the carry signal output when Q node Q(n) is charged, but sinking does not occur in the carry signal for boosting CB(n)T. Therefore, as shown in FIG. 7f, Q node Q(n) is boosted without being affected by sinking, and the rising speed of EM signal EMOUT(n) increases, thereby reducing output loss.

[0098] That is, in this embodiment, Q node Q(n) is boosted by boosting carry signal CB(n), so even if sinking occurs in carry signal C(n), the sinking is not transmitted to Q node Q(n).

[0099] Therefore, in this embodiment, in order to maintain a fast rising speed of the EM signal even if the output performance is degraded due to degradation of the pull-up transistor, the first capacitor C1 is connected to the second output node from which the boosting carry signal with a small load is output. That is, the first capacitor C1 is connected between the gate electrode of the second pull-up transistor T6b and the second output node.

[0100] In this embodiment, by adding a second capacitor together with the first capacitor to the second output node from which the boosting carry signal is output, a minimum gate-source voltage Vgs of the second pull-up transistor can be ensured even if the second pull-down transistor cannot perform its function.

[0101] 8a to 8d are diagrams for explaining and comparing the output characteristics of the example and the comparative example.

[0102] 8a and 8b show the configuration of a gate driver according to a comparative example, the voltage at Q node Q, the voltage at Qb node Qb, the voltage of EM signal EMOUT, and the voltage of boosting carry signal CBOUT.

[0103] In the comparative example, as shown in FIG. 8a, the first capacitor C1 is connected to the second output node from which the boosting carry signal is output, and as shown in FIG. 8b, the output characteristics are degraded due to a decrease in boosting of the Q node Q(n).

[0104] In other words, the point at which Q node Q(n) is charged is the point at which Qb node Qb(n) changes from high to low, and because Q node Q(n) and Qb node Qb(n) are not both active, the second pull-down transistor is turned off and is unable to maintain the output voltage at the second low-potential voltage. When the second pull-down transistor is turned off, the second output node is floating, and the voltage at Q node Q(n) rises. As a result, the voltage at the second output node rises due to coupling with the first capacitor C1, and the gate-source voltage Vgs of the second pull-up transistor decreases. As a result, the boosting of Q node Q(n) decreases, and the output characteristics deteriorate.

[0105] 8c to 8d show the configuration of the gate driver according to the embodiment, the voltage of the Q node Q(n), the voltage of the Qb node Qb(n), the voltage of the EM signal EMOUT(n), and the voltage of the boosting carry signal CB(n), respectively.

[0106] In this embodiment, as shown in FIG. 8c, a first capacitor C1 and a second capacitor C2 are connected to a second output node from which a boosting carry signal is output, and as shown in FIG. 8d, the output characteristics are improved by increasing the boosting of the Q node Q(n).

[0107] In other words, even if the second pull-down transistor is turned off and the second output node is floating, if the voltage at Q node Q(n) rises, the second capacitor C2 prevents the voltage at the second output node from rising. As a result, the gate-source voltage Vgs of the second pull-up transistor is maintained, and the boosting of Q node Q(n) increases, improving the output characteristics.

[0108] FIG. 9 is a diagram showing a gate driver according to a second embodiment of the present invention.

[0109] Referring to FIG. 9, the gate driver 122 according to the second embodiment of the present invention may include a first control node (hereinafter referred to as the "Q node") that pulls up the output voltage, a second control node (hereinafter referred to as the "Qb node") that pulls down the output voltage, a first circuit unit 122-1, a second circuit unit 122-2, a first output unit 122-3, and a second output unit 122-4.

[0110] The first circuit unit 122-1 controls the charging and discharging of the Q node Q(n). When the shift clock CLK1 is at a high voltage VGH2 that is greater than or equal to the gate-on voltage VEH, the first circuit unit 122-1 supplies the voltage of the (n-1)th carry signal C(n-1) from the (n-1)th signal processing unit ST(n-1), which is the previous signal processing unit, to the Q node Q(n), thereby charging the Q node Q(n). The first circuit unit 122-1 includes a plurality of transistors T1, T1A, and T3q.

[0111] When the shift clock CLK1 is at a high voltage VGH2 that is greater than or equal to the gate-on voltage VEH, the first transistor T1 is turned on to supply the voltage of the carry signal C(n-1) to the Qh node Qh. The first transistor T1 includes a gate to which the shift clock CLK1 is applied, a first electrode connected to the (N-1)th carry signal line C(n-1), and a second electrode connected to the Qh node Qh.

[0112] The high voltage VGH2 of the shift clock CLK1 may be set to a voltage lower than the second high voltage VGH1. The high voltage VGH1 of the carry signal C(n-1) and the first gate signal EMOUT(n) is the same voltage as the second high voltage VGH1. If the high voltage VGH2 of the shift clock CLK1 is set to be lower than the second high voltage VGH1, when the threshold voltage Vth of the first transistor T1 is shifted to a negative polarity (-Vth) during charging of the Q node Q(n), the Q node Q(n) may float, thereby improving the voltage boosting of the Q node Q(n).

[0113] When the shift clock CLK1 is at a voltage VGH2 greater than or equal to the gate-on voltage VEH, the first A transistor T1A is turned on to supply the voltage of the Qh node Qh to the Q node Q(n), thereby charging and discharging the Q node. The first A transistor T1A includes a gate to which the shift clock CLK1 is applied, a first electrode connected to the Qh node Qh, and a second electrode connected to the Q node Q(n).

[0114] At this time, the plurality of transistors T1 and T1A are connected in series between the (N-1)th carry signal line C(n-1) and the Qh node Qh.

[0115] The third q transistor T3q is turned on when the Q node Q(n) is charged and supplies a second high voltage to the Qh node Qh through the second high voltage line GVDD1. The second high voltage GVDD1 is supplied to the Qh node Qh through the second high voltage line GVDD1. The third q transistor T3q has a gate connected to the Q node Q(n), a first electrode connected to the second high voltage line GVDD1, and a second electrode connected to the Qh node Qh.

[0116] The second circuit unit 122-2 includes an inverter circuit that inverts the voltage of the Q node Q(n) and applies it to the Qb node Qb(n). The inverter circuit of the second circuit unit 122-2 includes a Qb node charging unit and a Qb node discharging unit.

[0117] The Qb node charging unit includes a plurality of transistors T4 and T41, and the Qb node discharging unit includes a plurality of transistors T4q and T5q, which are connected in series.

[0118] The Qb node charging unit switches the current path between the second high potential voltage line GVDD1 and the Qb node Qb(n) according to the voltage of the (n-1)th Qb node Qb(n-1) from the (n-1)th signal transmission unit ST(n-1).

[0119] The fourth transistor T4 is turned on when the voltage at the first node n1 is a high voltage equal to or greater than the gate-on voltage VEH, and connects the second high-potential voltage line GVDD1 to the Qb node Qb(n), thereby charging the Qb node Qb(n) to a high voltage equal to or greater than the gate-on voltage VEH. The fourth transistor T4 has a gate connected to the first node n1, a first electrode connected to the second high-potential voltage line GVDD1, and a second electrode connected to the Qb node Qb(n). The third capacitor C3 is connected between the gate and the second electrode of the fourth transistor T4. The third capacitor C3 allows the voltage at the first node n1 to be boosted when the fourth transistor T4 is turned on.

[0120] The 41st transistor T41 is turned on when the voltage at the (n-1)th Qb node Qb(n-1) of the (n-1)th signal transmission unit ST(n-1) is a high voltage equal to or higher than the gate-on voltage VEH, and supplies the second high potential voltage GVDD1 to the first node n1, thereby charging the first node n1 to a voltage equal to or higher than the gate-on voltage VEH. The 41st transistor T41 includes a gate connected to the (n-1)th Qb node (Qb(N-1)) of the (n-1)th signal transmission unit ST(n-1), a first electrode connected to the second high potential voltage line GVDD1, and a second electrode connected to the first node n1.

[0121] The Qb node discharge unit is turned on to discharge the Qb node Qb(n) when the voltage of the Qh node Qh is a high voltage higher than the gate high voltage VEH.

[0122] The fourth q transistor T4q is turned on when the voltage at the Qh node Qh is a high voltage equal to or higher than the gate-on voltage VEH, connecting the first node n1 to the Qb node Qb(n). The fourth q transistor T4q includes a first electrode connected to the first node n1, a gate electrode connected to the Qh node Qh, and a second electrode connected to the Qb node Qb(n).

[0123] The fifth q transistor T5q is turned on when the voltage of the Qh node Qh is a high voltage equal to or higher than the gate-on voltage VEH, and connects the Qb node Qb(n) to the second low voltage line GVSS1, thereby discharging the voltage of the Qb node Qb(n) to the second low voltage. The fifth q transistor T5q has an electrode connected to the Qb node Qb(n), a gate electrode connected to the Qh node Qh, and a second electrode connected to the second low voltage line GVSS1.

[0124] The first output unit 122-3 may output a carry signal C(n) corresponding to the potentials of the Q node Q(n) and the Qb node Q(n)b. The first output unit 122-3 may include a plurality of buffer transistors T6cr and T7cr that output the carry signal C(n).

[0125] The buffer transistors T6cr and T7cr may be divided into a first pull-up transistor T6cr that turns on based on the potential of the Q node Q(n) and a third pull-down transistor T7cr that turns on based on the potential of the Qb node Qb(n). The first pull-up transistor T6cr has a gate electrode connected to the Q node Q(n), a first electrode connected to a second high voltage line GVDD1, and a second electrode connected to a first output node. The first pull-down transistor T7cr has a gate electrode connected to the Qb node Qb(n), a first electrode connected to the first output node, and a second electrode connected to a second low voltage line GVSS2. The buffer transistors T6cr and T7cr may output a carry signal C(n) to the first output node based on a second high voltage applied through the second high voltage line GVDD1 and a second low voltage applied through the second low voltage line GVSS1.

[0126] The first capacitor C1 and the second capacitor C2 may be provided for boosting the Q node Q(n). The first capacitor C1 may be connected between the Q node Q(n) and the first output node, and the second capacitor C2 may be connected between the first output node and the second low-potential voltage line GVSS1.

[0127] The second output unit 122-4 may output an EM signal EMOUT(n) in response to the potentials of the Q node Q(n) and the Qb node Qb(n). The second output unit 122-4 may include a plurality of buffer transistors T6 and T7 that output the EM signal EMOUT(n).

[0128] The plurality of buffer transistors T6 and T7 may be divided into a third pull-up transistor T6 that turns on based on the potential of the Q node Q(n) and a third pull-down transistor T7 that turns on based on the potential of the Qb node Qb(n). The third pull-up transistor T6 has a gate electrode connected to the Q node Q(n), a first electrode connected to a first high potential voltage line GVDD0, and a second electrode connected to a third output node. The third pull-down transistor T7 has a gate electrode connected to the QB node QB(n), a first electrode connected to the third output node, and a second electrode connected to a first low potential voltage line GVSS0. The plurality of buffer transistors T6 and T7 may output an EM signal EMOUT(n) based on a high potential voltage applied through the first high potential voltage line GVDD0 and a first low potential voltage applied through the first low potential voltage line GVSS0.

[0129] The driving timing of the gate driver according to the second embodiment is the same as that of the gate driver according to the first embodiment, and is shown in FIG. 5, so a description thereof will be omitted.

[0130] Although the present invention has been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present invention. Therefore, the disclosed embodiments are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the scope of the claims, and all technical concepts within the equivalent range thereof should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0131] 100: Display panel 110: Data driver 120: Gate driver 130: Timing controller 140: Power supply section

Claims

1. A gate driver, a plurality of signaling portions cascaded via carry lines that apply carry signals from previous signaling portions to the signaling portions; The nth (n is a positive integer) signal transmission unit of the plurality of signal transmission units is a first output section that outputs a carry signal to a first output node according to the voltages of a first control node that pulls up the output voltage and a second control node that pulls down the output voltage; a second output section for outputting a boosting carry signal to a second output node according to the voltages of the first control node and the second control node; a third output section that outputs a gate signal to a third output node according to voltages of the first control node and the second control node; the boosting carry signal is a signal generated to boost the voltage of the first control node, The second output unit a pull-up transistor connected to a high potential voltage line and applying a gate high voltage to the second output node in response to a charging voltage of the first control node; a pull-down transistor for applying a gate low voltage to the second output node in response to the charging voltage of the second control node; a first capacitor directly coupled between the gate of the pull-up transistor and the second output node; and a second capacitor directly connected between the second output node and a low potential voltage line; Including, The second output node is coupled to both the first capacitor and the second capacitor.

2. The gate driver of claim 1 , wherein the first capacitor and the second capacitor have different capacitances.

3. The gate driver of claim 2 , wherein the second capacitor has a smaller capacitance than the first capacitor.

4. 2. The gate driver of claim 1, wherein the carry signal and the boosting carry signal have the same phase.

5. 2. The gate driver of claim 1, wherein the first control node is connected to a first output node of an (n-1)th signal transfer unit configured to output an (n-1)th carry signal.

6. A display device, a display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power supply lines to which different constant voltages are applied, and a plurality of sub-pixels; a data driver for supplying a data voltage of pixel data to the data line; and a gate driver for supplying gate signals to the gate lines; the gate driver includes a plurality of signaling units cascaded via a carry line that applies a carry signal from a previous signaling unit to a signaling unit; The nth (n is a positive integer) signal transmission unit of the plurality of signal transmission units is a first output section that outputs a carry signal to a first output node according to the voltages of a first control node that pulls up the output voltage and a second control node that pulls down the output voltage; a second output section for outputting a boosting carry signal to a second output node according to the voltages of the first control node and the second control node; and a third output section that outputs a gate signal to a third output node according to voltages of the first control node and the second control node; the boosting carry signal is a signal generated to boost the voltage of the first control node, The second output unit a pull-up transistor connected to a high potential voltage line and applying a gate high voltage to the second output node in response to a charging voltage of the first control node; a pull-down transistor for applying a gate low voltage to the second output node in response to the charging voltage of the second control node; a first capacitor directly coupled between the gate of the pull-up transistor and the second output node; and a second capacitor directly connected between the second output node and a low potential voltage line; Including, The second output node is coupled to both the first capacitor and the second capacitor.

7. The display device of claim 6 , wherein the first capacitor and the second capacitor have different capacitances.

8. The display device according to claim 7 , wherein the second capacitor has a smaller capacitance than the first capacitor.

9. 7. The display device according to claim 6, wherein the carry signal and the boosting carry signal have the same phase.

10. 7. The display device according to claim 6, wherein the second control node is connected to a second control node of an (n-1)th signal transmission unit via one or more transistors.

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