Display driver and display device

Abstract

PURPOSE: To provide a display driver and a display device in which failure occurring in a display panel can be accurately detected without increasing an output load.CONSTITUTION: A display device according to the present invention comprises: an amplifier circuit that supplies output voltage to a source line by outputting output current based on a differential signal representing a difference between gradation voltage corresponding to a video signal and the output voltage to the source line of a display panel; an output current detection circuit that generates mirror current copying the output current, and outputs an output current detection signal representing the mirror current; and a failure determination circuit that determines whether or not short circuit failure or current leakage failure is occurring in the source line by comparing a level of the output current detection signal with a predetermined threshold value. The output current detection circuit includes: a transistor that generates mirror current by receiving a differential signal at a gate; and a variable resistor that generates the output current detection signal by flowing the generated mirror current.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display driver that drives a display panel in response to a video signal, and a display device having the display driver. [Background technology]

[0002] BACKGROUND ART In recent years, vehicles have appeared that are equipped with display panels such as liquid crystal display panels and organic EL (Electro Luminescence) display panels not only for car navigation but also for various electronic instruments.

[0003] However, if the display panel malfunctions while the vehicle is running and an incorrect display is displayed, this may cause problems for the driver.

[0004] Therefore, a liquid crystal display device has been proposed that is equipped with a fault inspection circuit that checks whether a fault has occurred in the display panel during normal use and, if a fault is detected, warns the vehicle occupants of that fact (see, for example, Patent Document 1).

[0005] The fault inspection circuit supplies a monitor input signal to one end of each of the plurality of source lines of the liquid crystal display panel and compares the monitor output signals output from the other ends of each of the source lines with predetermined expected values ​​to detect short-circuit and open-circuit abnormalities in the source lines. Therefore, the fault inspection circuit includes monitor signal lines that are individually connected to one end of each source line for inputting the monitor input signals for fault inspection, and a comparison circuit that compares the monitor output signals output from the other ends of each source line with predetermined expected values. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] WO2018 / 079636 publication Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the fault inspection described in Patent Document 1, whether or not a short circuit or an open circuit has occurred in the source line of the display panel is determined by comparing the magnitude using an expected value as a threshold value, making it difficult to accurately detect faults such as minute current leaks. Also, in the fault inspection circuit described in Patent Document 1, a switch for extracting the above-mentioned monitor output signal is connected to the other end of the source line, which causes a problem in that the output load of the amplifier that outputs a drive voltage to the source line increases by the amount of this switch element.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display driver and a display device that are capable of accurately detecting a fault occurring in a display panel without increasing the output load. [Means for solving the problem]

[0009] A display driver according to the present invention includes an amplifier circuit that receives a grayscale voltage having a voltage value corresponding to a brightness level indicated by a video signal, and outputs an output current based on the grayscale voltage to a source line of a display panel, thereby supplying an output voltage having a voltage value corresponding to the grayscale voltage to the source line; an output current detection circuit that generates a mirror current that is a copy of the output current, and outputs an output current detection signal having a level corresponding to the current amount of the mirror current; and a display driver that determines whether a short circuit failure or a current leakage failure has occurred in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a predetermined threshold. and a fault determination circuit for detecting a difference between the gradation voltage and the output voltage, wherein the amplifier circuit includes a differential section that generates a differential signal representing the difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected, and the output current detection circuit includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and receives the mirror current flowing into it to generate the output current detection signal at the second output node.

[0010] A display driver according to the present invention includes first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a brightness level of each pixel indicated by a video signal, generate currents corresponding to amounts of change in voltage values ​​of the grayscale voltages for each of the first to n-th grayscale voltages as first to n-th output currents, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines; first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels corresponding to amounts of the first to n-th mirror currents; and a fault determination circuit that determines whether a short-circuit fault or a current leakage fault has occurred in the first to n-th source lines based on the first to n-th output current detection signals output from the output current detection circuits, wherein each of the first to n-th amplifier circuits includes a differential section that generates a differential signal that represents a difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected, and each of the first to n-th output current detection circuits includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and receives the mirror current flowing into it to generate the output current detection signal at the second output node.

[0011] A display device according to the present invention comprises a display panel in which display cells are arranged at each intersection of first to n-th (n is an integer of 2 or more) source lines and a plurality of gate lines, and a display driver that drives the display panel in response to a video signal, wherein the display driver receives first to n-th gradation voltages each having a voltage value corresponding to a luminance level of each pixel indicated by the video signal, generates, for each of the first to n-th gradation voltages, currents corresponding to an amount of change in the voltage value of the gradation voltage as first to n-th output currents, and supplies the generated first to n-th output voltages to the first to n-th source lines, first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels corresponding to the current amounts of the first to n-th mirror currents, and and a fault determination circuit that individually determines whether a short-circuit fault or a current leakage fault has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the output current detection circuits with respective predetermined thresholds, wherein each of the first to nth amplifier circuits includes a differential section that generates a differential signal representing the difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected, and each of the first to nth output current detection circuits includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and receives the mirror current flowing into it to generate the output current detection signal at the second output node.

[0012] Further, a display driver according to the present invention includes first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a brightness level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of the grayscale voltage for each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines; a failure determination circuit that determines a short-circuit failure or a current leakage failure in the first to n-th source lines; and a common wiring connected to each of the first to n-th amplifier circuits, a first transistor that receives the differential signal at its gate and outputs the output current from its drain; and a second transistor that receives the differential signal at its gate and outputs a mirror current that is a copy of the output current output from the first transistor to the common wiring, wherein the fault determination circuit includes a variable resistor that is connected to the common wiring and generates an output current detection signal on the common wiring when a current that is a combination of the mirror currents output from the second transistors of the first to nth amplifier circuits flows through the common wiring; and a comparator that determines whether a short-circuit fault or a current leakage fault has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.

[0013] A display driver according to the present invention receives first to n-th (n is an integer of 2 or more) grayscale voltages each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generates first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and outputs the generated first to n-th output currents to first to n-th source lines of a display panel, respectively. a fault determination circuit that determines whether the first to n-th source lines are short-circuit faults or current leakage faults; and first to k-th common wirings that are individually connected to the first to k-th amplifier circuit groups, where the first to n-th amplifier circuits are divided into first to k-th amplifier circuit groups (k is an integer equal to or greater than 2 and less than n), each of which includes at least one amplifier circuit, and each of the first to n-th amplifier circuits generates a differential signal that represents a difference between the grayscale voltage and the output voltage. a first transistor receiving the differential signal at its gate and sending out the output current from its drain; and a second transistor receiving the differential signal at its gate and sending out a mirror current, which is a copy of the output current sent out from the first transistor, to a common wiring among the first to k-th common wirings to which the amplifier circuit group to which the second transistor belongs, is connected. The fault determination circuit includes: a multiplexer selecting the first to k-th common wirings one by one and connecting the selected one common wiring to an output node; a variable resistor connected to the output node and generating an output current detection signal at the output node when a current obtained by combining the mirror currents sent out from the second transistors of each of the amplifier circuits flows through the one common wiring, the multiplexer, and the output node; and a comparator comparing a level of the output current detection signal with a predetermined threshold to determine whether a short-circuit fault or a current leakage fault has occurred in the first to n-th source lines. [Effects of the Invention]

[0014] The present invention provides a display driver including an amplifier circuit that supplies an output voltage to a source line of a display panel by outputting an output current based on a gradation voltage corresponding to a brightness level indicated by a video signal to the source line, and further provides the following output current detection circuit and failure judgment circuit that detect short-circuit failures or current leakage failures in the source line of the display panel.

[0015] The output current detection circuit generates a mirror current that is a copy of the output current output from the amplifier circuit to the source line, and obtains an output current detection signal that represents the mirror current. The fault determination circuit compares the level of the output current detection signal with a predetermined threshold to determine whether a short circuit fault or a current leakage fault has occurred in the source line.

[0016] Here, the output current detection circuit includes a transistor that generates the above-mentioned mirror current by receiving at its gate a differential signal that represents the difference between the gradation voltage and the output voltage, which is generated in the differential section of the amplifier circuit, and a variable resistor that generates the above-mentioned output current detection signal by the flow of the mirror current and adjusts the level of this output current detection signal.

[0017] Therefore, by adjusting the level of the output current detection signal using the variable resistor in accordance with the amount of current leakage expected due to the size of the display panel, the length and material of each source line, etc., it is possible to perform highly accurate fault detection using a predetermined threshold value regardless of the amount of current leakage.

[0018] Therefore, even if the amount of current leakage occurring in the source line of the display panel is minute, it is possible to accurately detect this as a failure.

[0019] Furthermore, the output current detection circuit generates a mirror current that copies the output current output by the amplifier circuit based on the differential signal generated in the differential part of the amplifier circuit, and generates an output current detection signal that indicates the change in the current amount of the output current based on the mirror current.

[0020] This eliminates the need to connect elements such as current detection switches and resistors to the output node of the amplifier circuit, making it possible to detect short-circuit faults or current leakage faults in the source lines of the display panel without increasing the output load. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a block diagram showing the configuration of a display device 100. FIG. [Figure 2] 4A and 4B are waveform diagrams showing examples of waveforms of a data capture signal LOAD and a strobe signal STB. [Figure 3] 2 is a block diagram showing an example of the internal configuration of a source driver 13. FIG. [Figure 4] FIG. 2 is a circuit diagram showing the internal configuration of an amplifier AMI. [Figure 5] 10A and 10B are diagrams showing operational waveforms in an amplifier AM1 when a short circuit fault or a current leakage fault occurs in a source line S1 of a display panel 20 and when no such fault occurs. [Figure 6] FIG. 13 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330. [Figure 7] 10 is a block diagram showing another example of the internal configuration of the source driver 13. FIG. [Figure 8] FIG. 2 is a circuit diagram showing the internal configuration of an amplifier AXI. [Figure 9] FIG. 10 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330A. [Figure 10] 10 is a block diagram showing yet another example of the internal configuration of the source driver 10. FIG. [Figure 11] FIG. 10 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330B. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0023] FIG. 1 is a block diagram showing the configuration of a display device 100 including a display driver according to the present invention.

[0024] The display device 100 includes a drive control unit 11, a gate driver 12, a source driver 13, and a display panel 20.

[0025] The display panel 20 is, for example, a liquid crystal or organic electroluminescence (EL) panel. The display panel 20 has gate lines G1 to Gm (m is an integer of 2 or more) each extending in the horizontal direction of the two-dimensional screen and source lines S1 to Sn (n is an integer of 2 or more) each extending in the vertical direction of the two-dimensional screen, arranged to intersect with each other. Display cells PC made of liquid crystal or organic EL elements or the like are formed at the intersections of the gate lines and source lines.

[0026] The drive control unit 11 receives the video signal VS, generates a scanning signal in accordance with the horizontal synchronization signal included in the video signal VS, and supplies the generated scanning signal to the gate driver 12.

[0027] In addition, the drive control unit 11 generates a video data signal VPD including a series of display data fragments representing the brightness level of each pixel, for example, in 8 bits, based on the video signal VS, and various control signals including a data capture signal LOAD, and supplies these to the source driver 13.

[0028] As shown in FIG. 2, the data loading signal LOAD is a binary (logical levels 0 and 1) pulse signal having the same period (1H) as the horizontal synchronization signal.

[0029] Furthermore, the drive control unit 11 periodically receives a failure location data signal FLD supplied from the source driver 13. The failure location data signal FLD is a signal that indicates the location of a failure when a failure occurs in the display panel 20. When the failure location data signal FLD indicates the location of a failure, the drive control unit 11 executes display control or audio output control to notify the user that a failure has occurred in the location of the failure.

[0030] The gate driver 12 generates scanning pulses in response to the scanning signals supplied from the drive control unit 11, and applies these to the gate lines G1 to Gn of the display panel 20 in sequence.

[0031] The source driver 13 loads a series of display data fragments included in the video data signal VPD in response to a data load signal LOAD. Each time the source driver 13 loads one horizontal scan line, i.e., n display data fragments, it generates output voltages GV1-GVn having voltage values ​​corresponding to the brightness levels represented by the respective display data fragments. The source driver 13 then supplies the output voltages GV1-GVn to source lines S1-Sn of the display panel 20.

[0032] Furthermore, the source driver 13 detects a failure occurring in the source lines S1 to Sn of the display panel 20, and supplies a signal indicating the location of the failure to the drive control unit 11 as the above-mentioned failure location data signal FLD.

[0033] FIG. 3 is a block diagram showing an example of the internal configuration of the source driver 13. As shown in FIG.

[0034] As shown in FIG. 3, the source driver 13 includes a data latch unit 131, a decoder unit 132, and an output amplifier unit 133.

[0035] The data latch unit 131 captures a series of display data pieces corresponding to each pixel contained in the video data signal VPD at the timing of, for example, the front edge of the data capture signal LOAD.

[0036] Then, every time the data latch unit 131 captures n pieces of display data for one horizontal scanning period, it supplies the pieces of display data J1 to Jn to the decoder unit 132 at the timing of, for example, the front edge of the data capture signal LOAD.

[0037] The decoder unit 132 selects, for each of the display data J1 to Jn, a grayscale voltage corresponding to the luminance level indicated by the display data Jq (q is an integer from 1 to n) from, for example, 256 grayscale voltages having different voltage values. Then, the decoder unit 132 supplies the n grayscale voltages selected as described above based on the display data J1 to Jn to the output amplifier unit 133 as grayscale voltages V1 to Vn.

[0038] The output amplifier section 133 includes amplifiers AM1 to AMn provided corresponding to the source lines S1 to Sn of the display panel 20, respectively, and a failure determination circuit 1330.

[0039] The amplifiers AM1 to AMn receive the grayscale voltages V1 to Vn and amplify each of them individually to generate output voltages GV1 to GVn having voltage values ​​corresponding to the respective grayscale voltage values. The external terminals TM1 to TMn are connected to the source lines S1 to Sn of the display panel 20, respectively. The amplifiers AM1 to AMn supply the generated output voltages GV1 to GVn to the source lines S1 to Sn via the external terminals TM1 to TMn.

[0040] Furthermore, the amplifiers AM1 to AMn detect the output current sent to each of the source lines S1 to Sn, and supply output current detection signals f1 to fn indicating the amount of the output current for each of the source lines S1 to Sn to the failure determination circuit 1330.

[0041] The amplifiers AM1 to AMn have the same internal configuration, so the internal configuration of the amplifier AM1 will be explained below by selecting it from the amplifiers AM1 to AMn.

[0042] FIG. 4 is a circuit diagram showing an example of the internal configuration of the amplifier AM1.

[0043] The amplifier AM1 includes an amplifier circuit 1331 and an output current detection circuit 1332 as shown in FIG.

[0044] The amplifier circuit 1331 is, for example, a voltage follower operational amplifier, and has a differential section DC, a transistor Q1 as a P-channel MOS output transistor, and a transistor Q2 as an N-channel MOS output transistor.

[0045] The differential unit DC receives the output voltage GV1 output from the amplifier circuit 1331 and the above-mentioned gradation voltage V1, and generates a differential signal PG having a level corresponding to the difference between the voltage values ​​of the two. The differential unit DC supplies the generated differential signal PG via node nd0 to the gate of transistor Q1, which serves as a positive output transistor, and to the output current detection circuit 1332. Furthermore, the differential unit DC inverts the phase of the differential signal PG to generate an inverted differential signal NG, which is supplied to the gate of transistor Q2, which serves as a negative output transistor.

[0046] That is, when the grayscale voltage V1 is higher than the output voltage GV1, i.e., when the output voltage rises, the differential unit DC generates a differential signal PG whose level increases as the difference between the two increases.Furthermore, when the grayscale voltage V1 is lower than the output voltage GV1, i.e., when the output voltage falls, the differential unit DC generates an inverted differential signal NG whose level increases as the difference between the two increases.

[0047] The source of the transistor Q1 is connected to a power supply potential, and the drain of the transistor Q1 is connected to the drain of the transistor Q2 and an external terminal TM1 via an output node nd1. The source of the transistor Q2 is connected to a ground potential.

[0048] The transistor Q1 generates an output current Iout corresponding to the differential signal PG received at its gate and sends this to the external terminal TM1 via the output node nd1. The transistor Q2 extracts a current (called extraction current) corresponding to the inverted differential signal NG received at its gate from the output node nd1. This operation generates an output voltage GV1 having a voltage value corresponding to the input gradation voltage V1 at the output node nd1 and the external terminal TM1.

[0049] 4, the external terminal TM1 connected to the amplifier circuit 1331 included in the amplifier AM1 is connected to the source line S1 of the display panel 20. Therefore, the amplifier AM1 supplies the output voltage GV1 generated as described above to the source line S1 of the display panel 20. Similarly, the external terminal TMj connected to the amplifier circuit 1331 included in the amplifier AMj (j is an integer from 2 to n) is connected to the source line Sj of the display panel 20, and supplies the output voltage GVj generated by each of them to the source line Sj.

[0050] The output current detection circuit 1332 detects the output current output to the source line connected to the amplifier circuit 1331 and generates an output current detection signal that represents the amount of the output current as a voltage value level. For example, the output current detection circuit 1332 included in amplifier AM1 detects the output current Iout that the amplifier circuit 1331 sends to the source line S1 and generates an output current detection signal f1 that represents the amount of the current as a voltage value level. Similarly, the output current detection circuit 1332 included in amplifier AMj (j is an integer from 2 to n) detects the output current that the amplifier circuit 1331 sends to the source line Sj and generates an output current detection signal fj that represents the amount of the current as a voltage value level.

[0051] As shown in FIG. 4, the output current detection circuit 1332 includes a P-channel MOS transistor QS, a resistor RG1, and a variable resistor R1.

[0052] The source of transistor QS is supplied with the power supply potential, and its gate is supplied with the differential signal PG via node nd0. In other words, like transistor Q1, transistor QS receives the differential signal PG generated by the differential section DC at its gate. The drain of transistor QS is connected to one end of variable resistor R1 via output node nd2. Ground potential is applied to the other end of variable resistor R1, and its resistance value can be changed by adjusting the value stored in register RG1.

[0053] With this configuration, transistor QS generates a current corresponding to the differential signal PG received at its gate, i.e., a mirror current corresponding to the output current output by transistor Q1 of amplifier circuit 1331, and sends this to variable resistor R1 via output node nd2. Therefore, the mirror current flows into variable resistor R1, and a voltage signal is generated at output node nd2, generating an output current detection signal f whose voltage level indicates the change in the amount of output current sent to the source line. In other words, the mirror current flows into variable resistor R1, and an output current detection signal that changes depending on the amount of this flow is provided to output node nd2.

[0054] As a result, the output current detection circuits 1332 included in the amplifiers AM1 to AMn respectively supply the failure determination circuit 1330 with output current detection signals f1 to fn that individually indicate the amounts of the output currents sent to the source lines S1 to Sn, respectively.

[0055] The level of each of the output current detection signals f1 to fn can be adjusted by a variable resistor R1 using an adjustment value stored in a register RG1. For example, taking into consideration an increase in output current due to a current leak that is expected when a source line of the display panel 20 is short-circuited with a gate line, the adjustment value is stored in advance in the register RG1 so that the failure determination circuit 1330 can determine that this current increase is a failure.

[0056] The fault determination circuit 1330 determines whether a short circuit fault or a current leakage fault has occurred in the source lines S1 to Sn of the display panel 20 based on the output current detection signals f1 to fn, and generates a fault location data signal FLD indicating the source line in which the fault has occurred.

[0057] Specifically, the fault determination circuit 1330 compares the level of the output current detection signal with a predetermined threshold value Vth for fault determination at time t1, a predetermined period DL after time t0 of the front edge of the data capture signal LOAD, as shown in FIG. 2. If the level of the output current detection signal is greater than the threshold value Vth, the fault determination circuit 1330 determines that a short-circuit fault or a current leakage fault has occurred in the source line corresponding to this output current detection signal. On the other hand, if the level of the output current detection signal is equal to or less than the threshold value Vth, the fault determination circuit 1330 determines that a short-circuit fault or a current leakage fault has not occurred in the source line corresponding to this output current detection signal. The fault determination circuit 1330 then generates a fault location data signal FLD that indicates the determination result obtained by performing the above-described determination process for each output current detection signal.

[0058] The failure determination operations in the amplifier circuit 1331, the output current detection circuit 1332, and the failure determination circuit 1330 will be described below with reference to FIGS.

[0059] 5 is a diagram showing the operating waveforms in the amplifier AM1 shown in FIG. 4, divided into cases where a short circuit fault or a current leakage fault occurs and where no short circuit fault occurs in the source line S1 of the display panel 20. Also, FIG. 5 shows the operating waveforms when the grayscale voltage V1 received by the amplifier AM1 transitions from a voltage value of 0 to a voltage value Va at the timing (time t0) of the leading edge of the data load signal LOAD.

[0060] [If there is no malfunction] As shown in FIG. 5, when the gradation voltage V1 transitions from zero to Va (Va > 0) at time t0, the differential unit DC of the amplifier circuit 1331 sends a differential signal PG having a difference (0 - Va) between the output voltage GV1 and the gradation voltage V1 to node nd0. In response to this differential signal PG, the transistor Q1 turns on and sends an output current Iout corresponding to the difference (0 - Va) to the source line S1. This causes the voltage on the source line S1, i.e., the voltage of the output voltage GV1, to gradually increase. As a result, the difference between the gradation voltage V1 and the output voltage GV1 gradually decreases, and the voltage of the differential signal PG gradually returns to Vb, causing the output current Iout to decrease. After that, when the voltage of the output voltage GV1 reaches Va, the voltage of the differential signal PG becomes Vb, which transitions the transistor Q1 to the off state. Therefore, when the transistor Q1 turns off, the output current Iout also becomes zero.

[0061] During this time, the transistor QS of the output current detection circuit 1332 sends a mirror current Imr, which is a copy of the output current Iout, to the variable resistor R1 via the output node nd2 as shown in Fig. 5. As a result, a signal representing the change in the amount of current in the mirror current Imr as a change in voltage value is generated on the output node nd2, that is, an output current detection signal f1 representing the change in the amount of current in the output current Iout shown in Fig. 5.

[0062] Here, if no short circuit or current leakage failure occurs in the source line S1 of the display panel 20, the output current Iout will be zero at time t1, a predetermined period DL after time t0, as shown in Fig. 5. At this time, the mirror current Imr, which is a copy of the output current Iout, will also be zero at time t1, and the level of the output current detection signal f1 corresponding to the mirror current Imr at time t1 will be a voltage value Vx that indicates a current amount of zero, as shown in Fig. 5.

[0063] Therefore, as shown in FIG. 5, since the level of the output current detection signal f1 at time t1 is below a predetermined threshold Vth (shown by the dashed line in FIG. 5), the fault determination circuit 1330 generates a fault location data signal FLD indicating that there is no short circuit fault or current leakage fault for the source line S1.

[0064] [If there is a malfunction] Even if a short circuit or current leakage fault occurs in the source line S1, when the gradation voltage V1 transitions from zero to Va at time t0, the differential part DC of the amplifier circuit 1331 sends a differential signal PG having a difference (0-Va) between the output voltage GV1 and the gradation voltage V1 to node nd0. In response to this differential signal PG, the transistor Q1 turns on and sends an output current Iout corresponding to the difference (0-Va) to the source line S1. This causes the voltage on the source line S1, i.e., the voltage of the output voltage GV1, to gradually increase. As a result, the difference gradually increases, and the voltage of the differential signal PG also gradually increases. As the voltage of the differential signal PG increases, the output current Iout decreases.

[0065] In this case, if the source line S1 is short-circuited to at least one of the gate lines G1-Gn, such as the gate line G2 as shown in FIG. 4, the output current Iout flows not only through the source line S1 but also through the gate line G2. In other words, a portion of the output current Iout leaks into the gate line G2 as a leakage current. Therefore, since both the source line S1 and the gate line G2 are charged by the output current Iout, the increase in the output voltage GV1 is slower than when there is no short-circuit fault in the source line S1. As a result, as shown in FIG. 5, at time t1, the voltage value of the output voltage GV1 does not reach Va, the voltage value of the gradation voltage V1, but remains at Vc, which is lower than Va. Therefore, the difference (Vc - Va) between the output voltage GV1 and the gradation voltage V1 does not become zero. Therefore, as shown in FIG. 5, the voltage value of the differential signal PG corresponding to this difference does not reach Vb, which is the voltage value that can transition the transistor Q1 to the off state. Therefore, the transistor Q1 remains on even at time t1, and outputs the output current Iout having the current amount Ib corresponding to the difference value (Vc-Va) represented by the differential signal PG, as shown in Fig. 5. As a result, the level of the output current detection signal f1 at time t1, which corresponds to the mirror current Imr that is a copy of the output current Iout, becomes the current amount Vy, which is higher than the voltage value Vx that represents zero current amount, as shown in Fig. 5.

[0066] Therefore, as shown in FIG. 5, since the level of the output current detection signal f1 at time t1 is higher than the predetermined threshold Vth, the failure determination circuit 1330 generates a failure location data signal FLD indicating the presence of a short circuit failure or a current leakage failure for the source line S1.

[0067] As described above in detail, in the display device 100, the output current detection circuit 1332 and the failure determination circuit 1330 are provided in the source driver 13 as a failure detection device that detects short-circuit failures or current leakage failures in the source lines (S1 to Sn) of the display panel 20.

[0068] The output current detection circuit 1332 is provided in each of the amplifiers AM1 to AMn, and for each amplifier AM, generates a mirror current Imr that is a copy of the output current Iout that the amplifier outputs to the source line, and sends this to the variable resistor R1 via the output node nd2. At this time, as the mirror current Imr flows through the variable resistor R1, an output current detection signal f is generated at the output node nd2, which is a signal obtained by current-voltage conversion of the mirror current Imr, that is, an output current detection signal f that represents the transition in the current amount of the mirror current Imr as a transition in voltage value.

[0069] As shown in FIG. 5, at time t1, a predetermined period DL has elapsed since time t0 when the voltage value of the input gradation voltage changed, if the level of the output current detection signal f is greater than a predetermined threshold Vth, the fault determination circuit 1330 determines that a fault exists, and if the level is equal to or less than the threshold Vth, it determines that no fault exists.

[0070] In this way, when a voltage follower operational amplifier (1331) is used as the output amplifier of the source driver, the fault detection device (1332, 1330) performs fault detection using the threshold value Vth, focusing on the fact that if a fault such as a short circuit or current leakage occurs in the source line, the mirror current Imr (=Iout) becomes higher than when no fault occurs.

[0071] Here, the output current detection circuit 1332 employs a variable resistor R1 as a resistor used to obtain an output current detection signal from the mirror current Imr, thereby making it possible to adjust the level of the output current detection signal.

[0072] This allows the level of the output current detection signal to be adjusted according to the amount of current leakage expected from the size of the display panel, the length and material of each source line, etc., thereby making it possible to perform highly accurate fault detection using a fixed threshold value Vth regardless of the amount of current leakage.

[0073] Therefore, the fault detection device (1332, 1330) can accurately determine that a fault has occurred even if the amount of current leakage occurring in the source line of the display panel 20 is minute.

[0074] Furthermore, in the output current detection circuit 1332, in order to detect the output current Iout output to the source line, a transistor QS is provided that receives the differential signal PG generated by the differential part DC of the amplifier circuit 1331 at its gate in the same manner as the output transistor (Q1).

[0075] That is, in the output current detection circuit 1332, the output current Iout is copied by the transistor QS, and the mirror current Imr obtained by this copy is sent to the resistor (R1) to detect the output current. This eliminates the need to connect elements such as switches and resistors for detecting faults (short circuits, current leaks) to the output node nd1 of the amplifier circuit 1331, and therefore makes it possible to detect short circuit faults or current leak faults in the source lines of the display panel 20 without increasing the output load of the amplifier.

[0076] Incidentally, the above-mentioned fault determination circuit 1330 may be configured to divide all source lines into a plurality of source line groups and perform fault determination on one representative source line for each source line group, rather than individually determining faults for all source lines S1 to Sn as described above.

[0077] Fig. 6 is a block diagram showing an example of the internal configuration of a fault determination circuit 1330 that has been made in consideration of the above points. In the configuration shown in Fig. 6, the source lines S1 to Sn are divided into first to r-th (r is an integer of 2 or more) source line groups each consisting of, for example, 20 adjacent source lines, and fault determination is performed on any one representative source line for each of the first to r-th source line groups.

[0078] The failure determination circuit 1330 shown in FIG. 6 includes selectors SL1 to SLr (r is an integer equal to or greater than 2), comparators CM1 to CMr, a delay circuit DD1, and a register RG2.

[0079] Each of the selectors SL1 to SLr receives 20 output current detection signals from the output current detection signals f1 to fn. Each of the selectors SL1 to SLr selects one output current detection signal indicated by the representative source line designation signal TS from the 20 output current detection signals received, and outputs this as the representative output current detection signal Sf. That is, the selectors SL1 to SLr supply the representative output current detection signals Sf1 to SFr selected and obtained in response to the representative source line designation signal TS to the corresponding comparators CM1 to CMr.

[0080] Each of the comparators CM1 to CMr compares the level of the representative output current detection signal Sf it receives with a predetermined threshold Vth for fault determination. At this time, each of the comparators CM1 to CMr generates a pre-fault determination signal that indicates the presence of a fault if the level of the representative output current detection signal Sf is greater than the threshold Vth, and indicates the absence of a fault if the level is equal to or less than the threshold Vth. Therefore, the comparators CM1 to CMr supply the pre-fault determination signals they have generated to the register RG2 as pre-fault determination signals e1 to er.

[0081] The delay circuit DD1 receives the data capture signal LOAD, delays it by a predetermined period DL as shown in FIG. 2, and supplies the signal to the register RG2 as a strobe signal STB.

[0082] The register RG2 captures the pre-fault determination signals e1 to er supplied from the comparators CM1 to CMr at the timing of the leading edge of the strobe signal STB shown in Fig. 2. The register RG2 outputs a fault location data signal FLD including the captured pre-fault determination signals e1 to er as fault determination signals b1 to br.

[0083] Here, for example, if the failure determination signal b1 indicates the presence of a failure, it can be confirmed that a short-circuit failure or a current leakage failure has occurred in the first source line group (S1 to S20) corresponding to the output current detection signal group (e.g., f1 to f20) to which the representative output current detection signal Sf1 corresponding to the failure determination signal b1 belongs. Also, for example, if the failure determination signal b2 indicates the presence of a failure, it can be confirmed that a short-circuit failure or a current leakage failure has occurred in the second source line group (S21 to S40) corresponding to the output current detection signal group (e.g., f21 to f40) to which the representative output current detection signal Sf2 corresponding to the failure determination signal b2 belongs.

[0084] 6, first, the output current detection signals f1 to fn corresponding to the source lines S1 to Sn are divided into first to r output current detection signal groups, each consisting of, for example, 20 output current detection signals. Then, for each of these first to r output current detection signal groups, a representative output current detection signal is selected, and the level of the selected output current detection signal is compared with the threshold value Vth. This allows a determination to be made as to whether a short-circuit fault or a current leakage fault has occurred in each source line group corresponding to the output current detection signal group to which the selected output current detection signal belongs.

[0085] In the above embodiment, in the output current detection circuit 1332 provided in each of the amplifiers AM1 to AMn, the mirror current Imr, which is a copy of the output current Iout, is converted into a voltage level by the variable resistor R1, thereby generating the output current detection signal f which indicates the amount of current of the output current Iout.

[0086] However, it is also possible to adopt a configuration in which only one system of variable resistor R1 and register RG1 included in the output current detection circuit 1332 is provided within the source driver 13, and the drain of the transistor QS included in each of the amplifiers AM1 to AMn and one end of the variable resistor R1 are commonly connected by a single wiring.

[0087] FIG. 7 is a block diagram showing another example of the internal configuration of the source driver 13 that has been designed in consideration of the above points.

[0088] In the configuration shown in FIG. 7, except for the use of output amplifier section 133A instead of output amplifier section 133, the other configurations, i.e., the data latch section 131 and decoder section 132, are the same as those shown in FIG. 3, and therefore description thereof will be omitted.

[0089] The output amplifier section 133A employs amplifiers AX1 to AXn instead of the amplifiers AM1 to AMn shown in FIG. 3, and employs a failure determination circuit 1330A instead of the failure determination circuit 1330 shown in FIG.

[0090] The amplifiers AX1 to AXn receive the grayscale voltages V1 to Vn in the same manner as the amplifiers AM1 to AMn, amplify each of the voltages individually to generate output voltages GV1 to GVn, and supply the generated output voltages GV1 to GVn to the source lines S1 to Sn via the external terminals TM1 to TMn.

[0091] The amplifiers AX1 to AXn have the same internal configuration, so the internal configuration of the amplifier AX1 will be explained below by selecting it from the amplifiers AX1 to AXn.

[0092] FIG. 8 is a circuit diagram showing an example of the internal configuration of the amplifier AX1.

[0093] 8, the amplifier AX1, like the amplifier AM1, includes an amplifier circuit 1331. However, the amplifier AX1 employs a mirror current generating circuit 1333 instead of the output current detecting circuit 1332 shown in FIG.

[0094] The amplifier circuit 1331 shown in FIG. 8 has the same configuration and operation as the amplifier circuit 1331 shown in FIG. 4, and therefore a description thereof will be omitted.

[0095] The mirror current generating circuit 1333 includes a P-channel MOS transistor QS having a power supply potential applied to its source. The gate of the transistor QS is connected to the gate of the transistor Q1 of the amplifier circuit 1331 via a node nd0, and receives the differential signal PG output from the differential section DC at its gate. The drain of the transistor QS is connected to a common line LB. The drains of the transistors QS included in each of the amplifiers AX2 to AXn are also commonly connected to the common line LB.

[0096] With this configuration, the transistor QS generates a current corresponding to the differential signal PG received at its gate, i.e., a mirror current Imr corresponding to the output current output by the transistor Q1 of the amplifier circuit 1331, and sends this to the common wiring LB.

[0097] The fault determination circuit 1330A determines, based on the current sent to the common line LB, at a timing according to the data capture signal LOAD, whether or not a short-circuit fault or a current leakage fault has occurred in the source lines S1 to Sn of the display panel 20. Then, the fault determination circuit 1330A outputs, as a result of the determination, a fault detection signal FLX indicating whether or not a fault has occurred.

[0098] FIG. 9 is a circuit diagram showing an example of the internal configuration of the failure determination circuit 1330A.

[0099] As shown in FIG. 9, the failure determination circuit 1330A includes a resistor RG1, a variable resistor R1, a comparator CM1, a resistor RG3, and a delay circuit DD1.

[0100] One end of the variable resistor R1 is connected to a common line LB, and the other end is connected to a ground potential. Therefore, a combined current, which is a combination of the mirror currents Imr output from the transistors QS included in each of the amplifiers AX1 to AXn, flows into the variable resistor R1 via the common line LB. As a result, the variable resistor R1 converts the combined current flowing into itself via the common line LB into a voltage level corresponding to the amount of that current, and generates a signal having this voltage level on the common line LB as an output current detection signal.

[0101] The register RG1 holds an adjustment value that indicates the resistance value of the variable resistor R1. The register RG1 sets the resistance value of the variable resistor R1 based on the adjustment value that is held therein.

[0102] The comparator CM1 compares the voltage of the common line LB, i.e., the output current detection signal, with a predetermined threshold Vth for fault determination, and generates a fault determination signal eX indicating the presence of a fault if the voltage level of the output current detection signal is greater than the threshold Vth, and indicating the absence of a fault if the voltage level is equal to or less than the threshold Vth. The comparator CM1 supplies the generated fault determination signal eX to the register RG3.

[0103] The delay circuit DD1 receives the data capture signal LOAD, delays it by a predetermined period DL as shown in FIG. 2, and supplies the signal to the register RG3 as a strobe signal STB.

[0104] The register RG3 captures the failure determination signal eX supplied from the comparator CM1 at the timing of the leading edge of the strobe signal STB shown in Fig. 2. The register RG3 holds a signal indicating the level of the captured failure determination signal eX and supplies it to the drive control unit 11 as a failure detection signal FLX indicating whether or not a short circuit failure or a current leakage failure has occurred in the source line group (S1 to Sn).

[0105] That is, a combined current, which is a combination of the output current Iout output from each transistor QS of the amplifiers AX1 to AXn and the same mirror current Imr, flows through the common line LB. At this time, if a short-circuit fault or current leakage fault occurs in at least one of the source lines S1 to Sn, the mirror current Imr (=Iout) at time t1 shown in FIG. 5 is higher than when no short-circuit fault or current leakage fault occurs in the source lines S1 to Sn.

[0106] Therefore, an adjustment value for adjusting the resistance value of variable resistor R1 is stored in register RG1 so that the above-mentioned threshold Vth can be used to distinguish between a case where a short circuit fault or current leakage fault has occurred in one of source lines S1 to Sn and a case where no short circuit fault or current leakage fault has occurred in source lines S1 to Sn.

[0107] 7 to 9, it is possible to detect a short circuit fault or a current leakage fault that has occurred in at least one of the source lines S1 to Sn. In this case, although the configurations shown in Figures 7 to 9 cannot identify the source line in which such a fault has occurred, it is possible to reduce the device scale compared to when the configurations shown in Figures 3, 4, and 6 are adopted.

[0108] In addition, by using a plurality of common lines LB in the configurations shown in FIGS. 7 to 9, it becomes possible to identify the fault location in units of source line groups.

[0109] FIG. 10 is a block diagram showing an example of the internal configuration of a source driver 10, which has been made in consideration of the above points and is an application example of the configurations shown in FIGS.

[0110] In the configuration shown in FIG. 10, except for the use of output amplifier section 133B instead of output amplifier section 133, the other configurations, i.e., the data latch section 131 and decoder section 132, are the same as those shown in FIG. 3, and therefore description thereof will be omitted.

[0111] The output amplifier section 133B includes amplifiers AX1 to AXn, common lines LB1 to LB3, and a failure determination circuit 1330B similar to those in Fig. 7. Since the amplifiers AX1 to AXn are the same as those shown in Fig. 7, a description thereof will be omitted.

[0112] However, the drain of the transistor QS of each of amplifiers AX1 to AXp (p is an integer equal to or greater than 2) among amplifiers AX1 to AXn is connected to a common wiring LB1. Furthermore, the drain of the transistor QS of each of amplifiers AX(p+1) to AXt (t is an integer greater than p) is connected to a common wiring LB2, and the drain of the transistor QS of each of amplifiers AX(t+1) to AXn is connected to a common wiring LB3.

[0113] The fault determination circuit 1330B determines, based on the currents sent to the common lines LB1 to LB3, at a timing according to the data capture signal LOAD, whether or not a short-circuit fault or a current leakage fault has occurred in the source lines S1 to Sn of the display panel 20. The fault determination circuit 1330B outputs a fault location data signal FLD that individually indicates whether or not a fault has occurred in each of the source line groups: a first source line group consisting of source lines S1 to Sp, a second source line group consisting of source lines S(p+1) to St, and a third source line group consisting of source lines S(t+1) to Sn.

[0114] FIG. 11 is a circuit diagram showing an example of the internal configuration of the failure determination circuit 1330B.

[0115] As shown in FIG. 11, the fault determination circuit 1330B includes a multiplexer MX, resistors RG1 and RG4, a variable resistor R1, a comparator CM1, and a delay circuit DD1.

[0116] The multiplexer MX selects the common lines LB1 to LB3 one by one in turn based on the representative source line designation signal TS, and connects the selected common line to the output node nd2.

[0117] One end of the variable resistor R1 is connected to the output node nd2, and the other end is connected to the ground potential. The register RG1 holds an adjustment value that indicates the resistance value of the variable resistor R1. The register RG1 sets the resistance value of the variable resistor R1 based on the adjustment value held therein.

[0118] Comparator CM1 compares the voltage of output node nd2, i.e., the voltage of one common line (LB1, LB2, or LB3) selected by multiplexer MX, with a predetermined threshold value Vth for fault determination. Here, comparator CM1 generates a fault determination signal eX that indicates the presence of a fault if the voltage of the one common line is greater than threshold Vth, and indicates the absence of a fault if the voltage is equal to or less than threshold Vth. Then, comparator CM1 supplies the generated fault determination signal eX to register RG4.

[0119] The delay circuit DD1 receives the data capture signal LOAD, delays it by a predetermined period DL as shown in FIG. 2, and supplies the signal to the register RG4 as a strobe signal STB.

[0120] The register RG4 captures the fault determination signal eX supplied from the comparator CM1 at the timing of the leading edge of the strobe signal STB shown in FIG. 2. The register RG4 holds a signal indicating the level of the captured fault determination signal eX. That is, the register RG4 holds a signal indicating the level of the fault determination signal eX obtained when the common wiring LB1 is connected to the comparator CM1 by the multiplexer MX as a first fault determination signal indicating whether a short-circuit fault or a current leakage fault has occurred in the first group of source lines (S1 to Sp). The register RG4 also holds a signal indicating the level of the fault determination signal eX obtained when the common wiring LB2 is connected to the comparator CM1 by the multiplexer MX as a second fault determination signal indicating whether a short-circuit fault or a current leakage fault has occurred in the second group of source lines [S(p+1) to St]. Furthermore, register RG4 holds a signal representing the level of the fault determination signal eX obtained when the common wiring LB3 is connected to the comparator CM1 by the multiplexer MX as a third fault determination signal representing whether or not a short circuit fault or a current leakage fault has occurred in the third source line group [S(t+1) to Sn].

[0121] The register RG4 then supplies the drive control unit 11 with a failure location data signal FLD for each of the first to third source line groups, which individually indicates whether or not a failure has occurred in that source line group.

[0122] 10 and 11, the amplifiers AX1 to AXn are divided into three amplifier groups, namely, [AX1 to AXp], [AX(p+1) to AXt], and [AX(t+1) to AXn], and three common wirings LB1 to LB3 are used for each amplifier group to connect the drains of the transistors QS included in that amplifier group, but the number is not limited to 3. In short, it is sufficient to divide the first to n-th amplifier circuits (AX1 to AXn) into first to k-th amplifier circuit groups (k is an integer greater than or equal to 2 and less than n) each including at least one amplifier, and to connect the first to k-th common wirings individually to the first to k-th amplifier circuit groups, respectively.

[0123] Furthermore, in the above embodiment, the delay circuit DD1 generates the strobe signal STB from the data capture signal LOAD, but the drive control unit 11 may directly generate the strobe signal STB. [Explanation of symbols]

[0124] 11 Drive control unit 13 Source Driver 20 Display panel 100 display device 1330 Failure determination circuit 1331 Amplifier circuit 1332 Output current detection circuit AM1~AMn amplifiers DC differential section QS transistor R1 variable resistor RG1 Register S1~Sn Source lines

Claims

1. an amplifier circuit that receives a grayscale voltage having a voltage value corresponding to a luminance level indicated by a video signal, and outputs an output current based on the grayscale voltage to a source line of a display panel, thereby supplying an output voltage having a voltage value corresponding to the grayscale voltage to the source line; an output current detection circuit that generates a mirror current that is a copy of the output current and outputs an output current detection signal having a level corresponding to the amount of the mirror current; a failure determination circuit that determines whether a short-circuit failure or a current leakage failure has occurred in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a predetermined threshold value, The amplifier circuit a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage; a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected; The output current detection circuit a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain; a variable resistor connected to the second output node, the variable resistor receiving the mirror current and generating the output current detection signal at the second output node.

2. a register for holding an adjustment value; 2. The display driver according to claim 1, wherein the variable resistor adjusts the level of the output current detection signal in accordance with the adjustment value held in the register.

3. a data latch unit that captures and outputs display data pieces that represent the luminance levels of the pixels based on the video signal at predetermined timings; a decoder unit that converts the display data fragment output from the data latch unit into a voltage having a voltage value corresponding to a luminance level indicated by the display data fragment, and supplies the voltage to the amplifier circuit as the gradation voltage, The display driver according to claim 1 or 2, characterized in that the fault judgment circuit judges whether a short circuit fault or a current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold value at a time when a predetermined period has elapsed from the predetermined timing.

4. 4. The display driver according to claim 3, wherein the failure determination circuit determines that a short circuit failure or a current leakage failure has occurred in the source line when the level of the output current detection signal is greater than the predetermined threshold value.

5. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines; first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels that respectively correspond to the amounts of the first to n-th mirror currents; a failure determination circuit that determines whether a short-circuit failure or a current leakage failure has occurred in the first to n-th source lines based on the first to n-th output current detection signals output from the first to n-th output current detection circuits, Each of the first to n-th amplifier circuits a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage; a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected; Each of the first to nth output current detection circuits comprises: a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain; a variable resistor connected to the second output node, the variable resistor receiving the mirror current and generating the output current detection signal at the second output node.

6. The display driver according to claim 5, characterized in that the failure determination circuit individually determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the first to nth output current detection circuits with respective predetermined threshold values.

7. The display driver of claim 5, wherein the failure judgment circuit divides the first to nth output current detection signals output from the first to nth output current detection circuits into first to rth (r is an integer equal to or greater than 2) output current detection signal groups, each consisting of a plurality of output current detection signals, selects one representative output current detection signal from the output current detection signal group for each of the first to rth output current detection signal groups, and compares the level of the selected one output current detection signal with a predetermined threshold value to determine whether a short-circuit failure or a current leakage failure has occurred in units of source line groups corresponding to the output current detection signal group belonging to the one output current detection signal.

8. a display panel in which display cells are arranged at each intersection of first to n-th (n is an integer of 2 or more) source lines and a plurality of gate lines; a display driver that drives the display panel in response to a video signal, The display driver first to n-th amplifier circuits that receive first to n-th gradation voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by the video signal, generate currents corresponding to an amount of change in voltage value of the gradation voltage for each of the first to n-th gradation voltages as first to n-th output currents, and output the generated first to n-th output currents to the first to n-th source lines, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th gradation voltages, respectively, to the first to n-th source lines; first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels that respectively correspond to the amounts of the first to n-th mirror currents; a failure determination circuit that individually determines whether or not a short-circuit failure or a current leakage failure has occurred in the first to n-th source lines by comparing the levels of the first to n-th output current detection signals output from the first to n-th output current detection circuits with predetermined threshold values, Each of the first to n-th amplifier circuits a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage; a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected; Each of the first to nth output current detection circuits comprises: a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain; a variable resistor connected to the second output node, the variable resistor generating the output current detection signal at the second output node when the mirror current flows into the variable resistor.

9. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines; a fault determination circuit for determining whether a short circuit fault or a current leakage fault occurs in the first to n-th source lines; a common wiring connected to each of the first to n-th amplifier circuits; and Each of the first to n-th amplifier circuits a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage; a first transistor receiving the differential signal at its gate and sending the output current from its drain; a second transistor that receives the differential signal at its gate and sends a mirror current that is a copy of the output current sent from the first transistor to the common wiring; The failure determination circuit a variable resistor connected to the common wiring, the variable resistor generating an output current detection signal on the common wiring when a current obtained by combining the mirror currents sent from the second transistors of the first to nth amplifier circuits flows through the common wiring; a comparator that determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.

10. a register for holding an adjustment value; 10. The display driver according to claim 9, wherein the variable resistor adjusts the level of the output current detection signal in accordance with the adjustment value held in the register.

11. a data latch unit that captures and outputs first to nth display data pieces that represent the luminance levels of the pixels based on the video signal at predetermined timings; a decoder section that converts the first to n-th display data pieces output from the data latch section into n voltages each having a voltage value corresponding to a luminance level indicated by the display data piece, and supplies the n voltages to the first to n-th amplifier circuits as the first to n-th gradation voltages, The display driver according to claim 9 or 10, characterized in that the fault judgment circuit judges whether a short circuit fault or a current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold value at a time when a predetermined period has elapsed from the predetermined timing.

12. The display driver according to claim 11, characterized in that the fault judgment circuit judges that a short circuit fault or a current leakage fault has occurred in at least one of the first to nth source lines when the level of the output current detection signal is greater than the predetermined threshold value.

13. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values ​​corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines; a fault determination circuit for determining whether a short circuit fault or a current leakage fault occurs in the first to n-th source lines; the first to n-th amplifier circuits are divided into first to k-th amplifier circuit groups (k is an integer equal to or greater than 2 and less than n), each of which includes at least one amplifier circuit; and first to k-th common wirings individually connected to the first to k-th amplifier circuit groups, Each of the first to n-th amplifier circuits a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage; a first transistor receiving the differential signal at its gate and sending the output current from its drain; a second transistor that receives the differential signal at its gate, and sends a mirror current that is a copy of the output current sent from the first transistor to a common wiring to which the amplifier circuit group to which the second transistor belongs is connected, among the first to kth common wirings; The failure determination circuit a multiplexer that selects one of the first to kth common wirings and connects the selected common wiring to an output node; a variable resistor connected to the output node, which generates an output current detection signal at the output node when a current obtained by combining the mirror currents sent from the second transistors of the amplifier circuits flows into the variable resistor via the first common wiring, the multiplexer, and the output node; a comparator that determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.

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