Display device and data driver

Abstract

PURPOSE: To provide a display device and a data driver with which, when driving a display panel by column inversion drive, it is possible to display an image suppressing not just flickers but also crosstalk, etc., that degrades image quality.CONSTITUTION: The present invention selectively executes a first mode in which a signal composed of data pulses appearing on a prescribed cycle, each having a positive voltage value corresponding to the luminance level of each pixel based on a video signal, is outputted as a positive grayscale data signal, and in which a signal composed of data pulses appearing in a different phase than the positive grayscale data signal on a prescribed cycle, each having a negative voltage value corresponding to the luminance level of each pixel based on a video signal is outputted as a negative grayscale data signal, and a second mode in which said positive grayscale data signal is generated, and in which a signal composed of data pulses appearing in the same phase as the positive grayscale data signal on a prescribed cycle, each having a negative voltage value corresponding to the luminance level of each pixel based on the video signal, is outputted as a negative grayscale data signal. The output modes are switched every prescribed period within the prescribed period.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device that displays an image according to a video signal, and a data driver included in the display device. [Background technology]

[0002] Currently, many large-screen display devices employ active matrix driven liquid crystal panels as display devices.

[0003] The liquid crystal panel has a plurality of data lines extending vertically across the two-dimensional screen and a plurality of gate lines extending horizontally across the two-dimensional screen, arranged to intersect with each other. Furthermore, at each intersection of the data lines and gate lines, a pixel section is formed, including pixel switches connected to the data lines and gate lines. The pixel section includes a transparent electrode independently arranged for each pixel, a counter substrate on which a single transparent electrode covering the entire two-dimensional screen of the liquid crystal panel is formed, a liquid crystal material sealed between each transparent electrode of each pixel and the counter substrate, and a backlight.

[0004] In addition to the liquid crystal panel, a liquid crystal display device includes a data driver that supplies grayscale data signals having analog voltage values ​​corresponding to the brightness level of each pixel to the data lines using data pulses per horizontal scanning period, and a gate driver that applies gate selection signals that control the on / off of pixel switches to each gate line.

[0005] In a liquid crystal display device, when a pixel switch is turned on in response to a gate selection signal sent from a gate driver, a grayscale data signal sent from a data driver is applied to the transparent electrode of the pixel section. Hereinafter, this operation will be referred to as supplying voltage to the pixel section or charging (including discharging) the pixel section. At this time, the transmittance of the liquid crystal changes depending on the potential difference between the voltage value of the grayscale data signal applied to the transparent electrode corresponding to each pixel and a fixed voltage (called the counter substrate voltage) applied to the counter substrate electrode facing the transparent electrode group across the liquid crystal layer, and a display according to the grayscale data signal is performed.

[0006] Furthermore, in order to prevent deterioration of the liquid crystal of the liquid crystal display device, polarity inversion driving is performed in which a grayscale data signal of positive polarity and a grayscale data signal of negative polarity are alternately supplied for each predetermined frame period with respect to the counter substrate voltage.

[0007] In addition, with the recent trend toward larger screens and ultra-high resolutions in liquid crystal display devices, the length of one horizontal scanning period of a video signal has become shorter, and the drive period per pixel, i.e., the period during which a gradation data signal corresponding to one pixel is supplied to a data line (also referred to as one data period), has also become shorter. As a result, the charging period for the pixel has become shorter, and in particular, there is a higher possibility of insufficient charging occurring in pixels supplied (charged) with positive gradation data signals than in pixels supplied (charged) with negative gradation data signals.

[0008] In other words, the pixel switch included in each pixel is actually a thin-film transistor, and the grayscale data signal is supplied to the pixel (transparent electrode) connected to its second terminal with a current driving capacity corresponding to the potential difference between the gate selection signal applied to its control terminal and the grayscale data signal applied to its first terminal. Therefore, the smaller the potential difference between the gate selection signal and the grayscale data signal, the smaller the current driving capacity of the pixel switch, and the slower the charging speed of the grayscale data signal to the pixel.

[0009] In this case, the voltage of the positive polarity grayscale data signal is generally higher than the voltage of the negative polarity grayscale data signal. Therefore, the potential difference between the positive polarity grayscale data signal and the gate selection signal is smaller than the potential difference between the negative polarity grayscale data signal and the gate selection signal. As a result, even if the pixels supplied (charged) with the negative polarity grayscale data signal are charged just enough within one data period, the pixels supplied (charged) with the positive polarity grayscale data signal may be undercharged, which could cause flickering or deterioration in image quality in the displayed image.

[0010] Therefore, a liquid crystal driving method has been proposed that solves the above-mentioned problem by adopting a driving method in which the polarity of the gradation data signal is inverted for each horizontal scanning line, and by making the length of one horizontal scanning period in which writing is performed with a positive polarity gradation data signal longer than the length of one horizontal scanning period in which writing is performed with a negative polarity gradation data signal (see, for example, Patent Document 1).

[0011] As LCD devices become larger and higher resolution, the data period becomes shorter and the wiring resistance and capacitance of gate and data lines increase. As a result, pixels located farther from the output terminal of the gate driver experience greater blunting of the pulse edges of the gate selection signal reaching those pixels than pixels located closer to the pixel. Furthermore, frequent charging and discharging of data lines with large potential differences due to polarity inversion increases the power consumption (heat generation) of the data driver.

[0012] Therefore, in large-screen and high-resolution liquid crystal panels, the polarity of the gradation data signal supplied to the data line is kept the same during a frame period, and the polarity is made different between adjacent data lines, and the polarity of the gradation data signal supplied to each data line is inverted on a frame-period basis, a method known as column inversion driving (also called column line inversion driving).

[0013] However, even when column inversion driving is performed, as mentioned above, even if the pixels supplied with negative polarity gradation data signals are charged without excess or deficiency, there is a risk that the pixels supplied with positive polarity gradation data signals will be insufficiently charged.

[0014] 1 is a waveform diagram showing an example of waveforms of a positive-polarity grayscale data signal Vdx and a negative-polarity grayscale data signal Vd(x+1) applied to adjacent Xth and (X+1)th data lines of a display panel, respectively, and a gate selection signal Vgk applied to a gate line by column inversion driving. In FIG. 1, the first gate line closest to the data driver is designated as GL1, and the rth gate line farthest from the data driver is designated as GLr. The gate driver sequentially outputs gate selection signals from gate line GLr toward gate line GL1. The positive-polarity grayscale data signal Vdx and negative-polarity grayscale data signal Vd(x+1) output from the data driver also correspond to the selection order of the gate selection signals, being sequentially output from grayscale data pulses Dpr and Dnr supplied to pixels in the rth row, and finally grayscale data pulses Dp1 and Dn1 supplied to pixels in the first row.

[0015] Here, the grayscale data signal has an analog voltage value (grayscale voltage) supplied to each pixel in the data line direction, and is composed of multiple grayscale data pulses per data period. Each grayscale data pulse of the positive-polarity grayscale data signal Vdx has a grayscale voltage within a voltage range from a predetermined lower limit Lpy to a higher upper limit Lpz on the higher potential side than the counter substrate voltage (hereinafter referred to as the counter substrate voltage VCOM). Meanwhile, the negative-polarity grayscale data signal Vd(x+1) has a grayscale voltage within a voltage range from a predetermined upper limit Lny to a lower lower limit Lnz on the lower potential side than the counter substrate voltage VCOM. The counter substrate voltage is generally set between the lower limit Lpy of the positive-polarity grayscale data signal and the upper limit Lny of the negative-polarity grayscale data signal. For convenience of explanation, the drawings show a driving pattern in which the grayscale data pulses of the grayscale data signals Vdx and Vd(x+1) alternately output grayscale voltages of the upper and lower limits within their respective voltage ranges every data period.

[0016] The gate selection signal Vgk is a pulse signal that transitions from a predetermined low potential VGL to a high potential VGH and is applied to the kth (k is an integer equal to or greater than 2) gate line to be selected. The gate selection signal waveform becomes dull due to impedance (wiring resistance and wiring capacitance) that corresponds to the wiring length of the gate line from the output terminal of the gate driver. Note that FIG. 1 shows an example of the waveform of the gate selection signal Vgk observed at a gate line that intersects with the Xth and (X+1)th data lines and has a relatively long wiring length from the output terminal of the gate driver. In the example shown in FIG. 1, in order to improve pixel charging efficiency, the gate selection signal Vgk maintains a high potential VGH from a data period prior to one data period in which the positive polarity grayscale data pulse Dpk and the negative polarity grayscale data pulse Dnk to be supplied to the pixels in the kth row are output to the Xth and (X+1)th data lines. As a result, as shown in FIG. 1, the pixels in the kth row to be selected are precharged by the gradation data pulses Dp(k+1) and Dn(k+1) immediately before Dpk and Dnk, which is known as gate precharge.

[0017] Here, the timing of the positive-polarity grayscale data pulse Dpk and the negative-polarity grayscale data pulse Dnk (where k is 1, 2, ..., r) is controlled by the same clock signal CLK, and their phases are the same. The phase timing of the gate selection signal Vgk and the grayscale data pulses Dpk and Dnk is determined by the relationship between the lower limit value Lnz of the amplitude of the negative-polarity grayscale data signal Vd(x+1) and the potential of the gate selection signal Vgk so that the selected pixels in the kth row are not charged by the next grayscale data pulses Dp(k-1) and Dn(k-1). In FIG. 1, the phase timing is adjusted so that the gate selection signal Vgk falls below the lower limit value Lnz at the end of one data period T1H during which the grayscale data pulse Dnk having the lower limit value Lnz of the negative-polarity grayscale data signal Vd(x+1) is supplied.

[0018] As a result, the effective pixel charging period Tn1 of the negative polarity grayscale data pulse Dnk becomes equal to one data period T1H.

[0019] On the other hand, the effective pixel charging period Tp1 of the positive polarity grayscale data pulse Dpk is determined by the grayscale data pulse Dpk at the lower limit Lpy of the dynamic range of the positive polarity grayscale data signal Vdx and the potential of the gate selection signal Vgk.

[0020] At this time, the effective pixel charging period Tp1 due to the positive polarity gradation data pulse Dpk is shorter than one data period T1H by a period Ts1 due to the rounding of the rear edge of the gate selection signal Vgk as shown in FIG. 1, and the pixel charging rate decreases by that amount.

[0021] Furthermore, as mentioned above, the potential difference between the gate selection signal Vgk and the gradation data signal also affects the pixel charging rate, and the pixel charging rate of the positive polarity gradation data signal Vdx is lower than the pixel charging rate of the negative polarity gradation data signal Vd(x+1) which has a larger potential difference.

[0022] Therefore, the charging rate based on the positive polarity grayscale data signal and the charging rate based on the negative polarity grayscale data signal do not match, causing problems such as flickering and image quality degradation in the displayed image.

[0023] In this case, when column inversion driving is performed, pixels to which positive polarity gradation data signals are supplied and pixels to which negative polarity gradation data signals are supplied are mixed along one horizontal scanning line, so the method described in Patent Document 1 cannot solve the above-mentioned problem. [Prior art documents] [Patent documents]

[0024] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-108288 Summary of the Invention [Problem to be solved by the invention]

[0025] Incidentally, when performing column inversion driving, it is conceivable that delaying the phase of the negative gradation data signal relative to the positive gradation data signal can reduce the difference between the pixel charging rate resulting from a gate selection signal with dullness in the rear edge portion and a negative gradation data signal, and the pixel charging rate resulting from the gate selection signal and a positive gradation data signal.

[0026] However, when such column inversion driving is used to display an image with a gray background that includes a relatively large white square area WE in the center of the screen, as shown in Figure 2, a problem occurs in that streaks (called crosstalk) appear along the top and bottom edges of the white square area WE.

[0027] The cause of such crosstalk will be explained below with reference to FIG.

[0028] Figure 3 is a waveform diagram showing the waveforms of the data signals sent to the data lines Df and D(f+1) that pass through the white square area WE and the data lines Dg and D(g+1) that do not pass through the white square area WE, and the voltage waveform of the counter substrate voltage VCOM, while a gate selection signal is supplied to the gate line Ga along the top edge of the white square area WE shown in Figure 2. Note that the following explanation assumes that the liquid crystal material has the property that the liquid crystal transmittance increases (white display) as the voltage difference between the counter substrate voltage VCOM and each pixel electrode increases.

[0029] As shown in Fig. 3, in the data line Df, the level of the positive polarity gradation data signal rises from a level Vp_gy representing gray to a level Vp_wt representing white at time Tp. Also, in the data line D(f+1), the level of the negative polarity gradation data signal falls from a level Vn_gy representing gray to a level Vn_wt representing white at time Tn, a predetermined period after time Tp. Also, as shown in Fig. 3, in the data line Dg that does not pass through the white square area WE, the positive polarity gradation data signal maintains the level Vp_gy, and in the data line D(g+1) that does not pass through the white square area WE, the negative polarity gradation data signal maintains the level Vn_gy.

[0030] At this time, the counter substrate voltage VCOM experiences large, wide voltage fluctuations due to capacitive coupling within the LCD panel in response to the rising edge of the positive-polarity grayscale data signal applied to data line Df and the falling edge of the negative-polarity grayscale data signal applied to data line D(f+1), as shown in Figure 3. The magnitude of the voltage fluctuation in the counter substrate voltage VCOM depends on the width of the white square area WE edge (the number of data lines that cause a voltage change at the edge of the white square area WE), the timing difference between the positive-polarity and negative-polarity grayscale data signals' transitions to the voltage level representing white, and the speed of the voltage level change (the magnitude of the slew rates of the positive and negative output amplifiers). The voltage fluctuation in the counter substrate voltage VCOM that occurs at the edge of the white square area WE also propagates within the panel surface to which the counter substrate electrodes are connected. As a result, if the potential difference between the pixel electrode and the counter substrate electrode at the intersection of the data lines Dg and D(g+1), which do not pass through the white square region WE, and the gate lines Ga and Gb, for example, is maintained at a value that deviates from the expected value, each pixel arranged along the gate lines Ga and Gb will have a brightness that differs from the original gray background. For example, in Figure 3, at the end of the 1H period selected by the gate line Ga, the pixel to which the positive polarity grayscale data signal from the data line Df is supplied has a voltage applied to the pixel's liquid crystal (the difference voltage between the grayscale data signal and the counter substrate voltage VCOM) lower than the expected value and maintained for one frame period, resulting in a lower brightness than the expected value. Also, the pixel to which the negative polarity grayscale data signal from the data line D(f+1) is supplied has a voltage applied to the pixel's liquid crystal higher than the expected value and maintained for one frame period, resulting in a higher brightness than the expected value, due to the increased counter substrate voltage VCOM. However, these pixels are located on the boundary where color changes occur, and because they are a bright white, humans cannot see the slight changes in brightness caused by fluctuations in the counter substrate voltage VCOM. On the other hand, at the end of the 1H period selected by the gate line Ga, for pixels to which the grayscale data signal of the data line Dg that does not pass through the white square area WE is supplied, the counter substrate voltage VCOM has risen, so the voltage applied to the liquid crystal of the pixel is maintained at a lower than expected value for one frame period, and the brightness drops below the expected value.Furthermore, for pixels receiving the grayscale data signal from data line D(g+1), the voltage applied to the pixel's liquid crystal remains higher than expected for one frame period due to the increased counter substrate voltage VCOM, resulting in higher-than-expected luminance. Because these pixels experience a luminance change of a certain level or greater, the offset between the luminance of the positive and negative polarity pixels in the nonlinear gamma characteristic shifts. Furthermore, because these pixels are located in the gray display region, where human visual sensitivity is high, the difference in luminance from the surrounding area becomes more noticeable. As a result, as shown in Figure 2, streaks of unevenness appear as crosstalk along the gate lines Ga and Gb on the gray background. Note that if the voltage fluctuation of the counter substrate voltage VCOM is large and extends over multiple data periods, streaks of unevenness as crosstalk may also appear in pixels along the gate line selected after the gate lines Ga and Gb.

[0031] Therefore, an object of the present invention is to provide a display device and a data driver that can display images while suppressing image quality degradation such as not only flicker but also crosstalk when driving a display panel by column inversion driving. [Means for solving the problem]

[0032] A display device according to the present invention comprises a display panel including a plurality of data lines consisting of first and second data line groups, and a plurality of gate lines arranged to intersect with the plurality of data lines; a gate driver that supplies a gate selection signal to each of the plurality of gate lines; and a plurality of data drivers provided for each predetermined number of data lines, each of which generates, in response to a video signal, a positive gradation data signal higher than a predetermined reference voltage and a negative gradation data signal lower than the reference voltage, and alternately performs an operation of supplying the positive gradation data signal to the first data line group and the negative gradation data signal to the second data line group, and an operation of supplying the positive gradation data signal to the second data line group and the negative gradation data signal to the first data line group, wherein the data driver generates data pulses, each having a positive voltage value corresponding to a luminance level of each pixel based on the video signal, at a predetermined period. and a control unit that selectively executes a first output mode in which a signal is output as the positive gradation data signal and a signal in which data pulses having negative voltage values ​​corresponding to the luminance levels of each pixel based on the video signal appear at the predetermined period in a different phase from the positive gradation data signal, and that outputs as the negative gradation data signal a signal in which data pulses having positive voltage values ​​corresponding to the luminance levels of each pixel based on the video signal appear at the predetermined period in a different phase from the positive gradation data signal, and that outputs as the negative gradation data signal a signal in which data pulses having positive voltage values ​​corresponding to the luminance levels of each pixel based on the video signal appear at the predetermined period in a different phase from the positive gradation data signal, and that outputs as the negative gradation data signal a signal in which data pulses having negative ... switches from the first output mode to the second output mode or from the second output mode to the first output mode within each predetermined period.

[0033] A data driver according to the present invention is a data driver that generates and outputs a plurality of positive grayscale data signals having a positive voltage value higher than a predetermined reference voltage and a plurality of negative grayscale data signals having a negative voltage value lower than the reference voltage in response to a video signal, and outputs signals in which data pulses each having a positive voltage value corresponding to a luminance level of each pixel based on the video signal appear at a predetermined cycle as the positive grayscale data signals, and signals in which data pulses each having a negative voltage value corresponding to a luminance level of each pixel based on the video signal appear at the predetermined cycle in a phase different from that of the positive grayscale data signals as the negative grayscale data signals. and a second output mode in which a signal in which data pulses each having a positive voltage value corresponding to a luminance level of each pixel based on the video signal appear at a predetermined period as the positive gradation data signal and a signal in which data pulses each having a negative voltage value corresponding to a luminance level of each pixel based on the video signal appear at the predetermined period in the same phase as the positive gradation data signal are output as the negative gradation data signal, and the control unit switches from the first output mode to the second output mode or from the second output mode to the first output mode within each predetermined period. [Effects of the Invention]

[0034] In the present invention, when the polarity of a grayscale data signal based on a video signal is inverted every frame period by column inversion driving and output to each data line of a display panel, the following first output mode and second output mode are selectively switched and executed.

[0035] In the first output mode, the phase of the negative grayscale data signal is shifted in a delayed direction relative to the positive grayscale data signal. This makes it possible to reduce the difference between the pixel charging rate due to the negative grayscale data signal and the pixel charging rate due to the positive grayscale data signal, even when the rear edge of the gate selection signal applied to the gate line of the display panel is dulled. Therefore, the first output mode makes it possible to suppress flicker and image quality degradation caused by the difference between the pixel charging rate due to the negative grayscale data signal and the pixel charging rate due to the positive grayscale data signal.

[0036] On the other hand, in the second output mode, the phases of the positive and negative gradation data signals are made the same. In the second output mode, a difference occurs between the pixel charging rate due to the negative gradation data signal and the pixel charging rate due to the positive gradation data signal. However, because the positive and negative gradation data signals are in phase, no crosstalk (streaks) occurs, which occurs in the first output mode when the phases of the two signals are made different.

[0037] As a result, the output of the gradation data signal in the first output mode and the output of the gradation data signal in the second output mode are alternately performed, so that the state in which crosstalk (streaks) occurs and the state in which crosstalk does not occur are visually integrated in the time direction, and the visually noticeable crosstalk (streaks) is reduced.

[0038] Therefore, according to the present invention, it is possible to display an image while suppressing image quality degradation such as flicker and crosstalk (striped unevenness). [Brief explanation of the drawings]

[0039] [Figure 1] 10A and 10B are waveform diagrams showing examples of waveforms of gate selection signals applied to gate lines and positive and negative grayscale data signals applied to a pair of adjacent data lines by conventional driving. [Figure 2]FIG. 10 is a diagram showing an example of crosstalk (streaks) that appears in an image that includes a white square area in the center of the screen against a gray background. [Figure 3] This is a waveform diagram showing the waveforms of the grayscale data signals and the counter substrate voltage applied to a pair of data lines that pass through the white square area and a pair of data lines that do not pass through the white square area, respectively, in order to display an image including a white square area in the center of the screen against a gray background. [Figure 4] FIG. 2 is a block diagram showing the configuration of a data driver 120 according to the present invention. [Figure 5A] 4 is a waveform diagram showing an example of the forms of output timing signals LOAD1 and LOAD2 in the first output mode. FIG. [Figure 5B] 10 is a waveform diagram showing an example of the forms of output timing signals LOAD1 and LOAD2 in the second output mode. FIG. [Figure 6] 10 is a time chart showing an example of the transition of the polarity state (positive polarity or negative polarity) of each of the grayscale data signals Vd1 to Vd4 output from the data driver 120. [Figure 7] 10 is a waveform diagram showing an example of the waveforms of a gate selection signal Vgk applied to a gate line and positive and negative grayscale data signals Vdx and Vd(x+1) applied to a pair of data lines in a first output mode. FIG. [Figure 8] FIG. 10 is a waveform diagram showing an example of the waveforms of a gate selection signal Vgk applied to a gate line and positive and negative grayscale data signals Vdx and Vd(x+1) applied to a pair of data lines in a second output mode. [Figure 9] 2 is a block diagram showing an example of the internal configuration of a data driver 120. FIG. [Figure 10] 1 is a diagram schematically illustrating an example of the structure of a display cell 154. FIG. [Figure 11] FIG. 10 is a diagram showing an example of a setting form of output modes for first and second data driver groups. [Figure 12] FIG. 10 is a diagram showing another example of a setting form of output modes for the first and second data driver groups. [Figure 13A]10 is a waveform diagram showing the forms of output timing signals LOAD1-Grs and LOAD2-Grs generated in the first output mode. FIG. [Figure 13B] FIG. 10 is a waveform diagram showing the forms of output timing signals LOAD1-Grs and LOAD2-Grs generated in the second output mode. DETAILED DESCRIPTION OF THE INVENTION

[0040] FIG. 4 is a block diagram showing the internal configuration of a data driver 120 according to the present invention, which drives a liquid crystal display panel in response to a video signal.

[0041] The data driver 120 receives a serial video signal DVS, generates grayscale data signals Vd1 to Vdi (i is an integer equal to or greater than 2) corresponding to the luminance levels of each pixel represented by the video signal DVS, and outputs the signals externally via output terminals T1 to Ti, respectively. The output terminals T1 to Ti are terminals for connection to the i data lines of the display panel, respectively.

[0042] The data driver 120 is formed on a semiconductor IC chip, and includes a grayscale voltage generating section 54 , a level shifter 80 , a decoder section 90 , an output amplifier section 95 , a control core section 510 , a setting storage section 600 , a timing control section 650 , and a latch section 700 .

[0043] The control core unit 510 performs deserialization, i.e., serial-to-parallel conversion, on the serial video signal DVS. Through this serial-to-parallel conversion, the control core unit 510 extracts from the video signal DVS a sequence of video data PD, digital setting information, and a clock signal CLK. The digital setting information includes output delay direction information CF, output delay shift amount information SA1 and SA2, and output start timing information TA1 and TA2.

[0044] The output delay direction information CF is information that specifies the increasing direction of the output delay time for each of the first to i-th output channels that output the gradation data signals Vd1 to Vdi, as follows: In other words, the output delay direction information CF is information that specifies whether the increasing direction of the output delay time for each of the positive and negative polarities is to increase in ascending or descending order of the output channel number, or whether the output delay time is to increase from both ends of the i output channels toward the center. The output delay shift amount information SA1 is information that indicates, for each output channel group obtained by dividing the first to i-th output channels into a plurality of groups, the delay time required from outputting a positive polarity gradation data signal corresponding to the first output channel in the output channel group to outputting a positive polarity gradation data signal corresponding to the last output channel in the output channel group, as the delay shift amount when outputting the positive polarity gradation data signal. The output delay shift amount information SA2 is information that indicates, for each of the output channel groups, the delay time required from outputting a negative polarity gradation data signal corresponding to the first output channel in the output channel group until outputting a negative polarity gradation data signal corresponding to the last output channel in the output channel group, as a delay shift amount when outputting the negative polarity gradation data signal. The output start timing information TA1 is information that specifies the output timing of the first channel for the output channel group that is responsible for outputting the positive polarity gradation data signal Vd. The output start timing information TA2 is information that specifies the output timing of the first channel for the output channel group that is responsible for outputting the negative polarity gradation data signal Vd group.

[0045] The control core unit 510 supplies the digital setting information (CF, SA1, SA2, TA1, TA2) to the setting storage unit 600, and supplies the sequence of the video data PD to the latch unit 700.

[0046] In addition, based on the video signal DVS, the control core unit 510 generates a binary (logical level 0 or 1) polarity inversion signal POL that inverts the polarity of each grayscale data signal output by the data driver 120 in frame period units, and supplies this to the latch unit 700.

[0047] Furthermore, the control core unit 510 generates a binary reference timing signal STD of one horizontal period cycle (1H cycle) based on the video signal DVS, and supplies this to the timing control unit 650.

[0048] Furthermore, the control core unit 510 causes the latch unit 700 to take in a positive polarity video signal every horizontal scanning period in response to the standard timing signal STD, and generates an output timing signal LOAD1 that indicates the timing at which the latch unit 700 should output the signal. Furthermore, the control core unit 510 causes the latch unit 700 to take in a negative polarity video signal every horizontal scanning period in response to the standard timing signal STD, and generates an output timing signal LOAD2 that indicates the timing at which the latch unit 700 should output the signal. The output timing signals LOAD1 and LOAD2 are binary signals in which, for example, a pulse having a voltage value corresponding to logic level 0 and a pulse having a voltage value corresponding to logic level 1 appear alternately every horizontal scanning period.

[0049] Here, the control core unit 510 includes an output mode setting unit that, when generating the output timing signals LOAD1 and LOAD2, sets either a first output mode in which the phase of LOAD2 is shifted in a delayed direction relative to LOAD1 as shown in Figure 5A, or a second output mode in which the phases of LOAD1 and LOAD2 are matched as shown in Figure 5B.

[0050] In the first output mode, the control core unit 510 has a function of adjusting the amount of phase shift, that is, the time length, by which the phase of the output timing signal LOAD2 is delayed relative to the output timing signal LOAD1, to any predetermined time length.

[0051] The control core unit 510 supplies the output timing signals LOAD1 and LOAD2 generated by the output mode setting unit to the timing control unit 650 and the latch unit 700.

[0052] The setting storage unit 600 takes in and stores the digital setting information (CF, SA1, SA2, TA1, TA2) supplied from the control core unit 510. The setting storage unit 600 supplies the stored digital setting information, i.e., output delay direction information CF, output delay shift amount information SA1 and SA2, and output start timing information TA1 and TA2, to the timing control unit 650. The digital setting information stored in the setting storage unit 600 is refreshed at predetermined intervals.

[0053] The timing control section 650 includes functional blocks for positive and negative polarities, and generates timing signals for outputting video data signals corresponding to the positive and negative polarities that are captured in a latch section 700 (described later).

[0054] That is, the positive polarity functional block (positive polarity timing control section) of the timing control section 650 generates an output timing signal group LOAD1-Grs of positive polarity gradation data signals based on the output delay direction information CF, the output delay shift amount information SA1, the output start timing information TA1, the reference timing signal STD, and the output timing signal LOAD1.

[0055] The negative polarity block (negative polarity timing control unit) of the timing control unit 650 generates an output timing signal group LOAD2-Grs of negative polarity gradation data signals based on the output delay direction information CF, the output delay shift amount information SA2, the output start timing information TA2, the reference timing signal STD, and the output timing signal LOAD2.

[0056] The output timing signal group LOAD1-Grs (LOAD2-Gr) is a signal group that indicates the output timing of the gradation data signal corresponding to each of the output channel groups. For example, the positive polarity timing control unit generates an output timing signal group LOAD2-Grs that indicates timing that is delayed from the output timing signal LOAD1 by a time based on the output delay direction information CF, output delay shift amount information SA1, and output start timing information TA1. The negative polarity timing control unit generates an output timing signal group LOAD2-Grs that indicates timing that is delayed from the output timing signal LOAD2 by a time based on the output delay direction information CF, output delay shift amount information SA2, and output start timing information TA2.

[0057] The timing control section 650 supplies the output timing signal groups LOAD1-Grs and LOAD2-Grs to the latch section 700.

[0058] The latch unit 700 includes a positive polarity data latch 710 and a negative polarity data latch 720. The latch unit 700 divides each video data PD in the video data PD sequence into positive polarity and negative polarity data in accordance with the polarity inversion signal POL.

[0059] The positive polarity data latch 710 receives each piece of video data PD allocated to the positive polarity in response to the output timing signal LOAD1. Then, the positive polarity data latch 710 outputs each piece of received positive polarity video data PD as video data P at the output timing set for each output channel group based on the output timing signal group LOAD1-Grs corresponding to the corresponding output channel.

[0060] The negative data latch 720 receives each of the video data PD allocated to the negative polarity in response to the output timing signal LOAD2. Then, the negative data latch 720 outputs each of the received negative video data PD as video data P at the output timing set for each predetermined output channel group based on the output timing signal group LOAD2-Grs corresponding to each corresponding output channel.

[0061] The latch section 700 supplies the i (i is an integer equal to or greater than 2) pieces of video data P output from the positive polarity data latch 710 and the negative polarity data latch 720 to the level shifter 80 as video data P1 to Pi.

[0062] The level shifter 80 performs level shift processing on each of the i pieces of video data P1 to Pi supplied from the latch unit 700 to increase the signal level (voltage amplitude) of the data, and supplies the resulting video data J1 to Ji to the decoder unit 90.

[0063] The grayscale voltage generation unit 54 generates L (L is an integer equal to or greater than 2) voltages each having a different voltage value and higher than the reference voltage as a group of positive reference voltages X1 to XL that express the luminance level of the pixel in L stages. Furthermore, the grayscale voltage generation unit 54 generates L voltages each having a different voltage value and lower than the reference voltage as a group of negative reference voltages Y1 to YL that express the luminance level of the pixel in L stages.

[0064] For example, the gradation voltage generation unit 54 generates the above-mentioned reference voltage groups X1 to XL and Y1 to YL by dividing the voltage between a predetermined high potential VGH and a predetermined low potential VGL that is lower than the high potential VGH into multiple voltages using a ladder resistor.

[0065] The reference voltage is a voltage (hereinafter referred to as a counter substrate voltage VCOM) applied to a counter substrate electrode arranged opposite to an electrode corresponding to each pixel in a display panel to be driven by the data driver 120, for example.

[0066] The grayscale voltage generating section 54 supplies the generated positive polarity reference voltages X1 to XL and negative polarity reference voltages Y1 to YL to the decoder section 90.

[0067] The decoder unit 90 has i decoders DEC that individually convert each of the video data J1 to Ji into a grayscale data signal having an analog voltage value.

[0068] Each of the decoders DEC receives a group of positive reference voltages X1 to XL and a group of negative reference voltages Y1 to YL from the grayscale voltage generation unit 54. Furthermore, each of the i decoders DEC individually receives one of the video data J1 to Ji.

[0069] When the video data J received by each decoder DEC is positive data, the decoder DEC selects one or more reference voltages from the positive reference voltage group X1 to XL specified by the video data J. On the other hand, when the video data J received by each decoder DEC is negative data, the decoder DEC selects one or more reference voltages from the negative reference voltage group Y1 to YL specified by the video data J.

[0070] The decoder section 90 outputs one or more reference voltages selected by each decoder DEC to the output amplifier section 95 as grayscale voltages corresponding to the luminance level of each pixel.

[0071] The output amplifier unit 95 has i output amplifiers (operational amplifiers) corresponding to the i decoders DEC included in the decoder unit 90. Each of the output amplifiers is a voltage follower whose output terminal and inverting input terminal (-) are connected to each other, and receives one or more reference voltages supplied from the corresponding decoder DEC at its non-inverting input terminal (+). Each of the i output amplifiers amplifies the one or more reference voltages received at its non-inverting input terminal (+) to generate pulse voltages having a voltage value corresponding to the video data J as gradation data pulses corresponding to the brightness level, and outputs these via its output terminal. The gradation data pulses are output continuously for each data period (e.g., one horizontal scanning period) within one frame period. Each of the i output amplifiers outputs a signal including a series of gradation data pulses appearing for each data period as a gradation data signal Vd to the outside via i output terminals T1 to Ti of the semiconductor IC, respectively. That is, the i grayscale data signals Vd output from the i output amplifiers are supplied to the i data lines of the display panel connected to the output terminals T1 to Ti, respectively.

[0072] The column inversion driving by the data driver 120 shown in FIG. 4 will be described in detail below.

[0073] FIG. 6 is a time chart showing an example of the state (positive polarity or negative polarity) of each of the grayscale data signals Vd1 to Vd4 output from, for example, the output terminals T1, T2, T3, and T4 of the data driver 120 by the column inversion driving.

[0074] 6, during one frame period when the polarity inversion signal POL is at logic level 1, the odd-numbered grayscale data signals Vd1 and Vd3 among the grayscale data signals Vd1 to Vd4 each have a positive polarity. Also, during one frame period when the polarity inversion signal POL is at logic level 1, the even-numbered grayscale data signals Vd2 and Vd4 each have a negative polarity.

[0075] 6, during one frame period in which the polarity inversion signal POL is at logic level 0, the odd-numbered gradation data signals Vd1 and Vd3 among the gradation data signals Vd1 to Vd4 each have negative polarity. Also, during one frame period in which the polarity inversion signal POL is at logic level 0, the even-numbered gradation data signals Vd2 and Vd4 each have positive polarity.

[0076] Furthermore, when performing such column inversion driving, the data driver 120 controls the video signal DVS to use the first output mode shown in Fig. 5A for N consecutive frame periods (N is an integer equal to or greater than 1), and to use the second output mode shown in Fig. 5B for M consecutive frame periods (M is an integer equal to or greater than 1). Furthermore, control is performed to alternately switch between N frame periods controlled in the first output mode and M frame periods controlled in the second output mode.

[0077] The output forms of the grayscale data signals in the first and second output modes will be described below with reference to the waveform diagram in the first output mode shown in FIG. 7 and the waveform diagram in the second output mode shown in FIG. 8.

[0078] 7 and 8 show examples of waveforms of a positive-polarity grayscale data signal Vdx and a negative-polarity grayscale data signal Vd(x+1) applied to adjacent data lines DLx and DL(x+1) among i data lines (hereinafter referred to as data lines DL1 to DLi) of the display panel connected to the data driver 120. Furthermore, in FIGS. 7 and 8, the waveform of a gate selection signal Vgk applied to the k-th (k is an integer from 1 to r) gate line GLk among r (r is an integer equal to or greater than 2) gate lines (hereinafter referred to as gate lines GL1 to GLr) arranged in the display panel is shown by a dashed-dotted line. That is, FIGS. 7 and 8 show the pulse waveform of the gate selection signal Vgk observed at the intersection of the gate line GLk with the data lines DLx and DL(x+1).

[0079] 7 and 8, the gate selection signal Vgk is affected by the high impedance associated with the wiring length of the gate line from the gate driver, resulting in a relatively large waveform distortion. In the example shown in FIGS. 7 and 8, the gate selection signal Vgk is subjected to gate precharge in order to increase the pixel charging rate. That is, the gate selection signal Vgk is maintained at a high potential VGH during the application period of the grayscale data pulses Dpk and Dnk corresponding to the display cells (pixels) in the kth row, as well as the grayscale data pulses Dp(k+1) and Dn(k+1) corresponding to the display cells (pixels) in the (k+1)th row, one data period before.

[0080] 7 and 8 show the waveforms of the gate selection signal Vgk and the grayscale data signal Vdx when writing (charging) based on the grayscale data pulse Dpk included in the grayscale data signal Vdx to a pixel at the intersection of the data line DLx and the gate line GLk in response to the gate selection signal Vgk. Also, Fig. 7 and 8 show the waveforms of the gate selection signal Vgk and the grayscale data signal Vd(x+1) when writing (charging) based on the grayscale data pulse Dnk included in the grayscale data signal Vd(x+1) in response to the gate selection signal Vgk.

[0081] 7 and 8, each of the grayscale data pulses Dp included in the positive-polarity grayscale data signal Vdx has a grayscale voltage within a voltage range from a lower limit Lpy to an upper limit Lpz. Similarly, each of the grayscale data pulses Dn included in the negative-polarity grayscale data signal Vd(x+1) has a grayscale voltage within a voltage range from an upper limit Lny to a lower limit Lnz. In FIGS. 7 and 8, the counter substrate voltage VCOM is set between the lower limit Lpy of the positive-polarity grayscale data signal and the upper limit Lny of the negative-polarity grayscale data signal. For ease of explanation, FIGS. 7 and 8 show a drive pattern in which the grayscale data pulses included in the grayscale data signals Vdx and Vd(x+1) alternate between upper and lower limit grayscale voltages within their respective voltage ranges every data period.

[0082] [First output mode] As shown in FIG. 7, in the first output mode, the output timings of the gradation data signals Vdx and Vd(x+1) are controlled in accordance with the output timing signal groups LOAD1-Grs and LOAD2-Grs so that the positive polarity gradation data pulse Dpk and the negative polarity gradation data pulse Dnk have different timings.

[0083] That is, in the first output mode, as shown in FIG. 7, the phase of the negative grayscale data pulse Dnk is delayed by a predetermined phase shift with respect to the positive grayscale data pulse Dpk.

[0084] The timing control of the positive polarity grayscale data signal Vdx and the gate selection signal Vgk will be described below.

[0085] The data driver 120 sets the output timing of the positive polarity gradation data signal Vdx as follows so that the gradation data pulse Dp(k-1) in the data period following the gradation data pulse Dpk is not supplied to the display cell (pixel) by the gate selection signal Vgk:

[0086] That is, the data driver 120 outputs the positive polarity grayscale data signal Vdx at a timing such that the potential of the rear edge of the gate selection signal Vgk becomes equal to or lower than the lower limit Lpy of the positive polarity grayscale data pulse Dpk at the time of the rear edge of the positive polarity grayscale data pulse Dpk, as shown in Fig. 7. For example, the phase of the positive polarity grayscale data signal Vdx may be adjusted by the timing control unit 650 to achieve such an output form.

[0087] This allows the effective pixel charging period by the positive polarity grayscale data pulse Dpk to be set to a pixel charging period Tp2 equivalent to one data period T1H, as shown in FIG.

[0088] As shown in FIG. 7, the data driver 120 shifts the phase of the negative grayscale data signal Vd(x+1) in a direction that delays the phase of the positive grayscale data signal Vdx by a time length Ts21.

[0089] As a result, the data driver 120 outputs a negative grayscale data signal Vd(x+1) synchronized with the output timing signal group LOAD2-Grs, whose phase is delayed by a time length Ts21 relative to the positive grayscale data signal Vdx synchronized with the output timing signal group LOAD1-Grs, as shown in Fig. 7. As a result, as shown in Fig. 7, the potential of the rear edge portion of the gate selection signal Vgk becomes equal to or lower than the lower limit Lpy of the grayscale data pulse Dnk at a point before the rear edge of the negative grayscale data pulse Dnk included in the negative grayscale data signal Vd(x+1).

[0090] Therefore, the effective pixel charging period by the negative polarity grayscale data pulse Dnk is a pixel charging period Tn2 that is shorter than one data period T1H by a time length Ts22 (≧0), as shown in Figure 7. The effect of this time length Ts22 is as follows.

[0091] Since the potential difference between the gate selection signal Vgk and the gradation data signal is larger for negative polarity than for positive polarity, the pixel charging rate for negative polarity is higher even during the same pixel charging period. Therefore, a time length Ts22 is provided as an adjustment period for the difference in pixel charging rate between positive polarity and negative polarity due to the potential difference between the gate selection signal Vgk and the gradation data signal.

[0092] In other words, the above-described driving ensures that the effective pixel charging period Tp2 by the positive polarity gradation data pulse Dpk is equal to one data period T1H, and also makes it possible to make the effective pixel charging period Tn2 by the negative polarity gradation data pulse Dnk equal to or shorter than one data period T1H.

[0093] Therefore, it is possible to make the pixel charging period Tp2 by the positive polarity gradation data pulse Dpk longer than the pixel charging period Tp1 shown in Figure 1, and to make the pixel charging period Tn2 by the negative polarity gradation data pulse Dnk shorter than the pixel charging period Tn1 shown in Figure 1.

[0094] In this way, by adjusting the pixel charging rate by the negative polarity gradation data signal downward while increasing the pixel charging rate by the positive polarity gradation data signal, the difference between the pixel charging rate by the negative polarity gradation data signal and the pixel charging rate by the positive polarity gradation data signal is reduced.

[0095] This makes it possible to suppress flicker and image quality degradation that occurs due to the difference between the pixel charging rate due to a negative polarity gradation data signal and the pixel charging rate due to a positive polarity gradation data signal, even if the pulse edge of the gate selection signal is dulled.

[0096] [Second Output Mode] As shown in FIG. 8, in the second output mode, the output timings of the gradation data signals Vdx and Vd(x+1) are controlled in accordance with the output timing signal groups LOAD1-Grs and LOAD2-Grs so that the positive polarity gradation data pulse Dpk and the negative polarity gradation data pulse Dnk have the same timing.

[0097] Therefore, in the second output mode shown in FIG. 8, although there is a difference between the pixel charging rate due to the negative gradation data signal and the pixel charging rate due to the positive gradation data signal, the positive gradation data signal and the negative gradation data signal are in phase, so there is no crosstalk (streaks) that occurs in the first output mode when the phases of the two signals are made different.

[0098] Here, the data driver 120 outputs the gradation data signal in the first output mode shown in FIG. 7 for N consecutive frame periods (N is an integer equal to or greater than 1), and outputs the gradation data signal in the second output mode shown in FIG. 8 for M consecutive frame periods (M is an integer equal to or greater than 1), alternately switching between the N frame periods in which the signal is controlled in the first output mode and the M frame periods in which the signal is controlled in the second output mode.

[0099] As a result, the state in which crosstalk (streaks) occurs (first output mode) and the state in which crosstalk does not occur (second output mode) as shown in Figure 2 are visually integrated in the time direction, thereby reducing the visible crosstalk (streaks).In addition, by adjusting the number of frame periods N and M, it is possible to adjust the ratio of the control periods for the first output mode and the second output mode, thereby making it possible to maximize the effect of reducing crosstalk (streaks).

[0100] Therefore, the data driver 120 makes it possible to display an image while suppressing image quality degradation such as flicker and crosstalk (streaks).

[0101] In the above embodiment, the data driver 120 uniformly sets all output channels in each frame to one of the first and second output modes, but it is also possible to mix a group of output channels set to the first output mode and a group of output channels set to the second output mode in each frame.

[0102] That is, the i gradation data signals output from the output terminals T1 to Ti are divided into a first gradation data signal group and a second gradation data signal group. Then, in each frame, the positive and negative gradation data signals belonging to the first gradation data signal group are output in a first output mode, and the positive and negative gradation data signals belonging to the second gradation data signal group are output in a second output mode. Furthermore, at this time, the output mode for outputting the first gradation data signal group and the output mode for outputting the second gradation data signal group are switched every N frames.

[0103] From the above, the data driver 120 may include the following control unit to generate and output a plurality of positive polarity gradation data signals having a positive polarity voltage value higher than a predetermined reference voltage (VCOM) and a plurality of negative polarity gradation data signals having a negative polarity voltage value lower than this reference voltage in accordance with the video signal (DVS).

[0104] The control unit (510, 650, 700) selectively executes the following first output mode and second output mode, and outputs a positive polarity gradation data signal and a negative polarity gradation data signal by switching from the first output mode to the second output mode or from the second output mode to the first output mode every predetermined period within the predetermined period.

[0105] In the first output mode (FIG. 7), a signal in which data pulses (Dp) each having a positive voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period (T1H) is output as the positive gradation data signal (Vdx), and a signal in which data pulses each having a negative voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period in a different phase from the positive gradation data signal is output as the negative gradation data signal [Vd(x+1)].On the other hand, in the second output mode, a signal in which data pulses each having a positive voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period in the same phase as the positive gradation data signal is output as the positive gradation data signal, and a signal in which data pulses each having a negative voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period in the same phase as the positive gradation data signal is output as the negative gradation data signal.

[0106] FIG. 9 is a block diagram showing the configuration of a liquid crystal display device 10 as a display device according to the present invention, including the above-described data driver 120.

[0107] As shown in FIG. 9, the liquid crystal display device 10 includes a display controller 100, a gate driver 110, data drivers 120-1 to 120-p (p is an integer of 2 or more), each of which is a data driver 120, and a display panel 150.

[0108] The display panel 150 is arranged with gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen and data lines DL1 to DLm (m is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen, and these lines intersect. At each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLm, a display cell 154 serving as a unit pixel is formed. The entire area where the data lines DL1 to DLm and gate lines GL1 to GLr are arranged serves as the display screen of the display panel 150.

[0109] FIG. 10 is a diagram showing a schematic structure of the display cell 154. As shown in FIG.

[0110] As shown in Fig. 10, the display cell 154 includes a pixel electrode C1, a liquid crystal layer C2, and a counter substrate electrode C3, which are stacked one on top of the other, and a thin-film transistor TR as a pixel switch. Fig. 3 shows an example of an n-channel thin-film transistor. The pixel electrode C1 is a transparent electrode provided independently for each display cell 154, and the counter substrate electrode C3 is a single transparent electrode that covers the entire surface of the display panel 150. A control terminal of the thin-film transistor TR is connected to the gate line GL, and a first terminal of the thin-film transistor TR is connected to the data line DL. Furthermore, a second terminal of the thin-film transistor TR is connected to the pixel electrode C1. A counter substrate voltage VCOM is applied to the counter substrate electrode C3 as a reference potential.

[0111] The display controller 100 receives a video signal VD and supplies, to the gate driver 110, a gate timing signal that indicates the timing at which to apply a gate selection signal to each of the gate lines GL1 to GLr, based on the video signal VD.

[0112] Furthermore, the display controller 100 generates a clock signal and a sequence of video data PD indicating the luminance level of each pixel based on the video signal VD, and also generates the digital setting information as described above corresponding to each of the data drivers 120-1 to 120-p. The display controller 100 also includes an output mode designation unit that generates an output mode designation signal that designates whether the display should be set to the first output mode or the second output mode.

[0113] The display controller 100 supplies the digital video signal DVS, which includes the clock signal, the video data PD sequence, the digital setting information, and the output mode designation signal generated as described above, to the data drivers 120-1 to 120-p. In the liquid crystal display device 10, in order to reduce the number of wires between the display controller 100 and each of the data drivers 120-1 to 120-p, the display controller 100 supplies the video signal DVS to each data driver in the form of a serial signal.

[0114] The gate driver 110 sequentially generates gate selection signals Vg1 to Vgr (r is an integer equal to or greater than 2) in response to a gate timing signal supplied from the display controller 100, each including at least one pulse for selecting a gate line, and outputs the signals individually from r output terminals. The gate driver 110 supplies the gate selection signals Vg(r) to Vg1 output from the r output terminals to the gate lines GL1 to GLr of the display panel 150, respectively. Note that, although the gate driver 110 is arranged only on one end side of the gate lines GL1 to GLr of the display panel 150 in the example shown in FIG. 9, a pair of gate drivers 110 may be arranged on both ends of the gate lines GL1 to GLr, respectively.

[0115] The data drivers 120-1 to 120-p are provided corresponding to the first to pth data line groups, each of which is formed by dividing the data lines DL1 to DLm of the display panel 150 into adjacent i data lines, and each of the output terminals T1 to Ti is connected to the i data lines belonging to the corresponding data line group.

[0116] 9, the data driver 120-1 is connected to data lines DL1 to DLi that drive a plurality of display cells 154 that are arranged in an area on each of the gate lines GL1 to GLr of the display panel 150 where the wiring length from the output terminal of the gate driver 110 is relatively short. Also, as shown in FIG. 9, the data driver 120-p is connected to data lines DLx (x is 2 or more) to DLm that drive a plurality of display cells 154 that are arranged in an area on each of the gate lines GL1 to GLr of the display panel 150 where the wiring length from the output terminal of the gate driver 110 is relatively long.

[0117] With this configuration, the data drivers 120-1 to 120-p take in a series of video data PD included in the video signal DVS for one horizontal scanning line (m pieces) at a time, and convert each video data PD into a gradation data signal having an analog voltage value corresponding to a luminance level. Then, the data drivers 120-1 to 120-p supply the generated gradation data signals Vd1 to Vd(m) to the data lines DL1 to DLm of the display panel 150, respectively.

[0118] Here, the output mode setting section of each of the data drivers 120-1 to 120-p sets each data driver individually to the first output mode or the second output mode based on the output mode designation signal and digital setting information supplied from the display controller 100.

[0119] For example, in the liquid crystal display device 10, the data drivers 120-1 to 120-p are divided into a first data driver group and a second data driver group, and each of the data drivers belonging to the first data driver group is set to the first output mode, and each of the data drivers belonging to the second data driver group is set to the second output mode, as shown in Fig. 11. That is, by mixing an area driven in the first output mode and an area driven in the second output mode within one frame of the display panel 150, the amount of fluctuation in the counter substrate voltage VCOM in a display pattern in which crosstalk is easily visible, as shown in Fig. 2, is suppressed.

[0120] Furthermore, one of the first and second output modes set in the first and second data driver groups, respectively, may be switched to the other output mode every N (N is an integer equal to or greater than 2) frame periods, as shown in FIG. 12. Furthermore, the allocation of the data drivers 120-1 to 120-p, which are divided into the first data driver group and the second data driver group, may be changed every N frame periods.

[0121] In the liquid crystal display device 10, regardless of the first or second output mode, the delay time of the output timing of the output timing signal group LOAD1-Grs, which indicates the output timing of the positive polarity gradation data signal Vd, starting from the rising (or falling) edge of the reference timing signal STD, is controlled for each of the data drivers 120-1 to 120-p.

[0122] The following describes the output timing signal groups LOAD1-Grs and LOAD2-Grs generated by the data drivers 120-1 and 120-p selected from the data drivers 120-1 to 120-p. As shown in Fig. 9, the data driver 120-1 is arranged closest to the gate driver 110, and the data driver 120-p is arranged farthest from the gate driver 110.

[0123] Fig. 13A is a timing chart showing the timing of the output timing signals LOAD1-Grs and LOAD2-Grs of the data drivers 120-1 and 120-p in the first output mode, and Fig. 13B is a timing chart showing the timing of the output timing signals LOAD1-Grs and LOAD2-Grs of the data drivers 120-1 and 120-p in the second output mode.

[0124] 13A and 13B, in the data driver 120-1, the timing control section 650 supplies the positive polarity data latch 710 with a group of output timing signals LOAD1-Grs, in which a pulse indicating output timing appears at a time Ts30 elapsed from each rising edge of the reference timing signal STD. On the other hand, in the data driver 120-p, the timing control section 650 supplies the positive polarity data latch 710 with a group of output timing signals LOAD1-Grs, in which a pulse indicating output timing appears at a time Ts20 elapsed from each rising edge of the reference timing signal STD. In this case, the time Ts20 is longer than the time Ts30 in the data driver 120-1.

[0125] 13A, in the first output mode, the timing control section 650 of the data driver 120-1 supplies, to the negative data latch 720, an output timing signal group LOAD2-Grs in which a pulse indicating output timing appears when a time length Ts31 has elapsed since each pulse in the output timing signal group LOAD1-Grs. In the first output mode, the timing control section 650 of the data driver 120-p supplies, to the negative data latch 720, an output timing signal group LOAD2-Grs in which a pulse indicating output timing appears when a time length Ts21 has elapsed since each pulse in the output timing signal group LOAD1-Grs.

[0126] That is, compared to the data driver 120-1, the wiring length of each gate line of the data driver 120-p that is wired between the data line group that the data driver 120-p drives and the output terminal group of the gate driver 110 is longer. Therefore, the fall (rise) time of the gate selection signal Vgk observed in the display cell 154 connected to the data line group (DLx to DLm) that the data driver 120-p drives is longer than that of the data line group (DL1 to DLi) that the data driver 120-1 drives.

[0127] Therefore, in the liquid crystal display device 10, regardless of the first or second output mode, the output timing of the grayscale data signal output from the data driver 120-p is controlled to be delayed from the output timing of the grayscale data signal output from the data driver 120-1 so as to follow the falling (rising) time of such a gate selection signal Vgk. Specifically, the time length Ts20 (Ts21) of the output timing signal group LOAD1-Grs (LOAD2-Grs) generated by the data driver 120-p is controlled to be longer than the time length Ts30 (Ts31) of the output timing signal group LOAD1-Grs (LOAD2-Grs) generated by the data driver 120-p.

[0128] Furthermore, the time length Ts31 of the phase shift in the delay direction of the negative polarity grayscale data signal relative to the positive polarity grayscale data signal output from the data driver 120-1 is set shorter than the time length Ts21 of the phase shift in the delay direction of the negative polarity grayscale data signal relative to the positive polarity grayscale data signal output from the data driver 120-p. That is, in the liquid crystal display device 10, each data driver 120 is set so that the shorter the wiring length of the gate line wired between the data line receiving the grayscale data signal and the output terminal of the gate driver 110, the shorter the time length of the phase shift of the negative polarity grayscale data signal relative to the positive polarity grayscale data signal.

[0129] By adjusting the output timing of the positive and negative polarity gradation data signals as described above, the liquid crystal display device 10 suppresses fluctuations in pixel charging rates that are caused by differences in the wiring lengths of the gate lines between the output terminals of the gate driver 110 and each pixel.

[0130] In the above embodiment, the output mode designation unit of the display controller 100 controls each of the data drivers 120-1 to 120-p to be set to the first or second output mode in accordance with a fixed or predetermined sequence as shown in FIG. 11 or FIG. 12.

[0131] However, the display controller 100 may control the data drivers 120-1 to 120-p to set the first or second output mode for each of a plurality of regions that divide each frame based on the video signal VD. [Explanation of symbols]

[0132] 120 Data Driver 150 Display Panel 510 Control Core 650 Timing control section 700 Latch section

Claims

1. a display panel including a plurality of data lines consisting of first and second data line groups, and a plurality of gate lines arranged to intersect with the plurality of data lines; a gate driver that supplies a gate selection signal to each of the plurality of gate lines; a plurality of data drivers provided for each predetermined number of data lines, each of which generates, in response to a video signal, a positive gradation data signal higher than a predetermined reference voltage and a negative gradation data signal lower than the reference voltage, and alternately repeats an operation of supplying the positive gradation data signal to the first data line group and the negative gradation data signal to the second data line group, and an operation of supplying the positive gradation data signal to the second data line group and the negative gradation data signal to the first data line group; The data driver a first output mode in which a signal in which data pulses each having a positive voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period is output as the positive gradation data signal, and a signal in which data pulses each having a negative voltage value corresponding to the luminance level of each pixel based on the video signal appear at the predetermined period in a phase different from that of the positive gradation data signal is output as the negative gradation data signal; a first output mode in which a signal in which data pulses each having a positive voltage value corresponding to a luminance level of each pixel based on the video signal appear at a predetermined period as the positive gradation data signal, and a second output mode in which a signal in which data pulses each having a negative voltage value corresponding to a luminance level of each pixel based on the video signal appear at the predetermined period in the same phase as the positive gradation data signal, is output as the negative gradation data signal, and a control unit which switches from the first output mode to the second output mode or from the second output mode to the first output mode within each predetermined period.

2. 2. The display device according to claim 1, wherein the negative polarity grayscale data signal in the first output mode is a signal whose phase is shifted in a direction lagging behind the phase of the positive polarity grayscale data signal.

3. 3. The display device according to claim 2, wherein the control unit has a function of adjusting the time length of the phase shift.

4. 4. The display device according to claim 2, wherein the control unit shortens the time length of the phase shift of the negative polarity grayscale data signal relative to the positive polarity grayscale data signal as the wiring length of the gate line wired between the data line receiving the grayscale data signal and the output terminal of the gate driver becomes shorter.

5. The display device according to any one of claims 1 to 4, characterized in that the control unit controls the N (N is an integer equal to or greater than 1) frame period of the video signal to the first output mode, controls the M (M is an integer equal to or greater than 1) frame period of the video signal to the second output mode, and alternately switches between the N frame period and the M frame period.

6. The display device according to any one of claims 1 to 4, characterized in that the control unit divides all of the gradation data signals output to the first data line group and the second data line group into a first gradation data signal group and a second gradation data signal group, and in each frame, outputs the positive polarity gradation data signals and the negative polarity gradation data signals belonging to the first gradation data signal group in the first output mode, and outputs the positive polarity gradation data signals and the negative polarity gradation data signals belonging to the second gradation data signal group in the second output mode.

7. The display device of any one of claims 1 to 4, characterized in that, within each frame of the video signal, the control unit included in at least one data driver among the plurality of data drivers executes one of the first output mode and the second output mode, and the control unit included in another one of the plurality of data drivers executes the other of the first output mode and the second output mode.

8. 8. The display device according to claim 6, wherein the control unit switches the first output mode and the second output mode from one state to the other state, or from the other state to the one state, every N (N is an integer greater than or equal to 1) frame periods of the video signal.

9. 9. The display device according to claim 1, further comprising a display controller that superimposes an output mode designation signal that designates the first output mode or the second output mode on the video signal and supplies the superimposed signal to the data driver.

10. A data driver that generates and outputs a plurality of positive polarity gray scale data signals having a positive polarity voltage value higher than a predetermined reference voltage and a plurality of negative polarity gray scale data signals having a negative polarity voltage value lower than the reference voltage in response to a video signal, a first output mode in which a signal in which data pulses each having a positive voltage value corresponding to the luminance level of each pixel based on the video signal appear at a predetermined period is output as the positive gradation data signal, and a signal in which data pulses each having a negative voltage value corresponding to the luminance level of each pixel based on the video signal appear at the predetermined period in a phase different from that of the positive gradation data signal is output as the negative gradation data signal; a first output mode in which a signal in which data pulses each having a positive voltage value corresponding to a luminance level of each pixel based on the video signal appear at a predetermined period as the positive gradation data signal, and a second output mode in which a signal in which data pulses each having a negative voltage value corresponding to a luminance level of each pixel based on the video signal appear at the predetermined period in the same phase as the positive gradation data signal, is output as the negative gradation data signal, and a control unit which switches from the first output mode to the second output mode or from the second output mode to the first output mode within each predetermined period.

11. 11. The data driver according to claim 10, wherein the negative grayscale data signal in the first output mode is a signal whose phase is shifted in a delayed direction relative to the phase of the positive grayscale data signal.

12. 12. The data driver according to claim 11, wherein the control unit has a function of adjusting the time length of the phase shift.

13. The data driver outputs the positive polarity grayscale data signal or the negative polarity grayscale data signal to each of a plurality of data lines of a display panel including a plurality of data lines consisting of first and second data line groups and a plurality of gate lines arranged to intersect with the plurality of data lines; The data driver according to any one of claims 10 to 12, characterized in that the control unit shortens the time length of the phase shift of the negative polarity gradation data signal relative to the positive polarity gradation data signal as the wiring length of the gate lines wired from the data line receiving the gradation data signal to the output terminal of the gate driver that supplies a gate selection signal to each of the plurality of gate lines becomes shorter.

14. The data driver according to any one of claims 10 to 13, characterized in that the control unit controls the N (N is an integer greater than or equal to 1) frame period of the video signal to the first output mode, controls the M (M is an integer greater than or equal to 1) frame period of the video signal to the second output mode, and alternately switches between the N frame period and the M frame period.

15. 14. The data driver according to claim 13, wherein the control unit divides all the gradation data signals to be output to the first data line group and the second data line group into a first gradation data signal group and a second gradation data signal group, and outputs the positive polarity gradation data signals and the negative polarity gradation data signals belonging to the first gradation data signal group in the first output mode and outputs the positive polarity gradation data signals and the negative polarity gradation data signals belonging to the second gradation data signal group in the second output mode within each frame.

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