Systems and methods for coupling between qubits

Abstract

The superconducting integrated circuit includes a first superconducting device having a first superconducting loop with a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device having a second superconducting loop with a second superconducting trace in a second layer, the first superconducting loop intersecting the second superconducting loop at an intersection region, at least a portion of each of the first and second superconducting traces inside the intersection region being narrower than at least a portion of each of the traces outside the intersection region, and following respective circuitous paths in inductive proximity to at least a portion of the other path.

Description

[Technical Field]

[0001] background Field This disclosure relates generally to improving the performance of quantum processors, and more particularly to coupling between qubits in superconducting quantum processors. [Background technology]

[0002] quantum devices Quantum devices are structures in which quantum mechanical effects can be observed. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics, which use electron spin as a resource, and superconducting circuits. Both spin and superconductivity are examples of quantum mechanical phenomena. Quantum devices can be used, for example, in instrumentation and computing systems.

[0003] quantum computing Quantum computing and quantum information processing encompass several types of marketable products. A quantum computer is a system that directly uses quantum mechanical phenomena (e.g., superposition, tunneling, and quantum entanglement) to perform calculations on data.

[0004] Data can be represented in a quantum computer by quantum binary digits (also referred to in this application as qubits). Quantum computers can provide exponential speedups for certain types of computational problems (e.g., quantum physics simulations). Advantageous speedups can exist for other types of problems.

[0005] In some implementations, the quantum computer includes a quantum circuit model. In other implementations, the quantum computer includes an adiabatic quantum computer. Adiabatic quantum computers can be useful, for example, for solving NP-hard optimization problems.

[0006] Adiabatic quantum computing Adiabatic quantum computing typically involves evolving a system from a known initial Hamiltonian (a Hamiltonian is an operator whose eigenvalues ​​are the allowed energies of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of adiabatic evolution is linear interpolation between the initial and final Hamiltonian. An example is given below: H e =(1-s)H i +sH f However, H i is the initial Hamiltonian, and H f is the final Hamiltonian, and H e is the evolution or instantaneous Hamiltonian, and s is the evolution coefficient that controls the rate of evolution. As the system evolves, initially (s=0), the evolution Hamiltonian H e is the initial Hamiltonian H i and finally (s=1), the evolution Hamiltonian H e is the final Hamiltonian H f The evolution coefficient s goes from 0 to 1 so that it is equal to

[0007] Before evolution begins, the system typically has an initial Hamiltonian H i The goal is to initialize the system to the ground state of f The goal is to evolve the system in such a way that the ground state of the system is reached. If the evolution is too fast, the system may be excited to a higher energy state (e.g., the first excited state).

[0008] In this application, adiabatic evolution is defined as evolution that satisfies the adiabatic condition expressed as follows:

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[0009] The process of changing the Hamiltonian in adiabatic quantum computation is referred to in this application as evolution. The rate of change of the evolution coefficient s is determined by the evolution Hamiltonian H e and desirably slow enough to avoid transitions at anticrossings (when the gap size is minimal). The evolution schedule may be linear, nonlinear, parametric, etc. Further details regarding adiabatic quantum computing systems, methods, and apparatus are described, for example, in U.S. Patent Nos. 7,135,701 and 7,418,283.

[0010] quantum annealing Quantum annealing is a computational method that can be used to find a low-energy state of a system, typically preferably the ground state of the system. Similar in concept to classical annealing, quantum annealing relies on the fundamental principle that natural systems tend toward lower-energy states because lower-energy states are more stable. While classical annealing uses classical thermal fluctuations to guide a system toward a low-energy state (ideally, a global energy minimum), quantum annealing can use quantum effects (e.g., quantum tunneling) to reach the global energy minimum more accurately and / or more quickly than classical annealing. In quantum annealing, thermal effects and other noise may be present to assist the annealing. The final low-energy state may not be a global energy minimum.

[0011] Adiabatic quantum computing can be thought of as a special case of quantum annealing, in which the system ideally starts and remains in the ground state throughout its adiabatic evolution.

[0012] Those skilled in the art will recognize that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this specification and the appended claims, any reference to quantum annealing is intended to include adiabatic quantum computing unless the context requires otherwise.

[0013] Quantum annealing can use quantum mechanics as a source of disorder during the annealing process. To solve an optimization problem using quantum annealing, we define the optimization problem as a Hamiltonian of the problem, H P The algorithm then encodes the problem Hamiltonian H P The disordered Hamiltonian H does not commute with D By adding

[0014] An example of evolution is as follows: H E ∝A(t)H D +B(t)H p where A(t) and B(t) are time-dependent envelope functions, and H E is the evolutionary Hamiltonian (the evolutionary Hamiltonian H e (similar to ).

[0015] The disordered Hamiltonian H D The disorder may be removed or at least reduced by removing or at least reducing the effect of (i.e., reducing A(t)). The disorder may be first added and then removed. In some implementations, a time-varying envelope function is placed into the problem Hamiltonian. A general disordered Hamiltonian H D can be expressed as follows:

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[0016] General Problem Hamiltonian H P contains a first component proportional to the diagonal single-qubit term and a second component proportional to the diagonal multi-qubit term. The problem Hamiltonian can be expressed, for example, as follows:

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[0017] where σ i z and σ i z σ j z The term is an example of a diagonal term. i z is a single qubit term, and σ i z σ j z is a two-qubit term. In this application, we use the terms "problem Hamiltonian" and "final Hamiltonian" interchangeably.

[0018] The Hamiltonian in the above equation (e.g., H D and H P ) may be physically realized in a variety of different ways. A particular example is realized by the implementation of a superconducting qubit (e.g., a superconducting flux qubit).

[0019] Quantum annealing of a system is performed by annealing a system starting with an initial Hamiltonian and annealing it to a final (problem) Hamiltonian H, whose ground state encodes the solution to the problem. P This is similar to adiabatic quantum computing, where the system evolves via an evolutionary Hamiltonian H. If the evolution is slow enough, the system will typically settle to a global minimum (i.e., the exact solution) or a local minimum in energy close to the exact solution. The performance of the computation may be evaluated by measuring the residual energy (difference from the exact solution using the objective function) as a function of evolution time. The computation time is the time required to generate residual energy below an acceptable threshold. In quantum annealing, the problem Hamiltonian H P Although H can encode an optimization problem, the system does not necessarily stay in the ground state at all times. Just as the global minimum is the answer to the optimization problem to be solved and a low local minimum is a good approximation to the answer, P You can create an energy landscape of

[0020] The reduction of the envelope function A(t) in quantum annealing may follow a prescribed schedule, referred to in this application as an annealing schedule, and is an example of an evolutionary schedule. In traditional forms of adiabatic quantum computing, the system typically starts and remains in a ground state throughout the evolution. In quantum annealing, the system may not remain in the ground state throughout the annealing schedule. Quantum annealing may be implemented as a heuristic technique, where a low-energy state with an energy close to that of the ground state may provide an approximate solution to the problem.

[0021] Superconducting qubit One type of solid-state qubit is based on circuits of superconducting materials, which conduct electricity without electrical resistance under certain conditions (e.g., below a critical temperature, critical current, or magnetic field strength), or in the case of some materials above a certain pressure. Superconducting effects that can be the basis for how superconducting qubits operate include a) magnetic flux quantization, and b) Josephson tunneling.

[0022] If a loop of superconducting material through which a magnetic flux passes is cooled below the superconducting critical temperature of the superconducting material while the magnetic field is switched off, the magnetic flux can be quantized. A supercurrent continues to try to maintain the magnetic flux. The magnetic flux is quantized. Superconductivity is a quantum mechanical effect. The current in a loop of superconducting material can be controlled by a single wave function. The magnetic flux is quantized if the wave function is to be evaluated singly at the points in the loop.

[0023] Josephson tunneling occurs when a current in a loop of superconducting material passes through a small obstacle in the loop, for example, when the current passes through an insulating gap of a few nanometers. The amount of current can have a sinusoidal dependence on the phase difference across the small obstacle in the loop. The sinusoidal dependence is a nonlinearity that can cause anharmonic changes in the energy levels of the system.

[0024] The superconducting effect can exist in different configurations to create different types of superconducting qubits (e.g., flux qubits, phase qubits, charge qubits, and hybrid qubits). Different types of qubits can have different topologies for the loop of superconducting material and physical parameters (e.g., inductance, capacitance, and persistent current).

[0025] persistent current A superconducting qubit (e.g., a superconducting flux qubit) may include a loop of superconducting material (also referred to herein as the qubit loop) interrupted by at least one Josephson junction. The qubit loop is also referred to herein as the body of the superconducting qubit.

[0026] Because the qubit loop is in a superconducting state, the qubit loop has virtually no electrical resistance. Electrical current traveling in the qubit loop may not experience energy dissipation. If a current is generated in the qubit loop, for example, by a magnetic flux signal, the current may continue to circulate around the qubit loop even if the source of the magnetic flux signal is removed. The current may persist indefinitely until the current is interrupted or until the qubit loop is no longer in a superconducting state.

[0027] For the purposes of this application, the term "persistent current" is used to describe a current circulating in a loop of superconducting material (a loop that is interrupted by at least one Josephson junction). The sign and magnitude of the persistent current are determined by a) a magnetic flux signal Φ that is directly coupled to the superconducting loop; X , and b) a magnetic flux signal Φ coupled to a compound Josephson junction that interrupts the superconducting loop. CJJ (or Φ CO ) may depend on several factors, including, but not limited to:

[0028] quantum processor The quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include two or more superconducting qubits and associated local bias devices. Additionally, the superconducting quantum processor may include a coupling device (also referred to herein as a coupler) capable of providing a communicable coupling between the superconducting qubits. Further details and examples of quantum processors that can be used in conjunction with the present systems and devices are described in, for example, U.S. Patent Nos. 7,533,068, 8,008,942, 8,195,596, 8,190,548, and 8,421,053.

[0029] The types of problems that can be solved by any particular implementation of a quantum processor, and the relative size and complexity of such problems, may depend on many factors, including the number of qubits in the quantum processor and the connectivity (i.e., the availability of communicable couplings) between the qubits in the quantum processor.

[0030] Throughout this specification, the term "connectivity" is used to describe an upper limit on the number of physically available paths to communicably couple individual qubits in a quantum processor without the use of intervening qubits. For example, a qubit with a connectivity of three can be communicably coupled directly to three other qubits, i.e., a qubit with a connectivity of three can be communicably coupled to three other qubits without the use of intervening qubits. In other words, there are communicable coupling paths available to three other qubits, although in any particular application some or all (e.g., zero, one, two, or three) of the communicable coupling paths may be used.

[0031] In a quantum processor that uses coupling devices between qubits, for example, a qubit with three connectivity can be selectively communicatively coupled to each of three other qubits through each one of the three coupling devices. Typically, the number of qubits in a quantum processor can limit the size of the problems that can be solved, and the connectivity between the qubits can limit the complexity of the problems that can be solved.

[0032] Many prior art techniques using adiabatic quantum computing and / or quantum annealing to solve computational problems can include heuristics that map (or embed) a representation of the problem into a quantum processor. For example, U.S. Patent Application Publication No. 2008-0052055 describes solving a protein folding problem by first assigning the problem as an Ising spin glass problem and then embedding the Ising spin glass problem into a quantum processor. U.S. Patent No. 8,073,808 describes solving a computational problem (e.g., an image matching problem) by first assigning the problem as a quadratic unconstrained binary optimization ("QUBO") problem and then directly embedding the QUBO problem into a quantum processor. In both cases, the problem is solved by first assigning the problem to a devised formulation (e.g., Ising spin glass, QUBO, etc.) because that particular formulation directly maps to the particular implementation of the quantum processor being used. In other words, the intermediate formulation can be used to remap the original problem to a form that corresponds to the number of qubits and / or connectivity constraints in a particular implementation of the quantum processor, and the intermediate formulation can then be incorporated into the quantum processor. The incorporation approach can be driven by limitations inherent in the architecture of the quantum processor used. For example, quantum processors that use only pairwise interactions between qubits (i.e., quantum processors that use coupling devices that provide communicable coupling between each pair of qubits (rather than between a larger set of qubits, such as three or more qubits)) are inherently well-suited to solving problems with quadratic terms (e.g., the QUBO problem) because quadratic terms in the problem can be directly mapped to pairwise interactions between qubits in the quantum processor. Summary of the Invention [Means for solving the problem]

[0033] Quick Overview The superconducting integrated circuit comprises a first superconducting device including a first superconducting loop including a first superconducting trace in a first layer of the superconducting integrated circuit; a second superconducting device including a second superconducting loop including a second superconducting trace in a second layer of the superconducting integrated circuit, the second layer overlying and / or adjacent to the first layer, the second layer being separated from the first layer by an intervening layer; and an intersection region where the first superconducting loop intersects the second superconducting loop in projection, wherein at least a portion of the first superconducting trace inside the intersection region is intersected. The crossover region can be summarized as: the first superconducting trace is narrower than at least a portion of the first superconducting trace outside the crossover region; at least a portion of the second superconducting trace inside the crossover region is narrower than at least a portion of the second superconducting trace outside the crossover region; at least a portion of the first superconducting trace inside the crossover region follows a first circuitous path; and at least a portion of the second superconducting trace inside the crossover region follows a second circuitous path; and the first and second circuitous paths include a crossover region inductively proximate to each other for at least a portion of the length of the first circuitous path.

[0034] In some implementations, the first detour path and the second detour path at least partially overlie each other for at least a portion of the length of the first detour path.

[0035] In various of the above-described implementations, the first superconducting loop intersects the second superconducting loop substantially perpendicularly.

[0036] In various of the above-described implementations, the first and second superconducting traces each include a respective superconducting metal selected from the group consisting of niobium and aluminum.

[0037] In various of the above-described implementations, the first superconducting device further includes a first Josephson junction, where the first Josephson junction interrupts the first superconducting loop, and the second superconducting device further includes a second Josephson junction, where the second Josephson junction interrupts the second superconducting loop.

[0038] In various of the above-described implementations, the first superconducting device is a first superconducting flux qubit and the second superconducting device is a second superconducting flux qubit.

[0039] In various of the above-described implementations, at least a portion of the first superconducting trace inside the intersection region includes four direction changes.

[0040] In various of the above-described implementations, the first shape of the first detour path matches the second shape of the second detour path.

[0041] In various implementations described above, the intervening layer includes an insulating layer. The insulating layer may include a dielectric material and / or an air bridge. The dielectric material may include at least one of silicon dioxide or silicon nitride.

[0042] In various of the above-described implementations, the system further includes a coupling device coupled to the first superconducting device and the second superconducting device, the coupling device being communicatively coupled to provide a mediated coupling between the first superconducting device and the second superconducting device.

[0043] In various of the above-described implementations, at least a portion of the first superconducting trace inside the intersection region and at least a portion of the second superconducting trace inside the intersection region each include one or more U-shaped profiles.

[0044] Quantum computers can be summarized to include superconducting integrated circuits of various of the above-mentioned implementations.

[0045] A method for tuning a magnitude of a communicateable coupling between a first superconducting device and a second superconducting device, wherein the magnitude of the communicateable coupling is a sum of magnitudes of the mediated communicateable coupling and the direct communicateable coupling, includes determining a target magnitude of the communicateable coupling between the first and second superconducting devices; determining a difference between the magnitude of the mediated communicateable coupling and the target magnitude; determining an adjustment tolerance based at least in part on the difference between the magnitude of the mediated coupling and the target magnitude; attaching a first superconducting loop of the first superconducting device to a first layer; and attaching a second superconducting loop of the second superconducting device to a second layer, The superconducting loop can be summarized as including: intersecting a first superconducting loop to form an intersection region; following a first bypass path and adjusting at least a portion of the first superconducting loop within the intersection region by an adjustment tolerance so as to be narrower than at least a portion of the first superconducting loop outside the intersection region; and following a second bypass path and adjusting at least a portion of the second superconducting loop within the intersection region by an adjustment tolerance so as to be narrower than at least a portion of the second superconducting loop outside the intersection region, such that the first bypass path and the second bypass path are inductively proximate to each other for at least a portion of the length of the first bypass path.

[0046] In some implementations, the method further includes depositing an intervening layer between the first layer and the second layer. Depositing the intervening layer between the first layer and the second layer may include depositing an insulating layer. Depositing the insulating layer may include depositing a layer of dielectric material and / or forming an air bridge.

[0047] In various above-described implementations, attaching the second superconducting loop of the second superconducting device to the second layer includes attaching the second superconducting loop of the second superconducting device to the second layer such that at least a portion of the second layer overlies at least a portion of the first layer.

[0048] In some implementations, tuning at least a portion of the first superconducting loop by a tuning tolerance includes tuning at least a portion of the first superconducting loop to a width between 0.5 μm and 2.0 μm.

[0049] In some implementations, adjusting at least a portion of the first superconducting loop by the adjustment tolerance includes performing an adjustment width etch of at least a portion of the first superconducting loop. Performing an adjustment width etch of at least a portion of the first superconducting loop may include depositing a first hard mask overlying at least a portion of the first superconducting loop, depositing a second hard mask overlying at least a portion of the first hard mask, depositing a photoresist layer overlying at least a portion of the second hard mask, patterning the photoresist layer to define a predetermined adjustment width, and etching at least a portion of the first superconducting loop to remove the predetermined adjustment width.

[0050] A method of forming an integrated circuit can be summarized as including forming a first device including a first trace on a first layer of the integrated circuit; and forming a second device including a second trace on a second layer of the integrated circuit, wherein at least a portion of the second trace is in inductive proximity to at least a portion of the first trace, thereby providing an inductively communicable coupling between the first device and the second device, and wherein at least a portion of the first trace is narrower than at least another portion of the first trace.

[0051] In some implementations, forming the second device includes forming the second device, wherein at least a portion of the second trace is narrower than at least another portion of the second trace.

[0052] In some implementations, forming the first device includes forming a first superconducting device and forming the second device includes forming a second superconducting device. Forming the first superconducting device may include depositing a superconducting material. Forming the first superconducting device may further include tailoring at least a portion of the first trace to follow a first circuitous path and to be narrower than at least another portion of the first trace.

[0053] In various implementations described above, forming the second superconducting device includes forming the second superconducting device in inductive proximity to an intermediate coupling device, where the intermediate coupling device provides a communicable coupling between the first superconducting device and the second superconducting device. Forming the second superconducting device in inductive proximity to the intermediate coupling device may include forming the second superconducting device in inductive proximity to an intermediate coupling device that provides an antiferromagnetic (AFM) coupling between the first superconducting device and the second superconducting device, whereby the inductively communicable coupling between the first superconducting device and the second superconducting device increases the antiferromagnetic coupling.

[0054] A superconducting integrated circuit can be summarized as comprising a first superconducting device including a first superconducting loop including a first superconducting trace in a first layer of the superconducting integrated circuit; a second superconducting device including a second superconducting loop including a second superconducting trace in a second layer of the superconducting integrated circuit; and a region in which a portion of the first superconducting loop overlaps a portion of the second superconducting loop, wherein at least a portion of the first superconducting trace within the region is narrower than at least a portion of the first superconducting trace outside the region, and at least a portion of the second superconducting trace within the region is narrower than at least a portion of the second superconducting trace outside the region, wherein at least a portion of the first superconducting trace within the region follows a first path and at least a portion of the second superconducting trace within the region follows a second path, and wherein the first path and the second path are in inductive proximity to each other for at least a portion of the length of the first path.

[0055] In some implementations, the first layer is a different layer than the second layer.

[0056] In some implementations, the first layer is separated from the second layer by an intervening layer.

[0057] In some implementations, the first path is a detour path. The first path and the second path may be coincident.

[0058] In some implementations, the first path and the second path at least partially overlie one another.

[0059] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS In the drawings, the same reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily to scale. For example, the shapes and angles of various elements are not necessarily to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing visibility. Furthermore, the particular shapes of elements as shown are not intended to convey any information regarding the actual shape of the particular elements, but have been selected merely for ease of recognition in the drawings. [Brief explanation of the drawings]

[0060] [Figure 1] 1 is a schematic diagram of an exemplary mediated coupling layout in accordance with the present systems and methods. [Figure 2] 1 is a schematic diagram of an exemplary hybrid mediated and direct coupling layout in accordance with the present systems and methods. [Figure 3] 1 is a schematic diagram of another exemplary hybrid mediated and direct coupling layout in accordance with the present systems and methods. [Figure 4] 1 is a schematic diagram of another exemplary hybrid mediated and direct coupling layout in accordance with the present systems and methods. [Figure 5] 1 is a schematic diagram of another exemplary hybrid mediated and direct coupling layout in accordance with the present systems and methods. [Figure 6A] 1 is a schematic diagram of an exemplary layout of a pair of communicatively coupled superconducting devices, where each loop of each superconducting device has an inward bend at an intersection region, in accordance with the present systems and methods. [Figure 6B] 6B is a diagram of an example implementation of the intersection region of the layout of FIG. 6A in accordance with the present systems and methods. [Figure 7A] 10 is a schematic diagram of another exemplary layout of a pair of communicatively coupled superconducting devices, where each loop of each superconducting device has an outward curvature at an intersection region, in accordance with the present systems and methods. [Figure 7B] 7B is a diagram of an example implementation of the intersection region of the layout of FIG. 7A in accordance with the present systems and methods. [Figure 8A] 10 is a schematic diagram of another exemplary layout of a pair of communicatively coupled superconducting devices, where each loop of each superconducting device has multiple bends in the intersection region, in accordance with the present systems and methods. [Figure 8B] 8B is a diagram of an example implementation of the intersection region of the layout of FIG. 8A in accordance with the present systems and methods. [Figure 8C] 8B is a schematic diagram of another example implementation of the intersection region of the layout of FIG. 8A in accordance with the present systems and methods. [Figure 9] 1 is a schematic diagram of an exemplary superconducting quantum processor topology in accordance with the present systems and methods. [Figure 10] 1 is a schematic diagram of an exemplary layout of a pair of superconducting devices directly and communicatively coupled to one another in accordance with the present systems and methods. [Figure 11] 1 is a schematic diagram of another exemplary layout of a pair of superconducting devices directly communicatively coupled to one another in accordance with the present systems and methods. [Figure 12] 1 is a schematic diagram of an example hybrid computing system including a digital computer coupled to an analog computer in accordance with the present systems, devices, articles, and methods. [Figure 13A] 1 is a cross section of a portion of a superconducting integrated circuit in accordance with the present systems and methods. [Figure 13B] 1 is another cross section of a portion of a superconducting integrated circuit in accordance with the present systems and methods. [Figure 14A] 1 is a flowchart of an example method for forming an integrated circuit in accordance with the present systems and methods. [Figure 14B] 14B is a flowchart of an example method for adjusting the first path of FIG. 14A in accordance with the present systems and methods. DETAILED DESCRIPTION OF THE INVENTION

[0061] Detailed Description In the following description, certain specific details are set forth to provide a thorough understanding of various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with quantum processors, qubits, combiners, readout devices, and / or interfaces are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0062] Unless the context requires otherwise, throughout the following specification and claims, the term "comprise" and variations such as "comprises" and "comprising" are to be interpreted in an open-ended, inclusive sense, i.e., "including, but not limited to."

[0063] References throughout this specification to "one example," "an example," "one embodiment," or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, appearances of the terms "in one example," "in an example," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally used in its sense to include "and / or" unless the context clearly dictates otherwise.

[0065] As used in this specification and claims, "inductively proximate" means a structure (e.g., a device, line, or trace) that is suitably oriented and sufficiently close to another structure so that the flow of current in the structure directly induces the flow of current in the other structure. "Suitably oriented" typically means parallel, or at least non-orthogonal.

[0066] As used in this specification and claims, "overlapping" means a projection of a structure in plan or elevation that at least partially intersects or includes another structure, with or without intervening structures.

[0067] As used in this specification and claims, "overlying" means the projection of a structure in a plan view that at least partially intersects or includes another structure, typically with one or more intervening layers.

[0068] As used in this specification and claims, "adjacent" means the projection of a structure in an elevational view that at least partially intersects or includes another structure, typically with one or more intervening materials.

[0069] An overlapping structure may overlie (e.g., above / below) in a projection perpendicular to a plan view or a major face or surface (e.g., top or bottom) of the product or chip, and / or may be adjacent (e.g., parallel or serial) in a projection perpendicular to an elevation view or a minor face or surface (e.g., edge) of the product or chip. An overlapping structure may or may not be inductively adjacent to another structure.

[0070] A structure may overlap another structure on the next wiring layer below, or two wiring layers below, etc. Overlapping structures include partial overlapping structures and full overlapping structures. A structure may be, for example, a superconducting loop or a portion of a superconducting loop. The terms "overlap," "overlapping," etc. apply regardless of orientation, i.e., whether one structure is above, below, or to the side of another structure.

[0071] Overlapping structures may be adjacent to one another, i.e., have at least a portion of one structure running parallel to (or at least non-orthogonal to) at least a portion of the other structure, with the portions spaced closely enough together so that current flowing in one structure induces current in the other structure. In this application, structures that are in inductive proximity can be directly inductively coupled to one another.

[0072] A structure may be inductively proximate to another structure if the structures are on different layers of a multi-layer integrated circuit, where the structure at least partially overlies the other structure. A structure may be inductively proximate to another structure if the structures are on the same layer of a multi-layer integrated circuit, where the structure at least partially abuts the other structure. A structure may be inductively proximate to another structure if the structures are on different layers and not overlying, provided that the structures are appropriately oriented and are close enough to the other structure that current flow in the structure directly induces current flow in the other structure.

[0073] Overlapping and adjacent structures are described, for example, with reference to Figures 13A and 13B below, respectively. Adjacent structures in this application are separated by at least one intervening layer or material. Typically, the intervening layer or material is an insulating layer. In the case of multi-layer integrated circuits, adjacent structures are typically in the same layer as each other and separated by an intervening material.

[0074] The headings and abstract of the disclosure provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0075] It is desirable to improve the performance of quantum processors. One approach to improving performance is to increase the energy scale of the quantum processor. Although the energy scale of a quantum processor can be increased by increasing the critical current of the coupling devices in the quantum processor, there are constraints on how much the energy scale can be increased in this way.

[0076] The systems and methods described below aim to increase the energy scale of quantum processors by using direct inter-qubit coupling (i.e., no intervening coupling devices), alone or in combination with mediated coupling via coupling devices. The systems and methods described below can provide direct coupling that is tunable during fabrication. Advantages of the systems and methods described below advantageously include a) continuously variable tuning (as opposed to tuning in discrete steps), and b) little or no space penalty for integrated circuits.

[0077] Coupling between devices (e.g., a pair of superconducting qubits in a quantum processor) can be characterized by a coupling strength. Coupling strength quantifies the strength of the interaction between the devices. The interaction between the devices can be ferromagnetic or antiferromagnetic, depending on the sign of the coupling strength. By convention, a positive coupling strength can characterize an antiferromagnetic interaction, and a negative coupling strength can characterize a ferromagnetic interaction. Including both ferromagnetic (FM) and antiferromagnetic (AFM) interactions can be beneficial for quantum processors.

[0078] The definition of FM and AFM interaction can be based on the direction of the persistent current in each qubit of a pair of communicably coupled qubits and how the persistent current affects the Hamiltonian of the two-qubit system. If the mutual inductance (i.e., coupling) between the two qubits is positive, it follows that the currents in the two qubits flow in opposite directions. This is referred to in this application as AFM interaction.

[0079] In some implementations, FM coupling is achieved by biasing the compound Josephson junctions of the coupling device. In some implementations, it is preferentially beneficial to use direct coupling of communicable coupled qubits to enhance AFM coupling (rather than FM coupling).

[0080] Mutual inductance can be a measure of the coupling between two inductors (e.g., two superconducting qubits). The energy measure E that specifies the problem Hamiltonian in a quantum processor can be expressed as follows: E=M AFM I P 2 However, M AFM is the antiferromagnetic mutual inductance between two communicatively coupled superconducting devices (e.g., two superconducting qubits communicatively coupled by a coupling device), and I P is the average persistent current of the two superconducting devices.

[0081] For example, the mutual inductance M AFM and the average persistent current I P By increasing the energy measure E by increasing one or both of

[0082] The mutual inductance between two superconducting devices that are communicatively coupled by a coupling device may be limited by a) the inductance of the coupling device and b) the respective mutual inductances between each superconducting device and the coupling device.

[0083] The antiferromagnetic mutual inductance between two communicably coupled superconducting devices can be expressed as follows: M AFM =M1M2χ AFM where M1 is the mutual inductance between the first superconducting device and the coupling device, M2 is the mutual inductance between the second superconducting device and the coupling device, and χ AFM is the magnetic susceptibility of the coupling device.

[0084] Magnetic susceptibility χ of the coupled device AFM The magnetic susceptibility of a coupling device can be calculated by the magnetic flux bias φ of the coupling device.CO The critical current I of the coupling device can be set at least in part by C Increasing the magnetic susceptibility χ of the coupling device AFM is 1 / L CO (However, L CO is the inductance of the coupling device). Increasing the persistent current in the coupling device increases the magnetic susceptibility χ of the coupling device. AFM For example, in some implementations, if the persistent current is increased by a factor of 10, the magnetic susceptibility χ of the coupling device AFM can be at least about doubled.

[0085] Increasing the persistent current of a coupling device can also increase the screening parameter (also referred to as beta β in this application) of the coupling device. Beta of a coupling device is a parameter that describes the behavior of the superconducting loop in the coupling device. Beta of a coupling device can be expressed as follows: β=2πL CO I C / φ0 where φ0 is the magnetic flux quantum of the superconducting loop.

[0086] For example, the critical current I C Increasing the beta of the coupled device by increasing the magnetic susceptibility χ of the coupled device in the ferromagnetic region AFM The critical current I of the coupling device can be increased by C Increasing θ may decrease the precision with which ferromagnetic and / or antiferromagnetic coupling can be specified.

[0087] One way to increase the energy scale of a quantum processor is to increase the critical current of the coupling device. As mentioned above, the critical current I C Increasing the beta β of the coupling device by increasing the critical current of the coupling device increases the magnetic susceptibility χ of the coupling device. AFMβ can be increased, i.e., increasing β increases the derivative dI of the current flowing in the body of the coupling device with respect to the applied magnetic flux. P / dφ x There is a limit to how much the magnetic susceptibility can be increased by increasing the critical current. The magnetic susceptibility is a nonlinear function, so increasing the critical current of a coupling device increases the magnetic susceptibility χ AFM may increase with decreasing return.

[0088] Another approach to increasing the energy scale of a quantum processor is to implement direct coupling between the bodies of two or more superconducting devices. In some implementations, there is direct coupling (i.e., no intervening device) between a pair of superconducting devices that are further communicatively coupled by a coupling device. In some implementations, the direct coupling is inductive coupling. A pair of superconducting devices communicatively coupled by a coupling device may be a) a pair of superconducting qubits, b) a superconducting qubit and another superconducting device, or c) any pair of superconducting loops that can be coupled to each other (e.g., a superconducting qubit, a quantum flux parametron (QFP), a multiplier, and an L-tuner). A pair of superconducting devices, each including a loop of superconducting material interrupted by at least one Josephson junction, may be configured to include a direct coupling between the superconducting devices of the pair of superconducting devices.

[0089] Detailed descriptions of such other superconducting devices are found, for example, in U.S. Patent Nos. 8,169,231 and 7,843,209, and U.S. Patent Application Publication Nos. 2011-0057169A1 and 2011-0060780A1. Examples of systems and methods for increasing the energy scale of quantum processors are given in U.S. Patent No. 9,129,224.

[0090] Direct coupling between superconducting devices is undesirable because, for example, the direct coupling can cause unwanted crosstalk between the superconducting devices. The present applicant recognizes that the addition of a known antiferromagnetic or ferromagnetic direct coupling between two communicably coupled superconducting devices can beneficially exploit the asymmetric susceptibility of the coupled devices.

[0091] For example, in the absence of direct coupling, the mutual inductance M AFM But, M1M1χ AFM Although the antiferromagnetic coupling may be limited to .gtoreq..times ... M AFM =M1M1χ AFM +M QQ However, M QQ is the mutual inductance of the direct coupling.

[0092] Direct coupling may be added between the operably coupled superconducting devices (e.g., a pair of operably coupled superconducting devices) by configuring the devices to induce direct ferromagnetic or antiferromagnetic coupling between the operably coupled superconducting devices. Configuring qubits (e.g., a pair of qubits) to induce direct coupling between the operably coupled superconducting devices can include, for example, configuring a crossed geometry of qubits.

[0093] As described above, each qubit can include a loop of superconducting material (also referred to herein as a superconducting loop) interrupted by at least one Josephson junction. In some implementations, the Josephson junction is a compound Josephson junction. In some implementations, the Josephson junction is a compound-compound Josephson junction, i.e., a compound Josephson junction in which at least one of the constituent Josephson junctions is itself a compound Josephson junction.

[0094] The direct coupling between the qubits may be antiferromagnetic, ferromagnetic, or zero coupling.

[0095] In some implementations, zero direct coupling can be achieved by placing the respective long axes of each of a pair of communicably coupled qubits orthogonal to one another, with or without adjusting the qubit traces in the region where the qubits overlap.

[0096] In some implementations, ferromagnetic coupling can be achieved, for example, by tailoring the qubit traces so that they have outward curvatures (see, eg, FIG. 7).

[0097] Various implementations described herein provide systems and methods for increasing the energy scale of a quantum processor by adding a direct coupling between communicably coupled superconducting devices (e.g., a pair of superconducting qubits). Additionally, the communicably coupled superconducting devices may have a communicable coupling mediated by a coupling device.

[0098] Additionally, various implementations described herein provide systems and methods for increasing the energy scale of a quantum processor by increasing the linearity of the response or sensitivity of coupling devices in the quantum processor.

[0099] As an illustrative example, a superconducting quantum processor designed to perform adiabatic quantum computing and / or quantum annealing is used in the following description, although those skilled in the art will recognize that the present systems and methods can be applied to other forms of quantum processor hardware and quantum processors that implement other forms of quantum algorithms (e.g., adiabatic quantum computing, quantum annealing, and gate- and / or circuit-based quantum computing).

[0100] 1 is a schematic diagram of an exemplary mediated coupling layout 100. The exemplary mediated coupling layout 100 includes a pair of superconducting devices 102 and 104 that are communicatively coupled to each other by a coupling device 106. In the exemplary mediated coupling layout 100, there is little or no direct coupling induced between the two superconducting devices 102 and 104. In the exemplary layout 100, there is a mediated communicative coupling between the superconducting devices 102 and 104. The mediated communicative coupling may be mediated by the coupling device 106.

[0101] Superconducting device 102 includes a superconducting loop 108 that is interrupted by Josephson junction 110. Superconducting device 104 includes a superconducting loop 112 (shown in FIG. 1 as a dotted line) that is interrupted by Josephson junction 114. Josephson junctions (e.g., Josephson junctions 110 and 114) are represented by crosses in FIGS. 1-5, 6A, 7A, and 8A of the present application.

[0102] In this application, a superconducting loop is defined as a closed loop of material that is superconducting below a critical temperature. In some implementations, the superconducting loop is a closed loop of superconducting wire. In some implementations, the superconducting loop is a superconducting circuit trace (also referred to as a trace in this application) that runs in a closed loop in a superconducting integrated circuit. A superconducting trace is a path in a superconducting integrated circuit. A superconducting trace includes, for example, a line of superconducting material through which current can flow in a closed loop or between component circuits of a superconducting integrated circuit. In some implementations, the superconducting loop includes a superconducting wire and at least one superconducting trace.

[0103] In some implementations, a superconducting loop is an elongated loop having a major axis and a minor axis. The orientation of the superconducting loop may be defined as the direction of the major axis. For example, superconducting loop 108 has a major axis 128 and a minor axis 130. The orientation 132 of superconducting loop 108 may be defined as the direction of major axis 128. A superconducting integrated circuit is an integrated circuit that includes one or more superconducting component circuits.

[0104] In some implementations, the superconducting loops are traces formed in layers of a multi-layer superconducting integrated circuit. In some implementations, one or both of the superconducting loops 108 and 112 comprise a superconducting metal (e.g., niobium and / or aluminum). In some implementations, each of the superconducting loops 108 and 112 is a trace formed in a respective layer of a multi-layer superconducting integrated circuit, each layer separated from the other by a respective insulating layer. In some implementations, each insulating layer comprises silicon dioxide and / or silicon nitride.

[0105] Superconducting devices 102 and 104 may include more than one Josephson junction. In some implementations, one or both of Josephson junctions 110 and 114 are compound Josephson junctions. In some implementations, one or both of Josephson junctions 110 and 114 are compound-compound Josephson junctions. A compound Josephson junction is a Josephson junction that includes a pair of Josephson junctions that are electrically parallel to each other. A compound-compound Josephson junction is a compound Josephson junction in which at least one constituent Josephson junction is a compound Josephson junction.

[0106] Coupling device 106 is operable to communicatively couple superconducting devices 102 and 104 to one another via mutual inductance between superconducting loops 108 and 112 of superconducting devices 102 and 104, respectively. Coupling device 106 includes superconducting loop 116. In some implementations, such as layout 100 of FIG. 1 , superconducting loop 116 is interrupted by Josephson junction 118. Josephson junction 118 may be a compound Josephson junction or a compound-compound Josephson junction. In some implementations, coupling device 106 includes more than one Josephson junction.

[0107] In FIG. 1 , to more clearly illustrate the intersection geometry of superconducting devices 102 and 104, superconducting device 102 is depicted with a solid line, while superconducting device 104 is depicted with a dotted line. In the exemplary layout 100, superconducting device 102 intersects superconducting device 104 substantially perpendicularly. The region where superconducting devices 102 and 104 intersect is referred to herein as intersection region 120. This application describes intersection region 120 layouts in which a portion of superconducting device 102 overlies a portion of superconducting device 104 to provide coupling. See, for example, intersection region layouts shown in FIGS. 6B , 7B , 8B , and 8C , which are suitable for the arrangement of FIG. 1 . Other layouts of intersection region 120 with bypass paths may be used as well. For example, selective adjustment of superconducting loops 108 and 112 in intersection region 120 during fabrication can control the magnitude of direct connectable coupling between superconducting devices 102 and 104 in some implementations without incurring a space penalty for the superconducting circuit.

[0108] For purposes of this application, one superconducting device is considered to intersect another superconducting device substantially perpendicularly if a portion (e.g., a trace or loop) of one superconducting device intersects a portion of the other superconducting device at an angle of 90°±10°.

[0109] In some implementations, the superconducting device includes a superconducting loop. The orientation of the superconducting device may be defined by the orientation of the superconducting loop. In some implementations, the superconducting loop has an elongated shape with a major axis in the longitudinal direction and a minor axis perpendicular to the major axis. In this case, the orientation of the superconducting loop can be defined by the orientation of the major axis. When the major axis of one superconducting loop intersects the major axis of the other superconducting loop at an angle of 90°±10°, one superconducting loop can be considered to intersect substantially perpendicularly with another superconducting loop. Consider the implementation shown in FIG. 1. When the major axes (also referred to as longitudinal axes in this application) of superconducting loops 108 and 112 intersect at an angle of 90°±10°, superconducting device 102 is substantially perpendicular to superconducting device 104.

[0110] An excitation current 122 in the superconducting loop 112 can induce a current 124 in the coupling device 106, which in turn can induce a current 126 in the superconducting loop 108, thereby providing a mediated inductively communicable coupling between the superconducting devices 102 and 104.

[0111] In some implementations, the direct coupling can be nulled by biasing the coupling device 106. In some implementations, a digital-to-analog converter (DAC) is used to bias, null the direct coupling, and / or adjust the strength of the combined direct and mediated coupling.

[0112] In some implementations, superconducting devices 102 and 104 are a pair of superconducting qubits. In other implementations, superconducting device 102 is a superconducting qubit, and superconducting device 104 is another type of superconducting device that is communicatively coupled to superconducting device 102 by coupling device 106. For example, superconducting device 104 may be one of a quantum flux parametron (QFP), a multiplier, a DAC, and a tuned Josephson inductance (also referred to herein as an inductance tuner or L-tuner for short). In still other implementations, superconducting devices 102 and 104 form a suitable combination of a pair of communicatively coupled superconducting devices (e.g., a superconducting qubit, a QFP, a multiplier, and / or an L-tuner).

[0113] The mutual inductance between superconducting devices 102 and 104 can be expressed as: M AFM =M 102 M 104 χ 106 However, M 102 is the mutual inductance between the superconducting device 102 and the coupling device 106, and M 104 is the mutual inductance between the superconducting device 104 and the coupling device 106, and χ 106is the magnetic susceptibility of coupling device 106. In example layout 100, superconducting loop 108 of superconducting device 102 runs substantially perpendicular to superconducting loop 112 of superconducting device 104, so that there is little or no direct coupling induced between superconducting devices 102 and 104 due to the mutual inductance between superconducting loops 108 and 112.

[0114] Direct coupling may be induced between a pair of communicably coupled superconducting devices by positioning the shapes of the superconducting devices relative to one another, for example, by positioning at least a portion of the superconducting loop of one of the superconducting devices at a non-orthogonal angle relative to at least a portion of the superconducting loop of the other superconducting device.

[0115] Crossing of at least some of the superconducting loops at non-orthogonal angles relative to one another may cause crosstalk between the superconducting loops. The crosstalk may increase the mutual inductance of the two communicably coupled superconducting loops. When the two superconducting devices are elements of a quantum processor, the crosstalk may result in an increase in the energy scale of the quantum processor. Although in some circumstances crosstalk may be undesirable, advantageously, crosstalk induced between a pair of superconducting devices may be used to controllably increase the energy scale of the quantum processor, which may beneficially improve the performance of the quantum processor. Improving the performance of the quantum processor may include improving the quality of the solution realized by the quantum processor and / or reducing the time to reach a solution.

[0116] 2 is a schematic diagram of an exemplary hybrid-mediated and direct-coupled layout 200. The exemplary layout 200 includes a pair of superconducting devices 202 and 204 that are communicatively coupled to one another by a coupling device 206. To more clearly illustrate the intersection geometry of superconducting devices 202 and 204, superconducting device 202 is depicted with a solid line, while superconducting device 204 is depicted with a dotted line. In the exemplary layout 200, superconducting device 202 intersects superconducting device 204 substantially perpendicularly.

[0117] Superconducting device 202 includes a superconducting loop 208 interrupted by a Josephson junction 210. Superconducting device 204 includes a superconducting loop 212 interrupted by a Josephson junction 214. In some implementations, one or both of superconducting loops 208 and 212 include a superconducting metal (e.g., niobium and / or aluminum).

[0118] Superconducting devices 202 and 204 may include more than one Josephson junction. In some implementations, one or both of Josephson junctions 210 and 214 are compound Josephson junctions. In some implementations, one or both of Josephson junctions 210 and 214 are compound-compound Josephson junctions. In some implementations, superconducting devices 202 and 204 are superconducting qubits (e.g., superconducting flux qubits).

[0119] Coupling device 206 is operable to communicatively couple superconducting devices 202 and 204 to one another via mutual inductance between superconducting loops 208 and 212, respectively.

[0120] 1, a portion of superconducting loop 208 of superconducting device 202 is positioned at a non-orthogonal angle relative to a portion of superconducting loop 212 of superconducting device 204 in shaping region 216. Such an orientation reduces the mutual inductance M between superconducting devices 202 and 204. QQ(also referred to in this application as direct coupling) can be induced. The direct coupling may be direct inductive coupling. In the example layout 200 of FIG. 2, a portion of superconducting loop 208 of superconducting device 202 is positioned to be substantially parallel to a portion of superconducting loop 212 of superconducting device 204 in shaping region 216.

[0121] In some implementations, a portion of superconducting loop 208 of superconducting device 202 has a bend, i.e., a short, abrupt change in orientation that interrupts the orientation of the remaining loop. For example, layout 200 includes bend 218. Bend 218 causes a portion of superconducting loop 208 to be substantially parallel to a portion of superconducting loop 212 of superconducting device 204. In some implementations, superconducting loop 208 of superconducting device 202 is Z-shaped. In other implementations, superconducting loop 208 of superconducting device 202 is L-shaped.

[0122] An excitation current 220 in superconducting loop 212 can induce a current 222 in superconducting loop 208 .

[0123] The mutual inductance M induced by the proximity and relative orientation of the superconducting loops 208 and 212 QQ In addition, the coupling device 206 (which provides a communicable coupling between the superconducting devices 202 and 204) has a mutual inductance M AFM The inductive mutual inductance can provide, for example, antiferromagnetic coupling. The total mutual inductance between the superconducting devices 202 and 204 is the mutual inductance M AFM and M QQ may include contributions from

[0124] The orientation of the direct coupling induced between superconducting devices 202 and 204 at or near shaping region 216 may depend, at least in part, on the direction of current flowing in each of superconducting loops 208 and 212 of superconducting devices 202 and 204. The orientation of the direct coupling may depend, at least in part, on the geometry of the traces of superconducting devices 202 and 204 in the region where the traces of superconducting devices 202 and 204 overlap. The intersection geometry of superconducting devices 202 and 204 (e.g., at or near shaping region 216) may affect the mutual inductance M QQ can at least partially determine whether the mutual inductance M is ferromagnetic, antiferromagnetic, or close to zero. QQ is antiferromagnetic and the mutual inductance M QQ is the mutual inductance M AFM , thereby increasing the antiferromagnetic (AFM) coupling of the superconducting devices 202 and 204. That is, the mutual inductance M QQ is the AFM, increasing the mediated coupling provided by the coupling device 206 can reduce the mutual inductance M QQ is the mutual inductance M AFM can be increased, thereby increasing the total mutual inductance.

[0125] This application includes a description of possible layouts for shaping region 216 in which a portion of superconducting device 202 overlies a portion of superconducting device 204 to provide coupling. See, for example, the intersection region layouts shown in Figures 6B, 7B, 8B, and 8C, which are suitable for the arrangement of Figure 2. Other layouts for shaping region 216 having circuitous paths may be used as well. For example, selective adjustment of superconducting loops 208 and 212 during fabrication can advantageously control the amount of direct communicable coupling between superconducting devices 202 and 204 in some implementations without incurring a space penalty for the superconducting circuit.

[0126] The systems and methods apply more generally to connectably coupled superconducting devices, each of which includes a loop of superconducting material. The systems and methods may provide direct inductive coupling between superconducting devices that is adjustable during fabrication to tunable inductive coupling between the superconducting devices.

[0127] 3 is a schematic diagram of another exemplary mediated and direct coupling layout 300. The exemplary layout 300 includes a pair of superconducting devices 302 and 304 that are communicatively coupled to one another by a coupling device 306. To more clearly illustrate the crossing geometry of superconducting devices 302 and 304, superconducting device 302 is depicted with a solid line, while superconducting device 304 is depicted with a dotted line.

[0128] Superconducting device 302 includes a superconducting loop 308 interrupted by a Josephson junction 310. Superconducting device 304 includes a superconducting loop 312 interrupted by a Josephson junction 314.

[0129] A superconducting loop topologically formed by a 180° out-of-plane rotation of a portion of the superconducting loop is referred to in this application as a superconducting loop with a crossover. Current through the superconducting loop on one side of the crossover flows in a clockwise direction around the loop, and current through the superconducting loop on the other side of the crossover flows in a counterclockwise direction around the loop. The two segments of the superconducting loop that cross over each other are galvanically isolated from each other at the crossover. A superconducting loop may include more than one crossover; for example, superconducting loop 308 includes two crossovers 316 and 318.

[0130] The crossing configuration of the superconducting devices 302 and 304 of FIG. 3 at or near the crossing region 320 provides a direct coupling M between the superconducting loops 308 and 312 of the superconducting devices 302 and 304, respectively. QQ For clarity, the intersection region 320 is shown in FIG. 3 as a shaping region.

[0131] A vector perpendicular to a plane containing the area of ​​superconducting loop 308 at intersection region 320 has a substantially opposite orientation relative to both i) a vector perpendicular to a plane containing the area of ​​superconducting loop 308 outside intersection region 320, and ii) a vector perpendicular to a plane containing the area of ​​superconducting loop 312 of superconducting device 304. A substantially opposite orientation of one vector relative to another vector means an orientation of 180°±10° between the two vectors.

[0132] A portion of the superconducting loop 308 of the superconducting device 302 has a bend 322 that causes the portion of the superconducting loop 308 to be substantially parallel to a portion of the superconducting loop 312 of the superconducting device 304. When portions of the superconducting loops 308 and 312 run parallel to each other, the portions of the superconducting loops 308 and 312 can overlie each other and / or be adjacent to each other. In some implementations, the superconducting loops 308 and 312 define traces on separate layers of a multi-layer superconducting integrated circuit. The traces of the superconducting loops 308 and 312 may overlie each other and / or be adjacent to each other and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The overlie and / or abutment of the portions of the superconducting loops 308 and 312 can create a mutual inductance, which can provide a direct inductive coupling between the superconducting devices 302 and 304.

[0133] An excitation current 324 in superconducting loop 312 can induce a current 326 in superconducting loop 308 .

[0134] The presence of crossovers 316 and 318 in superconducting loop 308 allows current flowing in a counterclockwise direction in intersection region 320 to be forced (by induction) to flow in a clockwise direction in the portion of superconducting loop 308 outside intersection region 320. The portion of superconducting loop 308 outside intersection region 320 is also referred to in this application as the body of superconducting device 302. The mutual inductance M QQ is the mutual inductance M AFM, which can increase the AFM coupling of the superconducting devices 302 and 304.

[0135] This application includes a description of possible layouts for intersection region 320 in which a portion of superconducting device 302 overlies a portion of superconducting device 304 to provide coupling. See, for example, the intersection region layouts shown in FIGS. 6B, 7B, 8B, and 8C, which are suitable for the mediated and direct coupling layout 300 of FIG. 3. Other layouts for intersection region 320 having bypass paths may be used as well. For example, selective adjustment of superconducting loops 308 and 312 during fabrication can advantageously control the amount of direct connectable coupling between superconducting devices 302 and 304 in some implementations without incurring a space penalty for the superconducting circuit.

[0136] 4 is a schematic diagram of another example layout 400. Layout 400 includes a pair of superconducting devices 402 and 404 that are communicatively coupled to one another by a coupling device 406. To more clearly illustrate the crossing geometry of superconducting devices 402 and 404, superconducting device 402 is depicted with a solid line, while superconducting device 404 is depicted with a dotted line.

[0137] Superconducting device 402 includes a superconducting loop 408 interrupted by a Josephson junction 410. Superconducting device 404 includes a superconducting loop 412 interrupted by a Josephson junction 414. Superconducting loop 408 includes crossovers 416 and 418.

[0138] The crossing configuration of the superconducting devices 402 and 404 of FIG. 4 at or near the crossing region 420 provides a direct coupling M between the superconducting loops 408 and 412 of the superconducting devices 402 and 404, respectively. QQ For clarity, the intersection region 420 is shown in FIG. 4 as a shaping region.

[0139] A vector perpendicular to a plane containing the area of ​​superconducting loop 408 in intersection region 420 has a substantially opposite direction to both i) a vector perpendicular to a plane containing the area of ​​superconducting loop 408 outside intersection region 420, and ii) a vector perpendicular to a plane containing the area of ​​superconducting loop 412 of superconducting device 404.

[0140] Each of the two portions of the superconducting loop 408 of the superconducting device 402 has a respective bend such that each bent portion 422 and 424 of the superconducting loop 408 is substantially parallel to a portion of the superconducting loop 412 of the superconducting device 404. When the portions of the superconducting loops 408 and 412 run parallel to each other, the portions of the superconducting loops 408 and 412 can overlie and / or be adjacent to each other. In some implementations, the superconducting loops 408 and 412 define traces on separate layers of a multi-layer superconducting integrated circuit. The traces of the superconducting loops 408 and 412 may overlie and / or be adjacent to each other and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The overlie and / or abutment of the portions of the superconducting loops 408 and 412 can create a mutual inductance, which can provide a direct inductive coupling between the superconducting devices 402 and 404.

[0141] An excitation current 426 in superconducting loop 412 can induce a current 428 in superconducting loop 408 .

[0142] The presence of crossovers 416 and 418 in superconducting loop 408 causes current flowing in a counterclockwise direction in intersection region 420 to flow in a clockwise direction in the portion of superconducting loop 408 outside intersection region 420 (also referred to in this application as the body of superconducting device 402). QQ is the mutual inductance M AFM , which can increase the AFM coupling of the superconducting devices 402 and 404.

[0143] For layouts 300 and 400 of Figures 3 and 4, respectively, the mutual inductance may be increased by increasing the length that the superconducting loops or traces overlie and / or are adjacent to each other. The direct coupling created between the bodies of two communicably coupled superconducting devices (e.g., superconducting devices 302 and 304 of Figure 3) in combination with the mediated coupling (e.g., by coupling device 306 of Figure 3) may result in ferromagnetic, antiferromagnetic, or substantially zero communicable coupling between the superconducting devices. For example, zero coupling may occur when the mediated and direct couplings cancel each other out.

[0144] This application includes a description of possible layouts for intersection region 420 in which a portion of superconducting device 402 overlies a portion of superconducting device 404 to provide coupling. See, for example, the intersection region layouts shown in FIGS. 6B, 7B, 8B, and 8C, which are suitable for layout 400 of FIG. 4. Other layouts for intersection region 420 having detour paths may be used as well. For example, selective adjustment of superconducting loops 408 and 412 during fabrication can advantageously control the amount of direct communication coupling between superconducting devices 402 and 404 in some implementations without incurring a space penalty for the superconducting circuit.

[0145] 5 is a schematic diagram of another example layout 500. Layout 500 includes a pair of superconducting devices 502 and 504 that are communicatively coupled to one another by a coupling device 506. To more clearly illustrate the crossing geometry of superconducting devices 502 and 504, superconducting device 502 is depicted with a solid line, while superconducting device 504 is depicted with a dotted line.

[0146] Superconducting device 502 includes a superconducting loop 508 interrupted by a Josephson junction 510. Superconducting device 504 includes a superconducting loop 512 interrupted by a Josephson junction 514.

[0147] The crossing configuration of superconducting devices 502 and 504 of FIG. 5 at or near crossing region 516 provides direct coupling M between superconducting loops 508 and 512 of superconducting devices 502 and 504, respectively. QQ For clarity, the intersection region 516 is shown in FIG. 5 as a shaping region.

[0148] Each of the two portions of superconducting loop 508 of superconducting device 502 has a respective outward curvature (outward defined as a curvature away from the center of the loop) that causes each curved portion 518 and 520 of superconducting loop 508 to be substantially parallel to a portion of superconducting loop 512 of superconducting device 504. When portions of superconducting loops 508 and 512 run parallel to each other (or are at least non-orthogonal), portions of superconducting loops 508 and 512 can overlie and / or be adjacent to each other. In some implementations, superconducting loops 508 and 512 define traces on separate layers of a multi-layer superconducting integrated circuit. The traces of superconducting loops 508 and 512 may overlie and / or be adjacent to each other and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The overlapping and / or abutment of portions of superconducting loops 508 and 512 can create a mutual inductance that can provide a direct inductively communicable coupling between superconducting devices 502 and 504 .

[0149] An excitation current 522 in superconducting loop 512 can induce a current 524 in superconducting loop 508 .

[0150] The absence of a crossover in superconducting loop 508 (such as crossovers 416 and 418 in superconducting loop 408 in FIG. 4) can result in a scenario where current flows counterclockwise in intersection region 516 and counterclockwise in the portion of superconducting loop 508 outside intersection region 516 (also referred to in this application as the body of superconducting device 502). QQcan induce ferromagnetic (FM) coupling, resulting in a mutual inductance M AFM , which can reduce the AFM coupling of superconducting devices 502 and 504 (eg, the AFM coupling mediated by coupling device 506).

[0151] A vector perpendicular to a plane containing the area of ​​superconducting loop 508 in shaped intersection region 516 has substantially the same orientation as both i) a vector perpendicular to the area of ​​superconducting loop 508 of the remaining superconducting device 502 and ii) a vector perpendicular to the area of ​​superconducting loop 512 of superconducting device 504.

[0152] In some implementations, superconducting devices 502 and 504 are superconducting qubits (eg, superconducting flux qubits).

[0153] This application includes a description of possible layouts for intersection region 516 in which a portion of superconducting device 502 overlies a portion of superconducting device 504 to provide coupling. See, for example, the intersection region layouts shown in Figures 6B, 7B, 8B, and 8C, which are suitable for layout 500 of Figure 5. Other layouts for intersection region 516 having detour paths may be used as well. For example, selective adjustment of superconducting loops 508 and 512 during fabrication can advantageously control the amount of direct communication coupling between superconducting devices 502 and 504 in some implementations without incurring a space penalty for the superconducting circuit.

[0154] FIG. 6A is a schematic diagram of an exemplary layout 600 of a pair of superconducting devices 602 and 604 that are communicatively coupled to one another, with each loop of each superconducting device having an inward bend in the intersection region, in accordance with the present systems and methods.

[0155] Layout 600 includes a pair of superconducting devices 602 and 604. Superconducting device 602 includes a superconducting loop 606 interrupted by a Josephson junction 608. Superconducting device 604 includes a superconducting loop 610 interrupted by a Josephson junction 612. Superconducting loop 606 and / or superconducting loop 610 may or may not be interrupted by a respective Josephson junction. Superconducting devices 602 and / or 604 may include other elements not shown in FIG. 6A . Superconducting devices 602 and / or 604 may be superconducting qubits (e.g., superconducting flux qubits).

[0156] Although the coupling described with reference to Figure 6A is a direct inductive coupling (i.e., with no intervening coupling device), superconducting devices 602 and 604 may alternatively, additionally, or optionally be coupled by galvanic and / or mediated coupling via at least one intervening coupling device. The same applies to devices 702 and 704, 802 and 804, 902 and 904, and 1002 and 1004 of Figures 7A and 7B, 8A, 8B and 8C, 10, and 11, respectively.

[0157] Each of superconducting devices 602 and 604 has inward bends 614 and 616, respectively (each inward bend is defined herein as a bend toward the center of the respective loop). Inward bends 614 and 616 are located in intersection region 618 at or near where superconducting devices 602 and 604 intersect with each other. Inward bends 614 and 616 cause a portion of superconducting loop 606 of superconducting device 602 to be substantially parallel (or at least non-orthogonal) to a portion of superconducting loop 610 of superconducting device 604 in regions 620, 622, 624, and 626 of layout 600.

[0158] When portions of superconducting loops 606 and 610 run parallel to each other (or at least non-orthogonal), portions of superconducting loops 606 and 610 can overlie each other and / or be adjacent to each other. In some implementations, superconducting loops 606 and 610 define traces on separate layers of a multi-layer superconducting integrated circuit. The traces of superconducting loops 606 and 610 may overlie each other and / or be adjacent to each other and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The overlie and / or abutment of portions of superconducting loops 606 and 610 can create mutual inductance, which can provide direct inductive coupling between superconducting devices 602 and 604. Where the present application describes overlying a portion of a superconducting loop to create mutual inductance and direct inductively connectable coupling, one skilled in the art will appreciate that implementations can include overlying a portion of a superconducting loop and / or placing portions of a superconducting loop adjacent to one another to create mutual inductance and direct inductively connectable coupling.

[0159] An excitation current flowing in direction 628 in superconducting loop 610 can induce a current flowing in direction 630 in superconducting loop 606 .

[0160] 6B is a schematic diagram of an example implementation of intersection region 618 of layout 600 of FIG. 6A in accordance with the present systems and methods. Intersection region 618 includes the region where superconducting loops 606 and 610 of superconducting devices 602 and 604 of FIG. 6A intersect with one another.

[0161] Superconducting loops 606 and 610 overlap (eg, overlie one another in a multi-layer superconducting integrated circuit) and run parallel to one another (or at least non-orthogonal) in each region 632, 634, 636, and 638.

[0162] 6B shows an example layout of layout 600 in a plan view. In some implementations, layout 600 is fabricated in a multi-layer superconducting integrated circuit using different layers for superconducting loops 606 and 610. In some implementations, the layers are fabricated using a superconducting metal and separated by an insulating layer (e.g., a layer of dielectric material). In some implementations, superconducting loops 606 and 610 include niobium. In some implementations, superconducting loops 606 and 610 include aluminum and / or another suitable superconducting material. In some implementations, the insulating layer includes silicon dioxide.

[0163] Superconducting loops 606 and 610 may be loops of superconducting wire. The superconducting wires may overlie one another in regions 632, 634, 636, and 638, providing a direct connectable coupling for superconducting devices 602 and 604. Fabrication of layout 600 may include methods for tailoring the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires overlie one another). For example, in FIG. 6B, regions 640, 642, and 644 of the left leg of superconducting loop 606 are tailored to produce inward bend 616 of FIG. 6A.

[0164] A superconducting loop in a superconducting integrated circuit (e.g., superconducting loop 606 of the multilayer superconducting integrated circuit of layout 600) can include one or more traces of superconducting material. Each trace (also referred to herein as a superconducting trace) has a respective thickness and a respective width. The length of a superconducting trace is the length of the path through which current can flow. The width is defined as the perpendicular distance between the opposing outer edges of the superconducting trace at any given point along the length. The width is the distance measured in the plane of the layers of the multilayer integrated circuit. The thickness is defined as being perpendicular to the length and width of the superconducting trace. The thickness is the distance measured in the stacking direction (i.e., perpendicular to the plane of the layers).

[0165] In this application, references to a portion of a superconducting loop being narrower within a region than outside the region refer to a trace in the portion of the superconducting loop having a smaller width within the region than outside the region, where a narrower trace occupies less surface area on an integrated circuit than a wider trace of the same length.

[0166] In some implementations (e.g., the implementation illustrated in FIG. 6B ), at least a portion of each of the superconducting loops 606 and 610 is narrower inside the intersection region 618 than outside the intersection region 618. That is, the width of each of the superconducting loops 606 and 610 inside the intersection region 618 is narrower than the width of each of the superconducting loops 606 and 610 outside the intersection region 618.

[0167] Fabrication of layout 600 can include creating detour paths for the superconducting traces of superconducting loops 606 and 610 inside intersection region 618. A detour path is a path between two points that takes a longer route than the most direct path (e.g., the shortest line). A detour path may include one or more turns or changes. For example, a detour path between two points may include a straight path between the two points interrupted by a right-angle left turn, a right-angle right turn, another right-angle right turn, and another right-angle left turn, with each turn followed by a straight path of an appropriate length. In FIG. 6B , for example, the path of the superconducting trace of superconducting loop 606 through intersection region 618 makes four changes of direction to proceed in the direction of current 630; the path makes a right-angle right turn, a right-angle left turn, another right-angle left turn, and another right-angle right turn.

[0168] The circuitous path of the superconducting trace of superconducting loop 606 in intersection region 618 may match the circuitous path of the superconducting trace of superconducting loop 610 in intersection region 618 .

[0169] For example, selective tuning of superconducting loops 606 and 610 during fabrication can control the magnitude of the direct connectable coupling of superconducting devices 602 and 604. For example, selective tuning can be achieved to adjust the width of the superconducting lines of superconducting loops 606 and 610 at intersection region 618 without incurring a space penalty for the superconducting circuit. Selective tuning of the superconducting lines during fabrication can provide adjustable tuning of the magnitude of the direct connectable coupling of superconducting devices 602 and 604 over a continuous range, rather than just discrete values. In one implementation, the magnitude of the direct connectable coupling between two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediated coupling by selectively tuning the superconducting traces and configuring the superconducting traces to follow an appropriate detour path. Tuning the superconducting traces reduces the width of the traces. In one implementation, the superconducting traces are selectively tuned from a width of 2 μm to a width of 0.5 μm.

[0170] The mediated coupling is not shown in Figures 6A and 6B. The mediated coupling can be implemented in combination with the layout 600 of Figures 6A and 6B by a coupling device (eg, coupling device 506 of Figure 5).

[0171] In some implementations, controlling the magnitude of the direct connectable coupling of superconducting devices 602 and 604 includes determining a target magnitude of the connectable coupling between superconducting devices 602 and 604, determining a difference between the magnitude of the mediated connectable coupling and the target magnitude, determining an adjustment tolerance based at least in part on the difference between the magnitude of the mediated coupling and the target magnitude, and adjusting the widths of the superconducting traces of superconducting loops 606 and 610 at intersection region 618.

[0172] As mentioned above, fabrication of layout 600 can include methods for adjusting superconducting traces to achieve desired curvature and overlap (i.e., the degree to which the lines overlie each other). For example, in Figure 6B, region 642 of superconducting loop 606 has been adjusted by adjustment tolerance 646.

[0173] FIG. 7A is a schematic diagram of another exemplary layout 700 of a pair of superconducting devices 702 and 704 that are communicatively coupled to one another, with each loop of each superconducting device having an outward curvature at the intersection region, in accordance with the present systems and methods.

[0174] Layout 700 includes a pair of superconducting devices 702 and 704. Superconducting device 702 includes a superconducting loop 706 interrupted by a Josephson junction 708. Superconducting device 704 includes a superconducting loop 710 interrupted by a Josephson junction 712.

[0175] Each of superconducting devices 702 and 704 has outward bends 714 and 716, respectively (each outward bend is defined herein as a bend away from the center of each superconducting loop). Outward bends 714 and 716 are located in intersection regions 718 at or near where superconducting devices 702 and 704 intersect with one another. Outward bends 714 and 716 cause a portion of superconducting loop 706 of superconducting device 702 to be substantially parallel (or at least non-orthogonal) to a portion of superconducting loop 710 of superconducting device 704 in regions 720, 722, 724, and 726 of layout 700.

[0176] When portions of superconducting loops 706 and 710 run parallel to each other (or at least non-orthogonal), portions of superconducting loops 706 and 710 can overlie each other and / or be adjacent to each other. In some implementations, superconducting loops 706 and 710 define traces on separate layers of a multi-layer superconducting integrated circuit. The traces of superconducting loops 706 and 710 may overlie each other and / or be adjacent to each other and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The overlie and / or abutment of portions of superconducting loops 706 and 710 can create mutual inductance, which can provide direct inductive coupling between superconducting devices 702 and 704.

[0177] An excitation current flowing in direction 728 in superconducting loop 710 can induce a current flowing in direction 730 in superconducting loop 706 .

[0178] 7B is a schematic diagram of an example implementation of intersection region 718 of layout 700 of FIG. 7A in accordance with the present systems and methods. Intersection region 718 includes the region where superconducting loops 706 and 710 of superconducting devices 702 and 704 of FIG. 7A intersect with one another.

[0179] Superconducting loops 706 and 710 overlap (eg, overlie one another in a multi-layer superconducting integrated circuit) and run parallel to one another (or at least non-orthogonal) in each region 732, 734, 736, and 738.

[0180] 7B shows an example layout of layout 700 in a plan view. In some implementations, layout 700 is fabricated in a multi-layer superconducting integrated circuit using different layers for superconducting loops 706 and 710. In some implementations, the layers are fabricated using a superconducting metal and separated by an insulating layer (e.g., a layer of dielectric material). In some implementations, superconducting loops 706 and 710 comprise niobium. In some implementations, superconducting loops 706 and 710 comprise aluminum and / or another suitable superconducting material. In some implementations, the insulating layer comprises silicon dioxide.

[0181] Superconducting loops 706 and 710 may be loops of superconducting wire. The superconducting wires may overlie one another in regions 732, 734, 736, and 738, providing a direct connectable coupling for superconducting devices 702 and 704. Fabrication of layout 700 may include tailoring the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires overlie one another). For example, in FIG. 7B, regions 740, 742, and 744 of the right leg of superconducting loop 706 are tailored to produce outward bend 716 of FIG. 7A.

[0182] Fabrication of layout 700 can include creating detour paths for the superconducting traces of superconducting loops 706 and 710 inside intersection region 718 .

[0183] For example, the magnitude of the direct connectable coupling between superconducting devices 702 and 704 can be controlled by selectively adjusting superconducting loops 706 and 710 during fabrication. For example, adjusting the width of the superconducting lines of superconducting loops 706 and 710 at intersection region 718 can be achieved by selective adjustment without incurring a space penalty for the superconducting circuit. Selective adjustment of the superconducting lines can provide adjustable tuning of the magnitude of the direct connectable coupling between superconducting devices 702 and 704 over a continuous range, rather than just discrete values. In one implementation, the magnitude of the direct connectable coupling between two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediated coupling by selectively adjusting the superconducting traces and configuring the superconducting traces to follow an appropriate detour path. In one implementation, the superconducting traces are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0184] Selective tuning of the superconducting traces may be achieved by a suitable tuning width etch process. The tuning width etch process may include, for example, depositing a first hard mask layer over the layer of superconducting material, depositing a second hard mask layer over the first hard mask layer, depositing a photoresist layer over the second hard mask layer, patterning the photoresist layer, transferring the pattern to the second hard mask layer, and tuning the second hard mask layer with the photoresist layer over the second hard mask layer. During the tuning width etch, the photoresist protects the top surface of the second hard mask layer, and the overlying first hard mask layer protects the substrate.

[0185] Fabrication of superconducting traces having a desired width may be achieved by deposition of superconducting material.

[0186] The mediated coupling is not shown in Figures 7A and 7B. The mediated coupling can be implemented in combination with the layout 700 of Figures 7A and 7B by a coupling device (eg, coupling device 506 of Figure 5).

[0187] FIG. 8A is a schematic diagram of another exemplary layout 800 of a pair of superconducting devices 802 and 804 that are communicatively coupled to one another, with each loop of each superconducting device having multiple bends in the intersection region, in accordance with the present systems and methods.

[0188] Layout 800 includes a pair of superconducting devices 802 and 804. Superconducting device 802 includes a superconducting loop 806 interrupted by a Josephson junction 808. Superconducting device 804 includes a superconducting loop 810 interrupted by a Josephson junction 812. Superconducting devices 802 and 804 cross each other at crossover region 814 (shown as hatched in FIG. 8A ).

[0189] An excitation current flowing in direction 816 in superconducting loop 810 can induce a current (not shown in FIG. 8A) in superconducting loop 806 .

[0190] 8B is a schematic diagram of an example implementation of intersection region 814 of layout 800 of FIG. 8A in accordance with the present systems and methods. Intersection region 814 includes the region where superconducting loops 806 and 810 of superconducting devices 802 and 804 of FIG. 8A intersect with one another.

[0191] Superconducting loops 806 and 810 overlap (eg, overlie one another in a multi-layer superconducting integrated circuit) and run parallel to one another (or at least non-orthogonal) in each region 820, 822, 824, and 826.

[0192] 8B shows an example layout of layout 800 in a plan view. In some implementations, layout 800 is fabricated in a multi-layer superconducting integrated circuit using different layers for superconducting loops 806 and 810. In some implementations, the layers are fabricated using a superconducting metal and separated by an insulating layer of a dielectric material. In some implementations, superconducting loops 806 and 810 comprise niobium. In some implementations, superconducting loops 806 and 810 comprise aluminum and / or another suitable superconducting material. In some implementations, the insulating layer comprises silicon dioxide.

[0193] Superconducting loops 806 and 810 may be loops of superconducting wire. The superconducting wires may overlie one another in regions 820, 822, 824, and 826, providing a direct connectable coupling between superconducting devices 802 and 804. Fabrication of layout 800 may include methods for tailoring the superconducting wires to achieve desired curvatures and overlaps (i.e., the degree to which the wires overlie one another). For example, in FIG. 8B , regions 828, 830, 832, 834, 836, and 838 of the right leg of superconducting loop 806 are tailored to create a bypass path through intersection region 814.

[0194] Fabrication of layout 800 can include creating detour paths for the superconducting traces of superconducting loops 806 and 810 inside intersection region 814 .

[0195] For example, the magnitude of the direct connectable coupling of superconducting devices 802 and 804 can be controlled by selectively adjusting superconducting loops 806 and 810 during fabrication. For example, adjusting the width of the superconducting lines of superconducting loops 806 and 810 at intersection region 814 can be achieved by selectively adjusting without incurring a space penalty for the superconducting circuit. Selectively adjusting the superconducting lines allows for adjustable tuning (during fabrication) of the magnitude of the direct connectable coupling of superconducting devices 802 and 804 over a continuous range, rather than just discrete values. Changing the magnitude of the direct coupling with the previous approaches generally requires changes to the layout of the integrated circuit and / or the area occupied by the integrated circuit. These changes typically constrain the magnitude of the direct coupling to discrete values.

[0196] In one implementation, the magnitude of the direct communication coupling between two superconducting devices is adjustable over a range from 0 to twice the magnitude of the mediated coupling by selectively tuning the superconducting traces and configuring the superconducting traces to follow appropriate detour paths. In one implementation, the superconducting traces are selectively tuned from a width of 2 μm to a width of 0.5 μm.

[0197] 8C is a schematic diagram of another example implementation of intersection region 814 of layout 800 of FIG. 8A in accordance with the present systems and methods. Intersection region 814 includes the region where superconducting loops 806 and 810 of superconducting devices 802 and 804 of FIG. 8A intersect with one another. Induced current 840 flows in superconducting loop 806 in the direction indicated by the arrow, and excitation current 816 flows in superconducting loop 810 in the direction indicated by the arrow.

[0198] Superconducting loops 806 and 810 overlap (eg, overlie one another in a multi-layer superconducting integrated circuit) and run parallel to one another (or at least non-orthogonal) in each region 842, 844, 846, and 848.

[0199] FIG. 8C shows an example layout of layout 800 in a plan view. In some implementations, layout 800 is fabricated in a multi-layer superconducting integrated circuit using different layers for superconducting loops 806 and 810. In some implementations, the layers are fabricated using a superconducting metal and are separated by an intervening layer. In some implementations, the intervening layer includes an insulating layer of a dielectric material. In some implementations, superconducting loops 806 and 810 include niobium. In some implementations, superconducting loops 806 and 810 include aluminum and / or another suitable superconducting material. In some implementations, the insulating layer includes silicon dioxide and / or silicon nitride. In some implementations, an integrated circuit air bridge insulates superconducting loops 806 and 810. A typical air bridge can be formed using a layer of metal deposited and patterned on a sacrificial material. The sacrificial material can then be removed, leaving the metal traces at least partially insulated from other metal traces or features by a fluid (eg, air) rather than a dielectric (eg, silicon dioxide).

[0200] Superconducting loops 806 and 810 may be loops of superconducting wire. The superconducting wires may overlie one another in regions 842, 844, 846, and 848, providing a direct connectable coupling of superconducting devices 802 and 804. Fabrication of layout 800 may include methods for tailoring the superconducting wires to achieve desired curvatures and overlaps (i.e., the degree to which the wires overlie one another). For example, in FIG. 8B , regions 850, 852, and 854 of the right leg of superconducting loop 806 are tailored to create a bypass path through intersection region 814.

[0201] Fabrication of layout 800 can include creating detour paths for the superconducting traces of superconducting loops 806 and 810 inside intersection region 814 .

[0202] For example, the magnitude of the direct connectable coupling between superconducting devices 802 and 804 can be controlled by selectively adjusting superconducting loops 806 and 810 during fabrication. For example, adjusting the width of the superconducting lines of superconducting loops 806 and 810 at intersection region 814 can be achieved by selective adjustment without incurring a space penalty for the superconducting circuit. Selective adjustment of the superconducting lines can provide adjustable tuning of the magnitude of the direct connectable coupling between superconducting devices 802 and 804 over a continuous range, rather than just discrete values. In one implementation, the magnitude of the direct connectable coupling between two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediated coupling by selectively adjusting the superconducting traces and configuring the superconducting traces to follow an appropriate detour path. In one implementation, the superconducting traces are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0203] Mediated coupling is not shown in Figures 8A, 8B, and 8C. Mediated coupling can be implemented in combination with layout 800 of Figures 8A, 8B, and 8C by a coupling device (e.g., coupling device 506 of Figure 5).

[0204] One benefit of the systems and methods of the present application is improved robustness to manufacturing errors and / or misalignments. Another benefit of the systems and methods of the present application is improved tunability of the layout of the superconducting integrated circuit and / or direct communicable coupling between superconducting devices during manufacturing, without affecting the amount of space used by the superconducting devices and / or other devices on the superconducting integrated circuit.

[0205] Yet another benefit of the systems and methods of the present application is reduced crosstalk to neighboring devices. The implementations described herein are more compact, self-contained, and symmetrical than previous approaches, resulting in little or no crosstalk to neighboring devices.

[0206] The intersection region layouts shown in Figures 6B, 7B, 8B, and 8C are suitable for use in any of the above-described configurations where a portion of a first superconducting device overlies a portion of a second superconducting device to provide coupling, and it is understood that other intersection region layouts having bypass paths can be used as well.

[0207] 9 is a schematic diagram of an exemplary superconducting quantum processor topology 900 according to the present disclosure. A superconducting quantum processor having topology 900 may be used, for example, for quantum annealing and / or adiabatic quantum computing.

[0208] The coupling layouts described with reference to Figures 1, 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, and 8C above, and Figures 10 and 11 below, may be used in superconducting quantum processors having topology 900. Furthermore, the coupling layouts may be used in superconducting quantum processors having other suitable topologies and / or other superconducting integrated circuits.

[0209] Topology 900 includes multiple qubits, e.g., qubits 902a, 902b, 902c, and 902d (collectively referred to as qubits 902). Qubits 902 are illustrated in topology 900 in Figure 9 as points. In one implementation, each qubit in a first subset of qubits 902 includes a respective elongated superconducting loop oriented in a first direction, and each qubit in a second subset includes a respective elongated superconducting loop oriented in a second direction that is at least approximately orthogonal to the first direction.

[0210] Additionally, topology 900 includes multiple coupling devices, such as coupling devices 904a, 904b, and 904c (collectively referred to as coupling devices 904). Coupling devices 904 are illustrated in topology 900 in Figure 9 as lines. Coupling devices 904 can provide communicable coupling between pairs of qubits 902.

[0211] Each qubit 902 includes a respective elongated superconducting loop having a major axis and a minor axis. The orientation of the qubit may be defined as the direction of the major axis.

[0212] Qubits 902a and 902b are oriented at least approximately orthogonal to one another. That is, the long axes of their respective elongated superconducting loops are oriented at least approximately orthogonal to one another. Coupling device 904a (also referred to herein as an internal coupling device) can provide a communicable coupling between qubits 902a and 902b. Figures 1, 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, and 8C include examples of superconducting devices (e.g., qubits) oriented at least approximately orthogonal to one another and that can be coupled by an intermediate coupling device, referred to as an internal coupling device in the architecture of Figure 9.

[0213] Qubits 902b and 902c are oriented at least generally parallel to one another. That is, the long axes of the elongated superconducting loops of each qubit 902c and 902d are oriented at least generally parallel to one another. Qubits 902c and 902d are in the same row or column of qubits in topology 900. Coupling device 904b can provide a communicable coupling between qubits 902b and 902c.

[0214] Qubits 902a and 902d are oriented at least generally parallel to one another, i.e., the long axes of the elongated superconducting loops of each qubit 902a and 902d are oriented at least generally parallel to one another. Qubits 902a and 902d are in adjacent rows or columns of qubits in topology 900. Coupling device 904c can provide a communicable coupling between qubits 902a and 902d.

[0215] In topology 900, each qubit can be communicatively coupled to 12 orthogonally oriented qubits, for a total of 15 qubits including the 12 orthogonally oriented qubits. The communicative coupling between pairs of qubits in topology 900 can include direct coupling and / or mediated coupling through intermediate coupling devices.

[0216] 6A, 6B, 7A, 7B, 8A, 8B, and 8C illustrate pairs of superconducting devices (e.g., qubits) having at least portions of the superconducting loops of the superconducting devices running orthogonal (at least non-parallel) to one another. The superconducting loops cross one another in projection at each crossover region. At the crossover region, portions of the superconducting traces of the superconducting loops can be arranged to run parallel to one another (or at least non-orthogonal) and can be arranged sufficiently closely together so that current flowing in one of the pair of superconducting loops induces current in the other superconducting loop (i.e., portions of the superconducting traces of the superconducting loops can be arranged in inductive proximity to one another).

[0217] In other implementations, the long axes of the superconducting loops of a superconducting device run parallel to one another (or are at least non-orthogonal). In some of these implementations, the loops are arranged at least partially in parallel, and in others, the loops are arranged in series. Some of the superconducting loops can be in inductive proximity to one another, i.e., they can be arranged closely enough that current flowing in one of a pair of superconducting loops induces current in the other superconducting loop.

[0218] FIG. 10A is a schematic diagram of another exemplary layout 1000 of a pair of superconducting devices 1002 and 1004 directly and communicatively coupled to one another in accordance with the present systems and methods.

[0219] Each superconducting device 1002 and 1004 includes a respective superconducting loop 1006 and 1008. The superconducting loops 1002 and 1004 are arranged in series. Each superconducting loop 1006 and 1008 may be interrupted by a respective Josephson junction 1010 and 1012. The superconducting devices 1002 and 1004 may be superconducting qubits (e.g., superconducting flux qubits). The superconducting loops 1006 and 1008 may be in the same layer or plane as each other, or in different layers or planes from each other. In addition to being directly inductively coupled to each other, the superconducting devices 1002 and 1004 may be communicatively coupled by an intermediate coupling device (e.g., coupling device 904b in FIG. 9 ). For clarity, the intermediate coupling device is not shown in FIG. 10A .

[0220] Layout 1000 includes meeting region 1014. Meeting region 1014 is a region of an integrated circuit where portions of superconducting loops 1006 and 1008 of superconducting devices 1002 and 1004 in Figure 10A are in inductive proximity to one another. In this application, two superconducting devices are in inductive proximity to one another if they are properly oriented with respect to one another and spaced closely enough such that a first one of the two superconducting devices is directly inductively coupled to a second one of the two superconducting devices when current flows through the superconducting loop of the first superconducting device.

[0221] Superconducting devices 1002 and 1004 can be directly inductively coupled to one another at association region 1014. For example, an excitation current flowing through superconducting loop 1006 can induce a current flowing through superconducting loop 1008.

[0222] Portions of superconducting loops 1006 and 1008 run parallel to each other (or at least non-orthogonal) and are in inductive proximity to each other at meeting region 1014 .

[0223] Layout 1000 of FIG. 10 can be implemented with superconducting loops 1006 and 1008 fabricated on the same layer of a superconducting integrated circuit. The superconducting integrated circuit may be a multi-layer superconducting integrated circuit. In some implementations, the layers are fabricated using a superconducting metal and separated by insulating layers of a dielectric material. Superconducting loops 1006 and 1008 may include niobium, aluminum, and / or another suitable superconducting material. The insulating layer may include silicon dioxide.

[0224] Superconducting loops 1006 and 1008 may be loops of superconducting wire. The superconducting wire may be implemented as one or more superconducting traces, for example, in a wiring layer in a fabrication stack. The superconducting traces may also be referred to as interconnect lines. The width of the superconducting traces may also be referred to as the linewidth of the interconnect lines.

[0225] Fabrication of layout 1000 may include methods for arranging superconducting traces so that at least some of the traces are in inductive proximity to one another, i.e., run parallel to one another or at least non-orthogonal and close enough that current flow in one trace directly induces current flow in the other trace. Meeting region 1014 may include traces that are deposited and / or arranged to create a bypass path for portions of superconducting loops 1006 and 1008 through meeting region 1014.

[0226] For example, the magnitude of the direct connectable coupling between superconducting devices 1002 and 1004 can be controlled by selectively depositing and / or adjusting superconducting loops 1006 and 1008 during fabrication. For example, adjusting the width of the superconducting traces of superconducting loops 1006 and 1008 in association region 1014 can be achieved by selective adjustment without incurring a space penalty for the superconducting circuit. Selective adjustment of the superconducting traces can provide adjustable tuning of the magnitude of the direct connectable coupling between superconducting devices 1002 and 1004 over a continuous range, rather than just discrete values. In one implementation, the magnitude of the direct connectable coupling between two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediated coupling by selectively adjusting the superconducting traces and configuring the superconducting traces to follow an appropriate detour path. In one implementation, the superconducting traces are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0227] 10B is a schematic diagram of an example implementation of meeting region 1014 of layout 1000 of FIG. 10A in accordance with the present systems and methods. Meeting region 1014 includes a region 1016 where the superconducting traces of each superconducting loop 1006 and 1008 follow respective circuitous paths.

[0228] FIG. 11 is a schematic diagram of another exemplary layout 1100 of a pair of superconducting devices 1102 and 1104 directly and communicatively coupled to one another in accordance with the present systems and methods.

[0229] Each superconducting device 1102 and 1104 includes a respective superconducting loop 1106 and 1108. The superconducting loops 1102 and 1104 are arranged at least partially in parallel. Each superconducting loop 1106 and 1108 may be interrupted by a respective Josephson junction 1110 and 1112. The superconducting devices 1102 and 1104 may be superconducting qubits (e.g., superconducting flux qubits). The superconducting devices 1102 and 1104 may be communicatively coupled by an intermediate coupling device (e.g., one of the coupling devices 904 in FIG. 9 ).

[0230] 11 are inductively proximate to one another at a meeting region 1114. Superconducting devices 1102 and 1104 may be directly inductively coupled to one another at region 1110. For example, an excitation current flowing in superconducting loop 1106 may cause an induced current to flow in superconducting loop 1108.

[0231] At least portions of superconducting loops 1106 and 1108 run parallel to each other (or at least non-orthogonal) in region 1110 and are dense enough that current flow in the portion of superconducting loop 1106 directly induces current flow in the portion of superconducting loop 1108.

[0232] Layout 1100 of FIG. 11 can be implemented with superconducting loops 1106 and 1108 fabricated on the same layer of a superconducting integrated circuit. The superconducting integrated circuit may be a multi-layer superconducting integrated circuit. In some implementations, layers are fabricated using a superconducting metal and separated by insulating layers of a dielectric material. Superconducting loops 1106 and 1108 may comprise niobium, aluminum, and / or another suitable superconducting material. The insulating layers may comprise silicon dioxide. Alternatively, layout 1100 can be implemented with superconducting loops 1106 and 1108 fabricated on different layers of a multi-layer superconducting integrated circuit.

[0233] Superconducting loops 1106 and 1108 may be loops of superconducting wire. The loops of superconducting wire may include one or more superconducting traces. Fabrication of layout 1100 may include methods of tuning the superconducting traces so that at least some of the superconducting traces are in inductive proximity to one another. Region 1110 may include traces that are deposited and / or tuned to create a bypass path for portions of superconducting loops 1106 and 1108 through region 1110.

[0234] Similar to the method described above with reference to FIG. 10 , the magnitude of the direct connectable coupling between superconducting devices 1102 and 1104 can be controlled, for example, by selectively adjusting and / or attaching superconducting loops 1106 and 1108 during fabrication. For example, adjusting the width of the superconducting lines of superconducting loops 1106 and 1108 in region 1110 can be achieved by selective adjustment without incurring a space penalty for the superconducting circuit. Selective adjustment of the superconducting lines can provide adjustable tuning of the magnitude of the direct connectable coupling between superconducting devices 1102 and 1104 over a continuous range, rather than just discrete values. In one implementation, the magnitude of the direct connectable coupling between the two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediated coupling by selectively adjusting the superconducting lines and configuring the superconducting lines to follow an appropriate detour path. In one implementation, the superconducting lines are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0235] 11B is a schematic diagram of an example implementation of meeting region 1114 of layout 1100 of FIG. 11A in accordance with the present systems and methods. Meeting region 1114 includes a region 1116 where the superconducting traces of each superconducting loop 1106 and 1108 follow respective circuitous paths.

[0236] 12 shows an example of a hybrid computing system 1200 that includes a digital computer 1202 coupled to an analog computer 1204. In some implementations, the analog computer 1204 is a quantum computer and the digital computer 1202 is a classical computer.

[0237] The exemplary digital computer 1202 includes at least one digital processor 1206, and each digital processor 1206 may include one or more central processing units (not shown in FIG. 12 ). Only one digital processor 1206 is shown in FIG. 12 . The digital processor 1206 may be used to perform the classical digital processing tasks described in the present systems and methods. In other implementations, the digital computer 1202 may include more than one digital processor. Those skilled in the art will appreciate that the present systems and methods can be implemented using other digital computers, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (“PCs”), network PCs, minicomputers, mainframe computers, etc., when appropriately configured or programmed to form special-purpose machines and / or communicatively coupled to control analog computers (e.g., quantum computers).

[0238] Although digital computer 1202 is sometimes referred to herein in the singular, this is not intended to limit application to a single digital computer. The present system and method may also be practiced in a distributed computing environment where tasks or sets of instructions are performed or executed by remote processing devices that are linked through a communications network. In a distributed computing environment, computer or processor readable instructions (also referred to herein as program modules), application programs, and / or data may be stored in both local and remote memory storage devices (e.g., persistent computer or processor readable media).

[0239] The digital computer 1202 may include at least one digital processor 1206, at least one system memory 1208, and at least one system bus 1210 that provides a communicative coupling between various system components (e.g., between the system memory 1208 and the digital processor 1206). The system memory 1208 may include non-volatile memory (e.g., read-only memory (“ROM”), static random access memory (“SRAM”), flash NAND), and volatile memory (e.g., random access memory (“RAM”)) (not shown), all of which are examples of persistent computer- or processor-readable media. The system bus 1210 can use any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus.

[0240] Digital processor 1206 may be, for example, any logical processing unit having one or more cores (e.g., one or more central processing units (“CPUs”), graphics processing units (“GPUs”), digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”), programmable gate arrays (“FPGAs”), etc.).

[0241] Unless otherwise stated, the construction and operation of the various blocks shown in Figure 12 are of conventional design. As a result, such blocks will be understood by those skilled in the art and there is no need to describe such blocks in greater detail here.

[0242] The digital computer 1202 may include a user input / output subsystem 1212. In some implementations, the user input / output subsystem includes one or more user input / output components (e.g., a display 1214, a mouse 1216, and / or a keyboard 1218).

[0243] Basic input / output system ("BIOS") 1220, which may form a part of the ROM, contains the basic routines that help to transfer information between elements within digital computer 1202, such as during start-up.

[0244] Additionally, the digital computer 1202 may include other non-volatile memory 1222. The non-volatile memory 1222 may take various forms, including a hard disk drive that reads from and writes to a hard disk, an optical disk drive that reads from and writes to a removable optical disk, and / or a magnetic disk drive that reads from and writes to a magnetic disk, all of which are examples of non-transitory computer- or processor-readable media. The optical disk may be a CD-ROM or DVD, while the magnetic disk may be a magnetic floppy disk or diskette. The non-volatile memory 1222 may communicate with the digital processor via the system bus 1210 and may include an appropriate interface or controller 1224 coupled to the system bus 1210. The non-volatile memory 1222 may serve as long-term storage for computer- or processor-readable instructions, data structures, or other data (also called program modules) for the digital computer 1202.

[0245] Although digital computer 1202 is described as using hard disks, optical disks, and / or magnetic disks, those skilled in the art will appreciate that other types of non-volatile computer-readable media (such as magnetic cassettes, flash memory cards, flash, ROM, smart cards, etc., which are all further examples of persistent computer or processor-readable media) can be used. Those skilled in the art will appreciate that some computer architectures combine volatile and non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory. Or, solid-state disks use integrated circuits to provide non-volatile memory. Some computers place data traditionally stored on disk in memory. Similarly, some media traditionally considered volatile can have non-volatile forms (e.g., a non-volatile dual in-line memory module variant of a dual in-line memory module).

[0246] Various sets of computer or processor readable instructions (also referred to herein as program modules), application programs, and / or data can be stored in system memory 1208. For example, system memory 1208 may store an operating system 1226 and a set of computer or processor readable server instructions (i.e., server modules) 1228. In some implementations, server modules 1228 include instructions for communicating with remote clients and scheduling the use of resources, including resources on digital computer 1202 and analog computer 1204. For example, web server applications and / or web client or browser applications that enable digital computer 1202 to exchange data with sources and other server applications running on server computers over the Internet, a corporate intranet, or other networks.

[0247] In some implementations, the system memory 1208 may store other sets of computer or processor readable instructions 1230 (e.g., computational instructions, analog computer interface instructions, etc.).

[0248] Although server instructions 1228, other instructions 1230, and other data (not shown in FIG. 12) are shown in FIG. 12 as being stored in system memory 1208, they may also be stored elsewhere, including in non-volatile memory 1222, or one or more other non-transitory computer- or processor-readable media.

[0249] Analog computer 1204 can be provided in an isolated environment (not shown in FIG. 12 ). For example, if analog computer 1204 is a quantum computer, the isolated environment shields the internal components of the quantum computer from heat, magnetic fields, etc., and other external noise (not shown in FIG. 12 ) and / or cools the analog processor to a temperature at or below which the circuitry of analog processor 1204 becomes superconducting. In contrast, digital computer 1202 typically operates at very high temperatures (e.g., room temperature) where superconductivity does not occur and / or may use materials that are not superconducting at or below the critical temperature. Analog computer 1204 includes analog processor 1232. Examples of analog processor 1232 include quantum processors (e.g., superconducting quantum processors).

[0250] The quantum processor includes programmable elements (e.g., qubits, couplers, and other devices). The qubits can be read out via readout system 1234. The readouts can be provided to various sets of computer- or processor-readable instructions for digital computer 1202, including server module 1228, or other modules 1230 stored in non-volatile memory 1222, back over a network, etc. The qubits can be controlled via qubit control system 1236. In some implementations, qubit control system 1236 and coupler control system 1238 are used to perform quantum annealing in analog processor 1232, as described herein. In some implementations, analog processor 1232 includes a conducting integrated circuit 1240 including superconducting qubits with mediated and / or direct qubit-qubit coupling according to various implementations described above.

[0251] In some implementations, the digital computer 1202 can operate in a networked environment using logical connections to at least one client computer system. In some implementations, the digital computer 1202 is coupled through logical connections to at least one database system. These logical connections may be formed using any means of digital communication over a network, such as, for example, a local area network ("LAN") or a wide area network ("WAN"), including the Internet. The networked environment may include wired or wireless enterprise-wide computer networks, intranets, extranets, and / or the Internet. Other embodiments may include other types of communication networks (e.g., telecommunications networks, cellular networks, paging networks, and other mobile networks). Information sent or received over the logical connections may be encrypted or unencrypted. When used in a LAN networking environment, the digital computer 1202 may be connected to the LAN through an adapter or network interface card ("NIC"), which is communicatively linked to the system bus 1210. When used in a WAN networking environment, the digital computer 1202 may include an interface and modem (not shown) or device (e.g., a NIC) for establishing communications over the WAN. Additionally or alternatively, non-networked communications may be used.

[0252] 13A is a cross-section of a portion of a superconducting integrated circuit 1300a in accordance with the present systems and methods. The superconducting integrated circuit 1300a includes a substrate 1302. The substrate 1302 may be, for example, a silicon substrate or a layer of dielectric material. The superconducting integrated circuit 1300a further includes a pair of superconducting traces 1304 and 1306 separated from each other by an intervening layer 1308, with the superconducting trace 1306 overlying the superconducting trace 1304. The superconducting traces 1304 and 1306 may include or consist of a superconducting metal (e.g., niobium or aluminum). The superconducting traces 1304 and 1306 may be adjacent to layers of dielectric material 1310 and 1312, respectively. The intervening layer 1308 may be an insulating layer. The insulating layer may include a layer of dielectric material or an air bridge. The thickness of intervening layer 1308 may be selected to directly inductively couple superconducting traces 1304 and 1306 to one another.

[0253] FIG. 13B is a cross-section of a portion of a superconducting integrated circuit 1300b in accordance with the present systems and methods. The superconducting integrated circuit 1300b includes a substrate 1314. The substrate 1314 may be, for example, a silicon substrate or a layer of dielectric material. Furthermore, the superconducting integrated circuit 1300b includes a pair of adjacent superconducting traces 1316 and 1318 separated from one another by an intervening layer 1320. The superconducting traces 1316 and 1318 may include or consist of a superconducting metal (e.g., niobium or aluminum). The superconducting traces 1316 and 1318 may be adjacent to an upper layer of dielectric material 1322. The intervening layer 1320 may be an insulating layer. The insulating layer may include a layer of dielectric material or an air bridge. The separation of adjacent superconducting traces 1316 and 1318 by the intervening layer 1320 may be selected to allow the superconducting traces 1316 and 1318 to be directly inductively coupled to one another.

[0254] Superconducting traces 1304 and 1306 in Figure 13A lie on top of each other. Superconducting traces 1304 and 1306 are separated by an interposer 1308. Superconducting traces 1304 and 1306 can be inductively close to each other, i.e., can be properly oriented and spaced closely enough such that current in superconducting trace 1304 can induce current in superconducting trace 1306 (and vice versa), regardless of the orientation of the superconducting integrated circuit. Superconducting traces 1316 and 1318 in Figure 13B are adjacent to each other. Superconducting traces 1316 and 1318 are separated by an interposer 1320. The superconducting traces can be inductively close to each other, i.e., can be properly oriented and spaced closely enough such that current in superconducting trace 1316 can induce current in superconducting trace 1318 (and vice versa), regardless of the orientation of the superconducting integrated circuit.

[0255] 14A is a flowchart of an example method 1400 of forming an integrated circuit according to the present systems and methods. Method 1400 includes operations 1402-1418, although one skilled in the art will appreciate that in alternative implementations, certain operations may be omitted and / or additional operations may be added. One skilled in the art will appreciate that the illustrated order of operations is shown for illustrative purposes only and may be varied in alternative implementations.

[0256] At 1402, method 1400 is invoked. In some implementations, a manufacturing system invokes method 1400 when it is ready to begin manufacturing an integrated circuit or continue manufacturing a partially completed integrated circuit. At 1404, the system determines a target magnitude of a communicable coupling between a pair of devices (e.g., superconducting devices) on the integrated circuit. At 1406, the system determines a difference between the magnitude of the mediated communicable coupling and the target magnitude. The mediated communicable coupling may be provided by an mediated coupling device (e.g., one of coupling devices 904 of FIG. 9 ).

[0257] At 1408, the system determines an adjustment tolerance (also referred to in this application as an adjustment range) based at least in part on the difference between the magnitude of the mediated coupling and the target magnitude. The adjustment range determined at 1408 is referred to as the determined adjustment range with reference to FIG. 14B.

[0258] At 1410, the system deposits a first loop of material (e.g., a superconducting metal), and at 1412, the system deposits a second loop of material. In some implementations, the system deposits the first and second loops of material to achieve a predetermined communicable bond, including narrowing of the traces at the intersection or meeting regions, and / or a bypass path, as described above. In other implementations, the system performs a controlled width etch to form a first path at 1414 and a second path at 1416.

[0259] At 1418, the method ends.

[0260] 14B is a flowchart of an example method 1419 for adjusting the first pass 1414 of method 1400 (FIG. 14A) in accordance with the present systems and methods. Method 1419 includes operations 1420-1428, although one skilled in the art will appreciate that in alternative implementations, certain operations can be omitted and / or additional operations can be added. One skilled in the art will appreciate that the illustrated order of operations is shown for illustrative purposes only and can vary in alternative implementations. A similar method can be used to perform an adjusted width etch to form the second pass at 1416 of method 1400 (FIG. 14A).

[0261] At 1420, the system deposits a first hard mask, and at 1422, the system deposits a second hard mask. At 1424, the system deposits a photoresist layer and patterns the photoresist layer at 1426. At 1428, the system performs an etch to remove material from the first path to achieve the predetermined alignment width and target size.

[0262] Although the example implementations of the present technology described above include direct inductive coupling between superconducting devices, other implementations include direct galvanic coupling between superconducting devices. There may be direct galvanic coupling between superconducting devices instead of or in addition to direct inductive coupling between the same superconducting devices. A direct galvanic coupling between two superconducting devices may include a shared portion of a superconducting loop of one device with a superconducting loop of the other device. A direct galvanic coupling may increase the magnitude of coupling between the superconducting devices. Other implementations include capacitive coupling between superconducting devices, alone or in combination with direct coupling according to the present systems and methods, and / or mediated coupling according to the present systems and methods, and / or a combination of direct and mediated coupling. For a description of various coupling topologies, including galvanic and capacitive coupling, see, for example, PCT Patent Application Publication No. WO2019126396A1, "SYSTEMS AND METHODS FOR COUPLING QUBITS IN A QUANTUM PROCESSOR."

[0263] Although the example implementations of the present technology described above include a direct connectable coupling between a pair of superconducting devices, other implementations include a direct connectable coupling between more than two superconducting devices. In general, connectable coupling between two or more superconducting devices according to the present technology may include a combination of inductive, galvanic, direct, and mediated connectable coupling. The layouts described above, and the selective adjustment of superconducting traces to achieve a desired coupling magnitude, are suitable for use in a variety of these arrangements.

[0264] In some implementations, direct coupling between superconducting devices in the quantum processor is used for only a select subset of the superconducting devices in the quantum processor.

[0265] The advantages of this technology may include: The layout implementation can be symmetric and compact, and the layout does not require any additional work on the qubit body (unlike other approaches). The magnitude of the direct coupling can be controlled by appropriate selection of the width of the tuning strip without any layout space penalty. For example, continuous tuning of the coupling magnitude from 0 to twice the magnitude of a typical mediated coupling can be achieved. The trace can be tuned, for example, from 2 μm wide to 0.5 μm wide. The technique is extensible to more symmetric / multiplexed implementations. The technique is robust to manufacturing misalignments and defects. One reason for the robustness to manufacturing errors (e.g., layer-to-layer misalignment) is the symmetrical arrangement, which provides at least some protection of the direct coupling magnitude from manufacturing errors. In one implementation, the direct coupling is robust to layer-to-layer misalignment of up to 120 nm.

[0266] Throughout this specification and the appended claims, for example, when used to describe the susceptibility of a coupling device, the term "ferromagnetic region" is used to describe a range of magnetic flux biases that can be applied to a coupling device to ferromagnetically couple a pair of superconducting devices that are communicatively coupled by the coupling device. Similarly, throughout this specification and the appended claims, for example, when used to describe the susceptibility of a coupling device, the term "antiferromagnetic region" is used to describe a range of magnetic flux biases that can be applied to a coupling device to antiferromagnetically couple a pair of superconducting devices that are communicatively coupled by the coupling device.

[0267] Throughout this specification and the appended claims, the terms "coupler" and "coupling device" are used interchangeably. However, both "coupler" and "coupling device" are used to describe a coupling loop of superconducting material interrupted by at least one Josephson junction that can be used to ferromagnetically or antiferromagnetically couple a pair of superconducting devices together. Furthermore, throughout this specification and the appended claims, the term "pair of communicably coupled superconducting devices" is used to describe a pair of superconducting devices that can be ferromagnetically or antiferromagnetically coupled together by a direct coupling or a coupling device.

[0268] Throughout this specification and the appended claims, when used to describe a physical structure such as a "loop of superconducting material," the term "superconducting" is used to indicate a material that can behave as a superconductor at an appropriate temperature. The superconducting material does not necessarily function as a superconductor at all times in all embodiments of the present systems and methods.

[0269] The above description of exemplary implementations, including what is set forth in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made without departing from the spirit and scope of the disclosure. The teachings provided herein of various embodiments can be applied to other analog processors (not necessarily the exemplary quantum processors generally described above).

[0270] The various embodiments described above can be combined to provide further embodiments. All commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referenced in this specification and / or listed in Application Data Sheets, including, but not limited to, U.S. Patent No. 9,129,224, entitled "SYSTEMS AND METHODS FOR INCREASING THE ENERGY SCALE OF A QUANTUM PROCESSOR," PCT Patent Application Publication No. WO 2019 / 126396 A1, entitled "SYSTEMS AND METHODS FOR COUPLING QUBITS IN A QUANTUM PROCESSOR," and U.S. Patent Application No. 63 / 046,394, entitled "SYSTEMS AND METHODS FOR COUPLING BETWEEN QUBITS," are hereby incorporated by reference in their entirety. These and other changes can be made to embodiment implementations in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. 1. A method of tuning a magnitude of a communicable coupling between a first superconducting device and a second superconducting device, wherein the magnitude of the communicable coupling is a sum of a magnitude of a mediated communicable coupling and a direct communicable coupling; determining a target magnitude of the communicable coupling between the first and second superconducting devices; determining a difference between the magnitude of the mediated communicable coupling and the magnitude of the target; determining an adjustment tolerance based at least in part on the difference between the magnitude of the intermediary communicable coupling and the target magnitude; attaching a first superconducting loop of the first superconducting device to a first layer; depositing a second superconducting loop of the second superconducting device on a second layer, the second superconducting loop intersecting the first superconducting loop to form an intersecting region; following a first detour path and adjusting at least a portion of the first superconducting loop within the intersection region by the adjustment tolerance so as to be narrower than at least a portion of the first superconducting loop outside the intersection region; following a second bypass path and adjusting at least a portion of the second superconducting loop within the intersection region by the adjustment tolerance so that the second superconducting loop is narrower than at least a portion of the second superconducting loop outside the intersection region, so that the first bypass path and the second bypass path are inductively close to each other for at least a portion of the length of the first bypass path; A method comprising:

2. The method of claim 1 further comprising applying an intervening layer between the first layer and the second layer.

3. The method of claim 2 , wherein depositing an intervening layer between the first layer and the second layer comprises depositing an insulating layer.

4. The method of claim 3 , wherein depositing an insulating layer comprises depositing a layer of dielectric material and / or forming an air bridge.

5. 10. The method of claim 1, wherein attaching the second superconducting loop of the second superconducting device to the second layer comprises attaching the second superconducting loop of the second superconducting device to the second layer such that at least a portion of the second layer overlies at least a portion of the first layer.

6. 10. The method of claim 1, wherein tuning at least a portion of the first superconducting loop by the tuning tolerance comprises tuning the at least a portion of the first superconducting loop to a width between 0.5 μm and 2.0 μm.

7. 2. The method of claim 1, wherein tuning at least a portion of the first superconducting loop by the tuning tolerance comprises performing a tuning width etch of the at least a portion of the first superconducting loop.

8. performing a tailored width etch of the at least a portion of the first superconducting loop; depositing a first hard mask overlying at least a portion of the at least a portion of the first superconducting loop; depositing a second hard mask overlying at least a portion of the first hard mask; depositing a photoresist layer overlying at least a portion of the second hard mask; patterning the photoresist layer to define a predetermined adjustment range; Etching the at least a portion of the first superconducting loop to remove the predetermined adjustment width; The method of claim 7, comprising:

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