Hybrid Architecture for Zero Border Displays

Abstract

To provide a configuration having a configurable size and shape to omit an area taken for driver ledge by facilitating manufacture of a reduced border or zero border tile-based display panel arrangement.SOLUTION: A hybrid architecture and method operate a display panel. In a hybrid pixel driver chip, each row of a pixel driver chip 110 includes a group of backbone hybrid pixel driver chips 110B and a group of LED driving pixel driver chips 110D, routing of a bus column 515 and the backbone hybrid pixel driver chips 110B forms a backbone of a tile 410, and the backbone hybrid pixel driver chips 110B and the LED driving pixel driver chips 110D are respectively configured only to be different to different functions, have different internal circuits, or are connected differently.SELECTED DRAWING: Figure 5B

Description

[Technical Field]

[0001] (Related Applications) This application claims the benefit of priority to pending U.S. patent application Ser. No. 16 / 356,914, filed March 18, 2019, and U.S. provisional patent application Ser. No. 62 / 686,297, filed June 18, 2018, which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION The embodiments described herein relate to display systems, and more particularly to passive matrix displays and methods of operation. [Background technology]

[0003] Display panels are utilized in a wide range of electronic devices. Common types of display panels include active matrix display panels, in which each pixel element, e.g., a light emitting diode (LED), can be individually driven to display a data frame, and passive matrix display panels, in which rows and columns of pixel elements can be driven in a data frame. Both active matrix and passive matrix display panels have been proposed for the production of tiled displays, where the display panel dimensions are larger than the limits imposed by the substrate and equipment size constraints. Summary of the Invention

[0004] A hybrid architecture display panel and method of operation are described. In one embodiment, the display panel includes a bus array of global signal lines, multiple rows of row function signal lines, and multiple rows of pixel driver chips, each row of pixel driver chips connected to a corresponding row of row function signal lines, and each pixel driver chip connected to a corresponding matrix of light emitting diodes (LEDs). Each row of pixel driver chips can include a group of backbone hybrid pixel driver chips and a group of LED-driving pixel driver chips. The bus array of global signal lines is coupled to the group of backbone hybrid pixel driver chips in each row of pixel driver chips, and each separate backbone hybrid pixel driver chip includes an input connected to a corresponding global signal line and an output connected to a corresponding row function signal line in the corresponding row of row function signal lines to send a corresponding driven signal to the corresponding row of pixel driver chips.

[0005] In one embodiment, the hybrid pixel driver chip includes a VST driver circuit for determining whether a particular row is on or off and for propagating a VST signal from the top to the bottom of the display panel. In addition, the hybrid pixel driver chip includes a signal modulator circuit for selecting whether to use a global row function signal line or a backup line input and for sending an internal signal to a multiplexer driver circuit to generate a manipulated row function signal. In addition, the hybrid pixel driver chip includes an LED drive circuit 1460 to drive a corresponding matrix of LEDs. Thus, the hybrid pixel driver chip includes a hybrid architecture for supporting row driver and pixel driver functions.

[0006] In one embodiment, a method for programming a display includes propagating VST signals to rows of pixel driver chips, receiving token driver configuration data at a backbone hybrid pixel driver chip, receiving a global configuration update pulse at the backbone hybrid pixel driver chip, receiving row driver configuration data at a token-activated backbone hybrid pixel driver chip, and sending steered configuration update signals from the backbone hybrid pixel driver chip to the rows of pixel driver chips. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic top view of a local passive matrix display including rows of hybrid pixel driver chips according to one embodiment.

[0008] [Figure 2] 1 is a schematic diagram of a matrix of light emitting diodes (LEDs) coupled to terminals of a hybrid pixel driver chip, according to one embodiment.

[0009] [Figure 3] FIG. 1 is a schematic diagram of a matrix of redundant pairs of LEDs being driven by redundant pairs of hybrid pixel driver chips according to one embodiment.

[0010] [Figure 4] FIG. 1 is a schematic top view of a tile-based display panel with cutouts and splined corners, according to one embodiment.

[0011] [Figure 5A] FIG. 1 is a schematic top view of a tile-based display including a tile backbone of hybrid pixel driver chips acting as row drivers according to one embodiment.

[0012] [Figure 5B]FIG. 5B is a schematic top view of a display tile partition of the display of FIG. 5A from a data and configuration update perspective, according to one embodiment.

[0013] [Figure 6] FIG. 1 is a routing diagram of row function partitioning within a hybrid pixel driver chip backbone according to one embodiment.

[0014] [Figure 7] FIG. 10 is a layout diagram of row control signal redundancy and backup within a hybrid pixel driver chip backbone according to one embodiment.

[0015] [Figure 8] FIG. 10 is a routing diagram of emission frame synchronization and emission row synchronization buffering within a row of a pixel driver chip, according to one embodiment.

[0016] [Figure 9] FIG. 10 is a routing diagram for vertical signal redundancy and light emitting clock vertical and horizontal buffering according to one embodiment.

[0017] [Figure 10] FIG. 10 is a routing diagram of rows of a hybrid pixel driver chip and backbone routing of global signal lines to row signal lines, according to one embodiment.

[0018] [Figure 11] FIG. 10 is a routing diagram of horizontal control signal redundancy for VST and backup line connections according to one embodiment.

[0019] [Figure 12] FIG. 10 is a routing diagram of horizontal control signal redundancy for row function signal connections according to one embodiment.

[0020] [Figure 13]FIG. 2 is a routing diagram of the connections of global and row signal lines to and from the backbone of a tile-based display panel according to one embodiment.

[0021] [Figure 14] FIG. 1 is a block circuit diagram of a backbone hybrid pixel driver chip according to one embodiment.

[0022] [Figure 15] FIG. 10 is a timing diagram of data loading for a token-activated hybrid pixel driver chip according to one embodiment.

[0023] [Figure 16] 1 is a flowchart of a method for programming a display tile from reset according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0024] In embodiments, a hybrid architecture and method for operating a display panel is described in which row function circuitry and pixel drive function circuitry are combined within the backbone of a hybrid pixel driver chip. In this way, designated row driver chips can be eliminated, reducing total silicon chip area. Additionally, this arrangement facilitates the manufacture of tile-based display panel arrangements with configurable sizes and shapes and reduced or zero borders, eliminating area traditionally reserved for driver bases.

[0025] In some embodiments, a tile-based display panel may include an arrangement of pixel driver chips for driving a local matrix of pixels in a local passive matrix (LPM). Compared to direct-drive approaches, an LPM arrangement according to embodiments may significantly reduce the silicon area associated with the pixel driver and the panel peak panel current when all pins of the pixel driver are connected to one LED. In some embodiments, the pixel driver chips are distributed among the LEDs. Such a configuration may include pixel driver chips located laterally between LEDs on the same side of the display substrate. Depending on the complexity, pixel driver chips may be longer than the corresponding LED matrix they control (e.g., wider than the length of the corresponding matrix row). As a result, pixel driver chips may be staggered, for example, in zigzag-patterned rows. The pixel driver chips need not be mounted on the same surface as the LEDs or between the LEDs. According to all embodiments described herein, the pixel driver chip may also be disposed within the display substrate, and may be disposed upward (e.g., with terminals facing upward toward the LEDs), downward (e.g., with terminals facing away from the LEDs), or both (with terminals on both the top and bottom sides). Thus, while pixel driver chips are described herein as being distributed around or interspersed within the display area, it should be understood that the pixel driver chips may be on the display substrate (e.g., surface-mounted) or embedded within the display substrate. According to all embodiments described herein, the pixel driver chip may be adjacent to a corresponding number of pixels. Similarly, this includes configurations of pixel driver chips both on or within the display substrate, where the pixel driver chip is adjacent to the LEDs on the display substrate. Tiled LPM displays according to embodiments may be implemented in both large-area displays and high-resolution displays with high pixel density.Furthermore, the LED and pixel driver chip sizes are scalable from macro to micro sizes: in one embodiment, the pixel driver chip may have a maximum dimension of less than 200 μm or even less than 100 μm, and the LED maximum dimension may be less than 100 μm or even less than 20 μm, for example less than 10 μm, or even less than 5 μm for high resolution and high pixel density displays.

[0026] Various embodiments are described with reference to the figures. However, some embodiments may be practiced without one or more of these specific details and in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions, and processes, to provide a thorough understanding of the embodiments. In other instances, well-known techniques and components have not been described in particular detail to avoid unnecessarily obscuring the embodiments. Throughout this specification, references to "one embodiment" mean that a particular feature, structure, configuration, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, references to the phrase "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0027] FIG. 1 is a schematic top view of a local passive matrix display 100 including rows [1, 2, . . . N] of pixel driver chips 110, according to one embodiment. Each pixel driver chip 110 may include two portions, or slices 0 and 1, for operating a pixel matrix 102 above and below the pixel driver chip 110. Slices 0 and 1 may be separated into a primary / redundant or master / slave configuration. Each matrix 102 may include multiple LEDs 104 and multiple pixels 106. In some configurations, rows of pixel driver chips 110 are arranged in alternate rows, either rows of primary pixel driver chips (e.g., rows 1 and 3, etc.) or rows of redundant pixel driver chips 110 (e.g., rows 2 and 4, etc.). It should be understood that the number and size of pixel driver chips 110 within the display area 105 are not necessarily drawn to scale and have been enlarged for illustrative purposes.

[0028] In general, a local passive matrix display 100 may include a display substrate 101, a display area 105, optional column driver or signal line driving circuitry, and external control circuitry 140 attached to the display substrate 101 and providing various control signals, video signals, and power supply voltages to the display substrate 101.

[0029] Referring now to FIG. 2 , a schematic diagram of a matrix 102 of light-emitting diodes (LEDs) coupled to terminals of a pixel driver chip is provided, according to one embodiment. In one embodiment, a local passive matrix display includes a pixel driver chip 110, a plurality of pixels 106 arranged in a plurality of display rows, and a plurality of terminals 111 of the pixel driver chip 110 coupled to the LEDs 104 of the plurality of pixels 106. As shown in FIG. 2 , a portion of the terminals 111 are coupled to corresponding row line switches and level shifters in the pixel driver chip 110 and to corresponding rows of LEDs 104, and a portion of the terminals 111 are coupled to output drivers 116 of the pixel driver chip 110 and to corresponding columns of LEDs 104. For example, interconnects 112 may connect row electrodes (e.g., cathodes) of LEDs 104 to corresponding row line switches and level shifters, while interconnects 114 may connect column electrodes (e.g., anodes) of LEDs 104 to corresponding output drivers 116, or vice versa. The particular embodiment shown in Figure 2 is shown as a matrix 102 of LEDs 104 connected to a portion of a pixel driver chip 110, more specifically, to "slice 1" of the pixel driver chip 110. Similar connections may be provided for a second portion, or "slice 0," of the pixel driver chip 110. It should be understood that the use of the term "slice" is for simplification and in no way implies a geometric division of the circuitry within the pixel driver chip 110, but instead is a simple reference to the top and bottom connections shown. Additionally, the particular choice of eight rows and six columns of LEDs in the matrix is ​​exemplary, and embodiments are not so limited.

[0030] In one embodiment, the first terminal 111A of the pixel driver chip 110 is coupled to a first row of the plurality of pixel light emitting diodes (LEDs) 104, the second terminal 111B of the pixel driver chip 110 is coupled to a second row of the plurality of pixel LEDs, and the third terminal 111C is coupled to a first column of the plurality of pixel LEDs, the first column of LEDs including a first LED of a first string (e.g., row) of LEDs and a first LED of a second string (e.g., row) of LEDs. The fourth terminal 111D is coupled to a second column of the plurality of pixel LEDs, the second column of LEDs including a second LED of the first string of LEDs and a second LED of the second string of LEDs. As shown, the third terminal may be coupled to a first output driver 116 of the pixel driver chip, and the fourth terminal may be coupled to a second output driver 116 of the pixel driver chip. As shown in FIG. 1, the pixel driver chip 110 may be arranged in rows of pixel driver chips in lines across the display substrate. In other embodiments, the rows of pixel driver chips may be curved to follow the display area of ​​the display substrate.

[0031] In the illustrated embodiment, the rows of LEDs 104 correspond to different emitting colors of LEDs, such as red (R), green (G), and blue (B) in an RGB pixel arrangement. Alternative pixel arrangements may also be used.

[0032] FIG. 3 is a schematic diagram of a matrix of redundant pairs of LEDs driven by redundant pairs of pixel driver chips, according to one embodiment. FIG. 3 illustrates a matrix 102 similar to that shown in FIG. 2 with the addition of redundant LEDs 104 within pixels 106. In such an embodiment, a portion (slice 1) of pixel driver chip 110N-1 includes terminals 111 coupled to the LEDs 104, similar to that described with reference to FIG. 2. Additionally, within the same matrix 102, a portion (slice 0) of pixel driver chip 110N, e.g., the next row of pixel driver chips, is also coupled to the redundant LEDs 104 with separate interconnects 112, 114. In this manner, providing separate anode and cathode contacts for pixel driver chip N-1 and pixel driver chip N can prevent timing conflicts between the primary driver portions and pixel driver portions (e.g., slice 0, slice 1) associated with the same matrix 102.

[0033] In one embodiment, such as that shown in Figure 3, separate cathodes may be provided for the primary and redundant portions or slices of the pixel driver chip 110. In one method of operation, half of the pixel driver chip 110 (e.g., the primary pixel driver chip 110) is active by default. Thus, all other rows of the pixel driver chip 110 are active. The LEDs 104 coupled to the pixel driver chip 110 may also be staggered to, for example, mitigate visual artifacts.

[0034] In some embodiments, the master portion, or slice 0, of each pixel driver chip is default active for each pixel driver chip, and the slave portion, or slice 1, of each pixel driver chip is default inactive. Thus, if the master or primary portion from an adjacent pixel driver chip malfunctions or is inactive, only the slave or redundant portion becomes active. In some embodiments, a portion of the primary pixel driver chip, or both slices 0 and 1, are default active, while the corresponding portion of the redundant pixel driver chip, or slice 0 and 1, is default inactive. Thus, if an adjacent primary pixel driver chip portion malfunctions or is inactive, a portion or the entire redundant pixel driver chip becomes active. According to embodiments, the arrangement of the LED matrix, pixel driver chips, and redundancy configuration can result in a particular LED lighting sequence in the operation of the display panel.

[0035] FIG. 4 is a schematic top view of a tile-based display panel with cutouts 530 and splined corners, according to one embodiment. In particular, the placement of pixel driver chips 110 according to an embodiment can eliminate the requirement for driver borders on the edges of the display panel. As a result, the display substrate 101 can have a reduced or zero border outside the display area. This configuration can facilitate the formation of display panels with curved edges, as well as the formation of cutouts 530. Additionally, this configuration can facilitate modular placement, including micro placement, of display tiles 410. In general, a control circuit 140 can be coupled to the edge of the display substrate 101. A bus array 515 of global signal lines can extend from the control circuit 140 to provide global signals to the display panel. For example, the global signal lines can include at least a data clock line 510 and an emission clock line 520. The global signal lines can be coupled to multiple “hybrid” pixel driver chips, which together form the backbone of the display, or display tile 410. The corresponding backbone hybrid pixel driver chip receives the global signals and then transmits steered signals to a corresponding row 404 of row signal lines connected to other pixel driver chips 110 in the same row. For example, the global data clock and emission clock signals may be converted into steered signals and transmitted along steered data clock lines 510M and steered emission clock lines 520M to the row of pixel driver chips 110. For example, the steered signals may contain only the necessary information for a particular row.

[0036] A tile-based display panel according to an embodiment may have various arrangements of display tiles 410. For example, the display tiles 410 may be arranged side-by-side (horizontally), stacked (vertically), both, and in other configurations. In addition, a bus array 515 of global signal lines may be aligned and connected to the stacked display tiles 410.

[0037] FIG. 5A is a schematic top view of a tile-based display including a tile backbone 402 of hybrid pixel driver chips functioning as row drivers, according to one embodiment. FIG. 5B is a schematic top view of a display tile partition of the display of FIG. 5A from a data and configuration update perspective, according to one embodiment. A display according to an embodiment may include a display panel including multiple tiles 410. The tiles 410 may be formed from the same or multiple display substrates 101. The control circuitry 140 of FIG. 1 may be implemented on a printed circuit board 430 connected to the display substrate 101 with, for example, a flex circuit or chip-on-film 432. Bus columns 515 and data lines 440 may extend from the control circuitry to the display substrate 101. Column drivers 430 may optionally be disposed on the display substrate 101 to buffer global signal lines in the bus columns 515 and / or data lines 440. Each tile 410 may include one or more bus columns 515 of global signal lines, multiple rows 404 of row function signal lines, and multiple rows of pixel driver chips 110, each row of pixel driver chips 110 connected to a corresponding row of row function signal lines 404. In addition, each pixel driver chip 110 is connected to a corresponding matrix 102 of LEDs 104, as described with respect to Figures 1-3.

[0038] As shown in FIG. 5B , each row of pixel driver chips 110 includes a group of backbone hybrid pixel driver chips 110B and a group of LED drive pixel driver chips 110D. The bus column 515 and the routing of the backbone hybrid pixel driver chips 110B may form the backbone 402 of the tile 410. Each of the backbone hybrid pixel driver chips 110B and the LED drive pixel driver chips 110D may be hybrid pixel driver chips configured differently only for different functions. Alternatively, the chips 110B and 110D may have different internal circuits. The backbone hybrid pixel driver chips 110B and the LED drive pixel driver chips 110D may also be connected differently. According to an embodiment, each of the backbone hybrid pixel driver chips 110B and the LED drive pixel driver chips 110D is connected to a corresponding matrix 102 of LEDs 104, as described with respect to FIGS. 1-3.

[0039] According to an embodiment, a bus column 515 of global signal lines is coupled to a group of backbone hybrid pixel driver chips 110B in each row of pixel driver chips 110, and each separate backbone hybrid pixel driver chip 110B includes an input connected to a corresponding global signal line (e.g., 622, 621, 614, 613, 605, 680, 681) and an output connected to a corresponding row function signal line (e.g., 613M, 614M) in a corresponding row 404 of row function signal lines to transmit a corresponding repeating global signal to the corresponding row of pixel driver chips 110.

[0040] 5B and described in further detail below, exemplary global signal lines forming bus column 515 may include, among others, global data clock_0 622, global data clock_1 621, hybrid driver configuration update_0 614, global configuration update_1 613, vertical selection token (VST) 605, vertical selection token scan clock 680, and vertical selection token row capture clock 681. In this context, the distinction between signal lines 0 / 1 is made due to adjacent pairs of pixel driver chips 110 sharing a common data 440 line. Thus, the same data signal may be sent to two pixel driver chips 110 in the same row, and the global signal lines are used to distinguish the pairs. In particular, the backbone hybrid pixel driver chip 110B according to an embodiment is configured to receive a designated global signal and then transmit a manipulated row function signal to a corresponding row 404 of row function signal lines coupled to a corresponding row of hybrid pixel driver chips 110, including multiple LED driving pixel driver chips 110D and one or more of the other backbone hybrid pixel driver chips 110B in the row of pixel driver chips (e.g., the global signal is manipulated to form the manipulated row function signal).

[0041] FIG. 6 is a routing diagram of row function partitioning within a hybrid pixel driver chip backbone, according to one embodiment. It should be understood that the connections shown in FIG. 6 represent a general high-level partitioning, and that actual implementations may be more complex. As shown, a bus bank 515 of global signal lines may include a global configuration update 610, a global data clock 620, a global light-emitting row sync 630, and a global light-emitting frame sync 640. A global light-emitting clock line may also be included. Additionally, in some embodiments, light-emitting clocks may be associated with different colored light-emitting LEDs, although this is not required. For example, there may be a global light-emitting clock red 650 and a global light-emitting clock blue-green 660. Each backbone hybrid pixel driver chip 110B may then transmit a driven row signal 610M-660M to a corresponding row 404 of row signal lines. These steered row signals 610M-660M may be sent to some or all of the other backbone hybrid pixel driver chips 110B, as well as to the LED-driving pixel driver chips 110D in the corresponding rows of the pixel driver chip 110. As will become clear in the detailed examples below, the global signal lines may further include odd / even index 1 / 0 or primary / redundant signal lines.

[0042] 7 is a layout diagram of row control signal redundancy and backup within a hybrid pixel driver chip backbone, according to one embodiment. As shown, the rows of hybrid pixel driver chips 110 and the rows of row signal lines 404 may be partitioned into odd and even indices to provide control signal redundancy and backup in case of a defective backbone hybrid pixel driver chip 110B. For example, a staggered arrangement of pixel driver chips 110 may include an odd partition (e.g., the top chip) and an even partition (e.g., the bottom chip). Bus column 515 may include partitions of global signal lines, including global hybrid driver configuration update 0 / 1 (614, 613), global data clock 0 / 1 (622, 621), global light emission row sync 0 / 1 (632, 631), global light emission frame sync 0 / 1 (642, 641), global light emission clock red 0 / 1 (652, 651), and global light emission clock blue / green 0 / 1 (662, 661). The backbone may further include one or more backup hybrid pixel driver chips 700A, 700B. In one embodiment, a global hybrid driver configuration update 610 is input to the backup hybrid pixel driver chip 700A, with a global data clock 620 input to the backup hybrid pixel driver chip 700B. Additional global signals 630, 640, 650, 660 may be input to both backup hybrid pixel driver chips 700A, 700B.

[0043] As shown in FIG. 7 , the backup hybrid pixel driver chips 700A, 700B output driven backup signal lines 711, 712, 721, 722 to the partitioned rows 404 and the rows of the hybrid pixel driver chip. The driven backup signal lines 711, 712, 721, 722 may be connected to the inputs of the backbone hybrid pixel driver chips configured for configuration update, data clock, frame sync, and row sync functions. During operation, the backup hybrid pixel driver chips 700A, 700B use tokens to initialize their multiplexer outputs (e.g., modified signals). Backup input pins are added to the backbone hybrid pixel driver chips configured for row functions (configuration update, data clock, frame sync, row sync) to recognize if either of the backup hybrid pixel driver chips 700A, 700B is active and provide modified row function signals to the rows. In the illustrated embodiment, the manipulated backup signal lines 711, 712, 721, 722 are not input to the hybrid pixel driver chips configured for the light emitting clock function. According to an embodiment, the backup hybrid pixel driver chips 700A, 700B can be programmed to either be LED driving pixel driver chips or to perform the function of a defective backbone hybrid pixel driver chip in the same backbone row.

[0044] 8 is a routing diagram of emission frame sync and emission row sync buffering within a row of a pixel driver chip, according to one embodiment. As shown, in addition to being optionally partitioned as described above, global emission row sync 630 and global emission frame sync 640 may be separated into multiple phases. While five phases Φ0-Φ4 are shown, this is exemplary and the embodiment is not limited to a particular number of phases. In the particular embodiment shown, every fifth row shares the same phase.

[0045] FIG. 9 is a routing diagram of vertical signal redundancy and lighting clock vertical and horizontal buffering according to one embodiment. As shown, the global lighting clocks 650, 660 may be separated into multiple phases similar to the global lighting row sync 630 and global lighting frame sync 640, in addition to being optionally partitioned as described above. The exemplary embodiment shown in FIG. 9 provides row partitioning with main / spare functionality. For example, odd partitions (e.g., 1) may function as spares, and even partitions (e.g., 0) may function as mains. In this manner, the backbone hybrid pixel driver chip 110B functionality can be determined by which odd / even chips in a row have a token. This can be determined by the VST inputs, VST_0 612 (main) and VST_1 611 (spare). As explained in more detail below, the global lighting clocks 650, 660 are replicated by the backbone hybrid pixel driver chips.

[0046] Referring now to FIG. 10 , a routing diagram of the backbone routing of global signal lines to rows of backbone hybrid pixel driver chips and row signal lines is provided, according to one embodiment. The exemplary layout provided in FIG. 10 combines several features according to embodiments. As shown, separate phases (Φ, Φ) of the global light emission row sync 630 and global light emission frame sync 640 signals are sent to different rows (N-1, N). In addition, separate phases (Φ, Φ) of the global light emission clock red 650 and global light emission clock blue-green 660 signals are sent to different rows (N-1, N). As shown, repeating light emission clock red and light emission clock blue / green signal lines 650R, 660R are output from the corresponding backbone hybrid pixel driver chip to the next row (e.g., every fifth row). It should be noted that the specific connections for the global signal lines 630, 640, 650, 660 differ from the examples described above, but any configuration is possible using combinations of embodiments. Specifically, the corresponding backbone hybrid pixel driver chips connected to the global signal lines 630, 640, 650, 660 are partitioned into pairs of either odd or even sections, rather than into single chips in either odd and even sections.

[0047] 10 , the Global Hybrid Driver Configuration Update 0 / 1 (614, 613) and Global Data Clock 0 / 1 (622, 621) signal lines are input to a corresponding pair of backbone hybrid pixel driver chips. Similarly, the VST_0 612 and VST_1 611 signal lines are input to each of the backbone hybrid pixel driver chips coupled to the Global Hybrid Driver Configuration Update 0 / 1 (614, 613) inputs and the backbone hybrid pixel driver chips coupled to the Global Data Clock 0 / 1 (622, 621) signal lines. The VST Output 617 signal line is output to both of the backbone hybrid pixel driver chips coupled to the Global Data Clock 0 / 1 (622, 621) signal lines in the next row (N). The VST Output 617 signal line also repeats the signal line that together repeats the VST_0 612 and VST_1 611 signal lines for the next row.

[0048] In the particular configuration shown in FIG. 10 , the data clock and hybrid pixel driver configuration update are generated separately for partitions 0 / 1 of each row. In this particular illustration, partitions 0 / 1 correspond to right / left, as opposed to bottom / top (even / odd). In other embodiments, partitions 0 / 1 correspond to bottom / top (even / odd), as previously described. Each hybrid pixel driver chip row buffers the emissive clock red, emissive clock blue / green, emissive frame sync, and emissive row sync for its associated clock phase. However, embodiments are not limited to this particular configuration, and each of the global signal lines may be generated separately for each row partition 0 / 1.

[0049] Figure 11 is a routing diagram of horizontal control signal redundancy for VST and backup line connections, according to one embodiment. Included in Figure 11 among selected global signal lines are VST scan clock 682 and VST row capture clock 681, emitting clock red_1 651 (spare), and emitting clock green / blue_1 661 (spare). Thus, in this situation, row partition 0 / 1 for the emitting clock signal lines corresponds to main / spare. As shown, VST scan clock 682, VST row capture clock 681, and VST_0 612 and VST_1 611 are input to the backbone hybrid pixel driver chip, which generates the steered hybrid driver configuration update 610M, steered data clock 620M, steered emitting clock red 651M (or 650M in general), and steered emitting clock blue-green 661M (or 660M in general) signals, as well as into spare backbone hybrid pixel driver chips 700A, 700B. The luminance clock red_1 651 (spare) and luminance clock green / blue_1 661 (spare) are input to the backbone hybrid pixel driver chip, which generates the driven luminance clock red 651M (or generally 650M) and driven luminance clock blue-green 661M (or generally 660M) signals, and into the spare backbone hybrid pixel driver chips 700A, 700B.

[0050] In the particular embodiment shown, the spare backbone hybrid pixel driver chip 700A output is connected to backup indicator_0 618 and backup line_0 712 in row 404, while the spare backbone hybrid pixel driver chip 700B output is connected to backup indicator_1 619 and backup line_0 711 in row 404. The backup indicators (e.g., 618, 619) indicate that the backup lines (e.g., 712, 711) are enabled to provide backup functionality. Backup indicator 0 618 and backup line_0 712 are used together, and backup indicator 0 619 and backup line_0 711 are used together. In this way, the spare backbone hybrid pixel driver chip 700A, 700B can be programmed to back up a defective backbone hybrid pixel driver chip originally designed to buffer the global emission clock signal and send a manipulated emission clock signal (e.g., generally 651, 661 or 650, 660) to row 404 via backup line_0 712 or backup line_0 711.

[0051] 12 is a routing diagram of horizontal control signal redundancy for row function signal connections according to one embodiment. Row function partitioning (or chip partitioning) within a hybrid pixel driver chip backbone according to an embodiment involves receiving global signals at one or more backbone hybrid pixel driver chips 110B and transmitting driven signals from one or more backbone hybrid pixel driver chips 110B to one or more other backbone hybrid pixel driver chips and to associated groups of LED driving pixel driver chips 110D in a corresponding row.

[0052] Certain global signals may be received directly by multiple backbone hybrid pixel driver chips 110B, while manipulated signals are generated by multiple specific backbone hybrid pixel driver chips 110B, or alternatively, by spare backbone hybrid pixel driver chips 700A, 700B. In the embodiment shown in Figure 12, the global hybrid driver configuration update 610 and global data clock 620 signal lines are input to each backbone chip where the manipulated signals are generated, as well as to backbone chips programmed to modify the global lighting clock (e.g., 650, 660) and spare chips (e.g., 700A, 700B). Similarly, the global lighting row sync 630 and global lighting frame sync 640 signal lines are input to each backbone chip where the manipulated signals are generated, as well as to backbone chips programmed to modify the global lighting clock (e.g., 650, 660) and spare chips (e.g., 700A, 700B). Additionally, as described with respect to FIG. 11, the global lighting clock red 650 and global lighting clock blue-green 660 signal lines are input to the respective backbone chips where manipulated signals are generated, as well as to spare chips (e.g., 700A, 700B).

[0053] In one embodiment, the display panel includes a bus array 515 of global signal lines, multiple rows 404 of row function signal lines, and multiple rows [1, ..N] of pixel driver chips 110, where each row of pixel driver chips is connected to a corresponding row 404 of row function signal lines and each pixel driver chip is connected to a corresponding matrix 102 of light emitting diodes (LEDs) 104. Each row of pixel driver chips can include a group of backbone hybrid pixel driver chips 110B and a group of LED driving pixel driver chips 110D. The bus array 515 of global signal lines is coupled to the group of backbone hybrid pixel driver chips 110B in each row of pixel driver chips, and each separate backbone hybrid pixel driver chip includes an input connected to a corresponding global signal line and an output connected to a corresponding row function signal line in the corresponding row of row function signal lines (e.g., 1450M in FIG. 14 ) to send a corresponding driven signal to the corresponding row of pixel driver chips.

[0054] The following example implementations are directed to data clock and configuration update routing. In one embodiment, each group of backbone hybrid pixel driver chips 110B includes a data clock backbone hybrid pixel driver chip having an input coupled to a global data clock 620 signal line and an output coupled to a corresponding row function signal line to send a driven data clock 620M signal to the corresponding row of the pixel driver chip. Each group of backbone hybrid pixel driver chips may also include a configuration update backbone hybrid pixel driver chip having an input coupled to a global configuration update 610 signal line and an output coupled to a corresponding row function signal line to send a driven configuration update 610M signal to the corresponding row of the pixel driver chip. In one embodiment, the data clock backbone hybrid pixel driver chip includes an input coupled to the global configuration update 610 signal line, and the configuration update backbone hybrid pixel driver chip includes an input coupled to the global data clock 620 signal line.

[0055] The following example implementation is directed to VST routing and backup chips. In one embodiment, each group of backbone hybrid pixel driver chips includes a backup backbone hybrid pixel driver chip 700A, 700B, which includes an input coupled to the global configuration update 610 signal line and an input coupled to the global data clock 620 signal line. VST clock lines (e.g., VST scan clock 682, VST row capture clock 681) may be coupled to inputs of the data clock backbone hybrid pixel driver chip, the configuration update backbone hybrid pixel driver chip, and the backup backbone hybrid pixel driver chip. The backup backbone hybrid pixel driver chip may also include outputs coupled to corresponding row function signal lines to send driven row function signals to corresponding rows of the pixel driver chip, including the data clock backbone hybrid pixel driver chip and the configuration update backbone hybrid pixel driver chip.

[0056] The following example implementations cover alternative routings, such as for synchronization. In one embodiment, each group of backbone hybrid pixel driver chips includes a first backbone hybrid pixel driver chip having an input coupled to a first global signal line, a first output coupled to a corresponding first row function signal line to transmit a first manipulated signal to the corresponding row of the pixel driver chip, and a second backbone hybrid pixel driver chip having an input coupled to a second global signal line, and a second output coupled to a corresponding second row function signal line to transmit a second manipulated signal to the corresponding row of the pixel driver chip. In one embodiment, the second row function signal line is coupled to a third input of the first backbone hybrid pixel driver chip, and the first row function signal line is coupled to a fourth input of the second backbone hybrid pixel driver chip. For example, the first global signal line may be a global light-emitting row sync 630 line, and the second global signal line may be a global light-emitting frame sync 640 line.

[0057] The display panel can distribute the global row function signals among the backbone hybrid pixel driver chips, whereby each backbone hybrid pixel driver chip is responsible for manipulating and / or repeating a designated global row function signal. In one embodiment, each group of backbone hybrid pixel driver chips includes a data clock backbone hybrid pixel driver chip having inputs coupled to the global data clock 620 signal line and the global configuration update 610 signal line, a configuration update backbone hybrid pixel driver chip having inputs coupled to the global data clock 620 signal line and the global configuration update 610 signal line, a frame sync backbone hybrid pixel driver chip having inputs coupled to the global frame sync 630 signal line, a row sync backbone hybrid pixel driver chip having inputs coupled to the global row sync 640 signal line, and an emission clock backbone hybrid pixel driver chip having inputs coupled to the global emission clock (e.g., 650, 660) signal line. Each group of backbone hybrid pixel driver chips may further include one or more backup backbone hybrid pixel driver chips 700A, 700B coupled to the global data clock 620 signal line, the global configuration update 610 signal line, the global frame sync 630 signal line, the global row sync 640 signal line, and the global emission clock (e.g., 650, 660) signal line.

[0058] FIG. 13 is a routing diagram of global and row signal line connections to and from the backbone of a tile-based display panel, according to one embodiment. In particular, the routing diagram shows the (steered) output from the global signal line inputs and odd / even indexes of a group of backbone hybrid pixel driver chips 110B to the odd / even routing within row 404 of row signal lines and the repeat output for the next row. At a high level, FIG. 13 provides the inputs for the odd / even indexes of a row of backbone hybrid pixel driver chips. Thus, the annotation 110B indicates the entire backbone row of backbone hybrid pixel driver chip 110B. Together, FIG. 13 shows the high-level connections of the odd / even indexes of backbone hybrid pixel driver chip 110B to backbone row 1300. As shown, several global signals (which may be digital) are input to both odd and even groups of backbone hybrid pixel driver chips, including VST scan clock 682, VST row capture clock 681, emission frame sync 640, and emission row sync 630. Additional signal lines not previously described include designs for hybrid pixel driver chip reset 690, token reset 692, and test control 694 signal lines. The global data clock_1 621 and global configuration update_1 613 signal lines are input only to odd-index backbone hybrid pixel driver chips, while global data clock_0 622 and global configuration update_0 614 are input only to even-index backbone hybrid pixel driver chips.

[0059] Additionally, data signals are input to each odd / even group of backbone hybrid pixel driver chips that contain data 440 and configuration update 445 signal lines.

[0060] Additionally, there are several vertically repeating global signals (e.g., digital) that are input to both odd / even groups of backbone hybrid pixel driver chips, including VST_0(main) 612, VST_1(spare) 611, luminance clock red_0(main) 652, luminance clock red_1(spare) 651, luminance clock blue-green_0(main) 662, and luminance clock blue-green_1(spare) 661. Outputs from the odd / even indexes of backbone hybrid pixel driver chip 110B include repeat luminance clock blue-green 662R, repeat luminance clock red 652R, repeat luminance clock blue-green 661R, repeat luminance clock red 651R, and VST output 617.

[0061] In this embodiment, the outputs from the odd indexes of the backbone hybrid pixel driver chip 110B include: driven data clock_1 621M, driven configuration update_1 613M, driven light frame sync_1 641M, driven light row sync_1 631M, driven light clock red_1 651M, driven light clock blue-green_1 661M, backup line_1 711, and backup line_3 721.

[0062] In this embodiment, the outputs from the even index backbone hybrid pixel driver chip 110B include driven data clock_0 622M, driven configuration update_0 614M, driven light frame sync_0 642M, driven light row sync_0 632M, driven light clock red_0 652M, driven light clock blue-green_0 662M, backup line_0 712, and backup line_2 722.

[0063] 14 is a block circuit diagram of a backbone hybrid pixel driver chip according to one embodiment. In the illustrated embodiment, the backbone hybrid pixel driver chip includes a VST driver circuit 1410, a signal modulator circuit 1430, a multiplexer driver circuit 1440, and an LED driver circuit 1460.

[0064] The LED drive circuit 1460 portion provides lighting functionality for the hybrid pixel driver chip and stores pixel data and configuration data. The LED drive circuit 1460 portion includes a shift register 1462, a latch 1464, a memory 1466, and a lighting clock counter 1468. At least the data 440 signal and the internal data clock 620I are input to the shift register 1462, and at least the internal lighting clock red 650I and the internal lighting clock blue-green 660I are input to the lighting clock counter 1468 to output lighting pulses at the output driver 116. However, before lighting can occur, the hybrid pixel driver chip needs to be configured for row functionality.

[0065] The VST driver circuit 1410 determines whether the row is on or off and provides VST propagation from the top to the bottom of the display panel. The actual token hybrid pixel driver chip receives a global VST signal, while the other hybrid pixel driver chips receive VST signals from the backup hybrid pixel driver chip. As shown, the VST driver circuit 1410 includes inputs for the VST scan clock 682, the VST row capture clock 681, VST_0 612, and VST_1 611, and outputs for the token latch 1414 and token 1412 signals. The token latch 1414, token 1412, VST_0 612, and VST_1 611 signals are input to a signal modulator 1430.

[0066] Specifically, VST driver circuit 1410 includes an OR gate 1470 coupled to VST inputs 611, 612, and multiple flip-flop circuits 1480 coupled to VST clock inputs 681, 682 and an output 1771 from the OR gate, the multiple flip-flop circuits 1480 including a token 1412 output and a token latch 1414 output. In operation, OR gate 1470 outputs a high output 1771 signal if one or both of the inputs to the gate are high (1). If neither input is high, a low output (0) results. With respect to flip-flop circuit 1480, if the VST clock input (e.g., 681 or 682) is low, the output is low. When the VST clock input (e.g., 681 or 682) is high, the flip-flop circuit output is high (1) if the data input is high (1) and low (0) if the data output is low (0).

[0067] Specifically, the output of OR gate 1470 is coupled to the data inputs of flip-flop circuits 1480A and 1480C. One VST clock (e.g., VST scan clock 682) is coupled to the clock input of flip-flop circuit 1480A. Another VST clock (e.g., VST row capture clock 681) is coupled to the clock inputs of flip-flop circuits 1480C and 1480B. The data output from flip-flop circuit 1480A is coupled to the data input of flip-flop circuit 1480B, and the anode from the data output from flip-flop circuit 1480A is also coupled to multiplexer 1442 within multiplexer driver circuit 1440. Token 1412 is coupled to the data output of flip-flop circuit 1480C, and token latch 1414 is coupled to the data output of flip-flop circuit 1480B.

[0068] When the VST driver circuit 1410 outputs that a row is on, a signal modulator circuit 1430 selects whether to take the global row function signal or the backup line for one of the row functions. The token latch 1414 and token 1412 are out of phase and, in combination with VST_0 612 and VST_1 611, signal which of the backup lines 711, 712 should be used for one of the row function signals 610, 620, 630, 640, 650, 660. In addition, the signal modulator circuit 1430 modifies the global input signal for a steered signal specific to a particular row. A number of multiplexers 1432 output the internal (steered) row function signals from the signal modulator 1430 to the multiplexer driver 1440 and the LED drive circuit 1460. Included outputs may be an internal configuration update 610I, an internal data clock 620I, an internal light row sync 630I, an internal light frame sync 640I, an internal light clock red 650I, and an internal light clock blue-green 660I.

[0069] The multiplexer driver circuit 1440 includes two sections: a repeater section 1440A and a row function output section 1440B. The output from the VST driver circuit 1410 is input to a multiplexer 1442 in the repeater section 1440A, which is then buffered in a buffer 1444 to output the VST_OUTPUT 617. The internal lighting clock is also input to the multiplexer 1442, which can alternatively output a repeating lighting clock signal, such as a repeating lighting clock red 650R (651R, 652R) or a repeating lighting clock blue-green 660R (661R, 662R). The internal row function signal from signal modulator circuit 1430 is input to multiplexer 1446 of row function output section 1440B, which is then buffered in buffer 1448 to output a driven multiplexer output 1450M signal (which is a driven or repeated signal output to the programmed backbone hybrid pixel driver chip). Thus, driven multiplexer output 1450M may be a driven output signal or any of the backup signals described above, and may be physically connected to a designated row function line within row 404 depending on the signal. For example, with reference to the exemplary embodiment shown in FIG. 13, driven multiplexer output 1450M may be connected to any of (621M, 613M, 641M, 631M, 651M, 661M, 711, 721, 622M, 614M, 642M, 632M, 652M, 662M, 712, 722), although other configurations are possible.

[0070] According to an embodiment, for non-backbone hybrid pixel driver chips, VST input terminals 611 and 612 are still connected to a backup indicator signal to select the backup signal as one of the row functions. The scan clock 681 and row capture clock 682 inputs may be tied to ground to indicate that they are not backbone hybrid drivers, while VST output 617 and multiplexer output 1450M may be floating. Thus, the circuitry may remain the same for backbone hybrid pixel driver chip 110B and drive hybrid pixel driver chip 110A; only the programming and external connections are different.

[0071] In one embodiment, the hybrid pixel driver chip includes vertical select token (VST) inputs (e.g., 611, 612), VST clock inputs (e.g., 681, 682), and a VST driver circuit 1410 coupled to the VST inputs and the VST clock input, the VST driver circuit further including a token 1412 output and a token latch 1414 output. The hybrid pixel driver chip further includes a signal modulator circuit 1430 coupled to the token 1412 output and the token latch 1414 output, the signal modulator circuit 1430 further including a plurality of multiplexers 1432 coupled to a plurality of global signal inputs and a plurality of internal signal outputs from the plurality of multiplexers 1432. The signal modulator circuit 1430 may also be coupled to the VST inputs (e.g., 611, 612). Additional components of the hybrid pixel driver chip may include a multiplexer driver circuit 1440 including a multiplexer 1446 coupled to a plurality of internal signal outputs and a multiplexer output 1450M, and an LED drive circuit 1460 coupled to the data 440 input and to one or more of the plurality of internal signal outputs, the LED drive circuit 1460 further including a plurality of output drivers 116.

[0072] In one embodiment, the multiplexer driver circuit 1440 includes a repeater section 1440A coupled to the VST driver 1410 and a row function output section 1440B coupled to the signal modulator 1430.

[0073] In one embodiment, the VST driver circuit 1410 includes an OR gate 1470 coupled to a VST input (e.g., 611, 612), and multiple flip-flop circuits (1480A, 1480B, 1480C) coupled to a VST clock input (e.g., 681 or 682) and an output 1471 from the OR gate 1470, the multiple flip-flop circuits including a token 1412 output and a token latch 1414 output.

[0074] Figure 15 is a timing diagram of data loading for a token-activated hybrid pixel driver chip, according to one embodiment. As such, the timing diagram of the embodiment of Figure 15 is directed to a particular backbone hybrid pixel driver chip wired to a VST routing backbone (e.g., as shown in Figure 11). Specifically, the timing diagram of Figure 15 is directed to the two leftmost backbone hybrid pixel driver chips shown in Figure 11, which have global / repeated VST connections.

[0075] 15 illustrates a specific aspect of an embodiment in which a particular backbone hybrid pixel driver chip is programmed in two parts. First, the particular backbone hybrid pixel driver chip is configured. The particular backbone hybrid pixel driver chip then communicates the corresponding multiplexer output 1450M signal, specifically the manipulated configuration update 610M and manipulated data clock 620 signals, to the other pixel driver chips connected to the corresponding row 404. Once the row is configured, other data bits can be defined. Thus, the method for programming a backbone hybrid pixel driver chip in one embodiment involves the general sequence of activating a token, once which programs the data clock and configuration update high, the row becomes available (sending manipulated data clock and manipulated configuration update to the remaining rows), and then the remaining configuration bits are written.

[0076] Three separate portions of data 440 bits are shown in FIG. 15. Token driver configuration 1510 data includes data for optional selection of backup lines 711 / 712 in signal modulator 1430 and data for steering the global data clock 620 and global configuration update 610 signals. This token driver configuration 1510 data is used only by token-activated backbone hybrid pixel driver chips that are hardwired to the VST signal lines. Row driver configuration 1520 data includes data for selecting other row function signals in signal modulator 1430 and LED configuration within a row. This row driver configuration 1520 data is used by all backbone hybrid pixel driver chips to send the driven row function signals to the corresponding row 404. LED pixel data 1530 includes data for LED pixel data slice 0 / 1 of the hybrid pixel driver chips in the corresponding row.

[0077] As shown in Figure 15, initially, the Token Reset 692 signal goes high to reset the backbone hybrid pixel driver chip. Also, the VST row capture clock 681 goes high (leading edge), and the VST driver 1410 generates a high Token 1412 signal. At this point, the backbone hybrid pixel driver chip for row 0 is token activated and ready for configuration and data loading. However, before loading LED pixel data, the hybrid pixel driver is first configured. When the VST is active for a particular row, it tends to high (Token). Token tracks the global VST clocks (VST scan clock 682, VST row capture clock 681). In this embodiment, the VST scan clock 682 and VST row capture clock 681 are the same frequency.

[0078] As described, configuration is performed in two parts. First, token driver configuration 1510 data is loaded to configure the specific hard-wired backbone hybrid pixel driver chip for multiplexer selection of backup lines 0 / 1 712, 711 and for generating the steered data clock 620M and steered configuration update 610M signals. The backup line configuration is included because it can be used for either the steered data clock 620M or the steered configuration update 610M signals. The initial configuration is important because the steered data clock 620M and steered configuration update 610M signals are needed to identify configuration bits or data bits. Second, row driver configuration 1520 is loaded to select multiplexers for other row function signals at multiplexer output 1450M. The specific timing diagram in Figure 15 is for the two leftmost backbone hybrid pixel driver chips shown in Figure 11 with global / repeated VST connections. Thus, the multiplexer output 1450M signal line corresponds to the manipulated data clock 620M and manipulated configuration update 610M signals.

[0079] As shown, pulses of the Global Configuration Update 610 signal are applied and received by the hardwired backbone hybrid pixel driver chip. Corresponding Internal Data Clock 620I and Internal Configuration Update 610I signals are generated during application of the Global Configuration Update 610 signal, and the steered signals (the Steering Data Clock 620M signal and the Steering Configuration Update 610M signal) are sent to the rows by the Multiplexer Output 1450M signal line.

[0080] The Global Configuration Update 610 signal is then deasserted (falling edge), causing the Configure Done 699 signal to go high. Also as shown, a subsequent falling edge of the Global Configuration 610 signal causes the Configure Done 699 signal to go low. The Configure Done 699 signal is an internal signal that allows the hybrid pixel driver chip to distinguish pixel data from configuration data, thus writing LED pixel data 1530 to memory 1466. During row 1 time, the configuration bits from the Global Data Clock 620 are used for the new row (row 1) driver, so the Configure Done 699 signal inhibits configuring the driver with data 1510. The pixel bits during row 0 and row 1 time are shared by both drivers for the two rows. Memory 1466 is written with the first few token driver configuration 1510 data bits, then general row driver configuration 1520 data, then pixel data 1530 followed by another set of pixel data during row 1 time.

[0081] Figure 16 is a flowchart of a method for programming a display tile from reset, according to one embodiment. For clarity, the description of the method of Figure 16 will be made with reference to features found in Figures 15, 14, and 11. In general, the programming sequence runs through the backbone of the display tile starting at row i=0 and ending at row i=N, where 0 is the first (top) row and N is the last (bottom) row of the backbone hybrid pixel driver chip 110B.

[0082] The sequence may start at row i=0, where the hybrid driver reset 690 and token reset 692 signals are initially low. At operation 1610, the hybrid driver reset 690 and token reset 692 signals are asserted high and released low. At operation 1620, the VST signal is asserted high at row i=0. In operation 1630, the token driver configuration 1510 data is received by the token-activated backbone hybrid pixel driver chip. Specifically, the token driver configuration 1510 data is received by the backbone hybrid pixel driver chip with a high Token 1412 signal. This occurs during a high Token Reset 692 signal. This may be due to the overlap of the VST row capture clock 681 propagating to the data 440 lines. The VST row capture clock 681 is used to propagate the token signal row by row. When token 1412 is high, the hybrid pixel driver chip is open to receive data from the data 440 lines. Also, a reset signal is generated at the start of the token 1412 signal to reset the existing token state in the activated hybrid pixel driver chip. In operation 1640, the global configuration update 610 pulse and row driver configuration 1520 data are received by the backbone hybrid pixel driver chip, which then generates and sends a manipulated configuration update 610M signal to the row of pixel driver chips 110. In operation 1650, the global configuration update 610 pulse is deasserted and pixel data 1530 is sent to all pixel driver chips 110 in the row via the column of data 440 lines. In operation 1660, If is not equal to the number of rows N, the process is repeated for the next row, and if this is the last row, the process is complete.

[0083] In one embodiment, a method for programming a display includes propagating a VST signal (e.g., any of 611, 612, 681, 682) to a row of a pixel driver chip 110, receiving token driver configuration data 1510 at the backbone hybrid pixel driver chip 110B, receiving a global configuration update 610 pulse at the backbone hybrid pixel driver chip 110B, receiving row driver configuration data 1520 at the token-activated backbone hybrid pixel driver chip 110B, and sending a manipulated configuration update signal 610M from the backbone hybrid pixel driver chip 110B to a row (e.g., 1 ..N) of the pixel driver chip 110.

[0084] In one embodiment, the repeating VST signal 617 (eg, 611, 612) is propagated from the backbone hybrid pixel driver chip to a second backbone hybrid pixel driver chip in the second row of pixel driver chips.

[0085] In one embodiment, the method further includes asserting a token reset 692 signal and a VST clock (e.g., 681 or 682) signal to the backbone hybrid pixel driver chip 110B to token activate the backbone hybrid pixel driver chip before propagating the VST signals to the rows of the pixel driver chip.

[0086] It will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible when utilizing various aspects of the embodiments to form tile-based displays with backbone hybrid pixel driver chips. Although the embodiments have been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described above. Instead, the specific features and acts disclosed should be understood as embodiments of the claims for illustrative purposes.

Claims

1. A display panel, A display substrate, an array of LED driving pixel driver chips; an array of backbone hybrid pixel driver chips coupled to a plurality of global emission clock lines; a display substrate including: each backbone hybrid pixel driver chip is connected by a row function signal line to a corresponding row of LED driving pixel driver chips in the array of LED driving pixel driver chips; each LED driving pixel driver chip and each backbone hybrid pixel driver chip is connected to a corresponding matrix of light emitting diodes (LEDs) to drive the corresponding matrix of LEDs; a display panel, wherein each backbone hybrid pixel driver chip includes an output coupled to a row function signal line connected to a corresponding row of the LED drive pixel driver chips, the row function signal line transmitting a manipulated light emission clock signal formed based on a corresponding global light emission clock signal transmitted along a corresponding global light emission clock line.

2. 10. The display panel of claim 1, wherein each LED driving pixel driver chip has the same internal circuitry as each backbone hybrid pixel driver chip.

3. 3. The display panel of claim 2, further comprising a bus row of global signal lines coupled to the row of backbone hybrid pixel driver chips, the bus row of global signal lines including the plurality of global emission clock lines.

4. 4. The display panel of claim 3, wherein the bus row of global signal lines coupled to the row of backbone hybrid pixel driver chips further includes the plurality of global emission clock lines transmitting corresponding global emission clock signals.

5. 5. The display panel of claim 4, wherein each backbone hybrid pixel driver chip includes a plurality of outputs coupled to a plurality of row function signal lines connected to corresponding rows of the LED drive pixel driver chips, the plurality of row function signal lines transmitting manipulated emission clock signals formed based on corresponding global emission clock signals transmitted along corresponding global emission clock lines.

6. 6. The display panel of claim 5, wherein the plurality of row function signal lines includes a plurality of driven light-emitting clock signal lines, each driven light-emitting clock signal line transmitting a driven light-emitting clock signal formed based on a corresponding global light-emitting clock signal transmitted along a corresponding global light-emitting clock line.

7. The display panel of claim 1 further comprising a cutout portion extending through the display substrate.

8. 8. The display panel of claim 7, further comprising a bus row of global signal lines coupled to the row of backbone hybrid pixel driver chips, the bus row of global signal lines including the plurality of global emission clock lines.

9. 9. The display panel of claim 8, wherein each backbone hybrid pixel driver chip includes an output coupled to the row function signal line connected to a corresponding row of the LED drive pixel driver chips, the row function signal line transmitting a manipulated light emission clock signal formed based on a corresponding global light emission clock signal transmitted along a corresponding global light emission clock line.

10. a first row function signal line above the cutout; a second row function signal line below the cutout; 10. The display panel of claim 9, comprising:

11. 10. The display panel of claim 9, wherein each matrix of LEDs is a passive matrix.

12. 12. The display panel of claim 11, wherein each LED is a micro-LED having a maximum dimension of less than 100 μm.

13. 12. The display panel of claim 11, wherein each LED is a micro-LED having a maximum dimension of less than 10 μm.

14. 10. The display panel of claim 9, wherein the bus row of global signal lines coupled to the row of backbone hybrid pixel driver chips includes the plurality of global emission clock lines transmitting corresponding global emission clock signals.

15. 15. The display panel of claim 14, wherein the bus column of global signal lines coupled to columns of the backbone hybrid pixel driver chips includes a global emission row sync line that transmits a global row sync signal.

16. 15. The display panel of claim 14, wherein the bus columns of global signal lines coupled to columns of the backbone hybrid pixel driver chips include vertical select token (VST) lines.

17. 15. The display panel of claim 14, wherein each backbone hybrid pixel driver chip includes a plurality of outputs coupled to a plurality of row function signal lines connected to corresponding rows of the LED drive pixel driver chips, the plurality of row function signal lines transmitting manipulated emission clock signals formed based on corresponding global emission clock signals transmitted along corresponding global emission clock lines.

18. 18. The display panel of claim 17, wherein the plurality of row function signal lines include a driven light emitting clock signal line that transmits the driven light emitting clock signal formed based on a corresponding global light emitting clock signal transmitted along a corresponding global light emitting clock line.

19. 18. The display panel of claim 17, wherein the plurality of row function signal lines includes a plurality of driven light-emitting clock signal lines, each driven light-emitting clock signal line transmitting a driven light-emitting clock signal formed based on a corresponding global light-emitting clock signal transmitted along a corresponding global light-emitting clock line.

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