Optical Buffer

Abstract

To improve losses, dispersion and noise in an optical buffer for buffering an optical packet.SOLUTION: In an optical packet switch, an optical buffer 220 includes a clock generator 221 for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) 245, a fiber delay line (FDL) 247 having an FDL length, and a schedular. The clock generator, the MZI and the FDL are arranged in a circuit. An optical packet has an optical packet signal. The schedular inserts the optical packet into the optical buffer, and determines a number of circulations of the optical packet passing through the circuit. The MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet passing through the circuit. The FDL introduces, in the optical packet, a delay proportional to the FDL length.SELECTED DRAWING: Figure 2B

Description

Detailed Description of the Invention

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 167,082, filed March 28, 2021, which is incorporated herein by reference in its entirety.

[0002] (Technical field) Various system embodiments disclosed herein relate generally to optical switches, and more particularly to optical switches having all-optical memory buffers.

[0003] (background) Data centers utilize optical communications, and more specifically, optical packet switches for routing optical signals between communication devices. During periods of high load, optical packets may be discarded or lost as a result of contention or collisions. To prevent packet loss, some optical switches may include buffers.

[0004] For example, as shown in FIG. 1 , an N×N optical packet switch 110 includes N input ports 112-1...112-N and N output ports 114-1...114-N. An input data signal 102 can provide optical data packets to the input port 112, and these optical data packets can be routed to one of the output ports 114 and output as output data signals 104-1...104-N. While the optical switch 110 includes N input ports 112 and N output ports 114, it should be understood that not all of the input ports 112 and output ports 114 are connected to other communication devices. The switch 110 typically includes a scheduler 115 for directing data packets within the switch 110. The switch 110 may also provide wavelength conversion of packets between the input ports 112 and the output ports 114.

[0005] Packets may be directed by the scheduler 115 to the buffer 116 to slow packet throughput to prevent packet discards or packet loss due to contention. The buffer 116 may include one or more fiber delay lines (FDLs) 118-1...118-N. The FDLs 118 may take the form of a coil of fiber optic cable, which may typically have a length of one kilometer or more. The travel time of packets through the FDLs 118 introduces the desired delay / buffering of the packets. As shown, the FDLs 118-1, 118-2, and 118-3 are progressively longer so that packets can be directed through longer FDLs 118 to further delay the packets. In some implementations, packets may cycle through the FDLs 118 several times. Additionally or alternatively, the buffer 116 may include an electro-optical (EO) buffer 120. The EO buffer 120 converts optical packets into electrical data packets, which can be buffered using electrical memory. Once the buffering period is complete, the electrical data packets are converted into optical packets for routing to the output port 114 .

[0006] These known buffer systems may suffer from several limitations. The FDL may introduce dispersion and signal loss, which increases when multiple cycles of the FDL are used. The use of amplifiers to overcome signal loss may result in increased noise. Furthermore, the FDL has a fixed length that can "hold" a packet for the time it takes to travel through the FDL, requiring multiple FDLs or multiple cycles through the FDL to satisfy the desired buffer duration. Electro-optic buffers may increase power consumption and introduce delays. Furthermore, these devices are complex, increasing the likelihood of component failure.

[0007] It would therefore be desirable to provide an optical switching system that features a buffering mechanism that does not introduce significant loss, dispersion, and noise.

[0008] (Summary) Embodiments disclosed herein relate to systems, apparatus, and methods that enable high-data-rate optical packet switches using all-optical packet buffering. The all-optical buffers disclosed herein can significantly improve buffering and flow control in optical switches used in high-performance computing, such as data center architectures including spine-leaf, torus, cross networks, etc. The all-optical buffers disclosed herein can improve packet throughput and routing flexibility, reduce latency, and reduce power consumption.

[0009] To provide an all-optical packet switch buffer, the system described herein can use a combination of an all-optical unbalanced Mach-Zehnder interferometer (MZI) acting as an optical logic AND gate, a fiber delay line, an SOA for loss compensation, and optical dispersion compensation. As further described below, this configuration allows multiple circulations of buffered packets through the buffer, with reshaping and regeneration of the packets at each circulation. Thus, the all-optical buffer disclosed herein can overcome the limitations of current buffer solutions for preventing packet drops, packet loss, and contention by enabling extensive packet buffering while overcoming loss and dispersion issues and avoiding the use of electro-optic buffers.

[0010] The buffer also beneficially provides wavelength conversion so that additional wavelength conversion components may not be required in the switch. Furthermore, dispersion management may be handled optically within the buffer to compensate for dispersion introduced by the FDL. The use of optical dispersion management can reduce the computational complexity of the solution. In some embodiments, the buffers described herein can utilize integrated WDM to simultaneously buffer multiple packets through a single FDL. In some embodiments, an all-optical packet switch can be provided using integrated circuits (ICs) on a shared semiconductor substrate to further reduce power and size requirements.

[0011] Consistent with certain disclosed embodiments, an optical switch includes a scheduler and a buffer for buffering an optical packet, the buffer including a clock generator for generating a clock signal, an optical unbalanced Mach-Zehnder interferometer (MZI) having an FDL length, and a fiber delay line (FDL), the optical packet having an optical packet signal, the scheduler configured to insert the optical packet signal into the buffer and determine a number of times the optical packet circulates through the circuit; The MZI modulates a clock signal based on the optical packet signal, circulates the optical packet through the circuit, and then generates a reshaped optical packet. The FDL introduces a delay in the optical packet that is proportional to the FDL length.

[0012] In some embodiments, the circuit further includes a semiconductor optical amplifier (SOA) for compensating for loss introduced in the FDL. In some embodiments, the circuit further includes an optical dispersion management (DM) module for compensating for dispersion introduced in the FDL.

[0013] In some embodiments, the clock generator includes a tunable laser and an electro-optic (EO) modulator configured to modulate a laser output of the tunable laser based on the clock signal. In some embodiments, the switch further includes a WDM multiplexer and a WDM demultiplexer for sharing the FDL among the multiple buffers.

[0014] In some embodiments, the FDL is one of a single-core fiber optic cable or a multi-core fiber optic cable. In some embodiments, the reshaped optical packet is a wavelength-converted optical packet. In some embodiments, the MZI includes a pair of MZI SOAs. In some embodiments, the MZI SOA is a quantum dot SOA.

[0015] In some embodiments, the buffer further includes an optical packet splitter for directing the optical packet through a pair of MZI SOAs, the optical packet splitter including the pair of MZI SOAs. The signal power is divided unequally between the SOAs. In some embodiments, a clock and an optical packet are fed in counter-propagating directions to each of a pair of MZI SOAs to induce cross-gain modulation (XGM) and cross-phase modulation (XPM) of the clock signal and the optical packet signal.

[0016] In some embodiments, the switch further includes an egress SOA at an outlet of the buffer, and the scheduler is further configured to activate the egress SOA to release the optical packet from the buffer. In some embodiments, the clock generator includes a tunable laser, and the scheduler is further configured to power down the egress SOA and the tunable laser after releasing the optical packet, thereby emptying the buffer. In some embodiments, the scheduler is further configured to time the activation of the egress SOA to coincide with a time period nT, where n is an integer and T is an optical packet circulation time through the buffer, such that the optical packet is released through the egress SOA from the beginning to the end of the buffered optical packet and release of a partial optical packet through the egress SOA is prevented.

[0017] In some embodiments, the released optical packets are wavelength-converted optical packets.

[0018] Consistent with certain disclosed embodiments, a method for optical buffering of an optical packet having an optical packet signal includes providing an optical switch including a scheduler and a buffer, wherein the buffer includes a clock generator for generating a clock signal, an optical unbalanced Mach-Zehnder interferometer (MZI), and a fiber delay line (FDL) having an FDL length, and is disposed in a circuit to provide the optical switch; configuring the scheduler to insert the optical packet into the buffer and determine the number of circulations of the optical packet through the circuit; modulating a clock signal based on the optical packet signal using the MZI to create a reshaped optical packet after each circulation of the optical packet through the circuit; and introducing a delay of the optical packet proportional to the FDL length using the FDL.

[0019] In some embodiments, the circuit further includes a semiconductor optical amplifier (SOA) for compensating for losses introduced in the FDL. In some embodiments, the circuit further includes an optical dispersion management (DM) module for compensating for dispersion introduced in the FDL. In some embodiments, the clock generator includes a tunable laser and an electro-optic (EO) modulator configured to modulate a laser output of the tunable laser based on the clock signal.

[0020] In some embodiments, the method further includes providing a WDM multiplexer and a WDM demultiplexer for sharing the FDL among the plurality of buffers. In some embodiments, the FDL is one of a single-core fiber optic cable or a multi-core fiber optic cable. In some embodiments, the reshaped optical packets are wavelength-converted optical packets.

[0021] In some embodiments, the MZI includes a pair of MZI SOAs. In some embodiments, the MZI SOAs are quantum dot SOAs. In some embodiments, the buffer further includes an optical packet splitter for directing the optical packet through the pair of MZI SOAs, the optical packet splitter dividing the signal power unequally between the pair of MZI SOAs.

[0022] In some embodiments, a clock and an optical packet are supplied in counter-propagating directions to each of a pair of MZI SOAs to induce cross-gain modulation (XGM) and cross-phase modulation (XPM) of the clock signal and the optical packet signal. In some embodiments, the optical switch includes an egress SOA at an egress of the buffer, and the scheduler is further configured to activate the egress SOA to release the optical packet from the buffer. In some embodiments, the clock generator includes a tunable laser, and the scheduler is further configured to power down the egress SOA and the tunable laser after releasing the optical packet, thereby emptying the buffer.

[0023] In some embodiments, the scheduler is further configured to time activation of the egress SOA such that activation of the egress SOA coincides with a time period nT, where n is an integer and T is an optical packet circulation time through the buffer, such that the optical packet is released through the egress SOA from the beginning of the optical packet to the end, preventing release of partial optical packets through the egress SOA. In some embodiments, the released optical packets are wavelength-converted optical packets.

[0024] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0025] BRIEF DESCRIPTION OF THE DRAWINGS Aspects, embodiments, and features disclosed herein will become apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which like reference numerals designate those components common to different embodiments or configurations: FIG. 1 shows a block diagram of an optical packet switch.

[0026] 2A-2B show block diagrams of optical packet switches according to some embodiments.

[0027] 2C-2D illustrate the operation of an optical packet switch according to some embodiments.

[0028] 3A-3C show block diagrams of optical packet switches according to some embodiments.

[0029] (Detailed explanation) SUMMARY OF THE INVENTION The embodiments disclosed herein relate to systems, apparatus, and methods that enable high data rate optical packet switching using all-optical packet buffering.

[0030] 2A-2B illustrate an all-optical packet switch according to some embodiments. As shown in FIG. 2A, an N×N optical packet switch 210 may include N input ports 212-1...212-N and N output ports 214-1...214-N. An input data signal 102 may provide optical data packets to the input port 212, and these optical data packets may be routed to one of the output ports 214 for output as an output data signal 104. The data signals 102, 104 are packet-based optical data signals. While the optical switch 210 includes N input ports 212 and N output ports 214, it should be understood that not all of the input ports 212 and output ports 214 are connected to other communication devices. The switch 110 includes a scheduler 216 for directing data packets within the switch 210.

[0031] Packets may be directed to buffer 220 by scheduler 216 to slow packet throughput to prevent packet discard or packet loss due to contention. Scheduler 216 is a computing device as defined herein. Scheduler 216 is in data communication with components of buffer 220, as further described below.

[0032] In some embodiments, the components of the optical packet switch 210 may be provided as an integrated circuit (IC) on a shared semiconductor substrate. It should be understood that other switch internal components other than the scheduler 216 and the buffer 220 may be required for the operation of the switch 210, but these are not shown in the figure to reduce the complexity of the diagram. The components of the buffer 220 are described in more detail with reference to FIG. 2B and may include a clock generator 221, an optical unbalanced Mach-Zehnder interferometer (MZI) 245, and an FDL 247 configured in a circuit configuration. The components 221, 245, and 247 of the buffer 220 described below are exemplary implementations, and other implementations may be contemplated. In some embodiments, the components of the buffer 220 may be formed on a common semiconductor as an IC.

[0033] In clock generator 221, a tunable continuous wave (CW) laser 222 is modulated by EO modulator 228 based on a signal from clock 226 to generate an optical clock signal (herein λ 2 CLOCK The CW laser 222 may provide a source laser signal (referred to herein as λ2) that can form a CW laser 222. The wavelength of the laser 222 may be selected by the scheduler 216 according to the output port wavelength required for switching purposes, as described further below. The period of the clock 226 may be substantially the same as the data rate of the signal 102. The driver 224 may supply power to the CW laser 222.

[0034] The optical clock signal from the clock generator 221 is, for example, a clock signal according to the method described in Singh, Pallavi, et al., "All-Optical Logic Gates: Designs, Classification, and Comparison." Advances The clock signal may be fed into an unbalanced Mach-Zehnder interferometer (MZI) 245, which acts as an optical logic AND gate, as described in Optical Technologies (2014). Within the MZI 245, the optical clock signal may be split by a splitter 230 into an upper branch 231 and a lower branch 233. The splitting ratio of the splitter 230 into the upper branch 231 and the lower branch 233 may be controlled by the scheduler 216 to optimize the functionality of the buffer 220. Non-limiting examples of splitting ratios include 50 / 50, 90 / 10, and 80 / 20. In some implementations, the clock generator 221 may be implemented using a tunable pulsed laser (not shown).

[0035] In MZI 245, the output of splitter 230 may be connected to circulators 232-1 and 232-2. Circulators 232-1 and 232-2 may be connected to semiconductor optical amplifiers (SOAs) 234-1 and 234-2, respectively. While the circulators are shown in FIGS. 2B-2D as having a clockwise or counterclockwise orientation, it should be understood that the orientation used is functional. SOAs 234-1 and 234-2 may be powered by drivers 236-1 and 236-2, respectively. In some embodiments, SOAs 234-1 and 234-2 may be quantum dot SOAs.

[0036] The input packets to be buffered (here, λ 1-S1 , referred to as , are provided from port 212, which can communicate with MZI 245 at combiner 238. Combiner 238 may be connected to splitter 240. The output of splitter 240 may be connected to circulators 242-1 and 242-2. The splitting ratio of splitter 240 may be controlled by scheduler 216 to optimize the functionality of buffer 220. Non-limiting examples of splitting ratios include 50 / 50, 90 / 10, and 80 / 20. Circulator 242 may include ports connected to SOA 234 and combiner 244. Combiner 244 can combine the signals from circulator 242.

[0037] The output of the MZI 245 in the combiner 244 may be connected to a splitter 246. The splitter 246 may be connected to an SOA 252 and an FDL 247. The SOA 252 may be connected to one of the output ports 214.

[0038] In some embodiments, the MZI 245 may be implemented using a co-propagating scheme including a tunable filter (not shown). In some embodiments, the MZI 245 may be replaced with an ultra-nonlinear interferometer (UNI) configuration (not shown). In some embodiments, the MZI 245 may be replaced with a Sagnac interferometer (SI) gate.

[0039] The length of the FDL 247 substantially determines the delay introduced by a single circulation of a packet through the FDL 247 in the buffer 220, and therefore determines the optical buffer memory size. As a non-limiting example, a 1 km FDL introduces a delay of approximately 5 μs. For a data rate of 100 Gbps, such delay translates into an approximate optical buffer memory size of 0.5 Mbits.

[0040] The output of the FDL 247 may be connected to the SOA 248. The output of the SOA 248 may be connected to an optical dispersion management (DM) module 250. The DM 250 may compensate for the dispersion management introduced by the FDL 247. In some embodiments, the DM 250 may include a chirped Bragg grating controlled by a temperature controller (not shown). The output of the DM 250 may be connected to the coupler 238.

[0041] In buffer 220, scheduler 216 may monitor and control all components and provide automatic adjustment of adjustable components such as laser 222, SOA 234-1, SOA 234-2, SOA 248, DM 250, drivers 224, 236, and SOA 252. Scheduler 216 may be configured to ensure synchronization of the clock signal and the optical packets to be buffered.

[0042] The signal path within buffer 220 is shown in Figures 2C and 2D. In use, as shown in Figure 2C, a second wavelength (here λ 2 CLOCK ) can be fed to MZI 245 at splitter 230. Splitter 230 splits the upper branch 231 into the original clock signal λ 2 CLOCK , and the lower branch 233 carries a phase-shifted clock signal (herein λ 2 CLOCK-PS A phase shift of π / 2 can be introduced into the clock signal λ so that it carries a phase shift (referred to as π / 2) or vice versa. 2 CLOCK and λ 2 CLOCK-PS may pass through circulators 232-1 and 232-2 and enter SOAs 234-1 and 234-2, respectively.

[0043] The input optical data packets at the first wavelength (also referred to herein as the data signal, λ 1-S1 ) may be provided at combiner 238 from port 212 to MZI 245. Scheduler 216 may schedule packets λ for a period of time determined by scheduler 216 until the buffered packets are released from buffer 220 to output port 214. 1-S1 to buffer 220. Because output port 214 may operate at a different wavelength than the input port, switch 210 may provide wavelength conversion as part of the buffering process. The wavelength selected by the scheduler for tunable laser 222 may be the wavelength of the destination output port 214.

[0044] Then, packet λ 1-S1 may be directed to both circulators 242-1 and 242-2 by splitter 240. In some embodiments, splitter 240 may split the signal strength unequally between the two branches, thereby unbalancing MZI 245. Non-limiting examples of splitting ratios include 90 / 10 and 80 / 20.

[0045] The circulator 242 is 1-S1 λ 2 CLOCK and λ 2 CLOCK-PS λ can be directed to the SOA 234 in the opposite direction to that of 2 CLOCK and λ 2 CLOCK-PS The data packet λ with the clock signal 1-S1 The interaction of these signals can result in cross-gain and cross-phase modulation (XGM, XPM) between the clock signal and the packet signal, resulting in the SOA 234-1 generating the modulated clock signal (herein λ 2-XGM The SOA234-2 uses a phase-shifted modulated clock signal (λ 2-XGM-PS Each XGM clock λ 2-XGM and λ 2-XGM-PS It should be understood that λ is essentially a partially reshaped wavelength converted data packet. Similarly, in the reverse propagation, the data packet is modulated via XGM and XPM, resulting in λ 1-XGM and λ 1-XGM-PS The counterpropagating modulated data packet λ 1-XGM and λ 1-XGM-PS may be directed by circulator 232 to terminator 235.

[0046] The modulated clock signal λ 2-XGM and λ 2-XGM-PS is referred to herein as λ 2-S1 The wavelength-converted output packets may be combined in combiner 244 to form a reshaped wavelength-converted output packet, referred to as λ. Combiner 244 applies a further phase shift of π / 2 to the complete phase shift of π to provide the necessary conjunction at the output of MZI 245 (combiner 244). 2-XGM-PS The reshaped wavelength-converted output packet λ of the combiner 244 can be introduced into 2-S1 may be directed by splitter 246 to SOA 252 and FDL 247. Scheduler 216 schedules output packet λ 2-S1 has completed the required buffering period, scheduler 216 powers on SOA 252, thereby scheduling packet λ to one of the connected output ports 214. 2-S1It should be appreciated that scheduler 216 may time the release (power-on) of SOA 252 so that it coincides with time period nT (where n is an integer and T is the packet circulation time through buffer 220), such that buffered packets are released through SOA 252 from the beginning to the end of the buffered packet, and release of partial packets through SOA 252 may be prevented. Once packets are released from buffer 220, laser 222 and SOA 248 may be powered off by scheduler 216 to "empty" buffer 220.

[0047] Packet λ 2-S1 The signal passes through the FDL 247 until the SOA 248. The SOA 248 can amplify the signal after the FDL 247 to compensate for the signal loss incurred at the FDL 247. The amplified signal can further pass through the DM 250 to compensate for the dispersion introduced by the FDL 247.

[0048] As shown in Figure 2D, here λ 2-S1-REGEN The output signal from DM 250, called λ, may be reintroduced into MZI 245 at combiner 238. Then, packet λ 2-S1-REGEN may be directed to both circulators 242-1 and 242-2 by splitter 240. In some embodiments, splitter 240 may split the signal strength unequally between the two branches, thereby unbalancing MZI 245. Non-limiting examples of splitting ratios include 90 / 10 and 80 / 20.

[0049] The circulator 242 is 2-S1-REGEN λ 2 CLOCK and λ 2 CLOCK-PS λ can be directed to the SOA 234 in the opposite direction to that of 2 CLOCK and λ 2 CLOCK-PS The data packet λ with the clock signal 2-S1-REGENThe interaction of the clock signal with the circulated packet signal may result in XGM and XPM of the clock signal, and the SOA 234-1 generates a modulated clock signal (herein referred to as λ 2-XGM The SOA234-2 receives a phase-shifted modulated clock signal (λ 2-XGM-PS Each XGM clock λ 2-XGM and λ 2-XGM-PS It should be understood that λ may essentially be a partially reshaped circular data packet. In the reverse propagation, the data packet is modulated via XGM and XPM, λ 2-XGM and λ 2-XGM-PS The counter-propagating modulated data packet λ 2-XGM and λ 2-XGM-PS may be directed by circulator 232 to terminator 235.

[0050] Thus, the packet reshaping and regeneration process may allow several circulations of a packet through the FDL 247, with the packet effectively being regenerated in each circulation.

[0051] As in the first cycle (Fig. 2C), the modulated clock signal λ 2-XGM and λ 2-XGM-PS are combined in combiner 244 and are referred to herein as λ 2-S1 Combiner 244 applies a further phase shift of π / 2 to λ for the complete phase shift of π to provide the necessary conjunction at the output of MZI 245 (combiner 244). 2-XGM-PS The reshaped output packet λ of the combiner 244 can be introduced into 2-S1 may be directed by splitter 246 to SOA 252 and FDL 247. Scheduler 216 schedules output packet λ 2-S1 has completed the required buffering period, scheduler 216 powers on SOA 252, thereby scheduling packet λ to one of output ports 214, as described above. 2-S1 can be "released".

[0052] As determined by scheduler 216, packet λ 2-S1 λ may traverse the FDL 247 for a second circulation to the SOA 248. The SOA 248 may amplify the signal after the FDL 247 to compensate for the signal loss incurred at the FDL 247. The amplified signal may further pass through a DM 250 to compensate for the dispersion introduced by the FDL 247. 2-S1-REGEN The output signal from DM 250, referred to as , may be reintroduced at combiner 238 into MZI 245 for regeneration and emission (via SOA 252) or further circulation.

[0053] 3A-3C illustrate an all-optical packet switch according to some embodiments. As shown in FIG. 3A, the N×N optical packet switch 310 is the same as the packet switch 210 described above, but may further include multiple all-optical buffers 220-1, 220-2...220-M and a shared FDL 347. In some embodiments, the shared FDL 347 may use a single-core optical fiber cable. In some embodiments, the shared FDL 347 may utilize a multi-core optical fiber cable. In some embodiments, up to 64 wavelengths may be transmitted to the optical fiber cores in the shared FDL 347.

[0054] 3B and 3C, the shared FDL 347 may be shared by multiple optical buffers 220 using wavelength division multiplexing (WDM). A WDM multiplexer (mux) 312 may receive a signal from splitter 246-1 of buffer 220-1 and combine the received signal with signals received from splitters 246 of other buffers 220 for transmission via the shared FDL 347.

[0055] Following transmission via the shared FDL 347 , a WDM demultiplexer (demux) 314 may split the multiplexed signal for transmission to each of the SOAs 248 in the buffer 220 .

[0056] In the claims or specification of this application, unless otherwise specified, adjectives such as "substantially" and "about" modifying the state or relationship of a feature or characteristic of an embodiment of the invention are understood to mean that the state or characteristic is defined within a tolerance allowed for the operation of the embodiment for its intended use.

[0057] Implementation of the disclosed method and system may involve performing or completing certain selected tasks or steps manually, automatically, or a combination thereof. Furthermore, depending on the actual instrumentation and implementation of preferred embodiments of the disclosed method and system, some selected steps may be implemented by hardware (HW) or by software (SW) on any operating system of any firmware, or a combination thereof. For example, as hardware, selected steps of the disclosed method and system may be implemented as a chip or circuit. As software or an algorithm, selected steps of the disclosed method and system may be implemented as multiple software instructions executed by a computer using any suitable operating system. In either case, selected steps of the disclosed method and system may be described as being performed by a data processor, such as a computing platform, for executing multiple instructions.

[0058] Although this disclosure is described in terms of computing devices, or computers, any device featuring a data processor and the ability to execute one or more instructions may be any type of personal computer (PC), server, distributed server, master control unit, virtual server, cloud computing platform, cellular phone, IP phone, smartphone, smart phone, or any two or more such devices communicating with each other may, optionally, form a "network" or "computer network."

[0059] It is to be understood that when a claim or the specification refers to "a" or "an" element, such reference should not be construed as referring to only one of that element. In the description and claims of this application, the verbs "comprise," "comprise," and "have," respectively, and their conjugations, are used to indicate that the object or objects of the verb are not necessarily an exhaustive list of parts, elements, or portions of the subject or subjects of the verb.

[0060] While the present disclosure describes a limited number of embodiments, it will be understood that many variations, modifications, and other applications of such embodiments may be made. The present disclosure should not be understood to be limited by the specific embodiments described herein, but rather only by the scope of the appended claims. Different Aspects of the Disclosure [Item 1] A scheduler and A buffer for buffering optical packets, comprising: a clock generator for generating a clock signal; and the buffer including an optical unbalanced Mach-Zehnder interferometer (MZI) and a fiber delay line (FDL) having an FDL length, disposed in circuit; the optical packet comprises an optical packet signal; the scheduler is configured to insert the optical packet into the buffer and determine a number of circulations of the optical packet through the circuit; the MZI modulating a clock signal based on the optical packet signal to generate a reshaped optical packet after each circulation of the optical packet through the circuit; the FDL introduces a delay to the optical packet that is proportional to the FDL length; The MZI is an optical switch configured such that the clock signal and the optical packet signal are supplied to the MZI in a counter-propagating direction to induce transverse gain modulation (XGM) and transverse phase modulation (XPM) of the clock signal and the optical packet signal. [Item 2] The switch of claim 1 , wherein the circuit further comprises a circuit semiconductor optical amplifier (SOA) for compensating for losses introduced in the FDL. [Item 3] The switch of claim 1 , wherein the circuit further comprises an optical dispersion management (DM) module for compensating for dispersion introduced in the FDL. [Item 4] 10. The switch of claim 1, wherein the clock generator includes a tunable laser and an electro-optic (EO) modulator configured to modulate a laser output of the tunable laser based on the clock signal. [Item 5] The switch of claim 1 further comprising a WDM multiplexer and a WDM demultiplexer for sharing the FDL among multiple buffers. [Item 6] 10. The switch of claim 1, wherein the FDL is one of a single-core fiber optic cable or a multi-core fiber optic cable. [Item 7] The switch of claim 1 , wherein the reshaped optical packet is a wavelength-converted optical packet. [Item 8] The switch of claim 1 , wherein the MZI includes a pair of MZI SOAs. [Item 9] The switch of claim 8 , wherein the MZI SOA is a quantum dot SOA. [Item 10] the buffer further includes an optical packet splitter for directing the optical packet through the pair of MZI SOAs; The switch of claim 8 , wherein the optical packet splitter divides the signal power unequally between the pair of MZI SOAs. [Item 11] 9. The switch of claim 8, wherein the clock signal and the optical packet signal are supplied to each of the pair of MZI SOAs in counter-propagating directions to induce the XGM and the XPM. [Item 12] Further comprising an exit SOA at an exit of the buffer; The switch of claim 1 , wherein the scheduler is further configured to activate the egress SOA to release the optical packet from the buffer. [Item 13] the clock generator includes a tunable laser; The switch of claim 12 , wherein the scheduler is further configured to empty the buffer following the release of the optical packet by powering down the egress SOA and the tunable laser. [Item 14] the scheduler is further configured to time activation of the egress SOA to coincide with a time period nT, where n is an integer and T is an optical packet circulation time through the buffer; 13. The switch of claim 12, wherein the optical packets are released through the egress SOA from the beginning to the end of the buffered optical packets, and release of partial optical packets through the egress SOA is prevented. [Item 15] The switch of claim 12 , wherein the released optical packet is a wavelength-converted optical packet. [Item 16] 1. A method for optical buffering of optical packets comprising an optical packet signal, comprising: providing an optical switch including a scheduler and a buffer, the buffer including: a clock generator for generating a clock signal; an optical unbalanced Mach-Zehnder interferometer (MZI); and a fiber delay line (FDL) having an FDL length, disposed in circuit; configuring a scheduler to insert optical packets into the buffer and to determine the number of circulations of the optical packets through the circuit; providing the clock signal and the optical packet signal to the MZI in a counter-propagating direction to induce transverse gain modulation (XGM) and transverse phase modulation (XPM) of the clock signal and the optical packet signal, and modulating the clock signal based on the optical packet signal to generate a reshaped optical packet after each circulation of the optical packet through the circuit; and using the FDL to introduce a delay into the optical packets that is proportional to the length of the FDL. [Item 17] 17. The method of claim 16, wherein the circuit further comprises a circuit semiconductor optical amplifier (SOA) for compensating for losses introduced in the FDL. [Item 18] The method of claim 16 , wherein the circuit further comprises an optical dispersion management (DM) module for compensating for dispersion introduced in the FDL. [Item 19] 17. The method of claim 16, wherein the clock generator includes a tunable laser and an electro-optic (EO) modulator configured to modulate a laser output of the tunable laser based on the clock signal. [Item 20] 17. The method of claim 16, further comprising providing a WDM multiplexer and a WDM demultiplexer for sharing the FDL among multiple buffers. [Item 21] 17. The method of claim 16, wherein the FDL is one of a single-core fiber optic cable or a multi-core fiber optic cable. [Item 22] The method of claim 16 , wherein the reshaped optical packet is a wavelength-converted optical packet. [Item 23] The method of claim 16 , wherein the MZI comprises a pair of MZI SOAs. [Item 24] 24. The method of claim 23, wherein the MZI SOA is a quantum dot SOA. [Item 25] the buffer further includes an optical packet splitter for directing the optical packet through the pair of MZI SOAs; 24. The method of claim 23, wherein the optical packet splitter divides the signal power unequally between the pair of MZI SOAs. [Item 26] 24. The method of claim 23, wherein the clock signal and the optical packet signal are supplied to each of the pair of MZI SOAs in counter-propagating directions to induce the XGM and the XPM. [Item 27] the optical switch includes an egress SOA at an egress of the buffer; The method of claim 16 , wherein the scheduler is further configured to activate the egress SOA to release the optical packet from the buffer. [Item 28] the clock generator includes a tunable laser; 28. The method of claim 27, wherein the scheduler is further configured to empty the buffer by powering down the egress SOA and the tunable laser following the release of the optical packet. [Item 29] the scheduler is further configured to time the activation of the egress SOA to coincide with a time period nT, where n is an integer and T is an optical packet circulation time through the buffer; 28. The method of claim 27, wherein the optical packet is released through the egress SOA from the beginning of the optical packet to the end, and release of partial optical packets through the egress SOA is prevented. [Item 30] 28. The method of claim 27, wherein the released optical packets are wavelength-converted optical packets. [Brief explanation of the drawings]

[0061] [Figure 1] A block diagram of an optical packet switch is shown. [Figure 2A]FIG. 1 illustrates a block diagram of an optical packet switch according to some embodiments. [Figure 2B] FIG. 1 illustrates a block diagram of an optical packet switch according to some embodiments. [Figure 2C] 1 illustrates the operation of an optical packet switch according to some embodiments. [Figure 2D] 1 illustrates the operation of an optical packet switch according to some embodiments. [Figure 3A] FIG. 1 illustrates a block diagram of an optical packet switch according to some embodiments. [Figure 3B] FIG. 1 illustrates a block diagram of an optical packet switch according to some embodiments. [Figure 3C] FIG. 1 illustrates a block diagram of an optical packet switch according to some embodiments.

Claims

1. 1. An optical buffer for buffering optical packets, comprising: a clock generator for generating a clock signal; an optical unbalanced Mach-Zehnder interferometer (MZI); a fiber delay line (FDL) having an FDL length; a scheduler; the clock generator, the optical unbalanced Mach-Zehnder interferometer (MZI), and the FDL are arranged in a circuit; the optical packet comprises an optical packet signal; the scheduler is configured to insert the optical packet into the optical buffer and determine a number of circulations of the optical packet through the circuit; the MZI modulating a clock signal based on the optical packet signal to generate a reshaped optical packet after each circulation of the optical packet through the circuit; The FDL introduces a delay to the optical packet that is proportional to the FDL length.

2. The optical buffer of claim 1 , wherein the circuit further comprises a semiconductor optical amplifier (SOA) for compensating for losses introduced in the FDL.

3. The optical buffer of claim 1 , wherein the circuit further comprises an optical dispersion management module for compensating for dispersion introduced in the FDL.

4. 2. The optical buffer of claim 1, wherein the clock generator includes a tunable laser and an electro-optic modulator configured to modulate a laser output of the tunable laser based on the clock signal.

5. The optical buffer of claim 1 further comprising a WDM multiplexer and a WDM demultiplexer for sharing the FDL among multiple buffers.

6. The optical buffer of claim 1 , wherein the FDL is one of a single-core fiber optic cable or a multi-core fiber optic cable.

7. The optical buffer of claim 1 , wherein the reshaped optical packet is a wavelength-converted optical packet.

8. The optical buffer of claim 1 , wherein the MZI comprises a pair of MZI semiconductor optical amplifiers (SOAs).

9. The optical buffer of claim 8 , wherein the MZI SOA is a quantum dot SOA.

10. the optical buffer further includes an optical packet splitter for directing the optical packet through the pair of MZI SOAs; The optical buffer of claim 8 , wherein the optical packet splitter divides the signal power unequally between the pair of MZI SOAs.

11. 9. The optical buffer of claim 8, wherein the clock signal and the optical packet signal are supplied to each of the pair of MZI SOAs in counter-propagating directions to induce transverse gain modulation (XGM) and transverse phase modulation (XPM) of the clock signal and the optical packet signal.

12. further comprising an exit SOA at an exit of the optical buffer; The optical buffer of claim 1 , wherein the scheduler is further configured to activate the egress SOA to release the optical packet from the optical buffer.

13. the clock generator includes a tunable laser; The optical buffer of claim 12 , wherein the scheduler is further configured to empty the optical buffer following the release of the optical packet by powering down the egress SOA and the tunable laser.

14. the scheduler is further configured to time activation of the egress SOA to coincide with a time period nT, where n is an integer and T is an optical packet circulation time through the optical buffer; The optical buffer of claim 12 , wherein the optical packet is released through the egress SOA from the beginning to the end of the optical packet buffered by the optical buffer, and release of a partial optical packet through the egress SOA is prevented.

15. The optical buffer of claim 12 , wherein the released optical packets are wavelength-converted optical packets.

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