Gate driver and display device

Abstract

To reduce sensing time.SOLUTION: A gate driving unit according to an example and a display including the same are disclosed. The gate driving unit according to the example includes a number of signal transmission parts that are dependently connected via a carry line to which carrier signals are applied from the signal transmission parts before and output gate signals. The gate signal includes a scan signal for connecting a data line and a light emission control signal for connecting a pixel drive voltage line. The number of signal transmission parts apply the scan signals to pixel circuits via a predetermined data line in a section in which the electrical characteristics of the pixel circuits are sensed, thereby selecting a sensing area, and sequentially apply the voltage of the light emission control signals at a high voltage level for a predetermined number of pixel circuits in the sensing area, thereby selecting a block for performing sensing.SELECTED DRAWING: Figure 10a

Description

[Technical Field]

[0001] The present invention relates to a gate driver and a display device. [Background technology]

[0002] The display devices include a liquid crystal display (LCD), an electroluminescence display (ELD), a field emission display (FED), a plasma display panel (PDP), and the like.

[0003] Electroluminescent displays are divided into inorganic light-emitting displays and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays reproduce input images using self-emitting elements, such as organic light-emitting diodes (OLEDs). Organic light-emitting displays have the advantages of fast response speed, luminous efficiency, brightness, and a wide viewing angle.

[0004] Some display devices, such as liquid crystal display devices and organic light emitting display devices, include a display panel including a plurality of subpixels, a driver that outputs drive signals for driving the display panel, and a power supplier that generates power to be supplied to the display panel or the driver, etc. The driver includes a gate driver that supplies gate signals such as scan signals and light emission control signals to the display panel, and a data driver that supplies data signals to the display panel.

[0005] Such a display device can display an image by supplying driving signals, such as gate signals and data signals, to a plurality of sub-pixels formed on a display panel, causing the selected sub-pixels to transmit light or directly emit light. Summary of the Invention [Problem to be solved by the invention]

[0006] Each subpixel includes a driving TFT that controls the current flowing through the light-emitting element and one or more switching TFTs that switch the current. The driving TFTs can deteriorate over time due to prolonged operation, and a current-sensing-based compensation method is used to compensate for this deterioration. However, this current-sensing-based compensation method requires repeatedly sensing the amount of current after writing data to one block, and then sensing the amount of current after writing data to the next block, which results in a longer sensing time required to sense the entire block.

[0007] The present invention aims to solve the above-mentioned needs and / or problems, and provides a gate driver capable of shortening the sensing time and a display device including the same.

[0008] The objects of the present invention are not limited to those mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] The gate driver of the present invention includes a plurality of signal transmitters cascade-connected via carry lines to which carry signals are applied from the previous signal transmitters, and outputting gate signals, the gate signals including scan signals for connecting data lines and light emission control signals for connecting pixel driving voltage lines, the plurality of signal transmitters applying scan signals to pixel circuits via predetermined data lines during a period in which electrical characteristics of the pixel circuits are sensed to select a sensing area, and sequentially applying a voltage of a light emission control signal at a high voltage level to each of a predetermined number of pixel circuits in the sensing area to select a block for sensing. [Effects of the Invention]

[0010] In the present invention, when driving in sensing mode, a sensing area is selected in the column direction along the data line, and then light emission control signals are sequentially applied in block units within the sensing area to sense the current, thereby significantly shortening the sensing time or sensing tact time and improving consistency.

[0011] The present invention forms a current path that causes the current flowing through the power supply line to which the pixel drive voltage is applied to bypass the light emitting element, thereby suppressing the light emission of the light emitting element, thereby solving the visibility problem.

[0012] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram illustrating a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing a cross-sectional structure of the display panel shown in FIG. [Figure 3] 1 is a circuit diagram illustrating a pixel circuit coupled to an external compensation circuit of the present invention. [Figure 4] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 5] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 6a] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 6b] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 7] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 8] 1A and 1B are diagrams for explaining the operation principle of a sensing circuit according to an embodiment. [Figure 9a]FIG. 10 is a diagram for explaining and comparing the overall sensing time. [Figure 9b] FIG. 10 is a diagram for explaining and comparing the overall sensing time. [Figure 10a] 10A and 10B are diagrams showing various changes in the shape of blocks; [Figure 10b] 10A and 10B are diagrams showing various changes in the shape of blocks; [Figure 10c] 10A and 10B are diagrams showing various changes in the shape of blocks; [Figure 10d] 10A and 10B are diagrams showing various changes in the shape of blocks; [Figure 11a] FIG. 10 is a diagram for explaining the principle of selecting a sensing region. [Figure 11b] FIG. 10 is a diagram for explaining the principle of selecting a sensing region. [Figure 11c] FIG. 10 is a diagram for explaining the principle of selecting a sensing region. [Figure 11d] FIG. 10 is a diagram for explaining the principle of selecting a sensing region. [Figure 12] 2 is a diagram showing a shift register of a gate driver according to an embodiment of the present invention; [Figure 13] 10 is a diagram illustrating a signal transmission unit of a sensing driver according to an embodiment. [Figure 14] 1 is a diagram showing a signal transmission unit of an EM driver according to an embodiment. [Figure 15] 15 is a waveform diagram showing an output signal of the signal transmission unit shown in FIG. 14. DETAILED DESCRIPTION OF THE INVENTION

[0014] The advantages and features of the present invention, as well as methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be configured in various different forms. However, the present embodiments are provided so that the disclosure of the present invention will be complete and will fully convey the scope of the invention to those skilled in the art. The present invention is defined only by the scope of the claims.

[0015] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. Furthermore, in the description of the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0016] When the terms "comprise," "have," "consist of," etc. are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it also includes the plural unless otherwise expressly stated. In interpreting elements, it is understood that a margin of error is included even if there is no other explicit description.

[0017] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0018] In the description of the embodiments, terms such as "first," "second," etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of the present invention.

[0019] The same reference numerals refer to the same elements throughout the specification. Features of the various embodiments may be partially or fully combined or combined with each other, and various technical connections and operations may be possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship. Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the display panel shown in FIG.

[0021] Referring to Figures 1 and 2, a display device according to an embodiment of the present invention includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply unit 140 for generating power necessary to drive the pixels and the display panel driver.

[0022] The display panel 100 may have a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may include a power line to which a pixel driving voltage EVDD is applied, a power line to which an initialization voltage Vinit is applied, a power line to which a reference voltage Vref is applied, and a power line to which a low-potential power voltage EVSS is applied. These power lines are commonly connected to the pixels.

[0023] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes one line of pixels arranged along the line direction (X) in the pixel array of the display panel 100. The pixels arranged in one pixel line share a gate line 103. The sub-pixels arranged in the column direction (Y) along the data line direction share the same data line 102. One horizontal period (1H) is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0024] The display panel 100 may be a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on the screen and the actual object in the background can be seen.

[0025] The display panel can be made of a flexible display panel, which can be made of an OLED panel that uses a plastic substrate. The pixel array and light-emitting elements of the plastic OLED panel can be arranged on an organic thin film that is adhered to a back plate.

[0026] Each pixel 101 can be divided into red, green, and blue subpixels to achieve different colors. Each pixel can further include a white subpixel. Each subpixel includes a pixel circuit. Hereinafter, the term "pixel" can be interpreted as the same as "subpixel." Each pixel circuit is connected to a data line, a gate line, and a power supply line.

[0027] Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can achieve higher resolution than real color pixels by using a preset pixel rendering algorithm to drive two sub-pixels of different colors in one pixel 101. The pixel rendering algorithm can compensate for the insufficient color expression of each pixel with the color of light emitted by adjacent pixels.

[0028] A touch sensor may be disposed on the screen of the display panel 100. The touch sensor may be an on-cell type or an add-on type disposed on the screen of the display panel, or may be an in-cell type touch sensor built into the pixel array AA.

[0029] As shown in FIG. 2, the display panel 100 may include a circuit layer 12, a light emitting element layer 14, and an encapsulation layer 16 stacked on a substrate 10, when viewed from a cross-sectional view.

[0030] The circuit layer 12 may include pixel circuits connected to wiring such as data lines, gate lines, and power lines, and gate drivers GIPs connected to the gate lines. The wiring and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by insulating layers, and an active layer including a semiconductor material.

[0031] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered with a protective layer including an organic film and a protective film.

[0032] The encapsulation layer 16 covers the light emitting device layer 14 to seal the circuit layer 12 and the light emitting device layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which organic and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the path for moisture and oxygen to travel is longer than in a single layer, and the penetration of moisture and oxygen that affects the light emitting device layer 14 can be effectively blocked.

[0033] A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizer may be disposed on the touch sensor layer. The polarizer may convert the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12 to improve visibility and contrast ratio. The polarizer may be composed of a linear polarizer bonded to a phase delay film or a circular polarizer. A cover glass may be bonded on the polarizer.

[0034] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters and a black matrix pattern. The color filter layer absorbs some of the wavelengths of light reflected from the circuit layer and the touch sensor layer, replacing the polarizer and improving color purity. In this embodiment, a color filter layer 20 with higher light transmittance than a polarizer is applied to the display panel to improve the light transmittance of the display panel PNL and improve the thickness and flexibility of the display panel PNL. A cover glass may be bonded onto the color filter layer.

[0035] The power supply unit 140 uses a DC-DC converter to generate DC power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 adjusts the level of a DC input voltage applied from a host system (not shown) to generate constant voltages (or DC voltages), such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, a pixel driving voltage EVDD, a low-potential power supply voltage EVSS, a reference voltage Vref, an initialization voltage Vinit, and an anode voltage Vano. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driver 120. Constant voltages such as a pixel drive voltage EVDD, a low potential power supply voltage EVSS, a reference voltage Vref, an initialization voltage Vinit, and an anode voltage Vano are commonly supplied to the pixels.

[0036] The display panel driver writes pixel data of an input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0037] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0038] The demultiplexer array 112 uses a plurality of demultiplexers (DEMUX) to sequentially supply data voltages output from the channels of the data driver 110 to the data lines 102. The demultiplexer may include a number of switch elements disposed on the display panel 100. If the demultiplexer is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0039] The display panel driver may further include a touch sensor driver for driving the touch sensor. The touch sensor driver is omitted in the drawings. The data driver and the touch sensor driver may be integrated into a single drive IC (Integrated Circuit). In a mobile device or a wearable device, the timing controller 130, power supply 140, data driver 110, touch sensor driver, etc. may be integrated into a single drive IC.

[0040] The display panel driver can operate in a low-speed driving mode under the control of the timing controller 130. The low-speed driving mode can be set to reduce power consumption of the display device by analyzing an input image and determining that the input image remains unchanged for a predetermined period of time. The low-speed driving mode can reduce power consumption of the display panel driver and the display panel 100 by lowering the pixel refresh rate when a still image is input for a certain period of time or longer. The low-speed driving mode is not limited to when a still image is input. For example, when the display device operates in standby mode or when a user command or input image is not input to the display panel driver circuit for a certain period of time or longer, the display panel driver circuit can operate in the low-speed driving mode.

[0041] The data driver 110 uses a digital-to-analog converter (DAC) to convert pixel data of an input image, received as a digital signal from the timing controller 130, into gamma compensation voltages every frame period to generate data voltages. The gamma reference voltage VGMA is divided into gamma compensation voltages for each gray level through a voltage divider circuit and supplied to the DAC. The data voltages are output from each channel of the data driver 110 through an output buffer. The gate driver 120 may include a scan driver 121 and an EM driver 122. The gate driver 120 may be configured as a GIP (Gate in Panel) circuit directly formed on the circuit layer 12 of the display panel 100 together with the TFT array and wiring of the pixel array. The GIP circuit may be disposed on a bezel (BZ), which is a non-display area of ​​the display panel 100, or may be distributed within the pixel array where an input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals may include a scan pulse, an emission control pulse (hereinafter referred to as an "EM pulse"), an initialization pulse, and a sensing pulse.

[0042] The shift register of the gate driver 120 outputs a pulse of a gate signal in response to a start pulse and a shift clock from the timing controller 130, and shifts the pulse in accordance with the timing of the shift clock.

[0043] The timing controller 130 receives digital video data (DATA) of the input image from the host system and timing signals synchronized therewith. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted because the vertical and horizontal periods can be determined by counting the data enable signal DE. The data enable signal DE has a period of one horizontal period (1H).

[0044] The host system may be any one of a TV (television) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system scales a video signal from a video source to match the resolution of the display panel 100 and transmits the scaled video signal together with a timing signal to the timing controller 13.

[0045] In a normal driving mode, the timing controller 130 multiplies the input frame frequency by i to control the operation timing of the display panel driver at an input frame frequency of XI (where i is a natural number) Hz. The input frame frequency is 60 Hz for the NTSC (National Television Standards Committee) system and 50 Hz for the PAL (Phase-Alternating Line) system. In a low-speed driving mode, the timing controller 130 can lower the frame frequency to a frequency between 1 Hz and 30 Hz to lower the pixel refresh rate, thereby lowering the driving frequency of the display panel driver.

[0046] Based on timing signals (Vsync, Hsync, DE) received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0047] The voltage level of the gate timing control signal output from the timing controller 130 may be converted into gate-on voltages (VGH and VEH) and gate-off voltages VGL and VEL through a level shifter (not shown) and supplied to the gate driver 120. The level shifter converts the low level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0048] Due to process variations and device characteristic variations caused during the manufacturing process of the display panel 100, differences in the electrical characteristics of the driving elements may exist between pixels, and these differences may become larger as the pixels are driven over time. To compensate for the electrical characteristic variations of the driving elements between pixels, an internal compensation technique or an external compensation technique may be applied to the OLED display. The internal compensation technique uses an internal compensation circuit configured in each pixel circuit to sample the threshold voltage of the driving element for each subpixel and compensate the gate-source voltage Vgs of the driving element by the threshold voltage. The external compensation technique uses an external compensation circuit to sense the current or voltage of the driving element, which changes depending on the electrical characteristics of the driving element, in real time. The external compensation technique compensates for the electrical characteristic variations (or variations) of the driving element in real time for each pixel by modulating pixel data (digital data) of the input image by the deviation (or variation) of the electrical characteristic of the driving element sensed for each pixel. The display panel driver may drive pixels using external and / or internal compensation techniques.

[0049] 3 is a circuit diagram showing a pixel circuit connected to an external compensation circuit according to the present invention. Referring to FIG. 3, the pixel circuit includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a first switch element M01 for connecting a pixel driving voltage line 41 in response to an emission control signal EM, a second switch element M02 for connecting a data line 40 in response to a scan signal SCAN, a capacitor Cst connected to a gate electrode of the driving element DT, a third switch element M03 for connecting a reference voltage line 43 in response to a sensing signal SENSE, and a fourth switch element M04 for connecting an initialization voltage line 44 in response to an initialization signal INIT.

[0050] A pixel driving voltage, i.e., a high-potential voltage EVDD, is applied to the first electrode of the driving element DT through a high-potential voltage line 41. The driving element DT supplies current to the light-emitting element EL according to the gate-source voltage Vgs to drive the light-emitting element EL. The light-emitting element EL is turned on and emits light when the forward voltage between the anode electrode and the cathode electrode is greater than the threshold voltage. A low-potential voltage ELVSS is applied to the cathode electrode of the light-emitting element EL. A capacitor Cst is connected between the gate electrode and the second electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0051] The first switch element M01 is turned on by the gate-on voltage of the emission control signal EM applied from the gate line, and connects the pixel driving voltage line 41 to the first node n1.

[0052] The second switch element M02 is turned on by the gate-on voltage of the scan signal SCAN applied from the gate line, and connects the data line 40 to the gate electrode of the driving element DT and the capacitor Cst.

[0053] The third switch element M03 applies the reference voltage Vref in response to the sensing signal SENSE. The reference voltage VpreR is applied to the pixel circuit through a reference voltage line 43.

[0054] The fourth switch device M04 is turned on by the gate-on voltage of the initialization signal INIT to connect the initialization voltage line 44 to the gate electrode of the driving device DT and the capacitor Cst.

[0055] The light-emitting element EL may be composed of an OLED. The OLED includes organic compound layers formed between an anode electrode and a cathode electrode. The organic compound layers may include, but are not limited to, a hole injection layer HIL, a hole transport layer HTL, an emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. The switching elements MO1 and MO2 may be composed of n-channel oxide TFTs.

[0056] The OLED used as the light-emitting element EL may have a tandem structure in which multiple light-emitting layers are stacked. A tandem-structure OLED can improve the brightness and lifespan of a pixel. In this case, in sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element EL is sensed through a reference voltage line 43. The current flowing through the reference voltage line 43 is converted into a voltage through an integrator and then converted into digital data through an analog-to-digital converter (ADC). This digital data is sensing data containing information about the threshold voltage or mobility of the driving element DT. The sensing data is transmitted to a data calculation unit. The data calculation unit receives the sensing data from the analog-to-digital converter and adds or integrates a compensation value selected based on the sensing data to the pixel data to compensate for pixel driving deviations and degradation.

[0057] 4 to 8 are diagrams for explaining the operation principle of the sensing circuit according to the embodiment.

[0058] 4, a COF (Chip on Film) may be attached to the display panel PNL. The COF includes a drive IC (SIC) and connects a source PCB (SPCB) to the display panel PNL. The drive IC (SIC) includes a data driver.

[0059] The timing controller 130 and the power supply unit 150 may be mounted on a control PCB (CPCB), which may be connected to a source PCB (SPCB) via a flexible printed circuit (FPC).

[0060] The timing controller 130 includes the above-mentioned reference voltage control unit and can adjust the reference voltage Vref output from the power supply unit 150 based on the result of comparing the sensed reference voltage Vref_sensed from the display panel PNL with the reference voltage Vref output from the power supply unit 150.

[0061] The reference voltage Vref output from the power supply unit 150 can be supplied to the display panel PNL via the FPC, source PCB (SPCB) and COF. Therefore, the reference voltage Vref input (IN) of the display panel PNL is close to the drive IC (SIC).

[0062] The reference voltage lines REFL on the display panel PNL may be connected to the power supply unit 150 via the COF, SPCB, and FPC. The reference voltage lines REFL may be grouped by a shorting bar (SB). The shorting bar may be formed on one side of the display panel PNL, but may be formed as a line-of-glass (LOG) wiring on the display panel, not inside the drive IC (SIC). The reference voltage lines REFL connected to all pixels on the display panel PNL may be connected to the shorting bar. The sensing unit 160 senses the current flowing through the pixel power line to which the high potential voltage EVDD is applied when driven in a sensing mode after power-off. The sensing unit 160 provides the sensed current to the timing controller 130.

[0063] 5, the sensing unit may include a resistor connected to a pixel power line and an ADC connected to the resistor. The sensing unit may further include a switch connected between the pixel power line and the resistor. The switch is turned off in the display mode and turned on in the sensing mode.

[0064] When the switch SW is turned off in the display mode, a high potential voltage EVDD is applied to the pixel PXL through the pixel power line. When the switch SW is turned on in the sensing mode, a high potential voltage is applied to the pixel through the pixel power line and the resistor R, and the current flowing through the resistor is sensed.

[0065] 6a, in this embodiment, when driving in the sensing mode, the gate-on voltage of the light emitting control signal EM is applied to the first switch element M01, the gate-on voltage of the scan signal SCAN is applied to the second switch element M02, and the gate-on voltage of the sensing signal SENSE is applied to the third switch element M03. The gate-on voltages are applied to the first, second, and third switch elements M01, M02, and M03, which turn them on and form a current path that allows the current flowing through the pixel driving voltage line 41 to flow to the reference voltage line 43 without flowing to the light emitting element.

[0066] Therefore, in the embodiment, current sensing can be performed without emitting light from the light emitting element when driven in the sensing mode, and the light emission of the light emitting element is suppressed, thereby solving the visibility problem.

[0067] Referring to FIG. 6b, in this embodiment, when driving in the sensing mode, the gate-off voltage of the emission control signal EM is applied to the first switch element M01, so that the gate-on voltage is applied to the second and third switch elements M01, M02, and M03, preventing current from flowing through the pixel driving voltage line 41 even when they are turned on.

[0068] In this way, the pixel circuit can be selected by the light emission control signal EM when the sensing mode is driven, that is, the amount of current flowing can be measured by allowing current to flow only through the selected pixel circuit.

[0069] 7, the sensing unit senses current in units of blocks each including a predetermined number of pixels. Here, the block may be a square in shape, with the number of pixels in the line direction (X) and the number of pixels in the column direction (Y) being the same, for example, 30 pixels x 30 pixels. The block is not limited to a square shape and may be configured in various shapes.

[0070] The sensing unit senses the current in units of blocks in a predetermined order, and senses different currents depending on the characteristics and degree of degradation of the pixels included in each block.

[0071] The method of sensing current in units of blocks may reduce the overall sensing time and may be configured with a simpler structure than the method of sensing current in units of pixels.

[0072] In this embodiment, the current flowing through each block in the column direction (Y) is sensed, rather than the current flowing through each block in the line direction (X), to improve tack time and consistency.

[0073] 8, an embodiment shows a pixel structure for sensing current in units of blocks. A reference voltage line and a high potential voltage line are connected to all pixels on the display panel so as to be shared, and data voltage lines are connected to the pixels in the column direction (Y), respectively.

[0074] Therefore, even if a reference voltage and a high potential voltage are applied to all pixels on the display panel, it may be possible to select a block in which sensing is performed depending on whether or not data is applied. For example, white data is applied to all pixels in a first block ONBLK in which sensing is performed, and black data is applied to all pixels in a second block OFFBLK in which sensing is not performed. In this case, while white data is applied to one block on the display panel, black data is applied to the remaining blocks.

[0075] When white data is applied to all pixels in the first block, the sensing unit senses the current flowing through the pixel driving voltage line. At this time, since the current flowing through the pixel driving voltage line is a large value per block, the sensing unit does not require an integrator.

[0076] 9a and 9b are diagrams for comparing and explaining the total sensing time. Referring to FIG. 9a, in this embodiment, when driving in the sensing mode, sensing data, i.e., white data, is applied to each block in the column direction (Y), and the current flowing through each block can be sensed. In this case, the total sensing time Ttotal can be defined by the following Equation 1.

[0077] Ttotal=Taddressing+(Tsensing×N_Vblock)×N_subpxl×N_Hblock (Formula 1)

[0078] Here, Taddressing is the time to apply sensing data, Tsensing is the time to sense the current flowing in each block, N_Vblock is the number of blocks located in the column direction (Y), N_subpxl is the number of subpixels, and N_Hblock is the number of blocks located in the line direction (X).

[0079] For example, if the total number of blocks is 36x64, the number of pixels in each block is 30x30, and the resolution is FHD 120hz RGB, the total sensing time Ttotal is [8.33ms+(2ms×36)]×3×64=15.42 seconds.

[0080] 9b, in the comparative example, when the sensing mode is driven, sensing data, i.e., white data, is applied to each block in the line direction (X) to sense the current flowing through each block. At this time, the total sensing time Ttotal can be defined by the following Equation 2.

[0081] Ttotal=(Taddressing+Tsensing)×N_subpxl×N_Hblock×N_Vblock (Formula 2)

[0082] For example, if the total number of blocks is 36x64, the number of pixels in each block is 30x30, and the resolution is FHD 120hz RGB, the total sensing time Ttotal is (8.33ms+2ms)x3x64x36=71.4 seconds.

[0083] [Table 1]

[0084] As shown in Table 1, since there is a large difference in addressing time between the embodiment and the comparative example, it can be seen that the embodiment has a significantly reduced total sensing time compared to the comparative example.

[0085] 10a to 10d are diagrams showing various changes in the shape of the blocks.

[0086] 10a and 10b show a case where the size of the block to be sensed is changed. In this case, the tact time can be reduced depending on the size of the block, as shown in Table 2 below.

[0087] [Table 2]

[0088] 10c and 10d, the number of blocks to which data is applied may be changed. For example, a data voltage may be applied to each block in the column direction (Y), or the blocks in the column direction (Y) may be divided into multiple groups and a data voltage may be applied to each group. In this way, the cycle time may be shortened compared to the comparative example based on the same block size, and the block size may be reduced based on the same cycle time, leading to increased consistency. Therefore, although various configurations for current sensing are possible in the present embodiment, the design may be modified to an optimal configuration taking into account cycle time, block size, consistency, etc.

[0089] 11a to 11d are diagrams for explaining the principle of selecting a sensing region.

[0090] 11A, in an embodiment, sensing data, i.e., white data, is applied to pixels in a sensing region M1 to be sensed in the vertical or column direction (Y) along the data line, and black data is applied to pixels in unsensing regions (M2 to M8) that are not to be sensed. In an embodiment, a sensing region to be sensed can be selected by applying data. In this manner, current can be sensed for each block included in the selected sensing region.

[0091] Referring to FIG. 11b, current must be sensed for each block included in the sensing area, and at this time, the block can be selected using a light emission control signal.

[0092] In this embodiment, light emission control signals for selecting the blocks N1 to N6 included in the sensing region M1 arranged in the column direction (Y) along the data lines can be sequentially applied.

[0093] Referring to FIG. 11c, when the first block N1 included in the sensing region M1 is selected, a high voltage level of the light emission control signal is applied to the first block N1, and the pixel driving voltage EVDD flows through the driving element, and a low voltage level of the light emission control signal is sequentially applied to the second block to the sixth blocks N2 to N6.

[0094] At this time, each sub-pixel of the first block in the block group to be sensed is configured with the same circuit as that shown in FIG. 3, and the first switch element is turned on by the high voltage level of the light emitting control signal, and the pixel driving voltage EVDD is applied to form a current path.

[0095] Meanwhile, each sub-pixel of the remaining blocks in the sensing area to be sensed is configured with the same circuit as that shown in FIG. 3, and the first switch element is turned off by the low voltage level of the light emission control signal, so that the pixel driving voltage EVDD is not applied and a current path cannot be formed.

[0096] Referring to FIG. 11d, after the addressing period, blocks N1, N2, N3, N4, N5, and N6 in the sensing region to be sensed are sequentially driven during the sensing period, thereby sensing current.

[0097] FIG. 12 is a diagram showing a shift register of a gate driver according to an embodiment of the present invention, FIG. 13 is a diagram showing a signal transmission unit of a sensing driver according to an embodiment, FIG. 14 is a diagram showing a signal transmission unit of an EM driver according to an embodiment, and FIG. 15 is a waveform diagram showing an output signal of the signal transmission unit shown in FIG. 14.

[0098] Referring to FIG. 12, the gate driver 120 according to the embodiment includes a number of signal processing units STG1, STG2, STG3, STG4, STG5, STG6, and STG7 cascade-connected via carry lines through which carry signals are transmitted.

[0099] The timing controller 130 can adjust the width and multi-output of the output signal GOUT of the gate driver using the start pulse Vst input to the gate driver 120.

[0100] Each of the signal processing units STG1, STG2, STG3, STG4, STG5, STG6, and STG7 receives a start pulse or a carry signal output from the previous odd-numbered or even-numbered signal processing unit and a clock signal CLK1, CLK2, CLK3, or CLK4. The first signal processing unit STG1 begins to operate in response to a start pulse Vst, while the other signal processing units STG2, STG3, STG4, STG5, STG6, and STG7 begin to operate in response to a carry signal output from the previous odd-numbered or even-numbered signal processing unit.

[0101] 13, each signal transmission unit of the sensing driver according to the embodiment includes a first circuit unit 210 and a second circuit unit 220. The first circuit unit 210 charges or discharges a first control node (hereinafter referred to as a "Q node") and a second control node (hereinafter referred to as a "Qb node").

[0102] In this case, the first circuit unit 210 includes a control circuit that controls the charging and discharging of the Q node (Q) and the Qb node (Qb), and an inverter circuit that inverts the voltage of the Q node (Q(n)) and applies it to the Qb node (Qb(n)). The inverter circuit includes a Qb node charging unit and a Qb node discharging unit. The second circuit unit 220 outputs a sensing signal SEOUT(n) corresponding to the potentials of the Q node (Q) and the Qb node (Qb).

[0103] The second circuit unit 220 includes first buffer transistors T1 and T2 that output a sensing signal SEOUT(n). The first buffer transistors T1 and T2 are divided into a first pull-up transistor T1 that turns on based on the potential of a Q node (Q) and a first pull-down transistor T2 that turns on based on the potential of a Qb node (Qb). The first pull-up transistor T1 has a gate electrode connected to the Q node (Q), a first electrode connected to a clock signal line SECLK(n), and a second electrode connected to a first output terminal SEOUT(n). The first pull-down transistor T2 has a gate electrode connected to the Qb node (Qb), a first electrode connected to the first output terminal SEOUT(n), and a second electrode connected to a low-potential voltage line SEGVSS0. The first buffer transistors T1 and T2 output the sensing signal SEOUT(n) based on the clock signal applied through the clock signal line SECLK(n) and the low-potential voltage applied through the low-potential voltage line GVSS0.

[0104] 6A, in the embodiment, the voltage of the sensing signal is set to maintain a high voltage level so that a current path is formed bypassing the light emitting device when driven in the sensing mode. For example, in the embodiment, the voltages applied to the clock signal line SECLK(n) and the low potential voltage line SEGVSS0 can be set to a high voltage level when driven in the sensing mode.

[0105] 14, each signal transmission unit of the gate driver according to the embodiment includes a first circuit unit 211 and a second circuit unit 221. The first circuit unit 211 charges or discharges a first control node (hereinafter referred to as a "Q node") and a second control node (hereinafter referred to as a "Qb node").

[0106] In this case, the first circuit unit 211 includes a control circuit that controls the charging and discharging of the Q node (Q) and the Qb node (Qb), and an inverter circuit that inverts the voltage of the Q node (Q(n)) and applies it to the Qb node (Qb(n)). The inverter circuit includes a Qb node charging unit and a Qb node discharging unit. The second circuit section 221 outputs a light emission control signal EMOUT(n) corresponding to the potentials of the Q node (Q) and the Qb node (Qb).

[0107] The second circuit unit 221 includes first buffer transistors T1 and T2 that output an emission control signal EMOUT(n). The first buffer transistors T1 and T2 are divided into a first pull-up transistor T1 that turns on based on the potential of a Q node (Q) and a first pull-down transistor T2 that turns on based on the potential of a Qb node (Qb). The first pull-up transistor T1 has a gate electrode connected to the Q node (Q), a first electrode connected to a clock signal line EMCLK(n), and a second electrode connected to a first output terminal EMOUT(n). The first pull-down transistor T2 has a gate electrode connected to the Qb node (Qb), a first electrode connected to the first output terminal EMOUT(n), and a second electrode connected to a low-potential voltage line GVSS0. The first buffer transistors T1 and T2 output the emission control signal EMOUT(n) based on the clock signal applied through the clock signal line EMCLK(n) and the low-potential voltage applied through the low-potential voltage line GVSS0.

[0108] 15, each of the signal processors STG1, STG2, STG3, STG4, STG5, STG6, and STG7 sequentially outputs the light emission control signals by shifting the start pulse or the carry signal output from the previous signal processor in accordance with the timing of the clock signal. In this embodiment, the signal processor may sequentially output the light emission control signals in units of blocks.

[0109] Here, as an example, a case where one block includes five pixel lines is shown. For example, in a first sensing period (1), a light emission control signal of a high voltage level is applied from a signal transfer unit connected to the first block in response to a clock signal EMCLK(ON), and in a second sensing period (2), a light emission control signal of a high voltage level is applied from a signal transfer unit connected to the second block in response to the clock signal EMCLK(ON).

[0110] The light emitting control signal applied to the first block may be applied at a high voltage level in response to the rising edge of the clock signal EMCLK(ON) during the first sensing period, and at a low voltage level in response to the rising edge of the clock signal EMCLK(OFF) during the second sensing period. That is, the light emitting control signal from the signal transfer unit may be applied at a high voltage level only during the period in which the amount of current in the corresponding block is sensed. Therefore, in this embodiment, as shown in Figures 6a and 6b, when operating in sensing mode, the voltage of the light emitting control signal is applied at a high voltage level to pixel circuits located in selected blocks of the sensing area, and the voltage of the light emitting control signal is applied at a low voltage level to pixel circuits located in unselected blocks, thereby allowing a block to be selected by the light emitting control signal. Although the present invention has been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present invention. Therefore, the disclosed embodiments are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the scope of the claims, and all technical concepts within the equivalent range thereof should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0111] 100: Display panel 110: Data driver 120: Gate driver 130: Timing controller 140: Level shifter 200: Host System 400: Power supply section

Claims

1. a plurality of pixels connected to a power supply line for supplying a pixel driving voltage and extending along a first direction, the plurality of pixels being divided into a plurality of pixel blocks each including a different pixel; a plurality of data lines extending in a first direction, connected to the plurality of pixels, and applying data voltages of pixel data to the plurality of pixels; a plurality of gate lines connected to the plurality of pixels and extending in a second direction intersecting the first direction, the plurality of gate lines applying gate signals to the plurality of pixels; a data driver for supplying a plurality of data voltages to the plurality of data lines during a display mode and for supplying sensing data to the plurality of data lines during a sensing mode; a gate driver for supplying gate signals to the plurality of gate lines; a sensing circuit configured to sense a current flowing through a power supply line connected to each pixel included in each pixel block included in one column of the pixel blocks among the plurality of columns of pixel blocks during the sensing mode; The sensing circuit includes: Resistance and a switch that connects the resistor in series to the power supply line during the sensing mode, and disconnects the resistor from the power supply line during the display mode, so that no power is supplied; During the sensing mode, the data driver supplies the sensing data to a sensing area including one column of pixel blocks from the plurality of columns of pixel blocks; the gate driver sequentially supplies light emitting signals to each pixel block in the sensing area; the sensing circuit senses a current flowing through the power supply line connected to each of the pixels included in each pixel block to which the light emission signal is applied; Each of the plurality of pixels a driving element including a first electrode coupled to a first node, a gate electrode coupled to a second node, and a second electrode coupled to a third node; a first switch element including a first electrode connected to a power line to which a pixel driving voltage is applied, a gate electrode to which a light emitting signal is applied, and a second electrode connected to the first node; a light emitting device including an anode electrode connected to the third node and a cathode electrode to which a low potential power supply voltage is supplied; a capacitor coupled between the second node and the third node; a second switch element including a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; a third switch element including a first electrode connected to the third node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference line to which a reference voltage is applied; During the sensing mode, the first, second, and third switch elements are turned on to form a current path that causes the current flowing through the power supply line to flow to the reference line without flowing to the light-emitting element.

2. 2. The display device of claim 1, wherein the sensing circuit sequentially senses each pixel block included in a column of the pixel blocks during the sensing mode in which sensing data is supplied to each pixel included in the pixel block and a current flowing through the power line is sensed according to the sensing data.

3. 3. The display device of claim 2, wherein the sensing data includes white image data, and the data driver supplies the white image data to each pixel block in a column of sensed pixel blocks and supplies black image data to the remaining pixel blocks included in other columns of unsensed pixel blocks.

4. 4. The display device of claim 3, wherein each first switch element included in each pixel of the target pixel block in the sensed pixel block is turned on during the sensing mode in response to a gate electrode to which an emission signal is applied at an on level, and is turned off in response to a gate electrode to which an emission signal is applied at an off level.

5. 5. The display device of claim 4, wherein each of the first switch elements included in each pixel of the remaining pixel blocks included in the pixel blocks of the other columns to which the black image data is applied because they are not sensed is turned on during the sensing mode in response to a gate electrode to which an emission signal is applied at an on level.

6. The sensing circuit includes:

2. The display device of claim 1, further comprising an ADC coupled in parallel to the resistor and configured to convert a voltage difference across the resistor, which indicates a current flowing through the power line during the sensing mode, into a digital value.

7. 7. The display device of claim 6, wherein the pixel data of an image is adjusted with a compensation value based on the digital value.

8. The gate driver a shift register for outputting the sensing pulse; The shift register includes a plurality of signal transmission units, each of which: a first transistor including a gate electrode connected to a first control node, a first electrode connected to a clock node, and a second electrode connected to an output node from which the sensing pulse is output; a second transistor including a gate electrode coupled to a second control node, a first electrode coupled to the output node, and a second electrode coupled to a voltage node; During the display mode, a clock that switches between an on voltage and an off voltage is output to a clock node, and a low potential power supply voltage is applied to the voltage node; The display device of claim 1 , wherein during the sensing mode, the on-voltage is applied to the clock node and the voltage node, respectively.

9. a plurality of pixels connected to a power supply line to which a pixel driving voltage is applied; a plurality of data lines extending in a first direction, connected to the plurality of pixels, and applying data voltages of pixel data to the plurality of pixels; a plurality of gate lines connected to the plurality of pixels, extending in a second direction intersecting the first direction, and applying gate signals to the plurality of pixels; a data driver for supplying a plurality of data voltages to the plurality of data lines during a display mode and for supplying sensing data to the plurality of data lines during a sensing mode; a gate driver for supplying gate signals to the plurality of gate lines; a sensing circuit configured to sense a current flowing through a power supply line connected to each pixel included in each pixel block included in one column of the pixel blocks among the plurality of columns of pixel blocks during the sensing mode; The sensing circuit includes: Resistance and a switch that connects the resistor in series to the power supply line during the sensing mode, and disconnects the resistor from the power supply line during the display mode, so that no power is supplied; During the sensing mode, the data driver supplies the sensing data to a sensing area including one column of pixel blocks from the plurality of columns of pixel blocks; the gate driver sequentially supplies light emitting signals to each pixel block in the sensing area; the sensing circuit senses a current flowing through the power supply line connected to each of the pixels included in each pixel block to which the light emission signal is applied; Each of the plurality of pixels a driving element including a first electrode coupled to a first node, a gate electrode coupled to a second node, and a second electrode coupled to a third node; a first switch element including a first electrode connected to a power line to which a pixel driving voltage is applied, a gate electrode to which a light emitting signal is applied, and a second electrode connected to the first node; a light emitting device including an anode electrode connected to the third node and a cathode electrode to which a low potential power supply voltage is supplied; a capacitor coupled between the second node and the third node; a second switch element including a first electrode connected to a data line to which the data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; a third switch element including a first electrode connected to the third node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a reference line to which a reference voltage is applied; During the sensing mode, the first, second, and third switch elements are turned on to form a current path that causes the current flowing through the power supply line to flow to the reference line without flowing to the light-emitting element.

10. The display device of claim 9 , wherein the plurality of pixels are separated into a plurality of rows of pixel blocks extending along a first direction, each pixel block including another pixel of the plurality of pixels.

11. 11. The display device of claim 10, wherein the pixel is included in one pixel block among a column of sensed pixel blocks, and the pixels included in the column of pixel blocks are provided with sensing data including white image data, and the pixels included in the pixel blocks of the remaining columns among a plurality of columns of pixel blocks that are not sensed during the sensing mode are provided with black image data.

12. 12. The display device of claim 11, wherein the sensing circuit sequentially senses each pixel block included in a column of the pixel blocks during the sensing mode in which sensing data is supplied to each pixel included in each pixel block and a current flowing through the power line is sensed according to the sensing data.

13. 10. The display device of claim 9, wherein each first switch element included in each pixel of the target pixel block in the sensed pixel block is turned on during the sensing mode in response to a gate electrode to which an emission signal is applied at an on level, and is turned off in response to a gate electrode to which an emission signal is applied at an off level.

14. 14. The display device of claim 13, wherein each of the first switch elements included in each pixel of the remaining pixel blocks included in the pixel blocks of other columns to which black image data is applied because no sensing is performed is turned on during the sensing mode in response to a gate electrode to which an emission signal is applied at an on level.

Images