Display device manufacturing equipment

Abstract

To provide a display apparatus, and an apparatus for and a method of manufacturing the same.SOLUTION: A manufacturing apparatus of a display apparatus includes: a chamber a portion of which is selectively opened / closed; a first support part which is arranged inside the chamber and supports a board; a mask assembly which is arranged so as to be opposed to the board; a second support part which supports the mask assembly; and a vapor deposition source which supplies the substrate with a vapor deposition material. The mask assembly includes interchangeable first mask assembly and second mask assembly. The second mask assembly is equipped with a mask frame and a mask sheet placed on the mask frame. The mask sheet includes a first opening, a second opening, and a third opening. The second opening and the third opening are connected to each other. The first opening is separated from the second opening and the third opening. The shapes of the first opening and the second opening are different from each other. The area of the first opening is smaller than the area of the second opening.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to an apparatus and a method, and more particularly to a display device, a display device manufacturing apparatus, and a display device manufacturing method. [Background technology]

[0002] Recently, the uses of display devices have become more diverse, and display devices have become thinner and lighter, and their range of use has become wider.

[0003] As display devices are used in a variety of ways, various methods for designing display devices are emerging, and the number of functions that can be integrated or linked to display devices is increasing. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a method for increasing the functionality that can be integrated or linked to a display device, and a display device having a sensor area in which a sensor or the like is disposed inside the display area, a manufacturing apparatus for the same, and a manufacturing method for the same. However, such problems are merely examples, and the scope of the present invention is not limited thereto. [Means for solving the problem]

[0005] One embodiment of the present invention relates to a substrate including a first display region including a first pixel region, a second pixel region, and a first transmission region, a second display region disposed adjacent to the first display region and including a third pixel region, a fourth pixel region, a second transmission region, and a third transmission region, and a third display region disposed adjacent to the second display region; a first pixel disposed on the first pixel region and including a first pixel electrode, a first counter electrode, and a first intermediate layer disposed between the first pixel electrode and the first counter electrode; and a second pixel disposed on the second pixel region and including a second pixel electrode, a second counter electrode, and a first intermediate layer disposed between the second pixel electrode and the second counter electrode. a third pixel disposed on the third pixel region and including a third pixel electrode, a third opposing electrode, and a third intermediate layer disposed between the third pixel electrode and the third opposing electrode; and a fourth pixel disposed on the fourth pixel region and including a fourth pixel electrode, a fourth opposing electrode, and a fourth intermediate layer disposed between the fourth pixel electrode and the fourth opposing electrode, wherein the third opposing electrode is connected to the first opposing electrode or the second opposing electrode, the third opposing electrode and the fourth opposing electrode are connected to each other, and the third opposing electrode and the fourth opposing electrode have different planar areas.

[0006] In this embodiment, the first pixel regions, the second pixel regions, and the first transmission regions may be alternately arranged in a lattice pattern.

[0007] In this embodiment, the first transmission region may be defined by the first pixel region and the second pixel region connected to each other.

[0008] In this embodiment, the first opposing electrode and the second opposing electrode may be in surface contact with each other at portions thereof.

[0009] In this embodiment, the second opposing electrode may be disposed on the first opposing electrode in a region where they are in surface contact with each other.

[0010] In this embodiment, the first transmission region and the third transmission region may have different shapes.

[0011] In the present embodiment, the light transmittance of the first display region may be different from the light transmittance of at least one of the second display region and the third display region.

[0012] In this embodiment, the resolution of the image provided in the first display area may be lower than the resolution of the image provided in at least one of the second display area and the third display area.

[0013] In this embodiment, the third display region includes a main pixel arranged on the third display region, the main pixel including a main pixel electrode, a main counter electrode, and a main intermediate layer arranged between the main pixel electrode and the main counter electrode, and the main counter electrode may be arranged over the entire third display region.

[0014] In this embodiment, the main counter electrode may be connected to the fourth counter electrode disposed in the second display area.

[0015] In this embodiment, the main counter electrode may include a plurality of main counter electrodes formed in a stripe shape, and the plurality of main counter electrodes may be spaced apart from each other.

[0016] Another embodiment of the present invention relates to a substrate including a first display region including a first pixel region, a second pixel region, and a first transmissive region, a second display region disposed adjacent to the first display region and including a third pixel region, a fourth pixel region, a second transmissive region, and a third transmissive region, and a third display region disposed adjacent to the second display region, a first pixel disposed on the first pixel region and including a first pixel electrode, a first counter electrode, and a first intermediate layer disposed between the first pixel electrode and the first counter electrode, a second pixel disposed on the second pixel region and including a second pixel electrode, a second counter electrode, and a second intermediate layer disposed between the second pixel electrode and the second counter electrode, and a second intermediate layer disposed on the third pixel region. a third pixel including a third pixel electrode, a third opposing electrode, and a third intermediate layer disposed between the third pixel electrode and the third opposing electrode; a fourth pixel disposed on the fourth pixel region and including a fourth pixel electrode, a fourth opposing electrode, and a fourth intermediate layer disposed between the fourth pixel electrode and the fourth opposing electrode; and a component disposed on one side of the substrate to correspond to the first display region and including electronic elements that emit and receive light, wherein the third opposing electrode is connected to the first opposing electrode or the second opposing electrode, the third opposing electrode and the fourth opposing electrode are connected to each other, and the third opposing electrode and the fourth opposing electrode have different planar areas.

[0017] In this embodiment, the component may emit or receive light through the first transmissive region, and the light transmittance of the second display region and the third display region may be lower than the light transmittance of the first display region.

[0018] Yet another embodiment of the present invention discloses an apparatus for manufacturing a display device, the apparatus including: a chamber, a portion of which is selectively opened and closed; a first support portion disposed within the chamber and supporting a substrate; a mask assembly disposed within the chamber facing the substrate; a second support portion disposed within the chamber and supporting the mask assembly; and a deposition source disposed in the chamber and supplying a deposition material to the substrate, the mask assembly including a first mask assembly and a second mask assembly which are exchangeable with each other; the second mask assembly including a mask frame and a mask sheet placed on the mask frame; the mask sheet including a first opening, a second opening disposed in a portion of the mask sheet different from the first opening, and a third opening disposed in a portion of the mask sheet different from the first opening and the second opening, the second opening and the third opening being connected to each other, the first opening being separated from the second opening and the third opening, the first opening and the second opening having different shapes, and the area of ​​the first opening being smaller than the area of ​​the second opening.

[0019] In this embodiment, the deposition source may be disposed in a corner of the chamber.

[0020] In this embodiment, the first opening may be square and the second opening may be rectangular.

[0021] In this embodiment, at least one of the first support portion and the second support portion may adjust the relative position between the substrate and the first mask assembly.

[0022] In the present embodiment, a plurality of the third openings may be provided so as to be spaced apart from each other, and each of the third openings may be formed in a line shape.

[0023] Another embodiment of the present invention discloses a method for manufacturing a display device, the method comprising: disposing a substrate and a first mask assembly in a chamber; allowing a deposition material supplied from a deposition source to pass through the first mask assembly, thereby forming first opposing electrodes in a first display area and a second display area of ​​the substrate, respectively; varying a position of at least one of the substrate and the first mask assembly; allowing the deposition material supplied from the deposition source to pass through the first mask assembly, thereby forming second opposing electrodes in the first display area and the second display area, each of which at least partially overlaps the first opposing electrode; and replacing the first mask assembly with a second mask assembly, supplying a deposition material from the deposition source to the substrate to form a third opposing electrode and a fourth opposing electrode in the second display area and a main opposing electrode in the third display area of ​​the substrate, wherein the third opposing electrode connects one of the first opposing electrode or the second opposing electrode to the fourth opposing electrode, and the third opposing electrode and the fourth opposing electrode have different planar areas.

[0024] In the present embodiment, a first transmission region may be disposed between the first opposing electrode and the second opposing electrode.

[0025] In this embodiment, the first opposing electrode and the second opposing electrode may be in surface contact with each other at portions thereof.

[0026] In this embodiment, a second transmission region may be arranged between one of the first opposing electrode or the second opposing electrode, the third opposing electrode, and the fourth opposing electrode, and a third transmission region may be arranged between one of the first opposing electrode or the second opposing electrode, the third opposing electrode, the fourth opposing electrode, and the main opposing electrode.

[0027] In this embodiment, the second transmission region and the third transmission region may have different shapes.

[0028] In this embodiment, the resolution of the image provided in the first display area may be lower than the resolution of the image provided in at least one of the second display area and the third display area.

[0029] In the present embodiment, the light transmittance of the first display region may be different from the light transmittance of at least one of the second display region and the third display region.

[0030] In this embodiment, the light transmittance of the second display region may be higher than the light transmittance of the first display region and lower than the light transmittance of the third display region.

[0031] Other aspects, features, and advantages of the invention, in addition to those described above, will become apparent from the following drawings, claims, and detailed description of the invention.

[0032] Such general and specific aspects may be implemented using a system, a method, a computer program, or any combination of systems, methods, and computer programs. [Effects of the Invention]

[0033] According to an embodiment of the present invention as described above, it is possible to realize a display panel having an expanded display area so that an image can be displayed even in an area where components are arranged, and a display device including the same, although it should be understood that the scope of the present invention is not limited by such effects. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view illustrating a display device according to an embodiment of the present invention; [Figure 3] 1 is a plan view schematically illustrating a display panel according to an embodiment of the present invention; [Figure 4] 4 is an enlarged plan view showing an embodiment of the first display region of FIG. 3. FIG. [Figure 5] 2 is an equivalent circuit diagram of a pixel of a display panel according to an embodiment of the present invention; [Figure 6] 2 is an equivalent circuit diagram of a pixel of a display panel according to an embodiment of the present invention; [Figure 7] 2 is a schematic layout diagram of a pixel circuit of a pixel according to an embodiment of the present invention; [Figure 8] 8 is a cross-sectional view taken along lines II' and II-II' in FIG. 7. [Figure 9] 2 is a plan view showing a part of a first display region according to an embodiment of the present invention. FIG. [Figure 10] 2 is a plan view showing a part of a first display region according to an embodiment of the present invention. FIG. [Figure 11] 3A to 3C are cross-sectional views schematically illustrating a part of a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 12] 3A to 3C are cross-sectional views schematically illustrating a part of a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 13] FIG. 10 is a cross-sectional view schematically showing a cross section taken along line BB' in FIG. 9. [Figure 14] 2 is a plan view showing the arrangement of counter electrodes of a display panel according to an embodiment of the present invention; FIG. [Figure 15] FIG. 15 is a cross-sectional view schematically showing a cross section taken along line CC' in FIG. [Figure 16] FIG. 15 is a cross-sectional view schematically showing a cross section taken along line DD' in FIG. [Figure 17] 1 is a cross-sectional view schematically illustrating a display device manufacturing apparatus according to an embodiment of the present invention. [Figure 18] FIG. 18 is a perspective view showing the first mask assembly shown in FIG. 17. [Figure 19] FIG. 18 is a plan view showing a portion of one embodiment of the first mask sheet shown in FIG. 17. [Figure 20] FIG. 18 is a plan view showing a portion of one embodiment of the second mask sheet shown in FIG. 17. [Figure 21] FIG. 10 is a plan view showing the arrangement of counter electrodes of a display panel according to another embodiment of the present invention. [Figure 22] FIG. 18 is a plan view showing a portion of another embodiment of the second mask sheet shown in FIG. 17. [Figure 23] FIG. 10 is a plan view showing the arrangement of counter electrodes of a display panel according to another embodiment of the present invention. [Figure 24] FIG. 18 is a plan view showing a portion of another embodiment of the second mask sheet shown in FIG. 17. DETAILED DESCRIPTION OF THE INVENTION

[0035] The present invention can be modified in various ways and can have various embodiments, but specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. The advantages, features, and methods of achieving the present invention will become clear by referring to the embodiments described in detail below together with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be realized in various forms.

[0036] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be designated by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0037] In the following embodiments, terms such as "first" and "second" are not used in a limiting sense but are used to distinguish one component from another.

[0038] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0040] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only mean that it is directly on top of the other part, but also means that there is another film, region, component, etc. interposed between them.

[0041] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings.

[0042] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on a Cartesian coordinate system, but are also interpreted in a broader sense including the three axes. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may not be perpendicular to each other and point in different directions.

[0043] When an embodiment is otherwise realizable, the order of certain steps may be performed differently than that described, for example, two steps described as successive may be performed substantially simultaneously or may be performed in the opposite order from that described.

[0044] FIG. 1 is a perspective view showing a display device according to an embodiment of the present invention.

[0045] 1, the display device 1 includes a display area DA for displaying an image and a non-display area NDA for not displaying an image. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3. The display device 1 can provide a main image by using light emitted from a plurality of main pixels PXm arranged in the third display area DA3.

[0046] At least one of the first display area DA1 and the second display area DA2 may have components, such as sensors that use infrared rays, visible light, sound, etc., disposed below it, as will be described later with reference to Fig. 2. For ease of explanation, the following detailed description will focus on the case where components are disposed in the first display area DA1.

[0047] The first display area DA1 may include a first transmission area TA1 through which light and / or sound output from the component to the outside or traveling toward the component from the outside can pass. In one embodiment of the present invention, when infrared light passes through the first display area DA1, the light transmittance may be about 10% or more, more preferably 20% or more, 25% or more, 50% or more, 85% or more, or 90% or more.

[0048] The light transmittance of the first display region DA1 may be different from at least one of the light transmittance of the second display region DA2 and the light transmittance of the third display region DA3. For example, the light transmittance of the first display region DA1 may be higher than the light transmittance of the second display region DA2 or the light transmittance of the third display region DA3. In another embodiment, the light transmittance of the first display region DA1 may be higher than the light transmittance of the second display region DA2 and the light transmittance of the third display region DA3. In such a case, the light transmittance of the second display region DA2 is higher than the light transmittance of the third display region DA3. In particular, the light transmittance of the second display region DA2 is approximately equal to the arithmetic mean of the sum of the light transmittance of the first display region DA1 and the light transmittance of the third display region DA3.

[0049] In this embodiment, a plurality of auxiliary pixels PXa may be arranged in the first display area DA1, and a predetermined image may be provided using light emitted from the plurality of auxiliary pixels PXa. The image provided from the first display area DA1 is an auxiliary image and has lower resolution than an image provided from at least one of the second display area DA2 and the third display area DA3. That is, the first display area DA1 includes a first transmissive area TA1 through which light and / or sound can pass, but the number of auxiliary pixels PXa arranged per unit area may be smaller than the number of connecting pixels PXc arranged per unit area in the second display area DA2 or the number of main pixels PXm arranged per unit area in the third display area DA3. In another embodiment, the number of auxiliary pixels PXa arranged per unit area in the first display area DA1 may be smaller than the number of connecting pixels PXc arranged per unit area in the second display area DA2 and the number of main pixels PXm arranged per unit area in the third display area DA3. In such a case, the number of link pixels PXc arranged per unit area of ​​the second display area DA2 may be smaller than the number of main pixels PXm arranged per unit area of ​​the third display area DA3.

[0050] Hereinafter, an organic light emitting display device will be described as an example of a display device 1 according to an embodiment of the present invention, but the display device of the present invention is not limited thereto. In other embodiments, various types of display devices such as an inorganic electroluminescence display (EL display) or a quantum dot light emitting display (QD display) may be used.

[0051] 1, the first display area DA1 is shown disposed on one side of the rectangular second display area DA2, but the present invention is not limited thereto. The shape of the second display area DA2 may be circular, elliptical, or polygonal, such as triangular or pentagonal, and the position and number of the first display area DA1 may also be varied.

[0052] 2 is a cross-sectional view of a display device according to an embodiment of the present invention, taken along line AA' in FIG.

[0053] Referring to FIG. 2, the display device 1 may include a display panel 10 including a display element, and a component 20 located below the display panel 10 and corresponding to a first display area DA1.

[0054] The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. The display panel 10 may further include a lower protective film 175 disposed under the substrate 100.

[0055] The substrate 100 may include glass or a polymer resin. The polymer resin may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may also have a multilayer structure including a layer including the aforementioned polymer resin and an inorganic layer (not shown).

[0056] The display element layer 200 may include a circuit layer including thin film transistors TFT, organic light emitting diodes OLED as display elements, and an insulating layer IL therebetween.

[0057] In the third display area DA3, a main pixel PXm including a thin film transistor TFT and an organic light emitting diode OLED connected thereto is arranged, in the second display area DA2, a connection pixel PXc including a thin film transistor TFT and an organic light emitting diode OLED connected thereto is arranged, and in the first display area DA1, an auxiliary pixel PXa including a thin film transistor TFT and an organic light emitting diode OLED connected thereto is arranged, and wiring (not shown) electrically connected to the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa may be arranged.

[0058] The first display area DA1 may also be provided with a first transmissive area TA1 in which no thin film transistors TFTs or pixels are arranged. The first transmissive area TA1 may be understood as an area through which light / signals emitted from the component 20 or light / signals incident on the component 20 are transmitted. The second display area DA2 may also be provided with a second transmissive area TA2 and a third transmissive area TA3 similar to the first display area DA1.

[0059] The components 20 may be located in the first display area DA1 and the second display area DA2. Preferably, the components 20 are located in the first display area DA1. The components 20 may be electronic elements that utilize light or sound. For example, the components 20 may be sensors that receive and utilize light, such as infrared sensors, sensors that output light or sound to measure distance or recognize fingerprints, small lamps that output light, or speakers that output sound. It goes without saying that electronic elements that utilize light can utilize light in various wavelength bands, such as visible light, infrared light, and ultraviolet light. The first display area DA1 may include a plurality of components 20. For example, a single first display area DA1 may include both a light-emitting element and a light-receiving element. Alternatively, a single component 20 may include both a light-emitting unit and a light-receiving unit.

[0060] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, Figure 2 shows a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 with an organic encapsulation layer 320 therebetween.

[0061] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulators selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. Examples of polymer-based materials include polyethylene terephthalate (PET), polyethylene naphthalate, polycarbonate, polyimide (PI), polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), and any combination thereof.

[0062] The lower protective film 175 is attached to the lower part of the substrate 100 and may support and protect the substrate 100. The lower protective film 175 may have an opening 175OP corresponding to the first display area DA1. By providing the opening 175OP in the lower protective film 175, the light transmittance of the first display area DA1 may be improved. The lower protective film 175 may be made of polyethylene terephthalate or polyimide.

[0063] The area of ​​the first display area DA1 may be larger than the area in which the component 20 is disposed. Although the area of ​​the first display area DA1 and the area of ​​the opening 175OP are illustrated as being the same in FIG. 2, the area of ​​the opening 175OP provided in the lower protective film 175 does not have to be the same as the area of ​​the first display area DA1. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the first display area DA1.

[0064] Although not shown, components such as an input sensing element for sensing a touch input, a polarizer and a retarder, or an anti-reflection element including a color filter and a black matrix, and a transparent window may be further arranged on the display panel 10.

[0065] Meanwhile, in this embodiment, the thin film encapsulation layer 300 is illustrated as being used as an encapsulation member for encapsulating the display element layer 200, but the present invention is not limited thereto. For example, a encapsulation substrate that is bonded to the substrate 100 by a sealant or frit may also be used as an encapsulation member for encapsulating the display element layer 200.

[0066] Fig. 3 is a plan view schematically illustrating a display panel according to an embodiment of the present invention, and Fig. 4 is an enlarged plan view illustrating an embodiment of a first display region of Fig. 3.

[0067] 3 and 4, various components constituting the display panel 10 are disposed on a substrate 100. The substrate 100 includes a display area and a non-display area NDA surrounding the display area. The display area includes a second display area DA2 and a third display area DA3 in which a main image is displayed, and a first display area DA1 having a first transmissive area TA1 therein in which an auxiliary image is displayed.

[0068] A plurality of main pixels PXm are arranged in the third display area DA3. Each of the main pixels PXm may include a display element such as an organic light emitting element (OLED). Each main pixel PXm may emit light of, for example, red, green, blue, or white through the organic light emitting element (OLED). As described above, the main pixel PXm in this specification may be understood as a pixel that emits light of any one of red, green, blue, and white. The second display area DA2 may be covered with the sealing member described above with reference to FIG. 2 to protect it from external air or moisture.

[0069] The first display area DA1 may be disposed inside the second display area DA2, and a plurality of auxiliary pixels PXa may be disposed in the first display area DA1. Each of the auxiliary pixels PXa may include a display element such as an organic light emitting diode (OLED). Each of the auxiliary pixels PXa may emit light of, for example, red, green, blue, or white through the OLED. As described above, the auxiliary pixel PXa in this specification may be understood as a pixel that emits light of any one of red, green, blue, and white. Meanwhile, the first display area DA1 includes a first transmission area TA1 disposed between the auxiliary pixels PXa.

[0070] The first display area DA1 includes a first transmissive area TA1, but the resolution of the first display area DA1 is lower than that of the second display area DA2. For example, the resolution of the first display area DA1 may be approximately half that of the second display area DA2. In some embodiments, the resolution of the second display area DA2 may be 400 ppi or greater, and the resolution of the first display area DA1 may be approximately 200 ppi.

[0071] The first display area DA1 will be described with reference to FIG.

[0072] The first display area DA1 may include a sub-pixel area PA1 including at least one sub-pixel PXa and a first transmissive area TA1. The sub-pixel area PA1 and the first transmissive area TA1 may be alternately arranged along the first direction DR1 and the second direction DR2, for example, in a grid pattern.

[0073] The auxiliary pixel region PA1 may include a red-emitting auxiliary pixel Pr, a green-emitting auxiliary pixel Pg, and a blue-emitting auxiliary pixel Pb. While pentile-type auxiliary pixels PXa are illustrated in FIG. 4, the auxiliary pixels PXa may be formed in stripe or various other shapes. Although eight auxiliary pixels PXa are illustrated in FIG. 4, the number of auxiliary pixels PXa may be varied depending on the resolution of the first display region DA1.

[0074] In one embodiment, one main pixel PXm, one connecting pixel PXc, and one auxiliary pixel PXa may include the same pixel circuit. However, the present invention is not limited to this. It goes without saying that the pixel circuit included in the main pixel PXm, the pixel circuit included in the connecting pixel PXc, and the pixel circuit included in the auxiliary pixel PXa are different from each other.

[0075] The first transmissive region TA1 may not include auxiliary pixels PXa. This absence of auxiliary pixels PXa means that the auxiliary pixels PXa do not include display elements such as organic light-emitting elements (OLEDs). In other words, the first transmissive region TA1 may not include the pixel electrodes, intermediate layers, and counter electrodes constituting the organic light-emitting elements (OLEDs), as well as the pixel circuits electrically connected thereto. Some of the signal lines PL, DL, SL, and EL connected to supply signals to the auxiliary pixels PXa in the first transmissive region PA1 may cross the first transmissive region TA1. However, even in this case, the signal lines PL, DL, SL, and EL may be arranged to bypass the center of the first transmissive region TA1 to increase the transmittance of the first transmissive region TA1.

[0076] Although not shown, a conductive layer (not shown) may be disposed on the substrate 100 corresponding to the subpixel area PA1 in the first display area DA1. The conductive layer may be disposed below the subpixel PXa, for example, between the thin film transistor of the subpixel PXa and the substrate. The conductive layer may block light emitted from the component 20 from entering the pixel circuit PC (FIG. 5) of the subpixel PXa and prevent it from affecting the pixel circuit PC. A constant voltage or signal may be applied to such a conductive layer to prevent damage to the pixel circuit PC due to electrostatic discharge. A plurality of such conductive layers may be provided in the first display area DA1, and, in some cases, each conductive layer may be supplied with a different voltage.

[0077] The second and third transmission regions TA2 and TA3 are also formed similarly to the first transmission region TA1. That is, the connection pixel PXc may not be arranged in the second and third transmission regions TA2 and TA3. In this case, the meaning of not arranging the connection pixel PXc corresponds to the meaning of not arranging the auxiliary pixel PXa described above, and therefore a detailed description thereof will be omitted.

[0078] 3, each pixel PXm, PXc, and PXa is also electrically connected to an outer circuit arranged in the non-display area NDA, in which a first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power supply line 160, and a second power supply line 170 may be arranged.

[0079] The first scan drive circuit 110 can provide scan signals to each pixel PXm, PXc, and PXa via scan lines SL. The first scan drive circuit 110 can provide light-emitting control signals to each pixel via light-emitting control lines EL. The second scan drive circuit 120 can be arranged parallel to the first scan drive circuit 110, sandwiching the display area DA. Some of the pixels PXm, PXc, and PXa arranged in the display area DA can be electrically connected to the first scan drive circuit 110, and the rest can be connected to the second scan drive circuit 120. In other embodiments, the second scan drive circuit 120 can be omitted.

[0080] The terminal 140 may be disposed on one side of the substrate 100. The terminal 140 is exposed without being covered by an insulating layer and is electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB is also electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits signals or power from a controller (not shown) to the display panel 10. Control signals generated by the controller are transmitted to the first scan driving circuit 110 and the second scan driving circuit 120, respectively, via the printed circuit board PCB. The controller can provide the first power supply ELVDD and the second power supply ELVSS (FIGS. 5 and 6) to the first power supply wiring 160 and the second power supply wiring 170, respectively, via the first connection wiring 161 and the second connection wiring 171. The first power supply voltage ELVDD may be provided to each pixel PXm, PXa via a driving voltage line PL connected to the first power supply wiring 160, and the second power supply voltage ELVSS may be provided to the counter electrode of each pixel PXm, PXa connected to the second power supply wiring 170.

[0081] The data driving circuit 150 is electrically connected to the data lines DL. The data signals of the data driving circuit 150 are also provided to each pixel PXm, PXa via connection wiring 151 connected to the terminal 140 and the data lines DL connected to the connection wiring 151. Although FIG. 3 illustrates the data driving circuit 150 disposed on the printed circuit board PCB, in other embodiments, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power supply wiring 160.

[0082] The first power supply wiring 160 may include a first sub-wiring 162 and a second sub-wiring 163 extending parallel to each other along the x-direction, sandwiching the display area DA. The second power supply wiring 170 has a roof shape with one side open, and may partially surround the display area DA.

[0083] 5 and 6 are equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0084] 5 and 6, each of the pixels PXm, PXc, and PXa includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting element OLED connected to the pixel circuit PC.

[0085] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transmits a data signal Dm input via the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input via the scan line SL.

[0086] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0087] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and controls the driving current flowing from the driving voltage line PL to the organic light emitting element OLED in accordance with the voltage stored in the storage capacitor Cst, so that the organic light emitting element OLED can emit light having a predetermined brightness in response to the driving current.

[0088] Although Fig. 5 illustrates a case in which the pixel circuit PC includes two thin film transistors and one storage capacitor, the present invention is not limited thereto. As shown in Fig. 6, the pixel circuit PC may include seven thin film transistors and one storage capacitor. Although Fig. 6 illustrates a pixel circuit PC including one storage capacitor, the pixel circuit PC may include two or more storage capacitors.

[0089] 6, each pixel PXm, PXc, and PXa includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and storage capacitors. The thin film transistors and storage capacitors may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0090] 6, pixels PXm, PXc, and PXa are shown as being connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL, but the present invention is not limited to this. In another embodiment, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, or the drive voltage line PL may be shared by adjacent pixels.

[0091] The signal lines include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL for transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL for transmitting a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode.

[0092] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the lower driving voltage line PL via the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the main organic light emitting element OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm through the switching operation of the switching thin film transistor T2 and supplies the driving current IOLED to the main organic light emitting element OLED.

[0093] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and to the lower driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on by the scan signal Sn transmitted through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0094] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and to the pixel electrode of the organic light emitting element OLED via the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the drive gate electrode G1 of the drive thin film transistor T1. The compensation thin film transistor T3 is turned on by a scan signal Sn transmitted through the scan line SL to electrically connect the drive gate electrode G1 and the drive drain electrode D1 of the drive thin film transistor T1, making the drive thin film transistor T1 diode-connected.

[0095] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on by the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and transmits the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1 to perform an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

[0096] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emitting control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0097] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting element OLED.

[0098] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on by an emission control signal En transmitted through the emission control line EL, so that the driving voltage ELVDD is transmitted to the main organic light emitting element OLED and a driving current IOLED flows through the organic light emitting element OLED.

[0099] A second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1, a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the main organic light emitting element OLED, and a second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on by a previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the main organic light emitting element OLED.

[0100] 6 illustrates a case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, but the present invention is not limited thereto. In another embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and driven by a previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., a subsequent scan line) and driven by a signal transmitted to the signal line.

[0101] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting element OLED is connected to a common voltage ELVSS, so that the organic light emitting element OLED receives a driving current IOLED from the driving thin film transistor T1 to emit light and display an image.

[0102] Although the compensation thin film transistor T3 and the first initialization thin film transistor T4 are illustrated as having dual gate electrodes in FIG. 6, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0103] 7 is a schematic layout diagram of a pixel circuit of a pixel according to an embodiment of the present invention, and FIG 8 is a cross-sectional view taken along lines II' and II-II' in FIG 7.

[0104] 7 and 8, the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the light-emitting control thin film transistor T6 and the second initialization thin film transistor T7 are arranged along the semiconductor layer 1130.

[0105] The semiconductor layer 1130 is disposed on a substrate on which a buffer layer made of an inorganic insulating material is formed. In this embodiment, the semiconductor layer 1130 may include low temperature polysilicon (LTPS). Polysilicon materials have high electron mobility (100 cm 2 / Vs or more), low energy consumption, and excellent reliability, and therefore may be used as a semiconductor layer of a thin film transistor in a display device. However, the present invention is not limited thereto, and in other embodiments, the semiconductor layer 1130 may be formed of amorphous silicon (a-Si) and / or an oxide semiconductor, and some semiconductor layers of the plurality of thin film transistors may be formed of low temperature polysilicon (LTPS) and other semiconductor layers may be formed of amorphous silicon (a-Si) and / or an oxide semiconductor.

[0106] Some regions of the semiconductor layer 1130 correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 can be understood as being connected to each other and bent into various shapes.

[0107] The semiconductor layer 1130 includes a channel region and source and drain regions on either side of the channel region, which may be understood as the source and drain electrodes of the thin film transistor. Hereinafter, for convenience, the source and drain regions will be referred to as the source and drain electrodes, respectively.

[0108] The driving thin film transistor T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 on both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 has an omega-shaped bent shape, thereby forming a long channel length in a narrow space. When the driving channel region is long, the driving range of the gate voltage is widened, allowing for more precise control of the gray scale of light emitted from the organic light emitting diode OLED, thereby improving display quality.

[0109] The switching thin film transistor T2 includes a switching gate electrode G2 overlapping the switching channel region, a switching source electrode S2 and a switching drain electrode D2 on both sides of the switching channel region, and the switching drain electrode D2 is also connected to the driving source electrode S1.

[0110] The compensation thin film transistor T3 is a dual thin film transistor, and may include a compensation gate electrode G3 overlapping two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 disposed on both sides. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 via a node connection line 1174 described below.

[0111] The first initialization thin film transistor T4 is a dual thin film transistor, and includes a first initialization gate electrode G4 overlapping two first initialization channel regions, and may include a first initialization source electrode S4 and a first initialization drain electrode D4 disposed on both sides.

[0112] The operation control thin film transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S4 and an operation control drain electrode D5 located on both sides thereof. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0113] The light-emitting control thin film transistor T6 may include a light-emitting control gate electrode G6 overlapping the light-emitting control channel region, and a light-emitting control source electrode S6 and a light-emitting control drain electrode D6 located on both sides thereof. The light-emitting control source electrode S6 may be connected to the driving drain electrode D1.

[0114] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 located on both sides thereof.

[0115] The aforementioned thin film transistors may be connected to the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the drive voltage line PL.

[0116] The scan line SL, the previous scan line SL-1, the light emitting control line EL, and the driving gate electrode G1 may be disposed on the semiconductor layer 1130 with an insulating layer sandwiched therebetween.

[0117] The scan line SL also extends in the first direction DR1. A region of the scan line SL corresponds to the switching gate electrode G2 and the compensation gate electrode G3. For example, the regions of the scan line SL overlapping with the channel regions of the switching thin film transistor T2 and the compensation thin film transistor T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0118] The previous scan line SL-1 extends along the first direction DR1, and some regions thereof correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, regions of the previous scan line SL-1 overlapping with the channel regions of the first initialization driving thin film transistor T4 and the second initialization driving thin film transistor T7 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0119] The emission control line EL extends along the first direction DR1. A region of the emission control line EL corresponds to the operation control gate electrode G5 and the emission control gate electrode G6. For example, a region of the emission control line EL overlapping with the channel region of the operation control driving thin film transistor T6 and the emission control driving thin film transistor T7 may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0120] The driving gate electrode G1 is a floating electrode and may be connected to the compensation thin film transistor T3 via the node connection line 1174 described above.

[0121] An electrode voltage line HL may be disposed on the scan line SL, the previous scan line SL-1, the light emission control line EL, and the driving gate electrode G1, with an insulating layer interposed therebetween.

[0122] The electrode voltage line HL may extend along a first direction DR1 to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may serve as a lower electrode CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as an upper electrode CE2 of the storage capacitor Cst.

[0123] The upper electrode CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. Accordingly, the electrode voltage line HL may be connected to the driving voltage line PL disposed above the electrode voltage line HL through a contact hole CNT. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL may have a constant voltage of +5V. The electrode voltage line HL may be understood as a lateral driving voltage line.

[0124] The driving voltage lines PL extend along the second direction DR2, and the electrode voltage lines HL electrically connected to the driving voltage lines PL extend along the first direction DR1 that intersects with the second direction DR2, so that in the display area, the multiple driving voltage lines PL and the electrode voltage lines HL can form a mesh structure.

[0125] A data line DL, a driving voltage line PL, an initialization connection line 1173, and a node connection line 1174 may be arranged on the electrode voltage line HL with an insulating layer sandwiched therebetween.

[0126] The data line DL may extend in the second direction DR2 and be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode.

[0127] The driving voltage line PL extends in the second direction DR2 and is connected to the electrode voltage line HL through the contact hole CNT as described above. It may also be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL is also connected to the operation control drain electrode D5 through the contact hole 1155.

[0128] One end of the initialization connection line 1173 may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through a contact hole 1152, and the other end may be connected to the initialization voltage line VL described later through a contact hole 1151.

[0129] One end of the node connection line 1174 is connected to the compensation drain electrode D3 through a contact hole 1156, and the other end is connected to the drive gate electrode G1 through a contact hole 1157.

[0130] An initialization voltage line VL may be disposed above the data line DL, the drive voltage line PL, the initialization connection line 1173, and the node connection line 1174 with an insulating layer sandwiched therebetween.

[0131] The initialization voltage line VL extends in the first direction DR1. The initialization voltage line VL may be connected to the first initialization driving thin film transistor T4 and the second initialization driving thin film transistor T7 via an initialization connection line 1173. The initialization voltage line VL may have a constant voltage (e.g., −2V).

[0132] The initialization voltage line VL may be disposed on the same layer as the pixel electrode 210 of the organic light-emitting diode OLED (FIG. 8) and may contain the same material. The pixel electrode 210 may be connected to the emission control thin film transistor T6. The pixel electrode 210 is connected to a connection metal 1175 via a contact hole 1163, and the connection metal 1175 is connected to the emission control drain electrode D6 via a contact hole 1153.

[0133] In FIG. 7, the initialization voltage line VL is described as being arranged on the same layer as the pixel electrode 210, but in other embodiments, the initialization voltage line VL may be arranged on the same layer as the electrode voltage line HL.

[0134] Hereinafter, a stacked structure included in a display panel according to an embodiment of the present invention will be described with reference to FIG.

[0135] The substrate 100 may comprise glass or a polymeric resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing the aforementioned polymeric resin and an inorganic layer (not shown).

[0136] The buffer layer 111 is located on the substrate 100 and can reduce or block penetration of foreign substances, moisture, or external air from underneath the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite, and may have a single-layer structure or a multi-layer structure of inorganic and organic materials. A barrier layer (not shown) that blocks penetration of external air may further be included between the substrate 100 and the buffer layer 111.

[0137] Gate electrodes G1 and G6 are disposed on the semiconductor layers A1 and A6, sandwiching a first gate insulating layer 112. The gate electrodes G1 and G6 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers. For example, the gate electrodes G1 and G6 may be a single layer of Mo. The scan lines SL (FIG. 7), previous scan lines SL-1, and emission control lines EL may be formed in the same layer as the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, scan lines SL (FIG. 7), previous scan lines SL-1, and emission control lines EL may be disposed on the first gate insulating layer 112.

[0138] The first gate insulating layer 112 is made of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0139] A second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0140] The lower electrode CE1 of the storage capacitor Cst may be integrally formed with the gate electrode G1 of the driving thin film transistor T1, for example, the gate electrode G1 of the driving thin film transistor T1 may perform the function of the lower electrode CE1 of the storage capacitor Cst.

[0141] The upper electrode CE2 of the storage capacitor Cst overlaps the lower electrode CE1, sandwiching the second gate insulating layer 113. In this case, the second gate insulating layer 113 can function as a dielectric layer of the storage capacitor Cst. The upper electrode CE2 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayer including the above materials. For example, the upper electrode CE2 may be a single layer of Mo or a multilayer of Mo / Al / Mo.

[0142] In the drawings, the storage capacitor Cst is illustrated overlapping the driving thin film transistor T1, but the present invention is not limited thereto. Various modifications are possible, such as the storage capacitor Cst may be arranged so as not to overlap the driving thin film transistor T1.

[0143] The upper electrode CE2 can function as an electrode voltage line HL. For example, a part of the electrode voltage line HL may become the upper electrode CE2 of the storage capacitor Cst.

[0144] An interlayer insulating layer 115 may be provided to cover the upper electrode CE2. The interlayer insulating layer 115 may be made of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). Although interlayer insulating layer 115 is illustrated as being a single layer in FIG. 8, in one embodiment, interlayer insulating layer 115 may be formed as a multi-layer structure.

[0145] The data lines DL, the driving voltage lines PL, and the connection metal 1175 may be disposed on the interlayer insulating layer 115. The data lines DL, the driving voltage lines PL, and the connection metal 1175 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayer containing the above materials. For example, the data lines DL, the driving voltage lines PL, and the connection metal 1175 may have a Ti / Al / Ti multilayer structure.

[0146] The upper electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL through a contact hole CNT defined in the interlayer insulating layer 115. This means that the electrode voltage line HL is connected to the driving voltage line PL through the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL.

[0147] The connection metal 1175 is connected to the semiconductor layer A6 of the emission control thin film transistor T6 via a contact hole 1153 that penetrates the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED via the connection metal 1175.

[0148] A planarization layer 117 is disposed on the data lines DL, the driving voltage lines PL, and the connection metal 1175, and an organic light emitting diode OLED can be disposed on the planarization layer 117.

[0149] The planarization layer 117 may have a flat upper surface so that the pixel electrode 210 is formed flat. The planarization layer 117 may be formed of a single layer or multiple layers of an organic material film. The planarization layer 117 may include a general-purpose polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene polymer, a vinyl alcohol polymer, or a blend thereof. The planarization layer 117 may include an inorganic material. Examples of such a planarization layer 117 include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), etc. If the planarization layer 117 is made of an inorganic material, chemical planarization polishing may be performed. On the other hand, the planarization layer 117 may include both organic and inorganic materials.

[0150] The pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may have an ITO / Ag / ITO stacked structure.

[0151] A pixel defining layer 119 may be disposed on the planarization layer 117. The pixel defining layer 119 has an opening 119OP that exposes a center portion of the pixel electrode 310, thereby defining a light-emitting region of the pixel. The pixel defining layer 119 also increases the distance between the edge of the pixel electrode 310 and the counter electrode 230 above the pixel electrode 210, thereby preventing arcing or the like from occurring at the edge of the pixel electrode 210. The pixel defining layer 119 is made of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin, and may be formed by a method such as spin coating.

[0152] The intermediate layer 220 of the organic light-emitting diode OLED may include an organic light-emitting layer. The organic light-emitting layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally disposed above and below the organic light-emitting layer. The intermediate layer 220 may be disposed corresponding to each of the plurality of pixel electrodes 210. However, the present invention is not limited thereto. Various modifications are possible for the intermediate layer 220, such as including a layer that is integral across the plurality of pixel electrodes 210.

[0153] The counter electrode 230 may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may be formed of a thin metal film with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof. A transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, may be further disposed on the thin metal film.

[0154] When the pixel electrode 210, the reflective electrode, and the counter electrode 230 are formed of translucent electrodes, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device can also be a top-emitting type. When the pixel electrode 210 is formed of a transparent or semi-transparent electrode and the counter electrode 230 is formed of a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device can also be a bottom-emitting type. However, this embodiment is not limited thereto. The display device of this embodiment can also be a double-sided emitting type that emits light in both the front and back directions.

[0155] In this embodiment, the counter electrode 230 may be provided in the auxiliary pixel PXa located in the first display area DA1. However, the first display area DA1 includes the auxiliary pixel area PA1 where the auxiliary pixel PXa is located and the first transmissive area TA1, but a portion of the counter electrode 230 is not provided in a region corresponding to the first transmissive area TA1. In a top-emission type display device, light is emitted toward the counter electrode 230, but the transmittance is partially reduced by the counter electrode 230. Therefore, by not providing the counter electrode 230 in the region corresponding to the first transmissive area TA1, the transmittance of the first transmissive area TA1 can be improved.

[0156] To this end, the counter electrode 230 disposed in the first display area DA1 may be patterned for each auxiliary pixel area PA1. The counter electrode 230 disposed in the first display area DA1 may be formed by removing a portion of the first transmissive area TA1 using laser lift-off, or may be formed using fine metal mask (FMM) patterning. In the following description of the present embodiment, it is assumed that the counter electrode 230 is formed in the first display area DA1 using FMM patterning.

[0157] The counter electrode 230 may be provided in the connection pixel PXc located in the second display area DA2. However, the second display area DA2 includes the connection pixel area PA2 where the connection pixel PXc is located, the second transmissive area TA2, and the third transmissive area TA3, but a portion of the counter electrode 230 is not provided in the areas corresponding to the second transmissive area TA2 and the third transmissive area TA3. Here, in the case of a top-emitting display device, light is emitted toward the counter electrode 230, but it goes without saying that the transmittance is partially reduced by the counter electrode 230. Therefore, by not providing the counter electrode 230 in the areas corresponding to the second transmissive area TA2 and the third transmissive area TA3, the transmittance of the second transmissive area TA2 and the third transmissive area TA3 can be improved.

[0158] To this end, the counter electrode 230 disposed in the second display area DA2 may be patterned for each connection pixel area PA2. The counter electrode 230 disposed in the second display area DA2 may be formed by removing a portion of the area corresponding to the second transmissive area TA2 and the third transmissive area TA3 using laser lift-off, or may be formed using FMM patterning. In the following description of the present embodiment, it is assumed that the counter electrode 230 is formed in the second display area DA1 using FMM patterning.

[0159] The counter electrode 230 is disposed over the entire third display area DA3, and a portion of its edge may be located in the non-display area NDA. The counter electrode 230 is integrally formed with the main pixels PXm, i.e., the plurality of organic light emitting diodes OLED, located in the third display area DA3, and corresponds to the plurality of pixel electrodes 210.

[0160] 9 and 10 are plan views showing a portion of a first display area according to an embodiment of the present invention.

[0161] 9 and 10, as described above, the first display area DA1 includes the auxiliary pixel area PA1 and the first transmissive area TA1, and the auxiliary pixels PXa are arranged in the auxiliary pixel area PA1. The auxiliary pixel area PA1 includes the first pixel area PA1-1 and the second pixel area PA1-2, as shown in FIG. 9, and the first pixel area PA1-1 includes a plurality of first pixels PXa1, and the second pixel area PA1-2 includes a plurality of second pixels PXa2.

[0162] In this embodiment, a first opposing electrode 230a is provided on the first pixel region PA1-1, and a second opposing electrode 230b is provided on the second pixel region PA1-2. The first opposing electrode 230a may be disposed corresponding to the first pixel region PA1-1, and the second opposing electrode 230b may be disposed corresponding to the second pixel region PA1-2. The first opposing electrode 230a and the second opposing electrode 230b may contact each other in a partial area. In this case, the shapes of the first opposing electrode 230a and the second opposing electrode 230b may be the same.

[0163] 10, a plurality of first pixels PXa1 are disposed on the first pixel region PA1-1. Each of the first pixels PXa1 includes a scan line to which a scan signal is supplied and a data line to which a data signal is supplied. The scan lines extend along a first direction DR1, and the data lines extend along a second direction DR2 that intersects with, for example, orthogonal to, the first direction DR1. It goes without saying that other signal lines PL, EL, SL-1, and VL (FIG. 7) are also provided on the first pixel region PA1-1.

[0164] Portions of the data lines and scan lines may be located above the first transmissive region TA1. Even in this case, for example, the scan lines may have a detour region around the edge of the first transmissive region TA1 to improve the transmittance of the first transmissive region TA1. Such detour regions are also applied to the other signal lines PL, EL, SL-1, and VL (FIG. 7).

[0165] The plurality of first pixels PXa1 arranged on the first pixel region PA1-1 may include a first counter electrode 230a integrally formed on one first pixel region PA1-1.

[0166] The plurality of second pixels PXa2 arranged on the second pixel region PA1-2 may include a second counter electrode 230b integrally formed on one second pixel region PA1-2.

[0167] The first pixel region PA1-1 and the second pixel region PA1-2 may be arranged on different lines. In this case, the first pixel region PA1-1 and the second pixel region PA1-2 may be arranged to surround the first transmission region TA1. That is, the first pixel region PA1-1 and the second pixel region PA1-2 may be arranged in a zigzag pattern.

[0168] The first opposing electrode 230a and the second opposing electrode 230b are disposed corresponding to the first pixel region PA1-1 and the second pixel region PA1-2, respectively, and are in contact with each other in a partial region. The first opposing electrode 230a and the second opposing electrode 230b may have a first contact region CTA1 where they are in contact with each other in a region where the first pixel region PA1-1 and the second pixel region PA1-2 are adjacent to each other, and may be electrically connected to each other via the first contact region CTA1.

[0169] In the above-mentioned case, the first opposing electrode 230a and the second opposing electrode 230b are connected to each other via the first contact area CTA1, thereby improving the resistance increase in the opposing electrodes 230a, 230b arranged on the first display area DA1.

[0170] 11 and 12 are cross-sectional views schematically illustrating a part of a manufacturing process of a display panel according to an embodiment of the present invention, and Fig. 13 is a cross-sectional view schematically illustrating a cross section taken along line BB' in Fig. 9.

[0171] 11 to 13, an insulating layer IL in which a pixel circuit PC is located is formed on a substrate 100, and a first pixel electrode 210a and a second pixel electrode 210b electrically connected to the pixel circuit PC are formed on the insulating layer IL. The first pixel electrode 210a is disposed on a first pixel region PA1-1, and the second pixel electrode 210b is disposed on a second pixel region PA1-2.

[0172] A pixel defining layer 119 having openings exposing central portions of the first and second pixel electrodes 210a and 210b is formed on the first pixel electrode 210a and the second pixel electrode 210b, respectively. A first intermediate layer 220a is formed on the first pixel electrode 210a exposed through the openings in the pixel defining layer 119, and a second intermediate layer 220b is formed on the second pixel electrode 210b. The first intermediate layer 220a and the second intermediate layer 220b may be understood to be made of the same material as the intermediate layer 220 described in FIG. 8.

[0173] Thereafter, a first opposing electrode 230a and a second opposing electrode 230b may be formed on the first intermediate layer 220a and the second intermediate layer 220b. In this embodiment, the first opposing electrode 230a and the second opposing electrode 230b may be formed through different processes. In this case, the first mask sheet 422A of the same first mask assembly (described later) may be used to form the first opposing electrode 230a and the second opposing electrode 230b. That is, after forming the first opposing electrode 230a, at least one of the first mask assembly and the substrate 100 may be moved to a position different from its initial position, and then the second opposing electrode 230b may be formed on the substrate 100. In another embodiment, after forming the second opposing electrode 230b, at least one of the mask assembly and the substrate 100 may be moved to a position different from its initial position, and then the first opposing electrode 230a may be formed on the substrate 100. For the sake of convenience, the following description will be focused on the case where the position of the substrate 100 is moved after the first opposing electrode 230a is formed, and the second opposing electrode 230b is formed.

[0174] Specifically, as shown in Fig. 11, a first opposing electrode 230a is formed on a first intermediate layer 220a. The first opposing electrode 230a may be formed by depositing a deposition material that has passed through a first opening 422A-1 in a first mask sheet 422A onto the substrate 100. Thereafter, as shown in Fig. 12, the substrate 100 is moved to the left in Fig. 11, and a second opposing electrode 230b is formed on a second intermediate layer 220b. The second opposing electrode 230b may be manufactured through the first opening 422A-1 in the first mask sheet 422A.

[0175] 13, the first opposing electrode 230a and the second opposing electrode 230b formed as described above are in surface contact with each other in the first contact region CTA1. The surface contact between the first opposing electrode 230a and the second opposing electrode 230b does not mean that any layer is interposed between the first opposing electrode 230a and the second opposing electrode 230b, but rather that the second opposing electrode 230b is stacked on the first opposing electrode 230a, resulting in contact with each other.

[0176] In the first contact region CTA1, the second opposing electrode 230b is disposed on the first opposing electrode 230a. This means that the second opposing electrode 230b is formed in a process later than the first opposing electrode 230a. As another embodiment, if the second opposing electrode 230b is formed in a process later than the first opposing electrode 230a, the first opposing electrode 230a may be disposed on the second opposing electrode 230b in the first contact region CTA1. The first contact region CTA1 may be formed to a thickness approximately twice or less than that of a region in which only the first opposing electrode 230a or the second opposing electrode 230b is disposed, due to the surface contact between the first opposing electrode 230a and the second opposing electrode 230b. Furthermore, it is desirable that the first contact region CTA1 not be disposed on the light-emitting regions of the first pixel PXa1 and the second pixel PXa2. In this case, the “light-emitting regions” of the first and second pixels may be defined as a first opening OP1 and a second opening OP2 that are formed in the pixel defining layer 119 and expose central portions of the first and second pixel electrodes 210a and 210b, respectively. That is, the first contact region CTA1 may be provided so as not to overlap the first opening OP1 and the second opening OP2 formed in the pixel defining layer 119.

[0177] The larger the area of ​​the first contact region CTA1, the lower the resistance of the first opposing electrode 230a and the second opposing electrode 230b. However, as mentioned above, if the area of ​​the first contact region CTA1 is made larger than a certain amount, it will overlap with the light-emitting regions of the pixels PXa1 and PXa2, which will cause a decrease in the light-emitting quality of the pixels PXa1 and PXa2.

[0178] Therefore, the area of ​​the first contact region CTA1 may be formed to such an extent that it does not block the first opening OP1 and the second opening OP2.

[0179] 11 and 13, the first transmissive region TA1 does not include a display element such as an organic light emitting element (OLED) and a pixel circuit PC electrically connected thereto, unlike the first pixel region PA1-1. Furthermore, such a first transmissive region TA1 may be defined as a region in which a portion of a layer disposed on the substrate 100 is removed.

[0180] Fig. 14 is a plan view showing the arrangement of counter electrodes of a display panel according to an embodiment of the present invention. Fig. 15 is a cross-sectional view schematically showing a cross section taken along line CC' in Fig. 14. Fig. 16 is a cross-sectional view schematically showing a cross section taken along line DD' in Fig. 14.

[0181] 14 to 16, as described above, the first display area DA1 may include a first pixel area PA1-1, a second pixel area PA1-2, and a first transmission area TA1. In this case, a first counter electrode 230a may be arranged in the first pixel area PA1-1, and a second counter electrode 230b may be arranged in the second pixel area PA1-2.

[0182] The second display area DA2 may include a third pixel area PA2-1, a fourth pixel area PA2-2, a second transmission area TA2, and a third transmission area TA3. In this case, a third opposing electrode 230c may be arranged in the third pixel area PA2-1, and a fourth opposing electrode 230d may be arranged in the fourth pixel area PA2-2.

[0183] In the above case, the third opposing electrode 230c and the fourth opposing electrode 230d may have different shapes. For example, the third opposing electrode 230c may be the same as the first opposing electrode 230a or the second opposing electrode 230b, and the fourth opposing electrode 230d may not be the same as the third opposing electrode 230c. In particular, the third opposing electrode 230c may be square, and the fourth opposing electrode 230d may be rectangular. Furthermore, the fourth opposing electrode 230d may be the same as or larger than at least two or more third opposing electrodes 230c connected together.

[0184] The third display area DA3 may include a main pixel area PA3, and a main counter electrode 230e may be disposed in the main pixel area PA3.

[0185] In the above case, the third opposing electrode 230c and the fourth opposing electrode 230d may be formed simultaneously when the main opposing electrode 230e is formed.

[0186] A plurality of third opposing electrodes 230c and a plurality of fourth opposing electrodes 230d may be provided. The plurality of third opposing electrodes 230c may be arranged to be spaced apart from one another. Furthermore, the plurality of fourth opposing electrodes 230d may be arranged to be spaced apart from one another. In such a case, the plurality of third opposing electrodes 230c and the plurality of fourth opposing electrodes 230d may be arranged in a line in the X direction of FIG. 14. Furthermore, each of the third opposing electrodes 230c and each of the fourth opposing electrodes 230d may be arranged in the Y direction of FIG. 14 and connected to one another.

[0187] The third opposing electrode 230c may be connected to the first opposing electrode 230a or the second opposing electrode 230b. In this case, the third opposing electrode 230c may include a second contact region CTA2 overlapping the first opposing electrode 230a or the second opposing electrode 230b. In such a case, the third opposing electrode 230c is in surface contact with the first opposing electrode 230a or the second opposing electrode 230b in the second contact region CTA2. In addition, the third opposing electrode 230c may be disposed above the first opposing electrode 230a or the second opposing electrode 230b in the second contact region CTA2, or the third opposing electrode 230c may be disposed below the first opposing electrode 230a or the second opposing electrode 230b. For convenience of explanation, the following detailed description will focus on the case where the third opposing electrode 230c is disposed above the second opposing electrode 230b in the second contact region CTA2.

[0188] In the above case, the thickness of the second contact region CTA2 may be thicker than the thickness of the second opposing electrode 230b or the third opposing electrode 230c. For example, the thickness of the second contact region CTA2 may be approximately twice the thickness of the second opposing electrode 230b or the third opposing electrode 230c.

[0189] In the above case, the third opposing electrode 230c and the fourth opposing electrode 230d connected to each other may include a third contact region CTA3 that overlaps each other. In this case, the thickness of the third contact region CTA3 is the same as or similar to the thickness of either the third opposing electrode 230c or the fourth opposing electrode 230d, as described above. That is, since the third opposing electrode 230c and the fourth opposing electrode 230d are simultaneously formed in the third contact region CTA3, one of the third opposing electrode 230c or the fourth opposing electrode 230d directly contacts the top surface of the other of the third opposing electrode 230c or the fourth opposing electrode 230d. In this case, the third opposing electrode 230c and the fourth opposing electrode 230d are in surface contact with each other. For convenience of explanation, the following detailed description will focus on the case where the fourth opposing electrode 230d is disposed on the third opposing electrode 230c, as shown in FIG. 15.

[0190] The fourth opposing electrode 230d is also connected to the main opposing electrode 230e. In this case, a portion of the fourth opposing electrode 230d and the main opposing electrode 230e may be spaced apart, and another portion may be directly connected to the main opposing electrode 230e. In this case, the fourth opposing electrode 230d may be formed in a "T" shape and connected to the main opposing electrode 230e. That is, a portion of the fourth opposing electrode 230d may be formed to protrude toward the main opposing electrode 230e, and another portion of the fourth opposing electrode 230d may protrude in a direction perpendicular to the portion of the fourth opposing electrode 230d.

[0191] A second transmissive region TA2 may be disposed between the first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c as described above. In this case, the second transmissive region TA2 may have the same shape and size as the first transmissive region TA1.

[0192] A third transmissive region TA3 may be disposed between one of the first opposing electrode 230a or the second opposing electrode 230b, the third opposing electrode 230c, and the fourth opposing electrode 230d. In this case, the third transmissive region TA3 may have a different shape from the second transmissive region TA2.

[0193] At least one pixel may be arranged in each of the first pixel region PA1-1, second pixel region PA1-2, third pixel region PA2-1, and fourth pixel region PA2-2 described above. For example, a first pixel PXa1 may be arranged in the first pixel region PA1-1, and a second pixel PXa2 may be arranged in the second pixel region PA1-2. A third pixel PXc1 may be arranged in the third pixel region PA2-1, and a fourth pixel PXc2 may be arranged in the fourth pixel region PA2-2. A main pixel PXm may be arranged in the main pixel region PA3. Such pixels may be the same as or similar to those described above.

[0194] Fig. 17 is a cross-sectional view schematically showing an apparatus for manufacturing a display device according to an embodiment of the present invention. Fig. 18 is a perspective view showing a first mask assembly shown in Fig. 17. Fig. 19 is a plan view showing a portion of an embodiment of a first mask sheet shown in Fig. 17. Fig. 20 is a plan view showing a portion of an embodiment of a second mask sheet shown in Fig. 17.

[0195] 17 to 20, the display panel (not shown) of the display device 1 may be manufactured by a manufacturing apparatus 400 for the display device.

[0196] The display device manufacturing apparatus 400 may include a chamber 410, a first mask assembly 420A, a second mask assembly 420B, a first support unit 430, a second support unit 440, a deposition source 450, a magnetic force generating unit 460, a vision unit 470, and a pressure adjusting unit 480.

[0197] The chamber 410 may have an internal space, and a portion of the chamber 410 may be formed to be open. In this case, a gate valve 411 may be disposed in the open portion of the chamber 410 so as to be openable and closable.

[0198] The first mask assembly 420A may be selectively disposed inside the chamber 410. In this case, the first mask assembly 420A may include a first mask frame 421A and a first mask sheet 422A. The first mask frame 421A may be formed by connecting a plurality of frames together and may include an opening therein. In this case, the first mask frame 421A may include one opening or may include a plurality of first openings 422A-1 that are separated from one another. In this case, the first mask frame 421A may be formed in a lattice shape like a window frame. The first mask sheet 422A may be fixed in a tensioned state to the first mask frame 421A. In this case, the first mask sheet 422A may have a first opening disposed therein so that the deposition material can pass through.

[0199] The first mask sheet 422A may include a first opening 422A-1 through which the deposition material passes to form the aforementioned first counter electrode (not shown) or second counter electrode (not shown).

[0200] The shape of the first opening 422A-1 may be formed to correspond to the first pixel region PA1-1 or the second pixel region PA1-2. For example, the shape of the first opening 422A-1 may include a rectangle, a square, or a diamond. In this case, the deposition material passing through the first opening 422A-1 may be deposited on the substrate 100 to form a first counter electrode or a second counter electrode. In this case, if a plurality of first openings 422A-1 are provided, the plurality of first openings 422A-1 may be arranged sufficiently spaced apart so that the deposition material passing through each first opening 422A-1 is not connected to each other after being deposited on the substrate 100.

[0201] The first opening 422A-1 as described above may be arranged to form a counter electrode in a region corresponding to the first display region DA1 of the substrate 100. In particular, the first opening 422A-1 may be arranged only in the first region AR1-1 of the first mask sheet 422A. In such a case, a separate opening may not be arranged in the second region AR1-2 of the first mask sheet 422A. In particular, the first region AR1-1 corresponds to the first display region DA1 of the substrate 100, and the second region AR1-2 corresponds to the second display region DA2 and the third display region DA3 of the substrate 100.

[0202] 17, the second mask assembly 420B may be replaced with the first mask assembly 420A. That is, the second mask assembly 420B may be used to form the third counter electrode (not shown), the fourth counter electrode (not shown), and the main counter electrode (not shown) in the second display area DA2 and the third display area DA3 after the first and second counter electrodes are formed in the first display area DA1 using the first mask assembly 420A.

[0203] The second mask assembly 420B may include a second mask frame 421B and a second mask sheet 422B. Since the second mask frame 421B is the same as or similar to the first mask frame 421A, a detailed description thereof will be omitted.

[0204] As shown in FIG. 20, the second mask sheet 422B may include a second opening 422B-1, a third opening 422B-2, and a fourth opening 422B-3 that form the third counter electrode, the fourth counter electrode, and the main counter electrode described above.

[0205] In the above case, the second opening 422B-1 may have substantially the same shape as the first opening 422A-1. The third opening 422B-2 may be formed to be different from the second opening 422B-1. For example, the third opening 422B-2 may be formed larger than the second opening 422B-1. In such a case, the third opening 422B-2 may be formed to correspond to at least two or more of the second openings 422B-1. The second openings 422B-1 may be arranged to be separated from the third openings 422B-2. In this case, the first width W1 of the second mask sheet 422B arranged between the second opening 422B-1 and the third opening 422B-2 is formed to be very narrow, so that the deposition materials deposited through the second opening 422B-1 and the third opening 422B-2 are connected to each other even on the substrate 100.

[0206] The fourth opening 422B-3 may be connected to the third opening 422B-2. In this case, the second width W2 of the second mask sheet 422B disposed between the fourth opening 422B-3 and the third opening 422B-2 may be wider than the first width W1, so that only a portion of the fourth counter electrode is connected to the main counter electrode. In such a case, the portions of the second mask sheet 422B disposed between the second opening 422B-1 and the third opening 422B-2 and between the third opening 422B-2 and the fourth opening 422B-3 can ensure a certain degree of strength of the second mask sheet 422B when the second mask sheet 422B is pulled.

[0207] The second opening 422B-1 to fourth opening 422B-3 as described above may be arranged in the third region AR2-1 of the second mask sheet 422B corresponding to the second region AR1-2 of the first mask sheet 422A. On the other hand, no separate opening may be formed in the fourth region AR2-2 of the second mask sheet 422B corresponding to the first region AR1-1 of the first mask sheet 422A.

[0208] The substrate 100 is placed on the first support part 430. At this time, the first support part 430 can adjust the position of the substrate 100. For example, the first support part 430 may include a UVW stage.

[0209] The first mask assembly 420A or the second mask assembly 420B is placed on the second support part 440. In this case, the second support part 440 is similar to the first support part 430 and is capable of adjusting the position of the first mask assembly 420A or the second mask assembly 420B.

[0210] The deposition source 450 may store a deposition material, vaporize the deposition material, or sublimate the deposition material, and supply the vaporized deposition material to the chamber 410. The deposition source 450 may include a heater therein, and the heater may be operated to heat the deposition material inside the deposition source 450, thereby melting or sublimating the deposition material. In this case, the deposition source 450 may be disposed in the center or a corner of the chamber 410. For convenience of explanation, the following description will be focused on the case where the deposition source 450 is disposed in a corner of the chamber 410.

[0211] The magnetic force generator 460 is disposed in the chamber 410 and can bring the substrate 100 and the first mask assembly 420A or the substrate 100 and the second mask assembly 420B into close contact with each other. In this case, the magnetic force generator 460 may include an electromagnet or a permanent magnet that generates a magnetic force.

[0212] The vision unit 470 is disposed in the chamber 410 and can photograph the positions of the first mask assembly 420A and the substrate 100, or the positions of the second mask assembly 420B and the substrate 100. At this time, the vision unit 470 can photograph an alignment mark of at least one of the first mask assembly 420A, the second mask assembly 420B, and the substrate 100.

[0213] The pressure adjusting unit 480 is connected to the chamber 410 and can adjust the internal pressure of the chamber 410. In this case, the pressure adjusting unit 480 may include a connecting pipe 481 connected to the chamber 410 and a pump 482 disposed in the connecting pipe 481.

[0214] The display device 1 can be manufactured by the display device manufacturing apparatus 400. In this case, the display device manufacturing apparatus 400 can manufacture the display device 1 according to not only the above-described embodiment but also the embodiments described below. However, for the sake of convenience, the following detailed description will focus on the case where the display device manufacturing apparatus 400 manufactures a pixel region of a display panel (not shown) shown in FIG. 14. In the following, the same reference numerals as those in FIG. 14 indicate the same components.

[0215] Specifically, the substrate 100 on which an insulating layer (not shown) is formed and the first mask assembly 420A may be placed inside the chamber 410. At this time, a pixel electrode (not shown) and an organic light-emitting layer (not shown) may be formed in the thin film transistor (not shown) and the organic light-emitting element (not shown).

[0216] After the substrate 100 and the first mask assembly 420A are placed on the first support part 430 and the second support part 440, respectively, the substrate 100 and the first mask assembly 420A can be photographed through the vision part 470. Thereafter, the substrate 100 and the first mask assembly 420A can be aligned.

[0217] When the deposition source 450 is activated to supply a deposition material, the deposition material may pass through the first openings 422A-1 of the first mask sheet 422A and be deposited on the organic light-emitting layer and pixel defining layer of the substrate 100. In this case, the deposition material passing through the first openings 422A-1 may form the first opposing electrode 230a or the second opposing electrode 230b, as described above. For convenience of explanation, the following detailed description will focus on the case of forming the first opposing electrode 230a.

[0218] When deposited as described above, the first counter electrodes 230a may be arranged in a single row, or multiple rows may be provided and spaced apart from one another.

[0219] Once the above process is completed, the position of at least one of the substrate 100 and the first mask assembly 420A can be changed. For example, the position of the substrate 100 can be changed after the position of the first mask assembly 420A is fixed. In another embodiment, the position of the substrate 100 can be fixed and then the position of the first mask assembly 420A can be changed. In yet another embodiment, the positions of both the substrate 100 and the first mask assembly 420A can be changed. For convenience of explanation, the following description will focus on the case where the position of the first mask assembly 420A is fixed and then the position of the substrate 100 is changed.

[0220] When the position of the substrate 100 is variable, the first opening 422A may be disposed so as to correspond to a portion of the substrate 100 where the first opposing electrode 230a is not formed. That is, the first opening 422A-1 may be disposed between adjacent first opposing electrodes 230a.

[0221] After the position of the substrate 100 is changed, when a deposition material is supplied from the deposition source 450, the deposition material passes through the first opening 422A-1 and is also deposited on the substrate 100. At this time, the deposition material that has passed through the first opening 422A-1 is deposited on the substrate 100 to form the second opposing electrode 230b. The second opposing electrode 230b may be disposed between the first opposing electrodes 230a and connected via the first contact region CTA1.

[0222] After the above process is completed, the operation of the deposition source 450 is stopped or the deposition material is prevented from being supplied from the deposition source 450, and the pressure inside the chamber 410 can be maintained at atmospheric pressure through the pressure adjusting unit 480.

[0223] After opening the gate valve 411, the first mask assembly 420A can be drawn out from inside the chamber 410, and the second mask assembly 420B can be supplied from outside the chamber 410 to inside the chamber 410. When the second mask assembly 420B is placed on the second support part 440, the second mask assembly 420B and the substrate 100 can be aligned. In addition, the pressure adjusting part 480 can maintain the pressure inside the chamber 410 at a nearly vacuum state. The deposition source 450 can supply a deposition material to the substrate 100 to form the third opposing electrode 230c, the fourth opposing electrode 230d, and the main opposing electrode 230e on the substrate 100.

[0224] Specifically, when the third opposing electrode 230c is formed on the substrate 100, the third opposing electrode 230c may be connected to one of the first opposing electrode 230a or the second opposing electrode 230b. Specifically, when the third opposing electrode 230c is formed, a second contact region CTA2 is formed between the third opposing electrode 230c and one of the first opposing electrode 230a or the second opposing electrode 230b. In this case, in the second contact region CTA2, the third opposing electrode 230c may be disposed on the upper surface of one of the first opposing electrode 230a or the second opposing electrode 230b. In another embodiment, when the third opposing electrode 230c, the fourth opposing electrode 230d, and the main opposing electrode 230e are first formed on the substrate 100, and the first opposing electrode 230a and the second opposing electrode 230b are sequentially formed, one of the first opposing electrode 230a or the second opposing electrode 230b may be disposed on the upper surface of the third opposing electrode 230c.

[0225] As described above, when the third opposing electrode 230c and the fourth opposing electrode 230d are formed, the first width W1 of the second mask sheet 422B between the second opening 422B-1 and the third opening 422B-2 is sufficiently narrow, so that the third opposing electrode 230c and the fourth opposing electrode 230d formed on the substrate 100 may be overlapped and connected to each other.

[0226] Therefore, the counter electrodes disposed on the substrate 100 may be connected to each other via the respective contact regions.

[0227] Furthermore, the display device manufacturing apparatus 400 can prevent the pixels in each display area from not emitting light by connecting the counter electrodes arranged in the display area DA to each other.

[0228] 21 is a plan view showing the arrangement of counter electrodes of a display panel according to another embodiment of the present invention, and FIG 22 is a plan view showing a portion of another embodiment of the second mask sheet shown in FIG 17.

[0229] 21 and 22, the display device 1 is similar to that described with reference to FIGS. 1 to 14. For ease of explanation, the following description will focus on differences from the arrangement of the counter electrodes shown in FIG. 14.

[0230] The first opposing electrode 230a, the second opposing electrode 230b, the third opposing electrode 230c, and the fourth opposing electrode 230d may be the same as those described above with reference to FIG. 14. A plurality of main opposing electrodes 230e may be provided spaced apart from one another. In this case, the plurality of main opposing electrodes 230e may be arranged in the Y direction of FIG. 21. In such a case, the main opposing electrodes 230e may not be connected to one another, and one of the plurality of main opposing electrodes 230e may be connected to the plurality of fourth opposing electrodes 230d. In this case, each main opposing electrode 230e may be connected to each wiring arranged on the side of the substrate 100.

[0231] To form the main counter electrode 230e as described above, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from one another. A plurality of fourth openings 422B-3 may be provided, and the plurality of fourth openings 422B-3 may be arranged in one direction and spaced apart from one another. To separate adjacent fourth openings 422B-3, the second mask sheet 422B is partially disposed between the adjacent fourth openings 422B-3.

[0232] In the above case, the deposition material passing through the fourth opening 422B-3 can form the main opposing electrode 230e in the third display area DA3, and as described above, the deposition material passing through different fourth openings 422B-3 can be deposited in different regions of the substrate 100 to form different main opposing electrodes 230e.

[0233] 23 is a plan view showing the arrangement of counter electrodes of a display panel according to another embodiment of the present invention, and FIG. 24 is a plan view showing a portion of another embodiment of the second mask sheet shown in FIG.

[0234] 23 and 24, the display device 1 is similar to that described with reference to FIGS. 1 to 14. For ease of explanation, the following description will focus on differences from the arrangement of the counter electrodes shown in FIG. 14.

[0235] The first opposing electrode 230a, the second opposing electrode 230b, the third opposing electrode 230c, and the fourth opposing electrode 230d may be the same as those described above with reference to FIG. 14. A plurality of main opposing electrodes 230e may be provided, spaced apart from one another. In this case, the plurality of main opposing electrodes 230e may be arranged in the Y direction of FIG. 23. In particular, two main opposing electrodes 230e may be arranged in the X direction of FIG. 23. In such a case, the two main opposing electrodes 230e may be separated from one another and not connected to one another. The main opposing electrodes 230e described above may not be connected to one another, and some of the plurality of main opposing electrodes 230e may be connected to the fourth opposing electrode 230d. In this case, each main opposing electrode 230e may be connected to a respective wiring arranged on a side surface of the substrate 100.

[0236] To form the main counter electrode 230e as described above, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from one another. A plurality of fourth openings 422B-3 may be provided, and the plurality of fourth openings 422B-3 may be arranged spaced apart from one another in one direction. A portion of the second mask sheet 422B may be disposed between adjacent fourth openings 422B-3 to separate the adjacent fourth openings 422B-3. That is, two fourth openings 422B-3 are arranged in a column, and two fourth openings 422B-3 are arranged in a row.

[0237] In the above case, the deposition material passing through the fourth opening 422B-3 can form the main opposing electrode 230e in the third display area DA3, and as described above, the deposition material passing through different fourth openings 422B-3 can be deposited in different regions of the substrate 100 to form different main opposing electrodes 230e.

[0238] Although the present invention has been described above with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible. Therefore, the true technical scope of the present invention is determined by the technical spirit of the claims. [Explanation of symbols]

[0239] 10. Display panel 20 Components 100... board 110 First scan drive circuit 111... Buffer layer 112 First gate insulating layer 113...Second gate insulating layer 115...Interlayer insulation layer 117...flattening layer 119...Pixel-defined membrane 120 Second scan drive circuit 130 Second scan drive circuit 140... terminal 150 Data drive circuit 151 Connection wiring 160...1st power supply wiring 162...First sub wiring 163 Second sub-wiring 170...Second power supply wiring 175···Bottom protective film 200 Display element layer 210 Pixel electrode 220 Middle class 230 Counter electrode 230a: First opposing electrode 230b: Second opposing electrode 230c Third opposing electrode 230d: Fourth opposing electrode 300 Thin film sealing layer 310 Pixel electrode 320...Organic sealing layer 400 Display device manufacturing equipment 410 Chamber 420A···First mask assembly 420B... Second mask assembly 421A···First mask frame 421B···Second mask frame 422A···First mask sheet 422B...Second mask sheet 430...1st support part 440...Second support part 450···Evaporation source 460 Magnetic force generating unit 470 Vision Department 480 Pressure adjustment unit 1130 Semiconductor layer 1173 Initialization connection line 1174···Node connection line 1175···Connecting metal 1151,1152,1153,1154,1155,1156,1157,1163...Contact holes

Claims

1. a chamber, a portion of which is selectively opened and closed; a first support disposed inside the chamber and configured to support a substrate; a mask assembly disposed within the chamber so as to face the substrate; a second support portion disposed inside the chamber and supporting the mask assembly; a deposition source disposed in the chamber to supply a deposition material to the substrate; The mask assembly includes a first mask assembly and a second mask assembly that are interchangeable with each other; the first mask assembly or the second mask assembly is placed on the second support portion, The second mask assembly is Mask frame and a mask sheet placed on the mask frame, the mask sheet includes a first opening, a second opening disposed in a portion of the mask sheet different from the first opening, and a third opening disposed in a portion of the mask sheet different from the first opening and the second opening, the second opening and the third opening are connected via parts of opposing sides, the first opening is separated from the second opening and the third opening, the shapes of the first opening and the second opening are different from each other, the area of ​​the first opening is smaller than the area of ​​the second opening, and the width of the mask sheet disposed between the second opening and the third opening is wider than the width of the mask sheet disposed between the first opening and the second opening, The apparatus for manufacturing a display device, wherein the deposition materials that pass through the first opening and the second opening and are deposited on the substrate are connected to each other on the substrate.

2. 2. The display device manufacturing apparatus according to claim 1, wherein the deposition source is disposed in a corner of the chamber.

3. 2. The display device manufacturing apparatus according to claim 1, wherein the first opening is square and the second opening is rectangular.

4. 2. The apparatus of claim 1, wherein at least one of the first support portion and the second support portion adjusts a relative position between the substrate and the first mask assembly.

5. The third opening is provided in a plurality of pieces spaced apart from each other, 2. The display device manufacturing apparatus according to claim 1, wherein each of the third openings is formed in a line shape.

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