How to train a neural network model

Abstract

To provide a neural network model that can perform highly accurate processing on input data.SOLUTION: A neural network model includes first and second neutral networks. The first neural network includes a first layer, a second layer, and a third layer. A feature map output from the first layer is input to the second layer and the second neural network, and a feature map output from the second neural network is input to the third layer. Given that the feature map output from the first layer when first data is input to the first neural network is a correct feature map and that the feature map output from the first layer when second data obtained by adding noise to the first data is input to the first neural network is a learning feature map, the second neural network is trained so that an output feature map matches the correct feature map when the learning feature map is input.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a neural network model and a method for training a neural network model. [Background technology]

[0002] Image processing techniques using AI (Artificial Intelligence) are attracting attention. For example, Patent Document 1 discloses a segmentation technique that uses a neural network to detect the type of object contained in an image and the area of ​​the object. In addition, techniques have been developed that use AI to colorize black-and-white images, estimate depth, and perform other functions.

[0003] Neural networks with skip-connected layers have also been developed. Here, skip connection refers to a configuration in which a feature map output from a layer of a neural network is input not only to the next layer but also to other layers closer to the output layer. Non-Patent Document 1 discloses U-Net as a neural network with skip connections. Due to the skip connections, U-Net makes it easier to reflect, for example, information contained in image data input to the neural network in a feature map output from a layer close to the output layer. This enables highly accurate image processing. For example, U-Net makes it easier to reflect information such as the position and contours of an object contained in image data input to the neural network in a feature map output from a layer close to the output layer, thereby enabling highly accurate segmentation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-82979 [Non-patent literature]

[0005] [Non-Patent Document 1] Olaf Ronneberger, Philipp Fischer, and Thomas Brox, "U-Net: Convolutional Networks for Biomedical Image Segmentation," Medical Image Computing and Computer-Assisted Intervention, 234-241 (2015). Summary of the Invention [Problem to be solved by the invention]

[0006] In a neural network with skip-connected layers, if the data input to the neural network (input data) contains noise, the noise is likely to propagate to layers close to the output layer, which may result in the data not being processed with high accuracy.

[0007] An object of one embodiment of the present invention is to provide a neural network model that can remove noise contained in input data, to provide a neural network model that can process input data with high accuracy, or to provide a novel neural network model.

[0008] An object of one embodiment of the present invention is to provide a neural network model training method capable of removing noise contained in input data, to provide a neural network model training method capable of processing input data with high accuracy, or to provide a novel neural network model training method.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a neural network model including a first neural network and a second neural network, the first neural network having a layer skip-connected via the second neural network, and a training method thereof. The second neural network has a function of performing noise removal on an input feature map. This makes it possible to prevent noise from being transmitted to layers close to the output layer of the first neural network, even if the data input to the first neural network contains noise.

[0011] When training a neural network model according to an embodiment of the present invention, first, initial values ​​of weight coefficients of a first neural network are obtained. Next, a first training is performed to obtain weight coefficients of a second neural network. After that, a second training is performed to obtain weight coefficients of the first neural network. After the first training and the second training are performed, the inference accuracy of the neural network model according to an embodiment of the present invention is evaluated. The first training and the second training are performed until the inference accuracy reaches or exceeds a specified value.

[0012] One aspect of the present invention is a neural network model that includes a first neural network and a second neural network. The first neural network has a first layer, a second layer, and a third layer. A feature map output from the first layer is input to the second layer and the second neural network. A feature map output from the second neural network is input to the third layer. The second neural network is trained by a first learning process so that the feature map output from the first layer when first data is input to the first neural network is a ground truth feature map, and the feature map output from the first layer when second data, which is the first data plus noise, is input to the first neural network is a training feature map. The second neural network is trained by a first learning process so that the feature map output from the second neural network when the training feature map is input to the second neural network matches the ground truth feature map.

[0013] Alternatively, in the above aspect, the weighting coefficients of the second neural network may be obtained by first learning after inputting data for obtaining initial values ​​into the first neural network to obtain initial values ​​of the weighting coefficients of the first neural network.

[0014] Alternatively, in the above aspect, the weighting coefficients of the first neural network may be obtained by a second learning process that is performed by inputting second data into the first neural network after obtaining the weighting coefficients of the second neural network.

[0015] Alternatively, in the above aspect, the first neural network may have a fourth layer, a fifth layer, and a sixth layer, and the feature map output from the fourth layer may be input to the fifth layer and the sixth layer that is skip-connected to the fourth layer, and the fourth layer may be closer to the output layer of the first neural network than the first layer, and the third layer may be closer to the output layer of the first neural network than the sixth layer.

[0016] Alternatively, one aspect of the present invention includes a first neural network and a second neural network, the first neural network having a first layer, a second layer, a third layer, and a fourth layer, the fourth layer being closer to the output layer of the first neural network in the order of the third layer, the second layer, and the first layer, the feature map output from the first layer being input to the second layer and the second neural network, the feature map output from the third layer and the feature map output from the second neural network being input to the fourth layer, and the feature map output from the second neural network being input to the fourth layer. The neural network is a neural network model that is trained by a first learning process so that when first data is input to the first neural network, the feature map output from the first layer is the correct feature map, and when second data, which is the first data with noise added, is input to the first neural network, the feature map output from the first layer is the trained feature map, and when the trained feature map is input to the second neural network, the feature map output from the second neural network matches the correct feature map.

[0017] Alternatively, in the above aspect, the weighting coefficients of the second neural network may be obtained by first learning after inputting data for obtaining initial values ​​into the first neural network to obtain initial values ​​of the weighting coefficients of the first neural network.

[0018] Alternatively, in the above aspect, the weighting coefficients of the first neural network may be obtained by a second learning process that is performed by inputting second data into the first neural network after obtaining the weighting coefficients of the second neural network.

[0019] Alternatively, in the above aspect, the first neural network model may have a fifth layer, a sixth layer, and a seventh layer, and the feature map output from the fifth layer may be input to the sixth layer and the seventh layer that is skip-connected to the fifth layer, and the fifth layer may be closer to the output layer of the first neural network than the first layer, and the fourth layer may be closer to the output layer of the first neural network than the seventh layer.

[0020] Alternatively, one aspect of the present invention is a method for training a neural network model, the method comprising: a first neural network and a second neural network; the first neural network having a first layer, a second layer, and a third layer; a feature map output from the first layer being input to the second layer and the second neural network; and a feature map output from the second neural network being input to the third layer, the method comprising: a first step of acquiring initial values ​​of weight coefficients of the first neural network by inputting data for acquiring initial values ​​into the first neural network; a step of determining a feature map output from the first layer when the first data is input to the first neural network as a correct feature map; and a step of determining a feature map output from the first layer when second data, in which noise has been added to the first data, is input to the first neural network as a correct feature map. This is a neural network model training method comprising: a second step of acquiring weight coefficients for a second neural network by performing a first training process in which the feature map output from the first layer is used as a training feature map and the feature map output from the second neural network matches the correct feature map when the training feature map is input to the second neural network; a third step of acquiring weight coefficients for the first neural network by inputting the second data to the first neural network and performing a second training process; and a fourth step of inputting test data to the first neural network and evaluating the inference accuracy of the neural network model based on the output data output from the first neural network, where steps two through four are performed until the inference accuracy reaches or exceeds a specified value.

[0021] Alternatively, in the above aspect, the first neural network may have a fourth layer, a fifth layer, and a sixth layer, and the feature map output from the fourth layer may be input to the fifth layer and the sixth layer that is skip-connected to the fourth layer, and the fourth layer may be closer to the output layer of the first neural network than the first layer, and the third layer may be closer to the output layer of the first neural network than the sixth layer. [Effects of the Invention]

[0022] According to one aspect of the present invention, it is possible to provide a neural network model that can remove noise contained in input data, or a neural network model that can process input data with high accuracy, or a novel neural network model.

[0023] According to one aspect of the present invention, it is possible to provide a neural network model training method capable of removing noise contained in input data, a neural network model training method capable of processing input data with high accuracy, or a novel neural network model training method.

[0024] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0025] [Figure 1]1A and 1B are diagrams showing an example of the configuration of a neural network model. [Figure 2] FIG. 2 is a flowchart showing an example of a method for training a neural network model. [Figure 3] 3A and 3B are diagrams showing an example of a learning method for a neural network model. [Figure 4] 4A, 4B1, 4B2, and 4C are diagrams showing an example of a method for training a neural network model. [Figure 5] FIG. 5 is a diagram illustrating an example of a learning method for a neural network model. [Figure 6] FIG. 6 is a diagram illustrating an example of a learning method for a neural network model. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a neural network model. [Figure 8] 8A and 8B are block diagrams showing examples of the configuration of a processing system. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of the imaging unit. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a pixel block 200 and a circuit 201. As shown in FIG. [Figure 11] FIG. 11 is a diagram showing an example of the configuration of a pixel. [Figure 12] 12A to 12C are diagrams illustrating filters. [Figure 13] Fig. 13A is a diagram showing an example of the configuration of a pixel, and Figs. 13B to 13D are diagrams showing an example of the configuration of a photoelectric conversion device. [Figure 14] FIG. 14 is a cross-sectional view showing an example of the configuration of an imaging device. [Figure 15] 15A to 15C are cross-sectional views showing examples of the structure of a transistor. [Figure 16] FIG. 16 is a cross-sectional view showing an example of the configuration of an imaging device. [Figure 17] FIG. 17 is a cross-sectional view showing an example of the configuration of an imaging device. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0027] It should be noted that the ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and are not intended to limit the numbers.

[0028] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0029] Furthermore, a single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via multiple conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0030] (Embodiment) In this embodiment, a neural network model of one embodiment of the present invention and an example of a learning method for the neural network model will be described.

[0031] <Neural network model_1> 1A is a diagram showing an example of the configuration of a neural network model 10 according to one embodiment of the present invention. The neural network model 10 includes a neural network NN1 and a neural network NN2.

[0032] Neural network NN1 has multiple layers made up of neurons, and the neurons in each layer are connected to each other. Therefore, neural network NN1 can be said to be a hierarchical neural network. Each layer made up of neurons has the function of extracting features from data input to that layer and outputting data representing the features as a feature map. Note that neural network NN2 can also be a hierarchical neural network.

[0033] 1A shows layers L_1, L_2, and L_3 of the neural network NN1, and the flow of data between the layers is indicated by arrows.

[0034] In this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, an identifying symbol such as "_1" or "[1]" may be added to the reference numeral. For example, in Figure 1A and the like, three layers L are distinguished by being described as layer L_1, layer L_2, and layer L_3, respectively.

[0035] A neural network has an input layer and an output layer, with a hidden layer between the input layer and the output layer. A single neural network can have multiple hidden layers. Layers L_1, L_2, and L_3 shown in FIG. 1A can be hidden layers. Layer L_1 can be the input layer, and layer L_3 can be the output layer.

[0036] In this specification, inputting data into the input layer of a neural network may be referred to as "inputting data into a neural network," and outputting data from the output layer of a neural network may be referred to as "outputting data from a neural network."

[0037] The feature map output from layer L_1 is input to layer L_2, and the feature map output from layer L_2 is input to layer L_3. In other words, data is transmitted in the order of layer L_1, layer L_2, and layer L_3. Therefore, it can be said that the layer next to layer L_1 is layer L_2, and the layer next to layer L_2 is layer L_3.

[0038] The feature map output from layer L_1 is also input to neural network NN2. Specifically, if neural network NN2 is a hierarchical neural network having an input layer, a hidden layer, and an output layer, the feature map output from layer L_1 is input to the input layer of neural network NN2. Then, the feature map output from neural network NN2 is input to layer L_3.

[0039] Here, the neural network NN2 has the function of removing noise contained in the feature map input to the neural network NN2. Therefore, it can be said that the feature map input to the neural network NN2 from the layer L_1 and from which noise has been removed by the neural network NN2 is input to the layer L_3. From the above, it can be said that the feature map output from the layer L_1 is input to the layer L_3 via the neural network NN2.

[0040] As described above, the layer next to layer L_1 is layer L_2. Meanwhile, the feature map output from layer L_1 and input to neural network NN2 is input to layer L_3 via neural network NN2. That is, the feature map output from layer L_1 and input to neural network NN2 skips layer L_2, the layer next to layer L_1, and is input to layer L_3. Therefore, it can be said that layer L_1 and layer L_3 are skip-connected via neural network NN2. It can also be said that layer L_3 is a connection layer that connects the feature map output from layer L_1 and the feature map output from layer L_2.

[0041] In this specification, layers that are skip-connected are shown connected by dashed lines. For example, in Figure 1A, the skip connection between layer L_1 and layer L_3 via neural network NN2 is shown by connecting layer L_1 and neural network NN2, and neural network NN2 and layer L_3 with dashed lines, respectively.

[0042] The neural network NN1 has a function of outputting a predetermined inference result as a feature map from the output layer for data input to the input layer. For example, when image data is input to the input layer of the neural network NN1, the neural network NN1 has a function of performing segmentation or depth estimation on the image data. Alternatively, when black and white or grayscale image data is input to the input layer of the neural network NN1, the neural network NN1 has a function of colorizing the image data.

[0043] In this specification and the like, the feature map output from the output layer may be referred to as output data output from the neural network having the output layer.

[0044] In a neural network with skip-connected layers, if the data input to the neural network contains noise, the noise is likely to propagate to layers close to the output layer. This may result in inference on the data being unable to be performed with high accuracy. On the other hand, the neural network NN1 of the neural network model 10 has layers that are skip-connected via a neural network NN2 that has a noise removal function. This makes it possible to suppress the noise from propagating to layers close to the output layer even if the data input to the neural network NN1 contains noise. This allows inference on the data to be performed with high accuracy.

[0045] In the neural network model 10 shown in Fig. 1A, the layer L provided between layer L_1 and layer L_3, which are layers L skip-connected via the neural network NN2, is considered to be one layer, but the present invention is not limited to this. As shown in Fig. 1B, m layers (m is an integer of 2 or more) of layers L_2 may be provided between layer L_1 and layer L_3. In Fig. 1B, the m layers of layers L_2 are distinguished by being written as layer L_2[1] to layer L_2[m] in order from the layer closest to the input layer of the neural network NN1.

[0046] 1B, the feature map output from layer L_1 is input to layer L_2[1] and neural network NN2. Also, the feature map output from layer L_2[m] and the feature map output from neural network NN2 are input to layer L_3.

[0047] The neural network NN1 of the neural network model 10 can be, for example, a convolutional neural network (CNN). When the neural network NN1 has the configuration shown in FIG. 1B and is a CNN, the layer L_1 and the layer L_2[m] can be, for example, pooling layers.

[0048] The neural network NN2 can be, for example, an autoencoder. For example, it can be a generative adversarial network (GAN). When the neural network NN2 is a GAN, it can be, for example, a conditional GAN. Using a GAN as the neural network NN2 is preferable because it allows inference by the neural network NN2, for example, noise removal from a feature map input to the neural network NN2, to be performed with high accuracy.

[0049] <Learning Method> Next, an example of a training method for the neural network model 10 will be described with reference to Figures 2 to 6. Figure 2 is a flowchart showing an example of the training method for the neural network model 10. Figures 3 to 6 are schematic diagrams showing an example of the processing in each step shown in Figure 2. Note that in Figures 3 to 6, the neural network model 10 is assumed to have the configuration shown in Figure 1A. Also, Figures 3 to 6 show, as an example, an example of a training method for the neural network model 10, for providing the neural network NN1 with the function of performing segmentation on image data when the image data is input to the neural network NN1.

[0050] [Step S1] First, initial value acquisition data is input to the neural network NN1 to acquire a weighting coefficient 11_1, which is the initial value of the weighting coefficient 11 of the neural network NN1 (step S1). Figures 3A and 3B are schematic diagrams showing an example of the processing in step S1. Specifically, Figure 3A is a schematic diagram showing an example of the processing in step S1_1, and Figure 3B is a schematic diagram showing an example of the processing in step S1_2.

[0051] As shown in FIG. 3A, in step S1_1, data 21 is prepared. The data 21 can be represented by, for example, a matrix. Here, when the data 21 is image data acquired by imaging, for example, the elements of the matrix can be gradation values ​​representing the illuminance of light irradiated onto pixels of an imaging device. Alternatively, the elements can be gradation values ​​representing the luminance of light emitted from pixels of a display device that displays an image corresponding to the data 21. In other words, the number of rows and columns of the matrix representing the data 21 can be the same as the resolution of the image corresponding to the data 21, for example. Note that data other than the data 21 can also be represented by a matrix in some cases. For example, the data can be represented by a matrix with the same number of rows and columns as the data 21. Alternatively, the data can be represented by a matrix with fewer rows and columns than the data 21.

[0052] Data 22 is obtained by adding data assuming noise to data 21. For example, if image data acquired by capturing an image with a camera is assumed as the data input to the neural network NN1, the noise can be assumed to be, for example, scratches on the camera lens or water droplets on the camera. Alternatively, the noise can be assumed to be shot noise that occurs when capturing an image in a dark place. Furthermore, if image data acquired by capturing an image displayed on a display device is assumed as the data input to the neural network NN1, the noise can be assumed to be defects such as point defects and line defects. Note that the data added to data 21 does not necessarily have to be assumed to be noise, as long as it is data to be removed by the neural network NN2.

[0053] In the method described above, in step S1_1, data 22 is created from data 21, but one aspect of the present invention is not limited to this. For example, data 21 may be created from data 22. In this case, for example, data 22 is acquired by capturing an image in a rainy environment, and image processing is performed on the data 22 to remove water droplets, thereby acquiring data 21.

[0054] Next, as shown in FIG. 3B, in step S1_2, data 22 and data 23 are input to the neural network NN1. Here, data 23 can be, for example, data representing a desired result of segmentation of data 22. This makes it possible to obtain weighting coefficient 11_1, which is the initial value of weighting coefficient 11 of neural network NN1. For example, when data 22 is input to the neural network NN1, the neural network NN1 can obtain weighting coefficient 11_1 such that the error between the output data output from the neural network NN1 and data 23 is minimized.

[0055] In step S1_1 shown in FIG. 3A, one piece of data 21 is prepared, but two or more pieces of data 21 may be prepared. In step S1_2 shown in FIG. 3B, one piece of data 22 and one piece of data 23 are input to the neural network NN1, but two or more pieces of data 22 and two or more pieces of data 23 may be input to the neural network NN1. In step S1_2, the data 23 does not have to be input to the neural network NN1. For example, if the learning of the neural network NN1, which will be described later, is performed by unsupervised learning, the data 23 does not have to be input to the neural network NN1.

[0056] 3A and 3B, it can be said that the data 22 is the data for obtaining initial values. It can also be said that both the data 22 and the data 23 are the data for obtaining initial values.

[0057] At the stage of performing step S1, the neural network NN2 has not yet acquired the weighting coefficients, and therefore no processing is performed by the neural network NN2 at step S1.

[0058] [Step S2] Next, the neural network model 10 performs first learning to obtain weighting coefficients 12 of the neural network NN2 (step S2). Figures 4A, 4B1, 4B2, and 4C are schematic diagrams showing an example of the processing in step S2. Specifically, Figure 4A is a schematic diagram showing an example of the processing in step S2_1, Figure 4B1 is a schematic diagram showing an example of the processing in step S2_2a, Figure 4B2 is a schematic diagram showing an example of the processing in step S2_2b, and Figure 4C is a schematic diagram showing an example of the processing in step S2_3.

[0059] In step S2, a weighting coefficient 11_i (i is an integer equal to or greater than 1) is held in each layer of the neural network NN1. If step S2 is performed immediately after step S1, i can be set to 1. In Figs. 4B1 and 4B2, the weighting coefficient 11_i held in layer L_1 is shown as weighting coefficient 11_i[1].

[0060] Details of step S2 for performing the first learning will be described below. First, as shown in FIG. 4A, in step S2_1, a data set 25 including a plurality of data 24 is prepared, and data assuming noise is added to each of the data 24 to obtain data 26. In this way, a data set 27 including a plurality of data 26 is obtained. The noise added to the data 24 can be the same type of noise as the noise that can be added to the data 21 shown in FIG. 3A. Note that the data added to the data 24 does not necessarily have to be assumed to be noise, as long as it is data to be removed by the neural network NN2, similar to the data added to the data 21.

[0061] In the method described above, data 26 is created from data 24 in step S2_1, but one aspect of the present invention is not limited to this. The method of acquiring data 24 and data 26 can be the same as the method of acquiring data 21 and data 22 in step S1_1. For example, if data 21 is created from data 22 in step S1_1, data 24 can be created from data 26 in step S2_1, thereby acquiring data 24 and data 26.

[0062] Next, as shown in FIG. 4B1, in step S2_2a, data 24 is input to the neural network NN1, and a feature map 34 output from layer L_1 is obtained. For example, a feature map 34 is obtained for each of the multiple data 24 included in dataset 25. As a result, a feature map set 35 including the multiple feature maps 34 is obtained. Also, as shown in FIG. 4B2, in step S2_2b, data 26 is input to the neural network NN1, and a feature map 36 output from layer L_1 is obtained. For example, a feature map 36 is obtained for each of the multiple data 26 included in dataset 27. As a result, a feature map set 37 including the multiple feature maps 36 is obtained.

[0063] Then, as shown in FIG. 4C , in step S2_3, the feature map 36 is input as training data and the feature map 34 is input as correct data to the neural network NN2. This allows the weighting coefficients 12 of the neural network NN2 to be acquired. For example, the neural network NN2 can acquire weighting coefficients 12 such that when the feature map 36 is input to the neural network NN2, the feature map output from the neural network NN2 matches the feature map 34 corresponding to the feature map 36. Specifically, for example, by using a gradient descent method using an error function (also called a loss function), it is possible to acquire weighting coefficients 12 such that when the feature map 36 is input to the neural network NN2, the error between the feature map output from the neural network NN2 and the correct data feature map 34 is minimized. Examples of error functions that can be used include the sum-of-squares error and the cross-entropy error. The gradient descent method acquires weighting coefficients that minimize the error function. The minimum value can be obtained, for example, by differentiating the error function. The differentiation of the error function can be obtained, for example, by backpropagation.

[0064] When the neural network NN2 is a Conditional GAN, the neural network NN2 can learn by inputting the feature map 34 to the generator and the feature map 36 to the discriminator.

[0065] In this specification, a feature map that can be used as training data is sometimes referred to as a training feature map, and a feature map that can be used as correct data is sometimes referred to as a correct feature map. For example, feature map 36 can be called a training feature map, and feature map 34 can be called a correct feature map.

[0066] [Step S3] Next, the neural network model 10 performs second learning to obtain weighting coefficients 11 of the neural network NN1 (step S3). Figure 5 is a schematic diagram showing an example of the process in step S3.

[0067] In step S3, a weighting coefficient 11_i is held in each layer of the neural network NN1. As described above, for example, if an initial value of the weighting coefficient 11 is held in each layer of the neural network NN1, i can be set to 1. Furthermore, the weighting coefficient 12 acquired in the immediately preceding step S2 is held in the neural network NN2. Note that in FIG. 5, the weighting coefficient 11_i held in layer L_1 is represented as weighting coefficient 11_i[1], the weighting coefficient 11_i held in layer L_2 is represented as weighting coefficient 11_i[2], and the weighting coefficient 11_i held in layer L_3 is represented as weighting coefficient 11_i[3].

[0068] In step S3, data 26 is input as training data and data 28 as correct answer data to the neural network NN1. Here, data 26 may be the same data as data 26 acquired in step S2_1 shown in FIG. 4A and input to the neural network NN1 in step S2_2b shown in FIG. 4B2. That is, in step S2, when training the neural network NN2, the same data as that input to the neural network NN1 to acquire feature map 36, which is a training feature map, may be used as training data in training the neural network NN1. Furthermore, data 28 may be data representing a desired result of segmentation of data 26, for example. Here, a set of data 28 used as correct answer data in training the neural network NN1 is referred to as dataset 29. Note that the data 26 input to the neural network NN1 in step S2_2b may be different from the data 26 input to the neural network NN1 in step S3.

[0069] As described above, the weight coefficient 11_i+1 of the neural network NN1 can be obtained. Specifically, the weight coefficient 11_i+1 can be obtained by optimizing the weight coefficient 11_i. For example, the neural network NN1 can obtain a weight coefficient 11_i+1 such that when data 26 is input to the neural network NN1, the output data output from the neural network NN1 matches the data 28 corresponding to the data 26. Specifically, for example, by using a gradient descent method using an error function, it is possible to obtain a weight coefficient 11_i+1 such that when data 26 is input to the neural network NN1, the error between the output data output from the neural network NN1 and the correct data 28 is minimized.

[0070] As described above, the neural network NN2 holds the weighting factor 12 acquired in the immediately preceding step S2. Therefore, the data 26 input to the neural network NN1 is also processed by the neural network NN2. Therefore, the weighting factor 11_i+1 acquired by the neural network NN1 in step S3 can reflect the weighting factor 12 held in the neural network NN2. Note that although it has been described that the weighting factor 12 is not acquired in step S3, i.e., the weighting factor 12 acquired in the immediately preceding step S2 is not optimized in step S3, one aspect of the present invention is not limited to this. For example, both the weighting factor 11 and the weighting factor 12 may be optimized in step S3.

[0071] 5 shows a case where the neural network NN1 is trained by supervised learning, but the neural network NN1 may be trained by unsupervised learning. When the neural network NN1 is trained by unsupervised learning, the data 28, which is the correct answer data, does not need to be input to the neural network NN1.

[0072] [Step S4] Next, data 41 is input as test data to the neural network NN1, and the inference accuracy of the neural network model 10 is evaluated based on output data 43 output from the neural network NN1 (step S4). Figure 6 is a schematic diagram showing an example of the processing in step S4.

[0073] For example, output data 43 is compared with data 45 that represents the desired result of segmentation of data 41, and the inference accuracy of neural network model 10 is evaluated based on the difference between output data 43 and data 45. For example, if output data 43 and data 45 are represented by matrices with the same number of rows and columns, the inference accuracy of neural network model 10 is evaluated based on the difference between each element of the matrix that makes up output data 43 and each element of the matrix that makes up data 45.

[0074] For example, if the output data 43 and the data 45 are each represented by a matrix of p rows and q columns (p and q are integers equal to or greater than 1), first, it is determined whether the element in the first row and first column of the output data 43 matches the element in the first row and first column of the data 45. Similarly, it is determined whether the output data 43 matches the data 45 for all elements. Then, the number of matching elements is divided by the total number of elements in the matrix (p × q), and this is taken as the accuracy rate. The inference accuracy of the neural network model 10 is evaluated based on the accuracy rate. It can be evaluated that the higher the accuracy rate, the higher the inference accuracy.

[0075] Alternatively, the inference accuracy of the neural network model 10 may be evaluated based on an error function. When the neural network model 10 is trained so that the neural network NN1 has a function of performing segmentation on data input to the neural network NN1, the inference accuracy of the neural network model 10 can be evaluated by mIoU (mean intersection over union).

[0076] Alternatively, for example, if the output data 43 and the data 45 are each represented by a matrix with p rows and q columns, first, the absolute value of the difference between the element in the first row and first column of the output data 43 and the element in the first row and first column of the data 45 is calculated. Similarly, the absolute value of the difference between the output data 43 and the data 45 is calculated for all elements. Then, the sum of the absolute values ​​of the calculated p × q differences is calculated, and the inference accuracy of the neural network model 10 is evaluated based on the sum. The smaller the sum, the smaller the error between the output data 43 and the data 45, i.e., the higher the inference accuracy can be evaluated. This method can be suitably used when training the neural network model 10 so that the neural network NN1 has the function of performing depth estimation on data input to the neural network NN1, for example.

[0077] Alternatively, when training the neural network model 10 so that the neural network NN1 has the function of colorizing black-and-white image data input to the neural network NN1, the inference accuracy can be evaluated based on, for example, a color space. For example, the inference accuracy of the neural network model 10 can be evaluated by comparing the HSV color space of the output data 43 and the data 45. Here, the HSV color space is a numerical representation of the hue, saturation, and brightness of the image represented by the image data. The inference accuracy may also be evaluated using the RGB color space, CMY color space, HLS color space, or the like.

[0078] Note that multiple pieces of data 41, which are test data, can be prepared. In this case, a set of data 41 is referred to as data set 42. Furthermore, if multiple pieces of data 41 are prepared, multiple pieces of output data 43 and multiple pieces of data 45 are also prepared. For example, the same number of output data 43 as the number of pieces of data 41 and the same number of pieces of data 45 as the number of pieces of data 41 are prepared. When multiple pieces of output data 43 and multiple pieces of data 45 are prepared, the set of output data 43 is referred to as data set 44, and the set of data 45 is referred to as data 46. When evaluating the inference accuracy of the neural network model 10 using multiple pieces of data 41, for example, each of the multiple pieces of data 41 is input to the neural network NN1, and the inference accuracy for each piece of data 41 is calculated. Then, the average value of the inference accuracy for each piece of data 41 can be used as the inference accuracy of the neural network model 10 to be used in the next step.

[0079] [Step S5] Thereafter, it is determined whether the inference accuracy of the neural network model 10 evaluated in step S4 is equal to or greater than a specified value (step S5). If it is equal to or greater than the specified value, the learning of the neural network model 10 is terminated. If it is less than the specified value, 1 is added to i, and steps S2 to S5 are repeated. That is, the weighting coefficient 12 is optimized by the first learning, and the weighting coefficient 11 is optimized by the second learning, until the inference accuracy is equal to or greater than the specified value. This is an example of a learning method for the neural network model 10. Note that in step S5, the increase in inference accuracy resulting from the first learning and the second learning may be evaluated, and the learning of the neural network model 10 may be terminated if the increase is equal to or less than a specified value. For example, the difference in inference accuracy between the first learning and the second learning performed j times (j is an integer equal to or greater than 1) and the second learning performed j+1 times may be evaluated, and the learning of the neural network model 10 may be terminated if the difference is equal to or less than a specified value.

[0080] <Neural network model_2> 7 is a diagram showing an example of the configuration of a neural network model 10a, which is a neural network model according to one embodiment of the present invention. The neural network model 10a includes a neural network NN1a and a neural network NN2a. The neural network NN1a has the same function as the neural network NN1, and the neural network NN2a has the same function as the neural network NN2. Furthermore, the neural network model 10a can be trained using the same procedure as the neural network model 10.

[0081] In this specification, the neural network model 10 may include the neural network model 10a. The neural network NN1 may include the neural network NN1a, and the neural network NN2 may include the neural network NN2a.

[0082] The neural network NN1a includes an input layer IL, intermediate layers ML_1 to ML_17, and an output layer OL. The architecture of the neural network NN1a may be, for example, U-Net. Alternatively, it may be, for example, DenseNet.

[0083] In the neural network NN1a configured as shown in FIG. 7, the feature map output from the input layer IL is input to the hidden layer ML_1, and the feature map output from the hidden layer ML_1 is input to the hidden layer ML_2. In this way, the data input to the input layer IL is transmitted sequentially to the hidden layers ML_1 to ML_17. The feature map output from the hidden layer ML_17 is then input to the output layer OL. From the above, it can be said that, among the hidden layers ML_1 to ML_17, the hidden layer ML_1 is closest to the input layer IL, the hidden layers ML_2 to ML_16 are further away from the input layer IL in that order, that is, closer to the output layer OL, and the hidden layer ML_17 is closest to the output layer OL.

[0084] The feature map output from the hidden layer ML_1 is input not only to the hidden layer ML_2 but also to the neural network NN2a. The feature map output from the neural network NN2a is input to the hidden layer ML_16. That is, the feature map output from the hidden layer ML_15 as well as the feature map output from the neural network NN2a are input to the hidden layer ML_16. From the above, it can be said that the hidden layer ML_1 and the hidden layer ML_16 are skip-connected via the neural network NN2a. It can also be said that the hidden layer ML_16 functions as a connection layer that connects the feature map output from the hidden layer ML_15 and the feature map output from the neural network NN2a.

[0085] The feature map output from the intermediate layer ML_3 is input not only to the intermediate layer ML_4 but also to the intermediate layer ML_14. That is, the feature map output from the intermediate layer ML_13 as well as the feature map output from the intermediate layer ML_3 are input to the intermediate layer ML_14. Therefore, it can be said that the intermediate layer ML_3 and the intermediate layer ML_14 are skip-connected. It can also be said that the intermediate layer ML_14 functions as a connecting layer that connects the feature map output from the intermediate layer ML_13 and the feature map output from the intermediate layer ML_3.

[0086] The feature map output from the intermediate layer ML_5 is input not only to the intermediate layer ML_6 but also to the intermediate layer ML_12. That is, the feature map output from the intermediate layer ML_11 as well as the feature map output from the intermediate layer ML_5 are input to the intermediate layer ML_12. Therefore, it can be said that the intermediate layer ML_5 and the intermediate layer ML_12 are skip-connected. It can also be said that the intermediate layer ML_12 functions as a connecting layer, connecting the feature map output from the intermediate layer ML_11 and the feature map output from the intermediate layer ML_5.

[0087] The feature map output from the intermediate layer ML_7 is input not only to the intermediate layer ML_8 but also to the intermediate layer ML_10. That is, the feature map output from the intermediate layer ML_9 as well as the feature map output from the intermediate layer ML_7 are input to the intermediate layer ML_10. Therefore, it can be said that the intermediate layer ML_7 and the intermediate layer ML_10 are skip-connected. It can also be said that the intermediate layer ML_10 functions as a connecting layer that connects the feature map output from the intermediate layer ML_9 and the feature map output from the intermediate layer ML_7.

[0088] From the above, it can be said that the neural network NN1a shown in Fig. 7 has four pairs of skip-connected layers. Furthermore, among the skip-connected hidden layers ML, it can be said that the hidden layer ML_1 closest to the input layer IL is skip-connected to the hidden layer ML_16 closest to the output layer OL via the neural network NN2a.

[0089] For example, in U-Net, feature maps output from hidden layers close to the input layer are input to hidden layers close to the output layer via skip connections. Therefore, if noise is included in the data input to the input layer, the noise is likely to propagate to layers close to the output layer. This may result in inference on the data being unable to be performed with high accuracy. Meanwhile, in the neural network NN1a shown in Figure 7, for example, the hidden layer ML_1 closest to the input layer IL among the skip-connected hidden layers ML is skip-connected to the hidden layer ML_16 closest to the output layer OL via a neural network NN2a with a noise removal function. This allows the neural network NN1a to perform inference on the data with high accuracy.

[0090] As feature extraction by the intermediate layer ML progresses, the effect of noise contained in the data input to the input layer IL decreases. For example, if noisy data is input to the input layer IL, the effect of the noise on the feature map output by the intermediate layer ML_7 is smaller than the effect of the noise on the feature map output by the intermediate layer ML_1. Therefore, even if a feature map output from an intermediate layer ML far from the input layer IL is input to another intermediate layer ML via skip connection, noise removal is not required for that feature map. For example, the intermediate layers ML_3, ML_5, and ML_7, which are farther from the input layer IL than the intermediate layer ML_1, can be skip-connected to the intermediate layers ML_14, ML_12, and ML_10, respectively, without using a neural network with a noise removal function. Therefore, even if the number of skip-connected layers increases, the size of the neural network model 10 can be suppressed from expanding, while maintaining the accuracy of inference on the data input to the input layer IL.

[0091] While FIG. 7 illustrates a configuration in which the neural network NN1a has 17 hidden layers ML and four pairs of skip-connected layers, this embodiment of the present invention is not limited to this. For example, the number of hidden layers ML may be greater than 17. Furthermore, while FIG. 7 illustrates a configuration in which only hidden layers ML_1 and ML_16 are skip-connected via a neural network with a noise-removal function, this embodiment of the present invention is not limited to this. For example, in addition to hidden layers ML_1 and ML_16, hidden layers ML_3 and ML_14 may also be skip-connected via a neural network with a noise-removal function. Increasing the number of layers skip-connected via a neural network with a noise-removal function enables highly accurate inference of data input to the input layer IL.

[0092] <Example of processing system configuration> A neural network model according to an embodiment of the present invention can be applied to, for example, a processing system. Fig. 8A is a block diagram showing an example of the configuration of a processing system 100 to which the neural network model according to an embodiment of the present invention can be applied. The processing system 100 includes an information processing device 120.

[0093] The information processing device 120 has an imaging unit 121, an output unit 122, a calculation unit 123, a main memory unit 124, and an auxiliary memory unit 125. Data and the like can be transmitted between the components of the information processing device 120 via a transmission path 127. Note that in this specification and the like, the imaging unit can be referred to as an imaging device.

[0094] The imaging unit 121 has a function of capturing an image and acquiring image data. The image data can be the data 21 shown in Fig. 3A. The output unit 122 has a function of supplying information.

[0095] The calculation unit 123 has a function of performing calculation processing. The calculation unit 123 has a function of performing predetermined calculation processing on data transmitted to the calculation unit 123 from, for example, the imaging unit 121, the main memory unit 124, the auxiliary memory unit 125, etc. via the transmission path 127. The calculation unit 123 can have, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc.

[0096] The main memory unit 124 has a function of storing data, programs, etc. The calculation unit 123 can read the data, programs, etc. stored in the main memory unit 124 and execute calculation processing. For example, the calculation unit 123 can execute a program read from the main memory unit 124 to execute a predetermined calculation processing on the data read from the main memory unit 124.

[0097] It is preferable that the main memory unit 124 operates faster than the auxiliary memory unit 125. The main memory unit 124 can include, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0098] The auxiliary storage unit 125 has a function of storing data, programs, etc. for a longer period of time than the main storage unit 124. The auxiliary storage unit 125 may include, for example, a hard disk drive (HDD), a solid state drive (SSD), etc. The auxiliary storage unit 125 may also include a nonvolatile memory such as a resistive random access memory (ReRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FeRAM), a magnetoresistive random access memory (MRAM), or a flash memory.

[0099] The weighting coefficients 11 and 12 obtained by learning the neural network model of one embodiment of the present invention are stored in the auxiliary storage unit 125. Note that the weighting coefficients 11 and 12 may also be stored in the main storage unit 124.

[0100] The information processing device 120 can be provided in an information terminal such as a smartphone, a tablet, or a personal computer.

[0101] Note that the configuration of the data processing system 100 is not limited to the above. For example, the data processing system 100 may include an information processing device 110 in addition to the information processing device 120, as shown in FIG.

[0102] The information processing device 110 includes an imaging unit 111, an output unit 112, a calculation unit 113, a main memory unit 114, an auxiliary memory unit 115, and a communication unit 116. Data and the like can be transmitted between the components of the information processing device 110 via a transmission path 117.

[0103] The imaging unit 111 has a function of capturing an image and acquiring image data. The image data can be the data 21 shown in Fig. 3A. The output unit 112 has a function of supplying information.

[0104] The calculation unit 113 has a function of performing calculation processing. The calculation unit 113 has a function of performing predetermined calculation processing on data transmitted to the calculation unit 113 from, for example, the imaging unit 111, the main memory unit 114, the auxiliary memory unit 115, the communication unit 116, etc. via the transmission path 117. The calculation unit 113 can have, for example, a CPU, a GPU, etc.

[0105] The main memory unit 114 has a function of storing data, programs, etc. The calculation unit 113 can read the data, programs, etc. stored in the main memory unit 114 and execute calculation processing. For example, the calculation unit 113 can execute a program read from the main memory unit 114 to execute a predetermined calculation processing on the data read from the main memory unit 114.

[0106] It is preferable that the main memory unit 114 operates faster than the auxiliary memory unit 115. The main memory unit 114 may include, for example, a DRAM, an SRAM, or the like.

[0107] The auxiliary storage unit 115 has a function of storing data, programs, etc. for a longer period of time than the main storage unit 114. The auxiliary storage unit 115 may include, for example, an HDD or an SSD. The auxiliary storage unit 115 may also include non-volatile memory such as ReRAM, PRAM, FeRAM, MRAM, or flash memory.

[0108] The weighting coefficients 11 and 12 obtained by learning the neural network model of one embodiment of the present invention are stored in the auxiliary storage unit 115. Note that the weighting coefficients 11 and 12 may also be stored in the main storage unit 114.

[0109] The communication unit 116 has a function of transmitting and receiving data to and from devices provided outside the information processing device 110. The communication unit 116 can also have a function of supplying data to a network and a function of acquiring data from the network.

[0110] The information processing device 120 includes an imaging unit 121, an output unit 122, a calculation unit 123, a main memory unit 124, an auxiliary memory unit 125, and a communication unit 126. Note that the above description can be taken into consideration for the description of the information processing device 120 and the components of the information processing device 120.

[0111] The communication unit 126 has a function of transmitting and receiving data to and from devices provided outside the information processing device 120. The communication unit 126 can also have a function of supplying data to a network and a function of acquiring data from the network.

[0112] The calculation unit 123 has the function of performing predetermined calculation processing on data transmitted to the calculation unit 123 via a transmission path 127 from, for example, the imaging unit 121, the main memory unit 124, the auxiliary memory unit 125, the communication unit 126, etc.

[0113] Here, when the neural network model of one embodiment of the present invention is applied to the calculation unit 113 and the calculation unit 123, for example, the calculation unit 113 can acquire weighting coefficients 11 and 12 by learning, and supply the weighting coefficients 11 and 12 from the information processing device 110 to the information processing device 120. As a result, even if the calculation unit 123 provided in the information processing device 120 does not perform learning, it can perform calculation processing using the neural network model on data input to the calculation unit 123 based on the weighting coefficients 11 and 12 acquired by the calculation unit 113. Therefore, the calculation processing capability of the calculation unit 123 can be made lower than that of the calculation unit 113.

[0114] When the calculation unit 113 acquires the weighting coefficients 11 and 12 and supplies them from the information processing device 110 to the information processing device 120, the information processing device 110 can be provided in, for example, a server. Note that when the information processing device 110 is provided in the server, the information processing device 110 does not need to be provided with the imaging unit 111 and the output unit 112. In other words, the imaging unit 111 and the output unit 112 may be provided outside the information processing device 110.

[0115] Furthermore, as described above, the information processing device 120 can be provided in an information terminal such as a smartphone, tablet, or personal computer. Furthermore, at least some of the components of the information processing device 110 and at least some of the components of the information processing device 120 may both be provided in a server. For example, the calculation unit 113 and the calculation unit 123 may be provided in the server. In this case, for example, data acquired by the information terminal is supplied to the calculation unit 123 via a network, and the calculation unit 123 provided in the server performs estimation or the like on the data. Then, the estimation result is supplied to the information terminal via the network, allowing the information terminal to acquire the estimation result.

[0116] 8B and the calculation unit 113 performs learning to obtain the weighting coefficients 11 and 12, the data 21 shown in FIG. 3A does not need to be obtained by the imaging unit 111. For example, the imaging unit 121 may perform imaging to obtain image data that will become the data 21, and the image data may be supplied from the information processing device 120 to the information processing device 110. In this case, the information processing device 110 does not need to be provided with the imaging unit 111.

[0117] <Configuration example of imaging unit> FIG. 9 is a block diagram illustrating an example of the configuration of the imaging unit 111 and the imaging unit 121. The imaging unit includes a pixel array 300, a circuit 201, a circuit 302, a circuit 303, a circuit 304, a circuit 305, and a circuit 306. Note that the circuit 201 and the circuits 301 to 306 are not limited to a single circuit configuration and may be configured by a combination of multiple circuits. Alternatively, multiple circuits described above may be integrated. Furthermore, circuits other than those described above may be connected. Furthermore, the circuit 201, the circuit 301, the circuit 302, the circuit 303, the circuit 304, the circuit 305, and the circuit 306 may be provided in the calculation unit 113 or the calculation unit 123.

[0118] The pixel array 300 has an imaging function and a calculation function. The circuits 201 and 302 have a calculation function. The circuit 302 has a calculation function or a data conversion function. The circuits 303, 304, and 306 have a selection function. The circuit 303 is electrically connected to the pixel block 200 through a wiring 424. The circuit 304 is electrically connected to the pixel block 200 through a wiring 423. The circuit 305 has a function of supplying a potential for a product-sum calculation to the pixel. A shift register, a decoder, or the like can be used as the circuit having the selection function. The circuit 306 is electrically connected to the pixel block 200 through a wiring 413. Note that the circuits 301 and 302 may be provided externally.

[0119] 10 , the pixel array 300 includes a plurality of pixel blocks 200. As shown in FIG. 10 , the pixel block 200 includes a plurality of pixels 400 arranged in a matrix, and each pixel 400 is electrically connected to a circuit 201 via a wiring 412. Note that the circuit 201 can also be provided within the pixel block 200.

[0120] In addition, the pixel 400 is electrically connected to the adjacent pixel 400 via a transistor 450 (transistors 450a to 450f). The function of the transistor 450 will be described later.

[0121] The pixel 400 can acquire image data and generate data by adding the image data and a weighting factor. While the pixel block 200 has 3x3 pixels in FIG. 10 as an example, this is not limiting. For example, it can have 2x2, 4x4, or the like. Alternatively, the number of pixels in the horizontal and vertical directions may be different. Furthermore, some pixels may be shared between adjacent pixel blocks.

[0122] The pixel block 200 and the circuit 201 can be operated as a multiply-accumulate circuit.

[0123] As shown in FIG. 11, the pixel 400 can include a photoelectric conversion device 401, a transistor 402, a transistor 403, a transistor 404, a transistor 405, a transistor 406, and a capacitor 407.

[0124] One electrode of the photoelectric conversion device 401 is electrically connected to one of the source and drain of the transistor 402. The other of the source and drain of the transistor 402 is electrically connected to one of the source and drain of the transistor 403, the gate of the transistor 404, and one electrode of the capacitor 407. One of the source and drain of the transistor 404 is electrically connected to one of the source and drain of the transistor 405. The other electrode of the capacitor 407 is electrically connected to one of the source and drain of the transistor 406.

[0125] The other electrode of the photoelectric conversion device 401 is electrically connected to a wiring 414. The other of the source and the drain of the transistor 403 is electrically connected to a wiring 415. The other of the source and the drain of the transistor 405 is electrically connected to a wiring 412. The other of the source and the drain of the transistor 404 is electrically connected to a GND wiring or the like. The other of the source and the drain of the transistor 406 is electrically connected to a wiring 411. The other electrode of the capacitor 407 is electrically connected to a wiring 417.

[0126] A gate of the transistor 402 is electrically connected to a wiring 421. A gate of the transistor 403 is electrically connected to a wiring 422. A gate of the transistor 405 is electrically connected to a wiring 423. A gate of the transistor 406 is electrically connected to a wiring 424.

[0127] Here, the electrical connection point between the other of the source or drain of the transistor 402, the one of the source or drain of the transistor 403, one electrode of the capacitor 407, and the gate of the transistor 404 is referred to as a node FD. Also, the electrical connection point between the other electrode of the capacitor 407 and the one of the source or drain of the transistor 406 is referred to as a node FDW.

[0128] The wiring 414 and the wiring 415 can function as power supply lines. For example, the wiring 414 can function as a high-potential power supply line, and the wiring 415 can function as a low-potential power supply line. The wirings 421, 422, 423, and 424 can function as signal lines that control the conduction of each transistor. The wiring 411 can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel 400. The wiring 412 can function as a wiring that electrically connects the pixel 400 and the circuit 201. The wiring 417 can function as a wiring that electrically connects the other electrode of the capacitor 407 of the pixel to the other electrode of the capacitor 407 of another pixel through a transistor 450 (see FIG. 10).

[0129] Note that the wiring 412 may be electrically connected to an amplifier circuit or a gain adjustment circuit.

[0130] A photodiode can be used as the photoelectric conversion device 401. Any type of photodiode can be used, including a Si photodiode having silicon in the photoelectric conversion layer and an organic photodiode having an organic photoconductive film in the photoelectric conversion layer. Note that, if it is desired to increase the light detection sensitivity in low illuminance, it is preferable to use an avalanche photodiode.

[0131] The transistor 402 can have a function of controlling the potential of the node FD. The transistor 403 can have a function of initializing the potential of the node FD. The transistor 404 can have a function of controlling the current flowing from the circuit 201 in accordance with the potential of the node FD. The transistor 405 can have a function of selecting a pixel. The transistor 406 can have a function of supplying a potential corresponding to a weighting coefficient to the node FDW.

[0132] When an avalanche photodiode is used for the photoelectric conversion device 401, a high voltage may be applied, and therefore a high-voltage transistor is preferably used as a transistor connected to the photoelectric conversion device 401. For example, a transistor using a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) can be used as the high-voltage transistor. Specifically, an OS transistor is preferably used as the transistor 402.

[0133] In addition, OS transistors have an extremely low off-state current. By using OS transistors for the transistors 402, 403, and 406, the period during which charges can be held at the nodes FD and FDW can be significantly extended. Therefore, a global shutter system in which charges are simultaneously accumulated in all pixels can be applied without complicating the circuit configuration or operation method. Furthermore, while image data is held in the node FD, multiple calculations can be performed using the image data.

[0134] On the other hand, it may be desirable for the transistor 404 to have excellent amplification characteristics. Also, it may be preferable to use a transistor with high mobility that can operate at high speed as the transistor 406. Therefore, the transistors 404 and 406 may be transistors using silicon for their channel formation regions (hereinafter referred to as Si transistors).

[0135] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Furthermore, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single-crystal silicon).

[0136] The potential of the node FD in the pixel 400 is determined by a potential obtained by adding a reset potential supplied from the wiring 415 and a potential (image data) generated by photoelectric conversion by the photoelectric conversion device 401. Alternatively, the potential is determined by capacitively coupling a potential corresponding to a weighting factor supplied from the wiring 411. Therefore, a current corresponding to data obtained by adding an arbitrary weighting factor to image data can flow through the transistor 405.

[0137] The above is an example of the circuit configuration of the pixel 400, and the photoelectric conversion operation can be performed with other circuit configurations.

[0138] 10, the pixels 400 are electrically connected to each other through wirings 412. The circuit 201 can perform calculations using the sum of currents flowing through the transistors 404 of the pixels 400.

[0139] The circuit 201 includes a capacitor 202 , a transistor 203 , a transistor 204 , a transistor 205 , a transistor 206 , and a resistor 207 .

[0140] One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203. One of the source or drain of the transistor 203 is electrically connected to the gate of the transistor 204. One of the source or drain of the transistor 204 is electrically connected to one of the source or drain of the transistor 205. One of the source or drain of the transistor 205 is electrically connected to one of the source or drain of the transistor 206. One electrode of the resistor 207 is electrically connected to the other electrode of the capacitor 202.

[0141] The other electrode of the capacitor 202 is electrically connected to a wiring 412. The other of the source and the drain of the transistor 203 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 205 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 212. The other electrode of the resistor 207 is electrically connected to a wiring 217.

[0142] The wirings 217, 218, and 219 can function as power supply lines. For example, the wiring 218 can function as a wiring that supplies a dedicated potential for readout. The wirings 217 and 219 can function as high-potential power supply lines. The wirings 213, 215, and 216 can function as signal lines that control the conduction of each transistor. The wiring 212 is an output line and can be electrically connected to, for example, the circuit 301 shown in FIG. 9.

[0143] The transistor 203 can have a function of resetting the potential of the wiring 211 to the potential of the wiring 218. The wiring 211 is a wiring connected to one electrode of the capacitor 202, one of the source and the drain of the transistor 203, and the gate of the transistor 204. The transistors 204 and 205 can function as source follower circuits. The transistor 206 can have a function of controlling reading. Note that the circuit 201 has a function as a correlated double sampling circuit (CDS circuit) and can be replaced with a circuit having the same function.

[0144] In one aspect of the present invention, offset components other than the product of image data (X) and a weighting coefficient (W) are removed to extract the target WX. WX can be calculated using data for the same pixel with and without imaging, and data when weights are applied to each of these.

[0145] The current (I p ) is the sum of kΣ(XV th ) 2 , the current (I p ) is the sum of kΣ(W+XV th ) 2 In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(WVth ) 2 where k is a constant, V th is the threshold voltage of transistor 405.

[0146] First, calculate the difference (data A) between the captured data and the weighted data. kΣ((XV th ) 2 -(W+XV th ) 2 )=kΣ(-W 2 -2W·X+2W·V th )

[0147] Next, calculate the difference (data B) between the data without imaging and the data with weighting added to the data without imaging. kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W 2 +2W·V th )

[0148] Then, take the difference between data A and data B. kΣ(-W 2 -2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(-2W·X). In other words, it is possible to remove offset components other than the product of the image data (X) and the weighting coefficient (W).

[0149] The circuit 201 can read out data A and data B. Note that the difference between data A and data B can be calculated by the circuit 301, for example.

[0150] Here, the weights supplied to the entire pixel block 200 function as a filter. For example, a convolution filter of a convolutional neural network (CNN) can be used as the filter. Alternatively, an image processing filter such as an edge extraction filter can be used. Examples of edge extraction filters include the Laplacian filter shown in FIG. 12A, the Prewitt filter shown in FIG. 12B, and the Sobel filter shown in FIG. 12C.

[0151] If the pixel block 200 has 3 × 3 pixels 400, the elements of the edge extraction filter can be assigned as weights to each pixel 400 and supplied. As described above, data A and data B can be calculated using data with and without imaging and data when weights are applied to each of the data. Here, the data with and without imaging is data with no weight applied, which can be said to be data with a weight of 0 applied to all pixels 400.

[0152] 12A to 12C are filters in which the sum (ΣΔW / N, N is the number of elements) of the filter elements (weight: ΔW) is 0. Therefore, even if an operation to supply ΔW=0 from another circuit is not performed, by performing an operation to obtain ΣΔW / N, it is possible to obtain data in which ΔW=0 is added to all pixels 400.

[0153] This operation corresponds to turning on the transistors 450 (transistors 450a to 450f) provided between the pixels 400 (see FIG. 10). By turning on the transistors 450, the nodes FDW of the pixels 400 are all short-circuited via the wiring 417. At this time, the charges accumulated in the nodes FDW of the pixels 400 are redistributed, and when the edge extraction filters illustrated in FIGS. 12A to 12C are used, the potential (ΔW) of the nodes FDW becomes 0 or approximately 0. Therefore, data to which the equivalent of ΔW=0 has been added can be acquired.

[0154] Note that when rewriting the weight (ΔW) by supplying charge from a circuit outside the pixel array 300, it takes time to complete the rewriting due to factors such as the capacitance of the long-distance wiring 411. On the other hand, the pixel block 200 is a very small area, and the wiring 417 is short and has a small capacitance. Therefore, in the operation of redistributing the charge accumulated in the node FDW within the pixel block 200, the weight (ΔW) can be rewritten quickly.

[0155] 10 illustrates a configuration in which the transistors 450a to 450f are electrically connected to different gate lines (wirings 413a to 413f). In this configuration, the conduction of the transistors 450a to 450f can be controlled independently, and an operation for obtaining ΣΔW / N can be selectively performed.

[0156] 12B or 12C, there are pixels to which ΔW=0 is initially supplied. Assuming that ΣΔW / N=0, the pixels to which ΔW=0 is supplied may be excluded from the pixels to be summed. By excluding these pixels, it is no longer necessary to supply a potential for operating some of the transistors 450a to 450f, thereby reducing power consumption.

[0157] The data resulting from the product-sum operation output from the circuit 201 is sequentially input to the circuit 301. The circuit 301 may have various other operation functions in addition to the function of calculating the difference between data A and data B. For example, the circuit 301 may have the same configuration as the circuit 201. Alternatively, the function of the circuit 301 may be replaced by software processing.

[0158] The circuit 301 may also include a circuit that performs activation function calculations. For example, a comparator circuit can be used for this circuit. The comparator circuit compares input data with a set threshold value and outputs the result as binary data. In other words, the pixel block 200 and the circuit 301 can function as part of a neural network.

[0159] Data output from the circuit 301 is sequentially input to the circuit 302. The circuit 302 can have a configuration including, for example, a latch circuit and a shift register. With this configuration, parallel-serial conversion can be performed, and data input in parallel can be output to the wiring 311 as serial data.

[0160] For example, if the neural network model 10 having the configuration shown in FIG. 1A or 1B is applied to the calculation unit 113 and the calculation unit 123, the data output from the wiring 311 can be input to the layer L_1. Therefore, the layer L_1 can be used as the input layer of the neural network NN1. Furthermore, when the neural network model 10 having the configuration shown in FIG. 1A or 1B performs training, the data output from the wiring 311 can be used as the data 21 shown in FIG. 3A, and data obtained by adding noise to the data 21 can be used as the data 22. The noise can be, for example, Gaussian noise. As described above, even if the data output from the wiring 311 contains noise, it is possible to prevent the noise from degrading the accuracy of the inference of the neural network model applied to the calculation unit 113 and the calculation unit 123.

[0161] [Pixel configuration example] 13A is a diagram showing an example of the configuration of a pixel 400. The pixel 400 can have a stacked structure of a layer 561 and a layer 563.

[0162] The layer 561 includes the photoelectric conversion device 401. The photoelectric conversion device 401 can include a layer 565a and a layer 565b as shown in Fig. 13B. Note that the term "layer" may be replaced with "region" in some cases.

[0163] 13B is a pn junction photodiode, and for example, a p-type semiconductor may be used for the layer 565a and an n-type semiconductor may be used for the layer 565b. Alternatively, an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.

[0164] The pn junction photodiode can be typically formed using single crystal silicon.

[0165] 13C, the photoelectric conversion device 401 included in the layer 561 may be a stack of layers 566a, 566b, 566c, and 566d. The photoelectric conversion device 401 shown in FIG. 13C is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0166] The layer 566a is preferably a low-resistance metal layer, etc. For example, aluminum, titanium, tungsten, tantalum, silver, or a laminate of these may be used.

[0167] The layer 566d is preferably a conductive layer that has a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0168] The layers 566b and 566c of the photoelectric conversion unit may be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material, which is a p-type semiconductor, and the layer 566c is made of an n-type semiconductor such as gallium oxide.

[0169] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In these photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers advantages in terms of production, such as the ability to fabricate thin-film photoelectric conversion layers. Thin films of selenium-based materials can be formed using vacuum deposition, sputtering, or other methods.

[0170] As the selenium-based material, crystalline selenium such as single crystal selenium or polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS), etc. can be used.

[0171] The n-type semiconductor is preferably formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer and can reduce dark current.

[0172] 13D, the photoelectric conversion device 401 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e. The photoelectric conversion device 401 shown in FIG. 13D is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0173] One of the layer 567b and the layer 567d of the photoelectric conversion portion can be a hole-transporting layer, the other of the layer 567b and the layer 567d can be an electron-transporting layer, and the layer 567c can be a photoelectric conversion layer.

[0174] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C70 Fullerenes such as these, or derivatives thereof, can be used.

[0175] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.

[0176] 13A includes, for example, a silicon substrate. Si transistors and the like are provided over the silicon substrate. The pixel 400 can be formed using the Si transistors. In addition, the circuit 201 and the circuits 301 to 306 shown in FIG. 9 can be formed.

[0177] Next, the layered structure of the imaging device will be described using cross-sectional views. Note that the elements such as insulating layers and conductive layers shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Furthermore, the layered structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0178] 14 includes a layer 560, a layer 561, and a layer 563. In FIG. 14, the transistors 402 and 403 are shown as elements provided in the layer 563; however, other elements such as transistors 404 to 406 may also be provided in the layer 563.

[0179] The layer 563 includes a silicon substrate 632, an insulating layer 633, an insulating layer 634, an insulating layer 635, and an insulating layer 637. Also, a conductive layer 636 is provided.

[0180] The insulating layers 634, 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 633 functions as a protective film. The conductive layer 636 is electrically connected to the wiring 414 shown in FIG.

[0181] The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin.The protective film may be, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like.

[0182] The conductive layer may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be made of multiple layers composed of different materials.

[0183] The Si transistor shown in Fig. 14 is a fin type having a channel formation region in a silicon substrate. A cross section in the channel width direction (a cross section taken along A1-A2 in layer 563 in Fig. 14) is shown in Fig. 15A. The Si transistor may also be a planar type, as shown in Fig. 15B.

[0184] 15C, the transistor may have a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single-crystal silicon (SOI: Silicon on Insulator) formed on an insulating layer 546 on a silicon substrate 632.

[0185] The layer 561 is provided with a photoelectric conversion device 401. The photoelectric conversion device 401 can be formed on the layer 563. Fig. 14 shows a configuration in which the organic photoconductive film shown in Fig. 13D is used as the photoelectric conversion layer for the photoelectric conversion device 401. Here, the layer 567a is the cathode, and the layer 567e is the anode.

[0186] The layer 561 includes an insulating layer 651, an insulating layer 652, an insulating layer 653, an insulating layer 654, and a conductive layer 655.

[0187] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 401 and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. An organic insulating film or the like is preferably used as the element isolation layer.

[0188] The layer 567a corresponding to the cathode of the photoelectric conversion device 401 is electrically connected to one of the source and the drain of the transistor 402 included in the layer 563. The layer 567e corresponding to the anode of the photoelectric conversion device 401 is electrically connected to the conductive layer 636 provided in the layer 563 through the conductive layer 655.

[0189] The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0190] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. In addition, the metal layer may be laminated with a dielectric film that functions as an anti-reflection film.

[0191] A color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel. Furthermore, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device can be provided that can obtain images in various wavelength regions.

[0192] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths shorter than visible light in the optical conversion layer 672. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light with wavelengths shorter than near-infrared light in the optical conversion layer 672. Alternatively, an ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths longer than visible light in the optical conversion layer 672.

[0193] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 401. An imaging device having this configuration may also be used for a radiation detector or the like.

[0194] The scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, a scintillator made of resin or ceramics dispersed with Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, or the like can be used.

[0195] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 401. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 401, thereby enabling efficient photoelectric conversion. The microlens array 673 is preferably formed from a resin, glass, or the like that is highly translucent to light of the wavelength of the object to be imaged.

[0196] 16 is a modification of the stacked structure shown in FIG. 14, and differs in the configuration of the photoelectric conversion device 401 included in the layer 561 and in a portion of the configuration of the layer 563. In the configuration shown in FIG. 16, a bonding surface is provided between the layer 561 and the layer 563.

[0197] Layer 561 includes photovoltaic device 401 , insulating layer 661 , insulating layer 662 , insulating layer 664 , insulating layer 665 , and conductive layer 685 , conductive layer 686 .

[0198] The photoelectric conversion device 401 is a pn junction photodiode formed on a silicon substrate, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. The photoelectric conversion device 401 is a buried photodiode, and a thin p-type region (part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise.

[0199] The insulating layer 661, and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer. The insulating layer 665 functions to suppress the outflow of carriers.

[0200] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. The insulating layer 665 can prevent carriers generated in the photoelectric conversion device 401 from flowing into adjacent pixels. The insulating layer 665 also has the function of preventing stray light from entering. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0201] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using an STI (Shallow Trench Isolation) method or the like. For example, the insulating layer 665 may be an inorganic insulating film made of silicon oxide, silicon nitride, or the like, or an organic insulating film made of polyimide, acrylic, or the like. The insulating layer 665 may have a multi-layer structure. It is also possible to employ a structure without providing an element isolation layer.

[0202] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 401 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0203] In the layer 563, an insulating layer 638 is formed over the insulating layer 637. Furthermore, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 402, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0204] The insulating layer 638, and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have regions buried in the insulating layer 638. The surfaces of the insulating layer 638, the conductive layers 683, and the conductive layers 684 are planarized so that they are all at the same height.

[0205] Here, the conductive layers 683 and 685 are preferably mainly composed of the same metal element, and the conductive layers 684 and 686 are preferably mainly composed of the same metal element. Also, the insulating layers 638 and 661 are preferably mainly composed of the same metal element.

[0206] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layers 683 to 686. Cu, Al, W, or Au is particularly preferable because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layer 638 and the insulating layer 661.

[0207] That is, the same metal material as described above is preferably used for the conductive layers 683 to 686. The same insulating material as described above is preferably used for the insulating layer 638 and the insulating layer 661. With this structure, the layer 563 and the layer 561 can be bonded together at the boundary between them.

[0208] The conductive layers 683 to 686 may have a multilayer structure including multiple layers, in which case the surface layers (bonding surfaces) may be made of the same metal material. The insulating layer 638 and the insulating layer 661 may also have a multilayer structure including multiple layers, in which case the surface layers (bonding surfaces) may be made of the same insulating material.

[0209] By this bonding, the conductive layer 683 and the conductive layer 685 can be electrically connected to each other, and the conductive layer 684 and the conductive layer 686 can be electrically connected to each other. Furthermore, the insulating layer 661 and the insulating layer 638 can be connected to each other with sufficient mechanical strength.

[0210] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0211] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydration through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0212] When the layer 563 and the layer 561 are bonded to each other, a metal layer and an insulating layer are mixed on each bonding surface, so that the bonding may be performed by, for example, a combination of a surface activated bonding method and a hydrophilic bonding method.

[0213] For example, a method can be used in which the surface is polished and then cleaned, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0214] By the above-described bonding, the elements of the layer 563 and the elements of the layer 561 can be electrically connected to each other.

[0215] FIG. 17 is a modified example of the laminated structure shown in FIG. 16, in which the configuration of a layer 561 and a layer 563 is partially different.

[0216] In this modified example, the transistor 402 included in the pixel 400 is provided in a layer 561. In the layer 561, the transistor 402 is formed using a Si transistor. One of the source and the drain of the transistor 402 is directly connected to one electrode of the photoelectric conversion device 401. The other of the source and the drain of the transistor 402 is electrically connected to a node FD.

[0217] 17, the layer 563 includes transistors other than the transistor 402 among the transistors included in the imaging device. Although the transistors 404 and 405 are shown in FIG. 17 as elements provided in the layer 563, other elements such as the transistor 403 and the transistor 406 can also be provided in the layer 563. Furthermore, the layer 563 of the imaging device shown in FIG. 17 includes an insulating layer 647 between the insulating layer 635 and the insulating layer 637. The insulating layer 647 functions as an interlayer insulating film and a planarizing film. [Explanation of symbols]

[0218] 10: neural network model, 10a: neural network model, 21: data, 22: data, 23: data, 24: data, 25: data set, 26: data, 27: data set, 28: data, 29: data set, 34: feature map, 35: feature map set, 36: feature map, 37: feature map set, 41: data, 42: data set, 43: output data, 44: data set, 45: data, 46: data, 100: calculation processing system, 110: information processing device, 111: imaging unit, 112: output unit, 113: calculation unit, 114: main memory unit, 115: auxiliary memory unit, 116: communication unit, 117: transmission path, 120: information processing device, 121: imaging unit, 122: output unit, 123: calculation unit, 124: main memory unit, 125: auxiliary memory unit, 126: communication unit, 127: transmission path, 200: pixel block, 201: circuit, 202: capacitor, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: resistor, 211: wiring, 212: wiring, 213: wiring, 215: wiring, 216: wiring, 217: wiring, 218: wiring, 219: wiring, 300: pixel array, 301: circuit, 302: circuit, 303: circuit, 304: circuit, 305: circuit, 306: circuit, 311: wiring, 400: pixel, 401: photoelectric conversion device, 402: transistor, 403: transistor, 404: transistor, 405: transistor, 406: transistor, 407: capacitor, 411: wiring, 412: wiring, 413: wiring, 414: wiring, 415: wiring, 417: wiring, 421: wiring, 422: wiring, 423: wiring, 424: wiring, 450: transistor, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 563: layer , 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 647: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical conversion layer, 673: microlens array,683: Conductive layer, 684: Conductive layer, 685: Conductive layer, 686: Conductive layer,

Claims

1. a first neural network and a second neural network; the first neural network has a first layer, a second layer, and a third layer; The feature map output from the first layer is input to the second layer and the second neural network; The feature map output from the second neural network is input to the third layer; A neural network model training method for causing a computer to function to output output image data in which noise has been removed from input image data, the method comprising: a first step of inputting data for obtaining initial values ​​into the first neural network to obtain initial values ​​of weight coefficients of the first neural network; a second step of acquiring weight coefficients for the second neural network by performing first learning such that a feature map output from the first layer when first data is input to the first neural network is defined as a correct feature map, a feature map output from the first layer when second data, obtained by adding noise to the first data, is input to the first neural network is defined as a training feature map, and a feature map output from the second neural network when the training feature map is input to the second neural network is consistent with the correct feature map; a third step of inputting the second data into the first neural network and performing second learning to obtain weight coefficients for the first neural network; a fourth step of inputting test data into the first neural network and evaluating the inference accuracy of the neural network model based on output data output from the first neural network; A neural network model learning method that performs the second to fourth steps until the inference accuracy reaches a specified value or higher.

2. In claim 1, the first neural network has a fourth layer, a fifth layer, and a sixth layer; The feature map output from the fourth layer is input to the fifth layer and the sixth layer, which is skip-connected to the fourth layer; the fourth layer is closer to the output layer of the first neural network than the first layer; A method for training a neural network model, wherein the third layer is closer to the output layer of the first neural network than the sixth layer.

Images