quantum devices

Abstract

To provide a quantum device that can improve coherence while securing a terminal connected to the outside.SOLUTION: A quantum device according to an embodiment includes a quantum chip having a first surface and a second surface opposite to the first surface, and in which the second surface is provided with at least a part of a qubit circuit, a first interposer having a third surface and a fourth surface opposite to the third surface, and in which the quantum chip is connected such that the second surface faces the third surface, and a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, and to which the first interposer is connected such that the fourth surface faces the fifth surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to quantum devices. [Background technology]

[0002] A quantum device in which a superconducting quantum chip is flip-chip mounted on an interposer is placed on a sample stage with a cooling function, with the side of the interposer that is not flip-chip mounted. The quantum chip is cooled from the sample stage through the interposer and maintained at a predetermined temperature. In this configuration, one side of the interposer placed on the sample stage cannot be used to draw out terminals, so there is a limit to the number of terminals that can be drawn out. However, since performance cannot be achieved unless the quantum chip is cooled to a predetermined temperature, it is desirable to achieve both cooling of the quantum chip and an increase in the number of terminals.

[0003] When increasing the number of terminals, it is necessary to maintain the constraints required to achieve the performance required for the quantum bit circuit. Specifically, to maintain the coherence of the quantum bit circuit for a long time, it is necessary to avoid exposing the dielectric, which causes power loss in the electromagnetic field, in the area around the quantum bit circuit. For this reason, it is not desirable to increase the number of terminals of the interposer by using multiple dielectric, i.e., insulating layers.

[0004] Patent Document 1 describes a configuration in which multiple quantum chips are arranged and mounted on a package substrate, and the package substrate is further connected to a circuit board. The package substrate is formed with a large number of terminals so that it can be connected to the multiple quantum chips.

[0005] Patent Document 2 describes a configuration in which a quantum chip and a package substrate are connected by sandwiching a conductive member between them. The conductive member has a large number of terminals formed thereon.

[0006] Patent Document 3 describes a configuration in which multiple quantum chips are stacked and connected to multiple interposers divided by function. The multiple interposers have many terminals formed on them. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent No. 10,380,496 [Patent Document 2] U.S. Patent No. 10,256,206 [Patent Document 3] U.S. Patent No. 9,836,699 Summary of the Invention [Problem to be solved by the invention]

[0008] In the configuration of Patent Document 1, a quantum chip is connected to the front surface of a package substrate, and a circuit board is connected to the back surface of the package substrate. The package substrate in Patent Document 1 is connected to the circuit board by soldering, and there are no vias that penetrate the wiring layers on the front and back. Therefore, space is required for the soldering connection, and there is a limit to how many terminals can be increased.

[0009] In the configuration of Patent Document 2, multiple bumps connected to multiple quantum chips are formed on one conductive member, but since the configuration does not involve stacking multiple conductive members, there is a limit to how many terminals can be increased.

[0010] The configuration of Patent Document 3 does not describe a configuration for cooling the quantum chip, and when the quantum chip is connected to multiple interposers divided by function, it is difficult to cool the quantum bit circuit so that it can perform at its full potential.

[0011] Furthermore, Patent Documents 1 to 3 do not describe the positional relationship between the formation region of the quantum bit circuit and the dielectric, raising the question of whether the coherence of the quantum bit circuit can be maintained for a long period of time. Furthermore, Patent Documents 1 to 3 do not describe a configuration for cooling the quantum chip, requiring a complex cooling mechanism to achieve sufficient performance. Thus, Patent Documents 1 to 3 have limitations on the number of terminals that can be connected to the outside, and also raise the question of whether the coherence of the quantum bit circuit can be improved.

[0012] The object of the present disclosure has been made to solve such problems, and is to provide a quantum device that can improve coherence while ensuring terminals for connection to the outside. [Means for solving the problem]

[0013] The quantum device according to the present disclosure comprises a quantum chip having a first surface and a second surface opposite to the first surface, with at least a portion of a quantum bit circuit provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, with the quantum chip connected to it so that the second surface faces the third surface; and a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, with the first interposer connected to it so that the fourth surface faces the fifth surface. [Effects of the Invention]

[0014] According to the present disclosure, it is possible to provide a quantum device that can improve coherence while ensuring terminals for connection to the outside. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view illustrating a quantum device according to a first embodiment. [Figure 2] 2 is an exploded perspective view illustrating a quantum chip and a first interposer in the quantum device according to the first embodiment. FIG. [Figure 3] 1 is a cross-sectional view illustrating a first interposer according to a first embodiment. [Figure 4] 3 is a cross-sectional view illustrating a second interposer according to the first embodiment. FIG. [Figure 5] FIG. 10 is a cross-sectional view illustrating a quantum device according to a second embodiment. [Figure 6] 10 is a cross-sectional view illustrating a quantum device according to a first modification of the second embodiment. FIG. [Figure 7] FIG. 10 is a cross-sectional view illustrating a quantum device according to a second modification of the second embodiment. [Figure 8] 10 is a plan view illustrating a recess and a counterbore of a sample stage according to a second modification of the second embodiment. FIG. [Figure 9] 10 is a cross-sectional view illustrating a quantum device according to a third modification of the second embodiment. FIG. [Figure 10] FIG. 10 is a cross-sectional view illustrating a quantum device according to a fourth modification of the second embodiment. [Figure 11] FIG. 10 is a perspective view illustrating a recess and a pressing member of a sample stage according to a fifth modified example of the second embodiment. [Figure 12] 13 is a plan view illustrating a recess and a pressing member of a sample stage according to a fifth modification of the second embodiment. FIG. [Figure 13] 10 is a cross-sectional view illustrating a quantum device according to a sixth modification of the second embodiment. FIG. [Figure 14] FIG. 11 is a cross-sectional view illustrating a quantum device according to a seventh modification of the second embodiment. [Figure 15] 13 is a plan view illustrating an example of a recess formed at the bottom of a recess of a sample stage according to a seventh modified example of the second embodiment. FIG. [Figure 16] 13 is a cross-sectional view illustrating a quantum device according to an eighth modification of the second embodiment. FIG. [Figure 17] 13 is a cross-sectional view illustrating a quantum device according to a ninth modification of the second embodiment. FIG. [Figure 18] 13 is a cross-sectional view illustrating a quantum device according to a tenth modification of the second embodiment. FIG. [Figure 19] FIG. 16 is a cross-sectional view illustrating a quantum device according to an eleventh modification of the second embodiment. [Figure 20] FIG. 20 is a cross-sectional view illustrating a quantum device according to a twelfth modification of the second embodiment. [Figure 21] FIG. 20 is a cross-sectional view illustrating a quantum device according to a thirteenth modification of the second embodiment. [Figure 22] FIG. 20 is a cross-sectional view illustrating a quantum device according to a fourteenth modification of the second embodiment. [Figure 23] FIG. 20 is a cross-sectional view illustrating a quantum device according to a fifteenth modification of the second embodiment. [Figure 24] FIG. 20 is a cross-sectional view illustrating a quantum device according to a sixteenth modification of the second embodiment. [Figure 25] FIG. 20 is a cross-sectional view illustrating a quantum device according to a seventeenth modification of the second embodiment. [Figure 26] FIG. 10 is a cross-sectional view illustrating a quantum device according to a third embodiment. [Figure 27] FIG. 10 is a cross-sectional view illustrating a quantum device according to a first modification of the third embodiment. [Figure 28] FIG. 10 is a cross-sectional view illustrating a quantum device according to a second modification of the third embodiment. [Figure 29] FIG. 10 is a cross-sectional view illustrating a quantum device according to a third modification of the third embodiment. [Figure 30] FIG. 10 is a cross-sectional view illustrating a quantum device according to a fourth modification of the third embodiment. [Figure 31] FIG. 10 is a cross-sectional view illustrating a quantum device according to a fifth modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations have been omitted as necessary.

[0017] (Embodiment 1) A quantum device according to a first embodiment will be described. The quantum device of this embodiment includes a quantum chip that utilizes superconductivity in the quantum computing domain and multiple interposers having terminals for input and output. Quantum computing is a domain in which data is manipulated using quantum mechanical phenomena (qubits). Quantum mechanical phenomena include superposition of multiple states (quantum variables simultaneously taking on multiple different states) and entanglement (a state in which multiple quantum variables are related regardless of space or time). The quantum chip is provided with a qubit circuit that generates qubits.

[0018] Fig. 1 is a cross-sectional view illustrating a quantum device according to embodiment 1. Fig. 2 is an exploded perspective view illustrating a quantum chip and a first interposer in the quantum device according to embodiment 1.

[0019] As shown in Figures 1 and 2, the quantum device 1 includes a quantum chip QCH, a first interposer 10, and a second interposer 20. The quantum device 1 further includes a first bump BP1 that connects the quantum chip QCH to the first interposer 10, and a second bump BP2 that connects the first interposer 10 to the second interposer 20. Although the first interposer 10 and the second interposer 20 are shown as two layers, the interposer is not limited to two layers and may be multi-layered with three or more layers. The following describes the configuration of each of the <quantum chip>, <first bump>, <first interposer>, <second bump>, and <second interposer>.

[0020] <Quantum chip> The quantum chip QCH includes a chip core material QC5 and a wiring layer QC4. The chip core material QC5 is, for example, shaped like a plate-like substrate, and has one plate surface and another plate surface opposite the one plate surface. One plate surface is called the first surface QC1, and the other plate surface is called the second surface QC2. Thus, the quantum chip QCH has plate surfaces that constitute the first surface QC1 and the second surface QC2. For example, the first surface QC1 and the second surface QC2 are rectangular. In this way, the quantum chip QCH and the chip core material QC5 have the first surface QC1 and the second surface QC2.

[0021] The chip core material QC5 contains, for example, silicon (Si). Note that the chip core material QC5 is not limited to silicon-containing materials, and may contain other electronic materials such as sapphire or compound semiconductor materials (group IV, group III-V, group II-VI), as long as the quantum chip QCH can utilize the quantum state. Furthermore, single crystal is preferable, but polycrystalline or amorphous materials are also acceptable.

[0022] In the quantum device 1, the second surface QC2 of the quantum chip QCH faces the first interposer 10. The second surface QC2 of the quantum chip QCH is mounted on the first interposer 10 by bumps BP1.

[0023] Here, for ease of explanation of the quantum device 1, XYZ orthogonal coordinate axes are introduced. The plane parallel to the first surface QC1 is the XY plane, and the direction perpendicular to the first surface QC1 is the Z axis direction. The +Z axis direction is the upward direction, and the -Z axis direction is the downward direction. Note that the terms upward and downward are used for ease of explanation and do not indicate the directions in which the quantum device 1 will be placed when actually used.

[0024] The wiring layer QC4 is provided on the second surface QC2 side of the chip core material QC5. The wiring layer QC4 includes a superconducting material such as niobium (Nb). Note that the superconducting material used for the wiring layer QC4 is not limited to niobium (Nb), but may also be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, or an alloy containing at least one of these.

[0025] The wiring layer QC4 includes at least a portion of the configuration of the quantum bit circuit QC6. The quantum bit circuit QC6 includes a resonator QC8, an oscillator QC9, a control circuit, and a readout circuit. The resonator QC8 includes a SQUID (Superconducting Quantum Interference Device) in which superconducting materials are connected in a ring by Josephson junctions QC7. The control circuit controls the magnetic field applied to the resonator QC8. The readout circuit reads out information from the quantum bit circuit QC6.

[0026] For example, the wiring layer QC4 includes the resonator QC8 and oscillator QC9 of the quantum bit circuit QC6. Therefore, the resonator QC8 and oscillator QC9 are formed on the second surface QC2 of the quantum chip QCH. On the other hand, the control circuit and readout circuit may be provided on the first interposer 10. The wiring layer QC4 may also include the control circuit and readout circuit. The quantum bit circuit QC6 includes a superconducting material. The material used for the Josephson junction QC7 is preferably Al, but other superconducting materials may also be used. The quantum bit circuit QC6 is configured to utilize the resonator QC8 in a quantum state in superconductivity.

[0027] The chip core material QC5 and the wiring layer QC4 are exposed on the second surface QC2 of the quantum chip QCH. The second surface QC2 preferably does not include a dielectric such as an insulating film. The wiring layer QC4 may also include a ground wiring. With this configuration, the second surface QC2 of the quantum chip QCH, together with the third surface 11 of the first interposer 10 (described later), may form a package with electromagnetic coupling. A package with electromagnetic coupling is called an electromagnetic package. In the electromagnetic package, the resonator QC8 and oscillator QC9, which include capacitive coupling, are electromagnetically integrated. Furthermore, the electromagnetic package does not include a dielectric, shielding it from external magnetic fields. This minimizes power loss of the electromagnetic field within the electromagnetic package and achieves a low tan δ. This allows quantum coherence to be maintained for a long period of time, improving high-frequency characteristics. Therefore, a high Q factor can be achieved. To achieve thermal insulation, the quantum chip QCH is preferably surrounded by a reduced pressure, such as a vacuum.

[0028] The wiring layer QC4 is connected to the first interposer 10 via the first bump BP1. Therefore, the quantum chip QCH is flip-chip mounted on the first interposer 10.

[0029] <First Bump> The first bump BP1 may include the above-mentioned superconducting material. The first bump BP1 may include the same superconducting material as the wiring layer QC4, or may include a different superconducting material from that of the wiring layer QC4. Furthermore, when the first bump BP1 includes multiple metal layers, it is preferable that at least one of the surface layers includes a superconducting material. The first bump BP1 may be a layer including Nb (the wiring surface of the quantum chip QCH) / In (Sn, Pb, and an alloy containing at least one of these) / Ti / Nb (the wiring surface of the first interposer 10) / Cu, or a layer including Nb (the wiring surface of the quantum chip QCH) / Nb (the wiring surface of the first interposer 10) / Cu, or a layer including Nb (the wiring surface of the quantum chip QCH) / In (Sn, Pb, and an alloy containing at least one of these) / Ta (the wiring surface of the first interposer 10) / Cu. Furthermore, in the case of the first bump BP1 containing Al and In, TiN may be used as a barrier layer to prevent alloying between Al and In. In this case, the first bump BP1 may be a layer containing Al (the wiring surface of the quantum chip QCH) / Ti / TiN / In (Sn, Pb, and / or an alloy containing at least one of these) / TiN / Ti / Al (the wiring surface of the first interposer 10) / Cu. Here, Ti is an adhesive layer. A preferred flip-chip connection is Nb (the wiring of the quantum chip QCH) / In / Ti / Nb (the wiring surface of the first interposer 10) / Cu, or Nb (the wiring of the quantum chip QCH) / Nb (the wiring surface of the first interposer 10) / Cu. It is preferable to add 2 to 10 μm of Cu to the 2 μm thickness of the interposer wiring layer 13 to form a bump with a diameter of 100 μm.

[0030] <First interposer> Fig. 3 is a cross-sectional view illustrating a first interposer 10 according to embodiment 1. As shown in Figs. 1 to 3, the first interposer 10 has interposer wiring layers 13 and 14, a first core material 15, and a first through via 16. Note that the first through via 16 is omitted in Fig. 1 to avoid cluttering the drawing.

[0031] The first core material 15 is, for example, a plate-shaped substrate. The first core material 15 has, for example, one plate surface and another plate surface opposite the one plate surface. One plate surface is called the third surface 11, and the other plate surface is called the fourth surface 12. Therefore, the first core material 15 has plate surfaces that constitute the third surface 11 and the fourth surface 12. For example, the third surface 11 and the fourth surface 12 are rectangular. In this way, the first core material 15 and the first interposer 10 have the third surface 11 and the fourth surface 12. The quantum chip QCH is connected to the first interposer 10 so that the second surface QC2 of the quantum chip QCH faces the third surface 11.

[0032] For example, the quantum chip QCH is arranged on the +Z-axis direction side of the first interposer 10. The wiring layer QC4 arranged on the −Z-axis direction side of the quantum chip QCH and the third surface 11 arranged on the +Z-axis direction side of the first interposer 10 are connected via a first bump BP1.

[0033] The first core material 15 contains, for example, silicon (Si). The first core material 15 is not limited to silicon-containing materials, but may contain other electronic materials such as sapphire, compound semiconductor materials (Group IV, Group III-V, Group II-VI), glass, and ceramics, as long as the quantum chip QCH can be mounted thereon. It is desirable that the first core material 15 contains the same material as the chip core material QC5. This allows the thermal expansion coefficients to match, protecting the bond between the quantum chip QCH and the first interposer 10 at cryogenic temperatures. For example, in terms of the thermal expansion coefficient, the first core material 15 preferably contains the same silicon as the chip core material QC5. The first core material 15 has a thickness of, for example, 50 μm, but is not limited to this.

[0034] The interposer wiring layer 13 is formed on the third surface 11 of the first core material 15. That is, the interposer wiring layer 13 is formed on the +Z-axis direction side of the first interposer 10. The interposer wiring layer 13 contains the above-mentioned superconducting material. Therefore, the second surface QC2 of the quantum chip QCH and the third surface 11 of the first core material 15 contain superconducting material. The interposer wiring layer 13 may contain the same superconducting material as the wiring layer QC4, or may contain a different superconducting material from that of the wiring layer QC4. For example, the interposer wiring layer 13 preferably contains Nb (0.1 μm thick), Cu (2 μm thick), and Ti, in that order from the surface to the first core material 15. The interposer wiring layer 13 is connected to the wiring layer QC4 of the quantum chip QCH via a first bump BP1.

[0035] The interposer wiring layer 13 is preferably a single layer. For example, the interposer wiring layer 13 is preferably a single layer in which a dielectric such as an insulating film is not exposed, so as not to reduce the characteristics of the electromagnetic field package. The number of layers in the interposer wiring layer 13 is preferably the same as the number of layers in the interposer wiring layer 14. In other words, the interposer wiring layer 14 is also preferably a single layer. This can reduce warping of the first interposer 10 and improve the alignment accuracy and connection reliability of the bump connection by the first bump BP1.

[0036] The interposer wiring layer 13 may include the control circuit 13a and the readout circuit 13b of the quantum bit circuit QC6. The interposer wiring layer 13 may include components of the quantum bit circuit QC6 other than the control circuit 13a and the readout circuit 13b.

[0037] The interposer wiring layer 13 may include a ground wiring. The ground wiring formed on the second surface QC2 of the quantum chip QCH may face at least a part of the ground wiring formed on the third surface 11 of the first interposer 10. This allows an electromagnetic shield surrounded by the ground wiring to be formed between the second surface QC2 and the third surface 11.

[0038] When the portion of the third surface 11 facing the second surface QC2 is viewed from above, the facing portion is occupied by the interposer wiring layer 13 and the first core material 15. That is, the interposer wiring layer 13 and the first core material 15 are exposed in the facing portion, and the insulating layer is not exposed. The second surface QC2 is occupied by the wiring layer QC4 and the chip core material QC5. That is, the wiring layer QC4 and the chip core material QC5 are exposed in the second surface QC2, and the insulating layer is not exposed. As a result, the quantum device 1 forms the aforementioned electromagnetic field package between the facing portion and the second surface QC2.

[0039] The interposer wiring layer 14 is formed on the fourth surface 12 of the first core material 15. That is, the interposer wiring layer 14 is formed on the −Z-axis direction side of the first interposer 10. The interposer wiring layer 14 may include the above-mentioned superconducting material or may include a normal conducting material. If it includes a superconducting material, the interposer wiring layer 14 may include the same superconducting material as the wiring layer QC4 and the interposer wiring layer 13, or may include a different superconducting material from the wiring layer QC4 and the interposer wiring layer 13. If it includes a normal conducting material, the interposer wiring layer 14 may include, for example, copper (Cu), silver (Ag), gold (Au), platinum (Pt), or an alloy containing at least one of these. For example, the interposer wiring layer 14 preferably includes Cu and Ti in that order from the surface to the first core material 15.

[0040] The interposer wiring layer 14 is preferably a single layer. As described above, in order to reduce warpage, the number of layers of the interposer wiring layer 14 is preferably the same as the number of layers of the interposer wiring layer 13. In other words, the interposer wiring layers 13 and 14 are preferably a single layer. The interposer wiring layer 14 may include a terminal 14a. Although only one terminal 14a is shown in the figure to avoid complication, multiple terminals 14a may be provided.

[0041] The first through via 16 penetrates the first core material 15 from the third surface 11 side to the fourth surface 12 side. A plurality of first through vias 16 are provided. The plurality of first through vias 16 connect the interposer wiring layer 13 and the interposer wiring layer 14. When the first core material 15 contains silicon, the first through vias 16 are TSVs (Through Silicon Vias). The first through vias 16, together with the second through vias 26 described below, may be provided in greater than a predetermined number. The first through vias 16 may be provided in greater than a predetermined number so that the resonant frequency generated by a capacitor structure formed by circuits on the third surface 11 and the fourth surface 12 of the first interposer, particularly circuits opposing each other in the XY plane, is higher than the signal frequency. For example, a large number of first through vias 16 may be provided so that the resonant frequency is higher than 20 GHz. For example, when the first core material 15 contains silicon, the resonance frequency can be made higher than 20 GHz by setting the interval between adjacent first through vias 16 to 1 mm or less.

[0042] The first through via 16 may contain the above-mentioned superconducting material or may contain the above-mentioned normal conducting material. If the first through via 16 contains a superconducting material, the first through via 16 may contain the same superconducting material as the wiring layer QC4, etc., or may contain a different superconducting material from the wiring layer QC4, etc. Furthermore, if the first through via 16 contains a normal conducting material, the first through via 16 may contain the same normal conducting material as the interposer wiring layer 14, or may contain a different normal conducting material from the interposer wiring layer 14. For example, the first through via 16 may be formed by forming SiO2 (e.g., a thermal oxide film) on the side wall of the through hole and filling it with Cu using Ti as an adhesion layer. Note that the diameter and material of the first through via 16 are not limited to these.

[0043] The diameter of the first through vias 16 is preferably smaller than the diameter of the second through vias 26, which will be described later. For example, the diameter of the first through vias 16 is 10 to 15 μm. By setting the diameter of the first through vias 16 to 10 to 15 μm, the coupling capacitance can be reduced, and the effect on the operation of the read circuit 13b can be suppressed. Furthermore, the quantum bit circuit QC6 can be highly integrated. However, the diameter of the first through vias 16 is not limited to this. Furthermore, it is preferable that the pitch at which the first through vias 16 are arranged in the XY plane is smaller than the pitch of the second through vias 26. This allows the quantum bit circuit QC6 to be highly integrated.

[0044] The interposer wiring layer 14 is connected to the second interposer 20 via the second bumps BP2. Thus, the first interposer 10 is mounted on the second interposer 20.

[0045] <Second Bump> The second bump BP2 may contain the above-mentioned superconducting material or may contain the above-mentioned normal-conducting material. If the second bump BP2 contains a superconducting material, it may contain the same superconducting material as the wiring layer QC4, etc., or may contain a different superconducting material from that of the wiring layer QC4. If the second bump BP2 contains a normal-conducting material, it may contain the same normal-conducting material as the interposer wiring layer 14, or may contain a different normal-conducting material from that of the interposer wiring layer 14. An underfill may be provided in the connection portion of the second bump BP2.

[0046] <Second interposer> Fig. 4 is a cross-sectional view illustrating the second interposer 20 according to the first embodiment. As shown in Figs. 1 and 4, the second interposer 20 has interposer wiring layers 23 and 24, a second core material 25, and a second through via 26. Note that the second through via 26 is omitted in Fig. 1 to avoid cluttering the drawing. The second interposer 20 is omitted in Fig. 2.

[0047] The second core material 25 is, for example, a plate-shaped substrate. The second core material 25 has, for example, one plate surface and another plate surface opposite the one plate surface. One plate surface is called the fifth surface 21, and the other plate surface is called the sixth surface 22. Therefore, the second core material 25 has plate surfaces that constitute the fifth surface 21 and the sixth surface 22. For example, the fifth surface 21 and the sixth surface 22 are rectangular. In this way, the second core material 25 and the second interposer 20 have the fifth surface 21 and the sixth surface 22. The second interposer 20 is connected to the first interposer 10 so that the fourth surface 12 of the first interposer 10 faces the fifth surface 21.

[0048] For example, the first interposer 10 is disposed on the +Z-axis direction side of the second interposer 20. The interposer wiring layer 14 disposed on the -Z-axis direction side of the first interposer 10 and the interposer wiring layer 23 disposed on the +Z-axis direction side of the second interposer 20 are connected via a second bump BP2.

[0049] The second core material 25 contains, for example, silicon (Si). The second core material 25 is not limited to silicon-containing materials, and may contain other electronic materials such as sapphire, compound semiconductor materials (Group IV, Group III-V, Group II-VI), glass, and ceramics, as long as it can mount the first interposer 10. The first core material 15 preferably contains the same material as the second core material 25. This allows the thermal expansion coefficients to match, protecting the bonded portion between the first interposer 10 and the second interposer 20 at extremely low temperatures. The chip core material QC5 preferably contains the same material as the second core material 25. This allows the bonded portion from the quantum chip QCH to the second interposer 20 to be protected at extremely low temperatures. For example, in terms of the thermal expansion coefficient, the second core material 25 preferably contains the same silicon as the chip core material QC5. The second core material 25 has a thickness of, for example, 200 μm. This allows the ground potential to be stabilized, thereby stabilizing the cooling function. However, the thickness of the second core material 25 is not limited to this.

[0050] The interposer wiring layer 23 is formed on the fifth surface 21 of the second core material 25. That is, the interposer wiring layer 23 is formed on the +Z-axis direction side of the second interposer 20. The interposer wiring layer 23 preferably contains a normal conducting material, but may contain a superconducting material. Examples of normal conducting materials include copper (Cu), silver (Ag), gold (Au), platinum (Pt), and alloys containing at least one of these. For example, the interposer wiring layer 14 preferably contains Cu and Ti in that order from the surface to the first core material 15.

[0051] The interposer wiring layer 23 may be a single layer or multiple layers, but a multi-layer wiring structure consisting of insulating layers and wiring layers is desirable. The number of layers in the interposer wiring layer 23 is desirably the same as the number of layers in the interposer wiring layer 24. This can reduce warping of the second interposer 20 and improve the alignment accuracy and connection reliability of the bump connection using the second bumps BP2.

[0052] For example, the interposer wiring layer 23 is preferably configured with a coplanar (one layer), a microstrip line (two layers), or a strip line (three layers) sandwiched between insulating layers, and three or more layers are preferred to configure a strip line with particularly excellent high frequency characteristics.Furthermore, the interposer wiring layer 23 is preferably configured with three or more layers in which a ground wiring layer, a signal wiring layer, and a ground wiring layer are stacked in this order in the thickness direction with an insulating layer sandwiched between them.

[0053] The interposer wiring layer 24 is formed on the sixth surface 22 of the second core material 25. That is, the interposer wiring layer 24 is formed on the −Z-axis direction side of the second interposer 20. The interposer wiring layer 24 preferably contains a normal conducting material, but may contain a superconducting material. The interposer wiring layer 24 may contain the same normal conducting material as the interposer wiring layer 23, or may contain a normal conducting material different from that of the interposer wiring layer 23.

[0054] The interposer wiring layer 24 may be single layer or multilayer, but a multilayer wiring structure consisting of insulating layers and wiring layers is preferable, and as mentioned above, in order to reduce warping, it is desirable that the number of layers be the same as the number of layers of the interposer wiring layer 23.

[0055] The interposer wiring layer 24 is preferably provided with a routing wiring structure that does not degrade high-frequency (10 GHz, 200 GHz, etc.) signals. For example, the interposer wiring layer 24 is preferably configured with a coplanar (one layer), a microstrip line (two layers), and a strip line (three layers) sandwiched between insulating layers, and three or more layers are preferred to configure a strip line with particularly excellent high-frequency characteristics. Furthermore, the interposer wiring layer 23 is preferably configured with three or more layers in which a ground wiring layer, a signal wiring layer, and a ground wiring layer are stacked in this order in the thickness direction, with an insulating layer sandwiched between them.

[0056] The interposer wiring layer 24 may be connected to a socket or the like. In this case, the interposer wiring layer 24 has a structure adapted to the electrical connection of the socket or the like. For example, the connection surface may be configured to be compatible with gold (Au), copper (Cu), and solder, or terminals with an electrical contact pitch of 0.3 mm or more may be provided.

[0057] The second through vias 26 penetrate the second core material 25 from the fifth surface 21 side to the sixth surface 22 side. A plurality of second through vias 26 are provided. The plurality of second through vias 26 connect the interposer wiring layer 23 and the interposer wiring layer 24. When the second core material 25 contains silicon, the second through vias 26 are TSVs (Through Silicon Vias). Similar to the first through vias 16, the second through vias 26 may be provided in greater numbers than a predetermined number so that the resonant frequency generated by the capacitor structure formed by the circuits on the fifth surface 21 and the sixth surface 22 of the second interposer, particularly the circuits opposing each other in the XY plane, is higher than the signal frequency. For example, the second through vias 26 may be provided in greater numbers than a predetermined number so that the resonant frequency is higher than 20 GHz.

[0058] The second through via 26 preferably contains a normal conducting material, but may contain a superconducting material. The second through via 26 may contain the normal conducting material described above. The second through via 26 may contain the same normal conducting material as the interposer wiring layers 23 and 24, etc., or may contain a normal conducting material different from that of the interposer wiring layers 23 and 24, etc. For example, the second through via 26 is formed by forming SiO2 (e.g., a thermal oxide film) on the side wall of the through hole and filling it with Cu using Ti as an adhesion layer.

[0059] The diameter of the second through vias 26 may be larger than the diameter of the first through vias 16. For example, in order to increase the number of mobile electrons for potential stabilization of the ground circuit, it is desirable that the diameter of the second through vias 26 be larger than the diameter of the first through vias 16. For example, in order to increase the heat capacity and improve the heat dissipation and / or cooling performance, it is desirable that the diameter of the second through vias 26 be larger than the diameter of the first through vias 16. For example, the diameter of the second through vias 26 is 50 to 100 μm. Furthermore, the pitch at which the second through vias 26 are arranged may be larger than the pitch at which the first through vias 16 are arranged.

[0060] When viewed from above, the quantum chip QCH and the first interposer 10 may have outer shapes such that the quantum chip QCH is smaller, or may be the same size, or the first interposer 10 may be smaller. If they are the same size, for example, they may be cut after WoW (Wafer on Wafer) in which the quantum chip QCH is connected to the first interposer 10. Also, when viewed from above, the first interposer 10 and the second interposer 20 may have outer shapes such that the first interposer 10 is smaller, or may be the same size, or the second interposer 20 may be smaller. If they are the same size, for example, they may be cut after WoW in which the first interposer 10 is connected to the first interposer 10.

[0061] If the first interposer 10 has an outer shape larger than the quantum chip QCH, a terminal such as a check circuit may be provided on the third surface 11 on which the quantum chip QCH is mounted, in a portion that is not shielded by the quantum chip QCH.

[0062] In the quantum device 1 of this embodiment, a quantum bit circuit QC6 is formed between the second surface QC2 of the quantum chip QCH and the third surface 11 facing the quantum chip QCH. A second interposer 20 is then stacked on the fourth surface side of the first interposer 10. This allows the number of terminals to be increased while improving coherence.

[0063] The insulating layer containing SiO2, SiN, organic materials, etc. is not exposed on the second surface QC2 and the third surface 11 facing the quantum chip QCH. This further improves coherence. Furthermore, even if the fifth surface 21 and the sixth surface 22 of the second interposer 20 include an insulating layer, the influence on the electromagnetic field package is low. Therefore, the interposer wiring layers 23 and 24 of the second interposer 20 can be multilayer wiring. This allows for the construction of a circuit that takes high-frequency characteristics into consideration and increases the number of terminals.

[0064] (Embodiment 2) Next, we will explain the quantum device according to embodiment 2. The quantum device of this embodiment is placed on a sample stage with a cooling function.

[0065] FIG. 5 is a cross-sectional view illustrating a quantum device according to the second embodiment. As shown in FIG. 5, the quantum device 2 of this embodiment is placed on a sample stage 30. Like the quantum device 1, the quantum device 2 includes a quantum chip QCH, a first interposer 10, a second interposer 20, a first bump BP1, and a second bump BP2. Note that some reference numerals have been omitted to avoid cluttering the drawing. Also in the second embodiment, an XYZ Cartesian coordinate system is used for the convenience of explaining the quantum device 2, but the orientation of the Z axis perpendicular to the first surface QC1 is different from that in FIG. 1. That is, the direction from the quantum chip QCH toward the first interposer 10 is defined as the +Z axis direction.

[0066] The sample stage 30 has a cooling function. For example, the sample stage 30 is a cold stage that can be cooled to an extremely low temperature of about 10 mK using a refrigerator. The sample stage 30 preferably contains a metal such as Cu, a Cu alloy, or Al. In the case of a sample stage 30 that contains Al, it may be insulated by anodizing. The quantum device 2 of this embodiment uses a superconducting phenomenon at extremely low temperatures of 9.2 K or less when the quantum chip QCH contains Nb as the superconducting material, or 1.2 K or less when the quantum chip contains Al. For this reason, a sample stage 30 that can be cooled to such extremely low temperatures is used.

[0067] A recess 31 is formed in the sample stage 30. For example, the recess 31 is formed in a predetermined surface 32 of the sample stage 30. The predetermined surface 32 is, for example, the upper surface facing the +Z axis direction. The recess 31 is open on the +Z axis direction side. When viewed from above, the recess 31 is, for example, rectangular.

[0068] When viewed from above through the first interposer 10 and the second interposer 20, the quantum chip QCH is smaller than the recess 31. On the other hand, when viewed from above, the first interposer 10 is larger than the recess 31. The quantum chip QCH is disposed inside the recess 31 formed in the sample stage 30, which has a cooling function. On the other hand, a portion of the first interposer 10 is in contact with the sample stage 30. For example, a portion of the third surface 11 of the first interposer 10, on which the quantum chip QCH is mounted, is in contact with the upper surface of the sample stage 30.

[0069] An insulating film may be formed or an insulating spacer may be arranged on the portion of the third surface 11 of the first interposer 10 that contacts the sample stage 30 in order to prevent electrical conduction with the sample stage 30. Furthermore, the interposer wiring layer 13 may not be formed on the portion of the third surface 11 that contacts the sample stage 30.

[0070] By bringing at least a portion of the first interposer 10 into contact with the sample stage 30, the first interposer 10 can be used as a heat flow path to cool the quantum bit circuit QC6 in the quantum chip QCH to an extremely low temperature, thereby utilizing the superconducting phenomenon. Furthermore, by bringing the first surface QC1 of the quantum chip QCH into contact with the inner surface of the recess 31, the cooling performance can be further improved. In order to improve the thermal insulation that reduces temperature changes around the quantum chip QCH, it is preferable to create a vacuum or reduced-pressure atmosphere around the quantum chip QCH.

[0071] Furthermore, by having the first surface QC1 movably contact the inner surface of the recess 31, stress and strain due to the difference in contraction between the quantum chip QCH and the sample stage 30 caused by a temperature change to an extremely low temperature can be suppressed.

[0072] At least a portion of the first interposer 10 is in contact with the sample stage 30, so that the quantum chip QCH can be cooled by the thermal conduction of the sample stage 30 via the first interposer 10, thereby improving the cooling performance.

[0073] The fourth surface 12 of the first interposer 10 can be connected to the second interposer 20 and used to the maximum extent as a terminal for extracting information from the quantum chip QCH, thereby increasing the number of information extraction terminals.

[0074] (Variation 1) Next, a first modification of the second embodiment will be described. In this modification, the first interposer 10 is also disposed inside the recess 31. FIG. 6 is a cross-sectional view illustrating a quantum device according to the first modification of the second embodiment. As shown in FIG. 6, in the quantum device 2a, the first interposer 10 is disposed in the recess 31, and a portion of the fifth surface 21 of the second interposer 20 is in contact with the upper surface of the sample stage 30.

[0075] An insulating film may be formed or an insulating spacer may be arranged on the portion of the fifth surface 21 of the second interposer 20 that contacts the sample stage 30 in order to prevent electrical conduction with the sample stage 30. Furthermore, the interposer wiring layer 23 may not be formed on the portion of the fifth surface 21 that contacts the sample stage 30.

[0076] By bringing at least a portion of the second interposer 20 into contact with the sample stage 30, the second interposer 20 can be used as a heat flow path to cool the quantum bit circuit QC6 in the quantum chip QCH to an extremely low temperature, thereby utilizing the superconducting phenomenon.

[0077] (Variation 2) Next, a second modification of the second embodiment will be described. In this modification, a countersunk recess 31 is formed. FIG. 7 is a cross-sectional view illustrating a quantum device according to the second modification of the second embodiment. FIG. 8 is a plan view illustrating the recess 31 and the countersunk recess 38 of the sample stage 30 according to the second modification of the second embodiment. As shown in FIGS. 7 and 8, in a quantum device 2b, the recess 31 of the sample stage 30 is formed in a predetermined surface 32 of the sample stage 30. The countersunk recess 38 is formed around the opening of the recess 31. As a result, a step surface 39 having a step with the predetermined surface 32 is formed around the opening of the recess 31. Therefore, the countersunk recess 38 includes the step surface 39.

[0078] The step surface 39 is, for example, parallel to the predetermined surface 32. The step surface 39 is formed around the recess 31. The step surface 39 surrounds the recess 31. The quantum chip QCH is disposed inside the recess 31. A portion of the third surface 11 of the first interposer 10 is in contact with the step surface 39. A portion of the fifth surface 21 of the second interposer 20 is in contact with the predetermined surface 32.

[0079] An insulating film may be formed on the portion of the first interposer 10 that contacts the step surface 39 of the third surface 11 in order to prevent electrical conduction with the step surface 39. Furthermore, the portion of the third surface 11 that contacts the step surface 39 does not need to have the interposer wiring layer 13 formed thereon.

[0080] An insulating film may be formed on the portion of the fifth surface 21 of the second interposer 20 that contacts the predetermined surface 32 in order to prevent electrical conduction with the predetermined surface 32. Furthermore, the portion of the fifth surface 21 that contacts the predetermined surface 32 does not need to have the interposer wiring layer 23 formed thereon.

[0081] As shown in Fig. 8, the recess 31 may have spaces on all four sides so that a quantum chip QCH can be placed. The recess 31 may also have rounded or circular corners. This can suppress the occurrence of stress and strain due to volumetric changes when cooled to extremely low temperatures. In particular, it can prevent stress concentration at the four corners due to right-angled and acute-angled shapes.

[0082] In the quantum device 2b of this modified example, the first interposer 10 is disposed inside the countersunk portion 38 and is therefore surrounded by the sample stage 30. This improves the cooling performance. Furthermore, portions of the first interposer 10 and the second interposer 20 are in contact with the sample stage 30, which also improves the cooling performance.

[0083] (Variation 3) Next, a third modification of the second embodiment will be described. This modification has an adhesive or bonding layer between the quantum chip QCH and the inner surface of the recess 31. FIG. 9 is a cross-sectional view illustrating a quantum device according to the third modification of the second embodiment. As shown in FIG. 9, in a quantum device 2c according to the third modification, at least a portion of the first surface QC1 of the quantum chip QCH may be adhered or bonded to the inner surface of the recess 31. For example, the first surface QC1 may be adhered to the sample stage 30 by an adhesive layer BL such as varnish or grease. Alternatively, the first surface QC1 may be bonded by a bonding layer ML such as a metal layer formed between the chip core material QC5 and the sample stage 30. This configuration improves the installation stability and positional accuracy of the quantum chip QCH. It also improves the thermal connection with the sample stage 30.

[0084] The adhesive layer BL or bonding layer ML may be disposed over the entire first surface QC1, or may be disposed on at least a portion of the first surface QC1, such as the periphery or center of the first surface QC1. For example, the adhesive layer BL or bonding layer ML may be formed so as to avoid the area where the quantum bit circuit QC6 is formed, as viewed from above. If the adhesive layer BL is made of an insulating material, it may resonate with the quantum bit circuit QC6 as a capacitor, resulting in a loss of overall energy. By arranging the adhesive layer BL so as to avoid the area where the quantum bit circuit QC6 is formed, resonance can be suppressed.

[0085] Furthermore, if the bonding layer ML has conductivity like a metal layer, the ground potential of the quantum chip QCH may be obtained from the sample stage 30 via the bonding layer ML, or the potential specified by the sample stage 30 may be obtained.

[0086] (Variation 4) Next, a fourth modification of the second embodiment will be described. This modification has a space between the quantum chip QCH and the inner surface of the recess 31. FIG. 10 is a cross-sectional view illustrating a quantum device according to the fourth modification of the second embodiment. As shown in FIG. 10, in a quantum device 2d of the fourth modification, the quantum chip QCH does not have to contact the sample stage 30. That is, the first surface QC1 of the quantum chip QCH may be disposed with a space between it and the inner surface of the recess 31 of the sample stage 30. This configuration makes it possible to suppress stress and strain caused by differential contraction between the quantum chip QCH and the sample stage 30 due to a temperature change to cryogenic temperatures.

[0087] (Variation 5) Next, a fifth modification of the second embodiment will be described. This modification has a pressing member on the predetermined surface 32 of the sample stage 30. FIG. 11 is a perspective view illustrating the recess 31 and pressing member of the sample stage 30 according to the fifth modification of the second embodiment. FIG. 12 is a plan view illustrating the recess 31 and pressing member of the sample stage 30 according to the fifth modification of the second embodiment. As shown in FIGS. 11 and 12, in a quantum device 2e according to the fifth modification, the recess 31 is formed on the predetermined surface 32 of the sample stage 30, for example, on the upper surface of the sample stage 30. A plurality of pressing members 33 are provided on the predetermined surface 32 around the recess 31. For example, four pressing members 33 are provided on the predetermined surface 32.

[0088] At least a portion of the side surface of the first interposer 10 contacts a pressing member 33 provided on the predetermined surface 32. For example, if the first interposer 10 is rectangular when viewed from above, the multiple pressing members 33 press the side surfaces of the first interposer 10 near each corner with their flat portions. With this configuration, the multiple pressing members 33 can press the side surfaces of the first interposer 10 with discontinuous and flat portions at diagonal corners. Therefore, when the first interposer 10 or the pressing members 33 shrink at low temperatures, they can slide linearly, making it possible to equalize the shrinkage. Note that when the second interposer 20 contacts the predetermined surface 32, the multiple pressing members 33 may press the side surfaces of the second interposer 20. Furthermore, when the first interposer 10 contacts a stepped surface 39 of the counterbore 38, the pressing members 33 may be provided on the stepped surface 39.

[0089] (Variation 6) Next, a sixth modification of the second embodiment will be described. This modification has a cooling member on the sixth surface 22 of the second interposer 20 and thermal vias inside the first interposer 10 and the second interposer 20. FIG. 13 is a cross-sectional view illustrating a quantum device according to the sixth modification of the second embodiment. In FIG. 13, the first through via 16 of the first interposer 10 and the second through via 26 of the second interposer 20 are omitted to avoid cluttering the illustration. As shown in FIG. 13, in a quantum device 2f according to the sixth modification, the sixth surface 22 of the second interposer 20 may be in contact with a cooling member 34. The cooling member 34 has a cooling function. For example, the cooling member 34 may have a cooling function by being connected to the sample stage 30. With this configuration, the sixth surface 22 of the second interposer 20 can be cooled by thermal conduction of the cooling member 34, thereby improving cooling performance.

[0090] Furthermore, the first interposer 10 may include a thermal via 17, and the second interposer 20 may include a thermal via 27. The thermal vias 17 and 27 may be members extending in a direction perpendicular to the third surface 11 of the first core material 15 and the fifth surface 21 of the second core material 25, respectively. For example, each of the thermal vias 17 and 27 may penetrate the first core material 15 and the second core material 25, respectively. In this manner, the first interposer 10 may include a thermal via 17 that penetrates from the third surface 11 to the fourth surface 12 of the first core material 15. The second interposer 20 may include a thermal via 27 that penetrates from the fifth surface 21 to the sixth surface 22 of the second core material 25. Each of the thermal vias 17 and 27 may be, for example, cylindrical or prismatic, having a central axis extending in the Z-axis direction. Each of the thermal vias 17 and 27 allows heat to transfer between the third surface 11 and the fourth surface 12 and between the fifth surface 21 and the sixth surface 22.

[0091] Each of the thermal vias 17 and 27 preferably contains a material with high thermal conductivity. Each of the thermal vias 17 and 27 may contain the above-mentioned superconducting material. Each of the thermal vias 17 and 27 may contain the same superconducting material as the wiring layer QC4, etc., or may contain a different superconducting material from the wiring layer QC4, etc. Furthermore, each of the thermal vias 17 and 27 may contain the above-mentioned normal conducting material. Each of the thermal vias 17 and 27 may contain the same normal conducting material as the interposer wiring layer 14, etc., or may contain a different normal conducting material from the interposer wiring layer 14, etc. Furthermore, each of the thermal vias 17 and 27 may contain a ceramic with high thermal conductivity, such as aluminum nitride.

[0092] The thermal via 27 may be connected to the cooling member 34. This configuration can improve the cooling performance of the quantum device 2f. Note that the quantum device 2f may be provided with only the cooling member 34 without the thermal vias 17 and 27, or may be provided with only the thermal vias 17 and 27 without the cooling member 34. Alternatively, both the cooling member 34 and the thermal vias 17 and 27 may be provided.

[0093] Furthermore, as shown in the figure, each thermal via 17, 27 may include a tapered portion with a larger diameter in the +Z-axis direction. That is, each thermal via 17, 27 may include a generally truncated cone-shaped portion whose cross section increases toward the +Z-axis direction. The tapered shape increases the thermal capacity and mitigates sudden temperature changes. This improves the temperature stability of each thermal via 17, 27. Furthermore, when the thermal via 17, 27 is in contact with the cooling member 34, the thermal contact area with the cooling member 34 increases. This more effectively promotes heat transfer. Note that the adhesive strength at the interface between each thermal via 17, 27 and the through hole may decrease when the temperature is changed from room temperature to a cryogenic temperature. For example, if a force greater than the adhesive strength is applied to the interface between each thermal via 17, 27 and the through hole due to thermal contraction, or if a material with a low elastic modulus is used for the wall, the adhesive strength may be lost due to the increased elastic modulus at cryogenic temperatures (i.e., the molecules become immobile), which may cause peeling. If the thermal vias 17 and 27 are to be peeled off, it is expected that the positions of the thermal vias 17 and 27 will move, but by including a tapered shape, it is possible to maintain contact at the interface between the thermal vias 17 and 27 and the through holes even if the vertical positions move. In the case where the thermal vias 17 and 27 move, a convex shape that maintains contact with the cooling member 34 may be formed in advance on the cooling member 34, thereby maintaining contact between the cooling member 34 and the thermal vias 17 and 27.

[0094] Furthermore, as shown in another bubble in the figure, the first interposer 10 and the second interposer 20 may include common connecting members 18 and 28 that connect the multiple thermal vias 17 and 27. For example, the multiple thermal vias 17 and 27 may be connected by plate-shaped connecting members 18 and 28 that are parallel to the XY plane. The connecting members 18 and 28 preferably contain a material with high thermal conductivity, and may contain the same material as the thermal vias 17 and 27. The multiple thermal vias 17 and 27 connected by the connecting members 18 and 28 can increase the heat capacity and suppress temperature changes.

[0095] Furthermore, a constant potential may be applied to each of the multiple thermal vias 17 and 27 connected by the connection members 18 and 28. For example, a ground potential may be applied. This allows the quantum chip QCH, the first interposer 10, and the second interposer 20 to obtain the ground potential from each of the thermal vias 17 and 27. In this case, it is preferable that each of the thermal vias 17 and 27 and each of the connection members 18 and 28 have high thermal conductivity and include an electrically conductive material.

[0096] In the first interposer 10, the region where the wiring or signal lines connected to the quantum bit circuit QC6 are mounted generates more heat than the other regions. Therefore, it is preferable to make the density of the thermal vias 17 in such regions greater than the density in other regions. For example, when the quantum chip QCH is mounted in the center of the first interposer 10 when viewed from above the first core material 15, the density of the thermal vias 17 in the central region is made greater than the density of the thermal vias 17 in the peripheral region. Furthermore, in the first interposer 10, it is preferable to make the density of the thermal vias 17 near the first through vias 16 that transmit signals from the quantum bit circuit QC6 greater than the density in other regions. This can improve cooling performance.

[0097] (Variation 7) Next, a seventh modification of the second embodiment will be described. This modification has a recess at the bottom of the recess 31 of the sample stage 30. FIG. 14 is a cross-sectional view illustrating a quantum device according to the seventh modification of the second embodiment. FIG. 15 is a plan view illustrating a recess formed at the bottom of the recess 31 of the sample stage 30 according to the seventh modification of the second embodiment. As shown in FIGS. 14 and 15, a recess 35 is formed at the bottom of the recess 31 in a quantum device 2g according to the seventh modification. As shown in FIG. 15, when viewed from above, the area of ​​the recess 35 is larger than the area QC61 in which the quantum bit circuit QC6 is formed. Therefore, the area QC61 in which the quantum bit circuit QC6 is formed is included in the area of ​​the recess 35. The peripheral portion of the first face QC1 of the quantum chip QCH may contact the bottom of the recess 31. The central portion of the first face QC1 of the quantum chip QCH covers the recess 35.

[0098] When viewed from above, the area of ​​the recess 35 may be larger than the quantum chip QCH. In this case, the first surface QC1 of the quantum chip QCH does not contact the bottom of the recess 31.

[0099] In quantum device 2g, when viewed from above, the area of ​​recess 35 is larger than area QC61 where quantum bit circuit QC6 is formed, so the distance between area QC61 where quantum bit circuit QC6 is formed and sample stage 30, which includes metal, can be increased. This suppresses the generation of a pseudo-capacitor and reduces the effects of resonance occurring in the main material, such as silicon, of chip core material QC5. This reduces the effects on the operating frequency of quantum bit circuit QC6.

[0100] (Variation 8) Next, an eighth modification of the second embodiment will be described. In this modification, the periphery of the first surface QC1 of the quantum chip QCH is adhered or bonded to the periphery of the recess 35. FIG. 16 is a cross-sectional view illustrating a quantum device according to the eighth modification of the second embodiment. As shown in FIG. 16, in a quantum device 2h according to the eighth modification, the periphery of the first surface QC1 of the quantum chip QCH may be adhered to the bottom of the recess 31 by an adhesive layer BL or may be bonded by a bonding layer ML such as a metal layer. This configuration reduces the effects of resonance, improves the installation stability of the quantum chip QCH, and improves its positional accuracy. Furthermore, the thermal connection with the sample stage 30 can be improved.

[0101] (Variation 9) Next, a ninth modification of the second embodiment will be described. In this modification, there is a space between the periphery of the first face QC1 of the quantum chip QCH and the periphery of the recess 35. FIG. 17 is a cross-sectional view illustrating a quantum device according to the ninth modification of the second embodiment. As shown in FIG. 17, in a quantum device 2i according to the ninth modification, the periphery of the first face QC1 of the quantum chip QCH does not need to contact the sample stage 30. That is, the periphery of the first face QC1 of the quantum chip QCH may be disposed with a space between it and the bottom of the recess 31. This configuration reduces the effects of resonance and suppresses stress and strain caused by differential contraction between the quantum chip QCH and the sample stage 30 due to a temperature change to cryogenic temperatures.

[0102] (Variation 10) Next, a tenth modification of the second embodiment will be described. This modification has a pillar in the recess 35. FIG. 18 is a cross-sectional view illustrating a quantum device according to the tenth modification of the second embodiment. As shown in FIG. 18, in a quantum device 2j of the tenth modification, a recess 35 is formed at the bottom of the recess 31. One or more pillars 36 are provided in the recess 35. The pillars 36 extend in a direction perpendicular to the first surface QC1 and the second surface QC2. One end of the pillar 36 is connected to the bottom of the recess 35, and the other end of the pillar 36 is in contact with the first surface QC1 of the quantum chip QCH. In this way, the quantum chip QCH is in contact with the pillar 36 extending from the bottom of the recess 35 in a direction perpendicular to the first surface QC1. The pillar 36 may be cylindrical or columnar. The one or more pillars 36 and the first surface QC1 may be bonded by an adhesive layer BL or a metal layer.

[0103] In quantum device 2j, when viewed from above, the area of ​​recess 35 is larger than area QC61 where quantum bit circuit QC6 is formed, so the distance between area QC61 where quantum bit circuit QC6 is formed and sample stage 30, which includes metal or the like, can be increased. This reduces the effects of resonance occurring in the main material, such as silicon, of chip core material Q5. At the same time, because pillar 36 contacts first surface QC1 of quantum chip QCH, cooling performance can be improved.

[0104] (Variation 11) Next, an eleventh modification of the second embodiment will be described. In this modification, a through-hole is formed in the bottom of the recess 31 of the sample stage 30. FIG. 19 is a cross-sectional view illustrating a quantum device according to the eleventh modification of the second embodiment. As shown in FIG. 19, in a quantum device 2k according to the eleventh modification, a through-hole 37 is formed in the bottom of the recess 31. When viewed from above, the area of ​​the through-hole 37 is larger than the area QC61 in which the quantum bit circuit QC6 is formed. Therefore, the area QC61 in which the quantum bit circuit QC6 is formed is included in the area of ​​the through-hole 37. The periphery of the first surface QC1 of the quantum chip QCH may be in contact with the bottom of the recess 31, or may be adhered or bonded to the bottom of the recess 31. The center of the first surface QC1 of the quantum chip QCH covers the through-hole 37.

[0105] In quantum device 2k, the area of ​​through-hole 37 is larger than area QC61 where quantum bit circuit QC6 is formed when viewed from above, so the distance between area QC61 where quantum bit circuit QC6 is formed and sample stage 30, which includes metal or the like, can be increased. This reduces the effects of resonance occurring in the main material, such as silicon, of chip core material Q5. This reduces the effects on the operating frequency of quantum bit circuit QC6.

[0106] (Variation 12) Next, a twelfth modification of the second embodiment will be described. In this modification, the quantum chip QCH fits into the recess 31 at cryogenic temperatures. FIG. 20 is a cross-sectional view illustrating a quantum device according to the twelfth modification of the second embodiment. As shown in FIG. 20, in a quantum device 21 of the twelfth modification, the quantum chip QCH fits into the recess 31 at cryogenic temperatures. Therefore, the side surface of the quantum chip QCH is in contact with the inner surface of the recess 31. As a result, the quantum chip QCH is cooled by heat conduction from the side surface, thereby improving cooling performance.

[0107] Furthermore, the first interposer 10 may be fitted into the countersunk groove 38 at extremely low temperatures. Therefore, the side surface of the first interposer 10 may contact the inner surface of the countersunk groove 38. This allows the first interposer 10 to be cooled by heat conduction from the side surface, thereby improving cooling performance.

[0108] When the quantum device 2l is cooled from room temperature to an extremely low temperature of several mK, the quantum chip QCH, the first interposer 10, and the sample stage 30 undergo volumetric changes. Therefore, taking this volumetric change into consideration, the side of the quantum chip QCH is in contact with the recess 31 and the side of the first interposer 10 is in contact with the counterbore 38 at extremely low temperatures. The ground potential of the quantum chip QCH may be obtained from the sample stage 30 via the side of the quantum chip QCH.

[0109] (Variation 13) Next, a thirteenth modification of the second embodiment will be described. In this modification, the side surface of the first interposer 10 contacts the inner surface of the recess 31. FIG. 21 is a cross-sectional view illustrating a quantum device according to the thirteenth modification of the second embodiment. As shown in FIG. 21, in a quantum device 2m of the thirteenth modification, at least a portion of the side surface of the first interposer 10 contacts the inner surface of the recess 31.

[0110] With this configuration, the third surface 11 of the first interposer 10 does not need to be in contact with the sample stage 30, making it possible to make maximum use of the third surface 11. For example, the interposer wiring layer 13 can be formed on the third surface 11 to the maximum extent.

[0111] (Variation 14) Next, a fourteenth modification of the second embodiment will be described. This modification has a movable chip pin that protrudes from the bottom of the recess 31 of the sample stage 30. FIG. 22 is a cross-sectional view illustrating a quantum device according to the fourteenth modification of the second embodiment. As shown in FIG. 22, in the quantum device 2n of the fourteenth modification, the first surface QC1 of the quantum chip QCH is in contact with a movable chip pin 19 that protrudes from the bottom of the recess 31 of the sample stage 30.

[0112] For example, one or more chip pins 19 are provided at the bottom of the recess 31. The chip pins 19 extend in a direction perpendicular to the first surface QC1. The chip pins 19 are disposed inside holes formed at the bottom of the recess 31. One end of the chip pins 19 contacts the first surface QC1 of the quantum chip QCH.

[0113] The chip pin 19 preferably includes a material with high thermal conductivity. The chip pin 19 may include the same material as the sample stage 30, or may include the above-mentioned superconducting material. The chip pin 19 may include the same superconducting material as the wiring layer QC4, etc., or may include a different superconducting material from the wiring layer QC4, etc. Furthermore, the chip pin 19 may include the above-mentioned normal conducting material. The chip pin 19 may include the same normal conducting material as the interposer wiring layer 14, etc., or may include a different normal conducting material from the interposer wiring layer 14, etc. Furthermore, the chip pin 19 may include a ceramic with high thermal conductivity, such as aluminum nitride.

[0114] A constant potential may be applied to the chip pin 19. For example, a ground potential may be applied. This allows the quantum chip QCH to obtain the ground potential from the chip pin 19. In this case, it is preferable that the chip pin 19 has high thermal conductivity and contains an electrically conductive material.

[0115] The chip pin 19 is arranged inside the hole via an elastic body such as a spring. With this configuration, the chip pin 19 contacts the first surface QC1 of the quantum chip QCH, thereby improving cooling performance. In addition, stress and strain caused by differential contraction between the quantum chip QCH and the sample stage 30 due to temperature changes to cryogenic temperatures can be suppressed.

[0116] (Variation 15) Next, a fifteenth modification of the second embodiment will be described. In this modification, the first interposer 10 contacts the side surface of the countersunk portion 38. FIG. 23 is a cross-sectional view illustrating a quantum device according to the fifteenth modification of the second embodiment. As shown in FIG. 23, in a quantum device 2o, the recess 31 of the sample stage 30 is formed in the predetermined surface 32 of the sample stage 30. The countersunk portion 38 is formed around the opening of the recess 31. As a result, a step surface 39 having a step with the predetermined surface 32 is formed around the opening of the recess 31.

[0117] In the quantum device 2o of this modified example, at least a portion of the side surface of the first interposer 10 contacts a side surface of the countersunk portion 38 between the step surface 39 and the predetermined surface 32. A portion of the third surface 11 of the first interposer 10 is disposed with a space between it and the step surface 39. This means that the third surface 11 of the first interposer 10 does not need to contact the sample stage 30, allowing the third surface 11 to be used to the fullest extent.

[0118] (Variation 16) Next, a 16th modification of the second embodiment will be described. This modification has a spacer between the third surface 11 of the first interposer 10 and the step surface 39. FIG. 24 is a cross-sectional view illustrating a quantum device according to the 16th modification of the second embodiment. As shown in FIG. 24, in a quantum device 2p, a part of the third surface 11 of the first interposer 10 is disposed between the step surface 39 and the spacer SP. That is, the spacer SP is disposed between the third surface 11 and the step surface 39. The spacer SP preferably includes an insulating material with high thermal conductivity, such as aluminum nitride, silicon carbide, sapphire, silicon, or alumina.

[0119] The quantum device 2p has a spacer SP, which improves the installation stability of the quantum chip QCH and improves its positional accuracy. It also improves the thermal connection with the sample stage 30. Furthermore, by forming the interposer wiring layer 13, the third surface 11 can be used to the fullest extent.

[0120] (Variation 17) Next, a seventeenth modification of the second embodiment will be described. In this modification, the sample stage 30 is brought into contact with the sixth surface 22 of the second interposer 20. FIG. 25 is a cross-sectional view illustrating a quantum device according to the seventeenth modification of the second embodiment. As shown in FIG. 25, in a quantum device 2q of the seventeenth modification, the sixth surface 22 of the second interposer 20 is in contact with a predetermined surface 32 of the sample stage 30.

[0121] In the quantum device 2q, the quantum chip QCH is cooled by the sample stage 30 having a cooling function via the second interposer 20 and the first interposer 10. In addition, since the sixth surface 22 of the second interposer 20 is in contact with the sample stage 30, the terminals 29 are formed on the fifth surface 21.

[0122] Although the second embodiment and modifications 1 to 17 have been described above, combinations of the respective configurations of the modifications are also included within the technical spirit of the second embodiment. For example, combinations of the configurations of the sample stage 30 of the second embodiment, modification 1, and modification 2 with modifications 4 to 14 are also within the scope of the technical spirit of the second embodiment. Furthermore, the configuration applied to the first interposer 10 may also be applied to the second interposer 20 as appropriate. Furthermore, combinations of the configurations of the first embodiment, the second embodiment, and modifications 1 to 17 are also included within the technical spirit of the first and second embodiments. Effects other than those described in the second embodiment and modifications 1 to 17 are included in the description of the first embodiment.

[0123] (Embodiment 3) Next, a description will be given of a quantum device according to embodiment 3. The quantum device of this embodiment has a socket disposed opposite to the second interposer 20.

[0124] FIG. 26 is a cross-sectional view illustrating a quantum device according to embodiment 3. As shown in FIG. 26, the quantum device 3 of this embodiment further includes a socket 40 in addition to the quantum chip QCH, first interposer 10, second interposer 20, first bumps BP1, and second bumps BP2. The configurations of the quantum chip QCH, first interposer 10, second interposer 20, first bumps BP1, and second bumps BP2 are the same as those of embodiments 1 and 2. In embodiment 3, an XYZ Cartesian coordinate system is also used for the convenience of explaining the quantum device 3, but the orientation of the Z axis perpendicular to the first surface QC1 is different from that in FIG. 1. That is, the direction from the quantum chip QCH toward the first interposer 10 is defined as the +Z axis direction.

[0125] The socket 40 is disposed opposite the second interposer 20. For example, in this embodiment, the socket 40 is disposed opposite the sixth surface 22 of the second interposer 20. The socket 40 includes a housing 45 and a movable pin 47. Note that some reference numerals are omitted in FIG. 21 to avoid cluttering the drawing.

[0126] The housing 45 has one end face 41 and another end face 42 opposite to the one end face 41. The housing 45 also has a side surface 43 connecting the periphery of the one end face 41 with the periphery of the other end face 42. The one end face 41 faces downward, for example, toward the second interposer 20, and the other end face 42 faces upward. The housing 45 holds a movable pin 47. The housing 45 may hold multiple movable pins 47.

[0127] The housing 45 preferably includes an insulating material. At least the portion of the housing 45 that comes into contact with the movable pin 47 includes an insulating material. The housing 45 also preferably includes a non-magnetic material. Furthermore, the housing 45 preferably includes a material with a thermal expansion coefficient equivalent to that of the second interposer 20.

[0128] Housing 45 may include a low linear thermal expansion composite material including aluminum oxide (Al2O3, also called alumina), mica-based machinable ceramic, aluminum nitride (AlN), zirconia (ZrO2), macor-based machinable ceramic, glass, resin, and silica filler, or may include a superconducting material as long as it is insulated from movable pin 47.

[0129] The movable pin 47 is held by the housing 45. The movable pin 47 has one end and the other end opposite the one end. The movable pin 47 extends in the Z-axis direction, with one end facing downward and the other end facing upward. Therefore, one end of the movable pin 47 protrudes from one end surface 41 of the housing 45. One end of the movable pin 47 electrically connects to, for example, the terminal 29 of the second interposer 20. The other end of the movable pin 47 protrudes from the other end surface 42 and electrically connects to the terminal of the board 50. In this manner, the housing 45 has one end surface 41 from which one end of the movable pin 47 protrudes and the other end surface 42 from which the other end of the movable pin 47 protrudes. In FIG. 26 , a space is formed between the one end surface 41 of the housing 45 and the second interposer 20, but the space need not be formed as long as one end of the movable pin 47 can contact the terminal 29. Similarly, although a space is formed between the other end surface 42 of the housing 45 and the board 50, the space does not need to be formed as long as the other end of the movable pin 47 can contact the terminal of the board 50.

[0130] One end and the other end of the movable pin 47 are electrically connected with an elastic means such as a coil spring or a leaf spring sandwiched therebetween. Of the one end and the other end of the movable pin 47 that are in electrical contact with the terminal of the second interposer 20, at least one end is movable with respect to the housing 45. The other end of the movable pin 47 may also be movable with respect to the housing 45. The other end of the movable pin 47 is electrically connected to, for example, a terminal of a board 50 on which a connector 51 that serves as input and output to the outside is formed.

[0131] The movable pin 47 may include a superconducting material or may include a normal conducting material. The movable pin 47 may include the same superconducting material as the wiring layer QC4, etc., or may include a different superconducting material from the wiring layer QC4, etc. Furthermore, the movable pin 47 may include the same normal conducting material as the interposer wiring layer 24, etc., or may include a different normal conducting material from the interposer wiring layer 24, etc. Preferably, the movable pin 47 is made of a non-magnetic material. Preferably, the movable pin 47 includes, for example, a palladium alloy, a gold alloy, beryllium copper (BeCu), gold (plated), niobium (Nb), niobium titanium (Nb-Ti), or titanium (Ti).

[0132] The socket 40 may have a positioning pin 48. The positioning pin 48 is a pin that determines the placement position of the socket 40. The positioning pin 48 is held by the housing 45. The positioning pin 48 has, for example, one end that protrudes from one end surface 41. The positioning pin 48 determines the placement position of the socket 40 by contacting the one end with a predetermined position on the sixth surface 22 of the second interposer 20. Alternatively, the placement position of the socket 40 may be determined by forming a hole in the sixth surface 22 of the second interposer 20 and inserting the positioning pin 48 into the hole. This makes it possible to prevent the socket 40 from being misaligned.

[0133] The board 50 is disposed opposite the other end surface 42 of the socket 40. The board 50 includes a connector 51, a board substrate 55, and a terminal. The board substrate 55 is, for example, plate-shaped and has an upper surface and a lower surface. The lower surface of the board substrate 55 faces the socket 40. A terminal is provided on the lower surface of the board substrate 55. A connector 51 is formed on the upper surface of the board substrate 55, which serves as input and output to the outside. The connector 51 of the board 50 is connected to the terminal of the board 50. The other end of the movable pin 47 is electrically connected to the terminal of the board 50.

[0134] The board 50, on which a connector 51 for input from and output to the outside is formed, inputs and outputs power, signals, etc. to and from the quantum chip QCH via the socket 40 and the second interposer 20.

[0135] Next, the effects of this embodiment will be described. The quantum device 3 of this embodiment has a socket 40 disposed opposite the second interposer 20. The socket 40 has a movable pin 47 that is movable relative to the housing 45 and is electrically connected to the terminal 29 of the second interposer 20. Therefore, the movable pin 47 moves in response to volumetric changes in the terminals and the like that occur when the quantum device 3 is cooled to cryogenic temperatures, thereby preventing disconnection of the terminals connected to the second interposer 20. As described above, one end and the other end of the movable pin 47 are electrically connected via elastic means such as a coil spring or a leaf spring, and the movable pin 47 is installed in a pressed-in state between the second interposer 20 and the board 50. Therefore, the movable pin 47 is in a state where pressure is applied to the second interposer 20 and the board 50 by the elastic means. In this pressurized state, the movable pin 47 moves in response to volumetric changes such as contraction that occur due to cooling, maintaining contact with the terminals and the like, and effectively preventing disconnection.

[0136] In addition, the socket 40 has the other end of the movable pin 47 electrically contacted to a terminal of the board 50 on which a connector 51 for input and output to the outside is formed, thereby ensuring a terminal for connecting to the outside.

[0137] Providing the positioning pin 48 makes it easy to determine the position of the socket 40. Furthermore, by inserting the positioning pin 48 into the hole in the sixth surface 22, it is possible to prevent the socket 40 from shifting out of position.

[0138] (Variation 1) Next, a quantum device according to Modification 1 of Embodiment 3 will be described. In the quantum device of Modification 1, at least a portion of any of the quantum chip QCH, first interposer 10, second interposer 20, and socket 40 is in contact with a sample stage 30 having a cooling function. FIG. 27 is a cross-sectional view illustrating a quantum device according to Modification 1 of Embodiment 3. As shown in FIG. 27, in a quantum device 3a, of the quantum chip QCH, first interposer 10, second interposer 20, and socket 40, for example, a side surface of the second interposer 20 is in contact with the sample stage 30 having a cooling function. The sample stage 30 includes, for example, a plate-shaped portion 30a. The plate-shaped portion 30a sandwiches the side surfaces of the second interposer 20.

[0139] In the quantum device 3a, the second interposer 20 is used as a heat flow path. Therefore, the quantum device 3a can be cooled by heat conduction from the side surfaces of the second interposer 20. In addition, the fifth surface 21 and the sixth surface 22 of the second interposer 20 can be fully utilized as terminals.

[0140] (Variation 2) Next, a second modification of the third embodiment will be described. In this modification, only a portion of the socket 40 contacts the sample stage 30. FIG. 28 is a cross-sectional view illustrating a quantum device according to the second modification of the third embodiment. As shown in FIG. 28, in a quantum device 3b, a side surface 43 of a housing 45 contacts the sample stage 30, which has a cooling function. The sample stage 30 includes, for example, a plate-shaped portion 30a. The plate-shaped portion 30a sandwiches the side surface 43 of the housing 45. Note that in the quantum device 3b, not only the side surface 43 of the housing 45 but also a portion of one end surface 41 of the housing 45 may contact the sample stage 30, or a portion of the other end surface 42 of the housing 45 may contact the sample stage 30.

[0141] In quantum device 3b, at least a portion of one end face 41, the other end face 42, and the side face 43 of housing 45 contacts sample stage 30, which has a cooling function, so quantum device 3b can be cooled by heat conduction from sample stage 30. This improves the cooling performance of quantum device 3b.

[0142] (Variation 3) Next, a third modification of the third embodiment will be described. In this modification, at least a portion of the quantum chip QCH, at least a portion of the first interposer 10, at least a portion of the second interposer 20, and at least a portion of the socket 40 are in contact with a sample stage 30 having a cooling function. Fig. 29 is a cross-sectional view illustrating a quantum device according to the third modification of the third embodiment.

[0143] 29, in a quantum device 3c, at least a portion of the quantum chip QCH, at least a portion of the first interposer 10, at least a portion of the second interposer 20, and at least a portion of the socket 40 are in contact with the sample stage 30. Specifically, for example, the quantum chip QCH and the first interposer 10 are disposed inside a recess 31 of the sample stage 30 and are in contact with the inner surface. The second interposer 20 and the socket 40 are sandwiched between plate-shaped portions 30a of the sample stage 30. Furthermore, at least one of portions of the fifth surface 21 and the sixth surface 22 of the second interposer 20 and portions of one end surface 41 and the other end surface 42 of the socket 40 may be in contact.

[0144] In the quantum device 3c, the quantum chip QCH, the first interposer 10, the second interposer 20, and the socket 40 are each partially in contact with the sample stage 30, so that the cooling performance of the quantum device 3c can be improved.

[0145] (Variation 4) Next, a fourth modification of the third embodiment will be described. The socket 40 of this modification has a heat dissipation layer in contact with the sample stage 30. FIG. 30 is a cross-sectional view illustrating a quantum device according to the fourth modification of the third embodiment. As shown in FIG. 30, in a quantum device 3d, the socket 40 has heat dissipation layers 44a, 44b, and 44c in contact with the sample stage 30, which has a cooling function.

[0146] The heat dissipation layers 44a, etc. preferably contain a material with high thermal conductivity. The heat dissipation layers 44a, etc. may contain the above-mentioned superconducting material. The heat dissipation layers 44a, etc. may contain the same superconducting material as the wiring layers QC4, etc., or may contain a different superconducting material from the wiring layers QC4, etc. Furthermore, the heat dissipation layers 44a, etc. may contain the above-mentioned normal conducting material. The heat dissipation layers 44a, etc. may contain the same normal conducting material as the interposer wiring layers 14, etc., or may contain a different normal conducting material from the interposer wiring layers 14, etc. Furthermore, the heat dissipation layers 44a, etc. may contain a ceramic with high thermal conductivity, such as aluminum nitride. If the heat dissipation layers 44a, etc. contain a conductive material, they are preferably covered with an insulating film to maintain insulation from the movable pin 47.

[0147] The heat dissipation layer 44a is disposed on one end surface 41 of the housing 45. Therefore, the heat dissipation layer 44a is exposed at the one end surface 41. The heat dissipation layer 44b is disposed on the other end surface 42 of the housing 45. Therefore, the heat dissipation layer 44b is exposed at the other end surface 42. The heat dissipation layer 44c is disposed in the center of the housing 45 parallel to the XY plane. The heat dissipation layer 44c is exposed at the side surface 43 of the housing 45. The quantum device 3d may be provided with at least one of the heat dissipation layers 44a, 44b, and 44c.

[0148] The heat dissipation layers 44a, 44b, and 44c may be in contact with the sample stage 30. For example, the heat dissipation layers 44a, 44b, and 44c are in contact with a plate-shaped portion of the sample stage 30. In this manner, the socket 40 has a heat dissipation layer exposed on at least one of the one end surface 41, the other end surface 42, and the side surface 43 of the housing 45 and in contact with the sample stage 30.

[0149] In the quantum device 3d, the socket 40 has heat dissipation layers 44a, 44b, and 44c, which improves the cooling performance of the quantum device 3d. When the heat dissipation layers 44a, 44b, and 44c are in contact with the sample stage 30, the cooling performance of the quantum device 3d can be further improved.

[0150] (Variation 5) Next, a fifth modification of the third embodiment will be described. The socket 40 of this modification is disposed on the third surface 11 of the first interposer 10 and the fifth surface 21 of the second interposer 20. Fig. 31 is a cross-sectional view illustrating a quantum device according to the fifth modification of the third embodiment.

[0151] As shown in FIG. 31, in the quantum device 3e, the socket 40 is disposed on the third surface 11 of the first interposer 10 and the fifth surface 21 of the second interposer 20. In FIG. 31, the direction perpendicular to the first surface QC1 is defined as the Z-axis direction, the first surface QC1 side is defined as the +Z-axis direction, and the second surface QC2 side is defined as the -Z-axis direction. For ease of explanation, the +Z-axis direction side is defined as the upper side, and the -Z-axis direction side is defined as the lower side. Therefore, in the quantum device 3e of this embodiment, the socket 40 is disposed above the second interposer 20 (on the +Z-axis direction side).

[0152] The sixth surface 22 of the second interposer 20 may be in contact with the sample stage 30. This allows the quantum chip QCH to be cooled via the second interposer 20. Note that the ground potential of at least one of the quantum chip QCH, the first interposer 10, and the second interposer 20 may be obtained from the sample stage 30 via the second through via 26 of the second interposer 20.

[0153] The socket 40 is arranged around the quantum chip QCH in a square or U-shape when viewed from above. One end of the movable pin 47 may be electrically connected to a terminal on the third surface 11 of the first interposer 10. Also, one end of the movable pin 47 may be electrically connected to a terminal on the fifth surface 21 of the second interposer 20. One end of the movable pin 47 is movable with respect to the housing 45. The other end of the movable pin 47 is electrically connected to a terminal of a board 50 on which a connector 51 is formed, which serves as input and output to the outside.

[0154] The board 50 is disposed opposite the other end surface 42 of the socket 40, as in the previous modification. In this modification, a board 50a may be disposed on the sample stage 30 alongside the second interposer 20. The lower surface of a board substrate 55a of the board 50a is in contact with the sample stage 30. A connector 51a and terminals are formed on the upper surface of the board substrate 55a. The socket 40 may be disposed across the fifth surface 21 of the second interposer 20 and the upper surface of the board 50a. The multiple terminals formed on the lower surface of the board 50 may be connected to each other. In this case, the terminal formed on the fifth surface 21 of the second interposer 20 may be connected to the connector 51a of the board 50a via one end of the movable pin 47a, the other end of the movable pin 47a, a terminal on the board 50, another terminal on the board 50, the other end of the movable pin 47b, one end of the movable pin 47b, and a terminal on the board 50a, in this order.

[0155] The boards 50 and 50a, on which connectors 51 and 51a for input from and output to the outside are formed, input and output power, signals, etc. between the quantum chip QCH via the socket 40 and the second interposer 20.

[0156] According to the quantum device 3e of this modification, it is possible to increase the number of connectors 51a for input and output from the outside, thereby increasing the number of terminals for connection to the outside. Furthermore, it is possible to make the sixth surface 22 of the second interposer 20 contact the sample stage 30, thereby improving the cooling performance of the quantum device 3e.

[0157] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-described embodiments 1 to 3, and can be modified as appropriate without departing from the spirit of the invention. For example, appropriate combinations of the configurations of embodiments 1 to 3 and their modifications, a configuration in which multiple quantum chips QCH are connected to a first interposer 10 and a second interposer 20, and a configuration in which multiple first interposers 10 and multiple second interposers 20 are connected to a socket 40 are also included within the scope of the technical idea of ​​the present embodiments.

[0158] A part or all of the above-described embodiments can be described as, but not limited to, the following supplementary notes.

[0159] (Appendix 1) a quantum chip having a first surface and a second surface opposite to the first surface, and at least a part of a quantum bit circuit provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, the first interposer being connected to the quantum chip such that the second surface faces the third surface; a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, the second interposer being connected to the first interposer such that the fourth surface faces the fifth surface; Equipped with The quantum chip is placed inside a recess formed in a sample stage having a cooling function, a portion of at least one of the first interposer and the second interposer is in contact with the sample stage; Quantum devices. (Appendix 2) At least a portion of the first surface is in contact with the inner surface of the recess. 10. The quantum device of claim 1. (Appendix 3) At least a portion of the first surface is adhered or bonded to the inner surface of the recess. 3. The quantum device of claim 1 or 2. (Appendix 4) The first surface is disposed with a space interposed between it and the inner surface of the recess. 4. The quantum device according to any one of claims 1 to 3. (Appendix 5) the recess is formed on a predetermined surface of the sample stage, A part of the third surface is in contact with the predetermined surface. 5. The quantum device according to any one of claims 1 to 4. (Appendix 6) At least a portion of the side surface of the first interposer is in contact with a plurality of pressing members provided on the predetermined surface. 6. The quantum device of claim 5. (Appendix 7) the first interposer is rectangular when viewed in a direction perpendicular to the third surface; the plurality of pressing members press the side surfaces of the first interposer near the respective corners with flat portions thereof; 10. The quantum device of claim 6. (Appendix 8) The sixth surface is in contact with a cooling member having a cooling function. 8. The quantum device according to any one of claims 1 to 7. (Appendix 9) the first interposer includes a first core material and a thermal via that penetrates from the third surface side to the fourth surface side of the first core material; 9. The quantum device according to any one of appendices 1 to 8. (Appendix 10) the thermal via includes a tapered portion in which the diameter on the fourth surface side is larger than the diameter on the third surface side; 10. The quantum device of claim 9. (Appendix 11) the first interposer further includes a common connection member that connects the plurality of thermal vias; 11. The quantum device of claim 9 or 10. (Appendix 12) the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; A recess is formed at the bottom of the recess, When viewed from a direction perpendicular to the second surface of the quantum chip mounted on the first interposer, the region in which the quantum bit circuit is formed is included in the recessed region. 12. The quantum device according to any one of claims 1 to 11. (Appendix 13) The quantum chip is in contact with a pillar extending from the bottom of the recess in a direction perpendicular to the second surface, 13. The quantum device of claim 12. (Appendix 14) the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; a through hole is formed in the bottom of the recess; When viewed from a direction perpendicular to the second surface of the quantum chip mounted on the first interposer, the region in which the quantum bit circuit is formed is included in the region of the through hole. 12. The quantum device according to any one of claims 1 to 11. (Appendix 15) The side surface of the quantum chip is in contact with the inner surface of the recess. 15. The quantum device according to any one of claims 1 to 14. (Appendix 16) the recess is formed on a predetermined surface of the sample stage, At least a portion of the side surface of the first interposer is in contact with the inner surface of the recess. 16. The quantum device according to any one of appendices 1 to 15. (Appendix 17) the recess is formed on a predetermined surface of the sample stage, a stepped surface having a step with respect to the predetermined surface is formed around the opening of the recess, a portion of the third surface of the first interposer contacting the step surface; 16. The quantum device according to any one of appendices 1 to 15. (Appendix 18) the recess is formed on a predetermined surface of the sample stage, a stepped surface having a step with respect to the predetermined surface is formed around the opening of the recess, At least a portion of the side surface of the first interposer is in contact with a side surface between the step surface and the predetermined surface. 16. The quantum device according to any one of appendices 1 to 15. (Appendix 19) a part of the third surface of the first interposer is disposed with a space between it and the step surface; 19. The quantum device of claim 18. (Appendix 20) a part of the third surface of the first interposer is disposed between the third surface and the step surface via a spacer; 19. The quantum device of claim 18. (Appendix 21) a quantum chip having a first surface and a second surface opposite to the first surface, and at least a part of a quantum bit circuit provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, the first interposer being connected to the quantum chip such that the second surface faces the third surface; a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, the second interposer being connected to the first interposer such that the fourth surface faces the fifth surface; a socket disposed opposite the second interposer and including a movable pin and a housing supporting the movable pin; Equipped with at least one end of the movable pin, which is in electrical contact with the terminal of the second interposer and the other end opposite to the one end, is movable with respect to the housing; The other end is electrically connected to a terminal of a board on which a connector for input / output to the outside is formed. Quantum devices. (Appendix 22) At least a part of any of the quantum chip, the first interposer, the second interposer, and the socket is in contact with a sample stage having a cooling function. 22. The quantum device of claim 21. (Appendix 23) The quantum chip is placed inside a recess formed in a sample stage having a cooling function, a portion of at least one of the first interposer and the second interposer is in contact with the sample stage; 22. The quantum device of claim 21. (Appendix 24) At least a portion of the first surface is in contact with the inner surface of the recess. 24. The quantum device of claim 23. (Appendix 25) At least a portion of the first surface is adhered or bonded to the inner surface of the recess. 24. The quantum device of claim 23. (Appendix 26) The first surface is disposed with a space interposed between it and the inner surface of the recess. 24. The quantum device of claim 23. (Appendix 27) The first surface is in contact with a movable chip pin that protrudes from the bottom of the recess. 24. The quantum device of claim 23. (Appendix 28) the recess is formed on a predetermined surface of the sample stage, A portion of the third surface of the first interposer is in contact with the predetermined surface. 28. The quantum device according to any one of appendices 23 to 27. (Appendix 29) At least a portion of the side surface of the first interposer is in contact with a plurality of pressing members provided on the predetermined surface. 29. The quantum device of claim 28. (Appendix 30) the first interposer is rectangular when viewed in a direction perpendicular to the third surface; the plurality of pressing members press the side surfaces of the first interposer near the respective corners with flat portions thereof; 20. The quantum device of claim 29. (Appendix 31) The sixth surface is in contact with a cooling member having a cooling function. 31. The quantum device according to any one of claims 23 to 30. (Appendix 32) the first interposer includes a first core material and a thermal via that penetrates from the third surface side to the fourth surface side of the first core material; 32. The quantum device according to any one of claims 23 to 31. (Appendix 33) the thermal via includes a tapered portion in which the diameter on the fourth surface side is larger than the diameter on the third surface side; 33. The quantum device of claim 32. (Appendix 34) the first interposer further includes a common connection member that connects the plurality of thermal vias; 34. The quantum device of claim 32 or 33. (Appendix 35) the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; A recess is formed at the bottom of the recess, When viewed from a direction perpendicular to the second surface of the quantum chip, the region in which the quantum bit circuit is formed is included in the recessed region. 35. The quantum device according to any one of claims 23 to 34. (Appendix 36) The quantum chip is in contact with a pillar extending from the bottom of the recess in a direction perpendicular to the second surface, 36. The quantum device of claim 35. (Appendix 37) the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; a through hole is formed in the bottom of the recess; When viewed from a direction perpendicular to the second surface of the quantum chip, the region in which the quantum bit circuit is formed is included in the region of the through hole. 35. The quantum device according to any one of claims 23 to 34. (Appendix 38) The side surface of the quantum chip is in contact with the inner surface of the recess. A quantum device according to any one of Supplementary Notes 23 to 37. (Appendix 39) the recess is formed on a predetermined surface of the sample stage, At least a portion of the side surface of the first interposer is in contact with the inner surface of the recess. 39. The quantum device according to any one of Supplementary Notes 23 to 38. (Appendix 40) the recess is formed on a predetermined surface of the sample stage, a stepped surface having a step with respect to the predetermined surface is formed around the opening of the recess, a portion of the third surface of the first interposer contacting the step surface; 39. The quantum device according to any one of Supplementary Notes 23 to 38. (Appendix 41) the recess is formed on a predetermined surface of the sample stage, a stepped surface having a step with respect to the predetermined surface is formed around the opening of the recess, At least a portion of the side surface of the first interposer is in contact with a side surface between the step surface and the predetermined surface. 39. The quantum device according to any one of Supplementary Notes 23 to 38. (Appendix 42) a part of the third surface of the first interposer is disposed with a space between it and the step surface; 42. The quantum device of claim 41. (Appendix 43) a part of the third surface of the first interposer is disposed between the third surface and the step surface via a spacer; 42. The quantum device of claim 41. (Appendix 44) The socket is disposed opposite the sixth surface. 44. The quantum device according to any one of claims 21 to 43. (Appendix 45) The socket is disposed opposite the fifth surface. 23. The quantum device of claim 21 or 22. (Appendix 46) At least a portion of the quantum chip, at least a portion of the first interposer, at least a portion of the second interposer, and at least a portion of the socket are in contact with a sample stage having a cooling function. A quantum device according to any one of Supplementary Notes 21 to 45. (Appendix 47) the housing has one end surface from which one end of the movable pin projects, another end surface from which the other end of the movable pin projects, and a side surface connecting a periphery of the one end surface and a periphery of the other end surface, At least a part of the one end surface, the other end surface, and the side surface is in contact with a sample stage having a cooling function. 47. The quantum device according to any one of claims 21 to 46. (Appendix 48) the socket has a heat dissipation layer exposed on at least one of the one end surface, the other end surface, and the side surface of the housing and in contact with the sample stage; 48. The quantum device of claim 47. (Appendix 49) The socket has a positioning pin for determining the position of the socket. A quantum device according to any one of Supplementary Notes 21 to 48. (Appendix 50) a quantum chip having a first surface and a second surface opposite to the first surface, and at least a part of a quantum bit circuit provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, the first interposer being connected to the quantum chip such that the second surface faces the third surface; a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, the second interposer being connected to the first interposer such that the fourth surface faces the fifth surface; a socket disposed opposite the second interposer and including a movable pin and a housing supporting the movable pin; Equipped with At least a part of any of the quantum chip, the first interposer, the second interposer, and the socket is in contact with a sample stage having a cooling function. Quantum devices. [Explanation of symbols]

[0160] 1, 2, 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h Quantum Devices 2i, 2j, 2k, 2l, 2m, 2n, 2o, 2p, 2q quantum devices 3, 3a, 3b, 3c, 3d, 3e quantum devices 10 First interposer 11 Page 3 12 Side 4 13 Interposer wiring layer 13a Control circuit 13b Readout circuit 14 Interposer wiring layer 14a terminal 15 First core material 16 First through via 17 Thermal via 18 Connecting member 19 Chip Pin 20 Second interposer 21 Page 5 22 Page 6 23 Interposer wiring layer 24 Interposer wiring layer 25 Second core material 26 Second through via 27 Thermal via 28 Connecting member 29 terminals 30 Sample stage 31 Recess 32 specified surface 33 Retaining member 34 Cooling element 35 dent 36 Pillar 37 Through hole 38 Countersunk 39 Step surface 40 sockets 41 One end face 42 Other end face 43 Side 44a, 44b, 44c heat dissipation layer 45 Housing 47 Movable Pin 48 Locating pin 50 boards 51 Connector 55 Board BP1 First Bump BP2 2nd Bump QC1 Side 1 QC2 2nd page QC4 wiring layer QC5 chip core material QC6 qubit circuit QC61 area QC7 Josephson junction QC8 resonator QC9 Oscillator QCH quantum chip SP Spacer

Claims

1. a quantum chip having a first surface and a second surface opposite to the first surface, and at least a part of a quantum bit circuit being provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, the first interposer being connected to the quantum chip such that the second surface faces the third surface; a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, the second interposer being connected to the first interposer such that the fourth surface faces the fifth surface; Equipped with a portion of the first interposer and a portion of the second interposer are in contact with a sample stage having a cooling function; Quantum devices.

2. the third surface of the first interposer and the fifth surface of the second interposer are in contact with the sample stage having the cooling function; The quantum device of claim 1 .

3. a recess is formed on a predetermined surface of the sample stage, and a step surface is formed around an opening of the recess; a portion of the third surface of the first interposer contacts the step surface; a portion of the fifth surface of the second interposer contacting the predetermined surface; The quantum device of claim 2 .

4. the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; A recess or a through hole is formed at the bottom of the recess, When viewed from a direction perpendicular to the second surface of the quantum chip, the region in which the quantum bit circuit is formed is included in the region of the recess or through-hole. The quantum device of claim 3 .

5. a quantum chip having a first surface and a second surface opposite to the first surface, and at least a part of a quantum bit circuit being provided on the second surface; a first interposer having a third surface and a fourth surface opposite to the third surface, the first interposer being connected to the quantum chip such that the second surface faces the third surface; a second interposer having a fifth surface and a sixth surface opposite to the fifth surface, the second interposer being connected to the first interposer such that the fourth surface faces the fifth surface; Equipped with the third surface of the first interposer is in contact with a sample stage having a cooling function; the sixth surface of the second interposer is in contact with a cooling member; Quantum devices.

6. a step surface having a step with respect to the predetermined surface is formed on a predetermined surface of the sample table, and a recess is formed on the step surface, thereby forming the step surface around an opening of the recess; the quantum chip is disposed inside the recess such that the first surface of the quantum chip faces a bottom of the recess; a portion of the third surface of the first interposer contacts the step surface; a portion of the fifth surface of the second interposer contacting the predetermined surface; The quantum device of claim 5 .

7. the quantum chip includes a quantum bit circuit in which a resonator is formed having a loop circuit in which superconducting materials are connected in a ring by Josephson junctions; a recess or a through-hole is formed in the bottom of the recess; When viewed from a direction perpendicular to the second surface of the quantum chip, the region in which the quantum bit circuit is formed is included in the region of the recess or the through-hole. The quantum device of claim 6.

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