Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes a first display region (R1), a second display region (R2) located at least on one side of the first display region (R1), a plurality of sub-pixels located in the first display region (R1) and the second display region (R2), a plurality of pixel groups (P1) located in the first display region (R1), at least one pixel group (P1) among the plurality of pixel groups (P1) including at least two sub-pixels, and a first power line (311) configured to provide a first voltage signal (ELVDD) to the pixel circuits and including a plurality of first conducting lines (L1) and a plurality of second conducting lines (L2), at least one of the plurality of first conducting lines (L1) including a first sub-wiring (L111) extending along a first direction (D1) and a second sub-wiring (L112) extending along a second direction (D2), and the second sub-wiring (L112) electrically connected to at least one of the plurality of second conducting lines (L2). The display panel provides a more stable network structure of the first power lines, reducing the voltage drop in the first power lines, and thereby providing a more uniform brightness of the display panel.

Description

[Technical Field]

[0001] This disclosure claims priority to Chinese Patent Application No. 202010621890.3, filed on June 30, 2020, the entire contents of which are incorporated herein by reference.

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device. [Background technology]

[0003] Based on the design of the under-screen camera, the display panel typically includes a high pixel density (Pixels Per Inch, PPI) area and a low PPI area. However, the light transmittance of the low PPI area of ​​a typical display panel is low, which is unfavorable for improving the display effect in the camera's imaging area. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display panel, including: a first display area; a second display area located at least on one side of the first display area; a plurality of sub-pixels located in the first display area and the second display area, wherein a density of the sub-pixels in the first display area is less than a density of the sub-pixels in the second display area, the sub-pixels including pixel circuits; a plurality of pixel groups located in the first display area, at least one pixel group among the plurality of pixel groups including at least two sub-pixels; and a first power supply line configured to provide a first voltage signal to the pixel circuits, the first power supply line including a plurality of first conducting lines and a plurality of second conducting lines, the first conductive lines extend from the second display area to the first display area and are electrically connected to the plurality of pixel groups, the plurality of second conductive lines are located in the first display area and are located between adjacent first conductive lines, the plurality of second conductive lines extend along a first direction and adjacent second conductive lines are spaced apart from each other along the first direction, the plurality of second conductive lines are electrically connected to the plurality of pixel groups, at least one of the plurality of first conductive lines includes a first sub-wiring extending along the first direction and a second sub-wiring extending along the second direction, the first direction and the second direction intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conductive lines.

[0005] For example, in a display panel according to at least one embodiment of the present disclosure, the at least two subpixels include a first subpixel and a second subpixel arranged along the first direction, at least one of the plurality of second conductive lines electrically connects the first subpixel and the second subpixel, and the second subwiring and the plurality of second conductive lines are located in different layers.

[0006] For example, in a display panel according to at least one embodiment of the present disclosure, the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistors are respectively connected to the second transistors, the second transistors are connected to the light-emitting element, and the first transistors include a first active section and a second active section connected via a conductive section.

[0007] For example, in a display panel according to at least one embodiment of the present disclosure, the second conducting line further includes a connecting arm that is spaced apart from the conductive portion of one subpixel in the pixel group that overlaps with the second conducting line in a third direction and that partially overlaps with the conductive portion in the third direction, and the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0008] For example, in a display panel according to at least one embodiment of the present disclosure, the shape of the connecting arm includes a C-shape.

[0009] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected via a plurality of wirings.

[0010] For example, a display panel according to at least one embodiment of the present disclosure further includes a connecting conductor, and the orthogonal projections on the base substrate of at least two of the plurality of wirings between the adjacent first pixel group and second pixel group are within the orthogonal projections on the base substrate of the connecting conductor.

[0011] For example, in a display panel according to at least one embodiment of the present disclosure, there are a plurality of gaps between the plurality of wirings, and the orthogonal projection of at least one of the plurality of gaps on the base substrate at least partially overlaps with the orthogonal projection of the connecting conductor on the base substrate.

[0012] For example, in a display panel according to at least one embodiment of the present disclosure, the pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light-emitting control signal line, and an initialization signal line, which respectively provide a first reset signal, a second reset signal, a gate scanning signal, a light-emitting control signal, and an initialization signal to the pixel circuit, and the plurality of wirings are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the first conducting line.

[0013] For example, in a display panel according to at least one embodiment of the present disclosure, the connecting conductor has a stopper that is arranged in the same layer as the connecting conductor and is integrally formed therewith, the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is respectively connected to the second transistor and the storage capacitor, the second transistor is connected to the light-emitting element, the first transistor includes a first active portion and a second active portion connected via a conductive portion, and the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductor are arranged at a distance from each other in the third direction and partially overlap in the third direction.

[0014] For example, in a display panel according to at least one embodiment of the present disclosure, at least a portion of the orthogonal projection of the connecting conductor on the base substrate is located between the orthogonal projections of the adjacent first and second pixel groups on the base substrate.

[0015] For example, in a display panel according to at least one embodiment of the present disclosure, the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the second conducting line of the first pixel group are connected to the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the second conducting line of the second pixel group, respectively, via the plurality of wirings.

[0016] For example, in a display panel according to at least one embodiment of the present disclosure, the connection conductor and the second conductor are located in the same layer and formed integrally, or the connection conductor and the initialization signal line are located in the same layer and formed integrally, or the connection conductor and the first conductor are located in the same layer.

[0017] For example, in a display panel according to at least one embodiment of the present disclosure, the at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged along the first direction and located on one side of the first sub-pixel and the second sub-pixel along the second direction, and are electrically connected to another of the plurality of second conducting lines, and the second sub-line is electrically connected to at least one of the plurality of second conducting lines.

[0018] For example, in a display panel according to at least one embodiment of the present disclosure, the second sub-wiring has a stopper located in a layer different from the second sub-wiring and connected by a via, and the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductive line are spaced apart from each other in the third direction and partially overlap in the third direction.

[0019] For example, in a display panel according to at least one embodiment of the present disclosure, the first direction is perpendicular to the second direction.

[0020] For example, in a display panel according to at least one embodiment of the present disclosure, the second conducting wires are arranged in order along the first direction.

[0021] For example, in a display panel according to at least one embodiment of the present disclosure, the adjacent second conductive lines are not directly connected.

[0022] For example, in a display panel according to at least one embodiment of the present disclosure, the first conducting wire and the second conducting wire are connected by a via that penetrates an insulating layer.

[0023] For example, in a display panel according to at least one embodiment of the present disclosure, the first power line further includes a third conducting wire and a fourth conducting wire, the third conducting wire extends along the second direction and extends from the second display area to the first display area, the second conducting wire is electrically connected to the third conducting wire, the fourth conducting wire extends along the second direction and is electrically connected to the fourth conducting wire, and the length of the fourth conducting wire in the second direction is less than or equal to the length of the third conducting wire in the second direction.

[0024] For example, in a display panel according to at least one embodiment of the present disclosure, the display panel includes a plurality of fourth conductive wires positioned between adjacent third conductive wires and arranged in sequence along the second direction, and the adjacent fourth conductive wires are spaced apart from each other in the second direction.

[0025] For example, in a display panel according to at least one embodiment of the present disclosure, the first conducting wire and the third conducting wire are located in the same layer, and the fourth conducting wire and the third conducting wire are located in the same layer.

[0026] For example, in a display panel according to at least one embodiment of the present disclosure, the first display region includes a plurality of light-transmitting regions located between adjacent pixel groups.

[0027] For example, in a display panel according to at least one embodiment of the present disclosure, the plurality of pixel groups and the wiring connected to the adjacent pixel groups surround the plurality of light-transmitting regions.

[0028] At least one embodiment of the present disclosure further provides a display device including a display panel according to any embodiment of the present disclosure.

[0029] For example, a display device according to at least one embodiment of the present disclosure further includes a sensor, the sensor being installed on one side of the display panel, and the orthogonal projection of the sensor on the base substrate at least partially overlapping with the first display area.

[0030] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present disclosure and do not limit the present disclosure. [Brief explanation of the drawings]

[0031] [Figure 1A] FIG. 1A is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1B] FIG. 1B is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1C] FIG. 1C is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of a second display area of ​​a display panel in accordance with at least one embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram of a first display area of ​​a display panel in accordance with at least one embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram of sub-pixels and signal lines providing signals to the sub-pixels in a display panel in accordance with at least one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram of a display panel in accordance with at least one embodiment of the present disclosure. [Figure 6A] FIG. 6A is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 6B] FIG. 6B is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 6C] FIG. 6C is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 6D] FIG. 6D is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 6E] FIG. 6E is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 6F] FIG. 6F is a diagram illustrating a pixel circuit and its stack structure according to some embodiments of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of a display panel in accordance with at least one embodiment of the present disclosure. [Figure 8A] FIG. 8A is an enlarged schematic diagram of the region A11 shown in FIG. [Figure 8B] FIG. 8B is an enlarged schematic diagram of the area A12 shown in FIG. [Figure 8C] FIG. 8C is a plan view of the semiconductor pattern of the display panel shown in FIG. [Figure 9] FIG. 9 is a plan view of the first conductive pattern layer of the display panel shown in FIG. [Figure 10] FIG. 10 is a plan view of the second conductive pattern layer of the display panel shown in FIG. [Figure 11] FIG. 11 is a plan view of the third conductive pattern layer of the display panel shown in FIG. [Figure 12] FIG. 12 is a plan view of another display panel in accordance with at least one embodiment of the present disclosure. [Figure 13] FIG. 13 is an enlarged schematic diagram of the area A21 shown in FIG. [Figure 14] FIG. 14 is a plan view of the semiconductor pattern of the display panel shown in FIG. [Figure 15] FIG. 15 is a plan view of the first conductive pattern layer of the display panel shown in FIG. [Figure 16] FIG. 16 is a plan view of the second conductive pattern layer of the display panel shown in FIG. [Figure 17] FIG. 17 is a plan view of the third conductive pattern layer of the display panel shown in FIG. [Figure 18] FIG. 18 is a schematic diagram of another display panel in accordance with at least one embodiment of the present disclosure. [Figure 19] FIG. 19 is a plan view of the semiconductor pattern of the display panel shown in FIG. [Figure 20] FIG. 20 is a plan view of the first conductive pattern layer of the display panel shown in FIG. [Figure 21]FIG. 21 is a plan view of the second conductive pattern layer of the display panel shown in FIG. [Figure 22] FIG. 22 is a plan view of the third conductive pattern layer of the display panel shown in FIG. [Figure 23] FIG. 23 is a cross-sectional schematic diagram of a pixel circuit of a display panel according to at least one embodiment of the present disclosure. [Figure 24] FIG. 24 is a schematic cross-sectional view of a display panel according to at least one embodiment of the present disclosure. [Figure 25] FIG. 25 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0032] In order to more clearly explain the objectives, technical solutions and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the described embodiments of the present disclosure, all other embodiments that can be obtained by those skilled in the art without requiring creative work fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, technical and scientific terms used in this disclosure should have the ordinary meaning that would be understood by one skilled in the art of this disclosure. The terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but are used only to distinguish between different components. Similarly, similar terms such as "comprises" or "has" mean that the element or element listed before the term covers the element or element listed after the term and its equivalents, but does not exclude other elements or elements. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. Terms such as "top," "bottom," "left," and "right" are used only to indicate relative positional relationships, and if the absolute position of the described object changes, the relative positional relationships may also change accordingly.

[0034] People love taking selfies, so a front camera is necessary. However, the front camera and sensor take up some space. Traditionally, front camera placement methods have involved using a notch screen, a waterdrop-shaped notch screen, or an AA (active area) hole, i.e., opening a hole in the AA area and placing both the camera hole and the sensor within the AA area. However, neither of these two methods can meet the needs of a full screen. Therefore, under-screen camera technology is chosen to improve the screen aperture ratio by changing the pixel density, and by placing the camera below the screen, the integrity of the full screen display is not compromised.

[0035] To achieve a bezel-less full-screen design, under-screen camera technology must be used, which requires a large aperture ratio of the display panel. Therefore, while satisfying the above requirements, how to design the display panel structure to ensure the display effect of the display panel has become an urgent issue to be solved.

[0036] At least one embodiment of the present disclosure provides a display panel, comprising: a first display area; a second display area located at least on one side of the first display area; a plurality of sub-pixels located in the first display area and the second display area, the density of the sub-pixels in the first display area being less than the density of the sub-pixels in the second display area, the sub-pixels including pixel circuits; a plurality of pixel groups located in the first display area, at least one pixel group among the plurality of pixel groups including at least two sub-pixels; and a first power supply line configured to provide a first voltage signal to the pixel circuits, the first power supply line including a plurality of first conducting lines and a plurality of second conducting lines, The conductive lines extend from the second display area to the first display area and are electrically connected to the plurality of pixel groups, the plurality of second conductive lines are located in the first display area and are located between adjacent first conductive lines, the plurality of second conductive lines extend along a first direction and adjacent second conductive lines are spaced apart from each other along the first direction, the plurality of second conductive lines include a first power line electrically connected to the plurality of pixel groups, at least one of the plurality of first conductive lines includes a first sub-wiring extending along the first direction and a second sub-wiring extending along the second direction, the first direction and the second direction intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conductive lines.

[0037] The display panel according to the embodiment of the present disclosure improves the stability of the mesh structure of the first power line and reduces the voltage drop in the first power line, thereby improving the brightness uniformity of the display panel and thereby improving the display effect in the camera imaging area.

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0039] In a typical display panel, the first power lines use a mesh structure in both the high PPI area and the low PPI area. In order to increase the stability of the mesh structure of the first power lines, reduce the voltage drop in the first power lines, and improve the brightness uniformity of the display panel, thereby improving the display effect in the camera imaging area, the display panel according to the embodiment of the present disclosure optimizes the signal lines in the low PPI area, for example, in the embodiment of the present disclosure, optimizes the horizontally and vertically arranged conductors of the mesh-like first power lines.

[0040] 1A-1C are schematic diagrams of a display panel according to some embodiments of the present disclosure. As shown in FIGS. 1A-1C, the display panel includes a first display region R1 and a second display region R2. The first display region R1 is a low pixel density (Pixels Per Inch, PPI) region, and the second display region R2 is a high PPI region. The first display region R1 is a partially light-transmitting region. As shown in FIGS. 1A-1C, the second display region R2 is located at least on one side of the first display region R1. The display panel shown in FIGS. 1A and 1B further includes a third region R3. A sensor, such as a camera, may be installed in the first display region R1 (see FIG. 1C) or in both the first display region R1 and the third region R3 (see FIGS. 1A and 1B). The third region R3 shown in FIGS. 1A and 1B may be a perforated region, i.e., a through-hole is formed by removing material at a position corresponding to the third region R3. The sensor can receive ambient light. For example, if the sensor is a camera, by implementing an under-screen camera, when the screen is used normally, the first display area corresponding to the sensor can display the screen normally, but when taking a picture with the camera, the first display area can transmit ambient light, supporting normal use. For example, the sensor is installed on the non-display side of the display panel. The sensor is also called an under-screen device.

[0041] FIG. 1A further shows a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 includes a first gate line GL1, and the plurality of data lines 313 includes a first data line DL1. The first gate line GL1 extends from the second display region R2 to the first display region R1. The first data line DL1 extends from the first display region R1 to the second display region R2. In the embodiments of the present disclosure, when an element extends from the first display region R1 to the second display region R2, the element may be understood to be located in the first display region R1 and the second display region R2, or to be understood to be extending from the second display region R2 to the first display region R1. For clarity of illustration, FIG. 1A exemplarily shows several gate lines 113 and several data lines 313, and the number of gate lines 113 and data lines 313 may be determined as needed. The plurality of gate lines 113 and the plurality of data lines 313 cross each other and are insulated from each other.

[0042] Fig. 2 is a schematic diagram of a second display region of a display panel according to at least one embodiment of the present disclosure. Fig. 3 is a schematic diagram of a first display region of a display panel according to at least one embodiment of the present disclosure. As shown in Figs. 2 and 3, the display panel includes a plurality of sub-pixels P0, each of which includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the display panel includes a plurality of pixel groups P1, which are located in a first display region R1, and at least one of the plurality of pixel groups P1 includes at least two sub-pixels. For example, in some embodiments, one pixel group P1 may include four subpixels. For example, as shown in FIG. 3, one first subpixel 101, one second subpixel 102, one third subpixel 103, and one fourth subpixel 104 constitute one pixel group P1. In other examples, one pixel group P1 may include two subpixels. For example, as shown in FIG. 5, one first subpixel 101 and one second subpixel 102 constitute one pixel group P1. For example, one pixel group P1 may further include three subpixels (see FIG. 18). The embodiments of the present disclosure are not limited thereto. For example, one pixel group P1 is a repeating unit arranged in an array in the second display region R2. As shown in FIG. 3, in the first display region R1, one pixel group P1 is also called one pixel island P1. The following embodiments are similar to this, and detailed description thereof will be omitted. The first display region R1 includes a plurality of light-transmitting regions R0 located between adjacent pixel islands P1. The light-transmitting region R0 can transmit ambient light. For example, the light-transmitting region R0 may include a base substrate and a transparent insulating layer disposed on the base substrate. The light-transmitting region R0 does not have a light-shielding structure, such as no metal wiring. For example, the light-transmitting region R0 may be located within an area surrounded by four adjacent pixel islands P1, but is not limited thereto. For example, as shown in FIG. 3, the adjacent pixel islands P1 are spaced apart.

[0043] For example, the length of each of the plurality of light-transmitting regions R0 is approximately the same as the length of one sub-pixel.For example, the wiring connected to the pixel group and the adjacent pixel group surrounds the plurality of light-transmitting regions R0.

[0044] For example, in the example shown in FIG. 7, one pixel island may further include two sub-pixels, for example, a first sub-pixel 101 and a second sub-pixel 102, for example, the first sub-pixel 101 is a red sub-pixel and the second sub-pixel 102 is a green sub-pixel; for example, in the embodiment shown in FIG. 18, one pixel island P1 may further include three sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103, for example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a green sub-pixel; 12 , one pixel island may further include four subpixels, such as a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104, where the first subpixel 101 is a red subpixel, the second subpixel 102 is a green subpixel, the third subpixel 103 is a blue subpixel, and the fourth subpixel 104 is a green subpixel. In other embodiments, pixel groups may use pixel units of other colors. Of course, in other embodiments, the arrangement of the subpixels P0 in the display panel is not limited to that shown in FIGS. 2 and 3 . The embodiments of the present disclosure are not limited thereto.

[0045] As shown in FIGS. 2 and 3 , a plurality of subpixels P0 are located in the first display region R1 and the second display region R2. The density of pixel units in the first display region R1 is less than the density of pixel units in the second display region R2. Alternatively, the density of subpixels in the first display region R1 is less than the density of subpixels in the second display region R2. The density of pixel units in the first display region R1 shown in FIG. 3 is one-fourth of the density of pixel units in the second display region R2. That is, the density of subpixels in the first display region R1 shown in FIG. 3 is one-fourth of the density of subpixels in the second display region R2. The arrangement of the light-transmitting region R0 and the pixel units in the first display region R1 is not limited to that shown in FIG. 3 and may be set as needed. For example, in other embodiments, the density of subpixels in the first display region R1 may be other values ​​other than one-fourth, such as one-half, one-third, one-sixth, or one-eighth of the density of subpixels in the second display region R2, and the embodiments of the present disclosure are not limited thereto.

[0046] 1A and 3, the display panel further includes gate lines 113 and data lines 313. The gate lines 113 and the data lines 313 are insulated from each other. Each gate line 113 connects a row of sub-pixels, and each data line 313 connects a column of sub-pixels. For example, the gate lines 113 are configured to provide scanning signals to the sub-pixels in a row.

[0047] 1A and 3, the data lines 313 include a first data line DL1. The first data line DL1 is located at least in the first display region R1. For example, the first data line DL1 extends from the first display region R1 to the second display region R2.

[0048] 1A and 3, the gate lines include a first gate line GL1, which extends from the second display region R2 to the first display region R1. As shown in FIG. 3, the light-transmitting region R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

[0049] 4 is a schematic diagram of sub-pixels and signal lines for providing signals to the sub-pixels in a display panel according to an embodiment of the present disclosure. As shown in FIG. 4, the display panel includes a plurality of sub-pixels P0, each of which includes a light-emitting element EMC and a pixel circuit 10 for providing a driving current to the light-emitting element EMC. The light-emitting element EMC may be an electroluminescent element, for example, an organic electroluminescent element such as an organic light-emitting diode (OLED).

[0050] 4, the display panel further includes an initialization signal line 210, an emission control signal line 110, a data line 313, a first power supply line 311, and a second power supply line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The emission control signal line 110 is configured to provide an emission control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the second power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, the first voltage signal ELVDD being greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its value may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be equal to or less than the second voltage signal ELVSS. For example, the pixel circuit 10 is controlled by signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the emission control signal EM to output a driving current to drive the light-emitting element EMC to emit light. As shown in FIG. 4, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.

[0051] 5 is a schematic diagram of a display panel according to some embodiments of the present disclosure. Although FIG. 5 illustrates an example in which one pixel island P1 includes two sub-pixels, each pixel island P1 may include three or four sub-pixels, and the specific connection relationship between the sub-pixels is similar to that described above. Therefore, detailed description thereof will be omitted here, and the embodiments of the present disclosure are not limited thereto.

[0052] 5, the first power line 311 includes a plurality of first conductive lines L1 and a plurality of second conductive lines L2. For example, the first power line 311 may further include a plurality of third conductive lines L3. For example, the first conductive line L1 extends from the second display region R2 to the first display region R1 and is electrically connected to a plurality of pixel groups (i.e., pixel islands) P1. The plurality of second conductive lines L2 are located in the first display region R1 and are located between adjacent first conductive lines L1. Each second conductive line L2 extends along the first direction D1 and is electrically connected to a plurality of pixel groups P1. For example, the third conductive line L3 is located at least in the first display region R1. For example, the third conductive line L3 extends from the second display region R2 to the first display region R1. The third conductive line L3 extends along the second direction D2, intersecting the first direction D1 and the second direction D2. Adjacent second conductive lines L2 are spaced apart along the first direction D1. Adjacent second conductive lines L2 are connected to each other via the first conductive line L1 and connected to the third conductive line L3 to receive the first voltage signal ELVDD. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first conductive line L1 extends along the first direction D1. For example, in the embodiment of the present disclosure, the second conductive line L2 is located only in the first display region R1. In the embodiments of the present disclosure, an element extending along a certain direction is not necessarily a straight line, but may have curved or broken line portions, for example, the extension direction of an element is the general extension tendency of the element, and for example, each portion of the element does not necessarily extend along that direction.

[0053] For example, as shown in FIG. 5, the first conducting line L1 and the second conducting line L2 are respectively connected to sub-pixels located in corresponding rows in two adjacent pixel islands P1. However, this is not limiting, and in other embodiments, the pixel island P1 may include two or more rows of sub-pixels. For example, as shown in FIGS. 6A to 6E, the pixel island P1 includes at least two pixel units in one row, and the second conducting line L2 overlaps the two pixel units in the one row. For example, as shown in FIG. 5, the first conducting line L1 is located between two adjacent pixel islands P1, and the second conducting lines L2 that overlap the two adjacent pixel islands P1 are connected via the first conducting line L1.

[0054] For example, as shown in Fig. 5, a plurality of second conductive wires L2 are arranged sequentially along a first direction D1. For example, as shown in Fig. 5, adjacent second conductive wires L2 are not directly connected, but are connected, for example, by a jumper, i.e., connected via first conductive wires L1 located in different layers, thereby improving the stability of the network structure of the first power lines, reducing voltage drops in the first power lines, and thereby improving the brightness uniformity of the display panel. Of course, adjacent second conductive wires L2 may be directly connected, and the embodiments of the present disclosure are not limited thereto.

[0055] For example, as shown in FIG. 5, in order to improve the light transmittance of the first display region, the length in the first direction D1 of the portion of the first conducting wire L1 located in the first display region R1 is longer than the length in the first direction D1 of the second conducting wire L2.

[0056] 5, the first power line 311 further includes a fourth conducting line L4, which extends along the second direction D2 and is connected to the second conducting line L2 to receive the first voltage signal ELVDD, and the length of the fourth conducting line L4 in the second direction D2 is less than or equal to the length of the third conducting line L3 in the second direction D2. In the display panel shown in FIG. 5, the length of the fourth conducting line L4 in the second direction D2 is less than the length of the third conducting line L3 in the second direction D2.

[0057] For example, as shown in FIG. 5, to further improve the light transmittance of the first display area, a plurality of fourth conductive lines L4 are provided. The plurality of fourth conductive lines L4 are arranged in sequence along the second direction D2, and adjacent fourth conductive lines L4 are spaced apart from each other in the second direction D2. For example, as shown in FIG. 5, a plurality of fourth conductive lines L41 are arranged between the third conductive lines L31 and L32, and the third conductive lines L31 and L32 are adjacent third conductive lines L3. Although FIG. 5 shows five fourth conductive lines L41, the number of fourth conductive lines L4 between adjacent third conductive lines L3 is not limited to that shown in the figure and may be set as needed. Since the plurality of fourth conductive lines L4 are spaced apart from each other in the second direction D2, this corresponds to removing the portion of the first power line arranged along the second direction in a typical display panel, thereby reducing wiring, optimizing wiring space, and improving light transmittance.

[0058] 5, the first power line 311 further includes a fifth conductive line L5, which extends in the first direction D1 and is located in the second display region R2, and is spaced apart from the adjacent second conductive line L2 in the first direction D1, thereby reducing the number of wires at the boundary between the first and second display regions and improving light transmittance.

[0059] In the embodiments of the present disclosure, there are no limitations on the number of pixel units included in each pixel island and the arrangement of the pixel units.

[0060] 5, in the display panel, the first power line 311 further includes a plurality of sixth conductive lines L6, which are located in the second display region R2 and extend along the second direction D2. In the second display region R2, the plurality of fifth conductive lines L5 and the plurality of sixth conductive lines L6 are arranged crossing each other. In the embodiment of the present disclosure, the fifth conductive lines L5 and the sixth conductive lines L6 are both located only in the second display region R2.

[0061] As shown in FIG. 5 , the same gate line 113 connects subpixels located in the second display region R2 on both sides of the first display region R1 to subpixels located in the first display region R1, forming a row of subpixels. In the embodiments of the present disclosure, the form of the first conductive line is not limited, as long as it extends from the second display region R2 to the first display region R1. The first power line in FIG. 5 may be replaced with the first power line in other embodiments of the present disclosure. Furthermore, the extension form of the gate line 113 is not limited to that shown in FIG. 5 , as long as the arrangement form of the gate line 113 can connect pixels in the second display region R2 and pixels in the first display region R1. For example, in the first display region R1, the gate lines of subpixels in corresponding rows of two adjacent pixel islands are connected via a seventh conductive line L7 (i.e., in the form of a jumper). Of course, the gate lines of subpixels in corresponding rows of two adjacent pixel islands may also be directly connected, and the embodiments of the present disclosure are not limited thereto.

[0062] For example, the correspondence between the remaining signal lines (e.g., the initialization signal line that provides the initialization signal Vint, the light emission control signal line that provides the light emission control signal EM) and one pixel island P1 is as shown in FIG. 5, but the embodiments of the present disclosure are not limited thereto, and detailed description thereof will be omitted here.

[0063] For example, in the display panel shown in FIG. 5, a first conductive line and two adjacent second conductive lines are in contact with each other by, for example, vias that penetrate the insulating layer.

[0064] For example, in the embodiment of the present disclosure, the subpixels in one row are subpixels connected to the same gate line 113, and the subpixels in one column are subpixels connected to the same data line 313. In the embodiment of the present disclosure, the first conductive line L1, the second conductive line L2, and the fifth conductive line L5 all extend along the row direction (i.e., the first direction D1), and the third conductive line L3, the fourth conductive line L4, and the sixth conductive line L6 all extend along the column direction (i.e., the second direction D2), but this is not limiting. In other embodiments, the first conductive line L1, the second conductive line L2, and the fifth conductive line L5 all extend along the column direction, and the third conductive line L3, the fourth conductive line L4, and the sixth conductive line L6 all extend along the row direction, and correspondingly, the second direction D2 and the first direction D1 are interchangeable.

[0065] 5 illustrates an example in which a pixel island includes two subpixels (e.g., subpixels in one row), but in other embodiments, a pixel island may include three or more subpixels (e.g., subpixels in two rows). In this case, the second conducting lines may be understood as second conducting lines connected to subpixels in the same row in one pixel island. When the first conducting line L1, the second conducting line L2, and the fifth conducting line L5 all extend along the column direction, and the third conducting line L3, the fourth conducting line L4, and the sixth conducting line L6 all extend along the row direction, the second conducting lines may be understood as second conducting lines connected to subpixels in the same column in one pixel island.

[0066] Hereinafter, several embodiments of the present disclosure will be described with reference to Figures 6A to 24. In Figures 6A to 24, a 7T1C pixel circuit will be described as an example.

[0067] FIG. 6A is a principle diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure. FIG. 6B is a plan view of a semiconductor pattern in a display panel according to an embodiment of the present disclosure. FIG. 6C is a plan view of a first conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 6D is a plan view of a second conductive pattern layer in a display panel according to an embodiment of the present disclosure. FIG. 23 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. FIG. 24 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. In the embodiments of the present disclosure, for clarity of illustration, in the plan views, the insulating layer is shown in the form of a via, and the insulating layer itself is treated to be transparent.

[0068] 6B-6F are hierarchical structure diagrams of pixel circuits each including two subpixels, but more or fewer subpixels may be included, and the structure of the pixel circuit may be designed with the layout of one of the pixels shown in FIG. 6B-6F, and the embodiments of the present disclosure are not limited thereto. For example, in FIG. 6F, the pixel structure of the first subpixel 101 is described as an example, and the pixel structures of the remaining subpixels such as the second subpixel, the third subpixel, and the fourth subpixel are similar, and detailed descriptions thereof will be omitted.

[0069] 6A , the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light-emitting control signal line 110 is configured to provide a light-emitting control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10. The first power supply line 311 is configured to provide a first constant voltage signal ELVDD to the pixel circuit 10. The second power supply line 312 is configured to provide a second constant voltage signal ELVSS to the pixel circuit 10, the first voltage signal ELVDD being greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its value may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be less than the second voltage signal ELVSS. For example, the pixel circuit is controlled by signals such as a scan signal SCAN, a data signal DATA, an initialization signal Vint, a first voltage signal ELVDD, a second voltage signal ELVSS, and a light emission control signal EM, and outputs a driving current to drive the light emitting element 20 to emit light. When driven by the corresponding pixel circuit 10, the light emitting element 20 emits red light, green light, blue light, white light, etc.

[0070] 6A, the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The driving transistor T1 is electrically connected to the light-emitting element 20 and is controlled by signals such as a scan signal SCAN, a data signal DATA, a first voltage signal ELVDD, and a second voltage signal ELVSS to output a driving current to drive the light-emitting element 20 to emit light.

[0071] For example, a display panel according to an embodiment of the present disclosure may further include a data driving circuit and a scan driving circuit. The data driving circuit is configured to provide a data signal DATA to the sub-pixel P0 in response to a command from a control circuit, and the scan driving circuit is configured to provide signals such as an emission control signal EM, a scan signal SCAN, a first reset control signal RST1, and a second reset signal RST2 to the sub-pixel P0 in response to a command from the control circuit. For example, the control circuit may include, but is not limited to, an external integrated circuit (IC). For example, the scan driving circuit may be a gate driver on array (GOA) structure attached to the display panel or a driver chip (IC) structure bonded to the display panel. For example, different driving circuits may provide the emission control signal EM and the scan signal SCAN, respectively. For example, the display panel may further include a power supply (not shown), which may be a voltage source or a current source as needed, to provide the voltage signals. The power supply is configured to provide a first voltage signal ELVDD, a second voltage signal ELVSS, and an initialization signal Vint to the sub-pixel P0 via a first power line 311, a second power line 312, and an initialization signal line 210, respectively.

[0072] 6A, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data write transistor T2 is electrically connected to the gate line 113, and the first pole T21 and second pole T22 of the data write transistor T2 are electrically connected to the data line 313 and the first pole T11 of the driving transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

[0073] For example, as shown in FIG. 6A, the gate T40 of the first light-emitting control transistor T4 and the gate T50 of the second light-emitting control transistor T5 are both connected to the light-emitting control signal line 110. As shown in FIG.

[0074] 6A, the first electrode T41 and the second electrode T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first electrode T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T1 and the pixel electrode E1 (which may be the anode of an OLED) of the light-emitting element 20, respectively. The common electrode E2 of the light-emitting element 20 (which may be the common electrode of an OLED, such as a cathode) is electrically connected to the second power line 312.

[0075] 6A, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0076] 6B shows the semiconductor pattern SCP, and FIG. 6C shows the first conductive pattern layer LY1, with a first gate insulating layer disposed between the first conductive pattern layer LY1 and the semiconductor pattern SCP. By doping the semiconductor pattern SCP using the first conductive pattern layer LY1 as a mask, the region of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retains semiconducting properties to form the channel of the thin film transistor, and the region of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 becomes conductive to form the source or drain of the thin film transistor. FIG. 6A shows the active layer ALT formed after the semiconductor pattern SCP is partially made conductive.

[0077] 6C, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, an emission control signal line 110, a gate line 113, and a first pole C11 of a storage capacitor C1. FIG. 6C also shows a first portion DL11 (conductor 114) of the first data line DL1. For example, as shown in FIG. 7, in an embodiment of the present disclosure, the gate line 113 of a current row is further connected to the second reset control signal line 112 located in the same row.

[0078] 6D shows the second conductive pattern layer LY2, with a second gate insulating layer disposed between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes a stopper BK0, a stopper BK1, an initialization signal line 210, and the second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 of two subpixels of one pixel island is integrally formed and used as the second conductive line L2. The second pole C12 of the storage capacitor C1 has an opening OPN. An interlayer insulating layer is disposed between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. The first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3 can be described in the art, and detailed descriptions thereof will be omitted here.

[0079] Figure 6E shows the third conductive pattern layer LY3, which includes a first conductive line L1, a third conductive line L3 (part of the first power line 311), a fourth conductive line L4 (part of the first power line 311), a second part DL12 of the data line (part of the data line 313), a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c and a fourth connection electrode 31d.

[0080] For example, as shown in FIG. 6E, at least one of the multiple first conducting lines L1 includes a first sub-line L111 extending along the first direction D1 and a second sub-line L112 extending along the second direction D2, and the second sub-line L112 is electrically connected to at least one of the multiple second conducting lines L2. For example, as shown in FIG. 11, the second sub-line L112 is electrically connected to the second conducting lines L2 of the corresponding row in an adjacent pixel island. For example, as shown in FIGS. 13 and 17, the second sub-line L112 is electrically connected to two second conducting lines L2 in one pixel island and two second conducting lines L2 in a pixel island adjacent to the pixel island. The embodiments of the present disclosure are not limited thereto.

[0081] For example, the second sub-wiring L112 is connected to the stopper BK0 by a via that penetrates the interlayer insulating layer, and is connected to the second conducting wire L2 by a via that penetrates the interlayer insulating layer.

[0082] 6B-6E. As shown in FIGS. 6B-6E, the data line 313 is electrically connected to the first electrode T21 of the data write transistor T2 through a via, the first power line 311 is electrically connected to the first electrode T41 of the first light-emitting control transistor T4 through a via, the first power line 311 is electrically connected to the second electrode C12 of the storage capacitor C1 through a via, and the first power line 311 is electrically connected to the conductive block BK1 through a via. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through a via, and the other end of the first connection electrode 31a is electrically connected to the first electrode T61 of the first reset transistor T6 through a via, which further electrically connects the first electrode T61 of the first reset transistor T6 to the first initialization signal line 211. One end of the second connection electrode 31b is electrically connected to the second pole T62 of the first reset transistor T6 through a via, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1) through a via, thereby electrically connecting the second pole T62 of the first reset transistor T6 to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through a via, and the other end of the third connection electrode 31c is connected to the first pole T71 of the second reset transistor T7 through a via, and further electrically connects the first pole T71 of the second reset transistor T7 to the second initialization signal line 212. The fourth connection electrode 31d is electrically connected to the second pole T52 of the second light-emitting control transistor T5 through a via. The fourth connection electrode 31d may be electrically connected to a pixel electrode E1 (see FIG. 6A) of a subsequently formed light-emitting element 20. For example, the positional relationship between the first connection electrode 31a and the third connection electrode 31c can refer to the positions in FIG. 6E, and is not shown in FIG. 6F for clarity and simplicity.

[0083] Note that the transistors used in some embodiments of the present disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used herein may be structurally symmetrical, and therefore, the source and drain may not be structurally distinct. In one embodiment of the present disclosure, to distinguish between two poles other than the gate of a transistor, one pole is directly referred to as a first pole and the other pole as a second pole. Therefore, in the embodiments of the present disclosure, the first pole and the second pole of all or some transistors may be interchangeable as needed. For example, the first pole of a transistor described in an embodiment of the present disclosure may be the source, and the second pole may be the drain, or the first pole of a transistor may be the drain and the second pole of the transistor may be the source.

[0084] Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. In the embodiments of the present disclosure, a case where all transistors are P-type transistors will be described as an example. Based on the description and teachings of the implementations of the present disclosure, a person skilled in the art can easily conceive of using N-type transistors as at least some of the transistors in the pixel circuits of the embodiments of the present disclosure, without any creative effort, that is, using N-type transistors or a combination of N-type transistors and P-type transistors, and therefore, such implementations also fall within the scope of protection of the present disclosure.

[0085] 6A to 6F illustrate a 7T1C pixel circuit as an example, and the embodiments of the present disclosure include, but are not limited to, this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and the embodiments of the present disclosure are not limited thereto.

[0086] 23 is a cross-sectional schematic diagram of a pixel circuit of a display panel according to some embodiments of the present disclosure. For example, as shown in FIG. 23, the display panel includes a thin-film transistor 50 and a storage capacitor C1. The thin-film transistor 50 includes an active layer ATL1 located on a base substrate BS, a first gate insulating layer GI1 located on a side of the active layer ATL1 away from the base substrate BS, and a gate GE located on a side of the first gate insulating layer GI1 away from the base substrate BS. The display panel further includes a second gate insulating layer GI2 located on a side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on a side of the second gate insulating layer GI2 away from the base substrate BS, and a source or drain CNE1 located on a side of the interlayer insulating layer ILD away from the base substrate BS. For example, if the thin film transistor 50 is implemented as an N-type transistor, CNE1 represents the source of the thin film transistor 50 and CNE2 represents the drain of the thin film transistor 50. If the thin film transistor 50 is implemented as a P-type transistor, CNE1 represents the drain of the thin film transistor 50 and CNE2 represents the source of the thin film transistor 50. The active layer ATL1 includes a channel CN11 and a first pole ET1 and a second pole ET2 located on either side of the channel CN11, respectively. The connection electrode CNE1 is connected to the second pole ET2 by a via that penetrates the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first pole C11 and a second pole C12. The first pole C11 and the gate GE are located on the same layer and are both located on the first conductive pattern layer LY1. The second pole C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD and is located on the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is a source, and the other is a drain. The connecting electrode CNE1 is located on the third conductive pattern layer LY3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the source or drain CNE1 may be the first part of the fourth connecting electrode 31d shown in FIG. 6E or 6F, and the thin film transistor 50 may be the second light-emitting control transistor T5.

[0087] 23, the display panel further includes a light-emitting element EMC, which includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2. The pixel electrode E1 is connected to a connection electrode CNE1 through a via that penetrates the passivation layer PVX and the planarization layer PLN. The display panel further includes a package layer CPS, which includes a first package layer CPS1, a second package layer CPS2, and a third package layer CPS3. For example, the first package layer CPS1 and the third package layer CPS3 are inorganic material layers, and the second package layer CPS2 is an organic material layer. For example, the pixel electrode E1 is an anode, and the common electrode E2 is a cathode, but is not limited thereto.

[0088] For example, the light-emitting element EMC includes an organic light-emitting diode. The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer EML includes at least a light-emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0089] As shown in Fig. 23, the display panel further includes a pixel definition layer PDL and a spacer PS. The pixel definition layer PDL has an opening configured to limit the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the spacer PS is configured to support the fine metal mask when forming the light-emitting functional layer EML. Fig. 23 shows that the spacer PS is installed on both opposing sides of the light-emitting element, but is not limited thereto.

[0090] For example, the data line is configured to input a data signal to the pixel unit, the first power supply line is configured to input a first voltage signal to the driving transistor, and the second power supply line is configured to input a second voltage signal to the sub-pixel. The first voltage signal is a constant voltage, and the second voltage signal is a constant voltage, for example, but not limited to, the first voltage signal is a positive voltage, and the second voltage signal is a negative voltage. For example, in some embodiments, the first voltage signal is a positive voltage, and the second power supply line is grounded.

[0091] As shown in FIG. 23, in an embodiment of the present disclosure, the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0092] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel defining layer PDL, and the spacer PS are all made of insulating materials. For example, the materials of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX include, but are not limited to, at least one of SiOx and SiNx. For example, the planarization layer PLN, the pixel defining layer PDL, and the spacer PS may be made of an organic insulating material, such as, but not limited to, a resin.

[0093] As shown in FIG. 6F, the threshold compensation transistor T3 includes a first active part CN1 and a second active part CN2 connected via a conductive part CP. As shown in FIGS. 8B and 10, the second conductive line L2 further includes a connecting arm L21. The threshold compensation transistor T3 is a double-gate transistor. When the threshold compensation transistor T3 is turned off, the conductive part CP is in a floating state and is prone to jumps due to the surrounding line voltage. The voltage jump of the conductive part CP affects the leakage current of the threshold compensation transistor T3 and further affects the light-emitting brightness of the pixel unit. Therefore, the voltage of the conductive part CP needs to be stabilized. To this end, a stopper and the conductive part CP are designed to form a capacitor, and the stopper may have a constant voltage signal to stabilize the voltage of the conductive part CP in the floating state. The stopper BK0, the stopper BK1, and the connecting arm mentioned thereafter all serve to stabilize the voltage of the conductive part CP.

[0094] Fig. 7 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Fig. 8A is an enlarged schematic diagram of region A11 shown in Fig. 7. Fig. 8B is an enlarged schematic diagram of region A12 shown in Fig. 7. Fig. 8C is a plan view of a semiconductor pattern of the display panel shown in Fig. 7. Fig. 9 is a plan view of a first conductive pattern layer of the display panel shown in Fig. 7. Fig. 10 is a plan view of a second conductive pattern layer of the display panel shown in Fig. 7. Fig. 11 is a plan view of a third conductive pattern layer of the display panel shown in Fig. 7.

[0095] 7, the at least two sub-pixels include a first sub-pixel 101 and a second sub-pixel 102 arranged along a first direction D1. For example, as shown in FIG. 8A, at least one of the plurality of second conducting lines L2 electrically connects the first sub-pixel 101 and the second sub-pixel 102 and is located in a different layer from the second sub-wiring L112 and the plurality of second conducting lines L2.

[0096] For example, as shown in FIG. 6A, the sub-pixel P0 further includes a light-emitting element 20, and the pixel circuit includes a first transistor (e.g., a threshold compensation transistor T3) and a second transistor (e.g., a second light-emitting control transistor T5 shown in FIG. 6A), where the first transistor T3 is connected to the second transistor T5, and the second transistor T5 is connected to the light-emitting element 20; for example, as shown in FIG. 6F, the first transistor T3 includes a first active part CN1 and a second active part CN2 connected via a conductive part CP.

[0097] For example, as shown in Figures 8B and 10, the second conductive line L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive portion CP of one sub-pixel in the pixel group that overlaps with the second conductive line L2 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3 (see Figure 24), and the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2.

[0098] 8B and 10, the shape of the connecting arm L21 includes a C-shape. Note that the connecting arm L21 may have a substantially C-shape, and of course, the connecting arm L21 may have other shapes as long as it can play a role in stabilizing the threshold compensation transistor T3.

[0099] As shown in FIG. 24, the connection arm L21 partially overlaps the conductive portion CP of the threshold compensation transistor T3 to form a capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are disposed between the connection arm L21 and the conductive portion CP. FIG. 24 also shows the second active portion CN2. The capacitor C0 may also be called a stable capacitor, and the connection arm L21 and the conductive portion CP are the two plates of the capacitor C0. As shown in FIG. 24, the gate GE2 and the second active portion CN2 overlap in a direction perpendicular to the base substrate BS. The gate GE2 is one gate of the threshold compensation transistor T3. As shown in FIG. 24, a portion of the second connection electrode 31b (see FIG. 6E) is used as a second pole T32 (e.g., a drain) of the threshold compensation transistor T3.

[0100] For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2, and the third direction D3 is perpendicular to the base substrate BS. A first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connecting arm L21 and the conductive portion CP. For example, the first direction D1 and the second direction D2 are parallel to the main surface of the base substrate BS, and the third direction D3 is perpendicular to the main surface of the base substrate BS. Various elements are fabricated on the main surface of the base substrate BS.

[0101] As shown in Figures 6F, 8A, and 24, the stopper BK0 and the conductive portion of one sub-pixel in the pixel island that overlaps with the first conducting line L1 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. As shown in Figures 6F, 8A, and 24, the stopper BK0 and the conductive portion CP of one sub-pixel in the pixel island that overlaps with the first conducting line L1 (the lower right sub-pixel in Figure 8A) are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3.

[0102] 6A, 6F, 8B, and 24, the second conducting line L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive portion CP of one subpixel in the pixel island that overlaps with the second conducting line L2 (the upper right subpixel in FIG. 7, i.e., the subpixel in FIG. 8B) are spaced apart from each other in the third direction D3 and partially overlap each other in the third direction D3. For example, the first transistor and the second transistor are, respectively, the threshold compensation transistor T3 and the emission control transistor connected to the light-emitting element in the pixel circuit 10. For example, the emission control transistor connected to the light-emitting element is the second emission control transistor T5. Of course, in other embodiments of the present disclosure, the stopper or connecting arm that forms a capacitor with the conductive portion CP of the first transistor in the pixel island may take other forms, and this is not limited thereto.

[0103] 6D , the initialization signal line 210 includes multiple hollow regions HP, and the second conductive wire L2 is located within one hollow region HP and is surrounded by the portion of the initialization signal line surrounding the hollow region HP, but does not overlap with the portion of the initialization signal line surrounding the hollow region HP. That is, the second conductive wire L2 is completely surrounded by the portion of the initialization signal line surrounding the hollow region HP. In the embodiment of the present disclosure, the hollow region HP corresponds to the portion of the thin film removed during the manufacturing of the initialization signal line 210.

[0104] For example, as shown in Figure 8A, the first conductive line L1 includes a first sub-wire L111 and a second sub-wire L112, and the first sub-wire L111 of the first conductive line L1 and the second conductive line L2 are not located in the same layer, and the second sub-wire L112 of the first conductive line L1 and the second conductive line L2 are not located in the same layer. As shown in Figures 8A, 10 and 11, the second conductive line L2 is located in the second conductive pattern layer LY2, and the first conductive line L1 is located in the third conductive pattern layer LY3.

[0105] For example, as shown in Fig. 3, the data lines 313 include a first data line DL1 extending from the first display region R1 to the second display region R2. For example, as shown in Fig. 8A, the first portion DL11 of the first data line DL1 partially overlaps the orthogonal projection of the third conducting wire L3 on the base substrate BS. This arrangement is advantageous for reducing the wiring area and improving light transmittance.

[0106] 6C, 6D, 7, and 8A, the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps the third conductive line L3, the second portion DL12 of the first data line DL1 does not overlap the third conductive line L4, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are located in different layers. For example, the first portion DL11 (conductive line 214) of the left first data line DL1 in FIG. 8A is located in the second conductive pattern layer, and the second portion DL12 of the left first data line DL1 is located in the third conductive pattern layer, the first portion DL11 (conductive line 114) of the right first data line DL1 in FIG. 8A is located in the first conductive pattern layer shown in FIG. 9, and the second portion DL12 of the right first data line DL1 in FIG. 8A is located in the third conductive pattern layer shown in FIG. 11. For example, as shown in FIGS. 3, 19 and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands P1.

[0107] For example, as shown in Fig. 3, two first data lines DL1 are provided, and the two first data lines DL1 are respectively connected to two adjacent columns of sub-pixels. For example, as shown in Fig. 8A, the first portions DL11 of the two first data lines partially overlap with the orthogonal projections of the same third conducting line L3 on the base substrate BS. With this arrangement, the data lines located between the pixel islands in the two adjacent columns of sub-pixels can be hidden under the third conducting line, thereby reducing the wiring area and improving light transmittance.

[0108] For example, the first conductive line L1 and the second conductive line L2 are located on different layers and are connected by a via that penetrates the insulating layer. As shown in Figures 8A and 11, the first conductive line L1 is located on the third conductive pattern layer LY3, and the second conductive line L2 is located on the second conductive pattern layer LY2. As shown in Figures 23 and 24, an interlayer dielectric layer ILD is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, i.e., the second sub-wiring L112 of the first conductive line L2 and the second conductive line L2 are connected by a via that penetrates the interlayer dielectric layer ILD.

[0109] For example, as shown in Figure 11, the first conductive wire L1 and the third conductive wire L3 are located on the same layer, both located on the third conductive pattern layer LY3, and the fourth conductive wire L4 and the third conductive wire L3 are located on the same layer, both located on the third conductive pattern layer LY3.

[0110] For example, the multiple pixel groups include multiple first pixel groups (i.e., pixel islands) and multiple second pixel groups (i.e., pixel islands) arranged at intervals, and adjacent first pixel groups and second pixel groups are connected via multiple wirings (including, for example, wiring L11 between gate lines connecting adjacent pixel islands, wiring L13 (i.e., 210) between initialization signal lines connecting adjacent pixel islands, wiring L14 between light emission control signal lines connecting adjacent pixel islands, and first conductor L1, etc.).

[0111] 8A and 10, the display panel 1 further includes connecting wires Ld, and the orthogonal projections of at least two of the plurality of wires between the first and second adjacent pixel groups on the base substrate are within the orthogonal projections of the connecting wires Ld on the base substrate. For example, in some embodiments, there are a plurality of gaps between the plurality of wires, and the orthogonal projections of at least one of the plurality of gaps on the base substrate at least partially overlap with the orthogonal projections of the connecting wires Ld on the base substrate, thereby preventing light leakage due to the gaps between the wires.

[0112] 6A-6F , the pixel circuit 10 includes a first reset signal line 111, a second reset signal line 112, a gate line 113, a light-emitting control signal line 110, and an initialization signal line 210, respectively providing a first reset signal, a second reset signal, a gate scanning signal, a light-emitting control signal, and an initialization signal to the pixel circuit, and the plurality of wirings are selected from at least two of the first reset signal line 111, the second reset signal line 112, the gate line 113, the light-emitting control signal line 110, the initialization signal line 210, and the first conducting line. For example, the first reset signal line 111, the second reset signal line 112, the gate line 113, the light-emitting control signal line 110, the initialization signal line 21, and the second conducting line of the first pixel group are respectively connected to the second reset signal line 112, the gate line 113, the light-emitting control signal line 110, the initialization signal line 210, and the second conducting line of the second pixel group via the plurality of wirings.

[0113] For example, as shown in Figures 8A and 10, at least a portion of the orthogonal projection of the connecting conductor Ld on the base substrate is located between the orthogonal projections on the substrate of the adjacent first pixel group and second pixel group, and the connecting conductor Ld and the initialization signal line are located on the same layer and are integrally formed.

[0114] Fig. 18 is a schematic diagram of a display panel in which one pixel island includes three sub-pixels according to at least one embodiment of the present disclosure. For example, one pixel island includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Fig. 19 is a plan view of a semiconductor pattern of the display panel shown in Fig. 18. Fig. 20 is a plan view of a first conductive pattern layer of the display panel shown in Fig. 18. Fig. 21 is a plan view of a second conductive pattern layer of the display panel shown in Fig. 18. Fig. 22 is a plan view of a third conductive pattern layer of the display panel shown in Fig. 18.

[0115] For example, the connection structure of the display panel shown in Fig. 18 is almost the same as that of the display panel shown in Fig. 7, with the difference being that adjacent pixel islands shown in Fig. 18 are located in the same row, while adjacent pixel islands shown in Fig. 7 are arranged with a shift. For the related description of Fig. 18, please refer to the related descriptions of Figs. 7 to 11, and detailed description thereof will be omitted here.

[0116] 18 and 21, the connecting conductor Ld is located in the same layer as the second conductor L2 and is formed integrally therewith. However, the connecting conductor Ld may also be located in the same layer as the first conductor L1 and be formed integrally therewith, and the embodiments of the present disclosure are not limited thereto.

[0117] 21, in this embodiment, the connecting wire Ld has a stopper BK0 that is disposed on the same layer as the connecting wire Ld and is integrally formed therewith. The stopper and the conductive portion of one pixel unit in the BK0 pixel group that overlaps with the first conducting wire L1 are disposed spaced apart from each other in the third direction D1 and partially overlap in the third direction D3, thereby ensuring the stability of the threshold compensation transistor T3. For details, please refer to the above description and a detailed description will be omitted here.

[0118] Fig. 12 is a schematic diagram of a display panel in which one pixel island includes four subpixels according to at least one embodiment of the present disclosure. For example, one pixel island includes a first subpixel 101, a second subpixel 102, a third subpixel 103, and a fourth subpixel 104. Fig. 13 is an enlarged schematic diagram of an area A21 shown in Fig. 12. Fig. 14 is a plan view of a semiconductor pattern of the display panel shown in Fig. 12. Fig. 15 is a plan view of a first conductive pattern layer of the display panel shown in Fig. 12. Fig. 16 is a plan view of a second conductive pattern layer of the display panel shown in Fig. 12. Fig. 17 is a plan view of a third conductive pattern layer of the display panel shown in Fig. 12.

[0119] For example, in some embodiments of the present disclosure, as shown in FIG. 12 , the at least two sub-pixels further include a third sub-pixel 103 and a fourth sub-pixel 104, where the third sub-pixel 103 and the fourth sub-pixel 104 are arranged along the first direction D1 and are located on one side of the first sub-pixel 101 and the second sub-pixel 102 along the second direction D2, the third sub-pixel 103 and the fourth sub-pixel 104 are electrically connected to another of the plurality of second conductive lines L2 (e.g., the second conductive line L21 located at the bottom in the layout shown in FIG. 16 ), and the second sub-wiring L112 is electrically connected to at least one of the plurality of second conductive lines, for example, the second conductive line L2 located in the first row of pixels (i.e., the first sub-pixel 101 and the second sub-pixel 102) and / or the second conductive line L21 located in the second row of pixels (i.e., the third sub-pixel 103 and the fourth sub-pixel 104).

[0120] For example, the display panel shown in Fig. 12 is almost the same as the display panel shown in Fig. 7, but the difference is that the layers on which the wiring of two adjacent pixel groups connected to each other are located are different. Specifically, for example, as shown in Fig. 15, wiring L11 of a gate line connecting two adjacent pixel islands is located in the first conductive pattern layer LY2, but in Fig. 7, it is located in the third conductive pattern layer LY3, and the initialization signal line 111 extends from the second display region R2 to the first display region R1 in the first conductive pattern layer, and as shown in Fig. 16, the initialization signal line 111 may be further connected via wiring Lrest located in the second conductive pattern layer.

[0121] 16 and 10, the second sub-line L112 has a stopper BK0, and the stopper BK0 and the second sub-line L112 are located in a different layer and are connected by a via. For example, as shown in Fig. 24, the stopper BK0 is located in the second conductive pattern layer, and the second sub-line L112 is located in the third conductive pattern layer LY3 shown in Fig. 17 and 11. Therefore, in this embodiment, the stopper BK0 is connected to the second sub-line L112 by a via that penetrates the insulating layer, thereby ensuring the stability of the threshold compensation transistor T3.

[0122] However, the remaining structure of the display panel (for example, the stopper BK0), the first conductive wire L1, etc. can be referred to in the descriptions of FIGS. 7 to 11, and detailed descriptions thereof will be omitted here.

[0123] At least one embodiment of the present disclosure further provides a display device, including any of the display panels described above. For example, the display device may be a display device such as an organic light-emitting diode (OLED) display, or any product or component with a display function, including such a display device, such as a television, digital camera, mobile phone, wristwatch, tablet PC, laptop computer, or navigation device.

[0124] 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 25, the display device 2 includes a display panel 1 and a sensor 3. For example, the sensor 3 is disposed on one side of the display panel 1.

[0125] 1A-1C, the sensor 3 is disposed on the second side of the display panel 1, and the sensor 3 is configured to receive light from the first side of the display panel. For example, the first side of the display panel 1 is used for displaying, and the first display region R1 allows light from the first side of the display panel to at least partially transmit to the second side of the display panel.

[0126] For example, the orthogonal projection of the sensor 3 on the base substrate at least partially overlaps with the first display region R1.

[0127] For the sake of clarity and conciseness, the embodiments of the present disclosure do not include all components of the display device, and those skilled in the art may provide and install other structures not shown according to specific needs to achieve the basic functions of the display device, and the embodiments of the present disclosure are not limited thereto.

[0128] The technical effects of the display device 2 according to the above embodiment can be referred to the technical effects of the display panel 1 according to the embodiment of the present disclosure, and detailed description thereof will be omitted here.

[0129] In addition, (1) Unless otherwise defined, the same symbols have the same meanings in the examples and drawings of this disclosure. (2) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are shown, and other structures may refer to the general design. (3) For clarity, the thickness of layers or regions is exaggerated in the drawings illustrating the embodiments of the present disclosure. As will be understood, when an element such as a layer, film, region, or substrate is described as being located "on" or "under" another element, the element may be located "directly" "on" or "under" the other element, or intermediate elements may be present. (4) Where there is no conflict, features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0130] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and all modifications and substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure should fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be in accordance with the scope of protection of the claims.

Claims

1. A display panel, a first display area; a second display area located at least on one side of the first display area; a plurality of sub-pixels located in the first display region and the second display region, the density of the sub-pixels in the first display region being less than the density of the sub-pixels in the second display region, the sub-pixels including pixel circuits; a plurality of pixel groups located in the first display area, at least one of the plurality of pixel groups including at least two sub-pixels; a first power supply line configured to provide a first voltage signal to the pixel circuit; the first power supply line includes a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines extending from the second display area to the first display area and electrically connected to the plurality of pixel groups, the plurality of second conductive lines located in the first display area and located between adjacent first conductive lines, the plurality of second conductive lines extending along a first direction, adjacent second conductive lines being spaced apart from each other along the first direction, and the plurality of second conductive lines electrically connected to the plurality of pixel groups; At least one of the plurality of first conducting wires includes a first sub-wiring extending along a first direction and a second sub-wiring extending along a second direction, the first direction and the second direction intersect, and the second sub-wiring is electrically connected to at least one of the plurality of second conducting wires; the at least two sub-pixels include a first sub-pixel and a second sub-pixel arranged along the first direction, at least one of the plurality of second conducting lines electrically connects the first sub-pixel and the second sub-pixel, and the second sub-wiring and the plurality of second conducting lines are located in different layers.

2. 2. The display panel of claim 1, wherein the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is connected to the second transistor and the storage capacitor, respectively, the second transistor is connected to the light-emitting element, and the first transistor includes a first active portion and a second active portion connected via a conductive portion.

3. 3. The display panel of claim 2, wherein the second conducting line further includes a connecting arm that is spaced apart from the conductive portion of one subpixel in the pixel group that overlaps with the second conducting line in a third direction and partially overlaps with the conductive portion in the third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

4. The display panel according to claim 3 , wherein the shape of the connecting arm includes a C-shape.

5. 5. The display panel of claim 1, wherein the plurality of pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected via a plurality of wirings.

6. 6. The display panel of claim 5, further comprising connecting wires, wherein the orthogonal projections on the base substrate of at least two of the plurality of wirings between the adjacent first pixel group and second pixel group are within the orthogonal projections on the base substrate of the connecting wires.

7. 7. The display panel of claim 6, wherein there are a plurality of gaps between the plurality of wirings, and the orthogonal projection of at least one of the plurality of gaps on the base substrate at least partially overlaps with the orthogonal projection of the connecting conductor on the base substrate.

8. the pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control signal line, and an initialization signal line, for respectively providing a first reset signal, a second reset signal, a gate scanning signal, a light emission control signal, and an initialization signal to the pixel circuit; 8. The display panel according to claim 6, wherein the plurality of wirings are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the first conducting line.

9. the connecting wire has a stopper that is disposed in the same layer as the connecting wire and is integrally formed therewith; the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is respectively connected to the second transistor and the storage capacitor, the second transistor is connected to the light-emitting element, and the first transistor includes a first active portion and a second active portion connected via a conductive portion; 7. The display panel of claim 6, wherein the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductive line are spaced apart from each other in the third direction and partially overlap with each other in the third direction.

10. The display panel according to claim 8 , wherein the orthogonal projection of the connecting conductor on the base substrate is at least partially located between the orthogonal projections of the adjacent first and second pixel groups on the base substrate.

11. 11. The display panel of claim 10, wherein the first reset signal line, the second reset signal line, the gate line, the light-emission control signal line, the initialization signal line, and the second conducting line of the first pixel group are connected to the first reset signal line, the second reset signal line, the gate line, the light-emission control signal line, the initialization signal line, and the second conducting line of the second pixel group, respectively, via the plurality of wirings.

12. 12. The display panel of claim 11, wherein the connecting conductor and the second conductor are located in the same layer and formed integrally, or the connecting conductor and the initialization signal line are located in the same layer and formed integrally, or the connecting conductor and the first conductor are located in the same layer.

13. 3. The display panel of claim 2, wherein the at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged along the first direction and located on one side of the first sub-pixel and the second sub-pixel along the second direction, and are electrically connected to another of the plurality of second conducting lines, and the second sub-line is electrically connected to at least one of the plurality of second conducting lines.

14. the second sub-wiring has a stopper located in a layer different from the second sub-wiring and connected by a via; 14. The display panel of claim 2 or 13, wherein the stopper and the conductive portion of one pixel unit in the pixel group that overlaps with the first conductive line are spaced apart from each other in the third direction and partially overlap in the third direction.

15. The display panel of claim 1 , wherein the first direction is perpendicular to the second direction.

16. The display panel of claim 1 , wherein the second conductive lines are arranged in order along the first direction.

17. The display panel of claim 1 , wherein the adjacent second conductive lines are not directly connected.

18. The display panel of claim 1 , wherein the first conducting wire and the second conducting wire are connected by a via that penetrates an insulating layer.

19. the first power supply line further includes a third conducting line and a fourth conducting line; the third conducting wire extends along the second direction and extends from the second display area to the first display area, the second conducting wire is electrically connected to the third conducting wire, 19. The display panel of claim 1, wherein the fourth conducting wire extends along the second direction, the second conducting wire is electrically connected to the fourth conducting wire, and the length of the fourth conducting wire in the second direction is less than or equal to the length of the third conducting wire in the second direction.

20. 20. The display panel of claim 1, further comprising a plurality of fourth conductive wires positioned between adjacent third conductive wires and arranged in sequence along the second direction, wherein adjacent fourth conductive wires are spaced apart from each other in the second direction.

21. The display panel of claim 19 , wherein the first conducting wire and the third conducting wire are located in the same layer, and the fourth conducting wire and the third conducting wire are located in the same layer.

22. 22. The display panel of claim 1, wherein the first display region includes a plurality of light-transmitting regions located between adjacent groups of pixels.

23. 23. The display panel of claim 22, wherein wiring connected to the plurality of pixel groups and adjacent pixel groups surrounds the plurality of light-transmitting regions.

24. A display device comprising a display panel according to any one of claims 1 to 23.

25. further comprising a sensor; The display device of claim 24 , wherein the sensor is disposed on one side of the display panel, and an orthogonal projection of the sensor on the base substrate at least partially overlaps the first display area.

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