Display device and display panel

Abstract

To provide a display device with a repair structure, and a display panel.SOLUTION: A display device according to embodiments of the present disclosure may include a first lower metal directly connected to a first pixel electrode or a first source electrode in a first sub-pixel to overlap with a first active layer, a second lower metal directly connected to a second pixel electrode or a second source electrode in a second sub-pixel to overlap with a second active layer, and an overlapping pattern having one side overlapping with at least a portion of the first lower metal and another side overlapping with at least a portion of the second lower metal.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a display device and a display panel. [Background technology]

[0002] During the manufacturing of a display panel, defects such as bright or dark spots in a subpixel can occur due to various reasons, such as the occurrence of foreign particles at various positions within the subpixel. For example, the driving transistor in each subpixel is manufactured through multiple processes, and during these processes, minute process-related foreign particles can occur in the driving transistor. If foreign particles occur in the driving transistor, a short or open phenomenon can occur due to the foreign particles. This phenomenon can cause the subpixel to become a defective subpixel that cannot emit light normally, thereby reducing the yield of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present disclosure may provide a display device and a display panel having a repair structure that can repair a subpixel when a defect occurs in the subpixel.

[0004] The embodiments of the present disclosure can provide a display device and a display panel having a repair structure with high repair performance or a high probability of successful repair.

[0005] The embodiments of the present disclosure may provide a display device and a display panel having a repair structure that does not cause a decrease in aperture ratio.

[0006] The embodiments of the present disclosure can provide a display device and a display panel with a repair structure that does not occupy much space.

[0007] The embodiments of the present disclosure can provide a display device having a repair structure suitable for a high-resolution configuration. [Means for solving the problem]

[0008] A display device according to an embodiment of the present disclosure includes a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; a first pixel electrode directly connected to a portion of the first active layer or electrically connected to a portion of the first active layer through an additional first source electrode; a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; a second pixel electrode directly connected to a portion of the second active layer or electrically connected to a portion of the second active layer through an additional second source electrode; and a second pixel electrode directly connected to the first pixel electrode or directly connected to the first source electrode. and overlapping the first active layer; a second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; an overlapping pattern disposed on the first buffer layer and including a first portion overlapping with at least a portion of the first lower metal, a second portion overlapping with at least a portion of the second lower metal, and a third portion between the first and second portions; and a second buffer layer disposed on the overlapping pattern and below the first active layer and the second active layer.

[0009] A display panel according to an embodiment of the present disclosure may include a first subpixel including a first subpixel circuit and a first light-emitting element, a second subpixel including a second subpixel circuit and a second light-emitting element, a first lower metal connected to the first subpixel circuit, a second lower metal connected to the second subpixel circuit, an overlapping pattern including a first portion overlapping with a portion of the first lower metal, a second portion overlapping with a portion of the second lower metal, and a third portion between the first and second portions, and a first buffer layer disposed between the first and second lower metals and the overlapping pattern. [Effects of the Invention]

[0010] According to an embodiment of the present disclosure, it is possible to provide a display device and a display panel having a repair structure capable of normalizing a subpixel when a defect occurs in the subpixel.

[0011] According to the embodiments of the present disclosure, it is possible to provide a display device and a display panel having a repair structure that does not cause a decrease in aperture ratio.

[0012] According to the embodiments of the present disclosure, a display device and a display panel having a repair structure that does not occupy much space can be provided.

[0013] According to the embodiments of the present disclosure, it is possible to provide a display device having a repair structure suitable for a high-resolution configuration.

[0014] According to the embodiments of the present disclosure, it is possible to provide a display device and a display panel having a repair structure with high repair performance or high repair success rate, and also to reduce manufacturing costs and optimize processes. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] 1 is an equivalent circuit of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a schematic plan view of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 4] 10 is an equivalent circuit diagram of first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 5] 10 illustrates a symmetrical structure of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 6] 10 illustrates a symmetrical structure of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 7]10 illustrates a situation in which a defect occurs in the second subpixel of first and second subpixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 8] 1 shows a repair structure for a display device according to an embodiment of the present disclosure. [Figure 9] 1 shows a repair structure for a display device according to an embodiment of the present disclosure. [Figure 10] 10 is a diagram illustrating a welding repair process when a defect occurs in a second subpixel circuit in a second subpixel among first and second subpixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 11] 10 is a diagram illustrating a welding repair process when a defect occurs in a second subpixel circuit in a second subpixel among first and second subpixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 12] 10 is an equivalent circuit showing a cutoff point for disabling a second subpixel circuit in a second subpixel when a defect occurs in the second subpixel circuit in the second subpixel between first and second subpixels adjacent in a column direction in a display device according to an embodiment of the present disclosure. [Figure 13] 1 shows first to eighth sub-pixels in a display panel according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a plan view of the circuit cluster area of ​​FIG. [Figure 15] FIG. 1 is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is an enlarged plan view of a partial area of ​​FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line AA' in FIG. [Figure 18] 3 is a cross-sectional view of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 19] FIG. 10 is a plan view of a display panel that has been repaired. [Figure 20] FIG. 16 is an enlarged plan view of a partial area of ​​FIG. [Figure 21]3 is a cross-sectional view of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 22] FIG. 1 is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 23] FIG. 23 is an enlarged plan view of a part of FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view taken along the line BB' in FIG. 23. [Figure 25] 3 is a cross-sectional view of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 26] FIG. 10 is a plan view of a display panel that has been repaired. [Figure 27] 10 is a diagram illustrating a current supply state after a repair process when a defect occurs in a second sub-pixel among first to fourth sub-pixels arranged in a column direction in a display panel according to an embodiment of the present disclosure. [Figure 28] 10 is a diagram illustrating a current supply state after a repair process when a defect occurs in a first subpixel among first to fourth subpixels arranged in a column direction in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0016] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may be assigned the same numerals whenever possible, even if they are displayed in different drawings. Furthermore, when describing the present invention, if it is determined that a detailed description of related known structures or functions may obscure the gist of the present invention, such a detailed description may be omitted. When terms such as "include," "have," and "be made" are used in this specification, other terms may be added unless "only" is used. When a component is expressed in the singular, it may also include a plural unless otherwise expressly stated.

[0017] In addition, in describing the components of this embodiment, terms such as first, second, A, B, (a), (b), etc. are used only to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the corresponding component.

[0018] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" through an additional "intervening" component. Here, the additional component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0019] In describing the temporal flow relationship associated with components, operating methods, manufacturing methods, etc., when the temporal or flow precedence relationship is described using, for example, "after," "following," "next," or "before," it may also include cases where the relationship is not consecutive, since "immediately" or "directly" is not used.

[0020] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) for a component is mentioned, the numerical value or its corresponding information may be interpreted as including an error range that may occur due to various factors (e.g., process factors, internal or external impact, noise, etc.), even if not otherwise explicitly stated.

[0021] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0022] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0023] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 including a plurality of sub-pixels (SP), and a driving circuit for driving the plurality of sub-pixels (SP) included in the display panel 110.

[0024] The driving circuit includes a data driving circuit 120 and a gate driving circuit 130 , and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130 .

[0025] The display panel 110 may include a substrate (SUB) and signal lines such as a plurality of data lines (DL) and a plurality of gate lines (GL) disposed on the substrate (SUB). The plurality of data lines (DL) and the plurality of gate lines (GL) may be connected to a plurality of sub-pixels (SP).

[0026] The display panel 110 may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display area (DA) of the display panel 110, a plurality of sub-pixels (SP) for displaying an image are arranged, and in the non-display area (NDA), the driver circuits 120, 130, and the controller 140 are electrically connected or the driver circuits 120, 130, and the controller 140 are mounted, and a pad unit to which an integrated circuit or a printed circuit is connected may be arranged.

[0027] The data driving circuit 120 is a circuit for driving a plurality of data lines (DL), and can supply data signals to the plurality of data lines (DL).

[0028] The gate driving circuit 130 is a circuit for driving a plurality of gate lines (GL) and can supply gate signals to the plurality of gate lines (GL).

[0029] The controller 140 can supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120, and can supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0030] The controller 140 starts scanning according to the timing configured for each frame, converts the input image data input from the outside to match the data signal format used by the data driving circuit 120, supplies the converted image data (Data) to the data driving circuit 120, and controls data driving at an appropriate time in accordance with the scan.

[0031] The controller 140 receives various timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), a clock signal (CLK), and the like, along with input video data from an external device (e.g., a host system 150).

[0032] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 receives timing signals such as a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK), generates various control signals (DCS, GCS), and outputs them to the data driving circuit 120 and the gate driving circuit 130.

[0033] For example, the controller 140 outputs various gate control signals (GCS) including a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc. to control the gate driving circuit 130.

[0034] In addition, the controller 140 outputs various data control signals (DCS: Data Control Signals) including a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), a source output enable signal (SOE: Source Output Enable), etc. to control the data driving circuit 120.

[0035] The controller 140 may be configured as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 to form an integrated circuit.

[0036] The data driving circuit 120 receives image data from the controller 140 and supplies data voltages to the data lines DL, thereby driving the data lines DL. Here, the data driving circuit 120 is also referred to as a source driving circuit.

[0037] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs).

[0038] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. Each source driver integrated circuit (SDIC) may further include an analog-to-digital converter (ADC) in some cases.

[0039] For example, each source driver integrated circuit (SDIC) may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be configured using a chip on film (COF) method and connected to the display panel 110.

[0040] The gate driving circuit 130 can output gate signals of turn-on level voltages or gate signals of turn-off level voltages under the control of the controller 140. The gate driving circuit 130 can sequentially drive the plurality of gate lines (GL) by sequentially supplying gate signals of turn-on level voltages to the plurality of gate lines (GL).

[0041] The gate driving circuit 130 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method, or may be connected to the display panel 110 using a chip-on-film (COF) method. Alternatively, the gate driving circuit 130 may be formed in the non-display area (NDA) of the display panel 110 in a gate-in-panel (GIP) type. The gate driving circuit 130 may be disposed on or connected to the substrate (SUB). That is, in the case of a GIP type, the gate driving circuit 130 may be disposed in the non-display area (NDA) of the substrate (SUB). In the case of a chip-on-glass (COG) type or chip-on-film (COF) type, the gate driving circuit 130 may be connected to the substrate (SUB).

[0042] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area (DA). For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed so as not to overlap with the sub-pixels (SP), or may be disposed so as to overlap partially or entirely with the sub-pixels (SP).

[0043] When the gate line (GL) selected by the gate driving circuit 130 is driven, the data driving circuit 120 can convert the image data (Data) received from the controller 140 into an analog data voltage and supply it to a plurality of data lines (DL).

[0044] The data driving circuit 120 may be connected to one side (e.g., the top or bottom) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the top and bottom) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0045] The gate driving circuit 130 may be connected to one side (e.g., the left or right side) of the display panel 110. Depending on the gate driving method and panel design method, the gate driving circuit 130 may be connected to both sides (e.g., the left and right sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0046] The controller 140 may be a timing controller used in conventional display technology, a controller that includes a timing controller and can perform other control functions, a controller different from a timing controller, or a circuit within the controller. The controller 140 may be composed of various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0047] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0048] The controller 140 may transmit and receive signals to and from the data driving circuit 120 through one or more predetermined interfaces, where the interfaces may include, for example, a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point to Point Interface (EPI), a Serial Peripheral Interface (SPI), etc.

[0049] The controller 140 may include a storage medium such as one or more registers.

[0050] The display device 100 according to this embodiment may be a display including a backlight unit such as a liquid crystal display device, or may be a self-luminous display such as an organic light emitting display device, a quantum dot display device, or an inorganic light emitting display device.

[0051] When the display device 100 according to this embodiment is an organic light emitting display device, each sub-pixel (SP) may include an organic light emitting diode (OLED) as a light emitting element.

[0052] When the display device 100 according to this embodiment is a quantum dot display device, each sub-pixel (SP) may include a light-emitting element made of quantum dots, which are semiconductor elements that emit light themselves.

[0053] When the display device 100 according to this embodiment is an inorganic light emitting display device, each subpixel (SP) may include an inorganic light emitting element that emits light by itself and is made of an inorganic material on a substrate as a light emitting element. For example, an inorganic light emitting element is also called a micro or nano unit light emitting diode (LED), and an inorganic light emitting display device is also called a micro LED display device or a nano LED display device.

[0054] FIG. 2 is an equivalent circuit of a sub-pixel (SP) in a display panel 110 according to an embodiment of the present disclosure.

[0055] Referring to FIG. 2, each of a plurality of sub-pixels (SP) arranged on a display panel 110 according to an embodiment of the present disclosure may include a light emitting element (ED) and a sub-pixel circuit (SPC) for driving the light emitting element (ED).

[0056] The sub-pixel circuit (SPC) of each sub-pixel (SP) may include a drive transistor (DRT), a scan transistor (SCT), a sensing transistor (SENT), and a storage capacitor (Cst). In this case, the sub-pixel circuit (SPC) of each sub-pixel (SP) includes three transistors (DRT, SCT, SENT) and one capacitor (Cst), and therefore can be said to have a 3T (Transistor) 1C (Capacitor) structure.

[0057] Referring to FIG. 2, the light emitting element (ED) may include a pixel electrode (PE) and a common electrode (CE), and an emitting layer (EL) disposed between the pixel electrode (PE) and the common electrode (CE).

[0058] The pixel electrode (PE) is an electrode connected to a transistor such as a drive transistor (DRT) and may be an electrode disposed for each subpixel (SP). The common electrode (CE) may be an electrode to which a common voltage is applied, or may be an electrode commonly disposed for all subpixels (SP). For example, the common voltage may be a drive voltage (EVDD) that is a high-level common voltage or a ground voltage (EVSS) that is a low-level common voltage.

[0059] When the ground voltage (EVSS) is applied to the common electrode (CE), the common electrode (CE) may receive the ground voltage (EVSS) through the ground voltage line (BVL).

[0060] 2, the pixel electrode (PE) may be an anode electrode and the common electrode (CE) may be a cathode electrode, or alternatively, the pixel electrode (PE) may be a cathode electrode and the common electrode (CE) may be an anode electrode.

[0061] For example, the light emitting device (ED) may be an organic light emitting diode (OLED), an inorganic-based light emitting diode (LED), or a quantum dot light emitting device.

[0062] Referring to FIG. 2, the driving transistor DRT is a transistor for driving the light emitting element ED, and may include a first node N1, a second node N2, and a third node N3.

[0063] The first node (N1) of the driving transistor (DRT) is the source node or drain node of the driving transistor (DRT), and is electrically connected to the source node or drain node of the sensing transistor (SENT), and may also be electrically connected to the pixel electrode (PE) of the light emitting element (ED).

[0064] The second node (N2) of the driving transistor (DRT) is a gate node of the driving transistor (DRT) and may be electrically connected to the source node or the drain node of the scan transistor (SCT).

[0065] The third node (N3) of the driving transistor (DRT) may be electrically connected to a driving voltage line (DVL) that supplies a driving voltage (EVDD).

[0066] 2, the scan transistor (SCT) can be controlled by a scan signal (SC), which is a type of gate signal, to be connected between the second node (N2) of the drive transistor (DRT) and the data line (DL). In other words, the scan transistor (SCT) can be turned on or off by the scan signal (SC) supplied from the scan signal line (SCL), which is a type of gate line (GL), to control the connection between the data line (DL) and the second node (N2) of the drive transistor (DRT).

[0067] The scan transistor (SCT) is turned on by a scan signal (SC) having a turn-on level voltage and can transmit a data voltage (Vdata) supplied from the data line (DL) to the second node (N2) of the drive transistor (DRT).

[0068] Here, when the scan transistor (SCT) is an n-type transistor, the turn-on level voltage of the scan signal (SC) may be a high level voltage. When the scan transistor (SCT) is a p-type transistor, the turn-on level voltage of the scan signal (SC) may be a low level voltage. In the following, an example will be given in which the scan transistor (SCT) is an n-type transistor, and an example will be given in which the turn-on level voltage is a high level voltage.

[0069] 2, the sensing transistor (SENT) can be controlled by a sensing signal (SE), which is a type of gate signal, and can be connected between the first node (N1) of the driving transistor (DRT) and the reference voltage line (RVL). In other words, the sensing transistor (SENT) can be turned on or off by the sensing signal (SE) supplied from a sensing signal line (SENL), which is another type of gate line (GL), to control the connection between the reference voltage line (RVL) and the first node (N1) of the driving transistor (DRT).

[0070] The sensing transistor (SENT) is turned on by a sensing signal (SE) having a turn-on level voltage and may transmit a reference voltage (Vref) supplied from a reference voltage line (RVL) to a first node (N1) of the driving transistor (DRT). Here, the sensing signal (SE) may be a second scan signal different from the scan signal (SC).

[0071] In addition, the sensing transistor SENT may be turned on by a sensing signal SE having a turn-on level voltage to transfer the voltage of the first node N1 of the driving transistor DRT to the reference voltage line RVL.

[0072] Here, when the sensing transistor (SENT) is an n-type transistor, the turn-on level voltage of the sensing signal (SE) may be a high level voltage. When the sensing transistor (SENT) is a p-type transistor, the turn-on level voltage of the sensing signal (SE) may be a low level voltage. In the following, an example in which the sensing transistor (SENT) is an n-type transistor will be given, and an example in which the turn-on level voltage is a high level voltage will be given.

[0073] The function of the sensing transistor (SENT) to transfer the voltage of the first node (N1) of the driving transistor (DRT) to the reference voltage line (RVL) can be used when driving to sense the characteristic value of the sub-pixel (SP). In this case, the voltage transferred to the reference voltage line (RVL) can be a voltage for calculating the characteristic value of the sub-pixel (SP) or a voltage reflecting the characteristic value of the sub-pixel (SP).

[0074] In the present disclosure, the characteristic value of the subpixel (SP) may be a characteristic value of the driving transistor (DRT) or the light emitting element (ED). For example, the characteristic value of the driving transistor (DRT) may include a threshold voltage and mobility of the driving transistor (DRT). The characteristic value of the light emitting element (ED) may include a threshold voltage of the light emitting element (ED).

[0075] 2, the storage capacitor Cst may be connected between the second node N2 and the first node N1 of the driving transistor DRT. The storage capacitor Cst may be charged with an amount of charge corresponding to the voltage difference between both ends and may serve to maintain the voltage difference between both ends for a predetermined frame time. This allows the corresponding subpixel SP to emit light for the predetermined frame time.

[0076] In this specification, the source node, drain node, and gate node of various transistors (DRT, SCT, SENT) are also referred to as the source electrode, drain electrode, and gate electrode.

[0077] 2, the drive transistor (DRT), the scan transistor (SCT), and the sensing transistor (SENT) may each be an n-type transistor or a p-type transistor. For convenience of explanation, this disclosure will cite an example in which the drive transistor (DRT), the scan transistor (SCT), and the sensing transistor (SENT) are each an n-type transistor.

[0078] The storage capacitor (Cst) may be an external capacitor intentionally designed outside the drive transistor (DRT), rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor present between the gate node and the source node (or drain node) of the drive transistor (DRT).

[0079] The sub-pixels (SP) illustrated in FIG. 2 are merely examples and may be modified in various ways by further including one or more transistors or one or more capacitors.

[0080] 2, in one example, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) may not be connected, i.e., the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) may be connected to different gate lines (GL).

[0081] In this case, the on-off of the scan transistor (SCT) and the on-off of the sensing transistor (SENT) can be controlled independently.

[0082] 2, in another example, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) may be electrically connected to each other, i.e., the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) may be commonly connected to one gate line (GL).

[0083] In this case, the on-off of the scan transistor (SCT) and the on-off of the sensing transistor (SENT) can both be controlled.

[0084] The display panel 110 according to the embodiment of the present disclosure may have a top emission structure in which light emitted from the light emitting element (ED) is emitted in a direction away from the substrate (SUB), or a bottom emission structure in which light emitted from the light emitting element (ED) is emitted in the direction of the substrate (SUB). For convenience of explanation, the following description will be given assuming that the display panel 110 according to the embodiment of the present disclosure has a bottom emission structure.

[0085] FIG. 3 is a schematic plan view of a sub-pixel (SP) of a display device 100 according to an embodiment of the present disclosure.

[0086] Referring to FIG. 3, each sub-pixel (SP) may include an emissive area (EA) and a sub-pixel circuit (SPC).

[0087] Referring to FIG. 3, a pixel electrode (PE) may be disposed in the light emitting area (EA).

[0088] Referring to FIG. 3, a portion of the pixel electrode (PE) may be extended to an area where the sub-pixel circuit (SPC) is disposed, and may be electrically connected to an electrode (e.g., source electrode or drain electrode) corresponding to the first node (N1) of the driving transistor (DRT) in the sub-pixel circuit (SPC) through a contact hole (CNT).

[0089] FIG. 4 is an equivalent circuit diagram of first and second sub-pixels (SP1, SP2) adjacent to each other in the column direction in a display device 100 according to an embodiment of the present disclosure.

[0090] Each of the first sub-pixel (SP1) and the second sub-pixel (SP2) has the same structure (equivalent circuit) as the sub-pixel (SP) in FIG.

[0091] The first sub-pixel SP1 and the second sub-pixel SP2 may be arranged adjacent to each other in a column direction, where the column direction may refer to the direction in which the data line DL extends.

[0092] The first sub-pixel (SP1) may include a first light-emitting element (ED1) and a first sub-pixel circuit (SPC1) for driving the first light-emitting element (ED1).

[0093] The first sub-pixel circuit (SPC1) may include a first driving transistor (DRT1), a first scan transistor (SCT1), a first sensing transistor (SENT1), and a first storage capacitor (Cst1).

[0094] The first driving transistor (DRT1) may include a first node (N1), a second node (N2), and a third node (N3). Hereinafter, for convenience of explanation, the first node (N1), the second node (N2), and the third node (N3) of the first driving transistor (DRT1) will be referred to as a first source electrode (S1), a first gate electrode (G1), and a first drain electrode (D1).

[0095] The first scan transistor (SCT1) can control the connection between the data line (DL) and the first gate electrode (G1) of the first drive transistor (DRT1) according to the first scan signal (SC1).

[0096] The first sensing transistor (SENT1) can control the connection between the reference voltage line (RLV) and the first source electrode (S1) of the first driving transistor (DRT1) according to the first sensing signal (SE1).

[0097] The first storage capacitor Cst1 may be formed between the first gate electrode G1 and the first source electrode S1 of the first driving transistor DRT1.

[0098] The first light emitting element (ED1) may include a first pixel electrode (PE1), an emitting layer (EL), and a common electrode (CE).

[0099] The second sub-pixel (SP2) may include a second light-emitting element (ED2) and a second sub-pixel circuit (SPC2) for driving the second light-emitting element (ED2).

[0100] The second sub-pixel circuit (SPC2) may include a second driving transistor (DRT2), a second scan transistor (SCT2), a second sensing transistor (SENT2), and a second storage capacitor (Cst2).

[0101] The second driving transistor (DRT2) may include a first node (N1), a second node (N2), and a third node (N3). Hereinafter, for convenience of explanation, the first node (N1), the second node (N2), and the third node (N3) of the second driving transistor (DRT2) will be referred to as a second source electrode (S2), a second gate electrode (G2), and a second drain electrode (D2).

[0102] The second scan transistor (SCT2) can control the connection between the data line (DL) and the second gate electrode (G2) of the second drive transistor (DRT2) according to the second scan signal (SC2).

[0103] The second sensing transistor (SENT2) can control the connection between the reference voltage line (RLV) and the second source electrode (S2) of the second driving transistor (DRT2) according to the second sensing signal (SE2).

[0104] The second storage capacitor Cst2 may be formed between the second gate electrode G2 and the second source electrode S2 of the second driving transistor DRT2.

[0105] The second light emitting element (ED2) may include a second pixel electrode (PE2), an emitting layer (EL), and a common electrode (CE).

[0106] Meanwhile, the display device 100 according to an embodiment of the present disclosure may have a repair structure that can improve the aperture ratio while facilitating repair to normalize the defective subpixel (SP) when a defect occurs in the subpixel circuit (SPC) in the subpixel (SP) during the panel manufacturing process.

[0107] 5 and 6 show a symmetrical structure of first and second sub-pixels (SP1, SP2) adjacent to each other in the column direction in a display device 100 according to an embodiment of the present disclosure, although the following description will also refer to FIG. 4.

[0108] Referring to FIGS. 5 and 6, the first sub-pixel SP1 and the second sub-pixel SP2 may be arranged adjacent to each other in the column direction.

[0109] The first sub-pixel (SP1) may include a first light-emitting area (EA1) and a first sub-pixel circuit (SPC1).

[0110] A first pixel electrode (PE1) is disposed in the first light-emitting area (EA1), and a portion of the first pixel electrode (PE1) extends to an area where the first sub-pixel circuit (SPC1) is disposed and can be electrically connected to a certain point (point) in the first sub-pixel circuit (SPC1) (e.g., the first source electrode (S1) of the first driving transistor (DRT1)) through a first contact hole (CNT1).

[0111] The second subpixel (SP2) may include a second light-emitting area (EA2) and a second subpixel circuit (SPC2).

[0112] A second pixel electrode (PE2) is disposed in the second light-emitting area (EA2), and a portion of the second pixel electrode (PE2) extends to an area where the second sub-pixel circuit (SPC2) is disposed and can be electrically connected to a portion of the second sub-pixel circuit (SPC2) (e.g., the second source electrode (S2) of the second driving transistor (DRT2)) through a second contact hole (CNT2).

[0113] Referring to FIGS. 5 and 6, the first sub-pixel (SP1) and the second sub-pixel (SP2) may have a symmetrical structure with respect to the boundary between the first sub-pixel (SP1) and the second sub-pixel (SP2).

[0114] Referring to Figures 5 and 6, due to the symmetrical structure of the first subpixel (SP1) and the second subpixel (SP2), the first subpixel circuit (SPC1) may be arranged closer to the second light-emitting area (EA2) and the second subpixel circuit (SPC3) among the second light-emitting area (EA2) and the second subpixel circuit (SPC2).

[0115] Referring to FIG. 6, according to the symmetrical structure of the first sub-pixel (SP1) and the second sub-pixel (SP2), the first source electrode (S1) may be disposed closer to the second source electrode (S2) among the second source electrode (S2) and the second pixel electrode (PE2).

[0116] Referring to Figures 5 and 6, when the first subpixel (SP1) and the second subpixel (SP2) are normal subpixels (SP), the first subpixel circuit (SPC1) can supply a first current (I1) to the first light-emitting element (ED1), and the second subpixel circuit (SPC2) can supply a second current (I2) to the second light-emitting element (ED2).

[0117] According to this, a first current (I1) can flow from the first source electrode (S1) of the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) can flow from the second source electrode (S2) of the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0118] 7 illustrates a situation in which a defect occurs in the second sub-pixel SP2 among the first and second sub-pixels SP1 and SP2 adjacent to each other in the column direction in the display device 100 according to an embodiment of the present disclosure, although the following description will also refer to FIGS. 4 to 6.

[0119] 7, during the panel manufacturing process, a defect may occur in the second subpixel circuit (SPC2) of the second subpixel (SP2) among the first subpixel (SP1) and the second subpixel (SP2). In this case, the second subpixel (SP2) may not emit light normally, resulting in a deterioration in image quality.

[0120] For example, if a defect (e.g., a circuit break) occurs in the second subpixel circuit (SPC2), current is not supplied to the second light-emitting element (ED2) in the second subpixel circuit (SPC2), and the second light-emitting element (ED2) cannot emit light. In this case, the second subpixel (SP2) appears as a dark spot, and an image abnormality may occur.

[0121] For example, a defect occurring in the second sub-pixel circuit (SPC2) may be a defect in the second driving transistor (DRT2) in the second sub-pixel circuit (SPC2). For example, if at least one of the second source electrode (S2), the second drain electrode (D2), and the second gate electrode (G2) of the second driving transistor (DRT2) is broken due to foreign matter generated during the process, the defect in the second driving transistor (DRT2) may occur.

[0122] In this specification, a sub-pixel (SP) in which a defect occurs is also referred to as a defective sub-pixel, and a sub-pixel (SP) in which no defect occurs is also referred to as a normal sub-pixel.

[0123] Fig. 8 shows a repair structure of the display device 100 according to an embodiment of the present disclosure, and Fig. 9 is a cross-sectional view taken along line XX' in Fig. 8. It is assumed that the first sub-pixel (SP1) and the second sub-pixel (SP2) shown in Fig. 8 and Fig. 9 are normal sub-pixels.

[0124] Referring to FIG. 8, the first sub-pixel SP1 includes a first pixel electrode PE1 and a first source electrode S1, and the second sub-pixel SP2 includes a second pixel electrode PE2 and a second source electrode S2.

[0125] Each of the first source electrode (S1) and the second source electrode (S2) may be formed of a single metal layer, or each of the first source electrode (S1) and the second source electrode (S2) may be formed of multiple metal layers, or each of the first source electrode (S1) and the second source electrode (S2) may include multiple electrodes electrically connected to each other.

[0126] If the first subpixel (SP1) is a normal subpixel, a first current (I1) may flow from the first source electrode (S1) to the first pixel electrode (PE1). If the second subpixel (SP2) is a normal subpixel, a second current (I2) may flow from the second source electrode (S2) to the second pixel electrode (PE2).

[0127] Referring to Figures 8 and 9, the display device 100 according to an embodiment of the present disclosure may include a repair structure for repairing a defect when a defect occurs in either the first sub-pixel (SP1) or the second sub-pixel (SP2).

[0128] Referring to Figures 8 and 9, the repair structure of the display device 100 according to an embodiment of the present disclosure may include an overlap pattern (OP) that overlaps vertically with at least one of the first source electrode (S1) and the second source electrode (S2).

[0129] Referring to Figures 8 and 9, the repair structure of the display device 100 according to an embodiment of the present disclosure may include a first lower metal (LM1) connected to the first source electrode (S1) and a second lower metal (LM2) connected to the second source electrode (S2).

[0130] Referring to FIGS. 8 and 9, the first lower metal LM1 may be disposed in the region of the first sub-pixel SP1, and the second lower metal LM2 may be disposed in the region of the second sub-pixel SP2.

[0131] In this case, as shown in FIG. 9, in one example, the overlap pattern (OP) may include a first part (PART1) overlapping with a portion of the first lower metal (LM1), a second part (PART2) overlapping with a portion of the second lower metal (LM2), and a third part (PART3) between the first part (PART1) and the second part (PART2).

[0132] Referring to FIG. 9, a first lower metal (LM1) and a second lower metal (LM2) are disposed on a substrate (SUB), a first buffer layer (BUF1) is disposed on the first lower metal (LM1) and the second lower metal (LM2), and an overlapping pattern (OP) may be disposed on the first buffer layer (BUF1).

[0133] Therefore, the first lower metal (LM1) and the second lower metal (LM2) can be separated from the overlapping pattern (OP) by the first buffer layer (BUF1).

[0134] The first lower metal (LM1) and the second lower metal (LM2) may be formed in the lowest metal layer closest to the substrate (SUB) from the display panel 110. The overlapping pattern (OP) may be formed in the second lowest metal layer second closest to the substrate (SUB) from the display panel 110.

[0135] The first lower metal (LM1) may overlap the first drive transistor (DRT1), and the second lower metal (LM2) may overlap the second drive transistor (DRT2). For example, the first lower metal (LM1) may overlap the first active layer (ACT1) of the first drive transistor (DRT1), and the second lower metal (LM2) may overlap the second active layer (ACT2) of the second drive transistor (DRT2).

[0136] 10 illustrates a welding repair process when a defect occurs in a second subpixel circuit (SPC2) in a second subpixel (SP2) among first and second subpixels (SP1, SP2) adjacent in a column direction in a display device 100 according to an embodiment of the present disclosure. FIG. 11 is a cross-sectional view taken along line X-X' in FIG.

[0137] Referring to Figures 10 and 11, the first lower metal (LM1) may be connected to the first source electrode (S1) of the first driving transistor (DRT1), and the second lower metal (LM2) may be connected to the first source electrode (S2) of the second driving transistor (DRT2).

[0138] 10 and 11, before the welding repair process, the first portion (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) can be spaced apart from each other and electrically isolated from each other, and the second portion (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be spaced apart from each other and electrically isolated from each other.

[0139] Referring to Figures 10 and 11, when a fault occurs in the second subpixel circuit (SPC2) in the second subpixel (SP2) among the first and second subpixels (SP1, SP2) adjacent in the column direction, the first part (PART1) of the overlapping pattern (OP) can be electrically connected to the first lower metal (LM1) through laser welding, and the second part (PART2) of the overlapping pattern (OP) can be electrically connected to the second lower metal (LM2).

[0140] By laser welding, a first welding pattern (WPTN1) can be formed between a first part (PART1) of the overlapping pattern (OP) and a first lower metal (LM1), and a second welding pattern (WPTN2) can be formed between a second part (PART2) of the overlapping pattern (OP) and a second lower metal (LM2).

[0141] The first welding pattern (WPTN1) may be formed by welding to at least one of the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1), or may be a pattern made of a different material from the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1).

[0142] The second welding pattern (WPTN2) may be formed by welding to at least one of the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2), or may be a pattern made of a different material from the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0143] As a result, the first driving transistor DRT1 not only supplies the first current I1 to the first pixel electrode PE1 but also to the second pixel electrode PE2, causing the first light emitting element ED1 of the first sub-pixel SP1 to emit light and the second light emitting element ED2 of the second sub-pixel SP2 to emit light.

[0144] Even if a defect occurs in the second subpixel circuit (SPC2) of the second subpixel (SP2), the second light-emitting element (ED2) can emit light normally through the first driving transistor (DRT1) of the first subpixel (SP1), and the second subpixel (SP2) can operate normally.

[0145] FIG. 12 is an equivalent circuit showing cutting points (CP1, CP2, CP3) for disabling the second subpixel circuit (SPC2) in the second subpixel (SP2) when a defect occurs in the second subpixel circuit (SPC2) in the second subpixel (SP2) among the first and second subpixels (SP1, SP2) adjacent in the column direction in a display device 100 according to an embodiment of the present disclosure.

[0146] Referring to FIG. 12, the display panel 110 according to an embodiment of the present disclosure may include a driving voltage line (DVL) that transmits a driving voltage (EVDD) to the first drain electrode (D1) of the first driving transistor (DRT1) and the second drain electrode (D2) of the second driving transistor (DRT2).

[0147] Referring to FIG. 12, a display panel 110 according to an embodiment of the present disclosure may include a data line (DL) for transmitting a data voltage (Vdata), a first scan transistor (SCT1) for controlling a connection between the data line (DL) and a first gate electrode (G1) of a first drive transistor (DRT1), and a second scan transistor (SCT2) for controlling a connection between the data line (DL) and a second gate electrode (G2) of a second drive transistor (DRT2).

[0148] Referring to FIG. 12, a display panel 110 according to an embodiment of the present disclosure may include a reference voltage line (RVL) for transmitting a reference voltage, a first sensing transistor (SENT1) for controlling a connection between the reference voltage line (RVL) and a first source electrode (S1) of a first driving transistor (DRT1), and a second sensing transistor (SENT2) for controlling a connection between the reference voltage line (RVL) and a second source electrode (S2) of a second driving transistor (DRT2).

[0149] Referring to FIG. 12, when a defect occurs in the second subpixel circuit (SPC2) of the second subpixel (SP2) among the first and second subpixels (SP1, SP2) adjacent in the column direction, at least one of the driving voltage (EVDD), the data voltage (Vdata), and the reference voltage (Vref) needs to be prevented from being supplied to the second subpixel circuit (SPC2) in order to disable the second subpixel circuit (SPC2) of the second subpixel (SP2).

[0150] Referring to FIG. 12, the cutoff points for disabling the second subpixel circuit (SPC2) in the second subpixel (SP2) may include a first cutoff point (CP1) for cutting off the supply of the driving voltage (EVDD), a second cutoff point (CP2) for cutting off the supply of the data voltage (Vdata), and a third cutoff point (CP3) for cutting off the supply of the reference voltage (Vref).

[0151] Referring to FIG. 12, the first cutting point (CP1) may be a connection point between the driving voltage line (DVL) and the second sub-pixel circuit (SPC2), the second cutting point (CP2) may be a connection point between the data line (DL) and the second sub-pixel circuit (SPC2), and the third cutting point (CP3) may be a connection point between the reference voltage line (RVL) and the second sub-pixel circuit (SPC2).

[0152] 12, when the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are both normal, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2). At this time, the driving voltage line (DVL) may be electrically connected to the first drain electrode (D1), and the driving voltage line (DVL) may be electrically connected to the second drain electrode (D2).

[0153] 12, when the second subpixel circuit (SPC2) of the first and second subpixel circuits (SPC1 and SPC2) is defective, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2). At this time, the driving voltage line (DVL) may be electrically connected to the first drain electrode (D1), and the driving voltage line (DVL) may be electrically disconnected from the second drain electrode (D2).

[0154] 12, when the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are both normal, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2). At this time, the data line (DL) may be connected to the first scan transistor (SCT1), and the data line (DL) may be connected to the second scan transistor (SCT2).

[0155] 12, when the second subpixel circuit (SPC2) of the first and second subpixel circuits (SPC1 and SPC2) is defective, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2). At this time, the data line (DL) and the first scan transistor (SCT1) may be connected, and the data line (DL) and the second scan transistor (SCT2) may be disconnected.

[0156] 12, when the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are both normal, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2). At this time, the reference voltage line (RVL) and the first sensing transistor (SENT1) may be connected, and the reference voltage line (RVL) and the second sensing transistor (SENT2) may be connected.

[0157] 12, if the second subpixel circuit SPC2 is defective among the first and second subpixel circuits SPC1 and SPC2, a first current I1 may be supplied from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2. At this time, the reference voltage line RVL may be connected to the first sensing transistor SENT1, and the reference voltage line RVL may be disconnected from the second sensing transistor SENT2.

[0158] 13 shows first to eighth sub-pixels (SP1 to SP8) in a display panel 110 according to an embodiment of the present disclosure. FIG. 14 is a plan view of a circuit cluster region 1500 of FIG.

[0159] 13, the first sub-pixel (SP1), the third sub-pixel (SP3), the fifth sub-pixel (SP5), and the seventh sub-pixel (SP7) may be arranged in the row direction in the first sub-pixel row (ROW1), and the second sub-pixel (SP2), the fourth sub-pixel (SP4), the sixth sub-pixel (SP6), and the eighth sub-pixel (SP8) may be arranged in the row direction in the second sub-pixel row (ROW2).

[0160] 13, the first subpixel (SP1) and the second subpixel (SP2) may be arranged in the first subpixel column (COL1) and adjacent to each other in the column direction. The third subpixel (SP3) and the fourth subpixel (SP4) may be arranged in the second subpixel column (COL2) and adjacent to each other in the column direction. The fifth subpixel (SP5) and the sixth subpixel (SP6) may be arranged in the third subpixel column (COL3) and adjacent to each other in the column direction. The seventh subpixel (SP7) and the eighth subpixel (SP8) may be arranged in the fourth subpixel column (COL4) and adjacent to each other in the column direction.

[0161] Referring to FIG. 13, the first subpixel (SP1) may include a first light-emitting area (EA1) and a first subpixel circuit (SPC1). The second subpixel (SP2) may include a second light-emitting area (EA2) and a second subpixel circuit (SPC2). The third subpixel (SP3) may include a third light-emitting area (EA3) and a third subpixel circuit (SPC3). The fourth subpixel (SP4) may include a fourth light-emitting area (EA4) and a fourth subpixel circuit (SPC4). The fifth subpixel (SP5) may include a fifth light-emitting area (EA5) and a fifth subpixel circuit (SPC5). The sixth subpixel (SP6) may include a sixth light-emitting area (EA6) and a sixth subpixel circuit (SPC6). The seventh subpixel (SP7) may include a seventh light-emitting area (EA7) and a seventh subpixel circuit (SPC7). The eighth sub-pixel (SP8) may include an eighth light-emitting area (EA8) and an eighth sub-pixel circuit (SPC8).

[0162] 13, the first and second sub-pixels SP1 and SP2 adjacent to each other in the column direction may have a symmetrical structure with respect to the boundary, such that the first and second sub-pixel circuits SPC1 and SPC2 are disposed between the first and second light-emitting regions EA1 and EA2, and the first and second sub-pixel circuits SPC1 and SPC2 may be disposed adjacent to each other.

[0163] 13, the third sub-pixel SP3 and the fourth sub-pixel SP4 adjacent to each other in the column direction may have a symmetrical structure with respect to the boundary, such that the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 are disposed between the third light-emitting region EA3 and the fourth light-emitting region EA4, and the third sub-pixel circuit SPC3 and the fourth sub-pixel circuit SPC4 may be disposed adjacent to each other.

[0164] 13, the fifth sub-pixel SP5 and the sixth sub-pixel SP6 adjacent to each other in the column direction may have a symmetrical structure with respect to the boundary, such that the fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 are disposed between the fifth light-emitting region EA5 and the sixth light-emitting region EA6, and the fifth sub-pixel circuit SPC5 and the sixth sub-pixel circuit SPC6 may be disposed adjacent to each other.

[0165] 13, the seventh sub-pixel SP7 and the eighth sub-pixel SP8 adjacent to each other in the column direction may have a symmetrical structure with respect to the boundary, such that the seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 are disposed between the seventh light-emitting region EA7 and the eighth light-emitting region EA8, and the seventh sub-pixel circuit SPC7 and the eighth sub-pixel circuit SPC8 may be disposed adjacent to each other.

[0166] Hereinafter, the symmetrical structure of two sub-pixels (SP) adjacent to each other in the column direction will be referred to as a "vertically symmetrical structure."

[0167] Referring to FIG. 13, a schematic planar structure of a circuit cluster region 1500 where the first to eighth sub-pixel circuits (SPC1 to SPC8) are clustered is shown in FIG.

[0168] 14, the first subpixel circuit (SPC1) may include a first driving transistor (DRT1), a first scan transistor (SCT1), a first sensing transistor (SENT1), and a first storage capacitor (Cst1). The second subpixel circuit (SPC2) may include a second driving transistor (DRT2), a second scan transistor (SCT2), a second sensing transistor (SENT2), and a second storage capacitor (Cst2). The third subpixel circuit (SPC3) may include a third driving transistor (DRT3), a third scan transistor (SCT3), a third sensing transistor (SENT3), and a third storage capacitor (Cst3). The fourth subpixel circuit (SPC4) may include a fourth driving transistor (DRT4), a fourth scan transistor (SCT4), a fourth sensing transistor (SENT4), and a fourth storage capacitor (Cst4). The fifth subpixel circuit (SPC5) may include a fifth drive transistor (DRT5), a fifth scan transistor (SCT5), a fifth sensing transistor (SENT5), and a fifth storage capacitor (Cst5). The sixth subpixel circuit (SPC6) may include a sixth drive transistor (DRT6), a sixth scan transistor (SCT6), a sixth sensing transistor (SENT6), and a sixth storage capacitor (Cst6). The seventh subpixel circuit (SPC7) may include a seventh drive transistor (DRT7), a seventh scan transistor (SCT7), a seventh sensing transistor (SENT7), and a seventh storage capacitor (Cst7). The eighth subpixel circuit (SPC8) may include an eighth drive transistor (DRT8), an eighth scan transistor (SCT8), an eighth sensing transistor (SENT8), and an eighth storage capacitor (Cst8).

[0169] The arrangement structure of the column wirings (DL1 to DL4, DVL, RVL) will be described with reference to FIG.

[0170] 14, a first data line DL1 and a second data line DL2 may be disposed between a first sub-pixel column COL1 and a second sub-pixel column COL2, and a third data line DL3 and a fourth data line DL4 may be disposed between a third sub-pixel column COL3 and a fourth sub-pixel column COL4.

[0171] The first data line (DL1) may supply a first data voltage (Vdata1) to the first subpixel circuit (SPC1) and the second subpixel circuit (SPC2) arranged in the first subpixel column (COL1). The first data line (DL1) may be connected to the first scan transistor (SCT1) in the first subpixel circuit (SPC1) and to the second scan transistor (SCT2) in the second subpixel circuit (SPC2).

[0172] The second data line (DL2) may supply a second data voltage (Vdata2) to the third subpixel circuit (SPC3) and the fourth subpixel circuit (SPC4) arranged in the second subpixel column (COL2). The second data line (DL2) may be connected to the third scan transistor (SCT3) in the third subpixel circuit (SPC3) and to the fourth scan transistor (SCT4) in the fourth subpixel circuit (SPC4).

[0173] The third data line (DL3) may supply a third data voltage (Vdata3) to the fifth subpixel circuit (SPC5) and the sixth subpixel circuit (SPC6) arranged in the third subpixel column (COL3). The third data line (DL3) may be connected to the fifth scan transistor (SCT5) in the fifth subpixel circuit (SPC5) and to the sixth scan transistor (SCT6) in the sixth subpixel circuit (SPC6).

[0174] The fourth data line (DL4) may supply a fourth data voltage (Vdata4) to the seventh subpixel circuit (SPC7) and the eighth subpixel circuit (SPC8) arranged in the fourth subpixel column (COL4). The fourth data line (DL4) may be connected to the seventh scan transistor (SCT7) in the seventh subpixel circuit (SPC7) and the eighth scan transistor (SCT8) in the eighth subpixel circuit (SPC8).

[0175] Referring to FIG. 14, the reference voltage line (RVL) may be disposed between the second sub-pixel column (COL2) and the third sub-pixel column (COL3).

[0176] The reference voltage line (RVL) may be connected to the first to eighth sub-pixel circuits (SPC1 to SPC8) arranged in the first to fourth sub-pixel columns (COL1 to COL4). The reference voltage line (RVL) may be connected to the first to eighth sub-pixel circuits (SPC1 to SPC8) arranged in the first to fourth sub-pixel columns (COL1 to COL4) through the reference connection pattern (CPTN_RVL).

[0177] The reference voltage line (RVL) may supply a reference voltage (Vref) to the drain or source nodes of the first to eighth sensing transistors (SENT1 to SENT8) in the first to eighth subpixel circuits (SPC1 to SPC8) arranged in the first to fourth subpixel columns (COL1 to COL4).

[0178] Referring to FIG. 14, the driving voltage line DVL may be disposed on one side of the first sub-pixel column COL1 and on the other side of the fourth sub-pixel column COL4.

[0179] The driving voltage line (DVL) arranged on one side of the first sub-pixel column (COL1) may be connected to the first to fourth sub-pixel circuits (SPC1 to SPC4) arranged in the first and second sub-pixel columns (COL1, COL2). The driving voltage line (DVL) arranged on one side of the first sub-pixel column (COL1) may be connected to the first to fourth sub-pixel circuits (SPC1 to SPC4) arranged in the first and second sub-pixel columns (COL1, COL2) through the driving connection pattern (CPTN_DVL).

[0180] The driving voltage line (DVL) arranged on one side of the first sub-pixel column (COL1) can supply a driving voltage (EVDD) to the drain nodes or source nodes of the first to fourth scan transistors (SCT1 to SCT4) in the first to fourth sub-pixel circuits (SPC1 to SPC4) arranged in the first and second sub-pixel columns (COL1, COL2).

[0181] The driving voltage line (DVL) arranged on the other side of the fourth sub-pixel column (COL4) may be connected to the fifth to eighth sub-pixel circuits (SPC5 to SPC8) arranged in the third and fourth sub-pixel columns (COL3, COL4). The driving voltage line (DVL) arranged on the other side of the fourth sub-pixel column (COL4) may be connected to the fifth to eighth sub-pixel circuits (SPC5 to SPC8) arranged in the third and fourth sub-pixel columns (COL3, COL4) through the driving connection pattern (CPTN_DVL).

[0182] The driving voltage line (DVL) arranged on the other side of the fourth sub-pixel column (COL4) can supply a driving voltage (EVDD) to the drain nodes or source nodes of the fifth to eighth scan transistors (SCT5 to SCT8) in the fifth to eighth sub-pixel circuits (SPC5 to SPC8) arranged in the third and fourth sub-pixel columns (COL3, COL4).

[0183] Referring to FIG. 14, since the first sub-pixel (SP1) and the second sub-pixel (SP2) have a vertically symmetrical structure, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) can also have a vertically symmetrical structure.

[0184] Referring to FIG. 14, since the third sub-pixel (SP3) and the fourth sub-pixel (SP4) have a vertically symmetrical structure, the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) can also have a vertically symmetrical structure.

[0185] Referring to FIG. 14, since the fifth sub-pixel (SP5) and the sixth sub-pixel (SP6) have a vertically symmetrical structure, the fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) can also have a vertically symmetrical structure.

[0186] Referring to FIG. 14, since the seventh sub-pixel (SP7) and the eighth sub-pixel (SP8) have a vertically symmetrical structure, the seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) can also have a vertically symmetrical structure.

[0187] Hereinafter, a repair structure that can improve the aperture ratio while facilitating repair in the display panel 110 according to the embodiment of the present disclosure will be described.

[0188] Fig. 15 is a plan view of a partial region 1600 of Fig. 14, Fig. 16 is an enlarged plan view of a partial region 1700 of Fig. 15, Fig. 17 is a cross-sectional view taken along line A-A' of Fig. 16, and Fig. 18 is a cross-sectional view of first and second sub-pixels (SP1, SP2) adjacent in the column direction in a display device 100 according to an embodiment of the present disclosure. Fig. 19 is a plan view of a display panel 110 that has been repaired, as a plan view of the partial region 1600 of Fig. 14.

[0189] 15, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) may be adjacent to each other in the column direction and have a vertically symmetrical structure. The third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) may be adjacent to each other in the column direction and have a vertically symmetrical structure. The fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) may be adjacent to each other in the column direction and have a vertically symmetrical structure. The seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) may be adjacent to each other in the column direction and have a vertically symmetrical structure.

[0190] Referring to FIG. 15, the repair structure of the display panel 110 according to an embodiment of the present disclosure may include lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) arranged in each of the subpixel circuits (SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8) having a vertically symmetrical structure, and an overlapping pattern (OP) overlapping with the lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) arranged in each of the subpixel circuits (SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8) having a vertically symmetrical structure.

[0191] Before the repair process, the lower metal (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) can be connected to adjacent positive power supply wiring (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.).

[0192] During repair processing, the connection points between the lower metal (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) and the positive power supply wiring (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.) can be cut. In other words, the connection points between the lower metal (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) and the positive power supply wiring (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.) become cutting points (CP) during repair processing.

[0193] During the repair process, a cutting process for disabling the subpixel circuits may also be performed, as shown in Figure 12. The cutting points (CP1, CP2, CP3) for disabling the subpixel circuits may be connection points between the subpixel circuits to be disabled and the signal wiring (e.g., DL, DVL, RVL).

[0194] Hereinafter, the repair structure will be described in more detail by way of example through the first sub-pixel (SP1) and the second sub-pixel (SP2).

[0195] 15 to 17, in a first subpixel circuit (SPC1) and a second subpixel circuit (SPC2) having a vertically symmetrical structure, a first lower metal (LM1) is disposed in the first subpixel circuit (SPC1), a second lower metal (LM2) is disposed in the second subpixel circuit (SPC2), and an overlapping pattern (OP) may overlap at least a portion of the first lower metal (LM1) and at least a portion of the second lower metal (LM2).

[0196] As shown in FIG. 17, in the first state, the overlapping pattern (OP) may be electrically disconnected from the first lower metal (LM1) and the second lower metal (LM2).

[0197] Alternatively, in the first state, the overlapping pattern (OP) may be electrically connected to one of the first lower metal (LM1) and the second lower metal (LM2) and may be electrically disconnected from the other one.

[0198] In a second state different from the first state, the overlay pattern (OP) may be electrically connected to both the first lower metal (LM1) and the second lower metal (LM2).

[0199] The first state may refer to a state in which the first subpixel (SP1) and the second subpixel (SP2) are both normal subpixels. In the first state, the first subpixel circuit (SPC1) may supply a first current to the first light-emitting element (ED1), and the second subpixel circuit (SPC2) may supply a second current to the second light-emitting element (ED2).

[0200] The second state may mean that, when one of the first subpixel (SP1) and the second subpixel (SP2) is a normal subpixel and the other is a defective subpixel (abnormal subpixel), the defective subpixel has undergone a repair process.

[0201] For example, if the first subpixel (SP1) is a normal subpixel and the second subpixel (SP2) is a defective subpixel (abnormal subpixel) among the first subpixel (SP1) and the second subpixel (SP2), the second state may be a state in which the second subpixel (SP2) is normalized after a repair process.

[0202] In this second state, the first sub-pixel circuit (SPC1) not only supplies the first current to the first light-emitting element (ED1) but also to the second light-emitting element (ED2), and the second sub-pixel circuit (SPC2) is disabled and does not supply current to the second light-emitting element (ED2).

[0203] The repair process may include a welding process (welding repair process) and a cutting process (cutting repair process).

[0204] The welding points (WP), which are the locations for the welding process, may include a location corresponding to the first part (PART1) of the overlapping pattern (OP) and a location corresponding to the second part (PART2) of the overlapping pattern (OP).

[0205] The vertical structure of the display panel 110 including the repair structure will be described in detail with reference to FIGS.

[0206] 17 and 18, a first lower metal (LM1) and a second lower metal (LM2) may be disposed on a substrate (SUB). The first lower metal (LM1) may be disposed in a region of a first sub-pixel circuit (SPC1), and the second lower metal (LM2) may be disposed in a region of a second sub-pixel circuit (SPC2).

[0207] 17 and 18, a first buffer layer (BUF1) may be disposed on a first lower metal (LM1) and a second lower metal (LM2), and an overlap pattern (OP) may be disposed on the first buffer layer (BUF1).

[0208] 17 and 18, the plates (PLT) of the first and second sub-pixel circuits (SPC1, SPC2) may be disposed on a first buffer layer (BUF1) together with an overlapping pattern (OP). The overlapping pattern (OP) and the plates (PLT) of the first and second sub-pixel circuits (SPC1, SPC2) may be located in the same layer and may include the same material.

[0209] Referring to FIGS. 17 and 18, a second buffer layer (BUF2) may be disposed on the plate (PLT) and the overlapping pattern (OP).

[0210] Referring to FIGS. 17 and 18, an active layer pattern may be disposed on the second buffer layer (BUF2).

[0211] For example, the active layer pattern may include a first active layer (ACT1) of the first driving transistor (DRT1), an active layer pattern (AP_SCT1) for forming the active layer of the first scan transistor (SCT1), an active layer pattern (AP_SENT1) for forming the active layer of the first sensing transistor (SENT1), a second active layer (ACT2) of the second driving transistor (DRT2), an active layer pattern (AP_SCT2) for forming the active layer of the second scan transistor (SCT2), and an active layer pattern (AP_SENT2) for forming the active layer of the second sensing transistor (SENT2).

[0212] For example, the active layer pattern may further include a driving connection pattern (CPTN_DVL) for connecting the driving voltage line (DVL) to the first drain electrode (D1) of the first driving transistor (DRT1) and the second drain electrode (D2) of the second driving transistor (DRT2).

[0213] For example, the active layer pattern may include an oxide semiconductor material.

[0214] 17 and 18, a gate insulating layer (GI) may be disposed on the active layer patterns (ACT1, AP_SCT1, AP_SENT1, ACT2, AP_SCT2, AP_SENT2, CPTN_DVL).

[0215] 16, 17, and 18, a first gate electrode (G1) and a first source electrode (S1) of a first driving transistor (DRT1) may be disposed on a gate insulating layer (GI), and a second gate electrode (G2) and a second source electrode (S2) of a second driving transistor (DRT2) may be disposed on the gate insulating layer (GI).

[0216] The first source electrode (S1) may be connected to the first lower metal (LM1) through the gate insulating layer (GI), the second buffer layer (BUF2), and a hole (GI Hole) in the first buffer layer (BUF1).

[0217] The second source electrode (S2) may be connected to the second lower metal (LM2) through the gate insulating layer (GI), the second buffer layer (BUF2), and a hole (GI Hole) in the first buffer layer (BUF1).

[0218] Referring to FIGS. 17 and 18, a passivation layer (PAS) may be disposed on the first gate electrode (G1), the first source electrode (S1), the second gate electrode (G2), and the second source electrode (S2).

[0219] Referring to Figures 17 and 18, an overcoat layer (OC) may be disposed on the passivation layer (PAS).

[0220] 16, 17, and 18, a first pixel electrode PE1 and a second pixel electrode PE2 may be disposed on an overcoat layer (OC). The first pixel electrode PE1 may be connected to a first source electrode S1 through an OC hole in the overcoat layer (OC) and a PAS hole in the passivation layer (PAS). The second pixel electrode PE2 may be connected to a second source electrode S2 through an OC hole in the overcoat layer (OC) and a PAS hole in the passivation layer (PAS).

[0221] 16, 17, and 18, the OC hole and the PAS hole may overlap each other, and the OC hole may be larger than the PAS hole.

[0222] Referring to Figures 16, 17 and 18, the positions of the holes (OCholes) in the overcoat layer (OC) and the holes (PAS holes) in the passivation layer (PAS) may be different from the positions of the holes (GI holes) in the gate insulating layer (GI).

[0223] 17 and 18, a bank (BK) may be disposed on a first pixel electrode (PE1) and a second pixel electrode (PE2). The bank (BK) may include a first opening (not shown) corresponding to (overlapping with) a first light-emitting area (EA1) and a second opening (not shown) corresponding to (overlapping with) a second light-emitting area (EA2). A portion of the first pixel electrode (PE1) may be exposed through the first opening of the bank (BK), and a portion of the second pixel electrode (PE2) may be exposed through the second opening of the bank (BK).

[0224] The repair structure of the display device 100 according to the embodiment of the present disclosure described above will be described again from the perspective of the first sub-pixel (SP1) and the second sub-pixel (SP2) adjacent to each other in the column direction.

[0225] In the display device 100 according to an embodiment of the present disclosure, when the first sub-pixel (SP1) and the second sub-pixel (SP2) have a vertically symmetrical structure and are a set for repair processing, the distance between the first source electrode (S1) of the first driving transistor (DRT1) and the second source electrode (S2) of the second driving transistor (DRT2) may be closer than the distance between the first light-emitting area (EA1) of the first light-emitting element (ED1) and the second light-emitting area (EA2) of the second light-emitting element (ED2).

[0226] A display device 100 according to an embodiment of the present disclosure may include a first subpixel (SP1) including a first driving transistor (DRT1) and a first light-emitting element (ED1), a second subpixel (SP2) including a second driving transistor (DRT2) and a second light-emitting element (ED2), a first lower metal (LM1) connected to a first source electrode (S1) of the first driving transistor (DRT1), a second lower metal (LM2) connected to a second source electrode (S2) of the second driving transistor (DRT2), an overlapping pattern (OP) including a first portion (PART1) overlapping a portion of the first lower metal (LM1), a second portion (PART2) overlapping a portion of the second lower metal (LM2), and a third portion (PART3) between the first portion (PART1) and the second portion (PART2), and a first buffer layer (BUF1) disposed between the first lower metal (LM1), the second lower metal (LM2), and the overlapping pattern (OP).

[0227] In the display device 100 according to an embodiment of the present disclosure, the first lower metal (LM1) may be disposed below the first active layer (ACT1) of the first driving transistor (DRT1), the second lower metal (LM2) may be disposed below the first active layer (ACT1) of the second driving transistor (DRT2), and the overlapping pattern (OP) may be disposed below the first lower metal (LM1) and the second lower metal (LM2).

[0228] If it is determined during the process that the first sub-pixel (SP1) and the second sub-pixel (SP2) are normal sub-pixels, the repair process is not performed during the process. In this case, in the first state of the display panel 110, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0229] In this first state, the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) may be spaced apart, and the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) may be spaced apart.

[0230] In the first state, the overlapping pattern (OP) may be electrically connected to a common power supply line, which may include, for example, one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a ground voltage line (BVL).

[0231] If the overlap pattern (OP) is in a floating state where it is not electrically connected to the common power line in the first state, foreign matter may be induced around the overlap pattern (OP), which may cause a defect in the repair structure. Therefore, by electrically connecting the overlap pattern (OP) to the adjacent common power line in the first state, defects in the repair structure can be prevented, and repair performance and the possibility of successful repair can be improved.

[0232] If it is determined during the process that the first sub-pixel SP1 is a normal sub-pixel and the second sub-pixel SP is a defective sub-pixel, a repair process for normalizing the second sub-pixel SP2 (i.e., a repair process for causing the second light-emitting element ED2 to emit light) may be performed during the process. In this case, in the second state of the display panel 110, a first current I1 may be supplied from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2.

[0233] In this second state, the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) may be connected, and the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) may be connected.

[0234] In the second state, the overlapping pattern (OP) may be electrically disconnected from the common power supply line, which may include one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a ground voltage line (BVL).

[0235] A display device 100 according to an embodiment of the present disclosure may include a first driving transistor (DRT1) including a first active layer (ACT1), a first source electrode (S1), a first drain electrode (D1), and a first gate electrode (G1), a first pixel electrode (PE1) electrically connected to the first source electrode (S1), a second driving transistor (DRT2) including a second active layer (ACT2), a second source electrode (S2), a second drain electrode (D2), and a second gate electrode (G2), and a second pixel electrode (PE2) electrically connected to the second source electrode (S2).

[0236] A display device 100 according to an embodiment of the present disclosure may include a first lower metal (LM1) electrically connected to a first source electrode (S1) and overlapping a first active layer (ACT1), a second lower metal (LM2) electrically connected to a second source electrode (S2) and overlapping a second active layer (ACT2), a first buffer layer (BUF1) disposed on the first lower metal (LM1) and the second lower metal (LM2), an overlap pattern (OP) disposed on the first buffer layer (BUF1) and including a first portion (PART1) overlapping a portion of the first lower metal (LM1), a second portion (PART2) overlapping a portion of the second lower metal (LM2), and a third portion (PART3) between the first portion (PART1) and the second portion (PART2), and a second buffer layer (BUF2) disposed on the overlap pattern (OP) and disposed below the first active layer (ACT1) and the second active layer (ACT2).

[0237] The distance between the first source electrode (S1) and the second source electrode (S2) is closer than the distance between the first light-emitting area (EA1) formed by the first pixel electrode (PE1) and the second light-emitting area (EA2) formed by the second pixel electrode (PE2).

[0238] The display device 100 according to the embodiment of the present disclosure may further include a gate insulating layer (GI) disposed on the first active layer (ACT1) and the second active layer (ACT2).

[0239] The first source electrode (S1) is disposed on the gate insulating layer (GI) and can be connected to the first lower metal (LM1) through the gate insulating layer (GI), the second buffer layer (BUF2), and a hole (GI Hole) in the first buffer layer (BUF1).

[0240] The second source electrode (S2) is disposed on the gate insulating layer (GI) and can be connected to the second lower metal (LM2) through the gate insulating layer (GI), the second buffer layer (BUF2), and the hole (GI Hole) of the first buffer layer (BUF1).

[0241] The display device 100 according to an embodiment of the present disclosure may further include a passivation layer (PAS) disposed on the first source electrode (S1), the first gate electrode (G1), the second source electrode (S2), and the second gate electrode (G2), and an overcoat layer (OC) disposed on the passivation layer (PAS).

[0242] The first pixel electrode (PE1) is disposed on the overcoat layer (OC) and can be connected to the first source electrode (S1) through a hole (OC hole) in the overcoat layer (OC) and a hole (PAS hole) in the passivation layer (PAS). The second pixel electrode (PE2) is disposed on the overcoat layer (OC) and can be connected to the second source electrode (S2) through a hole (OC hole) in the overcoat layer (OC) and a hole (PAS hole) in the passivation layer (PAS).

[0243] The first source electrode (S1) and the second source electrode (S2) may equally contain the gate electrode material contained in the first gate electrode (G1) and the second gate electrode (G2), and may be disposed in the same layer as the first gate electrode (G1) and the second gate electrode (G2).

[0244] A first gate electrode (G1) may be disposed on the first active layer (ACT1), and a second gate electrode (G2) may be disposed on the first active layer (ACT1).

[0245] Referring to Figures 15 to 18, the display device 100 according to an embodiment of the present disclosure may further include a first storage capacitor (Cst1) formed between the first source electrode (S1) and the first gate electrode (G1), and a second storage capacitor (Cst2) formed between the second source electrode (S2) and the second gate electrode (G2).

[0246] The first storage capacitor Cst1 may include a first upper capacitor Cu1 and a first lower capacitor Cd1.

[0247] The first upper capacitor Cu1 may include a first capacitor electrode corresponding to the first source electrode S1 and a second capacitor electrode AP_SCT1 including the same material (active layer pattern) as the first active layer ACT1.

[0248] The first lower capacitor Cd1 may include a third capacitor electrode PLT including the same material as the overlapping pattern OP and a fourth capacitor electrode corresponding to the first lower metal LM1.

[0249] The first capacitor electrode and the fourth capacitor electrode may be at the same potential as the first source electrode (S1), and the second capacitor electrode and the third capacitor electrode may be at the same potential as the first gate electrode (G1).

[0250] Therefore, the first upper capacitor Cu1 and the first lower capacitor Cd1 may be connected in parallel, thereby increasing the capacitance of the first storage capacitor Cst1.

[0251] The second storage capacitor Cst2 may include a second upper capacitor Cu2 and a second lower capacitor Cd2.

[0252] The second upper capacitor Cu2 may include a fifth capacitor electrode corresponding to the second source electrode S2 and a sixth capacitor electrode AP_SCT2 including the same material (active layer pattern) as the second active layer ACT2.

[0253] The second lower capacitor Cd2 may include a seventh capacitor electrode PLT including the same material as the overlapping pattern OP and an eighth capacitor electrode corresponding to the second lower metal LM2.

[0254] The fifth and eighth capacitor electrodes may be at the same potential as the second source electrode (S2), and the sixth and seventh capacitor electrodes may be at the same potential as the second gate electrode (G2).

[0255] Therefore, the second upper capacitor Cu2 and the second lower capacitor Cd2 may be connected in parallel, thereby increasing the capacitance of the second storage capacitor Cst2.

[0256] If it is determined during the process that the first sub-pixel (SP1) and the second sub-pixel (SP2) are normal sub-pixels, the repair process is not performed during the process. In this case, in the first state of the display panel 110, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0257] In this first state, as shown in Figures 17 and 18, the first part (PART1) of the overlap pattern (OP) and the first lower metal (LM1) may be spaced apart, and the second part (PART2) of the overlap pattern (OP) and the second lower metal (LM2) may be spaced apart.

[0258] Also, in the first state, the overlapping pattern (OP) may be electrically connected to a common power supply line, as shown in Figure 15. For example, the common power supply line may include one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a ground voltage line (BVL).

[0259] As shown in FIG. 15, for example, in the first state, the driving voltage line (DVL) may be connected to at least one of both ends of the overlapping pattern (OP) as a common power supply line for transmitting the driving voltage (EVDD) to the first drain electrode (D1) and the second drain electrode (D2).

[0260] The repair structure for the third subpixel circuit (SPC3) and the fourth subpixel circuit (SPC4) may include a third lower metal (LM3) connected to a source electrode of the third drive transistor (DRT3) in the third subpixel circuit (SPC3), a fourth lower metal (LM4) connected to a source electrode of the fourth drive transistor (DRT4) in the fourth subpixel circuit (SPC4), and an overlapping pattern (OP) overlapping at least a portion of the third lower metal (LM3) and overlapping at least a portion of the fourth lower metal (LM4). Here, the overlapping pattern (OP) may include a first portion (PART1) overlapping at least a portion of the third lower metal (LM3), a second portion (PART2) overlapping at least a portion of the fourth lower metal (LM4), and a third portion (PART3) between the first portion (PART1) and the second portion (PART2).

[0261] In addition, the third subpixel (SP3) and the fourth subpixel (SP4) are confirmed to be normal subpixels, and in a first state in which the third subpixel (SP3) and the fourth subpixel (SP4) are not repaired, as shown in FIG. 15, at least one of both ends of the overlap pattern (OP) can be connected to the reference voltage line (RVL), which is the closest common power line.

[0262] If it is determined during the process that the first sub-pixel SP1 is a normal sub-pixel and the second sub-pixel SP is a defective sub-pixel, a repair process for normalizing the second sub-pixel SP2 (i.e., a repair process for causing the second light-emitting element ED2 to emit light) may be performed during the process. In this case, in the second state of the display panel 110, a first current I1 may be supplied from the first driving transistor DRT1 to the first pixel electrode PE1 and the second pixel electrode PE2.

[0263] 11 and 18, in this second state, the first portion (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) are connected, and the second portion (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) are connected. As a result, a first welding pattern (WPTN1) is formed between the first portion (PART1) of the overlapping pattern (OP) and the first lower metal (LM1), and a second welding pattern (WPTN2) is formed between the second portion (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0264] 19, in the second state, the overlapping pattern (OP) may be electrically disconnected from the common power supply line. For example, the common power supply line may include one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a ground voltage line (BVL).

[0265] For example, the overlay pattern (OP) can be cut during the repair process while being connected to the driving voltage line (DVL) (first cutting).

[0266] As shown in FIG. 19, in the second state, a driving voltage line (DVL) is further included for transmitting a driving voltage (EVDD) to the first drain electrode (D1) and the second drain electrode (D2), and both ends of the overlapping pattern (OP) are electrically disconnected from the driving voltage line (DVL).

[0267] Meanwhile, in the second state, in which the fourth subpixel (SP4) among the third subpixel (SP3) and the fourth subpixel (SP4) is identified as a defective subpixel and a repair process is performed to normalize the fourth subpixel (SP4), the connection between at least one of both ends of the overlap pattern (OP) and the reference voltage line (RVL) may be cut off by a cutting process.

[0268] Also, as shown in FIG. 19, in the second state, in one example, the connection point between the first drive transistor (DRT2) and the drive voltage line (DLV) is cut off (2nd Cutting) to disable the second drive transistor (DRT2).

[0269] As mentioned above, the repair structure described with reference to Figures 15 to 19 requires two welding processes (i.e., welding processes at two welding points (WP1, WP2)) and two cutting processes (1st cutting, 2nd cutting).

[0270] 20 is an enlarged plan view of a portion 1700 of FIG. 15, and FIG. 21 is a cross-sectional view of first and second subpixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. The cross-sectional view of FIG. 21 includes a portion cut along line CC' of FIG. 20.

[0271] The plan view of FIG. 20 and the plan view of FIG. 16 are plan views showing the same region 1700 of FIG. 15 in more detail by enlarging it. Therefore, the plan view of FIG. 20 is almost identical to the plan view of FIG. 16. Furthermore, the cross-sectional view of FIG. 21 and the cross-sectional view of FIG. 18 are cross-sectional views of the same region. Therefore, the cross-sectional views of FIG. 21 and FIG. 18 are also almost identical. However, there are some differences between FIG. 20 and FIG. 21 and FIG. 16 and FIG. 18. Therefore, the following description will omit the same content and focus on the differences.

[0272] The position of the passivation layer (PAS) in Figures 20 and 21 is different from the position of the passivation layer (PAS hole) in Figures 16 and 18, and the position of the gate insulating layer (GI hole) in Figures 20 and 21 is different from the position of the gate insulating layer (GI hole) in Figures 16 and 18.

[0273] This difference is due to the fact that the first source electrode S1 and the second source electrode S2 in FIGS. 16 and 18 do not exist in FIGS.

[0274] In Figures 16 and 18, the first pixel electrode (PE1) and the first lower metal (LM1) are not directly connected but are electrically connected through the first source electrode (S1), and the second pixel electrode (PE2) and the second lower metal (LM2) are not directly connected but are electrically connected through the second source electrode (S2).

[0275] In contrast, in FIGS. 20 and 21, the first pixel electrode (PE1) may be directly connected to the first lower metal (LM1), and the second pixel electrode (PE2) may be directly connected to the second lower metal (LM2).

[0276] The first pixel electrode (PE1) may be directly connected to the first lower metal (LM1) through a hole that penetrates the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0277] The second pixel electrode (PE2) may be directly connected to the second lower metal (LM2) through a hole that penetrates all of the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0278] Referring to Figures 20 and 21, the hole that penetrates the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1) includes a hole in the passivation layer (PAS).

[0279] In Figures 20 and 21, the active layer pattern (AP_SENT1) for forming the active layer of the first sensing transistor (SENT1) serves as the first source electrode (S1), and the first pixel electrode (PE1) can also serve as the first source electrode (S1).

[0280] In Figures 20 and 21, the active layer pattern (AP_SENT2) for forming the active layer of the second sensing transistor (SENT2) serves as the second source electrode (S2), and the second pixel electrode (PE2) can also serve as the second source electrode (S2).

[0281] 20 and 21. The storage capacitor structure in FIGS. 20 and 21 may be changed to the point where the first source electrode S1 and the second source electrode S2 in FIGS. 16 and 18 do not exist in FIGS. 20 and 21.

[0282] Referring to FIG. 21, the first storage capacitor Cst1 may include a first upper capacitor Cu1 and a first lower capacitor Cd1.

[0283] The first upper capacitor (Cu1) may include a first capacitor electrode (AP_SCT1) including the same material (active layer pattern) as the first active layer (ACT1) and a second capacitor electrode (PLT) including the same material as the overlapping pattern (OP). Here, the first capacitor electrode (AP_SCT1) including the same material (active layer pattern) as the first active layer (ACT1) is electrically connected to the first pixel electrode (PE1). Therefore, the first capacitor electrode (AP_SCT1) can also be seen as the first pixel electrode (PE1).

[0284] The first lower capacitor Cd1 may include a second capacitor electrode PLT including the same material as the overlapping pattern OP and a third capacitor electrode corresponding to the first lower metal LM1.

[0285] The first and third capacitor electrodes may be at the same potential as the first source electrode (S1), and the second capacitor electrode may be at the same potential as the first gate electrode (G1). Thus, the first upper capacitor (Cu1) and the first lower capacitor (Cd1) may be connected in parallel. This may increase the capacitance of the first storage capacitor (Cst1).

[0286] Referring to FIG. 21, the second storage capacitor Cst2 may include a second upper capacitor Cu2 and a second lower capacitor Cd2.

[0287] The second upper capacitor (Cu2) may include a fourth capacitor electrode (AP_SCT2) including the same material (active layer pattern) as the second active layer (ACT2) and a fifth capacitor electrode (PLT) including the same material as the overlapping pattern (OP). Here, the fourth capacitor electrode (AP_SCT2) including the same material (active layer pattern) as the second active layer (ACT2) is electrically connected to the second pixel electrode (PE2). Therefore, the fourth capacitor electrode (AP_SCT2) may be considered as the second pixel electrode (PE2).

[0288] The second lower capacitor Cd2 may include a fifth capacitor electrode PLT including the same material as the overlapping pattern OP and a sixth capacitor electrode corresponding to the second lower metal LM2.

[0289] The fourth and sixth capacitor electrodes may be at the same potential as the second source electrode (S2), and the fifth capacitor electrode may be at the same potential as the second gate electrode (G2). Thus, the second upper capacitor (Cu2) and the second lower capacitor (Cd2) may be connected in parallel. This may increase the capacitance of the first storage capacitor (Cst1).

[0290] A repair structure that can reduce two welding processes to one welding process and two cutting processes to one cutting process will be described below with reference to FIGS. 22 to 26. FIG.

[0291] Fig. 22 is a plan view of a partial region 1600 of Fig. 14, Fig. 23 is an enlarged plan view of a partial region 2200 of Fig. 22, Fig. 24 is a cross-sectional view taken along line B-B' of Fig. 23, and Fig. 25 is a cross-sectional view of first and second sub-pixels (SP1, SP2) adjacent in the column direction of display device 100 according to an embodiment of the present disclosure. Fig. 26 is a plan view of display panel 110 that has been repaired, as a plan view of partial region 1600 of Fig. 14.

[0292] 22 to 26 may correspond to Figures 15 to 19, respectively, with only slight differences in the repair structure. Therefore, in the description with reference to Figures 22 to 26, the description of the same content as Figures 15 to 19 will be omitted and other content will be mainly described.

[0293] Referring to Figures 22 to 26, before the repair process, the second part (PART2) of the overlap pattern (OP) is not electrically connected to the second lower metal (LM2), but the first part (PART1) of the overlap pattern (OP) can be electrically connected to the first lower metal (LM1) through the connection pattern (CPTN_OP).

[0294] Alternatively, before the repair process, the first part (PART1) of the overlap pattern (OP) is not electrically connected to the first lower metal (LM1), but the second part (PART2) of the overlap pattern (OP) can be electrically connected to the second lower metal (LM2) through the connection pattern (CPTN_OP).

[0295] That is, the repair structure according to an embodiment of the present disclosure may further include a connection pattern (CPTN_OP) connecting a first part (PART1) of the overlapping pattern (OP) to a first lower metal (LM1), or connecting a second part (PART2) of the overlapping pattern (OP) to a second lower metal (LM2).

[0296] The connection pattern (CPTN_OP) may include the same material as the first source electrode (S1) and the second source electrode (S2), and may be disposed in the same layer as the first source electrode (S1) and the second source electrode (S2).

[0297] Referring to FIGS. 22 to 26, before the repair process, the overlap pattern (OP) may be disconnected from adjacent common power lines (e.g., drive voltage line (DVL), reference voltage line (RVL)).

[0298] Referring to Figures 22 to 26, it is confirmed that a defect has occurred in the second subpixel circuit (SPC2) of the first subpixel circuit (SPC1) and the second subpixel circuit (SPC2), and in order to perform a repair process to normalize the second subpixel (SP2), only one welding process and one cutting process need to be performed.

[0299] The single welding process may be a welding process for electrically connecting one end of the overlapping pattern (OP) that is not connected to the connection pattern (CPTN_OP) and the corresponding underlying metal, that is, through the single welding process, a welding pattern (WPTN) may be formed between the one end of the overlapping pattern (OP) that is not connected to the connection pattern (CPTN_OP) and the corresponding underlying metal.

[0300] For example, the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be electrically connected through a single welding process, i.e., the welding pattern (WPTN) can be formed between the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) through a single welding process.

[0301] The first cutting process may be a second cutting process for disabling the second subpixel circuit (SPC2). For example, as shown in FIG. 26, the first cutting process may cut the connection between the second drive transistor (DRT2) in the second subpixel circuit (SPC2) and the drive voltage line (DVL).

[0302] FIG. 27 shows the current supply status after repair processing when a defect occurs in the second subpixel (SP2) among the first to fourth subpixels (SP) arranged in the column direction in a display panel 110 according to an embodiment of the present disclosure, and FIG. 28 shows the current supply status after repair processing when a defect occurs in the first subpixel (SP1) among the first to fourth subpixels (SP) arranged in the column direction in a display panel 110 according to an embodiment of the present disclosure.

[0303] 27 and 28, an example will be given in which the first to fourth sub-pixels SP1 to SP4 are arranged in the column direction.

[0304] 27 and 28, the first subpixel (SP1) may include a first pixel electrode (PE1) of a first light-emitting element (ED1) and a first source electrode (S1) of a first drive transistor (DRT1) in a first subpixel circuit (SPC1). The second subpixel (SP2) may include a second pixel electrode (PE2) of a second light-emitting element (ED2) and a second source electrode (S2) of a second drive transistor (DRT2) in a second subpixel circuit (SPC2). The third subpixel (SP3) may include a third pixel electrode (PE3) of a third light-emitting element (ED3) and a third source electrode (S3) of a third drive transistor (DRT3) in a third subpixel circuit (SPC3). The fourth subpixel (SP4) may include a fourth pixel electrode (PE4) of a fourth light-emitting element (ED4) and a fourth source electrode (S4) of a fourth drive transistor (DRT4) in a fourth subpixel circuit (SPC4).

[0305] The first to fourth pixel electrodes (PE1 to PE4) and the first to fourth source electrodes (S1 to S4) may be electrically connected to each other through contact holes (CNT) in an insulating layer (e.g., an overcoat layer (OC), a passivation layer (PAS)).

[0306] Referring to Figures 27 and 28, the first subpixel (SP1) and the second subpixel (SP2) have a vertically symmetrical structure and may be a set for repair processing, and the third subpixel (SP3) and the fourth subpixel (SP4) have a vertically symmetrical structure and may be a set for repair processing.

[0307] 27 and 28, when the first subpixel (SP1) and the second subpixel (SP2) have a vertically symmetrical structure, the first subpixel circuit (SPC1) and the second subpixel circuit (SPC2) may be disposed adjacent to each other. When the third subpixel (SP3) and the fourth subpixel (SP4) have a vertically symmetrical structure, the third subpixel circuit (SPC3) and the fourth subpixel circuit (SPC4) may be disposed adjacent to each other. With such a vertically symmetrical structure, the second light-emitting element (ED2) and the third light-emitting element (ED3) may be disposed adjacent to each other.

[0308] Referring to Figures 27 and 28, the repair structure for the first and second subpixels (SP1, SP2) may include a first lower metal connected to the first source electrode (S1), a second lower metal connected to the second source electrode (S2), and an overlap pattern (OP) overlapping at least a portion of the first lower metal and overlapping at least a portion of the second lower metal.

[0309] Referring to Figures 27 and 28, the repair structure for the third and fourth subpixels (SP3, SP4) may include a third lower metal connected to the third source electrode (S3), a fourth lower metal connected to the fourth source electrode (S4), and an overlap pattern (OP) overlapping at least a portion of the third lower metal and overlapping at least a portion of the fourth lower metal.

[0310] 27, when a defect occurs in the second subpixel circuit SPC2, a repair process for normalizing the second subpixel SP2 may be performed to connect the first lower metal connected to the first source electrode S1 and the second lower metal connected to the second source electrode S2 to the overlapping pattern OP. As a result, a first welding pattern WPTN1 may be formed between the overlapping pattern OP and the first lower metal, and a second welding pattern WPTN2 may be formed between the overlapping pattern OP and the second lower metal.

[0311] Then, the second subpixel circuit (SPC2) can be disabled through a repair process to normalize the second subpixel (SP2).

[0312] 27, by performing a repair process to normalize the second sub-pixel SP2, the first current I1 output from the first source electrode S1 of the first driving transistor DRT1 in the normal first sub-pixel circuit SPC1 can be supplied to the second pixel electrode PE2 as well as the first pixel electrode PE1, thereby allowing the second light-emitting element ED2 to emit light normally.

[0313] 28, when a defect occurs in the first subpixel circuit SPC1, a repair process for normalizing the first subpixel SP1 may be performed to connect the first lower metal connected to the first source electrode S1 and the second lower metal connected to the second source electrode S2 to the overlapping pattern OP. As a result, a first welding pattern WPTN1 may be formed between the overlapping pattern OP and the first lower metal, and a second welding pattern WPTN2 may be formed between the overlapping pattern OP and the second lower metal.

[0314] Then, the first subpixel circuit (SPC1) can be disabled through a repair process to normalize the first subpixel (SP1).

[0315] 28, by performing a repair process to normalize the second sub-pixel SP2, the second current I2 output from the second source electrode S2 of the second driving transistor DRT2 in the normal second sub-pixel circuit SPC2 can be supplied to the first pixel electrode PE1 as well as the second pixel electrode PE2, thereby allowing the first light emitting element ED1 to emit light normally.

[0316] The above-described embodiment of the present disclosure can be summarized as follows.

[0317] A display device according to an embodiment of the present disclosure may include a first lower metal directly connected to a first pixel electrode or a first source electrode in a first subpixel and overlapping a first active layer, a second lower metal directly connected to a second pixel electrode or a second source electrode in a second subpixel and overlapping a second active layer, and an overlap pattern having one side overlapping with at least a portion of the first lower metal and another side overlapping with at least a portion of the second lower metal.

[0318] A display device according to an embodiment of the present disclosure includes a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; a first pixel electrode directly connected to a portion of the first active layer or electrically connected to a portion of the first active layer through an additional first source electrode; a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; a second pixel electrode directly connected to a portion of the second active layer or electrically connected to a portion of the second active layer through an additional second source electrode; and a second pixel electrode directly connected to the first pixel electrode or directly connected to the first source electrode. the first lower metal is directly connected to the second pixel electrode or directly connected to the second source electrode and overlaps with the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; an overlapping pattern disposed on the first buffer layer and including a first portion overlapping with at least a portion of the first lower metal, a second portion overlapping with at least a portion of the second lower metal, and a third portion between the first and second portions; and a second buffer layer disposed on the overlapping pattern and below the first and second active layers.

[0319] The distance between the first source electrode and the second source electrode is closer than the distance between the first light-emitting region formed by the first pixel electrode and the second light-emitting region formed by the second pixel electrode.

[0320] The display device according to the embodiments of the present disclosure may further include a gate insulating layer disposed on the first active layer and the second active layer.

[0321] The first source electrode may be disposed on the gate insulating layer and connected to the first lower metal through the gate insulating layer, the second buffer layer, and a hole in the first buffer layer.

[0322] The second source electrode may be disposed on the gate insulating layer and connected to the second lower metal through a hole in the gate insulating layer, the second buffer layer, and the first buffer layer.

[0323] The display device according to the embodiments of the present disclosure may further include a passivation layer disposed on the first source electrode, the first gate electrode, the second source electrode, and the second gate electrode, and an overcoat layer disposed on the passivation layer.

[0324] The first pixel electrode may be disposed on the overcoat layer and connected to the first source electrode through a hole in the overcoat layer and the passivation layer, and the second pixel electrode may be disposed on the overcoat layer and connected to the second source electrode through a hole in the overcoat layer and the passivation layer.

[0325] A first gate electrode may be disposed on the first active layer and a second gate electrode may be disposed on the second active layer.

[0326] The first and second source electrodes may equally include the gate electrode material included in the first and second gate electrodes.

[0327] As an example of a storage capacitor structure, a display device according to an embodiment of the present disclosure may further include a first storage capacitor formed between the first source electrode and the first gate electrode, and a second storage capacitor formed between the second source electrode and the second gate electrode.

[0328] The first storage capacitor may include a first upper capacitor and a first lower capacitor, which may be connected in parallel to form the first storage capacitor.

[0329] The second storage capacitor may include a second upper capacitor and a second lower capacitor, which may be connected in parallel to form the second storage capacitor.

[0330] The first upper capacitor may include a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode including the same material as the first active layer.

[0331] The first lower capacitor may include a third capacitor electrode including the same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal.

[0332] The second upper capacitor may include a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode including the same material as the second active layer.

[0333] The second lower capacitor may include a seventh capacitor electrode including the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal.

[0334] As another example of a storage capacitor structure, a display device according to an embodiment of the present disclosure may include a first storage capacitor formed between a first pixel electrode and a first gate electrode, and a second storage capacitor formed between a second pixel electrode and a second gate electrode.

[0335] The first storage capacitor may include a first upper capacitor and a first lower capacitor, and the second storage capacitor may include a second upper capacitor and a second lower capacitor.

[0336] The first upper capacitor and the first lower capacitor may be connected in parallel to form a first storage capacitor.

[0337] The first upper capacitor may include a first capacitor electrode including the same material as the first active layer and a second capacitor electrode including the same material as the overlapping pattern.

[0338] The first lower capacitor may include a second capacitor electrode and the third capacitor electrode corresponding to the first lower metal.

[0339] The second upper capacitor and the second lower capacitor may be connected in parallel to form a second storage capacitor.

[0340] The second upper capacitor may include a fourth capacitor electrode including the same material as the second active layer and a fifth capacitor electrode including the same material as the overlapping pattern.

[0341] The second lower capacitor may include a fifth capacitor electrode and the sixth capacitor electrode corresponding to the first lower metal.

[0342] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode (when the first subpixel and the second subpixel are all confirmed to be normal subpixels and are not repaired), the first portion and the first lower metal may be separated, or the second portion and the second lower metal may be separated.

[0343] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, at least one of the first lower metal and the second lower metal may be electrically isolated from the overlapping pattern.

[0344] The display device according to the embodiment of the present disclosure may further include a connection pattern connecting the first portion and the first lower metal or connecting the second portion and the second lower metal, wherein the connection pattern may include the same material as the first source electrode and the second source electrode.

[0345] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0346] A display device according to an embodiment of the present disclosure may further include a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode.

[0347] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, at least one of both ends of the overlapping pattern may be connected to a driving voltage line.

[0348] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode (when the first subpixel is confirmed to be a normal subpixel and the second subpixel is confirmed to be a defective subpixel among the first and second subpixels and repaired), both ends of the overlapping pattern can be electrically disconnected from the driving voltage line.

[0349] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the driving voltage line and the first drain electrode may be electrically connected, and the driving voltage line and the second drain electrode may be electrically connected.

[0350] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the driving voltage line and the first drain electrode may be electrically connected, and the driving voltage line and the second drain electrode may be electrically disconnected.

[0351] A display device according to an embodiment of the present disclosure may include a data line for transmitting a data voltage, a first scan transistor for controlling a connection between the data line and a first gate electrode, and a second scan transistor for controlling a connection between the data line and a second gate electrode.

[0352] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the data line and the first scan transistor can be connected, and the data line and the second scan transistor can be connected.

[0353] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the data line and the first scan transistor may be connected, and the data line and the second scan transistor may be disconnected.

[0354] A display device according to an embodiment of the present disclosure may include a reference voltage line for transmitting a reference voltage, a first sensing transistor for controlling a connection between the reference voltage line and a first source electrode, and a second sensing transistor for controlling a connection between the reference voltage line and a second source electrode.

[0355] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the reference voltage line and the first sensing transistor may be connected, and the reference voltage line and the second sensing transistor may be connected.

[0356] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the reference voltage line and the first sensing transistor may be connected and the reference voltage line and the second sensing transistor may be disconnected.

[0357] A display device according to an embodiment of the present disclosure may include a first subpixel including a first driving transistor and a first light-emitting element, a second subpixel including a second driving transistor and a second light-emitting element, a first lower metal connected to a first source electrode of the first driving transistor, a second lower metal connected to a second source electrode of the second driving transistor, an overlapping pattern including a first portion overlapping with a portion of the first lower metal, a second portion overlapping with a portion of the second lower metal, and a third portion between the first and second portions, and a first buffer layer disposed between the first and second lower metals and the overlapping pattern.

[0358] The first lower metal may be disposed under the first active layer of the first driving transistor, the second lower metal may be disposed under the first active layer of the second driving transistor, and the overlapping pattern may be disposed under the first lower metal and the second lower metal.

[0359] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the first portion and the first lower metal may be spaced apart, or the second portion and the second lower metal may be spaced apart.

[0360] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0361] The distance between the first source electrode and the second source electrode is closer than the distance between the first light-emitting region of the first light-emitting element and the second light-emitting region of the second light-emitting element.

[0362] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the overlapping pattern may be electrically connected to a common power line.

[0363] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the overlapping pattern can be electrically disconnected from the common power line.

[0364] A display panel according to an embodiment of the present disclosure may include a first subpixel including a first subpixel circuit and a first light-emitting element, a second subpixel including a second subpixel circuit and a second light-emitting element, a first lower metal connected to the first subpixel circuit, a second lower metal connected to the second subpixel circuit, an overlapping pattern including a first portion overlapping with a portion of the first lower metal, a second portion overlapping with a portion of the second lower metal, and a third portion between the first and second portions, and a first buffer layer disposed between the first and second lower metals and the overlapping pattern.

[0365] When a first current is supplied from the first subpixel circuit to the first light-emitting element and a second current is supplied from the second subpixel circuit to the second light-emitting element, the first portion and the first lower metal may be spaced apart, or the second portion and the second lower metal may be spaced apart.

[0366] When a first current is supplied from the first subpixel circuit to the first light emitting element and the second light emitting element, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0367] The distance between the first sub-pixel circuit and the second sub-pixel circuit is closer than the distance between the first light-emitting region of the first light-emitting element and the second light-emitting region of the second light-emitting element.

[0368] The display panel according to an embodiment of the present disclosure may further include a common power line adjacent to the overlapping pattern. For example, the common power line may include at least one of a driving voltage line, a reference voltage line, and a ground voltage line. For example, the common power line may be a positive voltage line whose voltage level does not change with time.

[0369] When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and a second current is supplied from the second sub-pixel circuit to the second light-emitting element, the overlapping pattern may be electrically connected to a common power line.

[0370] When a first current is supplied from the first sub-pixel circuit to the first light emitting element and the second light emitting element, the overlapping pattern may be electrically disconnected from the common power line.

[0371] A display panel according to an embodiment of the present disclosure may further include a substrate, a first active layer disposed within the first subpixel circuit, and a second active layer disposed within the second subpixel circuit.

[0372] The first lower metal may be disposed under the first active layer and overlap the first active layer, and the second lower metal may be disposed under the second active layer and overlap the second active layer.

[0373] The overlay pattern may be disposed in the metal layer between the first and second lower metal layers and the substrate.

[0374] According to the above-described embodiments of the present disclosure, it is possible to provide a display device and a display panel having a repair structure that can normalize a subpixel when a defect occurs in the subpixel.

[0375] According to the embodiments of the present disclosure, it is possible to provide a display device and a display panel having a repair structure that does not cause a decrease in aperture ratio.

[0376] According to the embodiments of the present disclosure, a display device and a display panel having a repair structure that does not occupy much space can be provided.

[0377] According to the embodiments of the present disclosure, it is possible to provide a display device having a repair structure suitable for a high-resolution configuration.

[0378] According to the embodiments of the present disclosure, it is possible to provide a display device and a display panel having a repair structure with high repair performance or high repair success rate, thereby reducing manufacturing costs and optimizing the manufacturing process.

[0379] The above description is merely an illustrative example of the technical idea of ​​the present disclosure, and various modifications and variations may be made by a person skilled in the art without departing from the essential characteristics of the present disclosure. Furthermore, the examples disclosed in the present disclosure are for the purpose of explanation, not for the purpose of limiting the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by these examples. [Explanation of symbols]

[0380] SP1 1st subpixel PE1 First pixel electrode S1 First source electrode SP2 Second subpixel PE2 Second pixel electrode S2 Second source electrode

Claims

1. A first subpixel including a first subpixel circuit and a first light-emitting element; a second subpixel including a second subpixel circuit and a second light-emitting element; a first lower metal and a second lower metal; a first buffer layer and a second buffer layer; A superimposed pattern; A display device comprising: the first subpixel circuit includes a first drive transistor including a first active layer, a first drain electrode, and a first gate electrode; the first light emitting element includes a first pixel electrode that is directly connected to a portion of the first active layer or that is electrically connected to a portion of the first active layer through an additional first source electrode; the second subpixel circuit includes a second drive transistor including a second active layer, a second drain electrode, and a second gate electrode; the second light emitting element includes a second pixel electrode that is directly connected to a portion of the second active layer or that is electrically connected to a portion of the second active layer through an additional second source electrode; the first lower metal is directly connected to the first pixel electrode or directly connected to the first source electrode, and overlaps with the first active layer; the second lower metal is directly connected to the second pixel electrode or directly connected to the second source electrode, and overlaps with the second active layer; the first buffer layer is disposed on the first lower metal and the second lower metal; the overlapping pattern is disposed on the first buffer layer and includes a first portion overlapping with at least a portion of the first lower metal, a second portion overlapping with at least a portion of the second lower metal, and a third portion between the first portion and the second portion; the second buffer layer is disposed on the overlay pattern and below the first active layer and the second active layer; Display device.

2. 2. The display device of claim 1, wherein a distance between the first source electrode and the second source electrode is shorter than a distance between a first light-emitting region formed by the first pixel electrode and a second light-emitting region formed by the second pixel electrode.

3. further comprising a gate insulating layer disposed on the first active layer and the second active layer; the first source electrode is disposed on the gate insulating layer and is connected to the first lower metal through the gate insulating layer, the second buffer layer, and a hole in the first buffer layer; The second source electrode is disposed on the gate insulating layer and is connected to the second lower metal through a hole in the gate insulating layer, the second buffer layer, and the first buffer layer. The display device according to claim 1 .

4. a passivation layer disposed on the first source electrode, the first gate electrode, the second source electrode, and the second gate electrode; an overcoat layer disposed on the passivation layer; further comprising the first pixel electrode is disposed on the overcoat layer and connected to the first source electrode through a hole in the overcoat layer and the passivation layer; The second pixel electrode is disposed on the overcoat layer and is connected to the second source electrode through a hole in the overcoat layer and the passivation layer. The display device according to claim 1 .

5. the first gate electrode is disposed on the first active layer; the second gate electrode is disposed on the second active layer; The first and second source electrodes include the same gate electrode material as that included in the first and second gate electrodes. The display device according to claim 1 .

6. a first upper capacitor including a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode including the same material as the first active layer; a first lower capacitor including a third capacitor electrode made of the same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal; a second upper capacitor including a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode including the same material as the second active layer; a second lower capacitor including a seventh capacitor electrode made of the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal; Including, the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor; The second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor. The display device according to claim 1 .

7. a first upper capacitor including a first capacitor electrode made of the same material as the first active layer and a second capacitor electrode made of the same material as the overlapping pattern; a first lower capacitor including the second capacitor electrode and a third capacitor electrode corresponding to the first lower metal; a second upper capacitor including a fourth capacitor electrode including the same material as the second active layer and a fifth capacitor electrode including the same material as the overlapping pattern; a second lower capacitor including the fifth capacitor electrode and a sixth capacitor electrode corresponding to the first lower metal; further comprising the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor; The second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor. The display device according to claim 1 .

8. When the first subpixel and the second subpixel are normal, a first current is supplied from the first driving transistor to the first pixel electrode, and a second current is supplied from the second driving transistor to the second pixel electrode; the first portion and the first lower metal are spaced apart, or the second portion and the second lower metal are spaced apart, At least one of the first lower metal and the second lower metal is electrically isolated from the overlapping pattern. The display device according to claim 1 .

9. further comprising a connection pattern that connects the first portion and the first lower metal when the second portion is spaced apart from the second lower metal, and that connects the second portion and the second lower metal when the first portion is spaced apart from the first lower metal; The connection pattern includes the same material as the first source electrode and the second source electrode. The display device according to claim 8 .

10. When the first subpixel or the second subpixel is defective, a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode; the first portion and the first lower metal are connected; The second portion and the second lower metal are connected. The display device according to claim 1 .

11. a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode; When the first subpixel and the second subpixel are normal, a first current is supplied from the first driving transistor to the first pixel electrode, and a second current is supplied from the second driving transistor to the second pixel electrode; At least one of both ends of the overlapping pattern is connected to the driving voltage line. The display device according to claim 1 .

12. a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode; When the first subpixel or the second subpixel is defective, a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode; Both ends of the overlapping pattern are electrically disconnected from the driving voltage line. The display device according to claim 1 .

13. a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode; When the first subpixel and the second subpixel are normal, a first current is supplied from the first driving transistor to the first pixel electrode, and a second current is supplied from the second driving transistor to the second pixel electrode; the driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode are electrically connected; When the first subpixel or the second subpixel is defective, a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode; The driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode are not electrically connected. The display device according to claim 1 .

14. a data line for transmitting a data voltage; a first scan transistor that controls a connection between the data line and the first gate electrode; a second scan transistor that controls a connection between the data line and the second gate electrode; Including, When the first subpixel and the second subpixel are normal, a first current is supplied from the first driving transistor to the first pixel electrode, and a second current is supplied from the second driving transistor to the second pixel electrode; the data line and the first scan transistor are connected, and the data line and the second scan transistor are connected; When the first subpixel or the second subpixel is defective, a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode; The data line and the first scan transistor are connected, and the data line and the second scan transistor are not connected. The display device according to claim 1 .

15. a reference voltage line for transmitting a reference voltage; a first sensing transistor that controls a connection between the reference voltage line and the first source electrode; a second sensing transistor that controls a connection between the reference voltage line and the second source electrode; Including, When the first subpixel and the second subpixel are normal, a first current is supplied from the first driving transistor to the first pixel electrode, and a second current is supplied from the second driving transistor to the second pixel electrode; the reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor are connected; When the first subpixel or the second subpixel is defective, a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode; The reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor are not connected. The display device according to claim 1 .

16. A substrate, a first sub-pixel including a first sub-pixel circuit and a first light emitting element; a second subpixel including a second subpixel circuit and a second light emitting element; a first lower metal connected to the first subpixel circuit; a second lower metal connected to the second subpixel circuit; an overlapping pattern including a first portion overlapping a portion of the first lower metal, a second portion overlapping a portion of the second lower metal, and a third portion between the first portion and the second portion; a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern; a first active layer disposed within the first subpixel circuit; a second active layer disposed within the second subpixel circuit; and Including, the first lower metal is disposed under the first active layer and overlaps the first active layer; the second lower metal is disposed under the second active layer and overlaps the second active layer; The overlapping pattern is disposed in a metal layer between the first lower metal and the second lower metal and the substrate. Display panel.

17. A first subpixel including a first subpixel circuit and a first light-emitting element; a second subpixel including a second subpixel circuit and a second light emitting element; a first lower metal connected to the first subpixel circuit; a second lower metal connected to the second subpixel circuit; an overlapping pattern including a first portion overlapping a portion of the first lower metal, a second portion overlapping a portion of the second lower metal, and a third portion between the first portion and the second portion; a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern; Including, a distance between the first sub-pixel circuit and the second sub-pixel circuit is shorter than a distance between the first light-emitting region of the first light-emitting element and the second light-emitting region of the second light-emitting element; Display panel.

18. When the first subpixel and the second subpixel are normal, a first current is supplied from the first sub-pixel circuit to the first light-emitting element, and a second current is supplied from the second sub-pixel circuit to the second light-emitting element; the first portion and the first lower metal are spaced apart, or the second portion and the second lower metal are spaced apart, When the first subpixel or the second subpixel is defective, a first current is supplied from the first subpixel circuit to the first light-emitting element and the second light-emitting element; The first portion and the first lower metal are connected, and the second portion and the second lower metal are connected. The display panel according to claim 16.

19. A first subpixel including a first subpixel circuit and a first light-emitting element; a second subpixel including a second subpixel circuit and a second light emitting element; a first lower metal connected to the first subpixel circuit; a second lower metal connected to the second subpixel circuit; an overlapping pattern including a first portion overlapping a portion of the first lower metal, a second portion overlapping a portion of the second lower metal, and a third portion between the first portion and the second portion; a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern; a common power line adjacent to the overlapping pattern; Including, When the first subpixel and the second subpixel are normal, a first current is supplied from the first sub-pixel circuit to the first light-emitting element, and a second current is supplied from the second sub-pixel circuit to the second light-emitting element; the overlapping pattern is electrically connected to the common power line; When the first subpixel or the second subpixel is defective, a first current is supplied from the first subpixel circuit to the first light-emitting element and the second light-emitting element; the overlapping pattern is electrically disconnected from the common power supply line; Display panel.

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