Method, apparatus and device for monitoring clock networks in integrated circuits

Abstract

To provide a method, device, and apparatus for monitoring a clock network in an integrated circuit.SOLUTION: The method for monitoring a clock network in an integrated circuit includes the steps of monitoring the clock frequency state of a first clock node in the clock network in the integrated circuit, detecting the clock operation state of a second clock node in the clock network, and determining an operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to methods, devices and equipment for monitoring clock networks in integrated circuits. [Background technology]

[0002] In terminal devices such as in-vehicle terminals and mobile phone terminals, to improve the operating efficiency of integrated circuits such as chips, clocks in integrated circuits generally adopt a mesh structure, which can be called a clock network. The clock network can include multiple clock nodes and is used to provide clocks to each circuit module and each on-chip clock controller (OCC) in the integrated circuit. To ensure the functional safety of the integrated circuit, it is very important to monitor each clock node in the clock network. Related technologies generally achieve global monitoring of the clock network by monitoring the clock frequency of each clock node in the clock network, but such a global monitoring method requires the consumption of a large amount of on-chip resources. Summary of the Invention [Problem to be solved by the invention]

[0003] To solve the above-mentioned problems such as the high resource consumption of clock monitoring, the embodiments of the present disclosure provide a method, apparatus and device for monitoring a clock network in an integrated circuit, which effectively reduces the resource consumption of clock monitoring. [Means for solving the problem]

[0004] A first aspect of the present disclosure provides a method for monitoring a clock network in an integrated circuit, the method including the steps of monitoring a clock frequency state of a first clock node in a clock network in the integrated circuit, detecting a clock operating state of a second clock node in the clock network, and determining an operating state of the clock network based on the clock frequency state of the first clock node and the clock operating state of the second clock node.

[0005] A second aspect of the present disclosure provides a clock network monitoring device in an integrated circuit, the clock network monitoring device in the integrated circuit including: a clock frequency monitoring module for monitoring a clock frequency state of a first clock node in a clock network in the integrated circuit; a clock operation detection module for detecting a clock operation state of a second clock node in the clock network; and a processing module connected to the clock frequency monitoring module and the clock operation detection module, respectively, for determining the operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node.

[0006] A third aspect of the present disclosure provides a computer-readable storage medium having stored thereon a computer program for executing a method according to any of the above embodiments of the present disclosure.

[0007] A fourth aspect of the present disclosure provides an electronic device, the electronic device including a processor and a memory for storing instructions executable by the processor, the processor being adapted to read and execute the executable instructions from the memory to implement a method according to any of the above embodiments of the present disclosure, or the electronic device including an apparatus according to any of the above embodiments of the present disclosure. [Effects of the Invention]

[0008] The above-described embodiments of the present disclosure provide a method, apparatus, and device for monitoring a clock network in an integrated circuit. The method, apparatus, and device can monitor the clock frequency status of a first clock node in a clock network in an integrated circuit, detect the clock operating status of a second clock node in the clock network, and determine the operating status of the clock network based on the clock frequency status of the first clock node and the clock operating status of the second clock node. The method of the embodiments of the present disclosure can monitor the clock frequency status of only some clock nodes in the clock network (e.g., one or more first clock nodes) and detect the clock operating status of other clock nodes, where the clock operating status indicates whether the clock node flips normally. Compared with monitoring the clock frequency status, detecting the clock operating status can be implemented with fewer on-chip resources. Therefore, the method of the embodiments of the present disclosure can effectively reduce the resource consumption of clock monitoring while supporting global monitoring of clocks in a clock network, thereby helping to solve the problem of high resource consumption in global monitoring methods in related art. [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates an example of a scenario in which the method for monitoring a clock network in an integrated circuit provided in the present disclosure is used. [Figure 2] 1 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in an exemplary embodiment of the present disclosure. [Figure 3] 10 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in another exemplary embodiment of the present disclosure. [Figure 4] 10 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in yet another exemplary embodiment of the present disclosure. [Figure 5] 10 is a flowchart of detecting a clock running state provided in an exemplary embodiment of the present disclosure. [Figure 6] 1 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in an exemplary embodiment of the present disclosure; [Figure 7] FIG. 10 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in another exemplary embodiment of the present disclosure. [Figure 8] FIG. 10 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in yet another exemplary embodiment of the present disclosure. [Figure 9] 1 is a structural schematic diagram of an exemplary embodiment of a clock network monitoring device in an integrated circuit provided in an exemplary embodiment of the present disclosure; [Figure 10] 2 is a structural schematic diagram of an exemplary embodiment of a clock operation detection module 52 provided in an exemplary embodiment of the present disclosure. [Figure 11] 1 is a structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to explain the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. Obviously, it should be understood that the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0011] Unless otherwise specified, the relative arrangement of components and steps, formulas and numerical values ​​described in these embodiments do not limit the scope of the present disclosure.

[0012] Summary of the Disclosure In the process of realizing the present disclosure, the inventors discovered the following. In order to improve the operating efficiency of integrated circuits such as chips in terminal devices such as in-vehicle terminals and mobile phone terminals, the clock in the integrated circuit generally adopts a mesh structure, which can be called a clock network. The clock network can include multiple clock nodes and is used to provide clocks to each circuit module and each on-chip clock controller (OCC) in the integrated circuit. In order to ensure the functional safety of the integrated circuit, it is very important to monitor each clock node in the clock network. In related technologies, global monitoring of the clock network is generally achieved by monitoring the clock frequency of each clock node in the clock network, but such a global monitoring method requires the consumption of a large amount of on-chip resources.

[0013] Illustrative Overview FIG. 1 illustrates an example of a scenario in which the method for monitoring a clock network in an integrated circuit provided by the present disclosure is used. As shown in FIG. 1, the clock network may include multiple clock nodes, and DIV stands for clock division, which is used to convert a high clock frequency to a lower frequency for use by other circuits in the integrated circuit. The method for monitoring a clock network in an integrated circuit provided by the present disclosure can be realized using the device for monitoring a clock network in an integrated circuit provided by the present disclosure. Specifically, the device monitors the clock frequency status of a first clock node in the clock network in the integrated circuit, detects the clock operating status of a second clock node in the clock network, and determines the operating status of the clock network based on the clock frequency status of the first clock node and the clock operating status of the second clock node. If the operating status of the clock network is abnormal, the device outputs clock abnormality information, an interrupt signal, etc., to an external module to timely process the clock network and restore the operating status of the clock network, ensuring normal operation of the clock network and thereby ensuring the functional safety of the integrated circuit. The method disclosed herein can monitor the clock frequency status of only some clock nodes in a clock network (e.g., one or more first clock nodes) and detect the clock operating status of other clock nodes. The clock operating status indicates whether a clock node flips normally. However, monitoring the clock frequency status generally requires a high-precision clock frequency monitoring circuit, which monitors the specific frequency of the clock node. Compared to monitoring the clock frequency status, detecting the clock operating status can be achieved with fewer on-chip resources. Therefore, the method of the embodiment disclosed herein can effectively reduce the resource consumption of clock monitoring while supporting global monitoring of clocks in a clock network, thereby contributing to solving the problem of large resource consumption in the global monitoring method of related art.

[0014] Exemplary Methods 2 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in an exemplary embodiment of the present disclosure. This embodiment can be specifically applied to electronic devices that require a clock network, such as an in-vehicle computing platform, a mobile phone, a computer, a server, etc. As shown in FIG. 2, the method of the embodiment of the present disclosure may include the following steps 201 to 203.

[0015] In step 201, the clock frequency status of a first clock node in a clock network in an integrated circuit is monitored.

[0016] Here, the integrated circuit may be any circuit that provides a clock using a clock network. For example, it may be a chip for various functions on an in-vehicle terminal. The clock network may include multiple clock nodes, and the first clock node may be any clock node in the clock network, and is not specifically limited. The number of first clock nodes may be one or more. It may be understood that the number of first clock nodes is less than the total number of clock nodes in the clock network. For each first clock node, the clock frequency status of this first clock node can be monitored. The clock frequency status may include two states: a normal frequency and an abnormal frequency.

[0017] In some alternative embodiments, a high-precision clock frequency monitoring circuit (also referred to as a clock frequency monitoring module) can monitor the clock frequency status of the first clock node. The clock frequency monitoring circuit can be implemented using any feasible circuit configuration. For example, the clock frequency monitoring circuit may include a reference clock, a register, a counter, a comparator, etc., and the specific circuit is not limited thereto. The clock frequency monitoring circuit can count the number of reference clock periods and the number of clock periods of the first clock node within a predetermined time period, and determine the clock frequency status of the first clock node based on the counting result. For example, the clock frequency monitoring circuit may calculate a ratio between the number of reference clock periods and the number of clock periods of the first clock node, compare the ratio value with a reference value, and determine the clock frequency status of the first clock node based on the comparison result. Alternatively, the clock frequency monitoring circuit may count the number of reference clock periods within a predetermined time period based on the reference clock, compare the counting result with a reference number threshold, and determine the clock frequency status of the first clock node based on the comparison result. Alternatively, the clock frequency monitoring circuit may count the number of reference clock periods within a certain time period of the first clock node, and determine the clock frequency status of the first clock node based on the counting result. The principle of determining the clock frequency state of the first clock node is mainly to determine the frequency relationship between the first clock node and the reference clock. For example, if the frequency of the reference clock is 100 MHz and the frequency of the first clock node is 1 GHz, during the operation of the clock network, if the clock network operates normally, the ratio value between the frequency of the reference clock and the frequency of the first clock node should remain the same or change within the error range.

[0018] In step 202, the clock operating state of a second clock node in the clock network is detected.

[0019] Here, the second clock node may include a clock node other than the first clock node in the clock network. That is, each clock node other than the first clock node in the clock network may be the second clock node. For each second clock node, the clock operating state of the second clock node can be detected. The clock operating state may include a normal state and an abnormal state. The clock operating state may indicate whether the clock signal of the second clock node flips normally.

[0020] In some alternative embodiments, the first clock node may also be the second clock node, and is not specifically limited thereto.

[0021] In some alternative embodiments, a clock operation detection circuit (also referred to as a clock operation detection module) can detect the clock operation state of the second clock node. The clock operation detection circuit can be implemented using any feasible circuit structure, and can determine the clock operation state of the second clock node by periodically detecting a clock signal flip situation of the second clock node. For example, the clock operation detection circuit can include an edge detection logic circuit, a register, a comparator, etc., and the specific circuit structure is not limited thereto. The edge detection logic circuit can detect an edge (which may include a rising edge and a falling edge) of a pulse signal that triggers periodic detection. The register can record the flip state value of the second clock node within the detection period. The comparator can compare the flip state value with a preset value and determine the clock operation state of the second clock node based on the comparison result.

[0022] The order of steps 201 and 202 does not matter.

[0023] In step 203, determine the operating state of the clock network based on the clock frequency state of the first clock node and the clock operating state of the second clock node.

[0024] Here, the operating state of the clock network may include two states: normal operation and abnormal operation.

[0025] In some alternative embodiments, if at least one of the clock frequency state of the first clock node and the clock operation state of the second clock node is in an abnormal state, it can be determined that the operation state of the clock network is abnormal.

[0026] In some alternative embodiments, if it is determined that the operating status of the clock network is abnormal, an abnormality signal can be output, for example, an interrupt signal can be output to a preset module responsible for abnormality processing in the integrated circuit. The preset module can be, for example, a processor (CPU), a microcontroller (MCU), etc. in the integrated circuit, so that the preset module can perform corresponding abnormality processing on the clock network in response to the interrupt, for example, controlling the clock network or the integrated circuit to reset or restart. The specific processing method is not limited.

[0027] A method for monitoring a clock network in an integrated circuit provided in this embodiment can monitor the clock frequency status of a first clock node in a clock network in an integrated circuit, detect the clock operating status of a second clock node in the clock network, and determine the operating status of the clock network based on the clock frequency status of the first clock node and the clock operating status of the second clock node. The method of the embodiment of the present disclosure can monitor the clock frequency status of only some clock nodes in the clock network (e.g., one or more first clock nodes) and detect the clock operating status of other clock nodes. The clock operating status indicates whether the clock node flips normally. The clock frequency status generally requires a high-precision clock frequency monitoring circuit to monitor the specific frequency of the clock node. Compared to monitoring the clock frequency status, detecting the clock operating status can be achieved with fewer on-chip resources. Therefore, the method of the embodiment of the present disclosure can effectively reduce the resource consumption of clock monitoring while supporting global monitoring of clocks in a clock network, thereby helping to solve the problem of high resource consumption in global monitoring methods in related art.

[0028] FIG. 3 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in another exemplary embodiment of the present disclosure.

[0029] In some alternative embodiments, as shown in FIG. 3, monitoring the clock frequency status of a first clock node in a clock network in an integrated circuit in step 201 may include the following steps 2011 and 2012.

[0030] In step 2011, the clock frequency of the first clock node is detected according to a preset period based on the reference clock.

[0031] Here, the reference clock may be a reference clock in the clock frequency monitoring module, and the preset period (which may be referred to as the first preset period) may be set to any period according to actual needs.

[0032] In some alternative embodiments, the clock frequency of the first clock node can be represented by counting the number of clock periods of the first clock node within a preset length of time (e.g., 1 second, 1 millisecond, 1 microsecond, etc.).

[0033] In step 2012, determine the clock frequency state of the first clock node based on the matching relationship between the clock frequency of the first clock node and the preset frequency range.

[0034] Here, the preset frequency range may be represented by a preset upper frequency limit and a preset lower frequency limit. For example, the preset upper frequency limit may be 1050 clock cycles, and the preset lower frequency limit may be 950 clock cycles. The matching relationship between the clock frequency of the first clock node and the preset frequency range may include being within the preset frequency range, being smaller than the preset frequency range, and being larger than the preset frequency range. For example, if the clock frequency of the first clock node is larger than the preset upper frequency limit, it may be determined that the clock frequency of the first clock node is larger than the preset frequency range, which may indicate that the clock frequency of the first clock node is too high and belongs to a frequency abnormality. If the clock frequency of the first clock node is equal to or smaller than the preset upper frequency limit and equal to or larger than the preset lower frequency limit, it may be determined that the frequency of the first clock node is normal. If the clock frequency of the first clock node is smaller than the preset lower frequency limit, it may be determined that the frequency of the first clock node is too slow and also belongs to a frequency abnormality.

[0035] In this embodiment, the clock frequency of the first clock node is periodically detected, and the specific clock frequency state of the first clock node is determined based on the matching relationship between the clock frequency of the first clock node and a preset frequency range, thereby realizing high-precision monitoring of the first clock node and contributing to ensuring the monitoring accuracy of the first clock node.

[0036] In some alternative embodiments, as shown in FIG. 3, detecting the clock running state of the second clock node in the clock network in step 202 may include the following steps 2021 and 2022.

[0037] In step 2021, a pulse signal output from a first module in the integrated circuit is detected.

[0038] The first module may be any module capable of generating a pulse signal in an integrated circuit. The first module may periodically output a pulse signal, which may be a long pulse signal, ensuring that the clock operation detection module can detect the pulse signal and trigger detection of the clock operation state of the second clock node. For example, the pulse signal may be a microsecond-level or millisecond-level pulse signal, but is not limited thereto.

[0039] In some alternative embodiments, the first module may be a clock frequency monitoring module or some other module.

[0040] In some alternative embodiments, the first module can periodically output a pulse signal, and the output period of the pulse signal can be any period, such as 1 millisecond or other value.

[0041] In some alternative embodiments, the clock frequency monitoring module can output a pulse signal each time it completes a determination of the clock frequency state of the first clock node. For example, the clock frequency monitoring module can periodically detect the number of clock periods of the first clock node within a predetermined time period (e.g., 1 millisecond, 1 microsecond, etc.), thereby determining the clock frequency state of the first clock node. When the detection of the clock frequency state of the first clock node is completed, the clock frequency monitoring module outputs a pulse signal to trigger the detection of the clock operating state of the second clock node. In this way, the detection of the clock operating state of the second clock node can be correlated with the detection of the clock frequency state of the first clock node. For example, when the clock is turned off, the detection of the clock frequency state of the first clock node can be automatically stopped and the pulse signal can be stopped from being output to the clock operating detection module, thereby stopping the detection of the clock operating state of the second clock node and preventing the clock operating detection module from reporting an error due to the clock signal flip not being detected by the clock operating detection module.

[0042] In step 2022, the clock operating state of the second clock node is determined based on the pulse signal.

[0043] In some alternative embodiments, a flip condition of the clock signal state of the second clock node within the valid state of the pulse signal can be detected based on the pulse signal, and the clock operating state of the second clock node can be determined based on the flip condition.

[0044] In this embodiment, the first module periodically outputs a pulse signal, and triggers detection of the clock operating state of the second clock node based on the pulse signal, thereby realizing simple and effective monitoring of the second clock node, contributing to reducing the consumption of integrated circuit resources due to monitoring the second clock node, and thereby reducing the resource consumption of monitoring the entire clock network.

[0045] In some alternative embodiments, determining the clock operating state of the second clock node based on the pulse signal in Step 2022 includes: The method may include determining a clock flip state of the second clock node at a rising edge of the pulse signal, and determining a clock operation state of the second clock node based on the clock flip state of the second clock node at a falling edge of the pulse signal.

[0046] Here, the clock flip state may include two states: flip and non-flip, and different states can be represented by different state values, for example, 1 represents flip and 0 represents non-flip. If the clock flip state is flip, it can be determined that the clock operation state of this second clock node is normal, and if the clock flip state is non-flip, it can be determined that the clock operation state of this second clock node is abnormal.

[0047] In some alternative embodiments, detecting a rising edge of the pulse signal triggers sampling of the clock signal of the second clock node, determining the level state of the clock signal of the second clock node, and determining the clock flip state of the second clock node based on the level state of the clock signal of the second clock node. For example, if it is determined that the level state of the clock signal of the second clock node has changed from low to high, it indicates that a flip has occurred, i.e., the clock flip state of the second clock node is flip, and it can be determined that the clock operating state of the second clock node is normal. If it is determined that the clock signal of the second clock node maintains the low level state, it indicates that the clock signal of the second clock node has not flipped, and it can be determined that the clock operating state of the second clock node is abnormal.

[0048] In some alternative embodiments, the step of determining the clock flip state of the second clock node at the rising edge of the pulse signal may include the step of setting a value of the status register to a preset value if it is detected that the second clock node flips at the rising edge of the pulse signal, the preset value representing that the clock flip state of the second clock node is a normal flip.

[0049] The step of determining the clock operating state of the second clock node based on the clock flip state of the second clock node at the falling edge of the pulse signal may include the steps of detecting the value of a state register at the falling edge of the pulse signal, and determining the clock operating state of the second clock node based on the correspondence between the value of the state register and a preset value.

[0050] Here, the value of the state register can be initially set to a preset reset value (also referred to as the initial value), for example, 0, and the value of the state register is maintained at the reset value before the rising edge of the pulse signal arrives. If it is detected that the second clock node flips at the rising edge of the pulse signal, the value of the state register is set to a preset value, for example, 1. That is, the value of the state register flips from 0 to 1. Therefore, the value of the state register being 1 can indicate that the clock flip state of the second clock node is a normal flip. If it is detected that the second clock node does not flip, the value of the state register is maintained at the initial reset value. After the value of the state register flips to the preset value, the value of the state register is maintained at the preset value before the falling edge of the pulse signal arrives. By detecting the value of the state register at the falling edge of the pulse signal, the flip state of the second clock node can be determined, and the clock operating state of the second clock node can also be determined. Specifically, the clock operating state of the second clock node can be determined based on the correspondence between the value of the state register and the preset value. For example, the value of the status register can be compared with a preset value, and if the value of the status register is equal to the preset value, it can be determined that the clock operating state of the second clock node is normal.

[0051] In some alternative embodiments, the rising edge of the pulse signal can be detected by rising edge detection logic, the falling edge of the pulse signal can be detected by falling edge detection logic, and the comparison of the value of the status register with the preset value can be realized by a comparator.

[0052] This embodiment detects the rising and falling edges of the pulse signal, records the flip state in a status register at the rising edge of the pulse signal, and determines whether the second clock node flips at the falling edge. The rising and falling edges can represent the effective time length for detecting whether the second clock node flips. Therefore, if the second clock node flips within the effective time length from the rising edge to the falling edge, the status register can be flipped to a preset value, and it can be determined that the second clock node has flipped at the falling edge, thereby determining that the second clock node is in an operating state. If the second clock node does not flip within the effective time length of the pulse signal due to the second clock node being stuck or its frequency being too low, the value of the status register does not flip and remains at its initial value. It can then be determined based on the value of the status register at the falling edge that the second clock node has not flipped for a long time, thereby determining that the second clock node is operating abnormally. This effectively determines the clock operating state of the second clock node, contributing to improving the validity and reliability of the clock operating state of the second clock node. Due to the effective time length of the periodic pulse signal, an abnormality in the second clock node can be detected within a relatively short time length, so that the abnormality can be reported in a timely manner at the falling edge of the pulse signal, and the operating state of the second clock node can be restored in a timely manner.

[0053] In some alternative embodiments, after determining the clock operating state of the second clock node based on the correspondence between the value of the status register and the preset value, the method further includes a step of resetting the value of the status register in response to the clock operating state of the second clock node being in a normal state.

[0054] Here, if the clock operation status of the second clock node is normal, it indicates that the second clock node is operating normally, and there is no need to output an abnormality signal, or a signal indicating normality can be output and the value of the status register can be reset, for example, the value of the status register can be reset from a preset value (e.g., 1) to an initial value (e.g., 0), so that the status register can continue to be used to detect the next clock operation status.

[0055] This embodiment contributes to making the status register available for periodic detection of the clock operating status of the second clock node by resetting the value of the status register when the clock operating status of the second clock node is normal, thereby ensuring continuous and effective monitoring of the clock network.

[0056] FIG. 4 is a flowchart of a method for monitoring a clock network in an integrated circuit provided in yet another exemplary embodiment of the present disclosure.

[0057] In some alternative embodiments, as shown in FIG. 4, determining the operating state of the clock network based on the clock frequency state of the first clock node and the clock operating state of the second clock node in step 203 may include the following steps 2031 to 2033.

[0058] In step 2031, a first abnormal condition of the clock frequency state of the first clock node is determined.

[0059] Here, if the clock frequency state of any first clock node is a frequency abnormality, a first abnormal state can be determined. The first abnormal state can be expressed in any form.

[0060] In step 2032, a second abnormal condition of the clock operating state of the second clock node is determined.

[0061] Here, if the clock operation state of any second clock node is in an abnormal state, a second abnormal state can be determined.

[0062] In step 2033, it is determined that the operating state of the clock network is abnormal based on the first abnormal state and the second abnormal state.

[0063] Here, it can be determined that the operating state of the clock network is abnormal based on either the first abnormal state or the second abnormal state.

[0064] In some alternative embodiments, a first abnormal state of the clock frequency state of the first clock node and a second abnormal state of the clock operating state of the second clock node can be determined by a data selector, a logical OR device, or the like. For example, the data selector outputs an abnormal signal indicating the first abnormal state when the clock frequency state of the first clock node is in an abnormal state, and outputs an abnormal signal indicating the second abnormal state when the clock operating state of the second clock node is in an abnormal state, thereby making it easy to determine which clock node in the clock network is operating abnormally. Also, for example, the logical OR device may output an abnormal signal indicating that the operating state of the clock network is abnormal when at least one of the clock frequency state of the first clock node is in an abnormal state (i.e., frequency abnormality) and the clock operating state of the second clock node is in an abnormal state.

[0065] In this embodiment, the operating state of the clock network is determined to be abnormal based on a first abnormal state of the clock frequency state of a first clock node and a second abnormal state of the clock operating state of a second clock node. The first clock node and the second clock node can cover all nodes in the clock network. When the clock frequency state of any first clock node is abnormal, the first abnormal state can be determined. When the clock operating state of any second clock node is abnormal, the second abnormal state can be determined. Therefore, when an abnormality occurs in any clock node in the clock network, the abnormality in the clock network can be detected in a timely manner, which facilitates the timely restoration of normal operation of the clock network and realizes global monitoring of the clock network with low resource consumption.

[0066] In some alternative embodiments, if the operational state of the clock network is determined to be abnormal, the method of the disclosed embodiment may further include resetting the clock network or the integrated circuit.

[0067] In some alternative embodiments, if it is determined that the clock frequency state of the first clock node is in an abnormal state, the method of the embodiment of the present disclosure may further include a step of detecting the clock frequency state of the first clock node again.

[0068] In some alternative embodiments, if it is determined that the clock operating status of the second clock node is in an abnormal state, the method of the embodiment of the present disclosure may further include a step of detecting the clock operating status of the second clock node again.

[0069] In some alternative embodiments, FIG. 5 is a flowchart of a clock operation status detection provided in an exemplary embodiment of the present disclosure. As shown in FIG. 5, the first module outputting a pulse signal may be a clock frequency monitoring module. A high-precision clock frequency monitoring module can be pre-configured by software, so that the clock frequency monitoring module can monitor the clock frequency status of the first clock node and periodically output a pulse signal. The clock operation detection module can detect the occurrence of a rising edge of the pulse signal. If a rising edge of the pulse signal does not occur, it continues to detect whether a rising edge occurs. If a rising edge of the pulse signal occurs, it detects whether a second clock node flips. If the second clock node flips, it sets the value of a register (i.e., a status register) to a preset value (e.g., 1); if the second clock node does not flip, the value of the register remains at its original value (e.g., 0). Next, it detects whether a falling edge of the pulse signal occurs. If a falling edge does not occur, it continues detecting. If a falling edge occurs, it detects whether the register value is correct (i.e., whether it is a preset value). If it is incorrect, it indicates that the clock operating state of this second clock node is abnormal, and an error line can be set and an abnormal signal can be output. If the register value is correct, it indicates that the clock operating state of the second clock node is normal, and it can reset the register and wait for the next rising edge of the pulse signal to occur, thereby detecting the next clock operating state. By this analogy, high-precision monitoring of the first clock node and periodic detection of the clock operating state of the second clock node are achieved, ensuring the normal operation of the clock network and thereby ensuring the functional safety of the integrated circuit.

[0070] The method of the embodiment of the present disclosure performs high-precision monitoring of one or some clock nodes based on the consistency of the clock sources of each clock node in a clock network, so that if a frequency error becomes too large, it can be detected in a timely manner, and protects a large number of other clock nodes in the form of clock running state detection, ensuring that these clock nodes will be detected in a timely manner if they hang up (also called stuck) or have a frequency that is too low, with the lowest resource consumption, thereby ensuring global monitoring of the clock network and effectively reducing the resource consumption of monitoring.

[0071] The above-mentioned embodiments of the present disclosure may be implemented alone, or may be implemented in any combination manner if there is no contradiction, and specifically may be set according to actual needs, and the present disclosure is not limited thereto.

[0072] Any of the methods for monitoring a clock network in an integrated circuit provided in the embodiments of the present disclosure may be executed by any suitable device having data processing capabilities, including, but not limited to, a terminal device, a server, etc. Alternatively, any of the methods for monitoring a clock network in an integrated circuit provided in the embodiments of the present disclosure may be executed by a processor, for example, the processor executes any of the methods for monitoring a clock network in an integrated circuit mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. Hereinafter, a description thereof will be omitted.

[0073] Exemplary Apparatus 6 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in an exemplary embodiment of the present disclosure. The device in this embodiment can be used to implement an embodiment of a method corresponding to the present disclosure. The device shown in FIG. 6 may include a clock frequency monitoring module 51, a clock activity detection module 52, and a processing module 53.

[0074] The clock frequency monitoring module 51 is used to monitor the clock frequency status of a first clock node in a clock network in an integrated circuit.

[0075] The clock operation detection module 52 is used to detect the clock operation status of a second clock node in the clock network.

[0076] The processing module 53 is respectively connected to the clock frequency monitoring module 51 and the clock operation detection module 52, and is used to determine the operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node.

[0077] Here, the specific functions of each module can be referred to in the corresponding method embodiments described above, and the description thereof will be omitted here.

[0078] In some alternative embodiments, each of the above modules can be implemented by software, hardware, a combination of software and hardware, etc., and the specific implementation is not limited thereto. To ensure the real-time nature of clock network monitoring, each of the above modules can be implemented by hardware. For example, the clock frequency monitoring module 51 may be implemented by a high-precision clock frequency monitoring circuit (e.g., the reference clock, counter, register, comparator, etc., described above). The clock operation detection module 52 may be implemented by a simple and effective clock operation detection circuit (e.g., the edge detection logic circuit, register, comparator, etc., described above). The processing module 53 may be implemented by a processing logic circuit (e.g., the data selector and OR device, etc., described above).

[0079] In some alternative embodiments, depending on the number of first clock nodes, the device of the disclosed embodiment may include one or more clock frequency monitoring modules 51. Each first clock node may be connected to one corresponding clock frequency monitoring module 51. The first clock nodes may have a one-to-one correspondence with the clock frequency monitoring modules 51. Similarly, depending on the number of second clock nodes, the device of the disclosed embodiment may include clock operation detection modules 52 corresponding to each second clock node, thereby realizing global monitoring of the clock nodes of the clock network in the integrated circuit.

[0080] In some alternative embodiments, the clock frequency monitoring module 51 may include a monitoring unit corresponding to each first clock node, thereby monitoring the clock frequency status of each first clock node, and the clock operation detection module 52 may include a detection unit corresponding to each second clock node, thereby monitoring the clock operation status of each second clock node.

[0081] FIG. 7 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in another exemplary embodiment of the present disclosure.

[0082] In some alternative embodiments, as shown in FIG. 7, the clock frequency monitoring module 51 may include a clock frequency detection unit 511 and a clock frequency status determination unit 512.

[0083] The clock frequency detection unit 511 can be used to detect the clock frequency of the first clock node according to a preset period based on a reference clock.

[0084] In some alternative embodiments, the clock frequency detection unit 511 may include a reference clock, a counter, a register, and the like.

[0085] The clock frequency state determination unit 512 is respectively connected to the clock frequency detection unit 511 and the processing module 53, and the clock frequency state determination unit 512 can be used to determine the clock frequency state of the first clock node based on the matching relationship between the clock frequency of the first clock node and the preset frequency range.

[0086] The clock frequency state determination unit 512 may further be used to output a frequency abnormality signal to the processing module 53 in response to determining that the clock frequency state of the first clock node is a frequency abnormality.

[0087] In some alternative embodiments, the clock frequency state determination unit 512 may include a comparator to implement a comparison between the clock frequency of the first clock node and a boundary value of a preset frequency range.

[0088] In some alternative embodiments, as shown in FIG. 7, the clock operation detection module 52 may include a pulse signal detection unit 521 and a clock operation state determination unit 522.

[0089] The pulse signal detection unit 521 can be connected to a first module that generates a pulse signal, and the pulse signal detection unit 521 can be used to detect the pulse signal output from the first module.

[0090] In some alternative embodiments, the pulse signal detection unit 521 may include an edge detection logic circuit used to detect an active pulse of the pulse signal. The edge detection logic circuit may be implemented by any feasible circuit configuration. For example, the edge detection logic circuit may include a two-stage flip-flop, an inverter, a logical AND device, etc., and the specific circuit structure is not limited.

[0091] The clock running state determining unit 522 can be connected to the pulse signal detecting unit 521, and the clock running state determining unit 522 can be used to determine the clock running state of the second clock node based on the pulse signal.

[0092] In some alternative embodiments, the clock operating state determination unit 522 samples a signal flip state of the clock of the second clock node within an effective pulse period of the pulse signal based on the pulse signal, and thereby determines the clock operating state of the second clock node based on the flip state.

[0093] FIG. 8 is a structural schematic diagram of a clock network monitoring device in an integrated circuit provided in yet another exemplary embodiment of the present disclosure.

[0094] In some alternative embodiments, as shown in FIG. 8, the pulse signal detection unit 521 may include a rising edge detection circuit 5211 and a falling edge detection circuit 5212.

[0095] The rising edge detection circuit 5211 is respectively connected to the first module and the clock operating state determination unit 522, and the rising edge detection circuit 5211 can be used to output a first trigger signal to the clock operating state determination unit 522 at the rising edge of the pulse signal.

[0096] Here, the first trigger signal may be a high-level signal, and after detecting the rising edge of the pulse signal, the rising edge detection circuit 5211 outputs a high-level first trigger signal to the clock running state determination unit 522, thereby triggering the clock running state determination unit 522 to sample the flip state of the clock signal of the second clock node.

[0097] The falling edge detection circuit 5212 can be connected to the first module and the clock operating state determination unit 522 respectively, and the falling edge detection circuit 5212 can be used to output a second trigger signal to the clock operating state determination unit 522 at the falling edge of the pulse signal.

[0098] Here, the second trigger signal may be a high-level signal. When the falling edge detection circuit 5212 detects the falling edge of the pulse signal, it outputs a high-level second trigger signal to the clock operating state determination unit 522.

[0099] The clock running state determination unit 522 may be used to determine the clock flip state of the second clock node in response to the first trigger signal.

[0100] Here, the clock operating state determination unit 522 samples the flip state of the clock signal of the second clock node when triggered by the first trigger signal, and can determine that the flip state of the clock signal of the second clock node is flipped if the clock signal of the second clock node flips; otherwise, it is not flipped.

[0101] The clock running state determination unit 522 may further be used to determine the clock running state of the second clock node based on the clock flip state of the second clock node in response to the second trigger signal.

[0102] Here, the clock running state determination unit 522 is triggered by the second trigger signal to determine the clock running state of the second clock node based on the clock flip state of the second clock node, and if a flip occurs, determines that the clock running state of the second clock node is normal; otherwise, determines that the clock running state is abnormal.

[0103] In some alternative embodiments, the clock operating state determination unit 522 may include a state register 5221 and a state detection circuit 5222 .

[0104] The state register 5221 can be connected to the rising edge detection circuit 5211 and the second clock node, and the state register 5221 can be used to flip the value of the state register to a preset value in response to the first trigger signal when the second clock node flips.

[0105] Here, the flip of the second clock node means that the level state of the clock signal of the second clock node changes; for example, the clock signal of the second clock node flips from low level to high level.

[0106] In some alternative embodiments, the first trigger signal and the clock signal are inputs to a state register, and when the first trigger signal is at a high level, the clock signal flips from a low level to a high level, triggering the value of the state register to flip from an initial value of 0 to a preset value of 1.

[0107] The state detection circuit 5222 can be connected to the falling edge detection circuit 5212, the state register 5221 and the processing module 53, respectively, and the state detection circuit 5222 can be used to respond to the second trigger signal, detect the value of the state register 5221, and determine the clock operating state of the second clock node based on the correspondence between the value of the state register 5221 and the preset value.

[0108] The state detection circuit 5222 may further be used to output an operation state abnormal signal to the processing module 53 in response to determining that the clock operation state of the second clock node is in an abnormal state.

[0109] In some alternative embodiments, the state detection circuit 5222 may include a comparator and a reference register, the output of the falling edge detection circuit 5212 is the operation enable input of the comparator, the state register 5221 is connected to one input end of the comparator, the reference register stores a preset value and is connected to the other input end of the comparator, and the comparator operates in response to a second trigger signal, compares the value of the state register 5221 with the preset value of the reference register, and outputs the clock operation status of the second clock node based on the comparison result, for example, outputting 0 to indicate an abnormality and outputting 1 to indicate normality, or outputting 0 to indicate normality and outputting 1 to indicate an abnormality.

[0110] In some alternative embodiments, as shown in FIG. 8, the clock operating state determination unit 522 may further include a reset circuit 5223.

[0111] The reset circuit 5223 can be connected to the state detection circuit 5222 and the state register 5221, respectively, and the reset circuit 5223 can be used to reset the value of the state register 5221 in response to determining that the clock operating state of the second clock node is normal.

[0112] Here, the reset circuit 5223 can be realized using any operable logic circuit. When the reset circuit 5223 determines that the clock operation state of the second clock node is normal, it outputs a reset signal (also called a reset signal) to the state register 5221, and can control the state register 5221 to reset. For example, the output terminal of the reset circuit 5223 is connected to a reset pin of the state register 5221, and outputs the reset signal to the state register 5221 via the reset pin. After receiving the reset signal, the state register 5221 clears its internal value and returns to its initial value. The specific reset method is not limited to the above method.

[0113] In some alternative embodiments, as shown in FIG. 7, the processing module 53 may include a data selector 531 and an interrupt register 532.

[0114] The data selector 531 may be used to output an abnormal condition signal in response to a first abnormal condition of the clock frequency state of the first clock node and a second abnormal condition of the clock operation state of the second clock node.

[0115] Here, the abnormal state signal may be a high level signal or a low level signal, and is not specifically limited.

[0116] In some alternative embodiments, the data selector may be an either / or selector that outputs an abnormal state signal when either the clock frequency state of the first clock node or the clock operation state of the second clock node is abnormal.

[0117] The interrupt register 532 can be connected to the data selector 531, and the interrupt register 532 can be used to output an interrupt signal to the preset module of the integrated circuit based on the abnormal state signal.

[0118] Here, the preset module may be a module that can perform abnormal processing on the clock network in response to an interrupt, such as a processor (CPU) or a microcontroller (MCU) in the basic circuit, and is not specifically limited.

[0119] In some alternative embodiments, the preset module can respond to an interrupt signal and reset the clock network or the integrated circuit to restore the operating state of the clock network.

[0120] In some alternative embodiments, the interrupt register 532 may be used to output a first instruction signal to the clock frequency monitoring module 51 in response to the clock frequency status of the first clock node being in an abnormal state, instructing the clock frequency monitoring module 51 to re-detect the clock frequency status of the first clock node. If the clock frequency status of the first clock node obtained by the re-detection is normal, no error processing may be performed, and the clock frequency status of the first clock node may continue to be monitored. If the clock frequency status of the first clock node obtained by the re-detection is in an abnormal state, processing such as resetting the clock network or the integrated circuit may be performed.

[0121] In some alternative embodiments, the interrupt register 532 may be used to output a second instruction signal to the clock operation detection module 52 in response to the clock operation status of the second clock node being in an abnormal state, instructing the clock operation detection module 52 to re-detect the clock operation status of the second clock node. A subsequent processing method may be determined based on the re-detection result. For example, if the re-detection result remains in an abnormal state, processing such as resetting the clock network or the integrated circuit may be performed.

[0122] In some alternative embodiments, for multiple first clock nodes, the device of the disclosed embodiment may further include a first OR unit used to perform a logical OR operation on the outputs of the clock frequency monitoring modules 51 corresponding to each first clock node, and output an abnormal signal to the processing module 53 if the clock frequency status of any of the first clock nodes is abnormal (e.g., indicated as 1).

[0123] In some alternative embodiments, for multiple second clock nodes, the device of the disclosed embodiment may further include a second OR unit used to perform a logical OR operation on the outputs of the clock operation detection modules 52 corresponding to each second clock node, and output an abnormal signal to the processing module 53 if the clock operation status of any second clock node is abnormal (e.g., indicated as 1).

[0124] In some alternative embodiments, Figure 9 is a structural schematic diagram of an exemplary embodiment of a clock network monitoring device in an integrated circuit provided in an exemplary embodiment of the present disclosure. As shown in Figure 9, any one or more clock nodes in the clock network can be a first clock node. For example, one clock node in the figure is the first clock node, and a clock frequency monitoring module 51 monitors the clock frequency status of the first clock node. Other clock nodes in the clock network other than the first clock node can be second clock nodes. Each second clock node can correspond to a clock operation detection module 52, and the clock operation detection module 52 detects the clock operation status of the second clock node. The clock frequency monitoring module 51, as a first module for generating a pulse signal, provides a periodic pulse signal to each clock operation detection module 52. The clock frequency monitoring module 51 and each clock operation detection module 52 are respectively connected to the processing module 53, or each clock operation detection module is connected to the processing module 53 via a logical OR circuit or a data selector, etc., and outputs the clock frequency state of the first clock node and the clock operation state of the second clock node to the processing module 53. The processing module 53 can determine the operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node, and when an abnormality occurs in the operation state of the clock network, it outputs an interrupt signal to the preset module, causing the preset module to perform abnormality processing on the clock network or integrated circuit in a timely manner, and restore the operation state of the clock network.

[0125] 10 is a structural schematic diagram of an exemplary embodiment of the clock operation detection module 52 provided in an exemplary embodiment of the present disclosure. As shown in FIG. 10, for any second clock node, mesh_clk represents the clock signal output from this second clock node. The clock frequency monitoring module 51 monitors the clock frequency status of the first clock node (outputting a frequency abnormality signal clk_frequency_error when a frequency abnormality occurs), and at the same time, outputs a pulse signal (i.e., cmm_int in the figure) at a regular interval based on the reference clock of the clock frequency monitoring module 51. The clock signal of the second clock node can provide an operating clock to the rising edge detection circuit 5211 and the status register 5221, and can also provide an operating clock to other circuits that require an operating clock. The rising edge detection circuit 5211 outputs a first trigger signal to the state register 5221 according to the pulse signal and the clock signal, and the state register 5221 flips or maintains its original value according to the first trigger signal and the clock signal. For example, if the first trigger signal is at a high level (or 1) and the clock signal is at a high level (or 1), the value of the state register 5221 flips to a preset value, for example, flips from 0 to 1, indicating that the second clock node flips normally. If either the first trigger signal or the clock signal is at a low level, the value of the state register 5221 does not flip and remains at a reset value (for example, 0), indicating that the pulse signal does not reach a rising edge or that the clock signal of the second clock node does not flip.After detecting the rising edge of the pulse signal, the falling edge detection circuit 5212 continues to detect the falling edge of the pulse signal, and at the falling edge of the pulse signal, the falling edge detection circuit 5212 outputs a second trigger signal (e.g., a high level signal or 1) to the state detection circuit 5222, the state detection circuit 5222 detects the value of the state register in response to the second trigger signal, compares the value of the state register with a preset value, and if the value of the state register 5221 is the preset value, it can be determined that the second clock node has flipped normally, thereby determining that the clock operating state of the second clock node is in a normal state; if the value of the state register 5221 is not the preset value, it can be determined that the second clock node has not flipped, thereby determining that the clock operating state of the second clock node is in an abnormal state, and the state detection circuit 5222 can output an operating state abnormal signal (i.e., clk_stuck_error in the figure) to the processing module 53. If the state detection circuit 5222 determines that the clock operating state of the second clock node is normal, it can output a reset trigger signal to the reset circuit 5223, and the reset circuit 5223 outputs a reset signal to the state register 5221 in response to the reset trigger signal, resetting the value of the state register 5221 to a reset value (e.g., 0). Each second clock node in the clock network can periodically detect its clock operating state according to the above detection process, and the first clock node in the clock network detects the clock frequency state using the high-precision clock frequency monitoring module 51, thereby ensuring the accuracy of local monitoring and simultaneously realizing global monitoring of the clock network and reducing the resources consumed in the monitoring process.

[0126] The beneficial technical effects corresponding to the exemplary embodiments of the present device can be referred to the beneficial technical effects corresponding to the exemplary method part above, and the description thereof will be omitted here.

[0127] Exemplary Electronic Devices FIG. 11 is a structural diagram of an electronic device provided in an embodiment of the present disclosure, which includes at least one processor 11 and a memory 12.

[0128] The processor 11 may be a central processing unit (CPU) or other processing unit having data processing and / or instruction execution capabilities, and may control other components within the electronic device 10 to perform desired functions.

[0129] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage media, and the processor 11 may execute the one or more computer program instructions to implement the methods of the above-described embodiments of the present disclosure and / or other desired functions.

[0130] In one example, electronic device 10 may further include input devices 13 and output devices 14, with these components interconnected via a bus system and / or other form of connection (not shown).

[0131] The input device 13 may further include, for example, a keyboard and a mouse.

[0132] The output device 14 can output various types of information to the outside, and may include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto.

[0133] 11 shows only some of the components of the electronic device 10 that are relevant to the present disclosure, and omits components such as a bus and an output / input interface, etc. In addition, the electronic device 10 may further include any other appropriate components depending on the specific application.

[0134] In some alternative embodiments, the embodiments of the present disclosure may further provide an electronic device, which may include a clock network monitoring device in an integrated circuit provided in any of the above embodiments of the present disclosure.

[0135] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the methods and apparatus described above, embodiments of the present disclosure may further provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods of various embodiments of the present disclosure described in the "Example Methods" section above.

[0136] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java®, C++®, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on a user's computing device, partially on a user's device, as separate software packages, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or a server.

[0137] Additionally, embodiments of the present disclosure may be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods of various embodiments of the present disclosure described in the "Example Methods" section above.

[0138] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0139] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, effects, etc. mentioned in the present disclosure are not limited but merely illustrative, and these benefits, advantages, effects, etc. do not necessarily exist in each embodiment of the present disclosure. Furthermore, the specific details disclosed above are not limited but merely serve to serve as examples and to facilitate understanding, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0140] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure also intends to include these modifications and variations.

Claims

1. monitoring a clock frequency status of a first clock node in a clock network in an integrated circuit; detecting a clock operating state of a second clock node in the clock network; determining an operational state of the clock network based on a clock frequency state of the first clock node and a clock operational state of the second clock node; A method for monitoring a clock network in an integrated circuit, performed by an apparatus for monitoring a clock network in an integrated circuit.

2. The step of detecting a clock operating state of a second clock node in the clock network includes: Detecting a pulse signal output from a first module in the integrated circuit; determining a clock operation state of the second clock node based on the pulse signal; 2. The method for monitoring a clock network in an integrated circuit according to claim 1.

3. The step of determining the clock operation state of the second clock node based on the pulse signal includes: determining a clock flip state of the second clock node at a rising edge of the pulse signal; and determining a clock operation state of the second clock node based on a clock flip state of the second clock node at a falling edge of the pulse signal.

3. The method for monitoring a clock network in an integrated circuit according to claim 2.

4. determining a clock flip state of the second clock node at a rising edge of the pulse signal, a step of setting a value of a state register to a preset value when detecting that the second clock node flips at a rising edge of the pulse signal, the preset value indicating that the clock flip state of the second clock node is a normal flip; determining a clock operation state of the second clock node based on a clock flip state of the second clock node at a falling edge of the pulse signal, detecting the value of the status register at the falling edge of the pulse signal; determining a clock operation state of the second clock node based on a correspondence between the value of the status register and the preset value; 4. The method for monitoring a clock network in an integrated circuit according to claim 3.

5. after determining the clock operation state of the second clock node based on the correspondence between the value of the status register and the preset value, resetting a value of the status register in response to the clock operation status of the second clock node being a normal status; 5. The method for monitoring a clock network in an integrated circuit according to claim 4.

6. The step of monitoring a clock frequency status of a first clock node in a clock network in an integrated circuit includes: detecting a clock frequency of the first clock node according to a preset period based on a reference clock; determining a clock frequency state of the first clock node based on a matching relationship between the clock frequency of the first clock node and a preset frequency range; A method for monitoring a clock network in an integrated circuit according to any one of claims 1 to 5.

7. determining an operating state of the clock network based on a clock frequency state of the first clock node and a clock operating state of the second clock node; determining a first abnormal condition of a clock frequency state of the first clock node; determining a second abnormal condition of the clock operating state of the second clock node; determining that the operating state of the clock network is abnormal based on the first abnormal state and the second abnormal state; A method for monitoring a clock network in an integrated circuit according to any one of claims 1 to 5.

8. a clock frequency monitoring module for monitoring a clock frequency status of a first clock node in a clock network in the integrated circuit; a clock operation detection module for detecting a clock operation state of a second clock node in the clock network; a processing module coupled to the clock frequency monitoring module and the clock operation detection module, respectively, for determining an operation state of the clock network based on the clock frequency state of the first clock node and the clock operation state of the second clock node; A device for monitoring a clock network in an integrated circuit.

9. The clock detection module includes: a pulse signal detection unit connected to a first module that generates a pulse signal, for detecting the pulse signal output from the first module; a clock operating state determination unit connected to the pulse signal detection unit, for determining a clock operating state of the second clock node based on the pulse signal; 9. The apparatus for monitoring a clock network in an integrated circuit according to claim 8.

10. The clock frequency monitoring module a clock frequency detection unit for detecting a clock frequency of the first clock node according to a preset period based on a reference clock; a clock frequency state determination unit, respectively connected to the clock frequency detection unit and the processing module, for determining a clock frequency state of the first clock node based on a matching relationship between the clock frequency of the first clock node and a preset frequency range; the clock frequency state determination unit is further configured to output a frequency abnormality signal to the processing module in response to determining that the clock frequency state of the first clock node is a frequency abnormality. The device for monitoring a clock network in an integrated circuit according to any one of claims 8 to 9.

11. A computer program for executing the method for monitoring a clock network in an integrated circuit according to claim 1 is stored. A computer-readable storage medium.

12. An electronic device, Processor and a memory for storing instructions executable by the processor; The processor is adapted to read and execute the executable instructions from the memory to implement the method for monitoring a clock network in an integrated circuit according to claim 1; or The electronic device includes the clock network monitoring device in an integrated circuit according to claim 8. electronic equipment.

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