Pixel circuit and display panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a driving module, a first reset module, a data writing module, a first light emission control module, a second light emission control module, and a memory module. The first reset module is connected to the driving module, the data writing module is connected to the driving module, the first light emission control module is connected in series between a light emitting element, a positive voltage power supply, and the driving module, the second light emission control module is connected between the driving module and a negative voltage power supply, and the memory module is electrically connected to the driving module.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application bearing application number 202310445544.8, filed with the China Patent Office on April 21, 2023, the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION The present application relates to the field of display technology, for example pixel circuits and display panels. [Background technology]

[0003] With the continuous development of display technology, the application range of display panels is becoming wider and wider, and user requirements for display panels are also increasing. The pixel circuit in a display panel plays a very important role in driving a light-emitting element to stably emit light. However, in the pixel circuit of the related art, the gate electrode potential of the driving transistor is unstable during the display process, which affects the stable output of the driving current, affects the display brightness of the light-emitting element, and further affects the display uniformity of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a pixel circuit and a display panel, which stabilizes the potential of the control end of the driving module in the pixel circuit, allows the pixel circuit to output a stable driving current in the light-emitting stage, and is advantageous in improving the display uniformity of the display panel. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides a pixel circuit including: a driving module configured to generate a driving current based on a potential of a control end thereof; a first reset module connected to the control end of the driving module and configured to transmit a first reset signal to the control end of the driving module in response to a first scanning signal; a data writing module connected to the driving module and configured to transmit a data voltage to the driving module in response to a second scanning signal; a first light-emitting control module connected in series between a light-emitting element, a positive voltage power supply, and a second end of the driving module, the first light-emitting control module being turned on in response to a light-emitting control signal and configured to transmit a first power supply signal provided from the positive voltage power supply to the second end of the driving module via a cathode of the light-emitting element; a second light-emitting control module connected between the first end of the driving module and a negative voltage power supply and being turned on in response to the light-emitting control signal; and a memory module electrically connected to the control end of the driving module and configured to store a potential of the control end of the driving module.

[0006] In a second aspect, an embodiment of the present application further provides a display panel including a plurality of pixel circuits according to any embodiment of the present application. [Effects of the Invention]

[0007] The present embodiment provides a circuit structure in which the cathodes of the light-emitting elements are isolated and the cathode potentials of the light-emitting elements can be individually controlled, and the cathodes of the light-emitting elements are connected to a pixel circuit. The cathodes of the light-emitting elements are directly or indirectly connected to the second end of the driving module, allowing the first end of the driving module to be connected to a negative voltage power supply by a second light-emitting control module. During the light-emitting phase, the second light-emitting control module is conductive, and the first end of the driving module receives a stable second power signal provided by the negative voltage power supply, thereby maintaining the potential of the first end of the driving module unchanged. At the same time, a memory module is provided to store charges and preserve the potential during the light-emitting phase, thereby maintaining the potential of the control end of the driving module unchanged. Therefore, the pixel circuit according to the embodiment of the present application can control the potentials of the control terminal and the first terminal of the driving module so that they do not change during the light-emitting stage. Compared with the related art in which the potentials of the gate electrode and the source electrode of the driving transistor both fluctuate during the light-emitting stage, the embodiment of the present application makes it easier to ensure that the potential difference between the control terminal and the first terminal of the driving module does not change. As a result, the driving current output from the driving module does not change, and the brightness of the light-emitting element during the light-emitting stage does not change, which is advantageous to improving the display uniformity of the display panel. Furthermore, the memory module in the embodiment of the present application does not need to provide a coupling function and only needs to provide a potential holding function, which reduces the impact of the memory module on the light-emitting brightness, reduces design requirements for the memory module, and allows for more flexibility in the configuration of the memory module and its layout on the display panel. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram illustrating the circuit structure of a pixel circuit in the related art. [Figure 2] FIG. 1 is a schematic diagram of a film layer structure of a pixel circuit in the related art. [Figure 3] FIG. 2 is a schematic diagram of a circuit structure of a pixel circuit according to an embodiment of the present application. [Figure 4] FIG. 2 is a schematic diagram of a time sequence of driving a pixel circuit according to an embodiment of the present application. [Figure 5] FIG. 10 is a schematic diagram of the circuit structure of another pixel circuit according to an embodiment of the present application. [Figure 6] FIG. 10 is a schematic diagram of a time sequence of driving another pixel circuit according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a film layer structure of a pixel circuit according to an embodiment of the present application. [Figure 8] FIG. 10 is a schematic diagram of a circuit structure of yet another pixel circuit according to an embodiment of the present application. [Figure 9] FIG. 10 is a schematic diagram of a circuit structure of yet another pixel circuit according to an embodiment of the present application. [Figure 10] FIG. 10 is a schematic diagram of a time sequence of driving still another pixel circuit according to an embodiment of the present application. [Figure 11] FIG. 10 is a schematic diagram of a circuit structure of yet another pixel circuit according to an embodiment of the present application. [Figure 12] 10A and 10B are simulation waveform diagrams of a driving process of a pixel circuit in the related art. [Figure 13] 10A and 10B are simulation waveform diagrams of the driving process of the pixel circuit according to the embodiment of the present application. [Figure 14] 10 is a graph showing the amount of change in luminance with fluctuation in the threshold voltage of the driving transistor of the pixel circuit according to the embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0009] The terms "first," "second," etc. in the specification and claims of this application, as well as in the drawings, need not be used to describe a particular order or chronology, but are intended to distinguish between similar subjects. It should be understood that the terms so used may be substituted where appropriate, such that the embodiments of this application described herein may be practiced in orders other than those illustrated or described herein. Additionally, the terms "comprise" and "have," and any variations thereof, are intended to cover non-exclusive inclusions.

[0010] As described in the background art, pixel circuits in related art suffer from an unstable gate electrode potential of the driving transistor during the display process, which affects the display uniformity of the display panel. According to the applicant's research, the reason for this is as follows: Pixel circuits in small-sized display products in related art typically employ either an LTPS (Low Temperature Poly-Silicon) pixel circuit, i.e., a structure in which all transistors in the pixel circuit are P-type transistors, or an LTPO (Low Temperature Polycrystalline Oxide) pixel circuit, i.e., a structure in which some transistors in the pixel circuit are P-type transistors and some transistors are N-type transistors. In these pixel circuits, all driving transistors are P-type transistors. However, in medium-sized and large-sized products, the P-type transistors have defects such as large leakage current and poor long-distance uniformity, which limits the applicability of these pixel circuits. Therefore, medium-sized and large-sized products manufactured using these pixel circuits are likely to suffer from poor brightness uniformity. Therefore, in the field of medium and large sizes, pixel circuits based on IGZO (Indium Gallium Zinc Oxide) have been proposed, in which all transistors in the pixel circuit are N-type transistors, in order to improve display uniformity by taking advantage of the low leakage current and good long-distance uniformity of N-type IGZO transistors.

[0011] FIG. 1 is a schematic diagram of the circuit structure of a pixel circuit in the related art. Referring to FIG. 1, the all-N-type pixel circuit in the related art includes a driving transistor M01 and switching transistors M02-M06, and signals applied to the transistors include scan signals S01, S02, and S03, light-emitting control signals EM01 and EM02, a first power supply signal VDD, a second power supply signal VSS, a data voltage Data, and a reset signal Vref0. FIG. 2 is a schematic diagram of the film layer structure of the pixel circuit in the related art. The structures of the switching transistors M05 and M06 are omitted in FIG. 2, and the connection structure between the driving transistor M01 and the light-emitting element OLED is mainly shown. In actual manufacturing, the driving transistor M01 can be connected to the light-emitting element OLED via the switching transistor M06. 1 and 2, the film layer structure of the all-N-type pixel circuit in the related art uses the film layer structure of the LTPS pixel circuit as is, and includes an active layer 010, a first metal layer 011, a second metal layer 012, and a third metal layer 013 laminated on a substrate 001. The light-emitting element OLED also has a common cathode structure, i.e., the cathodes of multiple light-emitting elements OLED in the display panel are provided over the entire surface and the same cathode voltage VSS is applied. The light-emitting element OLED includes an anode 021, a light-emitting functional layer 022, and a cathode 023 laminated on the side of the third metal layer 013 farther from the substrate 001. The anode of the light-emitting element OLED is connected to the pixel circuit, and the pixel circuit individually controls the anode potential of the corresponding light-emitting element OLED.

[0012] After adjusting the driving transistor M01 so that the N-type transistor is connected to the anode of the light-emitting element OLED, the direction of current flow when the light-emitting element OLED emits light is anode → cathode, so the source electrode of the driving transistor M01 is connected to the anode of the light-emitting element OLED. For example, ignoring the switching transistors M05 and M06, the current path during the light-emitting stage is from the power line LVDD (used to transmit the power signal VDD) → the drain electrode M011 of the driving transistor M01 → the channel region M012 of the driving transistor M01 → the source electrode M013 of the driving transistor M01 → the anode 021 of the light-emitting element OLED → the light-emitting functional layer 022 → the cathode 023 of the light-emitting element OLED. Meanwhile, because the anode potential of the light-emitting element OLED changes when it emits light, the gate-source voltage difference of the driving transistor M01 constantly changes during the light-emitting process, and the driving current output from the driving transistor M01 becomes unstable. To avoid this situation, in related art, a pixel circuit includes a capacitor Cst0 connected to the gate electrode of the driving transistor M01 and the anode of the light-emitting element OLED, respectively, and when the switching transistor M06 is conductive, the capacitor Cst0 corresponds to a capacitor connected between the gate electrode and source electrode of the driving transistor M01. During the light-emitting stage, the capacitor Cst0 maintains the gate-source voltage difference of the driving transistor M01 based on its coupling effect, but the coupling effect of the capacitor is affected by the size of the capacitor Cst0 and the gate-source voltage difference of the driving transistor M01 cannot be maintained 100% unchanged. Furthermore, in this design, the capacitor Cst0 not only affects the charging efficiency during the data write process, but also the gate electrode potential of the driving transistor M01 after coupling by the capacitor during the light-emitting stage, so the size of the capacitor has a significant impact on the driving current.

[0013] For the above reasons, in the related art, since the light-emitting element OLED has a common cathode structure, the pixel circuit based on all N-type transistors can only be connected to the anode of the light-emitting element OLED, and individual control of the anode potential of multiple light-emitting elements OLED is realized. Due to the above limitations, during the light-emitting stage, the gate-source voltage difference of the driving transistor in the pixel circuit becomes unstable, which causes the driving current output from the pixel circuit to become unstable, affecting display uniformity.

[0014] The applicant designed an element structure in which the cathode of each light-emitting element is individually separated, and based on this, designed a pixel circuit structure in which the driving transistor is electrically connected to the cathode of the light-emitting element to individually control the cathode potential of the light-emitting element, thereby stabilizing the gate electrode potential of the driving transistor in the pixel circuit during the light-emitting stage. During the manufacturing process of the display panel, an isolation structure is provided to separate the cathodes of adjacent light-emitting elements, allowing the cathodes of multiple light-emitting elements to be connected to corresponding pixel circuits, thereby achieving individual control of the cathode potential of multiple light-emitting elements by the pixel circuit. Below, we first explain the structure and operating principle of the pixel circuit, and the connection relationship between the light-emitting elements and the pixel circuit.

[0015] 3 is a circuit diagram of a pixel circuit according to an embodiment of the present invention, which includes a driving module 10, a first reset module 20, a data writing module 30, a first light-emitting control module 40, a second light-emitting control module 50, and a storage module 60.

[0016] The driving module 10 is configured to generate a driving current based on the potential of the control end G of the driving module 10. The first reset module 20 is connected to the control end G of the driving module 10 and configured to transmit a first reset signal Vref1 to the control end G of the driving module 10 in response to a first scan signal Scan1. The data write module 30 is connected to the driving module 10 and configured to transmit a data voltage Data to the driving module 10 in response to a second scan signal Scan2. The first light-emitting control module 40 and the light-emitting element OLED are connected in series between a positive voltage power supply and a second end D of the driving module 10. The first light-emitting control module 40 is turned on in response to a light-emitting control signal EM and is configured to transmit a first power supply signal ELVDD provided from the positive voltage power supply to the second end D of the driving module 10 via the cathode of the light-emitting element OLED. The second light-emitting control module 50 is connected between the first end S of the driving module 10 and a negative voltage power supply and configured to be turned on in response to the light-emitting control signal EM. The storage module 60 is electrically connected to the control end G of the driving module 10 and configured to store the potential of the control end G of the driving module 10.

[0017] For example, a specific connection manner of the multiple functional modules in the pixel circuit may be as follows: The first reset module 20 has a control end connected to the first scan line and accessing the first scan signal Scan1, a first end connected to the first reset signal line and accessing the first reset signal Vref1, and a second end connected to the control end G of the driving module 10. The data writing module 30 has a control end connected to the second scan line and accessing the second scan signal Scan2, a first end connected to the data line and inputting the data voltage Data, a second end connected to the first end S of the driving module 10, a third end connected to the control end G of the driving module 10, and a fourth end connected to the second end D of the driving module 10, and the data writing module 30 is configured to transmit a signal carrying information about the data voltage Data and information about the threshold voltage of the driving module 10 to the control end G of the driving module 10. The first light-emitting control module 40 has a control end connected to the light-emitting control signal line for receiving the light-emitting control signal EM, a first end connected to the first power signal line for receiving the first power signal ELVDD output from the positive voltage power supply, and a second end connected to the anode of the light-emitting element OLED. The cathode of the light-emitting element OLED is connected to the second end D of the driving module 10. The second light-emitting control module 50 has a control end connected to the light-emitting control signal line for receiving the light-emitting control signal EM, a first end connected to the first end S of the driving module 10, and a second end connected to the second power signal line for receiving the second power signal ELVSS output from the negative voltage power supply. The memory module 60 has a first end connected to the control end G of the driving module 10, and a second end connected to a fixed potential signal line for receiving the fixed potential signal V1, thereby maintaining the potential of the control end G of the driving module 10.

[0018] The first and second scanning signals Scan1 and Scan2 and the light emitting control signal EM are all scanning signals that alternate between high and low potentials, and the first and second power supply signals ELVDD and ELVSS, the first reset signal Vref1 and the fixed potential signal V1 are all DC voltage signals with fixed potentials. For example, the first and second power supply signals ELVDD and Vref1 are at high potentials, and the second power supply signal ELVSS is at low potential.

[0019] FIG. 4 is a schematic diagram of the driving time sequence of a pixel circuit according to an embodiment of the present application. Referring to FIGS. 3 and 4, taking the example that the conductive potentials of the multiple functional modules are all high, the driving process of the pixel circuit includes the following: In a gate electrode reset phase T1, the first scanning signal Scan1 is at a high potential, and the second scanning signal Scan2 and the light-emitting control signal EM are at a low potential. The first reset module 20 is conductive and transmits a first reset signal Vref1 to the control end G of the driving module 10. In this phase, the first reset signal Vref1 resets the control end G of the driving module 10, preparing it for writing the next data and ensuring that the driving module 10 is able to conduct in the data writing phase T2.

[0020] In the data writing stage T2, the second scanning signal Scan2 is at a high potential, and the first scanning signal Scan1 and the light emission control signal EM are at a low potential, so that the data writing module 30 is turned on and writes the data voltage Data to the control end G of the driving module 10 via the first end S and the second end D of the driving module 10.

[0021] In the light-emitting stage TE, the light-emitting control signal EM is at a high potential, and the first and second scan signals Scan1 and Scan2 are at a low potential. The first and second light-emitting control modules 40 and 50 are both conductive, connecting the series path between the driving module 10 and the light-emitting element OLED between the positive and negative voltage power supplies. The driving module 10 generates a driving current to drive the light-emitting element OLED to emit light. During this stage, based on the memory function of the memory module 60, the potential of the control end G of the driving module 10 is stably maintained at the potential written in the data writing stage T2. The second power signal ELVSS is transmitted to the first end S of the driving module 10 via the second light-emitting control module 50. Since the potential of the second power signal ELVSS remains unchanged, the potential of the first end S of the driving module 10 also remains unchanged. Therefore, the potential difference between the control end G and the first end S of the driving module 10 is maintained unchanged during the light-emitting stage TE, so that the driving module 10 can stably output a driving current whose magnitude does not change according to the potential difference during the light-emitting stage TE, thereby driving the light-emitting element OLED to emit light stably.

[0022] In the present embodiment, the cathodes of the light-emitting elements OLED are isolated and the cathode potentials of the light-emitting elements OLED can be individually controlled. The cathodes of the light-emitting elements OLED are connected to the pixel circuit. The cathodes of the light-emitting elements OLED are directly or indirectly connected to the second end D of the driving module 10, allowing the first end S of the driving module 10 to be connected to the negative voltage power supply by the second light-emitting control module 50. During the light-emitting phase, the second light-emitting control module 50 is conductive, and the second power signal ELVSS provided by the negative voltage power supply is stably connected to the first end S of the driving module 10, thereby maintaining the potential of the first end S of the driving module 10 unchanged. At the same time, the storage module 60 is provided to store charges and maintain the potential during the light-emitting phase, thereby maintaining the potential of the control end G of the driving module 10 unchanged. Therefore, the pixel circuit according to the embodiment of the present application can control the potentials of the control terminal G and the first terminal S of the driving module 10 to remain unchanged during the light-emitting stage TE, and compared with the related art in which the potentials of the gate electrode and source electrode of the driving transistor both fluctuate during the light-emitting stage, the embodiment of the present application can more easily ensure that the potential difference between the control terminal G and the first terminal S of the driving module 10 remains unchanged, and therefore the driving current output from the driving module 10 remains unchanged, so that the brightness of the light-emitting element OLED during the light-emitting stage remains unchanged, which is advantageous to improving the display uniformity of the display panel. Furthermore, the memory module 60 in the embodiment of the present application does not need to provide a coupling function, but only needs to provide a potential holding function, and the memory module 60 To luminous brightness Therefore, the design requirements for the storage module 60 are lower, and the structure of the storage module 60 and its layout on the display panel can be set more flexibly.

[0023] 5 is a schematic diagram of the circuit structure of another pixel circuit according to an embodiment of the present application. Referring to FIG. 5 and based on the above embodiment, for example, the driving module 10 includes a driving transistor DTFT, whose gate electrode is connected to the control end G of the driving module 10, whose first pole is connected to the first end S of the driving module 10, and whose second pole is connected to the second end D of the driving module 10. In this embodiment, the driving module 10 is configured with a single transistor, which simplifies the structure of the driving module 10 and makes it easier to implement. For example, the driving transistor DTFT has a first pole as its source electrode and a second pole as its drain electrode.

[0024] 5, based on the above embodiment, for example, the first reset module 20 includes a first transistor M1, the gate electrode of which is connected to the first scanning line, the first pole of which is connected to the control terminal G of the driving module 10, and the second pole of which is connected to the first reset signal line. In this embodiment, the first reset module 20 is configured with a single transistor, which simplifies the structure of the first reset module 20 and makes it easier to implement.

[0025] Continuing to refer to FIG. 5 and based on the above embodiment, for example, the data writing module 30 includes a data writing unit 301 and a threshold compensation unit 302. The data writing unit 301 is connected to the first end S of the driving module 10, and is turned on in response to a second scanning signal Scan2, and is configured to transmit a data voltage Data to the first end S of the driving module 10. The threshold compensation unit 302 is connected between the control end G and the second end D of the driving module 10, and is turned on in response to the second scanning signal Scan2, and is configured to perform threshold voltage compensation for the driving module 10.

[0026] For example, the data writing unit 301 includes a second transistor M2, and the threshold compensation unit 302 includes a third transistor M3. The gate electrodes of the second transistor M2 and the third transistor M3 are both connected to the second scan line, the first pole of the second transistor M2 is connected to the data line, and the second pole is connected to the first terminal S of the driving module 10, and the first pole of the third transistor M3 is connected to the control terminal G of the driving module 10, and the second pole is connected to the second terminal D of the driving module 10. In this embodiment, Third transistor M3 is connected between the gate electrode and the second electrode of the drive transistor DTFT. When the second transistor M2 and the third transistor M3 are both turned on in response to the second scan signal Scan2, the gate electrode and the second electrode of the drive transistor DTFT are connected to form a diode connection, and the data voltage Data can be written to the first electrode of the drive transistor DTFT by the second transistor M2 and then written to the gate electrode of the drive transistor DTFT via the drive transistor DTFT and the third transistor M3. When the potential difference between the gate electrode and the first electrode of the drive transistor DTFT is equal to the threshold voltage Vth of the drive transistor DTFT, the drive transistor DTFT is turned off, and the gate electrode potential of the drive transistor DTFT is maintained at Data+Vth, which is equivalent to simultaneously storing the data voltage Data and the threshold voltage information of the drive transistor DTFT. This is advantageous for eliminating the effect of the threshold voltage shift of the drive transistor DTFT on the driving current in the subsequent light-emitting stage and compensating for the effect of the non-uniform threshold voltage of the drive transistor DTFT on the display effect.

[0027] 5 , based on the above embodiment, for example, the first light-emitting control module 40 includes a fourth transistor M4, the gate electrode of which is connected to the light-emitting control signal line, and the fourth transistor M4 is connected in series between the light-emitting element OLED, the positive voltage power supply, and the second terminal D of the driving module 10. For example, the fourth transistor M4 has a first terminal to which the first power supply signal ELVDD is connected, a second terminal connected to the anode of the light-emitting element OLED, and a cathode connected to the second terminal D of the driving module 10. In this embodiment, the first light-emitting control module 40 is configured with one transistor, which simplifies the structure of the first light-emitting control module 40 and makes it easier to implement.

[0028] 5 , based on the above embodiment, for example, the second light-emitting control module 50 includes a fifth transistor M5, the fifth transistor M5 having a gate electrode connected to the light-emitting control signal line, a first pole connected to the first terminal S of the driving module 10, and a second pole connected to a negative voltage power supply. In this embodiment, the second light-emitting control module 50 is configured with only one transistor, which simplifies the structure of the second light-emitting control module 50 and makes it easier to implement.

[0029] In accordance with the above embodiment, for example, the memory module 60 has a first end connected to the control end G of the driving module 10 and a second end to which at least one fixed potential signal can be applied, thereby providing a potential holding function. As shown in FIG. 5 , the memory module 60 is exemplarily connected to a fixed potential signal, and includes a memory unit 610 having a first end connected to the control end G of the driving module 10 and a second end to which the fixed potential signal V1 can be applied. For example, the memory unit 610 may include a capacitor Cst, the first end of which is the first end of the memory unit 610 and the second end of which is the second end of the memory unit 610. In this embodiment, the memory unit 610 is configured with a capacitor Cst, which simplifies the structure of the memory unit 610 and makes it easier to implement.

[0030] Continuing to refer to FIG. 5 , based on the above embodiment, for example, the pixel circuit further includes a second reset module 70 electrically connected to the cathode of the light-emitting element OLED and configured to transmit a second reset signal Vref2 to the cathode of the light-emitting element OLED in response to a third scan signal Scan3. By providing the second reset module 70 in this embodiment, the second reset signal Vref2 can be used to initialize the cathode of the light-emitting element OLED before the light-emitting step, thereby eliminating any residual charge of the light-emitting element OLED from the previous frame, which is beneficial to improving contrast. For example, the second reset signal Vref2 can be a DC voltage signal having a low potential.

[0031] For example, the second reset module 70 may include a sixth transistor M6, the gate electrode of the sixth transistor M6 is connected to the third scan line, and the third scan signal Scan3 is accessed; the first electrode of the sixth transistor M6 is connected to the cathode of the light-emitting element OLED; M6 The second reset signal line is connected to the second pole of the second reset module 70, and the second reset signal Vref2 is accessed. In this embodiment, the second reset module 70 includes one transistor, which simplifies the structure of the second reset module 70 and makes it easier to implement.

[0032] Referring to FIG. 5 , for example, the plurality of transistors in the pixel circuit may all be N-type transistors to form an all-N-type pixel circuit. Based on the characteristics of N-type transistors having low leakage current, this is advantageous for improving the display uniformity of the display panel, making the pixel circuit particularly suitable for medium / large-sized products, and for realizing low-frequency display of the display panel.

[0033] 6 is a schematic diagram of a driving time sequence of another pixel circuit according to an embodiment of the present application. In conjunction with FIGS. 5 and 6, taking the pixel circuit as an all-N-type pixel circuit as an example, the driving process of the pixel circuit may include the following: In a cathode reset stage T0, the third scan signal Scan3 is at a high potential, and the first scan signal Scan1, the second scan signal Scan2, and the light-emitting control signal EM are all at a low potential. The sixth transistor M6 is conductive, and the second reset signal Vref2 is transmitted to the cathode of the light-emitting element OLED through the sixth transistor M6, resetting the cathode of the light-emitting element OLED to eliminate residual charges from the previous frame and favoring contrast improvement. At the same time, since the gate electrode of the drive transistor DTFT maintains the potential of the previous frame, the drive transistor DTFT remains conductive at this stage, and the second reset signal Vref2 is transmitted to the second pole of the drive transistor DTFT via the sixth transistor M6, and then to the first pole of the drive transistor DTFT via the drive transistor DTFT, resetting the first and second poles of the drive transistor DTFT, which is advantageous to correct the threshold voltage shift of the drive transistor DTFT and improving the phenomenon of low brightness in the first frame when the grayscale changes.

[0034] In the gate electrode reset stage T1, the first scanning signal Scan1 is at a high potential, the second scanning signal Scan2, the third scanning signal Scan3, and the light emission control signal EM are all at a low potential, the first transistor M1 is conductive, and the first reset signal Vref1 is transmitted to the gate electrode of the driving transistor DTFT through the first transistor M1, resetting the gate electrode of the driving transistor DTFT and changing the gate electrode of the driving transistor DTFT to a high potential.

[0035] During the data write phase T2, the second scan signal Scan2 is at a high potential, and the first scan signal Scan1, the third scan signal Scan3, and the light-emitting control signal EM are all at a low potential. The second transistor M2 and the third transistor M3 are conductive, and the data voltage Data is transmitted to the gate electrode of the drive transistor DTFT via the second transistor M2, the first and second poles of the drive transistor DTFT, and the third transistor M3. During the data write process, the gate electrode potential Vg of the drive transistor DTFT continues to decrease from the high potential of the first reset signal Vref1. When the potential difference between the gate electrode and the first pole of the drive transistor DTFT reaches Vgs=Vth, the drive transistor DTFT is turned off. At this time, the gate electrode potential of the drive transistor DTFT does not change and remains at Vg=Data+Vth, where Vth is the threshold voltage of the drive transistor DTFT.

[0036] In the cathode precharge stage T3, the third scan signal Scan3 is at a high potential, and the first scan signal Scan1, the second scan signal Scan2, and the light emitting control signal EM are all at a low potential. The sixth transistor M6 is turned on, and the second reset signal Vref2 precharges the cathode of the light emitting element OLED through the sixth transistor M6. This increases the lighting speed of the light emitting element OLED at low brightness, and reduces flicker caused by slow lighting at low brightness due to the low mobility of the IGZO driving transistor. At the same time, it is possible to further reduce the display non-uniformity at low brightness.

[0037] JPEG0007810815000001.jpg94169

[0038] In the pixel circuit according to the embodiment of the present application, the light emitting element OLED is disposed between two light emitting control modules, for example, between the first light emitting control module 40 and the driving module 10. Therefore, during a time period when the light emitting control signal EM is at a low potential, both of the two light emitting control modules are shut off to cut off the power supply source for the light emitting element OLED, so that the light emitting element OLED can be controlled to be completely turned off, effectively preventing the false lighting phenomenon of the light emitting element OLED caused by leakage current of the sixth transistor M6, and at the same time, the range of the initialization voltage of the cathode of the light emitting element OLED (i.e., the second reset signal Vref2) can be greatly widened, so that the second reset signal Vref2 can provide a sufficiently low potential to the cathode of the light emitting element OLED, eliminating the need to worry about the light emitting element OLED being unable to be turned off and displaying a black screen. In light of this, by setting the cathode reset stage T0, it is possible to completely reset the state of the driving transistor DTFT before data is written, which is advantageous for improving situations such as reduced brightness in the first frame, low-frequency flicker, and frequency switching flicker. Furthermore, by resetting the cathode potential of the light-emitting element OLED, it is possible to eliminate residual charge from the cathode of the light-emitting element OLED from the previous frame and improve contrast. Furthermore, by setting the cathode precharge stage T3, it is possible to precharge the cathode of the light-emitting element OLED before light emission. In particular, during low-brightness periods, the cathode of the light-emitting element OLED is precharged to a low potential, which increases the lighting speed of the light-emitting element OLED and improves low-frequency flicker caused by a slow lighting speed of the light-emitting element OLED due to the low mobility of the IGZO driving transistor, and improves brightness non-uniformity caused by non-uniform lighting speeds during low-brightness periods.

[0039] In the above embodiment, the circuit connection relationship and operation principle of the pixel circuit are explained in connection with one specific pixel circuit. Hereinafter, the film layer structure of the pixel circuit will be specifically explained.

[0040] FIG. 7 is a schematic diagram of the film layer structure of a pixel circuit according to an embodiment of the present application. FIG. 7 shows a specific layout of one pixel circuit in the film layers of a display panel. FIG. 7 mainly shows the series structure of the driving transistor DTFT and the light-emitting element OLED between the positive voltage power supply and the negative voltage power supply. The structures of the fourth transistor M4 and the fifth transistor M5 are omitted. In addition, FIG. 7 also shows the structure of the capacitor Cst.

[0041] 7 , for example, the display panel includes an active layer 82, a gate insulating layer 83, a first metal layer 84, a capacitor intermediate dielectric layer 85, a second metal layer 86, an interlayer insulating layer 87, an organic insulating layer 88, a third metal layer 89, a planarization layer 90, an anode layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer 96, an organic encapsulation layer 97, and a second inorganic encapsulation layer 98, which are sequentially stacked on a substrate 81. The anode 91 of the light-emitting element OLED is disposed on the anode layer, the light-emitting functional related film layer 93 is disposed on the light-emitting functional layer, and the cathode 94 is disposed on the cathode layer. The anodes 91 of the light-emitting element OLEDs are separated from one another by pixel definition layers 92, and the light-emitting functional related film layers 93 and the cathodes 94 of the light-emitting element OLEDs are separated from one another by isolation structures 95.

[0042] The substrate 81 is configured to support multiple upper film layers and may be made of an organic material such as polyimide (PI) or an inorganic material such as glass. The active layer 82 is configured to form the channel portion and source / drain regions of the transistor in the pixel circuit. Its material may be, for example, a-Si, P-Si, IGZO, etc., and may be any material capable of forming a PN junction. The gate insulating layer 83 is configured to isolate the active layer 82 from the first metal layer 84 and may be made of an inorganic material such as silicon nitride or silicon oxide. The capacitor intermediate dielectric layer 85 is configured to isolate the first metal layer 84 from the second metal layer 86 and may be made of an inorganic material such as silicon nitride. The interlayer insulating layer 87 and the organic insulating layer 88 are both configured to isolate the second metal layer 86 from the third metal layer 89. The interlayer insulating layer 87 may be made of a stack of silicon nitride and silicon oxide. The planarization layer 90 is configured to separate the third metal layer 89 from the anode layer, planarize the surface film layers to optimize pixel light output, and flatten the subsequent light-emitting element OLED film layers, and can be made of organic materials. The material of the metal layer can be a metal material such as molybdenum or titanium-aluminum-titanium. The pixel definition layer 92 is configured to define the size of the pixel aperture, and can be made of inorganic materials. The first inorganic sealing layer 96, the organic sealing layer 97 (e.g., an inkjet printing layer), and the second inorganic sealing layer 98 are configured to form sealing film layers of the display panel.

[0043] Wherein, the isolation structures 95 may be fabricated on the side of the pixel definition layer 92 away from the substrate 81 before depositing the light-emitting functional layers, and the isolation structures 95 corresponding to the light-emitting element OLEDs may be provided to surround the pixel openings corresponding to the light-emitting element OLEDs, and the isolation structures 95 have a certain height so that, when the light-emitting functional layers and the cathode layer are deposited, the protruding isolation structures 95 separate the light-emitting functionally related film layers 93 between different light-emitting element OLEDs and isolate the electrical connection between the cathodes 94 of adjacent light-emitting element OLEDs, ensuring that the cathode potentials of the plurality of light-emitting element OLEDs can be individually controlled. For example, the isolation structures 95 may have a structure that is wide at the top and narrow at the bottom, for example, a cross-sectional shape of an inverted trapezoid, thereby ensuring that the cathodes 94 of adjacent light-emitting element OLEDs are isolated from each other when the cathode layer is fabricated.

[0044] The following describes, in conjunction with Figure 7, the main components of the pixel circuit after the dashed-line frame and the arrangement of the signal lines in the film layers of the display panel. The fourth transistor M4 and the fifth transistor M5 are omitted from Figure 7. In actual manufacturing, the first electrode MS of the driving transistor DTFT can be connected to the second power signal line LVSS via the fifth transistor M5. The second electrode MD of the driving transistor DTFT can be directly connected to the cathode 94 of the light-emitting element OLED, or can be connected to the cathode 94 of the light-emitting element OLED via the fourth transistor M4.

[0045] In one embodiment, for example, the channel region, source region, and drain region of the driving transistor DTFT are all provided in the active layer 82, and the gate electrode MG of the driving transistor DTFT is provided in the first metal layer 84, and its projection in the thickness direction of the display panel covers the channel region of the driving transistor DTFT. The first pole MS and second pole MD of the driving transistor DTFT are all provided in the third metal layer 89, and DTFT The projections of the first pole MS and the second pole MD in the thickness direction of the display panel respectively cover the source region and the drain region of the driving transistor DTFT, and the driving transistor DTFTThe first pole MS and the second pole MD can be connected to the source region and the drain region of the drive transistor DTFT by via holes, respectively.

[0046] The fixed potential signal is provided from a fixed potential signal line LV1, which may be disposed on the second metal layer 86 as shown in FIG. 7 or on another conductive film layer, such as the third metal layer 89. The projection of the fixed potential signal line LV1 in the thickness direction of the display panel at least partially overlaps with the gate electrode MG of the drive transistor DTFT. The gate electrode MG of the drive transistor DTFT can also serve as the first plate C1 of the capacitor Cst, thereby connecting the first end of the capacitor Cst to the gate electrode MG of the drive transistor DTFT. The overlapping portion of the fixed potential signal line LV1 and the gate electrode MG of the drive transistor DTFT can also serve as the second plate C2 of the capacitor Cst, thereby connecting the second end of the capacitor Cst to the fixed potential signal line LV1. The first plate C1 and the second plate C2 face each other to form the capacitor Cst, and the facing area between the first plate C1 and the second plate C2 can be set according to actual needs.

[0047] The isolation structure 95 may include a conductive material layer, and the cathode 94 of the light-emitting element OLED contacts the isolation structure 95 and is electrically connected to the corresponding pixel circuit, for example, to the second pole MD of the driving transistor DTFT, through the isolation structure 95. The pixel circuit and the light-emitting element OLED may both be arranged in an array in the display panel. When the isolation structure 95 includes a conductive material layer, one isolation structure 95 may surround the periphery of each light-emitting element OLED, thereby isolating two adjacent light-emitting elements OLEDs from each other by two isolation structures 95. The two isolation structures 95 are insulated from each other, for example, by an organic sealing layer 97, thereby reliably blocking electrical connection between the cathodes 94 of adjacent light-emitting elements OLEDs. Before fabricating the isolation structure 95, a through-hole may be first formed in the pixel definition layer 92 and the planarization layer 90 to expose the surface of the second pole MD of the driving transistor DTFT, so as to achieve electrical connection between the isolation structure 95 and the second pole MD of the driving transistor DTFT. The isolation structure 95 may then be fabricated in the pixel definition layer 92. The upper surface of the isolation structure 95 may be a flat surface anywhere. Alternatively, the isolation structure 95 may be lower in height corresponding to the through-hole region than in other regions as long as the cathodes 94 of the adjacent light-emitting elements OLEDs can be cut, and the height difference of the top surface of the isolation structure 95 itself can be filled in flat by the organic encapsulation layer 97. Furthermore, the cross-sectional shape of the isolation structure 95 can be understood as the cross-sectional shape of the part of the isolation structure 95 located above the through-hole, and this cross-sectional shape itself does not include the through-hole part, and the shape and size of the through-hole itself can be arbitrarily set according to the manufacturing process and actual needs.

[0048] Continuing to refer to FIG. 7 , for example, a positive voltage power supply is connected to the pixel circuit via a first power signal line LVDD, for example, connected to the anode 91 of the light-emitting element OLED. The first power signal line LVDD may be provided in a conductive film layer located below the light-emitting functional layer, for example, in the second metal layer 86, the third metal layer 89, or the anode layer. FIG. 7 shows the first power signal line LVDD provided in the third metal layer 89 as an example. Furthermore, a negative voltage power supply is connected to the pixel circuit via a second power signal line LVSS, for example, connected to the first electrode MS of the drive transistor DTFT. The second power signal line LVSS may be provided in a conductive film layer located below the light-emitting functional layer, for example, in the second metal layer 86, the third metal layer 89, or the anode layer. FIG. 7 shows the second power signal line LVSS provided in the third metal layer 89 as an example. The overlapping portion of the second power signal line LVSS and the source region of the drive transistor DTFT can also serve as the first electrode MS of the drive transistor DTFT.

[0049] Based on the film layer structure in FIG. 7, starting from the first power signal line LVDD, the first power signal line LVDD→the anode 91 of the light emitting element OLED→the light emitting function of the light emitting element OLED. Associated membranes A current path can be provided from the layer 93 to the cathode 94 of the light-emitting element OLED, the isolation structure 95, the second pole MD of the driving transistor DTFT, the channel region of the driving transistor DTFT, the first pole MS of the driving transistor DTFT, and the second power signal line LVSS.

[0050] As can be seen from the above, in the pixel circuit according to the embodiment of the present application, the cathodes 94 of the plurality of light-emitting elements OLED are separated by the isolation structure 95, which is wide at the top and narrow at the bottom, thereby ensuring that the potentials of the cathodes 94 of the plurality of light-emitting elements OLED can be individually controlled. Furthermore, the cathode 94 of the light-emitting element OLED is connected to the second electrode MD of the N-type driving transistor DTFT by the isolation structure 95, the first electrode MS of the driving transistor DTFT is connected to the second power signal line LVSS, and the gate electrode MG of the driving transistor DTFT is connected to a capacitor Cst. This ensures that the potential difference Vgs between the gate electrode and the first electrode of the driving transistor DTFT (i.e., the gate-source voltage difference) remains constant during the light-emitting phase, thereby ensuring that the light-emitting current remains constant. Furthermore, because the cathodes 94 of the plurality of light-emitting elements OLED are separated from one another, only the current of a single pixel circuit is carried on the cathode 94 of each light-emitting element OLED, and the main current of the entire panel is carried by two power signal wirings, the first power signal line LVDD and the second power signal line LVSS. Meanwhile, the first power signal line LVDD and the second power signal line LVSS are both metal wirings provided under the light-emitting functional layer, and do not block the light-emitting surface of the light-emitting element OLED, so the transparency of the two power signal lines does not affect the light emission of the light-emitting element OLED. Therefore, compared with the fully transparent cathode structure in the related art, the film layer structure according to the embodiment of the present application does not limit the materials of the two power signal lines by transparency, and can be manufactured using materials with lower resistance according to needs, thereby reducing the voltage drop (IR drop) of the power signal lines and reducing power consumption.

[0051] Considering the above embodiment, for example, the film layer structure of multiple transistors not shown in FIG. 7 may be distributed as follows: The active layer 82 may further include channel regions, source regions, and drain regions of the first to sixth transistors M1 to M6. The first metal layer 84 may further include a first scan line, a second scan line, a third scan line, and a light-emission control signal line. The overlapping portions of the active layer 82 with the multiple scan lines and light-emission control signal lines form corresponding transistors. The multiple scan lines and light-emission control signal lines also serve as gate electrodes for multiple transistors. The portions of the active layer 82 that are covered by the scan lines or light-emission control signal lines form the channel regions of the transistors, and both sides of the channel region are the source and drain regions, respectively. The source region of a transistor corresponds to its first pole, and the drain region corresponds to its second pole, or the source region of a transistor corresponds to its second pole, and the drain region corresponds to its first pole. The second metal layer 86 may further include a first reset signal line and a second reset signal line. The third metal layer 89 may further include a data line.

[0052] The above embodiment provides a detailed explanation of the structure and operation of an all-N type pixel circuit based on the pixel circuit in FIG. 5, but this is not intended to limit the scope of the present application. In other embodiments, the pixel circuit may have a different circuit structure and, correspondingly, a different film layer structure. Some adjustment methods are described below.

[0053] 8 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present application. Referring to FIG. 8, in one embodiment, for example, the first power supply signal ELVDD may also be used as the first reset signal Vref1. Correspondingly, the first power supply signal line LVDD may also be used as the first reset signal line, thereby eliminating the need for a separate first reset signal line in the film layer structure.

[0054] The first power supply signal ELVDD and the first reset signal Vref1 are both high-potential signals, and when they are transmitted through different signal lines, the first reset signal Vref1 can be provided from a separate power supply, and therefore the first reset signal Vref1 has an adjustable voltage, thereby providing the gate electrode potential of the driving transistor DTFT according to needs in the gate electrode reset stage, which is beneficial to optimizing the display effect of the product. When the first power supply signal ELVDD is also used as the first reset signal Vref1, the number of signal lines in the display panel can be reduced, which is beneficial to reducing the space required for pixel wiring, which is beneficial to the design of products with high pixel density, and also reduces the number of output channels required for the driving chip.

[0055] In the above embodiment, for example, at least one of the first power supply signal ELVDD, the second power supply signal ELVSS, the first reset signal Vref1, and the second reset signal Vref2 may also serve as the fixed potential signal V1. Accordingly, at least one of the first power supply signal line LVDD, the second power supply signal line LVSS, the first reset signal line, and the second reset signal line may also serve as the fixed potential signal line LV1. This eliminates the need for a separate fixed potential signal line LV1 in the display panel, which is advantageous in reducing the space required for pixel wiring. When using another signal line to serve as the fixed potential signal line LV1, a second electrode C2 of the capacitor Cst may be separately provided in the second metal layer 86 at a position opposite the gate electrode MG of the drive transistor DTFT, and the second electrode C2 may be connected to the corresponding signal line using a via hole, a jumper, or the like. For example, as shown in FIG. 8, the second power supply signal ELVSS may also serve as the fixed potential signal V1.

[0056] In the above embodiment, the storage module 60 is illustrated as having one storage unit 610 and is accessed by one fixed potential signal. However, this does not limit the present application. In other embodiments, for example, as shown in FIG. 9, the storage module 60 may include at least two storage units (two storage units are illustrated as an example). The first terminals of the multiple storage units are all connected to the control terminal G of the driving module 10, and different fixed potential signals are accessed at their second terminals. For example, as shown in FIG. 9, the first storage unit 611 may include a first capacitor Cst1, the second terminal of which is accessible to the second power supply signal ELVSS, and the second storage unit 612 may include a second capacitor Cst2, the second terminal of which is accessible to the first power supply signal ELVDD. In this embodiment, the storage module 60 includes multiple storage units, and multiple fixed potential signals are connected to the multiple storage units, which is advantageous for flexibly realizing a larger capacity design and improving the potential retention capability of the storage module 60.

[0057] In the above embodiment, a structure in which a positive voltage power supply is connected to the first terminal of the first light-emitting control module 40 and the driving module 10 is connected to the cathode of the light-emitting element OLED is shown as an example, but this is not intended to limit the present application. In another embodiment, for example, as shown in Fig. 9, a positive voltage power supply may be connected to the anode of the light-emitting element OLED, the first terminal of the first light-emitting control module 40 may be connected to the cathode, and the second terminal D of the driving module 10 may be connected to the second terminal of the first light-emitting control module 40. The second reset module 70 is still electrically connected to the cathode of the light-emitting element OLED.

[0058] FIG. 10 is a schematic diagram of a driving time sequence of yet another pixel circuit according to an embodiment of the present application. The pixel circuit shown in FIG. 9 can be driven using the driving time sequence shown in FIG. 10. In combination with FIGS. 9 and 10, the driving process of the pixel circuit includes the following: In a gate electrode reset stage T1, the first scanning signal Scan1 is at a high potential, and the second scanning signal Scan2, the third scanning signal Scan3, and the light-emitting control signal EM are all at a low potential. The first transistor M1 is conductive, and the first reset signal Vref1 is transmitted to the gate electrode of the driving transistor DTFT through the first transistor M1, resetting the gate electrode of the driving transistor DTFT.

[0059] During the data writing stage T2, the second scan signal Scan2 and the third scan signal Scan3 are at high potentials, and the first scan signal Scan1 and the light-emitting control signal EM are at low potentials. The second transistor M2 and the third transistor M3 are conductive, and the data voltage Data is transmitted to the gate electrode of the driving transistor DTFT via the second transistor M2, the first and second poles of the driving transistor DTFT, and the third transistor M3. The sixth transistor M6 is conductive, and the second reset signal Vref2 resets the cathode of the light-emitting element OLED via the sixth transistor M6.

[0060] In the light-emitting stage TE, the light-emitting control signal EM is at a high potential, the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all at a low potential, the fourth transistor M4 and the fifth transistor M5 are all conductive, and the driving transistor DTFT generates a driving current to drive the light-emitting element OLED to emit light.

[0061] 10, the pulses of the third scan signal Scan3 and the second scan signal Scan2 overlap, i.e., the cathode reset of the light-emitting element OLED and the data writing process of the driving transistor DTFT are performed simultaneously. However, the above time sequence is not intended to limit the present application. In other embodiments, for example, before the light-emitting step TE, the first light-emitting control module 40 remains cut off, and the potential of the second reset signal Vref2 is not transmitted to the second electrode of the driving transistor DTFT. Therefore, the cathode reset step of the light-emitting element OLED may be performed at any time during the time period when the light-emitting control signal EM is at a low potential, for example, simultaneously with the gate electrode reset step T1.

[0062] 11 is a schematic diagram of the circuit structure of another pixel circuit according to an embodiment of the present application. Referring to FIG. 11 and based on the above embodiment, for example, in order to simplify the wiring of the display panel, the second scanning signal Scan2 may also be used as the third scanning signal Scan3, and the pixel circuit may still adopt the driving time sequence shown in FIG. 4. Alternatively, in order to simplify the wiring of the display panel, the first scanning signal Scan1 may also be used as the third scanning signal Scan3, and in this case, the pixel circuit may still adopt the driving time sequence shown in FIG. 4.

[0063] Based on the above, the embodiment of the present application provides an all-N-type transistor pixel driving circuit that is applied to isolate the cathodes of multiple light-emitting elements (OLEDs) and can individually control the cathode potential. To verify the effect of the pixel circuit in improving display uniformity, the applicant simulated the pixel circuit structure of the related art shown in Figure 1 and the pixel circuit structure of the embodiment of the present application shown in Figure 8, and collected the changes in the potential of key nodes in the pixel circuit during the light emission process. The simulation results can be seen in Figures 12 and 13.

[0064] 12, when simulating a pixel circuit in the related art, the gate electrode potential VG, first electrode potential VS, and second electrode potential VD of the drive transistor are respectively sampled, and the anode potential VA of the light emitting element is also sampled. As can be seen from the simulation results in Fig. 12, in the related art, the potential difference is maintained using capacitor coupling, so the gate electrode potential VG and first electrode potential VS of the drive transistor DTFT rise synchronously for a long time after the start of the light emitting stage TE. For a long time after the start of the light emitting stage TE, the gate electrode potential VG and first electrode potential VS of the drive transistor DTFT are both constantly changing, and although the capacitor coupling keeps the voltage difference Vgs as constant as possible, the voltage difference cannot be maintained completely stably.

[0065] Referring to FIG. 13, when simulating the pixel circuit according to the embodiment of the present application, the gate electrode potential VG, the first electrode potential VS, and the second electrode potential VD of the driving transistor are respectively sampled, and further, the cathode potential VC of the light emitting element is sampled. As can be seen from the simulation result of FIG. 13, the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT are kept constant and unchanged from the light emitting stage TE, so the pixel circuit according to the embodiment of the present application can reliably maintain the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT.

[0066] 14, in order to verify the compensation effect of the pixel circuit according to the embodiment of the present application in response to the non-uniformity of the threshold voltage of the drive transistor DTFT, the applicant further simulated the percentage of luminance change when the threshold voltage Vth of the drive transistor DTFT fluctuated by ±0.5V at grayscales W255, W128, and W64 based on the pixel circuit according to the embodiment of the present application. As can be seen, even when Vth fluctuated by ±0.5V at 64 grayscales, the pixel circuit structure can ensure that the luminance change is within 3%, indicating that the pixel circuit can effectively compensate for the non-uniformity of the threshold voltage Vth of the drive transistor DTFT and reliably improve the display uniformity of the display panel.

[0067] The present invention also provides a display panel including a plurality of pixel circuits according to any of the present invention, and having corresponding beneficial effects. For example, the plurality of pixel circuits may be arrayed in a display area of ​​the display panel. Scanning signals and light-emitting control signals required for the pixel circuits may be provided via corresponding signal lines by corresponding gate electrode driving circuits provided in a non-display area of ​​the display panel, and data voltages required for the pixel circuits may be provided via data lines by a driving chip.

[0068] In the examples of pixel circuits, the film layer structures of the display panels of different pixel circuits have been specifically explained, but these film layer structures may all be considered to be the film layer structures of the display panels according to the examples of the present application, and overlapping content will not be repeated here.

[0069] For example, the display panel may include an active layer, a first metal layer, a second metal layer, a third metal layer, an anode layer, a light-emitting functional layer, and a cathode layer, which are sequentially stacked, wherein the channel region, source region, and drain region of the driving transistor are all located in the active layer, the gate electrode of the driving transistor is located in the first metal layer and its projection in the thickness direction of the display panel covers the channel region of the driving transistor, the first pole and second pole of the driving transistor are both located in the third metal layer and are connected to the source region and drain region of the driving transistor, respectively, a fixed potential signal is provided from a fixed potential signal line located in the second metal layer or the third metal layer and its projection in the thickness direction of the display panel at least partially overlaps with the gate electrode of the driving transistor, and the overlapping portion of the fixed potential signal line and the gate electrode of the driving transistor forms a memory module. The positive voltage power supply may be connected to the pixel circuit via a first power signal line, and the negative voltage power supply may be connected to the pixel circuit via a second power signal line, and both the first power signal line and the second power signal line may be provided in a conductive film layer below the light-emitting functional layer, such as the second metal layer, the third metal layer, or the anode layer. The display panel further includes a plurality of isolation structures surrounding the plurality of light-emitting elements and configured to isolate the cathodes of adjacent light-emitting elements. Exemplarily, the isolation structures may include a conductive material layer, the cathodes of the light-emitting elements contact the isolation structures and are electrically connected to the corresponding pixel circuits via the isolation structures, and the cross-sectional shape of the isolation structures may be an inverted trapezoid.

[0070] It should be understood that various types of flows shown above can be used, and steps can be rearranged, added, or deleted. For example, multiple steps described herein can be performed in parallel, sequentially, or in a different order, and this specification is not limited thereto, as long as the desired results of the technical aspects of the present application are achieved.

Claims

1. a drive module configured to generate a drive current based on a potential at a control end thereof; a first reset module connected to the control end of the driving module, configured to respond to a first scanning signal and transmit a first reset signal to the control end of the driving module; a data writing module connected to the driving module and configured to transmit a data voltage to the driving module in response to a second scanning signal; a first light-emitting control module connected in series between the light-emitting element, a positive voltage power supply, and the second end of the driving module, and configured to be turned on in response to a light-emitting control signal and to transmit a first power signal provided by the positive voltage power supply to the second end of the driving module via the cathode of the light-emitting element; a second light-emitting control module connected between the first end of the driving module and a negative voltage power supply, and configured to be conductive in response to the light-emitting control signal; a memory module electrically connected to the control end of the driving module and configured to store the potential of the control end of the driving module; the first light-emitting control module has a first terminal connected to the positive voltage power supply, a second terminal connected to the anode of the light-emitting element, and a second terminal connected to the cathode of the light-emitting element; Pixel circuit.

2. The memory module includes a memory unit that receives a fixed potential signal, a first end of which is connected to a control end of the driving module, and a second end of which is connected to the fixed potential signal; Alternatively, the storage module includes at least two storage units, each of which is accessed by at least two fixed potential signals, and each of which is connected to the control end of the driving module at a first end, and each of which is accessed by a different fixed potential signal at a second end; The pixel circuit of claim 1 .

3. The storage unit comprises a capacitor having a first end connected to the first end of the storage unit and a second end connected to the second end of the storage unit; and / or at least one of a first power supply signal provided from the positive voltage power supply, a second power supply signal provided from the negative voltage power supply, and the first reset signal is also used as the fixed potential signal; The pixel circuit of claim 2 .

4. The driving module comprises a driving transistor, the gate electrode of which is connected to the control end of the driving module, the first pole of which is connected to the first end of the driving module, and the second pole of which is connected to the second end of the driving module; the first reset module includes a first transistor, the gate electrode of which is connected to a first scanning line, the first pole of which is connected to a control end of the driving module, and the second pole of which is connected to a first reset signal line; The data writing module includes: a data writing unit connected to the first end of the driving module, the data writing unit being turned on in response to a second scanning signal and configured to transmit a data voltage to the first end of the driving module; and a threshold compensation unit connected between the control end and the second end of the driving module, the threshold compensation unit being turned on in response to the second scanning signal and configured to perform threshold voltage compensation for the driving module, wherein the data writing unit includes a second transistor having a gate electrode connected to the second scanning line, a first pole connected to a data line, and a second pole connected to the first end of the driving module; and the threshold compensation unit includes a third transistor having a gate electrode connected to the second scanning line, a first pole connected to the control end of the driving module, and a second pole connected to the second end of the driving module; the first light-emitting control module includes a fourth transistor, the gate electrode of which is connected to a light-emitting control signal line, and the fourth transistor is connected in series between the light-emitting element, the positive voltage power supply, and the second end of the driving module; the second light-emitting control module includes a fifth transistor, the fifth transistor having a gate electrode connected to a light-emitting control signal line, a first electrode connected to a first end of the driving module, and a second electrode connected to the negative voltage power supply; The pixel circuit of claim 1 .

5. A first power supply signal provided from the positive voltage power supply is also used as the first reset signal. The pixel circuit of claim 1 .

6. a second reset module electrically connected to the cathode of the light-emitting element, configured to transmit a second reset signal to the cathode of the light-emitting element in response to a third scanning signal; The pixel circuit of claim 1 .

7. The second reset module includes a sixth transistor having a gate electrode connected to a third scanning line, a first pole connected to a cathode of the light-emitting element, and a second pole connected to a second reset signal line; and / or, the memory module is accessed by at least one fixed potential signal, and the second reset signal is also used as one of the fixed potential signals; The pixel circuit of claim 6.

8. The first reset module is configured to be conductive in response to the first scanning signal during a gate electrode reset stage, and to employ the first reset signal to reset the control end of the driving module; the data writing module is configured to be turned on in response to the second scanning signal during a data writing stage and transmit the data voltage to the driving module; The second reset module is configured to be turned on in response to the third scanning signal in a cathode precharge step, and to precharge the cathode of the light-emitting element by using the second reset signal; The first light-emitting control module and the second light-emitting control module are configured to be conductive in response to the light-emitting control signal, so that in a light-emitting stage, the driving module generates a driving current based on the potential of its control end to drive the light-emitting element to emit light. The pixel circuit of claim 6.

9. The second reset module is further configured to be conductive in response to the third scanning signal before the gate electrode reset step, and to employ the second reset signal to reset the cathode of the light-emitting element, the first end and the second end of the driving module. The pixel circuit of claim 8 .

10. A drive module configured to generate a drive current based on the potential of its control end; a first reset module connected to the control end of the driving module, configured to respond to a first scanning signal and transmit a first reset signal to the control end of the driving module; a data writing module connected to the driving module and configured to transmit a data voltage to the driving module in response to a second scanning signal; a first light-emitting control module connected in series between the light-emitting element, a positive voltage power supply, and the second end of the driving module, and configured to be turned on in response to a light-emitting control signal and to transmit a first power signal provided by the positive voltage power supply to the second end of the driving module via the cathode of the light-emitting element; a second light-emitting control module connected between the first end of the driving module and a negative voltage power supply, and configured to be conductive in response to the light-emitting control signal; a memory module electrically connected to the control end of the driving module and configured to store the potential of the control end of the driving module; a second reset module electrically connected to the cathode of the light-emitting element and configured to transmit a second reset signal to the cathode of the light-emitting element in response to a third scanning signal; The light emitting element has an anode connected to the positive voltage power supply, a cathode connected to a first end of the first light emitting control module, and a second end of the first light emitting control module connected to a second end of the driving module; The first reset module is configured to be turned on in response to the first scanning signal in a gate electrode reset stage, and to use the first reset signal to reset the control end of the driving module; the data writing module is configured to be turned on in response to the second scanning signal during a data writing stage and transmit the data voltage to the driving module; the second reset module is configured to be turned on in response to the second scanning signal during at least one of the gate electrode reset step and the data writing step, and to reset the cathode of the light-emitting element using the second reset signal; The first light-emitting control module and the second light-emitting control module are configured to be conductive in response to the light-emitting control signal, so that in a light-emitting stage, the driving module generates a driving current based on the potential of its control end to drive the light-emitting element to emit light; the second reset module is turned on during the data writing step, and the second scanning signal is also used as the third scanning signal; Pixel circuit.

11. The memory module includes a memory unit to which a fixed potential signal is accessed, a first end of which is connected to a control end of the drive module, and a second end of which is accessed by the fixed potential signal; Alternatively, the storage module includes at least two storage units, each of which is accessed by at least two fixed potential signals, and each of which is connected to the control end of the driving module at a first end, and each of which is accessed by a different fixed potential signal at a second end; The pixel circuit of claim 10.

12. The storage unit comprises a capacitor having a first end connected to the first end of the storage unit and a second end connected to the second end of the storage unit; and / or at least one of a first power supply signal provided from the positive voltage power supply, a second power supply signal provided from the negative voltage power supply, and the first reset signal is also used as the fixed potential signal; The pixel circuit of claim 11.

13. The drive module comprises a drive transistor having a gate electrode connected to a control end of the drive module, a first pole connected to a first end of the drive module, and a second pole connected to a second end of the drive module; the first reset module includes a first transistor, the gate electrode of which is connected to a first scanning line, the first pole of which is connected to a control end of the driving module, and the second pole of which is connected to a first reset signal line; The data writing module includes: a data writing unit connected to the first end of the driving module, the data writing unit being turned on in response to a second scanning signal and configured to transmit a data voltage to the first end of the driving module; and a threshold compensation unit connected between the control end and the second end of the driving module, the threshold compensation unit being turned on in response to the second scanning signal and configured to perform threshold voltage compensation for the driving module, wherein the data writing unit includes a second transistor having a gate electrode connected to the second scanning line, a first pole connected to a data line, and a second pole connected to the first end of the driving module; and the threshold compensation unit includes a third transistor having a gate electrode connected to the second scanning line, a first pole connected to the control end of the driving module, and a second pole connected to the second end of the driving module; the first light-emitting control module includes a fourth transistor, the gate electrode of which is connected to a light-emitting control signal line, and the fourth transistor is connected in series between the light-emitting element, the positive voltage power supply, and the second end of the driving module; the second light-emitting control module includes a fifth transistor, the fifth transistor having a gate electrode connected to a light-emitting control signal line, a first electrode connected to a first end of the driving module, and a second electrode connected to the negative voltage power supply; The pixel circuit of claim 10.

14. A first power supply signal provided from the positive voltage power supply is also used as the first reset signal. The pixel circuit of claim 10.

15. The second reset module includes a sixth transistor having a gate electrode connected to a third scanning line, a first pole connected to a cathode of the light-emitting element, and a second pole connected to a second reset signal line; and / or, the memory module is accessed by at least one fixed potential signal, and the second reset signal is also used as one of the fixed potential signals; The pixel circuit of claim 10.

16. A pixel circuit according to any one of claims 1 to 15, Display panel.

17. the driving module of the pixel circuit comprises a driving transistor; the display panel includes an active layer, a first metal layer, a third metal layer, an anode layer, a light-emitting functional layer, and a cathode layer, which are stacked one on top of the other; a channel region, a source region, and a drain region of the driving transistor are all provided in the active layer; a gate electrode of the driving transistor is provided on the first metal layer, and a projection of the gate electrode in a thickness direction of the display panel at least partially covers a channel region of the driving transistor; a first electrode and a second electrode of the driving transistor are both provided on the third metal layer, and a source region and a drain region of the driving transistor are respectively connected to the first electrode and the second electrode of the driving transistor; The display panel according to claim 16.

18. The storage module according to claim 17, wherein at least one fixed potential signal is accessed; the display panel further includes a second metal layer provided between the first metal layer and the third metal layer; the fixed potential signal is provided from a fixed potential signal line provided in the second metal layer or the third metal layer, the projection of which in a thickness direction of the display panel at least partially overlaps with the gate electrode of the driving transistor, and the overlapping portion of the fixed potential signal line and the gate electrode of the driving transistor forms the memory module; and / or the positive voltage power supply is connected to the pixel circuit by a first power supply signal line provided in the second metal layer, the third metal layer, or the anode layer; and / or the negative voltage power supply is connected to the pixel circuit by a second power supply signal line provided in the second metal layer, the third metal layer, or the anode layer; The display panel according to claim 17.

19. a plurality of isolation structures surrounding the light-emitting elements and configured to isolate the cathodes of adjacent light-emitting elements; the isolation structure comprises a conductive material layer, and the cathode of the light-emitting element contacts the isolation structure and is electrically connected to a corresponding pixel circuit by the isolation structure; The display panel according to claim 16.

20. The isolation structure has a structure that is wide at the top and narrow at the bottom, and / or the cross-sectional shape of the isolation structure is an inverted trapezoid.

20. The display panel according to claim 19.

21. The light-emitting element, wherein the cathode is electrically connected to the corresponding pixel circuit active layer by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the second electrode of the driving transistor in the corresponding pixel circuit by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the active layer of the driving transistor in the corresponding pixel circuit by the isolation structure; and / or the cathode potential of each of the light-emitting elements is individually controlled; and / or the isolation structure corresponding to each of the light-emitting elements is provided to surround the light-emitting element, at least two of the isolation structures are provided between two adjacent light-emitting elements, and the two adjacent isolation structures are insulated from each other; 20. The display panel according to claim 19.

22. The display panel further comprises a pixel definition layer and a planarization layer located between a film layer in which the pixel circuit is located and a film layer in which the isolation structure is located, the planarization layer having a through hole formed therein to expose a surface of a second electrode of a driving transistor in the pixel circuit; the isolation structure is electrically connected to the second electrode of the driving transistor through the through hole; 20. The display panel according to claim 19.

23. The cathode of the light-emitting element is electrically connected to a transistor in a corresponding pixel circuit by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the active layer of a transistor in the corresponding pixel circuit by the isolation structure; 20. The display panel according to claim 19.

24. A pixel circuit, a light emitting element, and an isolation structure, the isolation structure corresponding to each of the light emitting elements is provided to surround the light emitting element, the isolation structure comprises a conductive material layer, the cathode of the light-emitting element contacts the isolation structure, and the isolation structure is electrically connected to the corresponding pixel circuit; Display panel.

25. At least two of the isolation structures are provided between two adjacent light-emitting elements, and the two adjacent isolation structures are insulated from each other.

25. The display panel according to claim 24.

26. The isolation structure is electrically connected to the corresponding pixel circuit by a through hole.

25. The display panel according to claim 24.

27. ​​The display panel further comprises a pixel definition layer and a planarization layer located between a film layer in which the pixel circuit is located and a film layer in which the isolation structure is located, the pixel definition layer and a planarization layer in which the through-hole is provided.

27. The display panel of claim 26.

28. The isolation structure is electrically connected to a transistor in a corresponding pixel circuit by the through hole.

27. The display panel of claim 26.

29. The cathode of the light-emitting element is electrically connected to the corresponding pixel circuit by the isolation structure.

25. The display panel according to claim 24.

30. A first power supply signal line is connected to the anode of the light-emitting element.

25. The display panel according to claim 24.

31. The isolation structure has a structure that is wide at the top and narrow at the bottom, and / or the cross-sectional shape of the isolation structure is an inverted trapezoid.

25. The display panel according to claim 24.

32. The isolation structure is configured to isolate the cathodes of adjacent light-emitting elements.

25. The display panel according to claim 24.

33. The cathode of the light-emitting element is electrically connected to the active layer of the corresponding pixel circuit by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the second electrode of the driving transistor in the corresponding pixel circuit by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the active layer of the driving transistor in the corresponding pixel circuit by the isolation structure; And / or, the cathode potential of each of the light-emitting elements is individually controlled.

25. The display panel according to claim 24.

34. The display panel further comprises a pixel definition layer and a planarization layer located between a film layer in which the pixel circuit is located and a film layer in which the isolation structure is located, the planarization layer having a through hole formed therein to expose a surface of the second electrode of the driving transistor in the pixel circuit; the isolation structure is electrically connected to the second electrode of the driving transistor through the through hole; 25. The display panel according to claim 24.

35. The light-emitting element, wherein the cathode is electrically connected to a transistor in a corresponding pixel circuit by the isolation structure; and / or the cathode of the light-emitting element is electrically connected to the active layer of a transistor in the corresponding pixel circuit by the isolation structure; 25. The display panel according to claim 24.

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