High Voltage Power Supply

Abstract

a boost rectifier circuit that generates a high voltage Vout by boosting and rectifying an output voltage transmitted from the isolation transformer, and supplies the generated high voltage Vout to a load; a detector that generates a detection voltage Vdet that indicates the magnitude of the high voltage Vout; a driver that generates a command voltage Vdrc based on a deviation of the detection voltage Vdet from a target value; a transmitter that transmits the command voltage Vdrc from the low potential side region to the high potential side region; and a waveform stabilization circuit that flows a current corresponding to the magnitude of the transmitted command signal from a first input terminal to an output terminal.

Description

[Technical Field]

[0001] This application claims priority to Japanese Patent Application No. 2024-104936, filed on June 28, 2024, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0002] In a high-voltage power supply that generates a high voltage of several hundred kilovolts, a wave-tail mitigation circuit for shortening the fall time of the high voltage and a drive circuit for driving the wave-tail mitigation circuit are known (for example, Patent Document 1). In the high-voltage power supply of Patent Document 1, the wave-tail mitigation circuit is configured with multiple FETs cascade-connected between terminals to which the high voltage is applied. The drive circuit controls the wave-tail mitigation circuit based on a high-voltage on signal for driving the high-voltage power supply. When the high-voltage on signal is off, the drive circuit turns on the first-stage FET of the wave-tail mitigation circuit. When the first-stage FET is turned on, the other FETs are turned on accordingly. In this way, the wave-tail mitigation circuit discharges charges accumulated in the filter capacitor in the high-voltage power supply and the capacitance of the high-voltage cable, thereby shortening the fall time of the high voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-212948 Summary of the Invention [Problem to be solved by the invention]

[0004] In the high-voltage power supply of Patent Document 1, the wave-tail mitigation circuit is controlled by turning on or off based on a high-voltage on signal. As a result, the discharge time of the high voltage during the period when the wave-tail mitigation circuit is on is determined by the time constant of the capacitance of the filter capacitor and the high-voltage cable, and the resistor connected in series to the wave-tail mitigation circuit. However, there are cases where it is desired to control the high voltage more quickly and stably.

[0005] An object of the present disclosure is to provide a high-voltage power supply that controls a high voltage quickly and stably. [Means for solving the problem]

[0006] A high-voltage power supply according to one aspect of the present disclosure includes: [1] "an inverter arranged in a low-potential side region having a first reference potential as a reference potential; a primary winding connected to the inverter in the low-potential side region; and an isolation transformer including a secondary winding arranged in a high-potential side region having a second reference potential different from the first reference potential as a reference potential; an input terminal connected to the secondary winding in the high-potential side region; and an output terminal that supplies a positive or negative high voltage generated by stepping up and rectifying a voltage input from the isolation transformer to a load, and defines a high-potential side region having the high voltage as a reference potential. a boost rectifier circuit including an output terminal, a detection unit that generates a detection signal indicating the magnitude of the high voltage, a drive unit that is connected to the detection unit in the low potential side region and generates an instruction signal based on a deviation of the detection signal from a target value, a transmission unit that transmits the instruction signal from the low potential side region to the high potential side region, and a waveform stabilization circuit that has one end connected to the output terminal of the boost rectifier circuit in the high potential side region and the other end connected to the first reference potential, and that causes a current corresponding to the magnitude of the transmitted instruction signal to flow between the one end and the other end.

[0007] In the high-voltage power supply described in [1] above, the driver generates an instruction signal based on a detection signal indicating the magnitude of the high voltage. The waveform stabilization circuit flows a current corresponding to the magnitude of the instruction signal in accordance with the potential difference between the high-potential side region and the low-potential side region, thereby allowing a current based on the magnitude of the high voltage to flow. In other words, the waveform stabilization circuit can variably control the amount of current based on the magnitude of the high voltage. This allows the high-voltage power supply to automatically control the amount of current flowing in the waveform stabilization circuit while applying high-voltage feedback. By flowing a current in the waveform stabilization circuit, charge accumulated in the capacitance of the high-voltage power supply is discharged. This allows, for example, overshoot occurring in the high voltage to be more stably reduced. As a result, the high-voltage power supply can quickly and stably control high-voltage fluctuations when switching the high voltage. In addition, since the driver is connected to the detection unit in the low-potential side region, the driver can be driven in the low-potential side region, which has a lower and more stable absolute value of potential than the high-potential side region. Furthermore, the instruction voltage generated by the driver can be stably transmitted to the high-potential side region by the transmission unit.

[0008] A high-voltage power supply according to one aspect of the present disclosure may be [2] "the high-voltage power supply according to [1], wherein the waveform stabilization circuit includes a plurality of transistors cascade-connected to each other between the one end and the other end, and each of the plurality of transistors is driven in a saturation region." In this case, by driving each transistor in a saturation region, the waveform stabilization circuit is able to flow a sufficient amount of current. In this state, the waveform stabilization circuit can output a current corresponding to the magnitude of the instruction signal.

[0009] A high-voltage power supply according to one aspect of the present disclosure may be [3] "the high-voltage power supply according to [2], wherein the plurality of transistors are two-dimensionally arranged in row and column directions, cascaded to one another in the row direction, and connected in parallel to one another in the column direction." In this case, cascading the plurality of transistors in the row direction can increase the withstand voltage of the waveform stabilization circuit. Connecting the plurality of transistors in parallel in the column direction can increase the current capacity of the waveform stabilization circuit.

[0010] A high-voltage power supply according to one aspect of the present disclosure may be [4] "the high-voltage power supply according to any one of [1] to [3], wherein the drive unit generates the instruction signal based on a difference between a setting signal for setting the magnitude of the high voltage and the detection signal, and the waveform stabilization circuit causes a current to flow when the magnitude of the setting signal is changed from a second setting value to a first setting value having an absolute value greater than the absolute value of the second setting value and the absolute value of the high voltage exceeds the absolute value of the high voltage corresponding to the first setting value." In this case, when an overshoot occurs in which the absolute value of the high voltage exceeds the absolute value of the high voltage corresponding to the first setting value, the waveform stabilization circuit can stably control the high voltage to the first setting value.

[0011] A high-voltage power supply according to one aspect of the present disclosure may be [5] "the high-voltage power supply according to any one of [1] to [4], wherein the drive unit generates the instruction signal based on a difference between a setting signal for setting the magnitude of the high voltage and the detection signal, and the waveform stabilization circuit causes a current to flow when the setting signal is changed from a third setting value to a fourth setting value having an absolute value smaller than that of the third setting value." In this case, when the magnitude of the absolute value of the high voltage falls from the absolute value of the high voltage corresponding to the third setting value to the absolute value of the high voltage corresponding to the fourth setting value, the waveform stabilization circuit can stably control the high voltage to a voltage value corresponding to the fourth setting value.

[0012] A high-voltage power supply according to one aspect of the present disclosure may be [6] "the high-voltage power supply according to [5], wherein the absolute value of the high voltage corresponding to the third set value is greater than the first reference potential, and the absolute value of the high voltage corresponding to the fourth set value is the first reference potential." In this case, a waveform stabilization circuit can stably control the high voltage to the first reference potential.

[0013] A high-voltage power supply according to one aspect of the present disclosure may be [7] "the high-voltage power supply according to [5], wherein the absolute value of the high voltage corresponding to the third set value is greater than the second reference potential, and the absolute value of the high voltage corresponding to the fourth set value is the second reference potential." In this case, a waveform stabilization circuit can stably control the high voltage to the second reference potential.

[0014] A high-voltage power supply according to one aspect of the present disclosure may be [8] "the high-voltage power supply according to any one of [1] to [7], wherein the drive unit generates the command voltage based on an added set value obtained by adding a margin to the set value of the high voltage to compensate for fluctuations in the high voltage due to fluctuations in the magnitude of the load." In this case, voltage fluctuations in the high voltage are suppressed even when the load fluctuates, and the high-voltage power supply can be driven stably.

[0015] A high-voltage power supply according to one aspect of the present disclosure may be the high-voltage power supply according to [9] "the high-voltage power supply according to [1], further comprising: an AC conversion unit that generates a DC voltage having a magnitude according to a first voltage instruction signal and provides the DC voltage to the inverter; and a control unit that generates an inverter drive signal for driving the inverter based on the magnitude of the instruction signal, wherein the drive unit has: a feedforward system that generates the first voltage instruction signal based on a setting signal for setting the magnitude of the high voltage and provides the first voltage instruction signal to the AC conversion unit; and a first feedback system that generates the instruction signal based on a difference between the setting signal and the detection signal and provides the instruction signal to the control unit, wherein the control unit controls the inverter based on the instruction signal when the load is greater than a threshold, and independently of the instruction signal when the load is less than the threshold." In this case, when the load is heavy and the output gain of the high-voltage power supply is small, the magnitude of the high voltage can be controlled with high precision by two-degree-of-freedom control using the feedforward system and the first feedback system. On the other hand, when the load is light and the output gain of the high-voltage power supply is large, the control by the first feedback system is reduced, and the magnitude of the high voltage is controlled mainly by the feedforward system. This eliminates the need to consider a large output gain during light loads when designing the first feedback system, making it easier to stabilize feedback control by the first feedback system, and enabling fast and stable control of high voltage regardless of load fluctuations.

[0016] A high-voltage power supply according to one aspect of the present disclosure may be

[10] "the high-voltage power supply according to [9], wherein the first voltage command signal has a magnitude obtained by multiplying the setting signal by a first gain function, and the command signal has a magnitude obtained by multiplying the deviation of the detection signal from the setting signal by a second gain function." In this case, feedforward control by a feedforward system and feedback control by a first feedback system can each be performed accurately and stably.

[0017] A high-voltage power supply according to one aspect of the present disclosure may be

[11] "the high-voltage power supply according to

[10] , wherein the first gain function is set so that the high voltage changes linearly with respect to the setting signal when the load is unloaded." In this case, feedforward control by a feedforward system can be performed more accurately and stably.

[0018] A high-voltage power supply according to one aspect of the present disclosure may be

[12] "the high-voltage power supply according to any one of [9] to

[11] , further comprising a second feedback system that generates a second voltage specifying signal based on a deviation of the detection signal from the setting signal and adds the second voltage specifying signal to the setting signal, the feedforward system generating the first voltage specifying signal based on the setting signal to which the second voltage specifying signal has been added." In this way, by adjusting the setting signal according to the magnitude of the high voltage, feedforward control by the feedforward system can be performed more accurately and stably.

[0019] A high-voltage power supply according to one aspect of the present disclosure may be

[13] "the high-voltage power supply according to

[12] , wherein the second voltage instruction signal has a magnitude obtained by multiplying the deviation of the detection signal from the setting signal by a third gain function." In this case, the setting signal can be more appropriately adjusted according to the magnitude of the high voltage, and feedforward control by the feedforward system can be performed more accurately and stably. [Effects of the Invention]

[0020] According to the present disclosure, it is possible to provide a high-voltage power supply that controls a high voltage quickly and stably. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram of a high voltage power supply according to one aspect of the present disclosure. [Figure 2] FIG. 2 is a block diagram of the high voltage power supply shown in FIG. [Figure 3]FIG. 3 is a circuit diagram showing an example of the driving section, the transmitting section, and the waveform stabilizing circuit shown in FIG. [Figure 4] FIG. 4 is a diagram for explaining the behavior of the set voltage, the behavior of the detection voltage Vdet, and the behavior of the discharge current Ichg. [Figure 5] FIG. 5 is a diagram for explaining the behavior of the high voltage of the high-voltage power supply. [Figure 6] FIG. 6 is a diagram for explaining behavior during load fluctuation. [Figure 7] FIG. 7 is a block diagram of a high-voltage power supply according to a first modified example. [Figure 8] FIG. 8 is a block diagram of a high-voltage power supply according to a first modified example. [Figure 9] FIG. 9 is a diagram for explaining the behavior of a high voltage when the load in a high-voltage power supply varies. [Figure 10] FIG. 10 is a diagram showing a driving section, a transmitting section, and a waveform stabilizing circuit in a high-voltage power supply according to a second modification. [Figure 11] FIG. 11 is a diagram showing a driving section, a transmitting section, and a waveform stabilizing circuit in a high-voltage power supply according to a third modified example. [Figure 12] FIG. 12 is a circuit diagram showing an example of a waveform stabilization circuit for a high voltage power supply according to the fourth modification. [Figure 13] FIG. 13 is a circuit diagram showing an example of a waveform stabilization circuit for a high voltage power supply according to the fifth modification. [Figure 14] FIG. 14 is a circuit diagram showing an example of a waveform stabilization circuit for a high voltage power supply according to the sixth modification. [Figure 15] FIG. 15 is a circuit diagram showing an example of a waveform stabilization circuit for a high voltage power supply according to the seventh modification. [Figure 16] FIG. 16 is a circuit diagram showing an example of a waveform stabilization circuit for a high voltage power supply according to the eighth modification. [Figure 17] FIG. 17 is a block diagram showing a high voltage power supply according to a ninth modification. [Figure 18] FIG. 18 is a block diagram showing an example of the configuration of the AC input unit and the drive unit. [Figure 19] FIG. 19 is a control block diagram that schematically shows a control system realized by the drive unit. [Figure 20] FIG. 20 is a circuit diagram showing an analog circuit as a specific example of the feedforward system and the second feedback system. [Figure 21] FIG. 21 is a block diagram showing a digital circuit as a specific example of the feedforward system and the second feedback system. [Figure 22] FIG. 22 is a graph schematically showing a response waveform to a rectangular input waveform in the case of feedback control only. [Figure 23] FIG. 23 is a graph showing the correlation between the drive frequency and the output gain of the inverter. [Figure 24] FIG. 24 is a graph showing a simulation result of a response waveform in a control method using only feedback control. [Figure 25] FIG. 25 is a graph showing another simulation result of a response waveform in a control method using only feedback control. [Figure 26] FIG. 26 is a graph showing a simulation result of a response waveform in accordance with the control method of the ninth modified example. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, a preferred embodiment of a high-voltage power supply according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0023] 1 is a block diagram of a high-voltage power supply 1 according to one aspect of the present disclosure. The high-voltage power supply 1 is applicable to devices that use an input voltage of several hundred kV, such as X-ray tubes and electron beam irradiation devices. The high-voltage power supply 1 includes an AC input unit AC, an inverter 2, an isolation transformer 3, a boost rectifier circuit 4, a detector 5, a controller 6, a driver 7, a transmitter 8, and a waveform stabilization circuit 9.

[0024] The AC input unit AC converts the AC voltage generated by the AC power supply AP into a DC voltage. The AC input unit AC is, for example, a switching AC / DC converter. For example, reinforced insulation is provided between the primary and secondary sides of the AC input unit AC. In this case, the reference potential of the primary side is different from the reference potential of the secondary side. In this example, the reference potential of the primary side of the AC input unit AC is potential G0. The primary side of the AC input unit AC defines an area 11 with potential G0 as its reference potential. The reference potential of the secondary side of the AC input unit AC is a first reference potential G1. The secondary side of the AC input unit AC defines a low-potential area 12 with first reference potential G1 as its reference potential. The inverter 2 converts the DC voltage input from the AC input unit AC into an AC voltage. The inverter 2 is a bridge circuit composed of multiple transistors, for example, a half-bridge circuit in which the source terminal of a high-side FET and the drain terminal of a low-side FET are connected to each other. The output terminal of the AC input unit AC is connected to the current terminals of the plurality of transistors in the inverter 2 (the drain terminals of the FETs), for example.

[0025] The isolation transformer 3 boosts the AC voltage generated in the inverter 2. The isolation transformer 3 includes a primary winding 3a and a secondary winding 3b. The primary winding 3a and the secondary winding 3b are insulated from each other. The primary winding 3a of the isolation transformer 3 is disposed in a low-potential region 12, which is a region having a first reference potential G1 as a reference potential. The secondary winding 3b of the isolation transformer 3 is disposed in a high-potential region 13, which is a region having a second reference potential G2 as a reference potential. The second reference potential G2 is a potential different from the first reference potential G1. In this embodiment, the absolute value of the first reference potential G1 is smaller than the absolute value of the second reference potential G2. The magnitude of the first reference potential G1 is, for example, 0 V. The primary winding 3a is connected to the inverter 2 in the low-potential region 12. The isolation transformer 3 boosts the AC voltage generated in the inverter 2 in accordance with the turn ratio of the primary winding 3a and the secondary winding 3b, and transmits the boosted voltage from the low potential side region 12 to the high potential side region 13.

[0026] The boost rectifier circuit 4 boosts and rectifies the AC voltage input from the isolation transformer 3 and supplies it to the load RL. The input terminal of the boost rectifier circuit 4 is connected to the secondary winding 3b. The output terminal of the boost rectifier circuit 4 is connected to the load RL. The boost rectifier circuit 4 boosts and rectifies the AC voltage input from the isolation transformer 3 to generate a DC high voltage Vout. The boost rectifier circuit 4 generates the high voltage Vout, which is a negative voltage. The magnitude of the high voltage Vout is, for example, several hundred kV below zero. The boost rectifier circuit 4 is, for example, a Cockcroft-Walton circuit.

[0027] The output terminal of the boost rectifier circuit 4 is connected to a load RL and defines the reference potential of a high-potential region 13, which is a region having a second reference potential G2 as a reference potential. The output terminal of the boost rectifier circuit 4 is connected to the load RL in the high-potential region 13. The second reference potential G2 is, for example, several hundred kV below zero. The magnitude of the absolute value of the second reference potential G2 is greater than the magnitude of the absolute value of the first reference potential G1.

[0028] The detection unit 5 generates a detection voltage Vdet that indicates the magnitude of the high voltage Vout. An input terminal of the detection unit 5 is connected to an output terminal of the boost rectifier circuit 4. The detection unit 5 is, for example, a circuit in which a plurality of high-voltage resistance resistors are connected in series with each other or in series and parallel, and divides the high voltage Vout generated by the boost rectifier circuit 4 to generate the detection voltage Vdet. The detection unit 5 outputs the detection voltage Vdet to the drive unit 7. In the example of FIG. 1 , the detection unit 5 is arranged to straddle the low potential side region 12 and the high potential side region 13, but it may be arranged in either the low potential side region 12 or the high potential side region 13.

[0029] The driver 7 generates a command voltage Vdrc based on the detection voltage Vdet. The driver 7 is disposed in the low-potential-side region 12. The driver 7 has a first input terminal 7a and a second input terminal 7b. A set voltage Vset for setting the magnitude of the high voltage Vout is input to the first input terminal 7a. The first input terminal 7a may be connected to, for example, an external control element, and the set voltage Vset may be input to the first input terminal 7a from the external control element. The detection voltage Vdet is input to the second input terminal 7b. The second input terminal 7b is connected to the output terminal of the detector 5 in the low-potential-side region 12. As will be described in detail later, the driver 7 generates the command voltage Vdrc based on the deviation of the detection voltage Vdet from a target value on the negative voltage side. The target value is the value of the detection voltage Vdet corresponding to the target value of the high voltage Vout. In this embodiment, the target value is set by the set voltage Vset. The driver 7 generates an instruction voltage Vdrc based on the difference between the set voltage Vset and the detected voltage Vdet. The driver 7 outputs the instruction voltage Vdrc to the transmitter 8 and the controller 6. The set voltage Vset is an example of a set signal. The detected voltage Vdet is an example of a detected signal. The instruction voltage Vdrc is an example of an instruction signal. In this embodiment, the set signal, the detection signal, and the instruction signal are described as voltage signals. However, the set signal, the detection signal, and the instruction signal are not necessarily limited to voltage signals, and may be, for example, current signals or power signals.

[0030] The control unit 6 generates an inverter drive signal for driving the inverter 2 based on the magnitude of the command voltage Vdrc. The control unit 6 includes an input terminal connected to the output terminal of the drive unit 7 and an output terminal connected to the inverter 2. The output terminal of the control unit 6 is connected to, for example, input terminals of multiple transistors in the inverter 2 (gate terminals of FETs). The control unit 6 may change the frequency of the inverter drive signal or the duty ratio based on the magnitude of the command voltage Vdrc. In the example of FIG. 1, the control unit 6 is arranged in the low potential side region 12, but it may also be arranged in the high potential side region 13.

[0031] The transmission unit 8 transmits the command voltage Vdrc from the low potential side region 12 to the high potential side region 13. The transmission unit 8 is arranged so as to span from the low potential side region 12 to the high potential side region 13. The transmission unit 8 is arranged in parallel with the isolation transformer 3. The input end of the transmission unit 8 is connected to the output end of the driver 7 in the low potential side region 12. The output end of the transmission unit 8 is connected to the waveform stabilization circuit 9 in the high potential side region 13. The transmission unit 8 transmits the command voltage Vdrc from the driver 7 to the waveform stabilization circuit 9.

[0032] The waveform stabilization circuit 9 flows a current corresponding to the magnitude of the command voltage Vdrc from the first reference potential G1 to the second reference potential G2. As will be described in detail later, the waveform stabilization circuit 9 functions to stably converge the high voltage Vout to a voltage corresponding to the set voltage Vset. The waveform stabilization circuit 9 is disposed across a low potential side region 12 and a high potential side region 13. The waveform stabilization circuit 9 includes a first input terminal 9a, a second input terminal 9b, and an output terminal 9c. The first input terminal 9a is connected to the first reference potential G1 in the low potential side region 12. The second input terminal 9b is connected to the output terminal of the transmission unit 8 in the high potential side region 13. The output terminal 9c is connected to the output terminal of the boost rectifier circuit 4 and the second reference potential G2 in the high potential side region 13.

[0033] FIG. 2 shows a block diagram 10 of the high-voltage power supply 1. The block diagram 10 includes a detector 5, a driver 7, a controller 6, a waveform stabilization circuit 9, and a power supply circuit block 14. The power supply circuit block 14 includes the inverter 2, isolation transformer 3, and boost rectifier circuit 4 in the high-voltage power supply 1. The driver 7 generates a command voltage Vdrc based on the difference between the set voltage Vset and the detected voltage Vdet input from the detector 5, and outputs the command voltage Vdrc to the controller 6 and the waveform stabilization circuit 9. The transmitter 8 is omitted from the block diagram 10. The controller 6 generates an inverter drive signal for driving the inverter 2 based on the magnitude of the command voltage Vdrc. In the example of the block diagram 10, the controller 6 multiplies the command voltage Vdrc by a constant Kp to generate the drive signal. The power supply circuit block 14 generates a high voltage Vout based on the drive signal input from the controller 6. In block diagram 10, power supply circuit block 14 has a first-order lag transfer function A(s) between the command voltage Vdrc multiplied by a constant Kp and the high voltage Vout. Transfer function A(s) is, for example, a function obtained by Laplace transforming the time-domain transfer function of power supply circuit block 14. Waveform stabilization circuit 9 flows a current corresponding to the magnitude of command voltage Vdrc from first reference potential G1 to second reference potential G2, thereby stabilizing high voltage Vout. Detection unit 5 generates detection voltage Vdet that indicates the magnitude of high voltage Vout. In block diagram 10, detection unit 5 has a first-order lag transfer function B(s) between high voltage Vout and detection voltage Vdet.

[0034] FIG. 3 is a circuit diagram showing an example of the driver 7, transmitter 8, and waveform stabilization circuit 9. The driver 7 has an error amplifier 71. The error amplifier 71 includes a first input terminal 71a, a second input terminal 71b, and an output terminal 71c. A set voltage Vset for setting the magnitude of the high voltage Vout is input to the first input terminal 71a. The first input terminal 71a may be connected to, for example, an external control element, and the set voltage Vset may be input from the external control element. A detection voltage Vdet is input to the second input terminal 71b. The second input terminal 71b is connected to the output terminal of the detector 5. An instruction voltage Vdrc is output from the output terminal 71c. The output terminal 71c is connected to the transmitter 8.

[0035] The error amplifier 71 generates the command voltage Vdrc based on the difference between the set voltage Vset and the detected voltage Vdet. The set voltage Vset is a fixed value unless, for example, the user changes the setting. The error amplifier 71 generates the command voltage Vdrc when the magnitude of the detected voltage Vdet is greater than the set voltage Vset. The magnitude of the command voltage Vdrc increases in proportion to the magnitude of the difference between the set voltage Vset and the detected voltage Vdet. In other words, when the magnitude of the detected voltage Vdet is greater than the set voltage Vset, the magnitude of the command voltage Vdrc increases in proportion to the magnitude of the detected voltage Vdet, and therefore the magnitude of the high voltage Vout.

[0036] The transmission unit 8 has a light-emitting element 81 and an optical fiber 82. The anode of the light-emitting element 81 is connected to the output terminal 71c of the error amplifier 71 in the low-potential side region 12. The cathode of the light-emitting element 81 is connected to a first reference potential G1 in the low-potential side region 12. The light-emitting element 81 converts the command voltage Vdrc into light energy. At this time, as the magnitude of the command voltage Vdrc increases, the amount of current flowing through the light-emitting element 81 increases, and the light emission intensity of the light-emitting element 81 increases. The light-emitting element 81 is, for example, an LED or a laser diode.

[0037] One end of the optical fiber 82 is optically connected to the light emitting element 81 in the low potential side region 12. The optical fiber 82 is arranged to span from the low potential side region 12 to the high potential side region 13. The indicator voltage Vdrc converted into optical energy is transmitted from the low potential side region 12 to the high potential side region 13 via the optical fiber 82.

[0038] The waveform stabilization circuit 9 includes a phototransistor 90 and a plurality of transistors T91 to T9. N (N is an integer greater than or equal to 2) and multiple resistors R91 to R9 N+1 and multiple input resistors RG1 to RG N and multiple Zener diodes ZD1 to ZD N The phototransistor 90 includes an input terminal 90a, a first current terminal 90b, and a second current terminal 90c. The phototransistor 90 is disposed in the high potential side region 13. The input terminal 90a is optically connected to the other end of the optical fiber 82 in the high potential side region 13. The input terminal 90a is a second input terminal 9b of the waveform stabilization circuit 9. The first current terminal 90b is connected to the transistor T9 N The second current terminal 90c is connected to the second reference potential G2 and also to the output terminal of the boost rectifier circuit 4. The second current terminal 90c is the output terminal 9c of the waveform stabilization circuit 9. When an optical signal having an intensity corresponding to the command voltage Vdrc is input from the optical fiber 82 to the input terminal 90a of the phototransistor 90, the phototransistor 90 causes a discharge current Ichg corresponding to the intensity of the optical signal to flow from the first current terminal 90b to the second current terminal 90c. In other words, the phototransistor 90 functions as a transistor T9 N A discharge current Ichg flows from the first reference potential G1 to the second reference potential G2.

[0039] Multiple transistors T91 to T9 N In the example of FIG. 3, the resistors R91 to R9 are cascade-connected to each other between the first input terminal 9a (one terminal) and the output terminal 9c (the other terminal). N+1 are connected in series between the first input terminal 9a (one terminal) and the output terminal 9c (the other terminal). N+1A plurality of transistors T91 to T9 are connected between the adjacent resistors. N The respective input terminals T91a to T9 N a is multiple input resistors RG1 to RG N The N-th stage transistor T92 is connected to the N-th stage transistor T91 via a resistor RG1. The specific configuration is as follows: The first current terminal T91b of the top-stage transistor T91 also serves as the first input terminal 9a and is connected to the first reference potential G1. The second current terminal T91c of the top-stage transistor T91 is connected to the first current terminal T92b of the second-stage transistor T92. One end of the top-stage resistor R91 also serves as the first input terminal 9a and is connected to the first reference potential G1. The input terminal T91a of the top-stage transistor T91 is connected to the node between the other end of the top-stage resistor R91 and one end of the second-stage resistor R92 via the top-stage input resistor RG1. The above configuration is the N-th stage transistor T9 N This is repeated until the Nth stage transistor T9 N Second current terminal T9 N The resistor R9 in the (N+1)th stage is connected to the first current terminal 90b of the phototransistor 90. N+1 The other end of each of the Zener diodes ZD1 to ZD2 is connected to the second current terminal 90c (second reference potential G2) of the phototransistor 90 and is also connected to the output terminal of the boost rectifier circuit 4. N Each of the transistors T91 to T9 N In each of the input terminals T91a to T9 N a and the second current terminals T91c to T9 N c.

[0040] Input terminals T91a to T9 N In a, the high voltage Vout output from the boost rectifier circuit 4 is connected to a plurality of resistors R91 to R9 N+1 That is, the voltage divided by the plurality of transistors T91 to T9 N As a result, the plurality of transistors T91 to T9 N In the saturation region, each of the plurality of transistors T91 to T9 Nare the first current terminals T91b to T9 N b to the second current terminals T91c to T9 N The magnitude of the current that can flow through the transistors T91 to T9c is constant (saturated). N By driving each of these in its saturation region, the waveform stabilization circuit 9 is able to flow a sufficient current. In this state, when an optical signal corresponding to the command voltage Vdrc is input to the input terminal 90a of the phototransistor 90, a discharge current Ichg proportional to the command voltage Vdrc flows through the waveform stabilization circuit 9. The discharge current Ichg flows from the first input terminal 9a (one terminal) of the waveform stabilization circuit 9 to the second current terminal 90c of the phototransistor 90. In other words, the discharge current Ichg flows from the first reference potential G1 to the second reference potential G2. Since the command voltage Vdrc increases in proportion to the difference between the high voltage Vout and the target value, the waveform stabilization circuit 9 can flow a current based on the difference between the high voltage Vout and the target value. In other words, the waveform stabilization circuit 9 can variably control the amount of the discharge current Ichg based on the magnitude of the high voltage Vout.

[0041] Next, multiple input resistors RG1 to RG N For example, the functions of the transistors T91 to T9 N are input terminals T91a to T9 N a and the second current terminals T91c to T9 N The capacitance (input capacitance) between the input terminals T91a to T9c is charged. N a and the second current terminals T91c to T9 N c and the voltage between (for example, transistors T91 to T9 N When the MOSFET is turned on, the voltage Vgs between the gate terminal and the source terminal becomes equal to or exceeds the threshold. N By suppressing the oscillation of the voltage Vgs, each of the transistors T91 to T9 N At the same time, the input resistors RG1 to RG N are the transistors T91 to T9 NThe transient response time here refers to the time required for each of the transistors T91 to T9. N may be the time of transient response when transitioning from on to off or from off to on.

[0042] Multiple input resistors RG1 to RG N indicates the multiple Zener diodes ZD1 to ZD2 added as protection elements. N It also plays a role in controlling the appropriate bias current of the plurality of transistors T91 to T9. N When the number of connected stages (number of cascade stages) is small, for example, when the high voltage Vout is about several kV, multiple resistors R91 to R9 N+1 Since the input resistors RG1 to RG N On the other hand, when the number of cascade stages is large, for example, when the high voltage Vout is 100 kV or more, each of the Zener diodes ZD1 to ZD N The current flowing into the transistors T91 to T9 N Therefore, a potential difference may occur between the voltages Vgs at the multiple resistors R91 to R9 N+1 Only multiple transistors T91 to T9 N Since it is difficult to regulate the voltage Vgs at each of the input resistors RG1 to RG2 at the same potential difference, N This makes it easier to specify the same potential difference.

[0043] Next, multiple Zener diodes ZD1 to ZD N The waveform stabilization circuit 9 has a plurality of resistors R91 to R9 N+1 The current flowing through each of the transistors T91 to T9 N The first current terminals T91b to T9 N b and the second current terminals T91c to T9 N c (for example, transistors T91 to T9 N When the second current terminals T91c to T91d are MOSFETs, the voltage Vds between the drain terminal and the source terminal is biased to the same voltage. NA parasitic capacitance may be formed between the transistors T91 to T9c and the reference potential (the first reference potential G1 or the second reference potential G2). N The speed at which the voltage Vgs at each of the transistors T91 to T9 changes during a transient state differs for each transistor. N To prevent this, multiple Zener diodes ZD1 to ZD N are the transistors T91 to T9 N The Zener diodes ZD1 to ZD N Since each of the transistors T91 to T9 has bidirectionality, even when the voltage Vgs oscillates between positive and negative due to a resonance phenomenon that occurs during a transient response, the transistors T91 to T9 N can be protected.

[0044] The operation of the high voltage power supply 1 will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram for explaining the operation of the set voltage Vset, the detection voltage Vdet, and the discharge current Ichg. Normally, the set voltage Vset, the detection voltage Vdet, and the discharge current Ichg are negative values, but for ease of explanation, absolute values ​​are shown in FIGS. 4 and 5. The horizontal axis in parts (a) to (c) of FIG. 4 represents time. The vertical axis in parts (a) and (b) of FIG. 4 represents the magnitude of voltage, and the vertical axis in part (c) of FIG. 4 represents the magnitude of current. As shown in part (a) of FIG. 4, the set voltage Vset is set from 0V to a first set value V1. The absolute value of the first set value V1 is greater than 0V. As shown in part (b) of Figure 4, the detection voltage Vdet does not immediately converge to the first set value V1, and the absolute value of the detection voltage Vdet is greater than the absolute value of the first set value V1 between the first timing TM1 and the second timing TM2. In other words, the absolute value of the high voltage Vout exceeds the absolute value corresponding to the first set value V1 between the first timing TM1 and the second timing TM2. As shown in part (c) of Figure 4, at the first timing TM1, which is the timing when the absolute value of the detection voltage Vdet exceeds the absolute value of the first set value V1, the waveform stabilization circuit 9 is driven and the discharge current Ichg begins to flow. When the set voltage Vset is changed from a second set value (0 V in the case of FIG. 4) to a first set value V1 whose absolute value is greater than that of the second set value, and the magnitude of the absolute value of the high voltage Vout exceeds the absolute value of the high voltage Vout corresponding to the first set value V1, the waveform stabilization circuit 9 causes the discharge current Ichg to flow until the high voltage Vout is stabilized at the high voltage Vout corresponding to the first set value V1. At a second timing TM2, which is the timing when the magnitude of the detection voltage Vdet becomes equal to the magnitude of the first set value V1, the waveform stabilization circuit 9 is stopped and the discharge current Ichg stops flowing.

[0045] Part (a) of FIG. 5 is a diagram illustrating the behavior of the high voltage Vout of the high-voltage power supply according to the comparative example. Part (b) of FIG. 5 is a diagram illustrating the behavior of the high voltage Vout of the high-voltage power supply 1 according to the present embodiment. While the high voltage Vout would normally be a negative value, absolute values ​​are shown in FIGS. 4 and 5 for ease of explanation. The high-voltage power supply according to the comparative example does not include a driver 7, a transmitter 8, or a waveform stabilization circuit 9. As shown in part (a) of FIG. 5, the high-voltage power supply according to the comparative example exhibits an overshoot during the rise of the high voltage Vout. In the high-voltage power supply according to the comparative example, a convergence time TS1 is required for the high voltage Vout to converge to the voltage Vout1 corresponding to the set voltage Vset. The convergence time TS1 is, for example, 15 ms or more. On the other hand, as shown in part (b) of FIG. 5, the high-voltage power supply 1 according to the present embodiment exhibits significantly reduced overshoot during the rise of the high voltage Vout. In the high-voltage power supply 1, a convergence time TS2 is required for the high voltage Vout to converge to the voltage Vout1 corresponding to the set voltage Vset. The convergence time TS2 is, for example, 5 ms or less. As described above, in the high-voltage power supply 1 according to this embodiment, the time required for the high voltage Vout to converge to the voltage Vout1 corresponding to the set voltage Vset during the rise of the high voltage Vout is significantly reduced compared to the high-voltage power supply according to the comparative example. In the example of FIG. 5, the time required for the high voltage Vout to converge to the voltage Vout1 corresponding to the set voltage Vset is reduced to, for example, 1 / 3 or less.

[0046] Although the high-voltage power supply 1 is applied to the rising edge of the absolute value of the high voltage Vout in FIGS. 4 and 5 , the high-voltage power supply 1 can also be applied to the falling edge of the absolute value of the high voltage Vout. For example, when the set voltage Vset is changed from a third set value to a fourth set value whose absolute value is smaller than the third set value, the waveform stabilization circuit 9 may flow the discharge current Ichg until the magnitude of the high voltage Vout changes from a voltage value corresponding to the third set value to a voltage value corresponding to the fourth set value. In this case, the waveform stabilization circuit 9 may function as a wave-tail suppression circuit. The absolute value of the voltage corresponding to the third set value may be greater than the first reference potential G1, and the absolute value of the voltage corresponding to the fourth set value may be the first reference potential G1. Alternatively, the absolute value of the voltage corresponding to the third set value may be greater than the second reference potential G2, and the absolute value of the voltage corresponding to the fourth set value may be the second reference potential G2. The waveform stabilization circuit 9 may variably control the magnitude of the high voltage Vout from the first reference potential G1 to the second reference potential G2.

[0047] [Action and effect] In the high-voltage power supply 1, the driver 7 generates an instruction voltage Vdrc based on the detection voltage Vdet, which indicates the magnitude of the high voltage Vout. In the waveform stabilization circuit 9, a discharge current Ichg corresponding to the magnitude of the instruction voltage Vdrc flows from the first input terminal 9a (one terminal) to the output terminal 9c (the other terminal) in accordance with the potential difference between the low-potential side region 12 and the high-potential side region 13, thereby allowing a current based on the magnitude of the high voltage Vout to flow. In other words, the waveform stabilization circuit 9 can variably control the amount of current based on the magnitude of the high voltage Vout. As a result, the high-voltage power supply 1 can automatically control the amount of current flowing in the waveform stabilization circuit 9 while applying feedback of the high voltage Vout. By flowing a current in the waveform stabilization circuit 9, charge accumulated in the electrostatic capacitance within the high-voltage power supply 1 is discharged. This allows, for example, overshoot occurring in the high voltage Vout to be more stably reduced. As described above, the high-voltage power supply 1 can quickly and stably control fluctuations in the high voltage Vout when switching the high voltage Vout. In addition, since the driver 7 is connected to the detector 5 in the low potential side region 12, the driver 7 can be driven in the low potential side region 12, which has a lower and more stable absolute value of potential than the high potential side region 13. Furthermore, the command voltage Vdrc generated by the driver 7 can be stably transmitted to the high potential side region 13 by the transmitter 8.

[0048] The waveform stabilization circuit 9 includes a plurality of transistors T91 to T9 connected in cascade between a first input terminal 9a (one terminal) and an output terminal 9c (the other terminal). N a plurality of transistors T91 to T9 N are driven in their saturation regions. In this case, by driving each transistor in its saturation region, the waveform stabilization circuit 9 is able to pass a sufficient amount of current. In this state, the waveform stabilization circuit 9 can output a discharge current Ichg that corresponds to the magnitude of the command voltage Vdrc.

[0049] The drive unit 7 generates the command voltage Vdrc based on the difference between a set voltage Vset for setting the magnitude of the high voltage Vout and the detection voltage Vdet, and the waveform stabilization circuit 9 flows a current when the magnitude of the set voltage Vset is changed from a second set value to a first set value V1 whose absolute value is greater than that of the second set value, and the absolute value of the high voltage Vout exceeds the absolute value corresponding to the first set value V1. In this case, when an overshoot occurs in which the absolute value of the high voltage Vout exceeds the absolute value corresponding to the first set value V1, the waveform stabilization circuit 9 can stably control the high voltage Vout to the first set value V1.

[0050] The driver 7 generates the command voltage Vdrc based on the difference between a set voltage Vset for setting the magnitude of the high voltage Vout and the detection voltage Vdet, and the waveform stabilization circuit 9 supplies a current when the set voltage Vset is changed from a third set value to a fourth set value whose absolute value is smaller than the absolute value of the third set value. In this case, when the absolute value of the high voltage Vout falls from the absolute value of the high voltage Vout corresponding to the third set value to the absolute value of the high voltage Vout corresponding to the fourth set value, the waveform stabilization circuit 9 can stably control the high voltage to a voltage value corresponding to the fourth set value.

[0051] The absolute value of the high voltage Vout corresponding to the third set value may be greater than the first reference potential G1, and the absolute value of the high voltage Vout corresponding to the fourth set value may be equal to the first reference potential G1. In this case, the waveform stabilization circuit 9 can stably control the high voltage Vout to the first reference potential G1.

[0052] The absolute value of the high voltage Vout corresponding to the third set value may be greater than the second reference potential G2, and the absolute value of the high voltage Vout corresponding to the fourth set value may be equal to the second reference potential G2. In this case, the waveform stabilization circuit 9 can stably control the high voltage Vout to the second reference potential G2.

[0053] Although the embodiments of the present disclosure have been described above, the present disclosure is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0054] [First Modification] In the high-voltage power supply 1, when the load RL connected to the output terminal of the boost rectifier circuit 4 fluctuates in a pulse-like or step-like manner, the magnitude of the high voltage Vout may fluctuate from the voltage corresponding to the set voltage Vset. For example, as shown in part (a) of FIG. 6, assume that the load RL fluctuates stepwise at the third time TM3, causing the load current Iout supplied to the load RL to increase by ΔI from I0 to I1. As shown in part (b) of FIG. 6, the magnitude of the high voltage Vout converges to the voltage Vout1 corresponding to the set voltage Vset until the third time TM3. However, at the third time TM3, the absolute value of the high voltage Vout fluctuates in a direction decreasing from the voltage Vout1 corresponding to the set voltage Vset. At the fourth time TM4, the magnitude of the fluctuation reaches a maximum value ΔV, and at the fifth time TM5, the magnitude of the high voltage Vout converges again to the voltage Vout1 corresponding to the set voltage Vset.

[0055] The high-voltage power supply according to the first modification has the effect of suppressing fluctuations in the magnitude of the high voltage Vout described above. FIG. 7 is a block diagram of a high-voltage power supply 1A according to the first modification, and FIG. 8 is a diagram showing a block diagram 10A. The high-voltage power supply 1A differs from the high-voltage power supply 1 only in that it includes an adder 17 upstream of the driver 7. The block diagram 10A differs from the block diagram 10 only in that it includes an adder block 15 and a differentiating circuit 16 upstream of the driver 7. The adder 17 includes the adder block 15 and the differentiating circuit 16. In the example of FIG. 8, the set voltage Vset is set from 0 V to a second set voltage V2. The differentiating circuit 16 generates a margin voltage Vmgn by differentiating the set voltage Vset. The margin voltage Vmgn is a voltage for compensating for fluctuations in the high voltage Vout (maximum fluctuation value ΔV). The adder block 15 generates an additional set voltage Vadd (addition set value) by adding the margin voltage Vmgn to the second set voltage V2 in response to a change in the magnitude of the load RL. The driver 7 generates a command voltage Vdrc based on the additional set voltage Vadd. In this case, the set voltage Vset in the above-described embodiment is replaced with the additional set voltage Vadd. The margin voltage Vmgn reaches its maximum value when the set voltage Vset is changed from 0 V to the second set voltage V2, and gradually decreases nonlinearly over a predetermined duration from that timing. The predetermined duration is the difference between the fifth timing TM5 and the fourth timing TM4. The difference between the fourth timing TM4 and the third timing TM3 in FIG. 6 is calculated using equation (1). The difference between the fifth timing TM5 and the fourth timing TM4 in FIG. 6 is calculated using equation (2). The maximum fluctuation value ΔV in FIG. 6 is calculated using equation (3). The magnitude of the margin voltage Vmgn is determined based on the maximum fluctuation value ΔV obtained by equation (3). TM4-TM3=1 / (fc×π)…(1) TM5-TM4=1 / (2π×fz)…(2) ΔV=ΔI / (2π×fc×Cout)…(3) When the detector 5, driver 7, controller 6, and power supply circuit block 14 are regarded as one feedback loop system, fc indicates the crossover frequency of the feedback loop system. Specifically, it is the frequency at which the loop gain in the feedback loop system becomes 1. fz indicates the zero point of the detector 5. Specifically, fz is the pole of the transfer function B(s). Cout indicates the capacitance of the output capacitor. The output capacitor in the high voltage power supply 1A according to the modified example is, for example, the multiple transistors T91 to T9 in the waveform stabilization circuit 9. N input capacitance and a plurality of transistors T91 to T9 N This is the wiring capacitance of the wiring connecting the two.

[0056] FIG. 9 is a diagram illustrating the behavior of the high voltage Vout when the load RL fluctuates in the high-voltage power supply according to the comparative example and the behavior of the high voltage Vout when the load RL fluctuates in the high-voltage power supply 1A according to the first modified example. The behavior when the load RL fluctuates at the third timing TM3 is compared between the comparative example and the modified example. As shown in part (a) of FIG. 9 , in the high-voltage power supply according to the comparative example, at the third timing TM3, the high voltage Vout fluctuates by a maximum fluctuation value ΔV1 from the voltage Vout1 corresponding to the set voltage Vset. On the other hand, as shown in part (b) of FIG. 9 , in the high-voltage power supply 1A according to the first modified example, at the third timing TM3, the high voltage Vout fluctuates by a maximum fluctuation value ΔV2 from the voltage Vout1 corresponding to the set voltage Vset. The absolute value of ΔV1 is larger than the absolute value of ΔV2. As a result, the high-voltage power supply 1A according to the modified example is more effective at suppressing fluctuations in the magnitude of the high voltage Vout than the high-voltage power supply according to the comparative example. In this way, in the high-voltage power supply 1A according to the modified example, even when the load RL fluctuates, the voltage drop of the high voltage Vout is suppressed, and the high-voltage power supply can be driven stably.

[0057] The boost rectifier circuit 4 may generate a positive high voltage Vout. The magnitude of the high voltage Vout may be, for example, several hundred kV, and the second reference potential G2 may be, for example, several hundred kV. In this case, the second reference potential G2 is higher than the first reference potential G1. The first input terminal 9a of the waveform stabilization circuit 9 may be connected to the output terminal of the boost rectifier circuit 4 and also to the second reference potential G2. In addition, the output terminal 9c of the waveform stabilization circuit 9 may be connected to the first reference potential G1. In this case, the waveform stabilization circuit 9 may cause a discharge current Ichg to flow from the second reference potential G2 to the first reference potential G1.

[0058] [Second Modification] The transmitter 8 may transmit the instruction signal Sdrc as a digital value instead of the instruction voltage Vdrc, which is an analog value. FIG. 10 is a diagram showing the driver 7, transmitter 8, and waveform stabilization circuit 9 in a high-voltage power supply 1B according to a second modification. In the high-voltage power supply 1B, the driver 7 includes a digital element instead of an error amplifier. The driver 7 is disposed in a low-potential region 12, which uses a first reference potential G1 as a reference potential. A setting signal Sset and a detection signal Sdet are input to the driver 7. The detection signal Sdet is, for example, a signal obtained by converting the detection voltage Vdet into a digital value using an AD converter (not shown). The setting signal Sset is, for example, a signal obtained by converting the setting voltage Vset into a digital value using an AD converter (not shown). The driver 7 generates the instruction signal Sdrc, which is an electrical signal with a digital value, based on the difference between the setting signal Sset and the detection signal Sdet.

[0059] In the high-voltage power supply 1B, the transmission unit 8 has an optical fiber transceiver 85 and a DA converter 83. The optical fiber transceiver 85 includes a transmitter 85a, a receiver 85b, and an optical fiber 85c. The optical fiber transceiver 85 is arranged to extend from the low-potential side region 12 to a high-potential side region 13, which has a second reference potential G2 as its reference potential. In the example of FIG. 10 , the transmitter 85a is arranged in the low-potential side region 12. The optical fiber 85c is arranged to extend from the low-potential side region 12 to the high-potential side region 13. The receiver 85b and the DA converter 83 are arranged in the high-potential side region 13.

[0060] The transmitter 85a includes, for example, a light-emitting element. The instruction signal Sdrc generated by the driver 7 is input to the transmitter 85a and converted from an electrical signal to an optical signal by the light-emitting element. The instruction signal Sdrc converted into an optical signal propagates through the optical fiber 85c and is input to the receiver 85b. As a result, the instruction signal Sdrc is transmitted from the low potential side region 12 to the high potential side region 13. The receiver 85b includes, for example, a light-receiving element. The instruction signal Sdrc is converted back into an electrical signal by the light-receiving element. The instruction signal Sdrc is then sent to the DA converter 83 and converted from a digital value to an analog value.

[0061] In the high-voltage power supply 1B, the DA converter 83 and the waveform stabilization circuit 9 are optically coupled by a photocoupler 84. The photocoupler 84 includes a light-emitting element 84a and a light-receiving element 84b. The light-receiving element 84b may correspond to the phototransistor 90 of the waveform stabilization circuit 9. The instruction signal Sdrc, which has been converted into an analog value, is converted into an optical signal by the light-receiving element 84b. When an optical signal of an intensity corresponding to the instruction signal Sdrc is input, the light-receiving element 84b causes a discharge current corresponding to the intensity of the optical signal to flow from a first current terminal 90b to a second current terminal 90c.

[0062] According to the high voltage power supply 1B, by transmitting the instruction signal Sdrc as a digital value through the optical fiber 85c, signal transmission can be performed stably and easily between the low potential side region 12 and the high potential side region 13, which have a large potential difference.

[0063] [Third Modification] FIG. 11 is a diagram showing the driver 7, transmitter 8, and waveform stabilization circuit 9 of a high-voltage power supply 1C according to a third modification. The high-voltage power supply 1C differs from the high-voltage power supply 1B in that the transmitter 8 has a pulse transformer transmitter / receiver 86 instead of the optical fiber transmitter / receiver 85, and that the pulse transformer transmitter / receiver 86 has a pulse transformer 86c instead of the optical fiber 85c. The pulse transformer 86c is disposed across the low-potential side region 12 and the high-potential side region 13. The primary winding of the pulse transformer 86c is coupled to the transmitter 85a. The secondary winding of the pulse transformer 86c is coupled to the receiver 85b. In the high-voltage power supply 1C, the instruction signal Sdrc is transmitted as an electrical signal by the pulse transformer 86c from the low-potential side region 12 to the high-potential side region 13.

[0064] In the high-voltage power supplies 1B and 1C, the instruction voltage Vdrc generated by the drive unit 7 can be stably transmitted to the high-potential side area 13 by the transmission unit 8 as an instruction signal Sdrc.

[0065] [Fourth Modification] In the waveform stabilization circuit, the plurality of transistors may be connected in parallel as well as in cascade with each other. Fig. 12 is a circuit diagram showing an example of a waveform stabilization circuit 9A of a high voltage power supply according to a fourth modification. The waveform stabilization circuit 9A includes a plurality of transistors T9 11 ~T9 NM (N and M are integers of 2 or more) and multiple input resistors RG 11 ~RG NM and multiple Zener diodes ZD 11 ~ZD NM The waveform stabilization circuit 9 differs from the waveform stabilization circuit 9 in that it has a plurality of transistors T9 11 ~T9 NM In this example, N transistors are arranged in the row direction (series direction) and M transistors are arranged in the column direction (parallel direction) in a two-dimensional connection relationship, and are connected to each other. Here, the row closest to the first reference potential G1 is the first row, and the row closest to the second reference potential G2 is the Nth row.N+1 The column closest to the first row is the first column, and the column furthest from the first row is the Mth column. N1 , transistor T9 N2 , and transistor T9 NM The phototransistor 90 causes a discharge current Ichg to flow from the transistor in the Nth row to the second reference potential G2.

[0066] Several transistors T9 11 ~T9 NM are cascaded to each other in the row direction and connected in parallel to each other in the column direction between the first input terminal 9a (one terminal) and the output terminal 9c (the other terminal). The cascaded configuration in the row direction is the same as the cascaded configuration in the waveform stabilization circuit 9. The parallel connection in the column direction is achieved by connecting the input terminals of multiple transistors located in the same row to multiple resistors R91 to R99. N+1 Multiple input resistors RG 11 ~RG NM For example, multiple transistors T9 11 ~T9 1M The input terminal of the resistor R91 is connected to the node between the resistors R92 and R93. 11 Connected via multiple Zener diodes ZD 11 ~ZD NM Each of the transistors T9 11 ~T9 NM In each of the above, a resistor is connected between the input terminal and the second current terminal.

[0067] Several transistors T9 11 ~T9 NM The transistors T9 are cascaded in the row direction to increase the withstand voltage of the waveform stabilization circuit 9. 11 ~T9 NM By connecting the resistors R91 to R9 in parallel in the column direction, the current capacity of the waveform stabilization circuit 9 can be increased. N+1The function of the input resistors RG is to ensure the balance of the drain-source and gate-source voltages of each transistor in conjunction with the gate resistors and bidirectional protection elements. 11 ~RG NM As in the waveform stabilization circuit 9 according to the embodiment, each transistor T9 11 ~T9 NM and prevents the false firing of each transistor T9 11 ~T9 NM The Zener diodes ZD function to uniquely control the transient response time of the 11 ~ZD NM As in the waveform stabilization circuit 9 according to the embodiment, each transistor T9 11 ~T9 NM It functions as a protective element to protect the

[0068] [Fifth Modification] 13 is a circuit diagram showing an example of a waveform stabilization circuit 9B of a high voltage power supply according to the fifth modification. The waveform stabilization circuit 9B includes a plurality of Zener diodes ZD1 to ZD N For example, the waveform stabilization circuit 9 does not have the transistors T91 to T9. N The input capacitance and the second current terminals T91c to T9 N The parasitic capacitance between c and the reference potential is sufficiently small, and each resistor R91 to R9 N+1 and each input resistor RG1 to RG N It is assumed that the time constant formed by the transistors T91 to T9 is sufficiently small (for example, the transient response time is small enough to be negligible). N Since the rate at which the voltage Vgs at the transistors changes in a transient state is unlikely to differ for each transistor, the multiple Zener diodes ZD1 to ZD N is no longer necessary.

[0069] [Sixth Modification] 14 is a circuit diagram showing an example of a waveform stabilization circuit 9C of a high voltage power supply according to a sixth modification. The waveform stabilization circuit 9C includes a plurality of Zener diodes ZD 11 ~ZD NMThe waveform stabilization circuit 9C differs from the waveform stabilization circuit 9A according to the fourth modification in that it does not have the transistors T9 11 ~T9 NM This configuration is applicable when the rate at which the voltage Vgs at the transistor changes in a transient state is unlikely to differ from transistor to transistor.

[0070] [Seventh Modification] 15 is a circuit diagram showing an example of a waveform stabilization circuit 9D of a high voltage power supply according to the seventh modification. The waveform stabilization circuit 9D has a plurality of input resistors RG 11 ~RG NM Instead of multiple input resistors RG1 to RG N The waveform stabilization circuit 9D differs from the waveform stabilization circuit 9C according to the fifth modification in that it has the following input resistors RG1 to RG N is provided for each column, so that the input resistance of the M transistors in each column is common.

[0071] [Eighth Modification] 16 is a circuit diagram showing an example of a waveform stabilization circuit 9E of a high voltage power supply according to Modification 8. The waveform stabilization circuit 9E differs from the waveform stabilization circuit 9 according to the embodiment in the following points.

[0072] The first input terminal 9a is connected to a constant potential line 9d, not to the first reference potential G1. A The constant potential line 9d is connected to a plurality of transistors T91 to T9 N A positive bias is applied to the constant potential line 9d. The potential of the constant potential line 9d is, for example, +15 V with respect to the first reference potential G1, but the potential of the constant potential line 9d is not limited to this as long as it is a positive potential with respect to the first reference potential G1. In the waveform stabilization circuit 9 shown in FIG. 3, when the output voltage (high voltage Vout, i.e., the second reference potential G2) from the boost rectifier circuit 4 drops, the multiple transistors T91 to T9, which are MOSFETs, are turned off. NIt becomes difficult for the phototransistor 90 to operate in the active region. Furthermore, the bias voltage between the second input terminal 9b and the second reference potential G2 alone is not enough to pass a current of sufficient magnitude through the phototransistor 90, and the operating speed of the phototransistor 90 decreases. In the waveform stabilization circuit 9E of this modification, even when the output voltage from the boost rectifier circuit 4 decreases, the multiple transistors T91 to T9 N In order to operate the transistors T91 to T9 in the active region, a constant voltage bias is applied to the first input terminal 9a from a constant potential line 9d. This allows the transistors T91 to T9 to operate in the active region regardless of the magnitude of the second reference potential G2. N Furthermore, since the phototransistor 90 can continue to operate in the active region, the transient response and DC static characteristics of the waveform stabilization circuit are improved.

[0073] In addition, the output terminal 9c is connected to a second reference potential G2 via a diode 90d. In a configuration such as this modification in which the first input terminal 9a is connected to a constant potential line 9d, even if the high voltage Vout from the boost rectifier circuit 4 is set to 0V, the actual high voltage Vout will be at the same level as the bias voltage of the constant potential line 9d and will not reach 0V. To prevent this, the output terminal 9c is connected to the second reference potential G2 via the forward diode 90d, thereby clamping the second reference potential G2, i.e., the high voltage Vout. This makes it possible to limit the high voltage Vout to a maximum value equivalent to the forward voltage of the diode 90d.

[0074] In addition, in this modification, a plurality of transistors T91 to T9 N are all depletion-type MOSFETs. N Since the gate-source voltage Vgs of each transistor is biased equally, the linearity of the high voltage Vout can be maintained over an extremely low voltage range.

[0075] [Ninth Variation] FIG. 17 is a block diagram showing a high-voltage power supply 1D according to the ninth modification. The high-voltage power supply 1D differs from the high-voltage power supply 1 according to the embodiment in the following respects. The high-voltage power supply 1D includes an AC input unit AC2 instead of the AC input unit AC of the embodiment. The AC input unit AC2 converts the AC voltage generated in the AC power supply AP into a DC voltage Vdc. The high-voltage power supply 1D includes a drive unit 7A instead of the drive unit 7 of the embodiment.

[0076] FIG. 18 is a block diagram showing a configuration example of the AC input unit AC2 and the drive unit 7A. The AC input unit AC2 generates a DC voltage Vdc having a magnitude corresponding to the first voltage instruction signal Sd1. The AC input unit AC2 includes an input power adjustment unit 21 and a detection system 22. The input power adjustment unit 21 adjusts the voltage value of the DC voltage Vdc output from the AC input unit AC2. The detection system 22 detects the voltage value of the DC voltage Vdc and generates an electrical detection voltage Vdet corresponding to the voltage value of the DC voltage Vdc. The input power adjustment unit 21 receives a deviation of the detection voltage Vdet from the first voltage instruction signal Sd1 and adjusts the voltage value of the DC voltage Vdc so that the deviation is reduced. The adjusted DC voltage Vdc is provided to the inverter 2.

[0077] The driver 7A includes a feedforward system FF, a first feedback system FB1, and a second feedback system FB2. The feedforward system FF receives a set voltage Vset and generates a first voltage command signal Sd1 based on the set voltage Vset. The first voltage command signal Sd1 is provided to the AC input unit AC2. In one example, the first voltage command signal Sd1 has a magnitude obtained by multiplying the set voltage Vset by a first gain function F1. The first gain function F1 is set, for example, so that the high voltage Vout changes linearly with the set voltage Vset when the load RL is unloaded.

[0078] The first feedback system FB1 is connected to the detection unit 5 and receives the detection voltage Vdet as an input. The first feedback system FB1 includes an error amplifier 71 that calculates the deviation of the detection voltage Vdet from the set voltage Vset. Based on the deviation of the detection voltage Vdet from the set voltage Vset, the first feedback system FB1 generates a command voltage Vdrc so as to reduce the deviation. The first feedback system FB1 provides the generated command voltage Vdrc to the control unit 6. The command voltage Vdrc has a magnitude obtained by multiplying the deviation of the detection voltage Vdet from the set voltage Vset by a second gain function F2, for example.

[0079] The second feedback system FB2 receives the deviation of the detection voltage Vdet from the set voltage Vset from the error amplifier 71. The second feedback system FB2 generates a second voltage command signal Sd2 based on the deviation of the detection voltage Vdet from the set voltage Vset. The second voltage command signal Sd2 has a magnitude, for example, obtained by multiplying the deviation of the detection voltage Vdet from the set voltage Vset by a third gain function F3. The second feedback system FB2 includes an adder circuit 72 that adds the second voltage command signal Sd2 to the set voltage Vset. The feedforward system FF generates a first voltage command signal Sd1 based on the set voltage Vset to which the second voltage command signal Sd2 has been added.

[0080] The control unit 6 controls the magnitude of the AC voltage by controlling the inverter 2 in a state where the command voltage Vdrc is dominant when the load RL is greater than a predetermined threshold, and in a state where the first voltage command signal Sd1 is dominant and the contribution of the command voltage Vdrc is small when the load RL is less than the predetermined threshold. The load RL can be known, for example, by detecting the magnitude of the output current from the inverter 2 or the load current flowing through the load RL.

[0081] FIG. 19 is a control block diagram illustrating a control system implemented by the driver 7A. In the diagram, the input signal r(s) corresponds to the set voltage Vset, the intermediate signal u(s) corresponds to the input voltage (DC voltage Vdc) to the inverter 2 and the inverter drive signal, and the output signal y(s) corresponds to the high voltage Vout to the load RL. Block 101 is a transfer function representing a controlled object including the inverter 2, the isolation transformer 3, and the boost rectifier circuit 4, block 102 is a transfer function representing a controller using the feedforward system FF, and block 103 is a transfer function representing a controller using the first feedback system FB1. As shown in FIG. 19, the high-voltage power supply 1D of this modification can control the magnitude of the high voltage Vout with high precision through two-degree-of-freedom control using the feedforward system FF and the first feedback system FB1. The reciprocal 1 / P(s) of the controlled object P(s) may be set in block 102 of the feedforward system FF.

[0082] 20 is a circuit diagram showing an analog circuit as a specific example of the feedforward system FF and the second feedback system FB2. In this example, the driver 7A includes an error amplifier 71, an adder circuit 72, and an amplifier circuit 73. The driver 7A further includes a resistor 701, a capacitor 702, and a buffer 703. The set voltage Vset is input to the buffer 703 through the resistor 701. One electrode of the capacitor 702 is connected to a node between the input terminal of the buffer 703 and the resistor 701, and the other electrode of the capacitor 702 is connected to the ground potential GND. The resistor 701 and the capacitor 702 function as a filter that removes noise from the set voltage Vset. The set voltage Vset is boosted by the buffer 703.

[0083] The error amplifier 71 is a subtractor including an operational amplifier 711. One input terminal of the operational amplifier 711 is connected to the output terminal of a buffer 703 via a resistor 712. The other input terminal of the operational amplifier 711 receives a detection voltage Vdet via a resistor 713. The output terminal of the operational amplifier 711 is connected to one input terminal via a feedback resistor 714 and a capacitor 715. The amplifier circuit 73 constitutes a part of a feedforward system FF. The amplifier circuit 73 is an amplifier including an operational amplifier 731 that multiplies a set voltage Vset by a first gain function F1. One input terminal of the operational amplifier 731 is connected to the output terminal of the buffer 703 via a resistor 732. The other input terminal of the operational amplifier 731 is connected to a ground potential GND. The output terminal of the operational amplifier 731 is connected to one input terminal via a feedback resistor 733. The amplification factor of the amplifier circuit 73 is determined according to the first gain function F1.

[0084] The adder circuit 72 constitutes a part of the second feedback system FB2. The adder circuit 72 is an adder including an operational amplifier 721. The adder circuit 72 multiplies the output from the error amplifier 71 (i.e., the deviation of the detection voltage Vdet from the set voltage Vset) by a third gain function F3, and adds the output from the amplifier circuit 73 (i.e., the set voltage Vset multiplied by the first gain function F1) to the multiplication result. Specifically, one input terminal of the operational amplifier 721 is connected to the output terminal of the error amplifier 71 via a resistor 722 and to the output terminal of the amplifier circuit 73 via a resistor 723. The other input terminal of the operational amplifier 721 is connected to the ground potential GND. The output terminal of the operational amplifier 721 is connected to one input terminal via a feedback resistor 724. The ratio between the resistance value of the resistor 722 and the resistance value of the resistor 723 is determined according to the third gain function F3. The adder circuit 72 outputs a first voltage instruction signal Sd1.

[0085] 21 is a block diagram showing a digital circuit as a specific example of the feedforward system FF and the second feedback system FB2. In this example, the driver 7A includes a control block for a first gain function F1, a control block for an integrator F31 that constitutes part of the third gain function F3, a control block for a proportional calculator F32 that constitutes another part of the third gain function F3, and an adder as the summing circuit 72. In the figure, data Dset and Ddet are digital values ​​of the set voltage Vset and the detection voltage Vdet, respectively. The feedforward value output from the control block for the first gain function F1, the integral value output from the control block for the integrator F31, and the proportional value output from the control block for the proportional calculator F32 are added together by the adder to generate the first voltage command signal Sd1.

[0086] The effects obtained by the high-voltage power supply 1D of this modified example described above will now be described. Within the high-voltage power supply, a resonant circuit is formed by parasitic capacitances formed between the junction surfaces of the diodes in the isolation transformer 3 and the boost rectifier circuit 4 and the ground potential. The Q value of this resonant circuit changes significantly in response to fluctuations in the load RL. As a result, the output gain of the high-voltage power supply (the ratio B / A of the output voltage B and the input voltage A) changes significantly in response to fluctuations in the load RL. For this reason, it may be difficult to control the high voltage Vout quickly and stably by using feedback control alone.

[0087] As an example, FIG. 22 is a graph showing response waveforms (lines G12 and G13) to a rectangular input waveform (line G11) under feedback control only. In FIG. 22, the horizontal axis represents time, and the vertical axis represents input / output values ​​(normalized values ​​where the input value is 1). Line G12 shows the case where the damping constant ζ is 1.0, and line G13 shows the case where the damping constant ζ is 0.1. Because high-voltage power supply control is a high-order system, increasing the damping constant ζ requires a long time for the oscillation to converge, as shown by line G12. Decreasing the damping constant ζ increases the oscillation, as shown by line G13, making it more likely for overshoot to occur. FIG. 23 is a graph showing the correlation between the drive frequency (Hz) and output gain (dB) of inverter 2. In FIG. 23, curves G21 to G25 show the cases where the load RL is 0.00049, 0.016, 0.031, 0.10, and 0.25, respectively. As shown in FIG. 23, the smaller the load RL (light load), the larger the peak value of the output gain, and the larger the load RL (heavy load), the smaller the peak value of the output gain.

[0088] To address this issue, the high-voltage power supply 1D of this modified example includes a feedforward system FF in addition to a first feedback system FB1. When the load RL is smaller than a threshold value, the control unit 6 controls the inverter 2 in a state where the effect of the control by the command voltage Vdrc generated by the first feedback system FB1 is small. As a result, the high voltage Vout is controlled in a state where the effect of the feedforward control by the feedforward system FF is dominant. When the load RL is larger than a threshold value, the control unit 6 controls the inverter 2 in a state where the command voltage Vdrc generated by the first feedback system FB1 is dominant. As a result, the high voltage Vout is controlled based on the feedback control by the first feedback system FB1 in addition to the feedforward control by the feedforward system FF.

[0089] In this way, under heavy load conditions where the output gain of the high-voltage power supply 1D is small, the magnitude of the high voltage Vout can be controlled with high precision by two-degree-of-freedom control using the feedforward system FF and the first feedback system FB1. On the other hand, under light load conditions where the output gain of the high-voltage power supply 1D is large, the effect of control by the first feedback system FB1 is relatively reduced, and the magnitude of the high voltage Vout is controlled in a state where the feedforward system FF is dominant. This eliminates the need to consider the large output gain under light load conditions in the design of the first feedback system FB1. This makes it easier to stabilize the feedback control by the first feedback system FB1, allowing for quick and stable control of the high voltage Vout regardless of fluctuations in the load RL.

[0090] FIG. 24 is a graph showing a simulation result of a response waveform obtained by a control method using only feedback control. FIG. 25 is a graph showing another simulation result of a response waveform obtained by a control method using only feedback control. FIG. 26 is a graph showing a simulation result of a response waveform obtained by a control method using this modified example. In FIGS. 24 to 26, the horizontal axis represents time and the vertical axis represents voltage. Line G31 shows the time waveform (5 V / div) of the output voltage command value (set voltage Vset in this modified example), line G32 shows the time waveform (2 V / div) of the output voltage (high voltage Vout in this modified example), and line G33 shows the deviation (1 V / div) of the output voltage from the command value. With a control method using only feedback control, as shown in FIG. 24, if the output voltage is attempted to quickly follow a change in the command value, it takes a long time for the output voltage oscillation to converge. As shown in FIG. 25, if an attempt is made to suppress the output voltage oscillation in response to a change in the command value, it takes a long time (3500 ms in this example) for the output voltage to reach the command value after the change. In contrast to these, the control method of this modified example makes it possible to suppress the oscillation of the output voltage in response to a change in the command value, and to make the output voltage quickly reach the command value after the change (in 150 ms in this example), as shown in Fig. 26. This effect of the control method of this modified example is thought to be due to the fact that, under a light load where the output gain is large, the effect of control by the first feedback system FB1 is relatively reduced, and the magnitude of the high voltage Vout is controlled in a state where the feedforward system FF is dominant, thereby making the control of the high-voltage power supply 1D a simple first-order lag system.

[0091] As in this modification, the first voltage command signal Sd1 may have a magnitude obtained by multiplying the set voltage Vset by the first gain function F1, and the command voltage Vdrc may have a magnitude obtained by multiplying the deviation of the detection voltage Vdet from the set voltage Vset by the second gain function F2. In this case, the feedforward control by the feedforward system FF and the feedback control by the first feedback system FB1 can both be performed accurately and stably.

[0092] As in this modification, the first gain function F1 may be set so that the high voltage Vout changes linearly with respect to the set voltage Vset when the load RL is unloaded. In this case, the feedforward control by the feedforward system FF can be performed more accurately and stably.

[0093] As in this modification, the high-voltage power supply 1D may further include a second feedback system FB2 that generates a second voltage instruction signal Sd2 based on the deviation of the detection voltage Vdet from the set voltage Vset and adds the second voltage instruction signal Sd2 to the set voltage Vset. The feedforward system FF may then generate a first voltage instruction signal Sd1 based on the set voltage Vset to which the second voltage instruction signal Sd2 has been added. By adjusting the set voltage Vset in accordance with the magnitude of the high voltage Vout in this manner, feedforward control by the feedforward system FF can be performed more accurately and stably. The second voltage instruction signal Sd2 may be added to the set voltage Vset either before or after multiplication of the set voltage Vset by the first gain function F1.

[0094] As in this modification, the second voltage command signal Sd2 may have a magnitude obtained by multiplying the deviation of the detection voltage Vdet from the set voltage Vset by the third gain function F3. In this case, the set voltage Vset can be more appropriately adjusted according to the magnitude of the high voltage Vout, and the feedforward control by the feedforward system FF can be performed more accurately and stably.

[0095] The high-voltage power supply according to the present disclosure is not limited to the above-described embodiment and each modified example, and various other modifications are possible. For example, depending on the application or required performance of the high-voltage power supply, the second feedback system FB2 of the above-described ninth modified example may be omitted from the drive unit 7A.

[0096] While the principles of the present invention have been illustrated and described in preferred embodiments, it will be recognized by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the particular constructions disclosed herein. We therefore claim all modifications and variations that come within the scope and spirit of the following claims. [Explanation of symbols]

[0097] 1,1A...High voltage power supply, 2...Inverter, 3...Isolation transformer, 3a...Primary winding, 3b...Secondary winding, 4...Boost rectifier circuit, 5...Detection unit, 7,7A...Driver unit, 8...Transmission unit, 9...Waveform stabilization circuit, 9a...First input terminal (one terminal), 9c...Output terminal (other terminal), 12...Low potential side region, 13...High potential side region, G1...First reference potential, G2...Second reference potential, RL...Load, T91 to T9 N ...transistor, V1...first set value, Vdrc...command voltage, Vout...high voltage.

Claims

1. an inverter disposed in a low potential side region having a first reference potential as a reference potential; an isolation transformer including a primary winding connected to the inverter in the low potential side region and a secondary winding arranged in a high potential side region having a second reference potential different from the first reference potential; a boost rectifier circuit including an input terminal connected to the secondary winding in the high potential side region, and an output terminal that supplies a positive or negative high voltage generated by boosting and rectifying a voltage input from the isolation transformer to a load and that determines the second reference potential by the high voltage; a detection unit that generates a detection signal indicating the magnitude of the high voltage; a driver connected to the detector in the low potential region and generating an indication signal based on a deviation of the detection signal from a target value; a transmission unit that transmits the instruction signal from the low potential side area to the high potential side area; a waveform stabilization circuit including one end connected to the output end of the boost rectifier circuit in the high potential side region and the other end connected to the first reference potential, and causing a current corresponding to the magnitude of the transmitted instruction signal to flow between the one end and the other end.

2. the waveform stabilization circuit includes a plurality of transistors cascade-connected to each other between the one end and the other end, 2. The high voltage power supply of claim 1, wherein each of said plurality of transistors is driven in a saturation region.

3. The plurality of transistors include: It has a two-dimensional connection relationship in the row and column directions, cascaded to each other in the row direction; 3. The high-voltage power supply according to claim 2, wherein the power supplies are connected in parallel to each other in the column direction.

4. the driver generates the instruction signal based on a difference between a setting signal for setting the magnitude of the high voltage and the detection signal; 4. The high-voltage power supply according to claim 1, wherein the waveform stabilization circuit flows a current when the magnitude of the setting signal is changed from a second setting value to a first setting value having an absolute value greater than the absolute value of the second setting value, and the magnitude of the high voltage exceeds an absolute value of a voltage corresponding to the first setting value.

5. the driver generates the instruction signal based on a difference between a setting signal for setting the magnitude of the high voltage and the detection signal; 4. The high-voltage power supply according to claim 1, wherein the waveform stabilization circuit causes a current to flow when the setting signal is changed from a third setting value to a fourth setting value having an absolute value smaller than that of the third setting value.

6. the absolute value of the high voltage corresponding to the third set value is greater than the first reference potential; 6. The high-voltage power supply according to claim 5, wherein the absolute value of the high voltage corresponding to the fourth set value is the first reference potential.

7. the absolute value of the high voltage corresponding to the third set value is greater than the second reference potential; 6. The high voltage power supply according to claim 5, wherein the absolute value of the high voltage corresponding to the fourth set value is the second reference potential.

8. 4. The high-voltage power supply according to claim 1, wherein the driving unit generates the instruction signal based on an added set value obtained by adding a margin for compensating for fluctuations in the high voltage due to fluctuations in the magnitude of the load to the set value of the high voltage.

9. an AC conversion unit that generates a DC voltage having a magnitude according to a first voltage indication signal and provides the DC voltage to the inverter; a control unit that generates an inverter drive signal for driving the inverter based on the magnitude of the instruction signal; Further provided with The drive unit is a feedforward system that generates the first voltage indication signal based on a setting signal for setting the magnitude of the high voltage and provides the first voltage indication signal to the AC conversion unit; a first feedback system that generates the instruction signal based on a difference between the setting signal and the detection signal and provides the instruction signal to the control unit; and 4. The high-voltage power supply according to claim 1, wherein the control unit controls the inverter based on the instruction signal when the load is greater than a threshold value, and controls the inverter independently of the instruction signal when the load is less than the threshold value.

10. the first voltage indicator signal has a magnitude obtained by multiplying the setting signal by a first gain function; 10. The high voltage power supply of claim 9, wherein the indicator signal has a magnitude equal to a deviation of the sensed signal from the setpoint signal multiplied by a second gain function.

11. 11. The high-voltage power supply of claim 10, wherein the first gain function is set so that the high voltage changes linearly with respect to the set signal when the load is unloaded.

12. a second feedback system that generates a second voltage indicating signal based on a deviation of the detection signal from the set signal and adds the second voltage indicating signal to the set signal; 10. The high voltage power supply according to claim 9, wherein the feedforward system generates the first voltage indicating signal based on the setting signal to which the second voltage indicating signal has been added.

13. 13. The high voltage power supply of claim 12, wherein the second voltage indicator signal has a magnitude equal to a deviation of the sensed signal from the setpoint signal multiplied by a third gain function.

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