Indication device

Abstract

To provide a display device capable of reducing overcurrent and power consumption.SOLUTION: A display device comprises: a display panel including a plurality of data lines and pixels connected to the data lines; a first data driving portion including a plurality of first output buffers arranged at a plurality of channels respectively connected to one ends of the plurality of data lines; and a second data driving portion including a plurality of second output buffers arranged at a plurality of channels respectively connected to the other ends of the plurality of data lines. Each of the first output buffers and the second output buffers alternates between a positive chopping state and a negative chopping state by frame, and offset directions of output voltages of the first output buffers and the second output buffers at the corresponding channel are the same in the same frame.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] 2. Description of the Related Art With the advancement of the information society, various demands on display devices for displaying images are increasing, and in recent years, various flat display devices such as organic light-emitting display devices and liquid crystal display devices have come into use.

[0003] Recently, organic light emitting display devices have been driven in a double bank structure in which data drivers are arranged at both ends of a data line. In the double bank structure, output buffers for each channel of the upper and lower data drivers output the same data voltage to the corresponding data line.

[0004] However, the upper and lower output buffers may output output voltages that are offset inversely to each other, resulting in a difference in output voltage between the upper and lower buffers. Such a voltage difference between the upper and lower buffers may cause an overcurrent and increase power consumption. Summary of the Invention [Problem to be solved by the invention]

[0005] The present specification aims to provide a technology that can reduce power consumption by improving the occurrence of overcurrent due to the difference in output voltage between the upper output buffer and the lower output buffer in a double bank structure. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, this specification provides a display device including a display panel including a plurality of data wirings and pixels connected to the data wirings; a first data driver including a plurality of first output buffers arranged in a plurality of channels each connected to one end of the plurality of data wirings; and a second data driver including a plurality of second output buffers arranged in a plurality of channels each connected to the other end of the plurality of data wirings, wherein each of the first output buffers and the second output buffers are alternately switched between a positive chopping state and a negative chopping state for each frame, and the first output buffers and the second output buffers of corresponding channels have the same offset direction of output voltages in the same frame.

[0007] The plurality of channels may include channels having the same chopping state in the same frame between the first output buffer and the second output buffer.

[0008] The plurality of channels may include channels having opposite chopping states in the same frame between the first output buffer and the second output buffer.

[0009] The positive chopping state may be a negative feedback state, and the negative chopping state may be a positive feedback state.

[0010] The first output buffer and the second output buffer may each have an output voltage offset direction opposite to that in the positive chopping state.

[0011] The first data driver may include a first memory that stores first chopping driving information in which a chopping state of the first output buffer for each frame is set, and the second data driver may include a second memory that stores second chopping driving information in which a chopping state of the second output buffer for each frame is set.

[0012] In the corresponding channels, the current consumption when the offset direction of the output voltage between the first output buffer and the second output buffer is the same may be smaller than the current consumption when the offset direction of the output voltage is opposite.

[0013] The pixels may include light emitting diodes.

[0014] Between the first output buffer and the second output buffer, in channels having the same chopping state in the same frame, the first output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state.

[0015] Between the first output buffer and the second output buffer, in a channel having opposite chopping states in the same frame, the first output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer may have a negative offset in the negative chopping state and a positive offset in the positive chopping state.

[0016] In another aspect, the present invention provides a display device including a display panel including a plurality of data lines; a first data driver including a plurality of first output buffers each connected to one end of the plurality of data lines; and a second data driver including a plurality of second output buffers each connected to the other end of the plurality of data lines, wherein each of the first output buffers and the second output buffers alternate between a positive chopping state and a negative chopping state every frame, and the first output buffers and the second output buffers connected to the same data line output data voltages with the same offset direction.

[0017] The first output buffer and the second output buffer connected to any one of the plurality of data lines may have the same chopping state in the same frame.

[0018] The first output buffer and the second output buffer connected to another data line among the plurality of data lines may have opposite chopping states in the same frame.

[0019] The positive chopping state may be a negative feedback state, and the negative chopping state may be a positive feedback state.

[0020] The first output buffer and the second output buffer may each have an output voltage offset direction opposite to that in the positive chopping state.

[0021] The first data driver may include a first memory that stores first chopping driving information in which a chopping state of the first output buffer for each frame is set, and the second data driver may include a second memory that stores second chopping driving information in which a chopping state of the second output buffer for each frame is set.

[0022] The current consumption when the offset direction of the output voltage between the first output buffer and the second output buffer connected to the same data line is the same may be smaller than the current consumption when the offset direction of the output voltage is opposite.

[0023] The display panel may include pixels connected to the data lines and each pixel having a light emitting diode.

[0024] The first output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state.

[0025] The first output buffer may have a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer may have a negative offset in the negative chopping state and a positive offset in the positive chopping state. [Effects of the Invention]

[0026] In the present invention, in the upper and lower data drivers of a double bank structure, when the upper and lower output buffers arranged for each channel are driven by a chopping method, the chopping state of the output buffers can be adjusted so that the output voltage offset between the upper output buffer and the lower output buffer for each channel has the same direction.

[0027] This allows the upper and lower output buffers for each channel to output the same data voltage in the offset direction, thereby reducing or eliminating the difference in output voltage between the upper and lower ends of the channels.

[0028] As a result, the overcurrent caused by the difference in the output voltage of the channels can be reduced or eliminated, so that power consumption can be reduced, low-power driving becomes possible, and damage to the driving circuit due to the overcurrent can be prevented. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. [Figure 2]FIG. 1 is a circuit diagram illustrating an example of a pixel according to an embodiment of the present invention. [Figure 3] 1 is a diagram illustrating a schematic configuration of a gate driver of a display device according to an embodiment of the present invention. [Figure 4] 4 is a timing diagram illustrating an example of a driving signal output from a gate driver according to an embodiment of the present invention; FIG. [Figure 5] 1 is a cross-sectional view schematically illustrating an example of a cross-sectional structure of a display panel according to an embodiment of the present invention. [Figure 6] 1 is a diagram illustrating a configuration of a data driver having a double bank structure according to an embodiment of the present invention; [Figure 7] 4A and 4B are diagrams illustrating a positive (+) chopping state and a negative (-) chopping state of an output buffer in a data driver according to an embodiment of the present invention. [Figure 8] 10 is a diagram illustrating a case where the directions of output offsets are opposite to each other between a first output buffer and a second output buffer according to an embodiment of the present invention. FIG. [Figure 9] 10A and 10B are diagrams illustrating an example of offset values ​​of output voltages before adjustment of the offset directions of the first output buffer and the second output buffer in accordance with an embodiment of the present invention, the first output buffer and the second output buffer being driven by a chopping method. [Figure 10] 10 is a diagram showing an example of an offset value of an output voltage by chopping driving of the first output buffer and the second output buffer after adjusting the offset direction of the first output buffer and the second output buffer according to an embodiment of the present invention. FIG. [Figure 11] 10 is a diagram illustrating an adjustment device and a data driver used in a test process for inspecting and adjusting the offset direction of a first output buffer and a second output buffer of a channel according to an embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0030] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed description of the embodiments in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. However, the embodiments are provided so that the disclosure of the present invention will be complete and so that those skilled in the art will be able to fully understand the scope of the invention, and the present invention is defined by the scope of the claims.

[0031] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples and are not intended to limit the present invention. The same reference numerals refer to the same components throughout the specification.

[0032] Furthermore, when describing the present invention, if a detailed description of related prior art is deemed to obscure the gist of the present invention, such detailed description will be omitted. When terms such as "comprise," "include," "have," "have," or "become," other parts may be added unless "only" is also used. Furthermore, when a component is described in the singular, it may be interpreted as being plural unless otherwise expressly stated. Furthermore, when interpreting a component, a margin of error is included even if there is no explicit statement. For example, when describing the positional relationship between two components using terms such as "adjacent" or "adjacent," one or more other components may be located between the two components unless the term "directly" or "directly" is used. Furthermore, when describing a temporal relationship using terms such as "after," "following," "next," or "before," a non-contiguous relationship may be included unless the term "directly" or "immediately" is used. Furthermore, although terms such as "first" and "second" are used to distinguish between components, the components are not limited to such terms. Therefore, the first component referred to below may also be the second component within the technical spirit of the present invention.

[0033] The features of the various embodiments of the present invention may be partially or entirely combined or combined, and various technical interlocking and driving mechanisms may be possible. In addition, the various embodiments may be implemented independently or in conjunction with each other.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Meanwhile, in the following embodiments, the same or similar components are denoted by the same or similar reference numerals, and a detailed description thereof may be omitted.

[0035] Fig. 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention, Fig. 2 is a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present invention, Fig. 3 is a diagram schematically illustrating a configuration of a gate driver of a display device according to an embodiment of the present invention, and Fig. 4 is a timing diagram schematically illustrating an example of a driving signal output from the gate driver according to an embodiment of the present invention.

[0036] Before going into a detailed description, the display device 10 according to this embodiment includes a light-emitting display device having light-emitting diodes, and can include any display device to which data driving of a double bank structure is applied.

[0037] For convenience of explanation, the display device 10 in this embodiment will be described as an organic light-emitting display device.

[0038] 1 to 4, a display device 10 of this embodiment may include a display panel 100 and a driving circuit unit for driving the display panel 100.

[0039] Here, the driving circuit unit may include, for example, a gate driver (or gate driving circuit) 210, a data driver (or data driving circuit) 220, and a timing control unit (or timing control circuit) 240. In addition, the driving circuit unit may include a power supply unit (or power circuit) 280 that supplies power necessary to drive the display panel 100, the gate driver 210, the data driver 220, and the timing control unit 240.

[0040] The display panel 100 can include a display area AA that displays an image, and a non-display area NA that is disposed outside the display area AA (or that surrounds the display area AA).

[0041] In the display area AA, a plurality of pixels P can be arranged in a matrix along a plurality of horizontal lines (or row lines) and a plurality of vertical lines (or column lines).

[0042] Here, the plurality of pixels P may be of different colors, for example, red pixels, green pixels, and blue pixels that respectively display red, green, and blue, but are not limited thereto.

[0043] In the display panel 100, any signal wiring for transmitting a drive signal for driving the pixel P can be formed on the substrate.

[0044] For example, a plurality of data lines DL for transmitting data signals (or data voltages) of video signals may extend along the vertical direction and be connected to pixels P on corresponding vertical lines.

[0045] Furthermore, gate lines GL that transmit gate signals (or gate voltages) may extend along the horizontal direction and be connected to pixels P on a corresponding horizontal line.

[0046] In this embodiment, a plurality of gate signals, such as the first scan signal SC1 to the fourth scan signal SC4 and the light emission control signal EM, can be used to drive each pixel P. Therefore, a plurality of gate lines GL can be used to transmit the plurality of gate signals, such as the first scan line SCL1 to the fourth scan line SCL4 and the light emission control lines EML1 and EML2.

[0047] In this manner, the pixels P can be defined by a plurality of data lines DL and gate lines GL that intersect with each other.

[0048] Each pixel P is a light-emitting element and can include a light-emitting diode OD, a plurality of transistors for driving the light-emitting diode OD, and at least one capacitor.

[0049] On the other hand, in this embodiment, for convenience of explanation, an 8T1C structure in which the pixel P is provided with eight transistors T1 to T7 and DT, and one capacitor Cst, as shown in FIG. 2, is taken as an example.

[0050] Referring to FIG. 2, a pixel P may include a plurality of switching transistors, ie, a first transistor T1 to a seventh transistor T7, a driving transistor DT, a storage capacitor Cst, and a light emitting diode OD.

[0051] Each of the first transistor T1 to the seventh transistor T7 and the driving transistor DT may include a first electrode, a second electrode, and a gate electrode, one of which may be a source electrode and the other of which may be a drain electrode.

[0052] Each of the first transistor T1 to the seventh transistor T7 and the drive transistor DT may be a P-type transistor or an N-type transistor. Meanwhile, in FIG. 2, the second transistor T2 to the sixth transistor T6 are P-type transistors, the first transistor T1 and the seventh transistor T7 are N-type transistors, and the drive transistor DT is a P-type transistor, but this is not limiting. For example, the drive transistor DT may be an N-type transistor.

[0053] The first through seventh transistors T1 through T7 and the driving transistor DT may include semiconductor layers of the same material or different materials. For example, some of the first through seventh transistors T1 through T7 and the driving transistor DT may include one of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, and other parts of the first through seventh transistors T1 through T7 and the driving transistor DT may include one of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, or another semiconductor layer.

[0054] On the other hand, oxide semiconductors have good off-current characteristics and can have characteristics suitable for switching transistors, so at least one of the first transistor T1 to the seventh transistor T7 can include an oxide semiconductor layer. Furthermore, polycrystalline silicon has excellent mobility, so the driving transistor DT can include a polycrystalline silicon layer. The first transistor T1 to the seventh transistor T7 and the driving transistor DT can also be configured in other forms. For example, the driving transistor DT can include an oxide semiconductor layer.

[0055] 2 (more specifically, an odd-numbered horizontal line or an even-numbered horizontal line constituting the nth horizontal line) is provided from a corresponding nth stage in the gate driver 210. For example, four scan signals, i.e., first to fourth scan signals SC1 to SC4: SC1(n) to SC4(n), and two light emission control signals, i.e., first and second light emission control signals EM1, EM2: EM1(n), EM2(n), may be provided. In this case, first to fourth scan lines SCL1 to SCL4 and first and second light emission control lines EML1, EML2 may be arranged in the display area AA and connected to the nth stage to transmit the first to fourth scan signals SC1(n) to SC4(n) and the first and second light emission control signals EM1(n), EM2(n) to the pixels P. Alternatively, the gate driver 210 may be configured to provide one light emitting control signal instead of the two light emitting control signals EM1(n) and EM2(n).

[0056] The first transistor T1 can function as a sampling transistor, the second transistor T2 as a data supply transistor, the third and fourth transistors T3 and T4 as light-emitting control transistors, the fifth transistor T5 as a bias transistor, the sixth transistor T6 as a reset transistor (or a first initialization transistor), and the seventh transistor T7 as an initialization transistor (or a second initialization transistor).

[0057] The light emitting diode OD may include an anode and a cathode, the anode of the light emitting diode OD being connected to the fifth node N5, and the cathode being able to receive the low potential driving voltage EVSS.

[0058] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current to the light emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0059] The first transistor T1 includes a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving the first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1, and a data voltage Vdata can be applied (or written or sampled) to the gate electrode.

[0060] The storage capacitor Cst may be connected between the first node N1 and the fourth node N4, and may store or hold the high potential driving voltage EVDD.

[0061] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) to transmit the data voltage Vdata to the second node N2.

[0062] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) are connected between the high-potential drive voltage EVDD and the light-emitting diode OD, and can form a path through which the drive current generated by the drive transistor DT travels.

[0063] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving a high-potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving a first light-emitting control signal EM1(n).

[0064] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting diode OD), and a gate electrode receiving a second light-emitting control signal EM2(n).

[0065] The third and fourth transistors T3 and T4 are turned on in response to the corresponding first and second light-emitting control signals EM1(n) and EM2(n), and a driving current is provided to the light-emitting diode OD, so that the light-emitting diode OD can emit light at a brightness corresponding to the driving current.

[0066] The fifth transistor T5 may include a first electrode connected to a bias voltage line VobsL that transmits a bias voltage Vobs, a second electrode connected to a second node N2, and a gate electrode that receives a third scan signal SC3(n).

[0067] The sixth transistor T6 may include a first electrode connected to a reset voltage line (or a first initialization voltage line) VarL that transmits an anode reset voltage (or a first initialization voltage) Var, a second electrode connected to a fifth node N5, and a gate electrode that receives a third scan signal SC3(n).

[0068] The fifth and sixth transistors T5 and T6 may be turned on in response to the third scan signal SC3(n), and the bias voltage Vobs may be applied to the second node N2 and the anode reset voltage Var may be applied to the fifth node N5 (i.e., the anode of the light emitting diode OD).

[0069] The seventh transistor T7 may include a first electrode connected to an initialization voltage line ViniL that transmits an initialization voltage Vini, a second electrode connected to a first node N1, and a gate electrode that receives a fourth scan signal SC4(n).

[0070] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n) to apply an initialization voltage Vini to initialize the gate electrode of the drive transistor DT. The high-potential drive voltage EVDD applied to the storage capacitor Cst can cause unnecessary charges to remain on the gate electrode of the drive transistor DT. Therefore, applying the initialization voltage Vini to the gate electrode of the drive transistor DT via the seventh transistor T7 can initialize the remaining charges.

[0071] The 8T1C structure of the pixel P described above is an example, and the pixel P of this embodiment may have other structures.

[0072] 1, the timing controller 240 processes image data Do input from the host system to suit the size and resolution of the display panel 100 and supplies the processed data to the data driver 220. The timing controller 240 generates gate control signals GCS and data control signals DCS using externally input synchronization signals, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal HSY, and a vertical synchronization signal VSY. The generated gate control signals GCS and data control signals DCS are supplied to the gate driver 210 and the data driver 220, respectively, to control the gate driver 210 and the data driver 220.

[0073] The timing control unit 240 may be configured in combination with various processors, such as a microprocessor, a mobile processor, or an application processor, depending on the device in which it is implemented.

[0074] On the other hand, the host system may correspond to, for example, a drive system that drives an electronic device in which the display device 10 is employed. Such an electronic device may be, for example, any one of a TV (television) navigation system, a monitor, a mobile device, and a wearable device.

[0075] The gate driver 210 receives a gate control signal GCS from the timing controller 240, generates gate signals, and sequentially applies the gate signals to the gate lines GL. For example, the gate signals may be sequentially output from the top to the bottom in the vertical direction.

[0076] The gate driver 210 may be disposed on at least one side of the display area AA, for example. In this embodiment, the gate driver 210 is configured to include a first gate driver 211 and a second gate driver 212 disposed on both sides of the display area AA, for example, on the left and right sides.

[0077] The gate driver 210 may have, for example, a GIP (gate-in-panel) structure and may be formed directly in the non-display area NA on the substrate of the display panel 100. In this case, the gate driver 210 may be formed during the process of forming the elements of the display panel 100.

[0078] The gate driver 210 of the GIP structure may include, for example, a first scan drive circuit that sequentially outputs first scan signals SC1, a second scan drive circuit that sequentially outputs second scan signals SC2, a third scan drive circuit that sequentially outputs third scan signals SC3, a fourth scan drive circuit that sequentially outputs fourth scan signals SC4, a first light-emitting drive circuit that sequentially outputs first light-emitting control signals EM1, and a second light-emitting drive circuit that sequentially outputs second light-emitting control signals EM2.

[0079] Each of the first to fourth scan drive circuits and the first and second light emission drive circuits can be configured with a shift register including a plurality of stages that output corresponding signals.

[0080] The gate driver 210 will be described with reference to Fig. 3. Fig. 3 shows a portion of the gate driver 210, and for convenience of explanation, shows the configuration of the portion of the gate driver 210 that drives the nth horizontal line consisting of the nth odd horizontal line (or the 2n-1th horizontal line) and the nth even horizontal line (or the 2nth horizontal line) in the display area AA.

[0081] The first gate driver 211 of the gate driver 210 may be provided with, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) that respectively constitute the first scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) that respectively constitute the first light-emitting drive circuit and the second light-emitting drive circuit; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) that constitute the second scan drive circuit.

[0082] In addition, the second gate driver 212 of the gate driver 210 may be provided with, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) that respectively constitute the first scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) that respectively constitute the first light-emitting drive circuit and the second light-emitting drive circuit; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) that constitute the second scan drive circuit.

[0083] The arrangement of the first scan stage SSC1(n) through the fourth scan stage SSC4(n) and the first light-emitting stage SEM1(n) and the second light-emitting stage SEM2(n) shown in FIG. 3 is an example, and they can be arranged in various combinations in the first gate driver 211 and the second gate driver 212.

[0084] The first scan stage SSC1(n) generates a first scan signal SC1(n) and outputs it to the corresponding first scan line SCL1, so that the pixel P_O(n) on the nth odd-numbered horizontal line and the pixel P_E(n) on the nth even-numbered horizontal line can receive the first scan signal SC1(n) in common.

[0085] The odd-numbered second scan stages SSC2_O(n) can generate odd-numbered second scan signals SC2_O(n) and output them to the corresponding odd-numbered second scan lines SCL2, and the even-numbered second scan stages SSC2_E(n) can generate even-numbered second scan signals SC2_E(n) and output them to the corresponding even-numbered second scan lines SCL2, so that the pixel P_O(n) on the nth odd-numbered horizontal line can receive the odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) on the nth even-numbered horizontal line can receive the even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) have different timings. For example, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) may be applied to the data write interval of the nth odd-numbered horizontal line and the data write interval of the subsequent nth even-numbered horizontal line.

[0086] The third scan stage SSC3(n) generates a third scan signal SC3(n) and outputs it to the corresponding third scan line SCL3, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can receive the third scan signal SC3(n) in common.

[0087] The fourth scan stage SSC4(n) generates a fourth scan signal SC4(n) and outputs it to the corresponding fourth scan line SCL4, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can receive the fourth scan signal SC4(n) in common.

[0088] The first light-emitting stage SEM1(n) generates a first light-emitting control signal EM1(n) and outputs it to the corresponding first light-emitting control signal EML1, so that the pixels P_O(n) and P_E(n) of the n-th odd and even horizontal lines can commonly receive the first light-emitting control signal EM1(n).

[0089] The second light-emitting stage SEM2(n) generates a second light-emitting control signal EM2(n) and outputs it to the corresponding second light-emitting control signal EML2, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can commonly receive the second light-emitting control signal EM2(n).

[0090] Meanwhile, referring to FIG. 3, a bias voltage line VobsL, a reset voltage line VarL, and an initialization voltage line ViniL can be arranged between the gate driver 210 configured as described above and the display area AA.

[0091] The bias voltage wiring VobsL, reset voltage wiring VarL, and initialization voltage wiring ViniL can supply the bias voltage Vobs, anode reset voltage Var, and initialization voltage Vini, respectively, from the power supply unit 280 to the pixels P in the display area AA.

[0092] 3, the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL are shown to be located on only one of the left and right sides of the display area AA, but this is not limitative and they may be located on both sides, and even if they are located on one side, they are not limited to either the left or right side.

[0093] Furthermore, referring to FIG. 3, one or more optical areas OA1, OA2 can be arranged in the display area AA.

[0094] The one or more optical regions OA1 and OA2 may be arranged to overlap one or more optical-electronic devices, such as a photographing device such as a camera (or image sensor) or a detection sensor such as a proximity sensor or an illuminance sensor. The one or more optical regions OA1 and OA2 may have a light-transmitting structure and a transmittance above a predetermined level for the operation of the optical-electronic devices. In other words, the number of pixels P per unit area in the one or more optical regions OA1 and OA2 may be smaller than the number of pixels P per unit area in the general area of ​​the display area AA excluding the optical regions OA1 and OA2. That is, the resolution of the one or more optical regions OA1 and OA2 may be lower than the resolution of the general area within the display area AA.

[0095] Referring again to FIG. 1, the data driver 220 receives the image data Do and the data control signal DSC from the timing controller 240, converts the image data Do into a data voltage Vdata of analog image data in accordance with the data control signal DCS, and outputs the data voltage Vdata to the corresponding data line DL.

[0096] The data driver 220 may have a double bank structure that outputs the data voltage Vdata to both ends of the data line DL.

[0097] In this regard, the data driver 220 may be configured with a first data driver 221 arranged (or connected) on one side of the display panel 100 (or display area AA), for example, on the upper side (or upper row), and a second data driver 222 arranged (or connected) on the other side of the display panel 100, for example, on the lower side (or lower row).

[0098] Each of the first data driver 221 and the second data driver 222 may be configured to include at least one data IC. In this case, the data IC may be mounted on a flexible printed circuit film and connected to the non-display area NA on one side of the corresponding display panel 100, or may be directly mounted in the non-display area NA. In this embodiment, as described below, the first data driver 221 and the second data driver 222 each include a plurality of data ICs (DICs in FIG. 6) configured with COF.

[0099] The first data driver 221 and the second data driver 222 may have channels (or output channels) corresponding to and connected to, for example, each of the plurality of data lines DL provided in the display panel 100. The first data driver 221 may have a channel for outputting a corresponding data voltage Vdata to the upper end of each data line DL. The second data driver 222 may have a channel for outputting a corresponding data voltage Vdata to the lower end of each data line DL.

[0100] In this manner, the first data driver 221 and the second data driver 222 disposed on the upper and lower sides of the display panel 100, respectively, may be provided with the image data Do output from the timing control unit 240 in common (or the same).

[0101] As a result, the same data voltage Vdata output from the first data driver 221 and the second data driver 222 can be applied to the upper and lower ends of each data line DL.

[0102] In this way, in the double bank structure, the data line DL receives the same data voltage Vdata at both ends, so that the data voltage Vdata can be stably supplied to the inside of the display area AA.

[0103] As described above, each of the first data driver 221 and the second data driver 222 that realizes the data driving of the double bank structure can output the data voltage Vdata in a so-called chopping manner.

[0104] In chopping drive, an operational amplifier (OP-AMP) arranged at the output terminal of each channel and constituting an output buffer that outputs a data voltage Vdata to the data line DL switches between a positive feedback state (or a positive (+) feedback state) and a negative feedback state (or a negative (-) feedback state) every frame. For example, the output buffer has a positive feedback state (or a negative feedback state) in the nth frame and a negative feedback state (or a positive feedback state) in the (n+1)th frame, and these positive feedback and negative feedback states are alternately repeated every frame.

[0105] Here, the positive feedback state in which the output terminal of the output buffer is connected to the non-inverting (+) input terminal can be defined as a negative (-) chopping state, and the negative feedback state in which the output terminal of the output buffer is connected to the inverting (-) input terminal can be defined as a positive (+) chopping state.

[0106] Driving the output buffer while switching between a positive feedback state and a negative feedback state in this way is called chopping method driving.

[0107] This chopping method takes into account the characteristics of the output difference of the operational amplifiers that make up the output buffer, and by using the chopping method to alternate between positive feedback and negative feedback states, the output difference can be converged to essentially zero.

[0108] In this regard, due to the characteristics of the output buffer, the output voltages in the positive feedback state and the negative feedback state may have opposite offset values. For example, the positive feedback state (or the negative feedback state) may have a positive offset (for example, a +10 mV offset), and the negative feedback state (or the positive feedback state) may have a negative offset (for example, a -10 mV offset).

[0109] In this way, the output buffer can have its output voltages substantially offset in opposite directions between the positive and negative feedback states.

[0110] To cancel out the unidirectional offset in the positive or negative feedback state, a chopping method can be adopted in which the output buffer is alternately driven in the positive and negative feedback states. As a result, the opposing offset values ​​in the positive and negative feedback states are canceled out, and the average offset value of the output voltage can be reduced to zero.

[0111] Therefore, when the output buffer is driven using the chopping method described above, the difference in the output voltage of the channel between the upper and lower ends is canceled out, and the desired output voltage can be output evenly to the data line DL.

[0112] In this embodiment, as described above, a double bank structure is adopted, so that a first output buffer, which is the output buffer of the first data driver 221, is connected to the upper end of the data wiring DL, and a second output buffer, which is the output buffer of the second data driver 222, is connected to the lower end of the data wiring DL.

[0113] As a result, the first output buffer at the upper end and the second output buffer at the lower end are driven in a chopping manner, and the feedback state is inverted every frame.

[0114] However, in some cases, the output offset direction of the first output buffer and the output offset direction of the second output buffer may be opposite to each other. For example, the output offset of the first output buffer may switch like "(+), (-), (+), (-)", and conversely, the output offset of the second output buffer may switch like "(-), (+), (-), (+)".

[0115] In such a case, the first output buffer and the second output buffer have offset values ​​in opposite directions for each frame, which causes a difference in output voltage between the first output buffer and the second output buffer, which can result in an overcurrent caused by the difference in output voltage between the first output buffer and the second output buffer.

[0116] In this case, the overcurrent increases current consumption (i.e., power consumption), and in some cases, the driving circuits of the data drivers 221 and 222 may be damaged.

[0117] In contrast to this, in this embodiment, the first output buffer on the upper side and the second output buffer on the lower side can be set and driven so as to have the same offset direction for each channel.

[0118] This reduces or eliminates the output voltage difference between the first and second output buffers of the channel, thereby reducing or eliminating the overcurrent caused by the output voltage difference, thereby reducing power consumption, enabling low-power driving, and preventing damage to the driving circuit due to overcurrent.

[0119] In this way, in the double bank structure, the difference in output voltage between the upper and lower corresponding channels (or between the output buffers of the corresponding channels) driven by the chopping method can be improved. Here, the corresponding channels are the channels of the first data driver 221 and the second data driver 222 connected to the upper and lower sides of the same data line DL.

[0120] 1 again, the power supply unit 280 uses, for example, a DC-DC converter to generate DC power necessary to drive the pixel array and the driving circuit unit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc.

[0121] The power supply unit 280 receives, for example, a power voltage Vcc, which is a drive voltage for driving the display device 10, from a host system, and can generate DC voltages such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, a high-potential drive voltage EVDD, and a low-potential drive voltage EVSS. The gate low voltages VGL and VEL and the gate high voltages VGH and VEH can be supplied to a level shift and gate driver 210 (not shown). The high-potential drive voltage EVDD and the low-potential drive voltage EVSS can be supplied in common to pixels P in the display panel 100.

[0122] The gate signals applied to the pixels P of the display panel 100 will be described with reference to Fig. 4. For convenience of explanation, Fig. 4 does not show the first and second light-emitting control signals EM(n) individually, but shows one representative light-emitting control signal EM(n) as an example.

[0123] In every frame, pixel P can operate in at least one bias section Tobs1, Tobs2, initialization section Ti, sampling section Ts, and light-emitting section Ton, but this is just an example and is not limited to this order.

[0124] At least one bias section Tobs1, Tobs2 is a section in which an on-bias stress operation (OBS) is performed, in which a bias voltage Vobs is applied. At this time, the light-emitting control signal EM(n), for example, the first and second light-emitting control signals EM1(n) and EM2(n), becomes a high voltage, and the third transistor T3 and the fourth transistor T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) become a low voltage, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2(n) (or the odd and even second scan signals) becomes a high voltage, and the second transistor T2 is turned off.

[0125] The third scan signal SC3(n) becomes a low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the drive transistor DT connected to the second node N2.

[0126] Here, by supplying the bias voltage Vobs to the third node N3, which is the drain electrode of the drive transistor DT, the charging time or charging delay of the voltage at the fifth node N5, which is the anode of the light emitting diode OD, during the light emitting period Ton can be reduced, and the drive transistor DT will be maintained in a further saturated state.

[0127] For example, as the bias voltage Vobs increases, the voltage at the third node N3, which is the drain electrode of the driving transistor DT, increases, and the gate-source voltage or drain-source voltage of the driving transistor DT may decrease. Therefore, it is preferable that the bias voltage Vobs is at least greater than the data voltage Vdata.

[0128] At this time, the magnitude of the drain-source current passing through the drive transistor DT may decrease, reducing the stress on the drive transistor DT under positive bias stress and eliminating the charging delay of the voltage at the third node N3. In other words, performing an on-bias stress operation (OBS) before sampling the threshold voltage of the drive transistor DT can mitigate the hysteresis of the drive transistor DT.

[0129] The initialization section Ti is a section in which the voltage of the gate electrode of the driving transistor DT is initialized.

[0130] The first scan signal SC1(n) through the fourth scan signal SC4(n) and the light emission control signal EM(n) become high voltages, and the first transistor T1 and the seventh transistor T7 are turned on. The second transistor T2 through the sixth transistor T6 are turned off. When the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the drive transistor DT connected to the first node N1 are initialized to the initialization voltage Vini.

[0131] The sampling period Ts may be a period in which the threshold voltage of the driving transistor DT and the data voltage Vdata are sampled.

[0132] The first scan signal SC1(n), the third scan signal SC3(n), and the light-emitting control signal EM(n) are at high voltages, and the second scan signal SC2(n) and the fourth scan signal SC4(n) are at low voltages. As a result, the third transistor T3 through the seventh transistor T7 are turned off, the first transistor T1 is maintained in the on state, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on, the data voltage Vdata is applied to the drive transistor DT, and the first transistor T1 is diode-connected between the first node N1 and the third node N3, thereby sampling the threshold voltage Vth of the drive transistor DT.

[0133] The light emitting section Ton is a section in which the sampled threshold voltage Vth is cancelled out and the light emitting diode OD is made to emit light with a drive current corresponding to the sampled data voltage Vdata.

[0134] The light emission control signals EM(n), for example, the first and second light emission control signals EM1(n) and EM2(n), become low voltage, and the third transistor T3 and the fourth transistor T4 perform a turn-on operation.

[0135] When the third transistor T3 is turned on, the high-potential driving voltage EVDD connected to the fourth node N4 is applied to the first electrode of the driving transistor DT connected to the second node N2 via the third transistor T3. The driving current supplied from the driving transistor DT to the light emitting diode OD via the fourth transistor T4 is independent of the threshold voltage of the driving transistor DT, and the threshold voltage of the driving transistor DT is compensated for, allowing operation.

[0136] An example of the edge structure of the display panel 100 according to this embodiment will be described below with reference to Fig. 5. Fig. 5 is a cross-sectional view that schematically shows an example of the cross-sectional structure of a display panel according to an embodiment of the present invention.

[0137] For convenience of explanation, two thin film transistors TFT1 and TFT2 are shown in pixel P in display area AA in Figure 5. Here, the thin film transistor TFT1 located closer to the substrate 101 and at a relatively lower position is referred to as the first thin film transistor TFT1, which may be a polycrystalline silicon thin film transistor. The thin film transistor TFT2 located further from the substrate 101 and at a relatively higher position is referred to as the second thin film transistor TFT2, which may be an oxide thin film transistor.

[0138] Meanwhile, the first thin film transistor TFT1 may be, but is not limited to, a driving transistor (DT in FIG. 2). For convenience of explanation, FIG. 5 shows an example in which the first thin film transistor TFT1 is connected to a light emitting diode OD. The second thin film transistor TFT2 may be, but is not limited to, one of the first to seventh transistors (T1 to T7 in FIG. 2) which are switching thin film transistors, more specifically, a transistor connected to a storage capacitor Cst.

[0139] The substrate 101 can be made of, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) so that the display panel 100 can have flexible properties.

[0140] Here, when the substrate 101 is made of a glass substrate, the substrate 101 may have a thickness of, for example, about 0.2 mm.

[0141] On the other hand, when the substrate 101 is made of a plastic substrate, for example, the substrate 101 may include at least one polyimide layer.

[0142] The first thin film transistor TFT1 may include a first semiconductor layer 105 disposed on the substrate 101, a first gate electrode 115 overlapping the semiconductor layer 105 with a first insulating layer 110 interposed therebetween, and a first source electrode 151 and a first drain electrode 152 located above the first gate electrode 115 and on the fourth insulating layer 145. Here, the first semiconductor layer 105 may be formed of, but is not limited to, polycrystalline silicon.

[0143] The first semiconductor layer 105 includes a central channel region and source and drain regions on either side of the channel region. The first source electrode 151 and the first drain electrode 152 can be connected to the source and drain regions of the first semiconductor layer 105 via a first contact hole 156 and a second contact hole 157 formed in the insulating layers 110, 120, 125, 135, and 145 located below the first source electrode 151 and the first drain electrode 152.

[0144] A second insulating layer 120 may be formed on the first gate electrode 115 of the first thin film transistor TFT1.

[0145] A first interlayer insulating layer 125 may be formed on the second insulating layer 120. A second thin film transistor TFT2 may be formed on the first interlayer insulating layer 125.

[0146] The second thin film transistor TFT2 may include a second semiconductor layer 130 on the first interlayer insulating layer 125, a second gate electrode 140 overlapping the second semiconductor layer 130 with a third insulating layer 135 interposed therebetween, and a second source electrode 153 and a second drain electrode 154 located above the second gate electrode 140 and on the fourth insulating layer 145. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited to this.

[0147] The second semiconductor layer 130 includes a central channel region and source and drain regions on either side of the channel region. The second source electrode 153 and the second drain electrode 154 can be connected to the source and drain regions of the second semiconductor layer 130 via a third contact hole 158 and a fourth contact hole 159 formed in the insulating layers 135 and 145 located below the second semiconductor layer 130.

[0148] A second interlayer insulating layer (or a first planarizing layer) 160 may be formed on the second thin film transistor TFT2.

[0149] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the fourth insulating layer 145 may be made of an inorganic insulating material such as silicon nitride or silicon oxide, but are not limited thereto.

[0150] The first interlayer insulating layer 125 and the second interlayer insulating layer 160 may be made of an organic insulating material such as photoacrylic or benzocyclobutene, but are not limited thereto.

[0151] A connection electrode 162 may be formed on the second interlayer insulating layer 160. The connection electrode 162 may be connected to the first drain electrode 152 via a contact hole 161 formed in the second interlayer insulating layer 160.

[0152] A third interlayer insulating layer (or a second planarizing layer) 163 may be formed on the connection electrode 162. The third interlayer insulating layer 163 may be made of an organic insulating material such as photoacrylic or benzocyclobutene, but is not limited thereto.

[0153] On the third interlayer insulating layer 163, a light emitting diode OD and a bank 165 may be formed.

[0154] The light-emitting diode OD may include an anode (or first electrode) 171 , a light-emitting layer 172 , and a cathode (or second electrode) 173 .

[0155] The anode 171 can be connected to the connection electrode 162 via a contact hole 164 formed in the third interlayer insulating layer 163 .

[0156] The bank 165 may be disposed along the boundary of the pixel P and may be formed to cover the edge of the anode 171. An emitting layer 172 may be formed on the anode 171 exposed through the opening in the bank 165.

[0157] The cathode 173 is formed on the light-emitting layer 172 and can receive a low-potential driving voltage (EVSS in FIGS. 1 and 2).

[0158] A sealing layer 180 may be formed on the cathode 173. The sealing layer 180 may include, but is not limited to, at least one inorganic sealing layer and at least one organic sealing layer. In the present invention, a structure of the sealing layer 180 in which a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 are sequentially stacked will be exemplified.

[0159] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 is formed, and may be formed to surround the top, bottom, and side surfaces of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light emitting diode OD. The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0160] The second encapsulating layer 182 functions as a buffer to relieve stress between layers due to warpage of the display device (10 in FIG. 1) and can flatten steps between layers. The second encapsulating layer 182 can be formed on the substrate 101 on which the first encapsulating layer 181 is formed, using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbonate (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulating layer 182 is formed using an inkjet method, a dam (DAM) can be disposed in the non-display area NA to prevent the liquid second encapsulating layer 182 from spreading to the edge of the substrate 101. The dam (DAM) can be disposed closer to the edge of the substrate 101 than the second encapsulating layer 182. The dam (DAM) can prevent the second encapsulating layer 182 from spreading to the pad area on the outermost side of the substrate 101 where the conductive pads are disposed.

[0161] The dam DAM is designed to prevent diffusion of the second sealing layer 182, but if the second sealing layer 182 is formed in a process so that the height of the dam DAM exceeds the height of the dam DAM, the second sealing layer 182, which is an organic layer, may be exposed to the outside, allowing moisture and the like to easily penetrate into the light emitting device. For this reason, at least 10 or more dam DAMs may be stacked to form the dam DAM, but this is not limited to this.

[0162] The dam DAM can be formed simultaneously with the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163. The lower layer of the dam DAM can be formed when the first interlayer insulating layer 125 is formed, and the upper layer of the dam DAM can be formed when the second interlayer insulating layer 160 and the third interlayer insulating layer 163 are formed, so that they are stacked to form a three-layer structure. As another example, the dam DAM can be formed using one or two of the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163.

[0163] Therefore, the dam DAM may be made of the same material as the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163, but is not limited to this.

[0164] The dam DAM can be formed so as to overlap the low potential drive voltage wiring VSSL. For example, in the non-display area NA, the low potential drive voltage wiring VSSL can be formed in a layer below the area where the dam DAM is located.

[0165] The low potential driving voltage wiring VSSL and the gate driver 210 having a GIP structure are formed along the outer side of the display panel 100, and the low potential driving voltage wiring VSSL can be located outside the gate driver 210. The low potential driving voltage wiring VSSL is connected to the cathode 173 and can apply a low potential driving voltage EVSS (see FIG. 2). Although the gate driver 210 in the drawings is simply shown in plan and cross section, it can have the same structure as the first and / or second thin film transistors TFT1 and / or TFT2 in the display area AA.

[0166] A touch layer (or touch element layer) 190 may be disposed on the encapsulation layer 180. A touch buffer film 191 in the touch layer 190 may be located between the touch sensor metal, including the touch electrode connecting lines 192, 194 and the touch electrodes 195, 196, and the cathode 173 of the light-emitting diode OD.

[0167] The touch buffer film 191 can block chemicals (such as a developing solution or an etching solution) used in the manufacturing process of the touch sensor metal disposed on the touch buffer film 191, or external moisture, from penetrating into the light-emitting layer 172 containing organic matter. As a result, the touch buffer film 191 can prevent damage to the light-emitting layer 172, which is sensitive to chemicals or moisture.

[0168] According to the structure of the mutual capacitance touch sensor, touch electrodes 195 and 196 are disposed on a touch buffer film 191, and the touch electrodes 195 and 196 may be disposed so as to cross each other.

[0169] The touch electrode connecting lines 192 and 194 can electrically connect the touch electrodes 195 and 196. One of the touch electrode connecting lines 192 and 194 and the touch electrodes 195 and 196 can be located in different layers with the touch insulating layer 193 interposed therebetween. Also, one of the touch electrode connecting lines 192 and 194 and the other can be located in different layers with the touch insulating layer 193 interposed therebetween.

[0170] The touch electrode connection lines 192 and 194 are arranged so as to overlap with the bank 165, and this can prevent a decrease in the aperture ratio, but the present invention is not limited to this.

[0171] On the other hand, parts of the touch electrodes 195, 196 and parts of the touch electrode connection lines 192 can pass through the top and side surfaces of the sealing layer 180 and the top and side surfaces of the dam DAM, and can be electrically connected to a touch drive circuit (not shown) via touch pads 198, 199.

[0172] A part of the touch electrodes 195, 196 and a part of the touch electrode connecting line 192 can receive a touch driving signal from a touch driving circuit and transmit it to the touch electrodes 195, 196, and transmit the touch sensing signal sensed by the touch electrodes 195, 196 to the touch driving circuit.

[0173] For example, the driving IC (such as a data IC) of the data driver 220 including the touch driving circuit may be configured as a COF and connected to the non-display area NA of the substrate 101 of the display panel 100. In this case, the ends of the touch pads 198 and 199 are connected to the flexible circuit film on which the driving IC is mounted, and signals can be transmitted.

[0174] A touch protective film 197 may be disposed on the touch electrodes 195 and 196. In FIG. 5, the touch protective film 197 is shown disposed only on the touch electrodes 195 and 196, but is not limited thereto. The touch protective film 197 may extend to the front or rear of the dam DAM and may also be disposed on the touch electrode connecting line 192.

[0175] A color filter (not shown) may be further disposed on the encapsulation layer 180. The color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190.

[0176] Hereinafter, a structure and a method for improving the output voltage difference between the upper and lower corresponding channels (or between the output buffers of the corresponding channels) driven by the chopping method in the double-bank structure data driver 220 according to an embodiment of the present invention will be described in detail.

[0177] FIG. 6 is a diagram illustrating a configuration of a double-bank data driver according to an embodiment of the present invention, and FIG. 7 is a diagram illustrating a positive (+) chopping state and a negative (-) chopping state of an output buffer in the data driver according to an embodiment of the present invention.

[0178] Referring to Figures 6 and 7, the double-bank structure data driver 220 may include a first data driver 221 arranged on the upper side (or upper row) of one side of the display panel 100, and a second data driver 222 arranged on the lower side (or lower row) of the other side of the display panel 100.

[0179] Each of the first data driver 221 and the second data driver 222 may include at least one data IC (DIC) and a source board SPCB connected to the data IC (DIC). Meanwhile, in this embodiment, the first data driver 221 and the second data driver 222 each include a plurality of data ICs (DICs), for example, three data ICs (DICs).

[0180] Here, the data IC (DIC) provided in the first data driver 221 may be referred to as a first data IC (DIC1), and the data IC (DIC) provided in the second data driver 222 may be referred to as a second data IC (DIC2). Also, the source board SPCB provided in the first data driver 221 may be referred to as a first source board SPCB1, and the source board SPCB provided in the second data driver 222 may be referred to as a second source board SPCB2.

[0181] The signal output from the timing control unit 240 can be transmitted to the first data IC (DIC1) via the first source board SPCB1, and can also be transmitted to the second data IC (DIC2) via the second source board SPCB2.

[0182] In this embodiment, the data ICs (DICs) of the first data driver 221 and the second data driver 222 are configured as COFs and mounted on a flexible circuit film FCF.

[0183] In this case, the first data IC (DIC1) is mounted on the flexible circuit board FCF, which is connected to the top of the display panel 100 and connected to the first source board SPCB1. In other words, the first data IC (DIC1) can be electrically connected to the first source board SPCB1 and the display panel 100 via the flexible circuit board FCF.

[0184] Similarly, the second data IC (DIC2) is mounted on the flexible circuit board FCF, which is connected to the bottom of the display panel 100 and connected to the second source board SPCB2. In other words, the second data IC (DIC2) can be electrically connected to the second source board SPCB2 and the display panel 100 via the flexible circuit board FCF.

[0185] Meanwhile, the first data driver 221 (more specifically, the first source board SPCB1) may include a memory MEM (or a first memory MEM1), and the second data driver 222 (more specifically, the second source board SPCB2) may include a memory MEM (or a second memory MEM2). The memory MEMs arranged in the first data driver 221 and the second data driver 222 will be described in detail later.

[0186] The upper first data driver 221 (more specifically, the first data IC (DIC1)) can have, for example, a plurality of channels CH connected to the upper ends of each of a plurality of data lines DL provided in the display panel 100 and outputting the data voltage Vdata.

[0187] Similarly, the lower second data driver 222 (more specifically, the second data IC (DIC2)) may have a plurality of channels CH connected to the lower ends of the respective data lines DL and outputting the data voltage Vdata.

[0188] As such, the first data driver 221 and the second data driver 222 are substantially symmetrical in shape from top to bottom, and can output substantially the same data voltage Vdata to the corresponding channels CH.

[0189] Here, for convenience of explanation, the data voltage Vdata output from the first data driver 221 for each channel CH can be referred to as the first data voltage Vdata1, and the data voltage Vdata output from the second data driver 222 for each channel CH can be referred to as the second data voltage Vdata2.

[0190] In this way, by arranging the first data driver 221 and the second data driver 222 with a double bank structure on the upper and lower sides of the display panel 100, the first data voltage Vdata1 and the second data voltage Vdata2 output from the corresponding channel CH can be applied to the upper and lower ends of each data line DL.

[0191] The first data driver 221 (more specifically, the first data IC (DIC1)) may be formed with a first output buffer AMP1 that is an output buffer AMP that outputs a data voltage Vdata for each channel CH. Similarly, the second data driver 222 (more specifically, the second data IC (DIC2)) may be formed with a second output buffer AMP2 that is an output buffer AMP that outputs a data voltage Vdata for each channel CH.

[0192] As described above, the output buffers AMP1 and AMP2 formed in the first and second data drivers 221 and 222 can output the corresponding data voltages Vdata in a chopping manner.

[0193] In this regard, referring to FIG. 7 as an example, the output buffer AMP arranged in each channel CH of the first data driver 221 and the second data driver 222 can alternately operate in a negative feedback state (or a positive chopping state) and a positive feedback state (or a negative chopping state) in frame FR units.

[0194] For example, the output buffer AMP can be in a negative feedback state in the fth frame FR(f), and in the f+1th frame FR(f+1), the output buffer AMP can be in a positive feedback state. In this way, the output buffer AMP can operate by alternately repeating the negative feedback state and the positive feedback state for each frame FR.

[0195] Here, the positive feedback state in which the output terminal of the output buffer AMP is connected to the non-inverting (+) input terminal can be defined as a negative (-) chopping state, and the negative feedback state in which the output terminal of the output buffer AMP is connected to the inverting (-) input terminal can be defined as a positive (+) chopping state.

[0196] As described above, when the feedback state of the output buffer AMP, i.e., the chopping state, is switched every frame, the output voltage of the output buffer AMP is offset in either the positive or negative direction based on the input data voltage Vdata, which prevents the occurrence of output differences.

[0197] Due to the characteristics of the output buffer AMP, the output voltages in the positive feedback state and the negative feedback state can have opposite offset values. For example, in the positive feedback state (or the negative feedback state), a positive offset, for example, +10 mV, can be produced, and conversely, in the negative feedback state (or the positive feedback state), a negative offset, for example, -10 mV, can be produced.

[0198] In this way, the output voltages of the output buffer AMP can be offset in substantially opposite directions between the positive feedback state and the negative feedback state.

[0199] When a chopping method of driving the output buffer AMP, which alternately drives it between a positive feedback state and a negative feedback state, is adopted, the offset value in the positive feedback state and the offset value in the opposite negative feedback state cancel each other out, so the offset value of the average output voltage of the output buffer AMP can become zero (or can be reduced).

[0200] Therefore, by driving the output buffer AMP in a chopping manner, the difference in the output voltages of the output buffer AMP is cancelled out, and it is possible to output a data voltage Vdata with substantially zero offset.

[0201] On the other hand, in this embodiment, since a double bank structure is adopted, the output voltage of the first output buffer AMP1 of the first data driver 221 is applied to the upper end of the data line DL, and the output voltage of the second output buffer AMP2 of the second data driver 222 is applied to the lower end of the data line DL.

[0202] As a result, the first output buffer AMP1 at the upper end and the second output buffer AMP2 at the lower end are each driven by the chopping method, and the feedback state is switched in units of frames FR.

[0203] However, due to various factors, the offset direction (i.e., positive and negative offset direction) depending on the feedback state may not match between output buffers AMP. For example, one output buffer AMP may be positively offset in a positive feedback state and negatively offset in a negative feedback state, while another output buffer AMP may be negatively offset in a positive feedback state and positively offset in a negative feedback state.

[0204] Therefore, among the multiple channels CH, the direction of the output offset is the same between the first output buffer AMP1 and the second output buffer AMP2 arranged in some of the channels CH in the same feedback state (or the same frame FR), but between the first output buffer AMP1 and the second output buffer AMP2 arranged in other of the channels CH, the direction of the output offset may be opposite to each other in the same feedback state (or the same frame FR).

[0205] This will be described with reference to Fig. 8. Fig. 8 is a diagram schematically illustrating a case where the directions of the output offsets are opposite to each other between the first output buffer and the second output buffer according to an embodiment of the present invention.

[0206] FIG. 8 shows an example of a typical chopping-type driving method in which the first output buffer AMP1(m) and the second output buffer AMP2(m) of the m-th channel CH(m) connected to the upper and lower ends of the m-th data wiring DL(m) have the same feedback state, i.e., the same chopping state, in the same frame FR.

[0207] In addition, the first output buffer AMP1(m) has a positive offset, for example, an offset value of +10 mV, in a positive chopping state (i.e., a negative feedback state), and a negative offset, for example, an offset value of −10 mV, in a negative chopping state (i.e., a positive feedback state). Conversely, the second output buffer AMP2(m) has a negative offset, for example, an offset value of −10 mV, in a positive chopping state (i.e., a negative feedback state), and a positive offset, for example, an offset value of +10 mV, in a negative chopping state (i.e., a positive feedback state).

[0208] In this case, during the fth through f+3th frames FR(f) to FR(f+3), the output voltage of the first output buffer AMP1(m) is alternately offset as "+10 mV, -10 mV, +10 mV, -10 mV", and conversely, the output voltage of the second output buffer AMP2(m) is alternately offset as "-10 mV, +10 mV, -10 mV, +10 mV".

[0209] In this way, offset values ​​in opposite directions occur between the first output buffer AMP1(m) and the second output buffer AMP2(m) for each frame FR, and a large output voltage difference of approximately 20 mV occurs between the first output buffer AMP1(m) and the second output buffer AMP2(m) for each frame FR.

[0210] As a result, for each frame FR, an overcurrent Io occurs due to the difference in output voltage between the first output buffer AMP1(m) and the second output buffer AMP2(m), and flows into the corresponding channel CH(n).

[0211] In this case, the overcurrent Io increases current consumption, ie, power consumption, and may even damage the driving circuit (eg, data IC (DIC)) of the data driver 220.

[0212] In contrast to this, in this embodiment, the offset direction (or chopping state, or feedback state) of the output buffer AMP can be adjusted and driven for each channel CH so that the first output buffer AMP1 and the second output buffer AMP2 have offsets in the same direction in the same frame FR.

[0213] This will be described with reference to Figures 9 and 10. Figure 9 is a diagram showing an example of an offset value of the output voltage when the first output buffer and the second output buffer are driven by the chopping method before the offset direction of the first output buffer and the second output buffer is adjusted according to an embodiment of the present invention. Figure 10 is a diagram showing an example of an offset value of the output voltage when the first output buffer and the second output buffer are driven by the chopping method after the offset direction of the first output buffer and the second output buffer is adjusted according to an embodiment of the present invention.

[0214] 9 and 10, for convenience of explanation, the first to fourth channels CH(1) to CH(4) are taken as examples.

[0215] FIG. 9 also illustrates a typical chopping-type driving example, in which the first output buffer AMP1 and the second output buffer AMP2 located in the corresponding channel CH have the same feedback state in the same frame FR, and the first output buffer AMP1 and the second output buffer AMP2 of each channel CH are alternately driven into a positive chopping state and a negative chopping state for each frame FR, as described above.

[0216] First, an example will be given with reference to Figure 9. For the first channel CH(1), the first output buffer AMP1(1) has an offset value of +5 mV in the positive chopping state (i.e., negative feedback state) and an offset value of -5 mV in the negative chopping state (i.e., positive feedback state). The second output buffer AMP2(1) has an offset value of -5 mV in the positive chopping state and an offset value of +5 mV in the negative chopping state. Thus, the output voltages of the first output buffer AMP1(1) and the second output buffer AMP2(1) of the first channel CH(1) are offset in opposite directions under the same chopping state, resulting in a large offset difference of 10 mV, i.e., a large output voltage difference, between the first output buffer AMP1(1) and the second output buffer AMP2(1) under the same chopping state.

[0217] For the second channel CH(2), the first output buffer AMP1(2) has an offset value of -10 mV in the positive chopping state and an offset value of +10 mV in the negative chopping state. The second output buffer AMP2(2) has an offset value of +8 mV in the positive chopping state and an offset value of -8 mV in the negative chopping state. Thus, the output voltages of the first output buffer AMP1(2) and the second output buffer AMP2(2) of the second channel CH(2) are offset in opposite directions under the same chopping state, resulting in a large output voltage difference of 18 mV between the first output buffer AMP1(2) and the second output buffer AMP2(2) under the same chopping state.

[0218] On the other hand, for the third channel CH(3), the first output buffer AMP1(3) has an offset value of -10 mV in the positive chopping state and an offset value of +10 mV in the negative chopping state. The second output buffer AMP2(3) has an offset value of -8 mV in the positive chopping state and an offset value of +8 mV in the negative chopping state. Thus, the output voltages of the first output buffer AMP1(3) and the second output buffer AMP2(3) of the third channel CH(3) are offset in the same direction under the same chopping state, resulting in a small output voltage difference of 2 mV between the first output buffer AMP1(3) and the second output buffer AMP2(3) under the same chopping state.

[0219] On the other hand, for the fourth channel CH(4), the first output buffer AMP1(4) has an offset value of -15 mV in the positive chopping state and an offset value of +15 mV in the negative chopping state. The second output buffer AMP2(4) has an offset value of +10 mV in the positive chopping state and an offset value of -10 mV in the negative chopping state. Thus, the output voltages of the first output buffer AMP1(4) and the second output buffer AMP2(4) of the fourth channel CH(4) are offset in opposite directions under the same chopping state, resulting in a large output voltage difference of 25 mV between the first output buffer AMP1(4) and the second output buffer AMP2(4) under the same chopping state.

[0220] In this way, the offset direction is reversed between the first output buffer AMP1 and the second output buffer AMP2 in the first channel CH(1), the second channel CH(2), and the fourth channel CH(4), resulting in a large difference in output voltage, which can result in a significant overcurrent.

[0221] On the other hand, in the third channel CH(3), the offset direction is the same between the first output buffer AMP1 and the second output buffer AMP2, and the difference in output voltage is small, resulting in a low (or prevented) overcurrent.

[0222] In contrast to this, in this embodiment, as described above, for channels CH(1), CH(2), and CH(4) in which the offset direction is opposite between the first output buffer AMP1 and the second output buffer AMP2, the chopping state (or chopping order) is adjusted (or switched) so that the offset direction is the same between the first output buffer AMP1 and the second output buffer AMP2.

[0223] In this regard, an example will be given with reference to Figure 10. For the first channel CH(1), which has the same chopping state but an opposite offset direction, when the first output buffer AMP1(1) is in a positive or negative chopping state, the second output buffer AMP2(1) can be adjusted (or switched) to a negative or positive chopping state, and the second output buffer AMP2(1) can be set and driven in a chopping state opposite to that of the first output buffer AMP1(1) for each frame FR. As a result, the output voltages of the first output buffer AMP1(1) and the second output buffer AMP2(1) of the first channel CH(1) are offset in the same direction for each frame FR, and the difference in output voltage between the first output buffer AMP1(1) and the second output buffer AMP2(1) can be significantly reduced from 10 mV to 0 mV.

[0224] Similarly, for a second channel CH(2) having the same chopping state but an opposite offset direction, when the first output buffer AMP1(2) is in a positive or negative chopping state, the second output buffer AMP2(2) can be adjusted to a negative or positive chopping state, and the second output buffer AMP2(2) can be set and driven in a chopping state opposite to that of the first output buffer AMP1(2) for each frame FR. As a result, the output voltages of the first output buffer AMP1(2) and the second output buffer AMP2(2) of the second channel CH(2) are offset in the same direction for each frame FR, and the difference in output voltage between the first output buffer AMP1(2) and the second output buffer AMP2(2) can be significantly reduced from 18 mV to 2 mV.

[0225] Furthermore, for the fourth channel CH(4), which has the same chopping state but the offset direction opposite, when the first output buffer AMP1(4) is in a positive / negative chopping state, the second output buffer AMP2(4) can be adjusted to a negative / positive chopping state conversely, and the second output buffer AMP2(4) can be set and driven in a chopping state opposite to that of the first output buffer AMP1(4) for each frame FR. As a result, the output voltages of the first output buffer AMP1(4) and the second output buffer AMP2(4) of the fourth channel CH(4) are offset in the same direction for each frame FR, and the difference in output voltage between the first output buffer AMP1(4) and the second output buffer AMP2(4) can be significantly reduced from 25 mV to 5 mV.

[0226] On the other hand, for the third channel CH(3), which has the same chopping state and offset direction, the first output buffer AMP1(3) and the second output buffer AMP2(3) have the same offset direction for each frame FR, and the difference in output voltage is small, so there is no need to adjust the chopping states of the first output buffer AMP1(3) and the second output buffer AMP2(3). As another example, the chopping order of both the first output buffer AMP1(3) and the second output buffer AMP2(3) can be changed. The positive-to-negative chopping switching of the first output buffer AMP1 can be changed to negative-to-positive, and similarly, the positive-to-negative chopping switching of the second output buffer AMP2(3) can be changed to negative-to-positive.

[0227] As described above, for channels CH in which the offset direction between the first output buffer AMP1 and the second output buffer AMP2 is opposite, the chopping state of the second output buffer AMP2 is adjusted so that the offset direction is the same in the same frame FR. In another example, the chopping state of the first output buffer AMP1 can also be adjusted. In other words, the chopping state of either the first output buffer AMP1 or the second output buffer AMP2 can be adjusted based on the chopping state of the other.

[0228] As a result, the offset direction between the first output buffer AMP1 and the second output buffer AMP2 of the channel CH becomes the same, and the difference in output voltage between the first output buffer AMP1 and the second output buffer AMP2 can be significantly reduced.

[0229] In this way, by adjusting the offset direction between the first output buffer AMP1 and the second output buffer AMP2 of the channel CH to be the same, it is possible to reduce or prevent overcurrent caused by the difference in output voltage between the first output buffer AMP1 and the second output buffer AMP2.

[0230] As a result, power consumption is reduced, low-power driving is possible, and damage to the driving circuit of the data driver 220 due to overcurrent can be prevented.

[0231] Hereinafter, the process of adjusting the offset direction of the output voltage between the first output buffer AMP1 and the second output buffer AMP2 of the channel CH to be the same will be described in more detail with reference to FIG.

[0232] FIG. 11 is a diagram schematically illustrating an adjustment device, a display panel, and a data driver used in a test process for inspecting and adjusting the offset direction of the first output buffer and the second output buffer of a channel according to an embodiment of the present invention.

[0233] 11, for example, the adjustment device 500 is used in a test to adjust the offset directions of the first output buffer AMP1 and the second output buffer AMP2 before shipping the display device. In other words, the adjustment device 500 can be used in a test to generate chopping drive information (or chopping state information) IN, which is information for detecting and adjusting the offset directions during the manufacturing process of the display device. The chopping drive information IN generated in this test can be transmitted to the memory MEM of the data driver 220 and then written and stored.

[0234] The adjusting device 500 may include, for example, an ammeter 510 that measures the current consumption Ic (or power consumption) of the data driver 220 .

[0235] In this regard, the power supply unit 280 supplies driving power for driving the first data driver 221 and the second data driver 222 of the double bank structure via the power supply wiring VDL, and the first data driver 221 and the second data driver 222 (or the first data IC (DIC1) and the second data IC (DIC2)) can output data voltages Vdata on multiple channels CH, for example, M channels CH(1) to CH(M), and output them to M data wirings DL(1) to DL(M) in the display panel 100.

[0236] The current consumption Ic consumed when driving the first data driver 221 and the second data driver 222 can be measured by the ammeter 510 of the adjusting device 500.

[0237] In this way, the current consumption Ic measured by the ammeter 510 makes it possible to determine whether the offset directions of the output voltages of the first output buffer AMP1 and the second output buffer AMP2 of the channel CH are the same or opposite.

[0238] For example, the ammeter 510 can measure, for each channel CH, the current consumption Ica (or the first current consumption) in the same chopping state in the first output buffer AMP1 and the second output buffer AMP2, and the current consumption Icb (or the second current consumption) in the opposite chopping state in the first output buffer AMP1 and the second output buffer AMP2.

[0239] For the first channel CH(1), the current consumption Ica can be measured when the first output buffer AMP1 and the second output buffer AMP2 are in the same chopping state, and the current consumption Icb can be measured when the first output buffer AMP1 and the second output buffer AMP2 are in the opposite chopping state. Here, to achieve the opposite chopping state, the chopping switching order of the first output buffer AMP1 can be maintained and the chopping switching order of the second output buffer AMP2 can be changed. Alternatively, the chopping switching order of the second output buffer AMP2 can be maintained and the chopping switching order of the first output buffer AMP1 can be changed.

[0240] Similarly, for each of the second to Mth channels CH(2) to CH(M), the current consumption Ica can be measured when the first output buffer AMP1 and the second output buffer AMP2 are in the same chopping state, and the current consumption Icb can be measured when the first output buffer AMP1 and the second output buffer AMP2 are in the opposite chopping state.

[0241] This allows the current consumption Ica and Icb in the same chopping state and the opposite chopping state in the first output buffer AMP1 and the second output buffer AMP2 to be measured using the ammeter 510 for each channel CH.

[0242] The adjustment device 500 can compare the current consumption Ica in the same chopping state and the current consumption Icb in the opposite chopping state in the first output buffer AMP1 and the second output buffer AMP2 measured for each channel CH using the ammeter 510.

[0243] If the comparison result shows that the current consumption Ica in the same chopping state of the first output buffer AMP1 and the second output buffer AMP2 is smaller than the current consumption Icb in the opposite chopping state (i.e., Ica < Icb), it means that the difference in output voltage is small in the same chopping state. Therefore, in this case, it can be determined that the offset directions of the first output buffer AMP1 and the second output buffer AMP2 are the same in the same chopping state.

[0244] Conversely, if the comparison result shows that the current consumption Ica in the same chopping state of the first output buffer AMP1 and the second output buffer AMP2 is larger than the current consumption Icb in the opposite chopping state (i.e., Ica > Icb), it means that the difference in output voltage is large in the same chopping state. Therefore, in this case, it can be determined that the offset directions of the first output buffer AMP1 and the second output buffer AMP2 are opposite in the same chopping state.

[0245] Based on such comparison results, chopping drive information IN for adjusting the offset directions of the output voltages of the first output buffer AMP1 and the second output buffer AMP2 to be the same for each channel CH can be generated.

[0246] Such chopping drive information IN can correspond to information for setting (or indicating) the switching order of the chopping states of the first output buffer AMP1 and the second output buffer AMP2 for each channel CH (or the chopping state for each frame). Such chopping drive information IN can include, for example, first chopping drive information IN1 indicating the switching order of the chopping states of each channel CH in the first data drive unit 221 and second chopping drive information IN2 indicating the switching order of the chopping states of each channel CH in the second data drive unit 222.

[0247] The first chopping driving information IN1 may be transmitted to, written into, and stored in a first memory MEM1, which is a memory MEM included in the corresponding first data driver 221 (or first source board SPCB1). The first chopping driving information IN1 stored in the first memory MEM1 is loaded and used when the first data driver 221 is driven, and the chopping state of the first output buffer AMP1 can be switched for each channel CH according to the chopping state set in the first chopping driving information IN1.

[0248] Similarly, the second chopping drive information IN2 may be transmitted to, written into, and stored in the second memory MEM2, which is a memory MEM included in the corresponding second data driver 222 (or the second source board SPCB2). The second chopping drive information IN2 stored in the second memory MEM2 is loaded and used when the second data driver 222 is driven, and the chopping state of the second output buffer AMP2 can be switched for each channel CH according to the chopping state set in the second chopping drive information IN2.

[0249] 10, regarding the first chopping drive information IN1 and the second chopping drive information IN2, for example, for the first channel CH(1), the first chopping drive information IN1 is set so that the first output buffer AMP1(1) has a positive chopping state in odd-numbered frames FR and a negative chopping state in even-numbered frames FR. Also, the second chopping drive information IN2 is set (or adjusted) so that the second output buffer AMP2(1) has a negative chopping state in odd-numbered frames FR and a positive chopping state in even-numbered frames FR.

[0250] In this way, the first chopping drive information IN1 and the second chopping drive information IN2 can adjust the chopping state of an output buffer AMP, for example, the second output buffer AMP2 (or the first output buffer AMP1), so that the offset direction of the output voltages of the first output buffer AMP1 and the second output buffer AMP2 for each frame FR is the same.

[0251] As a result, for each channel CH, a data voltage Vdata with a consistent offset direction can be output between the first output buffer AMP1 and the second output buffer AMP2, and the difference in output voltage between the upper and lower ends of the channel CH can be reduced or eliminated.

[0252] Therefore, the overcurrent caused by the difference in output voltage between the upper and lower ends of the channel can be reduced or eliminated, thereby reducing power consumption, enabling low-power driving, and preventing damage to the driving circuit due to the overcurrent.

[0253] As described above, in an embodiment of the present invention, in the upper and lower data drivers of a double bank structure, when the upper and lower output buffers arranged for each channel are driven by the chopping method, the chopping state of the output buffers can be adjusted so that the output voltage offset between the upper and lower output buffers for each channel is in the same direction.

[0254] This allows the upper and lower output buffers for each channel to output data voltages with the same offset direction, thereby reducing or eliminating the difference in output voltage between the upper and lower ends of the channel.

[0255] Therefore, the overcurrent caused by the difference in the output voltage of the channels can be reduced or eliminated, thereby reducing power consumption, enabling low-power driving, and preventing damage to the driving circuit due to the overcurrent.

[0256] The above-described embodiment of the present invention is merely an example, and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents. [Explanation of symbols]

[0257] 10…Display device 100...Display panel 210...Gate driver 220...Data driver 221...first data driver 222...second data driver 240...Timing control section 280...Power supply section 500…Adjustment equipment 510…Ammeter AA…display area NA…Hidden area GL...Gate wiring DL: Data wiring P...pixel CH...Channel SPCB...Source Board SPCB1...First source board SPCB2: Second source board DIC: Data IC DIC1: First data IC DIC2: Second data IC FCF: Flexible circuit film AMP...output buffer AMP1: First output buffer AMP2: Second output buffer MEM...Memory MEM1...first memory MEM2...second memory FR...Frame

Claims

1. a display panel including a plurality of data lines and pixels connected to the data lines; a first data driver including a plurality of first output buffers disposed in a plurality of channels each connected to one end of the plurality of data lines; a second data driver including a plurality of second output buffers disposed in a plurality of channels respectively connected to the other ends of the plurality of data lines; each of the first output buffer and the second output buffer is alternately switched between a positive chopping state and a negative chopping state for each frame; A display device, wherein the first output buffer and the second output buffer of corresponding channels have the same offset direction of the output voltage in the same frame.

2. The display device according to claim 1 , wherein the plurality of channels include channels having the same chopping state in the same frame between the first output buffer and the second output buffer.

3. 3. The display device according to claim 1, wherein the plurality of channels include channels having opposite chopping states in the same frame between the first output buffer and the second output buffer.

4. The display device of claim 1 , wherein the positive chopping state is a negative feedback state, and the negative chopping state is a positive feedback state.

5. The display device of claim 1 , wherein the first output buffer and the second output buffer have an output voltage offset direction opposite to that in the positive chopping state and the negative chopping state.

6. the first data driver includes a first memory configured to store first chopping driving information in which a chopping state of the first output buffer for each frame is set; The display device of claim 1 , wherein the second data driver comprises a second memory configured to store second chopping driving information in which a chopping state of the second output buffer for each frame is set.

7. 2. The display device according to claim 1, wherein, in the corresponding channels, a current consumption when the offset direction of the output voltage between the first output buffer and the second output buffer is the same is smaller than a current consumption when the offset direction of the output voltage is opposite.

8. The display device of claim 1 , wherein the pixel comprises a light emitting diode.

9. 3. The display device of claim 2, wherein, in channels having the same chopping state in the same frame between the first output buffer and the second output buffer, the first output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state.

10. 4. The display device of claim 3, wherein, in a channel having opposite chopping states in the same frame between the first output buffer and the second output buffer, the first output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer has a negative offset in the negative chopping state and a positive offset in the positive chopping state.

11. a display panel including a plurality of data lines; a first data driver including a plurality of first output buffers respectively connected to one ends of the plurality of data lines; a second data driver including a plurality of second output buffers respectively connected to the other ends of the plurality of data lines; each of the first output buffer and the second output buffer alternates between a positive chopping state and a negative chopping state on a frame-by-frame basis; The display device, wherein the first output buffer and the second output buffer connected to the same data wiring output data voltages with the same offset direction.

12. The display device of claim 11 , wherein the first output buffer and the second output buffer connected to any one of the plurality of data lines have the same chopping state in the same frame.

13. 13. The display device of claim 11, wherein the first output buffer and the second output buffer connected to different data lines among the plurality of data lines have opposite chopping states in the same frame.

14. The display device of claim 11 , wherein the positive chopping state is a negative feedback state, and the negative chopping state is a positive feedback state.

15. The display device of claim 11 , wherein the first output buffer and the second output buffer have an output voltage offset direction opposite to that in the positive chopping state and the negative chopping state.

16. the first data driver includes a first memory configured to store first chopping driving information in which a chopping state of the first output buffer for each frame is set; The display device of claim 11, wherein the second data driver comprises a second memory configured to store second chopping driving information in which a chopping state of the second output buffer for each frame is set.

17. 12. The display device according to claim 11, wherein a current consumption when the offset direction of the output voltage between the first output buffer and the second output buffer connected to the same data wiring is the same is smaller than a current consumption when the offset direction of the output voltage is opposite.

18. The display device according to claim 11 , wherein the display panel includes pixels connected to the data lines and each pixel includes a light-emitting diode.

19. 13. The display device of claim 12, wherein the first output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state.

20. 14. The display device of claim 13, wherein the first output buffer has a positive offset in the negative chopping state and a negative offset in the positive chopping state, and the second output buffer has a negative offset in the negative chopping state and a positive offset in the positive chopping state.

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