signal processing device

Abstract

To stabilize a distortion compensation process by avoiding overfitting.SOLUTION: A signal processing device includes a systolic array 7 as a systolic array structure that performs calculations using a recursive least squares algorithm by repeatedly passing the calculation results of a boundary cell 71 and an internal cell 72 to adjacent cells, and a regularization term α is added to an arithmetic processing algorithm in the boundary cell 71.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal processing device that performs distortion compensation processing to suppress signal distortion occurring in a compensated circuit such as a signal amplifier. [Background technology]

[0002] Amplifiers have nonlinear characteristics, and in order to compensate for signal distortion caused in the amplifier by the nonlinear characteristics, a distortion compensator is used that compensates for the distortion of the output signal by previously applying to the input signal a distortion that cancels out the distortion components generated in the output signal (i.e., an inverse distortion characteristic).A conventional predistortion type amplifier is known to have a mechanism that includes an amplifier, means for determining an error signal between the input signal of the amplifier and the output of the amplifier, means for generating a compensation coefficient that compensates for the distortion characteristic components of the amplifier from the error signal using an adaptive algorithm, means for outputting the generated compensation coefficient corresponding to the input signal, and means for multiplying the input signal by the compensation coefficient output corresponding to the input signal and inputting the result to the amplifier (see Patent Document 1).

[0003] In addition, in predistortion amplifiers, the predistortion characteristics are adaptively estimated using digital processing. In this case, if software processes continuously transmitted signals in a batch to estimate the predistortion characteristics, it generally takes several seconds for the signal to converge. Therefore, it is possible to analyze the amplifier characteristics using, for example, the recursive least-squares (RLS) algorithm. When using a systolic array processor, cells with the same function are regularly arranged, and each cell performs a simple calculation and then passes the calculation results to the adjacent cell. This allows the QRDRLS (QR Decomposition based Recursive Least-Squares) algorithm to be calculated in parallel, and the optimal compensation coefficients for the distortion compensation unit are estimated.

[0004] The QRDRLS algorithm uses QR decomposition based on the Givens rotation (see Non-Patent Document 1). Using a systolic array processor, Givens rotation and QR decomposition can be processed in parallel, enabling high-speed processing. In a systolic array processor, simple operation blocks called boundary cells and internal cells are arranged in parallel two-dimensionally. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 09-069733 [Non-patent literature]

[0006] [Non-Patent Document 1] Huadong Wang et al. “A Fast QR-RLS algorithm based on Givens Rotation for DPD application”, IEICE Communications Express, Vol. 3 No. 2, 44-49, 2014 Summary of the Invention [Problem to be solved by the invention]

[0007] Among distortion compensation processes that use polynomial approximation, DPD (Digital Pre-Distortion) processing uses the QRDRLS algorithm to calculate polynomial coefficients based on a comparison of the input signal and output signal of a distortion-compensated circuit such as an amplifier. Although the number of polynomial terms is adjusted to prevent overfitting, when high-level signals such as USB (Upper Side Band) audio signals (burst signals) appear suddenly and infrequently, if there are no high-level signals for an extended period of time (for example, if there is no audio input), the polynomial coefficients used in the distortion compensation processing are updated by the input noise, and the absence of high-level components in the signal causes the compensation characteristics in the high-level region to fall into overfitting, which in turn causes the distortion compensation processing loop to become unstable and prone to divergence.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a signal processing device that can avoid overfitting and stabilize distortion compensation processing. [Means for solving the problem]

[0009] In order to solve the above problem, a signal processing device according to the present invention is provided with a systolic array structure for performing calculations of a recursive least squares algorithm, and a regularization term is added to the recursive least squares algorithm. The systolic array structure comprises boundary cell elements that perform boundary cell operations and internal cell elements that perform internal cell operations, such that calculations are performed using QR decomposition and Givens rotation of a matrix, and when a systolic array is arranged by arranging a plurality of boundary cells and a plurality of internal cells, the boundary cell operations and the internal cell operations are performed by the boundary cell elements and the internal cell elements, and a regularization term is added to the algorithm for the operation processing in the boundary cells, and the algorithm for the operation processing in the boundary cells is When δ=0 or U=0, X←X δ'=δ S=0 In cases other than those mentioned above, BX = β2·(X+α) X ← BX+δ·|U|2 DX = δ / X δ' = BX DX S = U DX Here, δ: Calculation result in the previous boundary cell δ': Calculation result in the boundary cell U: Input signal to the boundary cell X: The value of the boundary cell α: Regularization term for recursive least squares calculation β: the square root of the forgetting factor in the recursive least squares algorithm S: Calculation result for the boundary cell That is, It is characterized by: [Effects of the Invention]

[0010] According to the signal processing device of the present invention, when a regularization term is added to a recursive least squares algorithm, the value of the regularization term acts as a penalty term for the magnitude of the polynomial coefficients in the objective function when minimizing the error, thereby making it possible to avoid overfitting and stabilize the distortion compensation process. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a functional block diagram showing a schematic configuration of a wireless transmitter including a signal processing device according to an embodiment of the present invention; [Figure 2] 2 is a diagram showing an example of the configuration of a systolic array for the first half processing of the QRDRLS algorithm, which is used as part of the calculation of the distortion calculation unit of the signal processing device of FIG. 1. FIG. [Figure 3] 3 is a diagram for explaining the arithmetic processing of the boundary cells of the systolic array of FIG. 2. FIG. [Figure 4] 3 is a diagram for explaining the arithmetic processing of the internal cells of the systolic array of FIG. 2. FIG. [Figure 5] 3 is a diagram showing an example of the configuration of a systolic array for the latter half of the processing of the QRDRLS algorithm, using the systolic array calculation results of FIG. 2. FIG. [Figure 6] 6 is a diagram for explaining the calculation process of the internal cells of the systolic array of FIG. 5, which can be realized by the same calculation as in FIG. 4. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present invention will be described below based on the illustrated embodiments.

[0013] 1 is a functional block diagram showing a schematic configuration of a wireless transmitter 1 including a signal processing device 3 according to an embodiment of the present invention. In this embodiment, an example will be described in which the signal processing device 3 is mounted on the wireless transmitter 1 including a nonlinear amplifier 4 as a distortion-compensated circuit. Note that illustrations and descriptions of circuit elements that are not related to the gist of the present invention will be omitted, and it is assumed that the wireless transmitter 1 is provided with the necessary circuit elements as appropriate, even if they are not illustrated or described.

[0014] (Overall configuration of wireless transmitter 1) The wireless transmitter 1 is a mechanism that amplifies an input transmission signal, performs DPD (Digital Pre-Distortion) processing to compensate for distortion of the transmission signal that occurs during amplification, and transmits the signal from the antenna 5. The wireless transmitter 1 mainly comprises a control unit 2, a signal processing device 3, a nonlinear amplifier 4, and the antenna 5.

[0015] The control unit 2 has the function of controlling the operation of each part that constitutes the wireless transmitter 1, including the signal processing unit 3, and includes a central processing unit 2a (CPU: Central Processing Unit), an input / output unit 2b (I / O: Input / Output), and a memory unit 2c.

[0016] The control unit 2 is connected to each component of the wireless transmitter 1 via the input / output unit 2b, and controls the start, content, and end of processing in each component of the wireless transmitter 1. To avoid complexity, the signal lines from the input / output unit 2b to each component are not shown in the figure.

[0017] The memory unit 2c has the function of serving as a working area for temporarily storing data and information generated when the central processing unit 2a performs arithmetic processing related to signal transmission, including distortion compensation processing, and as a memory area for storing and storing various information, programs, and data, and is composed of storage media such as RAM (Random Access Memory), ROM (Read Only Memory), and storage.

[0018] The memory unit 2c stores a control program that the control unit 2 uses to control the overall operation of the wireless transmitter 1, including the signal processing device 3. The control unit 2 controls the overall operation of the wireless transmitter 1, including the signal processing device 3, in accordance with the control program stored in the memory unit 2c, to realize each function.

[0019] A baseband transmit signal (referred to as "input signal x(t)"; it is a digital signal) generated by a transmission source (not shown) and transmitted by a wireless transmitter 1 is input to a signal processing device 3. "t" indicates a sampling time, i.e., "x(t)" indicates the input signal at a discrete time (in other words, sampling timing) t obtained by sampling.

[0020] The signal processing device 3 receives an input signal x(t) and performs distortion compensation processing (specifically, DPD processing) to suppress distortion occurring in the input signal x(t) (in other words, to cancel and compensate for distortion components) in a distortion-compensated circuit (specifically, the nonlinear amplifier 4) according to the nonlinear characteristics / distortion characteristics of the compensated circuit using polynomial approximation, and outputs the result. The signal processing device 3 can be realized by, for example, an FPGA (Field-Programmable Gate Array).

[0021] The nonlinear amplifier 4 receives the signal (an analog signal) that has been output from the signal processing device 3 and subjected to processing such as frequency conversion and digital-to-analog conversion as necessary, and high-frequency amplifies the power of the signal at a predetermined amplification factor G (gain) and outputs the amplified signal. Since the nonlinear amplifier 4 is used in a nonlinear region, distortion occurs in the signal output from the nonlinear amplifier 4 according to the nonlinear characteristics / distortion characteristics of the nonlinear amplifier 4.

[0022] The high-frequency amplified signal output from the nonlinear amplifier 4 is input to the antenna 5 and emitted into space as a radio wave via the antenna 5.

[0023] A part of the signal (which is an analog signal) output from the nonlinear amplifier 4 is branched off, for example, by a directional coupler, and is supplied as feedback data of the signal to the signal processing device 3 after undergoing processes such as attenuation, analog-to-digital conversion, and frequency conversion as necessary. The signal as feedback data supplied to the signal processing device 3 is called a "feedback signal y(t)."

[0024] (Configuration of signal processing device 3) The signal processing device 3 according to the embodiment includes a systolic array 7 configured as a systolic array structure that performs calculations of a recursive least squares algorithm by repeatedly passing the calculation results of each cell of a boundary cell 71 and an internal cell 72 to adjacent cells, and a regularization term α is added to the algorithm (specifically, the recursive least squares algorithm) of the calculation processing in the boundary cell 71. Specifically, the signal processing device 3 includes a boundary cell element that performs calculations for the boundary cell 71 and an internal cell element that performs calculations for the internal cell 72, which constitute the systolic array 7.

[0025] The signal processing device 3 is a mechanism for performing distortion compensation processing (specifically, DPD processing) to suppress distortion occurring in an input signal x(t) in a distortion-compensated circuit (specifically, the nonlinear amplifier 4 in this case) according to the nonlinear characteristics / distortion characteristics of the compensated circuit, and mainly includes a distortion compensation unit 31 and a distortion calculation unit 32.

[0026] The distortion compensation unit 31 generates a pre-distorted signal u(t) by applying an inverse distortion characteristic to the input signal x(t) input to the signal processing device 3 in accordance with a polynomial that indicates an inverse distortion characteristic to the distortion caused by the nonlinear characteristics / distortion characteristics of the nonlinear amplifier 4.

[0027] In order to calculate / update the values ​​of the polynomial coefficients (in other words, the compensation coefficients) used in the distortion compensation unit 31, the distortion calculation unit 32 receives a supply of the predistortion signal u(t) output from the distortion compensation unit 31 (and also input to the nonlinear amplifier 4) and an input of the feedback signal y(t) output from the nonlinear amplifier 4, and calculates distortion characteristics (inverse distortion characteristics) that are inverse to the distortion generated in the nonlinear amplifier 4 based on the predistortion signal u(t) and the feedback signal y(t). The predistortion signal u(t) output from the distortion compensation unit 31 and used to calculate / update the polynomial coefficients used in the distortion compensation unit 31 is a reference signal for the distortion compensation process in the distortion compensation unit 31.

[0028] The distortion calculation unit 32 uses the predistortion signal u(t) as a reference signal in accordance with the recursive least squares (RLS) algorithm to calculate the inverse distortion characteristics, i.e., the values ​​of the polynomial coefficients, that minimize the error between the predistortion signal u(t) and the signal obtained by applying the inverse distortion characteristics to the feedback signal y(t).

[0029] The distortion calculation unit 32 is configured by a systolic array 7 that sequentially calculates polynomial coefficients according to a recursive least squares (RLS) algorithm. The distortion calculation unit 32 expresses the inverse distortion characteristics of the nonlinear amplifier 4 as a polynomial and calculates the coefficient values ​​of the inverse distortion polynomial.

[0030] The systolic array 7 has cells with the same function arranged in a regular pattern, each of which performs a simple calculation and then passes the calculation result to the adjacent cell. By performing simple calculations in parallel, the recursive least squares (RLS) algorithm can be calculated.

[0031] The distortion calculation unit 32 is composed of a process (also called "first half processing") that processes the feedback signal y(t) to generate each term of a coefficientless polynomial, and a process (also called "second half processing") that calculates the polynomial coefficients. Specifically, the polynomial coefficient calculation process calculates the values ​​of the polynomial coefficients according to the QRDRLS algorithm, which uses QR decomposition and Givens rotation of a matrix. QR decomposition is a process of decomposing a given matrix into an orthogonal matrix Q and an upper triangular matrix R in order to find the eigenvalues ​​of the matrix. Givens rotation is a process of converting a given matrix into an upper triangular matrix using an orthogonal matrix derived from the values ​​of the matrix.

[0032] (Systolic array 7 configuration) 2 is a block diagram showing an example of the configuration of the systolic array 7 that constitutes the distortion calculation unit 32 of the signal processing device 3, and is a diagram showing an example of the first half of the QRDRLS algorithm. In this embodiment, the number of inputs (and also the number of parameters to be estimated (specifically, polynomial coefficients)) will be described as three. The up, down, left, and right directions in the following description correspond to the up, down, left, and right directions on the paper surface showing FIG. 2, respectively.

[0033] As shown in FIG. 2, the systolic array 7 is configured by arranging a plurality of boundary cells 71 and a plurality of internal cells 72 in a triangular matrix, and when the number of inputs is three, three boundary cells 71a to 71c and six internal cells 72a to 72f are arranged.

[0034] Boundary cells 71a, 71b, and 71c, the number of which corresponds to the number of inputs, are connected in series in the above order along a diagonal downward direction to the right, in other words, as diagonal elements of a matrix, with delay elements (not shown) interposed between each cell, which have the function of delaying the data transfer by a discrete time t (in other words, one timing).

[0035] Internal cells 72a, 72b, and 72c are connected in series in this order to the row output side (specifically, to the right) of boundary cell 71a, internal cells 72d and 72e are connected in series in this order to the row output side (specifically, to the right) of boundary cell 71b, and internal cell 72f is connected to the row output side (specifically, to the right) of boundary cell 71c.

[0036] The column-wise (specifically, downward) output of internal cell 72a is connected to boundary cell 71b, the column-wise (specifically, downward) output of internal cell 72b is connected to internal cell 72d, and the column-wise (specifically, downward) output of internal cell 72c is connected to internal cell 72e.

[0037] The column-direction (specifically, downward) output of the internal cell 72d is connected to the boundary cell 71c, and the column-direction (specifically, downward) output of the internal cell 72e is connected to the internal cell 72f.

[0038] An RLS input signal U is input to boundary cell 71a, internal cell 72a, and internal cell 72b, and a reference signal D is input to internal cell 72c. The RLS input signals U0, U1, U2, ... are specifically processed versions of the feedback signal y(t) and are the terms of a coefficientless polynomial. The reference signal D is specifically the predistortion signal u(t).

[0039] (Systolic Array 7 Operation) In the systolic array 7, each of the boundary cells 71a to 71c and each of the internal cells 72a to 72f performs a respective operation, and outputs the operation result to the adjacent cell.

[0040] Specifically, an RLS input signal U0 is input to boundary cell 71a, an RLS input signal U1 is input to internal cell 72a, an RLS input signal U2 is input to internal cell 72b, and a reference signal D is input to internal cell 72c, all of which are placed in the first stage.

[0041] The signals input to each cell in the first stage are as follows: <Boundary Cell 71a> U0(t), U0(t+1), U0(t+2), U0(t+3), ... are input sequentially at each discrete time t (in other words, at each timing). <Internal Cell 72a> U1(t), U1(t+1), U1(t+2), U1(t+3), ... are input sequentially at each discrete time t (each timing). <Internal Cell 72b> U2(t), U2(t+1), U2(t+2), U2(t+3), ... are input sequentially at each discrete time t (each timing). <Internal cell 72c> Predistortion signals D(t), D(t+1), D(t+2), D(t+3), etc. are input sequentially at discrete times t (at each timing).

[0042] The boundary cell 71a performs an operation using the diagonal input (δ=1), the column input (U0), and the value (X00) of the boundary cell 71a, and outputs the operation result (S0) and the input (U0) to the adjacent internal cell 72a in the row direction, and also outputs the operation result (δ') to the subsequent boundary cell 71b via a delay element (not shown). Also, the value (X00) of the boundary cell 71a is set / updated according to the operation result.

[0043] The internal cell 72a performs an operation using the input (U0) to the boundary cell 71a, which is an input from the row direction, the operation result (S0) of the boundary cell 71a, the input (U1) from the column direction, and the value (X01) held by the internal cell 72a, and outputs the operation result (U'1) to the adjacent boundary cell 71b in the column direction, and also outputs the input (U0) and operation result (S0) as is to the adjacent internal cell 72b in the row direction. In addition, the value (X01) held by the internal cell 72a is set / updated according to the operation result.

[0044] The internal cell 72b performs an operation using the inputs (U0, S0) from the row direction, the input (U2) from the column direction, and the value (X02) held by the internal cell 72b, and outputs the operation result (U'2) to the internal cell 72d adjacent in the column direction, and also outputs the input (U0, S0) as is to the internal cell 72c adjacent in the row direction. Also, the value (X02) held by the internal cell 72b is set / updated according to the operation result.

[0045] The internal cell 72c performs an operation using inputs (U0, S0) from the row direction, input (D) from the column direction, and the value (X03) held by the internal cell 72c, and outputs the operation result (D') to the adjacent internal cell 72e in the column direction. Also, the value (X03) held by the internal cell 72c is set / updated according to the operation result.

[0046] The boundary cell 71b performs an operation using the operation result (δ') of the preceding boundary cell 71a, which is delayed by a discrete time t (in other words, one timing) via a delay element (not shown), the operation result (U'1) of the adjacent internal cell 72a in the column direction, and the value (X11) held by the boundary cell 71b, and outputs the operation result (S1) and the operation result (U'1) to the adjacent internal cell 72d in the row direction, and also outputs the operation result (δ'') to the subsequent boundary cell 71c via a delay element (not shown). In addition, the value (X11) held by the boundary cell 71b is set / updated according to the operation result.

[0047] Internal cell 72d performs an operation using the operation result (U'1) of internal cell 72a and the operation result (S1) of boundary cell 71b, which are input to boundary cell 71b as input from the row direction, the operation result (U'2) of internal cell 72b, which is input from the column direction, and the value (X12) held by internal cell 72d, and outputs the operation result (U''2) to boundary cell 71c adjacent in the column direction, and outputs the operation result (U'1) and operation result (S1) as they are to internal cell 72e adjacent in the row direction. In addition, the value (X12) held by internal cell 72d is set / updated according to the operation result.

[0048] Similarly, each of the boundary cells 71a to 71c and each of the internal cells 72a to 72f performs a respective calculation and outputs the calculation result to the adjacent cell.

[0049] (Calculation algorithm for each boundary cell 71) Each boundary cell 71 (71a to 71c in the example shown in FIG. 2) performs a calculation process according to the following algorithm (see FIG. 3). When δ=0 or U=0, X←X δ'=δ S=0 In cases other than those mentioned above, BX = β 2(X+α) X ← BX+δ·|U| 2 DX = δ / X δ' = BX DX S = U DX

[0050] The meaning of each symbol in the above algorithm is as follows: δ: the result of the calculation in the preceding boundary cell 71 (a positive real number), input from the preceding boundary cell 71 to the boundary cell 71 in question (however, δ=1 is input to the first-stage boundary cell 71a). δ': the calculation result in the boundary cell 71 (a positive real number), output from the boundary cell 71 to the boundary cell 71 in the subsequent stage (however, the output from the boundary cell 71c in the final stage is used to calculate the error). U: Input signal to the boundary cell 71 in question (complex number), input to the boundary cell 71 in question from the adjacent internal cell 72 in the column direction (specifically, upward direction) (however, the RLS input signal U0 is input to the first-stage boundary cell 71a). X: A value that the boundary cell 71 has (also called an "internal state variable"; a positive real number). β: The square root of the forgetting factor λ in the QRDRLS algorithm (a positive real number). S: The result of the calculation in the boundary cell 71 (a complex number), output from the boundary cell 71 to the adjacent internal cell 72 in the row direction (specifically, to the right).

[0051] In the above algorithm, α is a regularization term for the QRDRLS operation, that is, the regularization term α is added to the algorithm for the operation processing in the boundary cell 71 (specifically, to the diagonal elements of the matrix).

[0052] In an overfitted polynomial, a complex curve is learned to pass through each point in the sample data, and the polynomial coefficients tend to be large. On the other hand, the coefficients of a polynomial without overfitting are smaller than those with overfitting. Therefore, by adding a penalty term (as a regularization term) for the magnitude of the coefficients to the objective function that minimizes the error, overfitting can be prevented and the distortion compensation process (specifically, the DPD process) can be stabilized.

[0053] The regularization term α is a small constant (fixed value) that is predetermined as a positive real number, and is not limited to a specific value, but is set to an appropriate value that is sufficiently small relative to the internal state variable X (i.e., the value that each boundary cell 71 has).

[0054] It is considered that the preferable value of the regularization term α varies depending on the fluctuation state of the RLS input signals U0, U1, U2 and the reference signal D, the number of calculation bits, etc., and therefore a preferable value may be selected by setting various conditions and performing simulations in advance to verify that overfitting can be effectively avoided, for example.

[0055] (Calculation algorithm in each internal cell 72) Each internal cell 72 (72a to 72f in the example shown in FIG. 2) performs a calculation process according to the following algorithm (see FIG. 4). (Calculation process 1) U'j = Uj-Ui·X (Calculation process 2) X ← S * ·U'j+X

[0056] The meaning of each symbol in the above algorithm is as follows: Ui: Input (complex number) to the internal cell 72 from the adjacent cell in the row direction (specifically, to the left). Uj: The result of the calculation in the adjacent internal cell 72 in the column direction (specifically, in the upward direction) (complex number), and the input to the internal cell 72 from the adjacent internal cell 72 in the column direction (specifically, in the upward direction) (however, RLS input signals U1 and U2 are input to the first-stage internal cells 72a and 72b, and reference signal D is input to the first-stage internal cell 72c). U'j: The calculation result of the internal cell 72 in question (a complex number), output from the internal cell 72 in question to the adjacent cell in the column direction (specifically, downward) (however, the output from the last internal cell 72f is used to calculate the error). X: The value of the internal cell 72 (also called "internal state variable"; complex number). S: The result of the calculation at the boundary cell 71 on the input side in the row direction (specifically, to the left) (complex number), and the input to the internal cell 72 from the adjacent cell in the row direction (specifically, to the left) (the subscript * represents a complex conjugate).

[0057] As a result of the above calculation process, an internal state variable (X00) is set in boundary cell 71a, an internal state variable (X01) is set in internal cell 72a, an internal state variable (X02) is set in internal cell 72b, and an internal state variable (X03) is set in internal cell 72c.

[0058] Furthermore, an internal state variable (X11) is set in the boundary cell 71b, an internal state variable (X12) is set in the internal cell 72d, and an internal state variable (X13) is set in the internal cell 72e.

[0059] Furthermore, an internal state variable (X22) is set in the boundary cell 71c, and an internal state variable (X23) is set in the internal cell 72f.

[0060] (Second half of the QRDRLS algorithm) 5 is a calculation block diagram for explaining the second half of the QRDRLS algorithm. In the second half of the QRDRLS algorithm, calculations are performed to move the array backward for the internal state variable X (see FIG. 2) obtained in the first half of the process.

[0061] The RLS input signals (U0, U1, U2) and the internal state variables (X12, X02, X01) set in each of the cells 72g, 72h, and 72i are set as shown in Fig. 5. Then, calculations are performed in each cell, and the calculation results are passed to the adjacent cells.

[0062] Specifically, first, the internal state variable (X23) of the internal cell 72f becomes the coefficient (W2) of the third term of the polynomial.

[0063] Furthermore, the internal state variable (X23) of the internal cell 72f is given to the internal cell 72g as an input (U0) from the row direction, and the internal state variable (X13) of the internal cell 72e is given to the internal cell 72g as an input (U1) from the column direction.

[0064] The internal cell 72g performs a calculation using the inputs (U0, U1) and the internal state variable (X12) of the internal cell 72d, and outputs the calculation result (U'1) in the column direction, while outputting the input (U0) as is to the adjacent internal cell 72h in the row direction. The calculation result (U'1) becomes the coefficient (W1) of the second term of the polynomial.

[0065] Furthermore, an input (U0) is given to the internal cell 72h from the internal cell 72g in the row direction, and the internal state variable (X03) of the internal cell 72c is given to the internal cell 72h as an input (U2) in the column direction.

[0066] The internal cell 72h performs an operation using the above inputs (U0, U2) and the internal state variable (X02) of the internal cell 72b, and outputs the operation result (U'2) to the internal cell 72i adjacent in the column direction.

[0067] The internal cell 72i is supplied with the operation result (U'1) of the internal cell 72g as an input from the row direction, and with the operation result (U'2) of the internal cell 72h as an input from the column direction.

[0068] The internal cell 72i performs a calculation using the above inputs (U'1, U'2) and the internal state variable (X01) of the internal cell 72a, and outputs the calculation result, which becomes the coefficient (W0) of the first term of the polynomial.

[0069] At this time, each internal cell 72 (72g, 72h, 72i in the examples shown in FIGS. 2 and 5) performs a calculation process according to the following algorithm (see FIG. 6). The calculation process below is the same as the "Calculation Process 1" (see FIG. 4) performed by each of the internal cells 72a to 72f. (Calculation process) U'j = Uj-Ui·X

[0070] According to the signal processing device 3 of the embodiment, when the regularization term α is added to the algorithm of the calculation processing in the boundary cell 71, the value of the regularization term α acts as a penalty term for the magnitude of the polynomial coefficients in the objective function when minimizing the error, thereby making it possible to avoid overfitting and stabilize the distortion compensation processing.

[0071] The above describes an embodiment of the present invention, but the specific configuration is not limited to the above embodiment, and even if there are design changes or the like within the scope of the gist of the present invention, they are included in the present invention.

[0072] For example, in the above embodiment, the distortion-compensated circuit is nonlinear amplifier 4, but the distortion-compensated circuits that can be covered by this invention are not limited to nonlinear amplifiers, and this invention can be applied to various circuits in which distortion occurs in the signal input to the circuit depending on the nonlinear characteristics / distortion characteristics of the circuit as the compensated circuit.

[0073] Furthermore, in the above embodiment, the distortion calculation unit 32 is supplied with the pre-distortion signal u(t) output from the distortion compensation unit 31 and calculates the inverse distortion characteristics of the distortion occurring in the nonlinear amplifier 4. However, the distortion calculation unit 32 may also be supplied with the input signal x(t) before it is input to the distortion compensation unit 31. In this case, the input signal x(t) serves as a reference signal for the distortion compensation process in the distortion compensation unit 31, and the distortion calculation unit 32 compares the input signal x(t) with a feedback signal y(t) and, based on the difference between the input signal x(t) and the feedback signal y(t), calculates values ​​of polynomial coefficients according to the QRDRLS algorithm so as to minimize the error of the feedback signal y(t) with respect to the input signal x(t). [Explanation of symbols]

[0074] 1 radio transmitter 2. Control section 2a Central Processing Unit (CPU) 2b Input / output section (I / O) 2c storage section 3. Signal Processing Device 31 Distortion compensation section 32 Distortion calculation section 4 Nonlinear Amplifier 5 Antennas 7 Systolic Array 71(71a,71b,71c) Boundary Cell 72(72a,72b,72c,72d,72e,72f) Internal Cell 72g, 72h, 72i Internal Cell

Claims

[Claim 1] A systolic array structure for performing calculations of a recursive least squares algorithm is provided, a regularization term is added to the recursive least squares algorithm; The systolic array structure includes: As calculated using the QR decomposition of a matrix and Givens rotation, a boundary cell element for performing boundary cell operations; an internal cell element for performing an internal cell operation; When a plurality of boundary cells and a plurality of internal cells are arranged in a systolic array, operations on the boundary cells and operations on the internal cells are performed by the boundary cell elements and the internal cell elements; a regularization term is added to the algorithm of the calculation process in the boundary cell; The algorithm for the calculation process in the boundary cell is When δ=0 or U=0, X←X δ' = δ S=0 In cases other than those mentioned above, BX = β2 (X + α) X ← BX+δ・|U|2 DX = δ / X δ' = BX DX S = U.DX Here, δ: Calculation result in the previous boundary cell δ': Calculation result for the boundary cell U: Input signal to the boundary cell X: The value of the boundary cell α: Regularization term for recursive least squares calculation β: The square root of the forgetting factor in the recursive least squares algorithm S: Calculation result for the boundary cell That is, A signal processing device comprising:

Images