Amplifier circuit

Abstract

To improve a distortion characteristic of an amplifier circuit.SOLUTION: An amplifier circuit comprises: a first FET Q1 that has a first semiconductor layer 12a, a first source electrode 14a connected with a first reference potential, a first gate electrode 18a for receiving a high-frequency signal, a first drain electrode 16a, and a first source wall 20a provided above the first gate electrode 18a; and a second FET Q2 that has a second semiconductor layer 12b, a second source electrode 14b connected with the first drain electrode 16a, a second gate electrode 18b connected with a second reference potential, a second drain electrode 16b for outputting the high-frequency signal, and a second source wall 20b provided above the second gate electrode 18b. A length L0b of the second source wall 20b in a direction in which the second source electrode 14b and the second drain electrode 16b are arranged is smaller than a length L0a of the first source wall 20a in a direction in which the first source electrode 14a and the first drain electrode 16a are arranged.SELECTED DRAWING: Figure 17

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, for example, an amplifier circuit having a field effect transistor.

Background Art

[0002] A high-frequency amplifier circuit is used in a base station of mobile communication. As a high-frequency amplifier circuit, an amplifier circuit in which a source-grounded field effect transistor (FET) and a gate-grounded FET are cascode-connected is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By using a cascode-connected amplifier circuit, the gain is improved. However, the distortion characteristics deteriorate.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to improve the distortion characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is an amplification circuit comprising: a first FET comprising: a first semiconductor layer; a first source electrode provided on the first semiconductor layer and connected at high frequency to a first reference potential; a first gate electrode provided on the first semiconductor layer to which a high-frequency signal is input; a first drain electrode provided on the first semiconductor layer; and a first source wall, at least a portion of which is provided above the first semiconductor layer between the first gate electrode and the first drain electrode; and a second FET comprising: a second semiconductor layer; a second source electrode provided on the second semiconductor layer and electrically connected to the first drain electrode; a second gate electrode provided on the second semiconductor layer and connected at high frequency to a second reference potential; a second drain electrode provided on the second semiconductor layer to which a high-frequency signal is output; and a second source wall, at least a portion of which is provided above the second semiconductor layer between the second gate electrode and the second drain electrode, wherein the length of the second source wall in the direction in which the second source electrode and the second drain electrode are aligned is smaller than the length of the first source wall in the direction in which the first source electrode and the first drain electrode are aligned.

[0007] One embodiment of the present disclosure is an amplification circuit comprising: a first FET having a first source connected at high frequency to a first reference potential, a first gate to which a high-frequency signal is input, and a first drain; and a second FET having a second source electrically connected to the first drain, a second gate connected at high frequency to a second reference potential, and a second drain to which a high-frequency signal is output, wherein the drain-source capacitance per unit gate width in the second FET is smaller than the drain-source capacitance per unit gate width in the first FET. [Effects of the Invention]

[0008] According to this disclosure, strain characteristics can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a circuit diagram of the amplification circuit according to Example 1. [Figure 2] Figure 2 shows the gain as a function of frequency in amplifier circuits A and B. [Figure 3] Figure 3 shows the equivalent circuit of a small-signal model in a common-source FET. [Figure 4] Figure 4 shows the equivalent circuit of a small-signal model in a common-gate FET. [Figure 5] Figure 5 shows the phase with respect to the input power Pin when the Cds2 of FETQ2 is changed in Simulation 1. [Figure 6] Figure 6 shows the phase with respect to the input power Pin when the Cgs2 of FETQ2 is changed in Simulation 1. [Figure 7] Figure 7 shows the phase with respect to the input power Pin when the Cgd2 of FETQ2 is changed in Simulation 1. [Figure 8] Figure 8 shows the phase with respect to output power Pout in amplifier circuits C and D in Simulation 2. [Figure 9] Figure 9 is a plan view of the FET used in Example 2. [Figure 10] Figure 10 is a cross-sectional view of the FET used in Example 2. [Figure 11] Figure 11 shows the Cds, Cgd, and Cgs for L1 in Simulation 2. [Figure 12] Figure 12 shows the Cds, Cgd, and Cgs for L2 in Simulation 2. [Figure 13] Figure 13 shows the Cds, Cgd, and Cgs for L3 in Simulation 3. [Figure 14] Figure 14 is a cross-sectional view of FETQ1 and Q2 in Example 2. [Figure 15] Figure 15 is a cross-sectional view of FETQ1 and Q2 in Modification 1 of Example 2. [Figure 16] Figure 16 is a cross-sectional view of FETQ1 and Q2 in a modified example 2 of Example 2. [Figure 17] FIG. 17 is a cross-sectional view of FETs Q1 and Q2 in Modification 3 of Example 2. [Figure 18] FIG. 18 is a plan view of FETs Q1 and Q2 in Modification 4 of Example 2. [Mode for Carrying Out the Invention]

[0010] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first semiconductor layer, a first source electrode provided on the first semiconductor layer and connected to a first reference potential in a high-frequency manner, a first gate electrode provided on the first semiconductor layer to which a high-frequency signal is input, a first drain electrode provided on the first semiconductor layer, and a first source wall provided at least partially above the first semiconductor layer between the first gate electrode and the first drain electrode. A first FET including: a second semiconductor layer; a second source electrode provided on the second semiconductor layer and electrically connected to the first drain electrode; a second gate electrode provided on the second semiconductor layer and connected to a second reference potential in a high-frequency manner; a second drain electrode provided on the second semiconductor layer to which a high-frequency signal is output; and a second source wall provided at least partially above the second semiconductor layer between the second gate electrode and the second drain electrode. A second FET, wherein the length of the second source wall in the direction in which the second source electrode and the second drain electrode are arranged is smaller than the length of the first source wall in the direction in which the first source electrode and the first drain electrode are arranged. This is an amplifier circuit. Thereby, distortion characteristics such as AM-PM characteristics can be improved. (2) In the above (1), the position of the end on the second source electrode side of the second source wall with respect to the second gate electrode is preferably located closer to the second drain electrode side than the position of the end on the first source electrode side of the first source wall with respect to the first gate electrode. (3) In the above (1) or (2), the position of the end on the second drain electrode side in the second source wall with reference to the second gate electrode is preferably located on the second source electrode side with respect to the position of the end on the first drain electrode side in the first source wall with reference to the first gate electrode. (4) In any of the above (1) to (3), it is preferable that at least a part of the second source wall overlaps at least a part of the second gate electrode when viewed from the thickness direction of the second semiconductor layer. (5) In any of the above (1) to (4), it is preferable that the first source wall and the first source electrode are at the same potential, and the second source wall and the second source electrode are at the same potential. (6) In any of the above (1) to (5), it is preferable that the first semiconductor layer and the second semiconductor layer are provided on the same substrate, and the first drain electrode and the second source electrode are provided as a common electrode. (7) One embodiment of the present disclosure includes a first FET including a first source that is connected to a first reference potential in a high-frequency manner, a first gate to which a high-frequency signal is input, and a first drain, a second source electrically connected to the first drain, a second gate that is connected to a second reference potential in a high-frequency manner, and a second drain from which a high-frequency signal is output. The drain-source capacitance per unit gate width in the second FET is smaller than the drain-source capacitance per unit gate width in the first FET. Thereby, distortion characteristics such as AM-PM characteristics can be improved. (8) In the above (7), it is preferable that the gate-drain capacitance per unit gate width in the second FET is larger than the gate-drain capacitance per unit gate width in the first FET.

[0011] [Details of Embodiments of the Present Disclosure] Specific examples of amplification circuits according to embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to these examples, and all modifications within the meaning and scope of the claims are intended to be included.

[0012] [Example 1] Figure 1 is a circuit diagram of an amplifier circuit according to Embodiment 1. As shown in Figure 1, the amplifier circuit 50 includes cascode-connected FETs Q1 and Q2. FET Q1 is a source-grounded FET. FET Q2 is a gate-grounded FET. The source S1 of FET Q1 is high-frequency connected to ground (first reference potential). The gate G1 is connected to the input terminal Tin, and a high-frequency signal of input power Pin is input to it. The drain D1 is connected to the source S2 of FET Q2. The source S2 of FET Q2 is connected to the drain D1 of FET Q1. The gate G2 is connected to ground (second reference potential) via capacitor C1. The drain D2 is connected to the output terminal Tout, which outputs a high-frequency signal of output power Pout. Since the gate G2 is grounded via capacitor C1, the gate G2 is high-frequency grounded. The gate bias voltage Vg of FET Q2 is applied to the gate G2. An impedance matching circuit (not shown) and a bias circuit that supplies a gate bias voltage to gate G1 are connected between gate G1 and input terminal Tin. An impedance matching circuit (not shown) and a bias circuit that supplies a drain bias voltage to drain D2 are connected between drain D2 and output terminal Tout. The gate widths of FETs Q1 and Q2 may be the same or different.

[0013] FETQ1 and Q2 are, for example, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or LDMOS (Laterally Diffused Metal Oxide Semiconductor). FETQ1 and Q2 may also be GaAs-based FETs. The center frequency of the bandwidth of the amplification circuit 50 is, for example, 0.5 GHz to 10 GHz, and it is used, for example, in a mobile communication base station.

[0014] Examples of gain are shown for amplifier circuit A, which has cascode-connected FETs as in Example 1, and amplifier circuit B, which has only a common-source FET and no common-gate FET. Figure 2 shows the gain as a function of frequency for amplifier circuits A and B. In Figure 2, the horizontal axis is frequency and the vertical axis is gain. As shown in Figure 2, amplifier circuit A has a greater gain than amplifier circuit B. Also, amplifier circuit A can produce a greater output power Pout than amplifier circuit B.

[0015] In high-frequency power amplifiers, improving the AM (Amplitude Modulation)-PM (Phase Modulation) characteristics is required as one of the distortion characteristics. The AM-PM characteristic is the characteristic in which the phase difference between the input signal and the output signal changes as the input power (or output power) increases. It is preferable that the phase does not change even when the input power increases. The AM-PM characteristic can be suppressed by reducing the reactance component of the Y parameter Y21 of the FET.

[0016] Figure 3 shows the equivalent circuit of a small-signal model in a common-source FET. As shown in Figure 3, in FETQ1, the source S1 is grounded, a high-frequency signal is input to the gate G1, and a high-frequency signal is output from the drain D1. The drain-source current is represented by the current source gmVgs. The node on the source S1 side of the current source gmVgs is connected to the source S1 via the source resistor Rs. The drain-source resistor Rds and drain-source capacitance Cds are connected in parallel to the current source gmVgs. The node on the drain D1 side of the current source gmVgs is connected to the drain D1 via the drain resistor Rd. The gate-drain capacitance Cgd and gate resistor Rg are connected in series between the node on the drain D1 side of the current source gmVgs and the gate G1. The gate-source capacitance Cgs and channel resistor Ri are connected in series between the node between Cgd and Rg and the node between gmVgs and Rs. When gate G1 is designated as port 1 and drain D1 as port 2, the Y parameter Y21 = gm - jωCgd. Therefore, in a common-source FETQ1, the AM-PM characteristics can be improved by reducing Cgd.

[0017] Figure 4 shows the equivalent circuit of a small-signal model in a common-gate FET. As shown in Figure 4, in FETQ2, the gate G2 is grounded, a high-frequency signal is input to source S2, and a high-frequency signal is output from drain D2. When source S2 is port 1 and drain D2 is port 2, the Y parameter Y21 = -gm - jωCds. Therefore, in a common-source FETQ2, the AM-PM characteristics can be improved by reducing Cds.

[0018] [Simulation 1] In Simulation 1, the AM-PM characteristics of gate-grounded FETQ2 alone were simulated. The gate G2 of FETQ2 was grounded, a high-frequency signal was input to source S2 as the input signal, and a high-frequency signal was output from drain D2 as the output signal. The input power of the input signal was defined as Pin, and the phase difference between the output signal and the input signal was defined as the phase. The capacitances Cds2, Cgs2, and Cgd2 in FETQ2 were set as follows. First, Cds1, Cgs1, and Cgd1 of source-grounded FETQ1 were set to improve the AM-PM characteristics of source-grounded FETQ1 alone. Based on the values ​​of Cds1, Cgd1, and Cgs1 of FETQ1, the values ​​of Cds2, Cgd2, and Cgs2 of gate-grounded FETQ2 were set. FETQ1 and Q2 are GaN HEMTs. The gate widths of FETQ1 and Q2 are the same.

[0019] Simulations were conducted for the cases where Cgs2 and Cgd2 of FETQ2 were set to Cgs1 and Cgd1, respectively, and Cds2 was set to 0.5×Cds1, 1×Cds1, and 2×Cds1. Figure 5 shows the phase with respect to the input power Pin when Cds2 of FETQ2 is changed in Simulation 1. The horizontal axis shows the input power Pin input to the input terminal Tin, and the vertical axis shows the phase difference between the high-frequency signal input to the input terminal Tin and the high-frequency signal output from the output terminal Tout. As shown in Figure 5, when Cds2 is 0.5×Cds1, the phase remains almost constant from Pin -20dBm up to 5dBm. The phase increases when Pin is 15-20dBm, and then decreases sharply as Pin increases further. The difference ΔP0.5 between the phase when Pin is small and the phase at the phase peak is approximately 2°. When Cds2 is 1×Cds1, the difference ΔP1 between the phase when Pin is small and the phase at the phase peak is approximately 4°. When Cds2 is 2×Cds1, the difference ΔP2 between the phase when Pin is small and the phase at the phase peak is approximately 8°. Thus, in a gate-common FETQ2, if Cds2 is made smaller than the optimized Cds1 in a source-common FETQ1, ΔP becomes smaller.

[0020] Simulations were conducted for the cases where Cds2 and Cgd2 of FETQ2 were set to Cds1 and Cgd1, respectively, and Cgs2 was set to 0.5×Cgs1, 1×Cgs1, and 2×Cgs1. Figure 6 shows the phase with respect to the input power Pin when Cgs2 of FETQ2 is changed in Simulation 1. As shown in Figure 6, ΔP0.5, ΔP1, and ΔP2 are all 7-8°. Thus, in a gate-grounded FETQ2, ΔP hardly changes even when Cgs2 is changed.

[0021] Simulations were conducted for the cases where Cds2 and Cgs2 of FETQ2 were set to Cds1 and Cgs1, respectively, and Cgd2 was set to 0.5×Cgd1, 1×Cgd1, and 2×Cgd1. Figure 7 shows the phase with respect to the input power Pin when Cgd2 of FETQ2 is changed in Simulation 1. As shown in Figure 7, ΔP0.5, ΔP1, and ΔP2 are all 2 to 3°. Thus, in a gate-grounded FETQ2, ΔP hardly changes even when Cgd2 is changed.

[0022] As described above, in the gate-grounded FETQ2, reducing Cds2 reduces ΔP, which means the AM-PM characteristics improve. The AM-PM characteristics are almost independent of Cgs and Cgd. This is because, as explained in Figure 4, the reactance component of Y21 in the gate-grounded FETQ2 is mainly Cds. As explained in Figure 3, in the source-grounded FETQ1, the reactance component of Y21 is mainly Cgd. Therefore, in the source-grounded FETQ1, reducing Cgs improves the AM-PM characteristics, and the AM-PM characteristics are almost independent of Cds and Cgs.

[0023] [Simulation 2] In Simulation 2, the AM-PM characteristics of an amplifier circuit 50 having FETQ1 and Q2 were simulated. The Cgs2 and Cgd2 of FETQ2 were set to the same values ​​as the Cgs1 and Cgd1 of FETQ1, respectively. In amplifier circuit C, the Cds2 of FETQ2 was set to 1 × Cds1. In amplifier circuit D, the Cds2 of FETQ2 was set to 0.5 × Cds1. The phase with respect to output power Pout (phase difference between input signal and output signal) was simulated for amplifier circuits C and D. Figure 8 shows the phase with respect to output power Pout in amplifier circuits C and D in Simulation 2. As shown in Figure 8, the phase is almost constant for both amplifier circuits C and D when Pout is 40 dB or less. In amplifier circuit C, the phase changes sharply when Pout is 40 dBm or more, with a phase change of approximately 10°. In amplifier circuit D, the phase does not change significantly even when Pout is 40 dBm or more, with a phase change of approximately 2°. In this way, by making the Cds2 of FETQ2 smaller than the Cds1 of FETQ1, the AM-PM characteristics of the amplification circuit can be improved.

[0024] According to Embodiment 1, FETQ1 (first FET) comprises a source S1 (first source) that is high-frequency connected to ground (first reference potential), a gate G1 (first gate) into which a high-frequency signal is input, and a drain D1 (first drain). FETQ2 (second FET) comprises a source S2 (second source) connected to drain D1, a gate G2 (second gate) that is high-frequency connected to ground (second reference potential), and a drain D2 (second drain) into which the amplified high-frequency signal is output. Note that high-frequency connection means that the connection is made at a frequency within the bandwidth of the amplification circuit 50. In the cascode amplification circuit 50 having FETQ1 and Q2, the drain-source capacitance Cds2 per unit gate width Wg in FETQ2 is smaller than the drain-source capacitance Cds1 per unit gate width Wg in FETQ1. As a result, the AM-PM characteristics of FETQ2 can be improved, as shown in Figure 5. Therefore, the AM-PM characteristics of the amplification circuit 50 can be improved, as shown in Figure 8.

[0025] To improve the AM-PM characteristics of FETQ2, the Cds2 per unit gate width Wg in FETQ2 is preferably 0.9 times or less, more preferably 0.8 times or less, and even more preferably 0.6 times or less, compared to the Cds1 per unit gate width Wg in FETQ1. FETs with small Cds2 are difficult to realize. Therefore, the Cds2 per unit gate width Wg is preferably 0.1 times or more, and more preferably 0.2 times or more, compared to the Cds2 per unit gate width Wg in FETQ1.

[0026] The gate drain capacitance Cgd2 per unit gate width in FETQ2 is greater than the gate drain capacitance Cgd1 per unit gate width in FETQ1. This improves the AM-PM characteristics of FETQ1. Therefore, the AM-PM characteristics of the amplifier circuit 50 can be improved. To improve the AM-PM characteristics of FETQ1, the Cgd1 per unit gate width Wg in FETQ1 is preferably 0.9 times or less, more preferably 0.8 times or less, and even more preferably 0.6 times or less, than the Cgd2 per unit gate width Wg in FETQ2. FETs with small Cgd1 are difficult to realize. For this reason, the Cgd1 per unit gate width Wg is preferably 0.1 times or more, and more preferably 0.2 times or more, than the Cgd2 per unit gate width Wg.

[0027] [Example 2]

[0028] Figure 9 is a plan view of the FET used in Example 2. Figure 10 is a cross-sectional view of the FET used in Example 2. The normal direction of the substrate 10 is the Z direction, the direction from the source electrode 14 to the drain electrode 16 is the X direction, and the extension direction of the source electrode 14, drain electrode 16 and gate electrode 18 is the Y direction.

[0029] As shown in Figures 9 and 10, a semiconductor layer 12 is provided on a substrate 10. In the case of a GaN HEMT, the substrate 10 is, for example, a SiC substrate, a sapphire substrate, or a GaN substrate. The semiconductor layer 12 consists of, for example, a GaN channel layer and an AlGaN barrier layer from the substrate 10 side. The region of the semiconductor layer 12 that has been deactivated by ion implantation or the like is an inactive region, and the region that has not been deactivated is an active region 11. A source electrode 14, a drain electrode 16, and a gate electrode 18 are provided on the active region 11 of the semiconductor layer 12. In the X direction, the gate electrode 18 is sandwiched between the source electrode 14 and the drain electrode 16. The source electrode 14 and the drain electrode 16 are metal layers, for example, a titanium layer and an aluminum layer from the semiconductor layer 12 side. The gate electrode 18 is a metal layer, for example, a nickel layer and a gold layer from the semiconductor layer 12 side. An insulating film 24 is provided on the semiconductor layer 12 so as to cover the source electrode 14, the drain electrode 16, and the gate electrode 18. The insulating film 24 is, for example, a silicon nitride film.

[0030] A source wall 20 is provided within the insulating film 24. The source wall 20 comprises a top portion 25, a wall portion 26, and a bottom portion 27. The upper and lower surfaces of the top portion 25 and the bottom portion 27 are substantially parallel to the XY plane. The lower surface of the top portion 25 is located above the gate electrode 18 (in the +Z direction). The lower surface of the bottom portion 27 is located below the upper surface of the gate electrode 18 (in the -Z direction). The wall portion 26 is located between the gate electrode 18 and the drain electrode 16, with the top portion 25 connected to the upper part of the -X side and the bottom portion 27 connected to the lower part of the +X side. The source wall 20 and the source electrode 14 are electrically connected and short-circuited by connecting wiring 22. As a result, the potentials of the source electrode 14 and the source wall 20 are approximately the same. The potential of the source wall 20 may be a potential other than that of the source electrode 14. The source wall 20 and the connecting wiring 22 are metal layers, for example, a gold layer.

[0031] By having at least a portion of the source wall 20 positioned above the semiconductor layer 12 between the gate electrode 18 and the drain electrode 16, the gate-drain breakdown voltage can be improved. Furthermore, the Cgd can be reduced. In a plan view, if at least a portion of the top portion 25 overlaps with at least a portion of the gate electrode 18, the Cgd can be further suppressed. In a plan view, the top portion 25 and the gate electrode 18 do not necessarily have to overlap.

[0032] The distance between the source electrode 14 and the gate electrode 18 is the source-gate distance Lsg, the distance between the gate electrode 18 and the drain electrode 16 is the gate-drain distance Lgd, and the length of the gate electrode 18 in the X direction is the gate length Lg. The width of the active region 11 in the Y direction is the gate width Wg. Let T1 be the thickness of the top portion 25 and the bottom portion 27, T2 be the height from the top surface of the semiconductor layer 12 to the bottom surface of the top portion 25, T3 be the height from the top surface of the semiconductor layer 12 to the bottom surface of the bottom portion 27, and T4 be the height from the top surface of the gate electrode 18 to the bottom surface of the top portion 25. Let X1 be the position of the -X side end of the top portion 25, X2 be the position of the +X side end of the bottom portion 27, X3 be the position of the -X side surface of the wall portion 26, X4 be the position of the +X side surface of the wall portion 26, and X5 be the position of the +X side surface of the gate electrode 18. Let L0 be the length of the source wall 20 in the X direction. Let L1 be the length of the top portion 25 in the X direction, L2 be the length of the bottom portion 27 in the X direction, L3 be the distance in the X direction between the gate electrode 18 and the wall portion 26, and L4 be the length of the wall portion 26 in the X direction.

[0033] [Simulation 2] We simulated Cds, Cgs, and Cgd by varying lengths L1, L2, and distance L3. The basic simulation conditions are as follows: Lsg=0.95μm, Lgd=3.15μm, Lg=0.5μm, Wg=1.26μm, T1=0.2μm, T2=0.6μm, T3=0.2μm, T4=0.2μm, L1=0.75μm, L2=0.35μm, L3=0.5μm, L4=0.5μm Insulating film 24: Silicon nitride film

[0034] Figure 11 shows the Cds, Cgd, and Cgs relative to L1 in Simulation 2. Dimensions other than L1 are as shown above. As shown in Figure 11, as L1 increases, Cds increases, Cgd decreases, and Cgs increases. Therefore, in FETQ1, Cgd can be reduced by increasing L1, and in FETQ2, Cds can be reduced by shortening L1. This improves the AM-PM characteristics.

[0035] Figure 12 shows the Cds, Cgd, and Cgs values ​​with respect to L2 in Simulation 2. Dimensions other than L2 are as shown above. As shown in Figure 12, as L2 increases, Cds increases, Cgd decreases, and Cgs remains almost unchanged. Therefore, the AM-PM characteristics can be improved by increasing L2 in FETQ1 and shortening L1 in FETQ2.

[0036] Figure 13 shows the Cds, Cgd, and Cgs values ​​with respect to L3 in Simulation 3. The position X1 at the end of the top section 25 remains unchanged, and as L3 lengthens, L1 lengthens. L2 and L4 remain unchanged. The distance between position X3 and X1 is set to 0.75 μm. The dimensions other than L1 and L3 are as shown above. As shown in Figure 13, as L3 lengthens, Cds increases, and Cgd and Cgs decrease. Therefore, the AM-PM characteristics can be improved by lengthening L3 in FETQ1 and by shortening L3 in FETQ2.

[0037] Figure 14 is a cross-sectional view of FETQ1 and Q2 in Example 2. As shown in Figure 14, in FETQ1, a semiconductor layer 12a is provided on a substrate 10a, and a source electrode 14a, a drain electrode 16a, and a gate electrode 18a are provided on the semiconductor layer 12a. An insulating film 24a is provided on the semiconductor layer 12a so as to cover the source electrode 14a, the drain electrode 16a, and the gate electrode 18a. A source wall 20a is provided within the insulating film 24a. The source wall 20a has a top portion 25a, a wall portion 26a, and a bottom portion 27a. In FETQ2, a semiconductor layer 12b is provided on a substrate 10b, and a source electrode 14b, a drain electrode 16b, and a gate electrode 18b are provided on the semiconductor layer 12b. An insulating film 24b is provided on the semiconductor layer 12b so as to cover the source electrode 14b, the drain electrode 16b, and the gate electrode 18b. A source wall 20b is provided within the insulating film 24b. The source wall 20b comprises a top section 25b, a wall section 26b, and a bottom section 27b. The structures of the other FETs Q1 and Q2 are the same as in Figures 9 and 10, and their description is omitted. The circuit diagram of the amplification circuit is the same as in Figure 1 of Embodiment 1, and its description is omitted.

[0038] The length L1b of the top portion 25b in FETQ2 is smaller than the length L1a of the top portion 25a in FETQ1. Therefore, the length L0b of the source wall 20b in FETQ2 is smaller than the length L0a of the source wall 20a in FETQ2. As a result, as shown in Figure 11, the Cds2 of FETQ2 is smaller than the Cds1 of FETQ1. The Cgd1 of FETQ1 is smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplification circuit can be improved.

[0039] [Modification 1 of Example 2] Figure 15 is a cross-sectional view of FETQ1 and Q2 in Modification 1 of Example 2. As shown in Figure 15, the length L2b of the bottom portion 27b in FETQ2 is smaller than the length L2a of the bottom portion 27a in FETQ1. Therefore, the length L0b of the source wall 20b in FETQ2 is smaller than the length L0a of the source wall 20a in FETQ1. The other configurations are the same as in Figure 14 of Example 1 and will not be described. In Modification 1 of Example 2, as shown in Figure 12, the Cds2 of FETQ2 is smaller than the Cds1 of FETQ1. The Cgd1 of FETQ1 is smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplification circuit can be improved.

[0040] [Modification 2 of Example 2] Figure 16 is a cross-sectional view of FETQ1 and Q2 in Modification 2 of Example 2. As shown in Figure 16, the distance L3b between the gate electrode 18b and the wall portion 26b in FETQ2 is smaller than the distance L3a between the gate electrode 18a and the wall portion 26a in FETQ1. As a result, the length L1b of the top portion 25b in FETQ2 is smaller than the length L1a of the top portion 25a in FETQ1, and the length L0b of the source wall 20b in FETQ2 is smaller than the length L0a of the source wall 20a in FETQ1. The other configurations are the same as in Figure 14 of Example 1 and will not be described. In Modification 2 of Example 2, as shown in Figure 13, the Cds2 of FETQ2 is smaller than the Cds1 of FETQ1. The Cgd1 of FETQ1 is smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplification circuit can be improved.

[0041] [Modification 3 of Example 2] Figure 17 is a cross-sectional view of FETQ1 and Q2 in Modification 3 of Example 2. As shown in Figure 17, the position X1b of the -X end of the source wall 20b of FETQ2 is located on the +X side than the position X1a of the -X end of the source wall 20a of FETQ1. The position X2b of the +X end of the source wall 20b of FETQ2 is located on the -X side than the position X2a of the -X end of the source wall 20a of FETQ1. The length L0b of the source wall 20b of FETQ2 is smaller than the length L0a of the source wall 20a of FETQ1. If the length L0 of the source wall 20 is long, the number of electric field lines between the source wall 20 and the drain electrode 16 increases, so the Cds increases. On the other hand, the electric field lines between the gate electrode 18 and the drain electrode 16 are obstructed by the source wall 20, so the Cds decreases. Therefore, in Modification 3 of Example 2, the Cds2 of FETQ2 is smaller than the Cds1 of FETQ1. The Cgd1 of FETQ1 is smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplification circuit can be improved.

[0042] The cross-sectional shapes of the source walls 20a and 20b may be overlapping rectangles, as in Example 2 and its modified examples 1 and 2. The upper and lower surfaces of the source walls 20a and 20b may be inclined with respect to the XY plane, as in Modified Example 3 of Example 2. From the viewpoint of improving gate-drain breakdown voltage, it is preferable that the distance T2a between the -X side end of the source wall 20a and the upper surface of the semiconductor layer 12a is greater than the distance T3a between the +X side end of the source wall 20a and the upper surface of the semiconductor layer 12a. It is preferable that the distance T2b between the -X side end of the source wall 20b and the upper surface of the semiconductor layer 12b is greater than the distance T3b between the +X side end of the source wall 20b and the upper surface of the semiconductor layer 12b. From the viewpoint of hindering the electric field lines between the gate electrode 18 and the drain electrode 16 and reducing Cgd, it is preferable that at least a part of the source wall 20a overlaps at least a part of the gate electrode 18a in a plan view.

[0043] In Example 2 and its variations 1-3, substrates 10a and 10b may be a single substrate. That is, FETQ1 and FETQ2 may be provided on the same chip, or they may be provided on different chips.

[0044] [Modification 4 of Example 2] Figure 18 is a plan view of FETQ1 and Q2 in Modification 4 of Embodiment 2. As shown in Figure 18, FETQ1 and Q2 are provided on the same substrate 10 and semiconductor layer 12. The drain electrode 16a of FETQ1 and the source electrode 14b of FETQ2 are common electrodes. In FETQ1, a gate electrode 18a is provided between the source electrode 14a and the drain electrode 16a, and a source wall 20a is provided overlapping the gate electrode 18a. Connecting wire 22a electrically connects the source electrode 14a and the source wall 20a. In FETQ2, a gate electrode 18b is provided between the source electrode 14b and the drain electrode 16b, and a source wall 20b is provided overlapping the gate electrode 18b. Connecting wire 22b electrically connects the source electrode 14b and the source wall 20b. In Modification 4 of Embodiment 2, the drain electrode 16a and the source electrode 14b are provided in common. This makes it possible to reduce the parasitic inductance between FETQ1 and Q2. Therefore, the amplification circuit is stabilized.

[0045] According to Example 2 and its modified form, FETQ1 comprises a semiconductor layer 12a (first semiconductor layer), a source electrode 14a (first source electrode), a drain electrode 16a (first drain electrode), a gate electrode 18a (first gate electrode), and a source wall 20a (first source wall) provided on the semiconductor layer 12a. The source electrode 14a is connected to ground (first reference potential) at a high frequency. The gate electrode 18a receives a high frequency signal. At least a portion of the source wall 20a is provided above the semiconductor layer 12a between the gate electrode 18a and the drain electrode 16a. FETQ2 comprises a semiconductor layer 12b (second semiconductor layer), a source electrode 14b (second source electrode), a drain electrode 16b (second drain electrode), a gate electrode 18b (second gate electrode), and a source wall 20b (second source wall) provided on the semiconductor layer 12b. The source electrode 14b is connected to the drain electrode 16a. The gate electrode 18b is connected to ground (second reference potential) at a high frequency. The drain electrode 16b outputs a high-frequency signal. At least a portion of the source wall 20b is located above the semiconductor layer 12b between the gate electrode 18b and the drain electrode 16b. In such an amplifier circuit, the length L0b of the source wall 20b in the X direction is smaller than the length L0a of the source wall 20a in the X direction.

[0046] As a result, as shown in Figures 11 to 13, the Cds2 of FETQ2 becomes smaller than the Cds1 of FETQ1, and the Cgd1 of FETQ1 becomes smaller than the Cgd2 of FETQ2. Therefore, the AM-PM of FETQ1 and Q2 can be improved, and the AM-PM characteristics of the amplification circuit can be improved. The length L0b is preferably 0.9 times or less of the length L0a, and more preferably 0.8 times or less. If the length L0b is too small, it will not function as a source wall 20b. Therefore, the length L0b is preferably 0.1 times or more of the length L0a, and more preferably 0.2 times or more.

[0047] As shown in Figure 14 of Example 2 and Figure 17 of Modification 3 of Example 1, the position X1b at the source electrode 14b side end of the source wall 20b with reference to the gate electrode 18b is located closer to the drain electrode 16b than the position X1a at the source electrode 14a side end of the source wall 20a with reference to the gate electrode 18a. As a result, the Cds2 of FETQ2 becomes smaller than the Cds1 of FETQ1, and the Cgd1 of FETQ1 becomes smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplifier circuit 50 can be improved. The difference between the position X1b with reference to the gate electrode 18b and the position X1a with reference to the gate electrode 18a is preferably 0.1 × Lg or more, and more preferably 0.2 × Lg or more.

[0048] As shown in Figures 15 to 17 of Modifications 1 to 3 of Example 2, the position X2b at the drain electrode 16b side end of the source wall 20b with reference to the gate electrode 18b is located closer to the source electrode 14a than the position X2a at the drain electrode 16a side end of the source wall 20a with reference to the gate electrode 18a. As a result, the Cds2 of FETQ2 becomes smaller than the Cds1 of FETQ1, and the Cgd1 of FETQ1 becomes smaller than the Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplifier circuit 50 can be improved. The difference between the position X2b with reference to the gate electrode 18b and the position X2a with reference to the gate electrode 18a is preferably 0.1 × Lg or more, and more preferably 0.2 × Lg or more.

[0049] As shown in Figures 14 to 17 of Example 2 and its modified form, when viewed from the thickness direction of the semiconductor layer 12b, at least a portion of the source wall 20a overlaps with at least a portion of the gate electrode 18b. This reduces the Cds2 of FETQ2 and increases the Cgd2. Therefore, the AM-PM characteristics of the amplifier circuit 50 can be improved.

[0050] Source wall 20a and source electrode 14a are at the same potential, and source wall 20b and source electrode 14b are at the same potential. As a result, Cds2 of FETQ2 becomes smaller than Cds1 of FETQ1, and Cgd1 of FETQ1 becomes smaller than Cgd2 of FETQ2. Therefore, the AM-PM characteristics of the amplifier circuit 50 can be improved. Note that "at the same potential (or substantially at the same potential)" means that the potentials are at a level that allows for voltage drop due to the resistance of the conductive layers such as connecting wires 22a and 22b.

[0051] As shown in Figure 18 of Modification 4 of Example 2, FETs Q1 and Q2 are provided on the same substrate 10. The drain electrode 16a and source electrode 14b are provided as common electrodes. This suppresses parasitic inductance between FETs Q1 and Q2. Therefore, the amplification circuit can operate stably.

[0052] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications are intended to be in the sense and scope equivalent to the claims. [Explanation of symbols]

[0053] 10, 10a, 10b substrates 11 Active area 12 Semiconductor layer 12a Semiconductor layer (first semiconductor layer) 12b Semiconductor layer (second semiconductor layer) 14 Source electrodes 14a Source electrode (first source electrode) 14b Source electrode (second source electrode) 16 Drain electrode 16a Drain electrode (first drain electrode) 16b Drain electrode (second drain electrode) 18 Guard gate 18a Grid gate (first grid gate) 18b Guard gate (second guard gate) 20 Sourcewall 20a Source Wall (First Source Wall) 20b Source Wall (Second Source Wall) 22, 22a, 22b Connection wiring 24, 24a, 24b insulating film 25, 25a, 25b Top section 26, 26a, 26b wall section 27, 27a, 27b Bottom section 50 Amplifier Circuit Q1 FET (First FET) Q2 FET (2nd FET) S1 Source (First Source) S2 Source (Second Source) D1 Drain (First Drain) D2 Drain (Second Drain) G1 Gate (Gate 1) G2 Gate (Gate 2)

Claims

1. A first FET comprising: a first semiconductor layer; a first source electrode provided on the first semiconductor layer and connected to a first reference potential at a high frequency; a first gate electrode provided on the first semiconductor layer to which a high-frequency signal is input; a first drain electrode provided on the first semiconductor layer; and a first source wall provided above the first semiconductor layer between the first gate electrode and the first drain electrode, at least a portion of which is provided; A second FET comprising: a second semiconductor layer; a second source electrode provided on the second semiconductor layer and electrically connected to the first drain electrode; a second gate electrode provided on the second semiconductor layer and high-frequency connected to a second reference potential; a second drain electrode provided on the second semiconductor layer and outputting a high-frequency signal; and a second source wall, at least a portion of which is provided above the second semiconductor layer between the second gate electrode and the second drain electrode; Equipped with, The first source wall and the second source wall are metal layers. The planar shape of the first source wall and the planar shape of the second source wall are rectangular. The first semiconductor layer has a first active region, The second semiconductor layer has a second active region, On the first active region of the first semiconductor layer, the first source electrode, the first gate electrode, and the first drain electrode are arranged in this order along a first direction and extend in a second direction intersecting the first direction. On the second active region of the second semiconductor layer, the second source electrode, the second gate electrode, and the second drain electrode are arranged in this order along the third direction and extend in a fourth direction intersecting the third direction. The width of the first active region in the second direction is the same as the width of the second active region in the fourth direction. The first source wall and the first source electrode are at the same potential. The second source wall and the second source electrode are at the same potential. The first source wall traverses the first active region in the second direction, The second source wall traverses the second active region in the fourth direction, In the first direction, the first source wall is spaced apart from the first source electrode and the first drain electrode. In the third direction, the second source wall is spaced apart from the second source electrode and the second drain electrode. An amplifier circuit in which the length of the second source wall in the third direction is smaller than the length of the first source wall in the first direction.

2. When viewed in the thickness direction of the first semiconductor layer, at least a portion of the first source wall overlaps with at least a portion of the first gate electrode, Viewed from the thickness direction of the second semiconductor layer, at least a portion of the second source wall overlaps with at least a portion of the second gate electrode, The amplifier circuit according to claim 1, wherein, in the third direction, the position of the end of the second source wall on the second source electrode side, with reference to the end of the second gate electrode on the second drain electrode side, is located on the second drain electrode side of the position of the end of the first source wall on the first source electrode side, with reference to the end of the first gate electrode on the first drain electrode side, in the first direction.

3. The amplifier circuit according to claim 1, wherein in the third direction, the position of the end of the second source wall on the second drain electrode side with reference to the end of the second gate electrode on the second drain electrode side is located on the second source electrode side of the position of the end of the first source wall on the first drain electrode side with reference to the end of the first gate electrode on the first drain electrode side in the first direction.

4. The amplification circuit according to claim 1, wherein, viewed from the thickness direction of the second semiconductor layer, at least a portion of the second source wall overlaps with at least a portion of the second gate electrode.

5. The first semiconductor layer and the second semiconductor layer are provided on the same substrate. The amplification circuit according to any one of claims 1 to 4, wherein the first drain electrode and the second source electrode are provided as common electrodes.

Images