LCD display with optical sensor

Abstract

To provide a liquid crystal display device with an optical sensor with which it is possible to realize a narrowed frame.SOLUTION: A liquid crystal display device with an optical sensor according to one embodiment comprises a display panel and a driver IC. The display panel includes a first signal line corresponding to a red color, a second signal line corresponding to a green color, and a third signal line corresponding to a blue color, an optical sensor that outputs a detection signal corresponding to incident light, and a sensor signal line that is connected to the optical sensor and transmits the detection signal to the driver IC. One piece of first wiring led out from one terminal of the driver IC is connected to four switching elements. Three switching elements out of the four switching elements are electrically connected to the first, second and third signal lines, respectively. One switching element other than the three switching elements out of the four switching elements is electrically connected to the sensor signal line.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a liquid crystal display device with an optical sensor. [Background technology]

[0002] In recent years, liquid crystal display devices (biometric authentication devices) have been developed that incorporate sensors for detecting biometric information, such as fingerprint sensors and vein sensors. For example, optical sensors using photoelectric conversion elements are used as this type of sensor. Optical sensors detect light emitted from a light source, such as a backlight, and reflected by an object, thereby detecting the biometric information of the object.

[0003] Just as there is a demand for narrower picture frames in general liquid crystal display devices, there is also a demand for narrower picture frames in such liquid crystal display devices with optical sensors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2020 / 0265207 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a liquid crystal display device with an optical sensor that can achieve a narrow frame. [Means for solving the problem]

[0006] A liquid crystal display device with an optical sensor according to one embodiment includes a display panel including a first substrate, a second substrate facing the first substrate, and a liquid crystal layer located between the first and second substrates; and a driver IC. The display panel includes a first signal line for supplying a video signal to a first subpixel corresponding to red, a second signal line for supplying a video signal to a second subpixel corresponding to green, and a third signal line for supplying a video signal to a third subpixel corresponding to blue; an optical sensor including a photoelectric conversion element for outputting a detection signal in response to light incident from the liquid crystal layer; and a sensor signal line connected to the optical sensor and transmitting the detection signal to the driver IC. One first wiring extending from one terminal of the driver IC is connected to four switching elements. Three of the four switching elements are electrically connected to one of the first signal line, the second signal line, and the third signal line. One of the four switching elements other than the three switching elements is electrically connected to the sensor signal line. Of the four switching elements, two switching elements electrically connected to the first signal line and the third signal line share one semiconductor layer. Of the four switching elements, two switching elements electrically connected to the second signal line and the sensor signal line do not share a semiconductor layer with other switching elements. The two switching elements electrically connected to the first signal line and the third signal line are disposed between the two switching elements electrically connected to the second signal line and the sensor signal line. Each of the semiconductor layers constituting the four switching elements has a convex portion and a concave portion in a first direction. Of two semiconductor layers adjacent in the first direction, the convex portion of one semiconductor layer faces the concave portion of the other semiconductor layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram schematically illustrating a display device according to an embodiment. [Figure 2] FIG. 2 is a plan view schematically showing the display device according to the embodiment. [Figure 3] FIG. 3 is a plan view showing a configuration example of a touch sensor mounted on the display device according to the embodiment. [Figure 4] FIG. 4 is an equivalent circuit diagram showing the optical sensor according to the embodiment and a sensor circuit connected to the optical sensor. [Figure 5] FIG. 5 is a diagram for explaining an example of the operation of the optical sensor according to the embodiment and a sensor circuit connected to the optical sensor. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an example of a structure that can be applied to the first substrate according to the same embodiment. [Figure 7]FIG. 7 is a schematic plan view showing an example of a structure that can be applied to the first substrate according to the same embodiment. [Figure 8] FIG. 8 is a schematic plan view showing an example of a structure that can be applied to the first substrate according to the same embodiment. [Figure 9] FIG. 9 is a schematic plan view showing an example of a structure that can be applied to the first substrate according to the same embodiment. [Figure 10] FIG. 10 is a schematic plan view showing an example of a structure that can be applied to the first substrate according to the same embodiment. [Figure 11] FIG. 11 is a diagram showing an example of a circuit configuration of a signal line / sensor signal line selection circuit according to the embodiment. [Figure 12] FIG. 12 is a plan view showing a schematic configuration example of the switching element shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a schematic configuration example of a portion where the second wiring shown in FIG. 12 is electrically connected to the sensor signal line. [Figure 14] FIG. 14 is a plan view showing a schematic configuration example of a portion where the second wiring shown in FIG. 12 is electrically connected to the sensor signal line. [Figure 15] FIG. 15 is a plan view schematically showing a display device according to a comparative example. [Figure 16] FIG. 16 is a circuit diagram showing the signal line selection circuit, the sensor signal line selection circuit, and the sensor line group shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be more schematic than the embodiments to clarify the description, but they are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted.

[0009] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction or first direction, the direction along the Y-axis is referred to as the Y-direction or second direction, and the direction along the Z-axis is referred to as the Z-direction, third direction, or thickness direction. The plane defined by the X-axis and Y-axis is referred to as the XY plane, and the plane defined by the X-axis and Z-axis is referred to as the XZ plane. Viewing the XY plane is referred to as planar view.

[0010] 1 is a diagram schematically illustrating a display device DSP according to an embodiment. The display device DSP is a liquid crystal display device with an optical sensor, and may also be referred to as a biometric authentication device. The display device DSP includes a display panel PNL, a cover member CM, a first polarizer PLZ1, a second polarizer PLZ2, and an illumination device IL.

[0011] The display panel PNL is a liquid crystal display panel and includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1, a sealant SE, and a liquid crystal layer LC. The liquid crystal layer LC is sealed between the first substrate SUB1 and the second substrate SUB2 by the sealant SE. The display panel PNL of this embodiment is a transmissive display panel that displays images by selectively transmitting light from the back side of the first substrate SUB1 to the upper surface side of the second substrate SUB2.

[0012] The first substrate SUB1 includes an optical sensor OS and a collimating layer CL. The optical sensor OS is located between the collimating layer CL and a main surface of the first substrate SUB1 that faces the second polarizing plate PLZ2. The collimating layer CL has an opening OP that overlaps with the optical sensor OS. The collimating layer CL is formed of, for example, a metal material and has light-blocking properties. Such a collimating layer CL may be disposed not only on the first substrate SUB1 but also on the second substrate SUB2.

[0013] The seal material SE bonds the first substrate SUB1 and the second substrate SUB2 together. A predetermined cell gap is formed between the first substrate SUB1 and the second substrate SUB2 by a spacer (not shown). The liquid crystal layer LC is filled in this cell gap.

[0014] The cover member CM is provided on the display panel PNL. For example, a glass substrate or a resin substrate can be used as the cover member CM. The cover member CM has an upper surface USF with which an object to be detected by the optical sensor OS comes into contact. In this embodiment, it is assumed that the upper surface USF of the cover member CM is parallel to the upper surface of the optical sensor OS. In the example of FIG. 1, a finger Fg, which is an example of an object, is in contact with the upper surface USF. The first polarizer PLZ1 is provided between the display panel PNL and the cover member CM.

[0015] The illumination device IL is provided below the display panel PNL and irradiates the first substrate SUB1 with light L. The illumination device IL is, for example, a side-edge type backlight and includes a plate-shaped light guide and multiple light sources that emit light to the side surfaces of the light guide. The second polarizer PLZ2 is provided between the display panel PNL and the illumination device IL.

[0016] The light L reflected by the finger Fg passes through an opening OP formed in the collimating layer CL and enters the optical sensor OS. That is, the light reflected by the finger Fg passes through the cover member CM, the first polarizing plate PLZ1, the second substrate SUB2, the liquid crystal layer LC, and even the portion of the first substrate SUB1 that is located above the optical sensor OS before entering the optical sensor OS.

[0017] The optical sensor OS outputs a detection signal corresponding to the incident light. As will be described later, the display panel PNL is equipped with a plurality of optical sensors OS, and based on the detection signals output by these optical sensors OS, the unevenness of the finger Fg, i.e., the fingerprint, can be detected.

[0018] In order to obtain a more accurate detection signal, it is desirable for the optical sensor OS to receive incident light parallel to the normal direction of the upper surface USF. The collimating layer CL functions as a collimator that collimates the light incident on the optical sensor OS. In other words, the collimating layer CL blocks light that is inclined with respect to the normal direction of the upper surface USF (in other words, light that is inclined with respect to the normal direction of the upper surface of the optical sensor OS).

[0019] As described above, by incorporating the optical sensor OS into the display device DSP, the display device DSP can be given the function of a fingerprint sensor. Furthermore, the optical sensor OS can be used to detect information about a living body, in addition to or instead of detecting a fingerprint. Information about a living body, such as an image of blood vessels such as veins, pulse rate, pulse waves, etc., is detected based on light reflected inside the finger Fg.

[0020] 2 is a plan view schematically showing a display device DSP according to this embodiment. The display device DSP includes the above-described display panel PNL, a first flexible printed circuit board 1, and a second flexible printed circuit board 2. The display panel PNL has a display area DA for displaying an image and a peripheral area PA surrounding the display area DA.

[0021] The first substrate SUB1 has a mounting area MA that does not overlap with the second substrate SUB2. The mounting area MA is provided with a terminal section 3 for mounting the first flexible printed circuit board 1 and a signal line / sensor signal line selection circuit 4. The sealant SE is located in the peripheral area PA. In FIG. 2, the area where the sealant SE is located is indicated by diagonal lines. The display area DA is located inside the sealant SE. The display panel PNL has a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y in the display area DA.

[0022] The pixel PX includes a subpixel SP1 that emits red (R) light, a subpixel SP2 that emits green (G) light, and a subpixel SP3 that emits blue (B) light. Note that the pixel PX may include subpixels that emit light of colors other than red, green, and blue.

[0023] 2, one optical sensor OS is provided for each pixel PX. More specifically, one optical sensor OS is provided for each subpixel SP3 that emits blue light and is included in each pixel PX. In the entire display area DA, the multiple optical sensors OS are arranged in a matrix in the first direction X and the second direction Y.

[0024] The optical sensor OS does not necessarily have to be arranged for every pixel PX. For example, the optical sensor OS may be arranged at a ratio of one for every multiple pixels PX. Furthermore, the optical sensor OS may be arranged for pixels PX in a portion of the display area DA, and not for pixels PX in other portions.

[0025] The first flexible printed circuit board 1 is connected to a terminal section 3 provided in the mounting area MA. One driver IC 5 is provided on the first flexible printed circuit board 1. The driver IC 5 is arranged so that the center of the driver IC 5 is aligned with the center of the display panel PNL. The driver IC 5 includes a function corresponding to a display mode for displaying images, a function corresponding to a touch sensing mode for detecting the approach or contact of an object, and a function corresponding to a detection operation by the optical sensor OS (a function corresponding to a detection mode for detecting biological information). The driver IC 5 is mounted on the first flexible printed circuit board 1 by COF (Chip On Film) using, for example, ACF.

[0026] A controller CT is provided on the second flexible printed circuit board 2. Detection signals output by the optical sensors OS are output to the controller CT via a signal line / sensor signal line selection circuit 4 and a driver IC 5. The controller CT executes arithmetic processing and the like for detecting fingerprints based on the detection signals from the multiple optical sensors OS. Note that the arithmetic processing and the like for detecting fingerprints may also be executed by the driver IC 5.

[0027] FIG. 3 is a plan view showing an example of the configuration of the touch sensor TS. Here, a self-capacitance touch sensor TS is described, but the touch sensor TS may also be a mutual capacitance touch sensor. The touch sensor TS includes a plurality of sensor electrodes Rx and a plurality of touch detection lines TL. The plurality of sensor electrodes Rx are located in a display area DA and are arranged in a matrix in a first direction X and a second direction Y. One sensor electrode Rx overlaps with a plurality of pixels PX shown in FIG. 2 in a plan view to form one sensor block B. The sensor block B is the smallest unit capable of touch sensing. The plurality of touch detection lines TL extend in the second direction Y in the display area DA and are aligned in the first direction X. Each of the touch detection lines TL is arranged at a position overlapping a signal line SL, which will be described later. Each of the touch detection lines TL is electrically connected to a corresponding sensor electrode Rx. Each of the touch detection lines TL is also drawn to the peripheral area PA and electrically connected to a driver IC 5 via a first flexible printed circuit board 1.

[0028] In touch sensing mode, a touch drive voltage is applied to the sensor electrode Rx, and sensing is performed at the sensor electrode Rx. A sensor signal corresponding to the sensing result at the sensor electrode Rx is output to the driver IC5 via the touch detection line TL. Based on the sensor signal, the driver IC5 or the controller CT detects whether an object is approaching or touching, and the position coordinates of the object that is approaching or touching.

[0029] In the display mode, a common voltage (Vcom) is applied to the sensor electrode Rx, and the sensor electrode Rx functions as a common electrode CE (described later). The common voltage is supplied via, for example, a power supply line PL (described later).

[0030] FIG. 4 is an equivalent circuit diagram showing the optical sensor OS according to this embodiment and a sensor circuit connected to the optical sensor OS. As shown in FIG. 4, the sensor circuit includes a first sensor scanning line SGL1, a second sensor scanning line SGL2, a first sensor power supply line SPL1, a second sensor power supply line SPL2, a third sensor power supply line SPL3, a sensor signal line SSL, a switching element SW2A, a switching element SW2B, a switching element SW2C, a capacitor C1, and a capacitor C2.

[0031] In the following description, the first sensor scanning line SGL1 will be referred to as the first scanning line SGL1, the second sensor scanning line SGL2 will be referred to as the second scanning line SGL2, the first sensor power supply line SPL1 will be referred to as the first power supply line SPL1, the second sensor power supply line SPL2 will be referred to as the second power supply line SPL2, and the third sensor power supply line SPL3 will be referred to as the third power supply line SPL3.

[0032] Although FIG. 4 shows a case where the switching elements SW2A, SW2B, and SW2C are each configured with an n-type TFT (Thin Film Transistor), the switching elements SW2A, SW2B, and SW2C may also be configured with a p-type TFT.

[0033] One electrode of the optical sensor OS is connected to a second power supply line SPL2, and the other electrode is connected to a node N1. The node N1 is connected to the drain electrode of the switching element SW2A and the gate electrode of the switching element SW2B. A second voltage Vcom_FPS is supplied to one electrode of the optical sensor OS through the second power supply line SPL2. The second voltage Vcom_FPS may also be referred to as a sensor reference voltage. When light is incident on the optical sensor OS, a signal (charge) corresponding to the amount of incident light is output from the optical sensor OS and accumulated in the capacitor C1. Note that the capacitance held in the capacitor C2 is a parasitic capacitance added to the capacitance held in the capacitor C1.

[0034] The switching element SW2A has a gate electrode connected to the first scan line SGL1, a source electrode connected to the first power supply line SPL1, and a drain electrode connected to a node N1. When the switching element SW2A is turned on in response to a scan signal supplied from the first scan line SGL1, the potential of the node N1 (i.e., the potential of the other electrode of the optical sensor OS) is reset to a first potential VPP1 by a first voltage VPP1 supplied through the first power supply line SPL1. The first voltage VPP1 may also be referred to as a reset voltage. The switching element SW2A may also be referred to as a reset transistor. The second voltage Vcom_FPS indicates a value lower than the first voltage VPP1, and the optical sensor OS is reverse-biased.

[0035] The switching element SW2B has a gate electrode connected to the node N1, a source electrode connected to a third power supply line SPL3 that supplies a third voltage VPP2, and a drain electrode connected to the source electrode of the switching element SW2C. A signal output from the optical sensor OS is supplied to the gate electrode of the switching element SW2B. The switching element SW2B outputs a voltage signal corresponding to the signal output from the optical sensor OS (a voltage signal obtained by amplifying the signal output from the optical sensor OS) to the switching element SW2C. The switching element SW2B may be referred to as a source follower transistor.

[0036] The switching element SW2C has a gate electrode connected to the second scan line SGL2, a source electrode connected to the drain electrode of the switching element SW2B, and a drain electrode connected to the sensor signal line SSL. When the switching element SW2C is turned on in response to a scan signal supplied from the second scan line SGL2, a voltage signal output from the switching element SW2B is output to the sensor signal line SSL as the detection signal Vdet. The switching element SW2C may also be referred to as a read transistor.

[0037] Although FIG. 4 shows a case where the switching elements SW2A and SW2C have a double gate structure, the switching elements SW2A and SW2C may have a single gate structure or a multi-gate structure.

[0038] 5 is a diagram for explaining an example of the operation of the optical sensor OS according to this embodiment and a sensor circuit connected to the optical sensor OS. The optical sensor OS captures an image of a fingerprint (detection operation) during a fingerprint imaging period P1 shown in FIG. 5. As shown in FIG. 5, the fingerprint imaging period P1 includes a reset period P11, an exposure period P12, and a read period P13. Although not shown here, a second voltage Vcom_FPS is supplied to one electrode of the optical sensor OS throughout the reset period P11, the exposure period P12, and the read period P13.

[0039] The reset period P11 is a period during which the potential of the node N1 is reset. The reset period P11 begins at time t0, and when the switching element SW2A is turned on in response to the scanning signal supplied from the first scanning line SGL1, the potential of the node N1 is reset to VPP1 by the first voltage VPP1 supplied through the first power supply line SPL1. At time t1, when the switching element SW2C is turned on in response to the scanning signal supplied from the second scanning line SGL2, the detection signal Vdet1 is output to the sensor signal line SSL. The potential of the detection signal Vdet1 is VPP1-Vth-Vsw2c, where Vth is the threshold voltage of the switching element SW2B, which is a source follower transistor, and Vsw2c is a voltage drop caused by the on-resistance of the switching element SW2C.

[0040] At time t2, when the reset period P11 ends and the exposure period P12 begins, the switching element SW2A turns off. When the exposure period P12 begins, the potential of the node N1 gradually decreases to VPP1-ΔVos in accordance with the amount of light incident on the optical sensor OS (light reflected by the finger). ΔVos is the voltage drop that occurs when light is incident on the optical sensor OS. At time t3 during the exposure period P12, the switching element SW2C turns off.

[0041] At time t4, the exposure period P12 ends and the read period P13 begins. The switching element SW2C turns on in response to the scanning signal supplied from the second scanning line SGL2, and the detection signal Vdet2 is output to the sensor signal line SSL. The potential of the detection signal Vdet2 becomes VPP1-Vth-Vsw2c-ΔVos. In other words, the potential of the detection signal Vdet2 is lower than the potential of the detection signal Vdet1 by ΔVos. The read period P13 ends at time t5.

[0042] The controller CT (or driver IC5) compares the potential of the detection signal Vdet1 with the potential of the detection signal Vdet2, and can detect light incident on the optical sensor OS based on the difference (i.e., ΔVos). Note that while Figure 5 shows an example of the operation of one optical sensor OS and one sensor circuit, all optical sensors OS and all sensor circuits can operate in the same way. The controller CT (or driver IC5) can detect the unevenness of a finger (fingerprint), blood vessel image (vein pattern), etc. by analyzing the in-plane distribution of the above-mentioned differences obtained from all the optical sensors OS.

[0043] 6 is a cross-sectional view showing a schematic configuration example of the first substrate SUB1. The first substrate SUB1 includes a transparent first base material 10, insulating layers 11, 12, 13, 14, 15, 16, and 17, and an alignment film AL.

[0044] The first base material 10 is, for example, a glass substrate or a resin substrate. The insulating layers 11, 12, 14, and 17 are made of an inorganic material. The insulating layers 13, 15, and 16 are made of an organic material. The insulating layers 11, 12, 13, 14, 15, 16, and 17 and the alignment film AL are stacked in this order in the third direction Z above the first base material 10.

[0045] The first substrate SUB1 includes, as elements related to image display, signal lines SL, scanning lines GL, switching elements SW1, pixel electrodes PE, common electrodes CE, relay electrodes R1, R2, R3, R4, and R5, and power supply lines PL. The pixel electrodes PE and switching elements SW1 are provided for the subpixels SP1, SP2, and SP3, respectively. The common electrode CE is provided across, for example, multiple pixels PX.

[0046] The switching element SW1 includes a semiconductor layer SC1. The semiconductor layer SC1 is disposed between the first base material 10 and the insulating layer 11. The scanning line GL is disposed between the insulating layers 11 and 12 and faces the semiconductor layer SC1. The scanning line GL may be disposed on a different layer instead of between the insulating layers 11 and 12. The signal line SL is disposed between the insulating layers 12 and 13 and contacts the semiconductor layer SC1 through a contact hole CH1 that penetrates the insulating layers 11 and 12.

[0047] The relay electrode R1 is disposed between the insulating layers 12 and 13, i.e., in the same layer as the signal line SL, and is in contact with the semiconductor layer SC1 through a contact hole CH2 that penetrates the insulating layers 11 and 12. The relay electrode R2 is disposed between the insulating layers 13 and 14, and is in contact with the relay electrode R1 through a contact hole CH3 that penetrates the insulating layer 13. The relay electrode R3 is disposed between the insulating layers 14 and 15, and is in contact with the relay electrode R2 through a contact hole CH4 that penetrates the insulating layer 14. The relay electrode R4 is disposed between the insulating layers 15 and 16, and is in contact with the relay electrode R3 through a contact hole CH5 that penetrates the insulating layer 15. The relay electrode R5 is disposed between the insulating layers 16 and 17, and is in contact with the relay electrode R4 through a contact hole CH6 that penetrates the insulating layer 16.

[0048] The pixel electrode PE is disposed between the insulating layer 17 and the alignment film AL, and is in contact with the relay electrode R5 through a contact hole CH7 that penetrates the insulating layer 17. The power supply line PL is disposed between the insulating layers 15 and 16, that is, in the same layer as the relay electrode R4. The common electrode CE is disposed between the insulating layers 16 and 17, that is, in the same layer as the relay electrode R5, and is in contact with the power supply line PL through a contact hole CH8 that penetrates the insulating layer 16.

[0049] A common voltage Vcom is supplied to the power supply line PL. The common voltage Vcom is supplied to the common electrode CE. A video signal is supplied to the signal line SL, and a scanning signal is supplied to the scanning line GL. When the scanning signal is supplied to the scanning line GL, the video signal on the signal line SL is supplied to the pixel electrode PE through the semiconductor layer SC1 and relay electrodes R1, R2, R3, R4, and R5. At this time, an electric field is generated between the pixel electrode PE and the common electrode CE due to the potential difference between the potential of the pixel electrode PE, which corresponds to the video signal, and the potential Vcom of the common electrode CE, and this electric field acts on the liquid crystal layer LC.

[0050] The first substrate SUB1 includes a switching element SW2, a sensor scanning line SGL, relay electrodes R6, R7, R8, and R9, a second power supply line SPL2, and a third power supply line SPL3 (collimating layer CL) as elements related to the optical sensor OS. The optical sensor OS also includes a first electrode E1 (lower electrode), a second electrode E2 (upper electrode), and a photoelectric conversion element PC.

[0051] For ease of explanation, in FIG. 6, elements related to the multiple switching elements SW2A, SW2B, and SW2C associated with the optical sensor OS are represented as switching element SW2. Also, in FIG. 6, the element functioning as the gate electrode of the switching element SW2 is represented as the sensor scan line SGL. Also, in FIG. 6, the element functioning as the source electrode of the switching element SW2 is represented as the relay electrode R7. Also, in FIG. 6, the element functioning as the drain electrode of the switching element SW2 is represented as the relay electrode R6. Furthermore, in FIG. 6, only some, but not all, of the elements associated with the optical sensor OS are shown.

[0052] The photoelectric conversion element PC has a first surface F1 facing the first substrate 10 and a second surface F2 facing the liquid crystal layer LC. The second surface F2 of the photoelectric conversion element PC corresponds to the upper surface of the optical sensor OS. The photoelectric conversion element PC is located between the insulating layers 13 and 14. The first electrode E1 is disposed between the photoelectric conversion element PC and the insulating layer 13 and is in contact with the first surface F1. The outer periphery of the first electrode E1 protrudes from the photoelectric conversion element PC and is covered by the insulating layer 14. The first electrode E1 is in contact with the relay electrode R6 through a contact hole CH9 that penetrates the insulating layer 13 below the photoelectric conversion element PC. The second electrode E2 is disposed between the photoelectric conversion element PC and the insulating layer 14 and is in contact with the second surface F2. The second electrode E2 is in contact with the second power supply line SPL2 through a contact hole CH10 that penetrates the insulating layer 14 above the photoelectric conversion element PC.

[0053] The second power supply line SPL2 is disposed between the insulating layers 14 and 15, and is in contact with the second electrode E2 through a contact hole CH10 that penetrates the insulating layer 14. A second voltage Vcom_FPS is supplied to the second power supply line SPL2, and the second voltage Vcom_FPS is supplied to the second electrode E2 through the second power supply line SPL2.

[0054] The switching element SW2 includes a semiconductor layer SC2. The semiconductor layer SC2 is disposed between the first base material 10 and the insulating layer 11. The sensor scanning line SGL is disposed between the insulating layers 11 and 12 and faces the semiconductor layer SC2. The sensor scanning line SGL may be disposed in a different layer instead of between the insulating layers 11 and 12.

[0055] The relay electrode R6 is disposed between the insulating layers 12 and 13 and is in contact with the semiconductor layer SC2 through a contact hole CH11 that penetrates the insulating layers 11 and 12. The relay electrode R7 is disposed between the insulating layers 12 and 13, i.e., in the same layer as the relay electrode R6, and is in contact with the semiconductor layer SC2 through a contact hole CH12 that penetrates the insulating layers 11 and 12. The relay electrode R8 is disposed between the insulating layers 13 and 14, i.e., in the same layer as the first electrode E1, and is in contact with the relay electrode R7 through a contact hole CH13 that penetrates the insulating layer 13. The relay electrode R9 is disposed between the insulating layers 14 and 15, i.e., in the same layer as the second power supply line SPL2, and is in contact with the relay electrode R8 through a contact hole CH14 that penetrates the insulating layer 14.

[0056] The third power supply line SPL3 is disposed between the insulating layers 15 and 16, i.e., in the same layer as the power supply line PL, and is in contact with the relay electrode R9 through a contact hole CH15 that penetrates the insulating layer 15. A third voltage VPP2 is supplied to the third power supply line SPL3. In addition to supplying the third voltage VPP2, the third power supply line SPL3 also functions as a collimating layer CL. In other words, a portion of the third power supply line SPL3 serves as the collimating layer CL, and the third power supply line SPL3 has an opening OP at a position overlapping the second surface F2 of the photoelectric conversion element PC.

[0057] The signal line SL and relay electrodes R1, R6, and R7 are formed of the same metal material. The first electrode E1 and relay electrodes R2 and R8 are formed of the same metal material. The second power supply line SPL2 and relay electrodes R3 and R9 are formed of the same metal material. The power supply line PL, the third power supply line SPL3 (collimating layer CL), and relay electrode R4 are formed of the same metal material. The second electrode E2, pixel electrode PE, common electrode CE, and relay electrode R5 are formed of a transparent conductive material such as ITO (Indium Tin Oxide).

[0058] The first electrode E1, made of a metal material, also functions as a light-shielding layer, preventing light from entering the photoelectric conversion element PC from below. The photoelectric conversion element PC is, for example, a photodiode, and outputs a detection signal Vdet corresponding to the incident light. A PIN (Positive Intrinsic Negative) photodiode can be used as the photoelectric conversion element PC. This type of photodiode has a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer. The p-type semiconductor layer is located on the second electrode E2 side, the n-type semiconductor layer is located on the first electrode E1 side, and the i-type semiconductor layer is located between the p-type semiconductor layer and the n-type semiconductor layer.

[0059] The p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are formed of, for example, amorphous silicon (a-Si). Note that the material of the semiconductor layers is not limited to this, and amorphous silicon may be replaced with polycrystalline silicon, microcrystalline silicon, etc., and polycrystalline silicon may be replaced with amorphous silicon, microcrystalline silicon, etc. Moreover, instead of the PIN photodiode, an OPD (Organic Photodiode) may be used.

[0060] A scanning signal is supplied to the sensor scanning line SGL at the timing when detection by the sensor OS should be performed. When the scanning signal is supplied to the sensor scanning line SGL, a detection signal Vdet generated by the photoelectric conversion element PC is output to a sensor signal line SSL, which is not shown in Fig. 6. The detection signal Vdet output to the sensor signal line SSL is output to the driver IC 5.

[0061] Fig. 7 is a plan view schematically showing elements applicable to the first substrate SUB1, which are arranged between the first base material 10 and the insulating layer 13 shown in Fig. 6. In Fig. 7, the reference numerals of elements related to the switching element SW2A are suffixed with "A," the reference numerals of elements related to the switching element SW2B are suffixed with "B," and the reference numerals of elements related to the switching element SW2C are suffixed with "C."

[0062] The scanning line GL, the first scanning line SGL1, and the second scanning line SGL2 each extend along the first direction X and are aligned along the second direction Y. The first scanning line SGL1 and the second scanning line SGL2 are aligned adjacent to each other in the second direction Y. The first scanning line SGL1 and the second scanning line SGL2 are disposed between two adjacent scanning lines GL.

[0063] The signal line SLR corresponding to the red subpixel SP1, the signal line SLG corresponding to the green subpixel SP2, and the signal line SLB corresponding to the blue subpixel SP3 are curved and extend along the second direction Y, and are aligned along the first direction X.

[0064] The sub-pixels SP1, SP2, and SP3 are arranged in a region surrounded by two adjacent scanning lines GL aligned in the second direction Y and two adjacent signal lines SL aligned in the first direction X. Each of the sub-pixels SP1, SP2, and SP3 has an opening surrounded by the second scanning line SGL2, the first scanning line SGL1, and the two adjacent signal lines SL.

[0065] The first scan line SGL1 has a branched portion (convex portion) extending in the second direction Y. This branched portion functions as the gate electrode of the switching element SW2A. A semiconductor layer SC2A is arranged in a region overlapping with the gate electrode of the switching element SW2A in plan view.

[0066] The semiconductor layer SC2A is disposed across the aperture of the subpixel SP3 and the aperture of the subpixel SP1, and a portion of the semiconductor layer SC2A overlaps with the signal line SLB corresponding to the subpixel SP3. An island-shaped relay electrode R7A, which functions as the source electrode of the switching element SW2A, is disposed in the aperture of the subpixel SP1 at a position overlapping with the semiconductor layer SC2A. The relay electrode R7A is in contact with the semiconductor layer SC2A through a contact hole CH12A. An island-shaped relay electrode R6A, which functions as the drain electrode of the switching element SW2A, is disposed in the aperture of the subpixel SP3 at a position overlapping with the semiconductor layer SC2A. The relay electrode R6A is in contact with the semiconductor layer SC2A through a contact hole CH11A.

[0067] The relay electrode R6A is in contact with the first gate electrode GE1, which functions as the gate electrode of the switching element SW2B, through a contact hole CH21A. The contact hole CH21 is a through-hole that penetrates the insulating layer 12, and brings into contact elements located on the same layer as the relay electrodes R6 and R7 with elements located on the same layer as the first scanning line SGL1 and the second scanning line SGL2.

[0068] The first gate electrode GE1 is disposed across the aperture of the subpixel SP3 and the aperture of the subpixel SP2, and a part of the first gate electrode GE1 overlaps with the signal line SLG corresponding to the subpixel SP2. In the aperture of the subpixel SP2, a semiconductor layer SC2B is disposed in a region that overlaps with the first gate electrode GE1 in a plan view.

[0069] An island-shaped relay electrode R7B, which functions as the source electrode of the switching element SW2B, is arranged at a position overlapping with the semiconductor layer SC2B. The relay electrode R7B is in contact with the semiconductor layer SC2B through a contact hole CH12B. An island-shaped relay electrode R6B, which functions as the drain electrode of the switching element SW2B, is arranged at a position overlapping with the semiconductor layer SC2B. The relay electrode R6B is in contact with the semiconductor layer SC2B through a contact hole CH11B.

[0070] The relay electrode R6B is in contact with the second gate electrode GE2 through a contact hole CH21B. The second gate electrode GE2 is disposed across the opening of the subpixel SP2 and the opening of the subpixel SP3, and a part of the second gate electrode GE2 overlaps with the signal line SLG corresponding to the subpixel SP2. The switching element SW2B and the switching element SW2C are connected by the second gate electrode GE2.

[0071] The second scan line SGL2 has a branched portion (protruding portion) extending in the second direction Y. This branched portion functions as the gate electrode of the switching element SW2C. A semiconductor layer SC2C is arranged in a region overlapping with the gate electrode of the switching element SW2C in a plan view.

[0072] The semiconductor layer SC2C is disposed across the aperture of the subpixel SP3 and the aperture of the subpixel SP1, and a portion of the semiconductor layer SC2C overlaps with the signal line SLB corresponding to the subpixel SP3. An island-shaped relay electrode R7C that functions as the source electrode of the switching element SW2C is disposed in the aperture of the subpixel SP3 at a position overlapping with the semiconductor layer SC2C. The relay electrode R7C is in contact with the semiconductor layer SC2C through a contact hole CH12C. The relay electrode R7C is also in contact with the second gate electrode GE2 through a contact hole CH21C.

[0073] An island-shaped relay electrode R6C that functions as the drain electrode of the switching element SW2C is disposed in the opening of the subpixel SP1 at a position overlapping with the semiconductor layer SC2C. The relay electrode R6C is in contact with the semiconductor layer SC2C through a contact hole CH11C.

[0074] In addition, a switching element SW1 is disposed in the opening between the first scanning line SGL1 and the scanning line GL as an element related to image display. The semiconductor layer SC1 included in the switching element SW1 is in contact with the signal line SL of the corresponding color through a contact hole CH1. The semiconductor layer SC1 included in the switching element SW1 is also in contact with the relay electrode R1 through a contact hole CH2.

[0075] Fig. 8 is a plan view schematically showing elements applicable to the first substrate SUB1, which are arranged between the insulating layers 13 and 14 shown in Fig. 6. In Fig. 8, in order to make the positional relationship easier to understand, the scanning lines GL, signal lines SL (SLR, SLG, SLB), first scanning lines SGL1, and second scanning lines SGL2 shown in Fig. 7 are also shown in a partially simplified form.

[0076] An island-shaped relay electrode R8A is disposed in the opening of the subpixel SP1. The relay electrode R8A is in contact with the underlying relay electrode R7A through a contact hole CH13A.

[0077] Furthermore, an island-shaped relay electrode R11 is disposed in the opening of the subpixel SP1. The relay electrode R11 is disposed between the insulating layers 13 and 14, i.e., in the same layer as the relay electrode R8 and the first electrode E1, and is in contact with the underlying relay electrode R6C through a contact hole CH22. The contact hole CH22 is a through-hole that penetrates the insulating layer 13 and brings the relay electrode R11 and the relay electrode R6C into contact with each other.

[0078] An island-shaped relay electrode R8B is disposed in the opening of the subpixel SP2. The relay electrode R8B is in contact with the underlying relay electrode R7B through a contact hole CH13B.

[0079] A first electrode E1 of the optical sensor OS is disposed in the opening of the subpixel SP3. The first electrode E1 is in contact with the underlying relay electrode R6A through a contact hole CH9.

[0080] In the opening between the first scanning line SGL1 and the scanning line GL, island-shaped relay electrodes R2 corresponding to the signal lines SLR, SLG, and SLB are arranged as elements related to image display. The relay electrodes R2 are in contact with the underlying relay electrodes R1 through contact holes CH3.

[0081] Fig. 9 is a plan view schematically showing elements applicable to the first substrate SUB1, which are arranged between the insulating layers 14 and 15 shown in Fig. 6. In Fig. 9 as well, the scanning line GL, the first scanning line SGL1, and the second scanning line SGL2 shown in Fig. 7 are shown in a partially simplified form to make the positional relationship easier to understand.

[0082] The first power supply line SPL1, the second power supply line SPL2, and the sensor signal line SSL are bent and extend in the second direction Y, and are aligned in the first direction X. The first power supply line SPL1 overlaps the signal line SLR corresponding to the red subpixel SP1 in a planar view. The second power supply line SPL2 overlaps the signal line SLG corresponding to the green subpixel SP2 in a planar view. The sensor signal line SSL overlaps the signal line SLB corresponding to the blue subpixel SP3 in a planar view.

[0083] The sensor signal line SSL has a branch portion (protrusion) SSL1 extending in the first direction X toward the opening of the subpixel SP1, and this branch portion SSL1 is in contact with the underlying relay electrode R11 through a contact hole CH23. The contact hole CH23 is a through-hole that penetrates the insulating layer 14 and brings the branch portion SSL1 and the relay electrode R11 into contact. This electrically connects the sensor signal line SSL and the switching element SW2C, allowing the detection signal Vdet to be output to the sensor signal line SSL.

[0084] The first power supply line SPL1 has a branch (protrusion) SPL11 extending in the first direction X toward the opening of the subpixel SP1, and this branch SPL11 is in contact with the underlying relay electrode R8A through the contact hole CH14A, thereby electrically connecting the first power supply line SPL1 and the switching element SW2A, and enabling the first voltage VPP1 to be supplied to the switching element SW2A.

[0085] An island-shaped relay electrode R9B is arranged in the opening of the subpixel SP2. The relay electrode R9B is arranged between the insulating layers 14 and 15, that is, in the same layer as the first power supply line SPL1, the second power supply line SPL2, and the sensor signal line SSL, and is in contact with the underlying relay electrode R8B through a contact hole CH14B.

[0086] A photoelectric conversion element PC is disposed on the first electrode E1 located in the aperture of the subpixel SP3. A second electrode E2 of the optical sensor OS is disposed on the photoelectric conversion element PC. The optical sensor OS has an oval shape with a major axis extending parallel to the second power supply line SPL2 and a minor axis perpendicular to the major axis. Therefore, the photoelectric conversion element PC, the first electrode E1, and the second electrode E2 are formed in an oval shape with a major axis extending parallel to the second power supply line SPL2 and a minor axis perpendicular to the major axis.

[0087] The second power supply line SPL2 has a branch (protrusion) SPL21 extending in the first direction X toward the opening of the subpixel SP3, and this branch SPL21 is in contact with the second electrode E2 of the optical sensor OS through the contact hole CH10. This electrically connects the second power supply line SPL2 and the optical sensor OS, and enables the second voltage Vcom_FPS to be supplied to the optical sensor OS.

[0088] In the opening between the first scanning line SGL1 and the scanning line GL, island-shaped relay electrodes R3 corresponding to the signal lines SLR, SLG, and SLB are arranged as elements related to image display. The relay electrodes R3 are in contact with the underlying relay electrodes R2 through contact holes CH4.

[0089] Fig. 10 is a plan view schematically showing elements applicable to the first substrate SUB1, which are arranged between the insulating layers 15 and 16 shown in Fig. 6. In Fig. 10, the scanning line GL, the first scanning line SGL1, and the second scanning line SGL2 shown in Fig. 7 are shown in a partially simplified form to make the positional relationship easier to understand.

[0090] The touch detection lines TL1 and TL2 and the third power supply line SPL3 extend in the second direction Y while bending, and are aligned in the first direction X. The touch detection line TL1 overlaps with the signal line SLB and the sensor signal line SSL corresponding to the blue subpixel SP3 in a planar view. The touch detection line TL2 overlaps with the signal line SLR and the first power supply line SPL1 corresponding to the red subpixel SP1 in a planar view. The third power supply line SPL3 overlaps with the signal line SLG and the second power supply line SPL2 corresponding to the green subpixel SP2 in a planar view.

[0091] The third power supply line SPL3 has an oval first branch portion SPL31 that overlaps with the outer periphery of the photoelectric conversion element PC in the opening of the subpixel SP3. The size of the first branch portion SPL31 is larger than the size of the photoelectric conversion element PC. The first branch portion SPL31 corresponds to the collimating layer CL, and the collimating layer CL has a circular opening OP. The collimating layer CL (first branch portion SPL31) transmits light from the liquid crystal layer LC side through the opening OP and blocks light from the liquid crystal layer LC side in other parts.

[0092] In addition to the oval collimating layer CL, the third power supply line SPL3 has a second branch portion (protrusion) SPL32 extending in the first direction X toward the opening of the subpixel SP2. The second branch portion SPL32 of the third power supply line SPL3 is in contact with a relay electrode R9B arranged in the opening of the subpixel SP2 through a contact hole CH15B. This electrically connects the third power supply line SPL3 and the switching element SW2B, enabling the third voltage VPP2 to be supplied to the switching element SW2B.

[0093] The touch detection lines TL1 and TL2 output sensor signals corresponding to the sensing results of the sensor electrodes Rx to the driver IC5. The touch detection line TL2 has a recessed shape on the opposite side to the opening of the subpixel SP2 at a position facing the second branch portion SPL32 that branches off from the third power supply line SPL3 toward the opening of the subpixel SP2. That is, the touch detection line TL2 has a recessed portion TL21 at a position facing the second branch portion SPL32 that is recessed so as to be spaced apart from the second branch portion SPL32. This can prevent the touch detection line TL2 and the second branch portion SPL32 from coming into contact with each other and causing a short circuit.

[0094] In addition, in the opening between the first scanning line SGL1 and the scanning line GL, island-shaped relay electrodes R4 corresponding to the signal lines SLR, SLG, and SLB are arranged as elements related to image display. The relay electrodes R4 are in contact with the relay electrodes R3 in the lower layer through contact holes CH5.

[0095] FIG. 11 is a diagram showing an example of the circuit configuration of the signal line / sensor signal line selection circuit 4. As shown in FIG. As shown in FIG. 11 , the signal line / sensor signal line selection circuit 4 has four second lines L2_R, L2_G, L2_B, and L2_FPS for one first line L1. The first line L1 is provided for each pixel column and transmits the video signal Sig_RGB output from the driver IC 5 during display mode and the detection signal Vdet to the driver IC 5 during detection operation. The second line L2_R is a line for transmitting the video signal Sig_R to the red subpixel SP1 included in each pixel PX located in a predetermined pixel column. The second line L2_G is a line for transmitting the video signal Sig_G to the green subpixel SP2 included in each pixel PX located in a predetermined pixel column. The second line L2_B is a line for transmitting the video signal Sig_B to the blue subpixel SP3 included in each pixel PX located in a predetermined pixel column. The second line L2_FPS is a line for transmitting the detection signal Vdet output from the optical sensor OS.

[0096] The signal line / sensor signal line selection circuit 4 is provided with four switching elements SW for each first line L1. More specifically, four switching elements SW11 to SW14 are provided for each first line L1_odd corresponding to odd-numbered pixel columns, and four switching elements SW21 to SW24 are provided for each first line L1_even corresponding to even-numbered pixel columns. The switching elements SW11 to SW14 and SW21 to SW24 each include an n-type TFT and a p-type TFT. The n-type TFT is a so-called nMOS (n-type semiconductor) that is turned on by a positive control signal ASW and is mainly turned on when transmitting a negative signal. The p-type TFT is a so-called pMOS (p-type semiconductor) that is turned on by a negative control signal xASW and is mainly turned on when transmitting a positive signal. However, both the n-type TFT and the p-type TFT may be turned on regardless of the polarity of the transmitted signal.

[0097] The switching element SW11 is connected to the first wiring L1_odd, a second wiring L2_R1 for transmitting a video signal Sig_R1 to a red subpixel SP1 included in each pixel PX located in an odd-numbered pixel column, a selection control signal line Lsel1 for transmitting a positive control signal ASW1 output from the driver IC5, and a selection control signal line Lxsel1 for transmitting a negative control signal xASW1 output from the driver IC5.

[0098] The switching element SW12 is connected to the first wiring L1_odd, a second wiring L2_G2 for transmitting a video signal Sig_G2 to a green subpixel SP2 included in each pixel PX located in an even-numbered pixel column, a selection control signal line Lsel2 for transmitting a positive control signal ASW2 output from the driver IC5, and a selection control signal line Lxsel2 for transmitting a negative control signal xASW2 output from the driver IC5.

[0099] The switching element SW13 is connected to the first wiring L1_odd, a second wiring L2_B1 for transmitting a video signal Sig_B1 to a blue subpixel SP3 included in each pixel PX located in an odd-numbered pixel column, a selection control signal line Lsel3 for transmitting a positive control signal ASW3 output from the driver IC5, and a selection control signal line Lxsel3 for transmitting a negative control signal xASW3 output from the driver IC5.

[0100] The switching element SW14 is connected to the first wiring L1_odd, a second wiring L2_FPS1 for transmitting a detection signal Vdet_FPS1 output from an optical sensor OS located in an odd-numbered pixel column, a selection control signal line Lsel4 for transmitting a positive control signal ASW4 output from the driver IC5, and a selection control signal line Lxsel4 for transmitting a negative control signal xASW4 output from the driver IC5.

[0101] The switching element SW21 is connected to the first wiring L1_even, the second wiring L2_R2 for transmitting the video signal Sig_R2 to the red subpixel SP1 included in each pixel PX located in the even-numbered pixel column, the above-mentioned selection control signal line Lsel1, and the above-mentioned selection control signal line Lxsel1.

[0102] The switching element SW22 is connected to the first wiring L1_even, the second wiring L2_G1 for transmitting the video signal Sig_G1 to the green subpixel SP2 included in each pixel PX located in the odd-numbered pixel column, the above-mentioned selection control signal line Lsel2, and the above-mentioned selection control signal line Lxsel2.

[0103] The switching element SW23 is connected to the first wiring L1_even, the second wiring L2_B2 for transmitting the video signal Sig_B2 to the blue subpixel SP3 included in each pixel PX located in the even-numbered pixel column, the above-mentioned selection control signal line Lsel3, and the above-mentioned selection control signal line Lxsel3.

[0104] The switching element SW24 is connected to the first wiring L1_even, the second wiring L2_FPS2 for transmitting the detection signal Vdet_FPS2 output from the optical sensor OS located in the even-numbered pixel column, the above-mentioned selection control signal line Lsel4, and the above-mentioned selection control signal line Lxsel4.

[0105] FIG. 12 is a plan view showing a schematic configuration example of the switching elements SW11 to SW14 and SW21 to SW24 shown in FIG. First, the switching elements SW11 and SW13 will be described. The wiring GLR1_ASW1 functions as the gate electrode of the n-type TFT of the switching element SW11, extends along the second direction Y, and is connected to the selection control signal line Lsel1 through a contact hole CHR1_ASW1. The wiring GLB1_ASW3 functions as the gate electrode of the n-type TFT of the switching element SW13, extends along the second direction Y, and is connected to the selection control signal line Lsel3 through a contact hole CHB1_ASW3. A single semiconductor layer SC11 is arranged in an area overlapping with the wiring GLR1_ASW1 and the wiring GLB1_ASW3 in a planar view. The semiconductor layer SC11 is shared by the n-type TFTs of the switching elements SW11 and SW13. The wiring GLR1_ASW1 and the wiring GLB1_ASW3 are arranged adjacent to each other in the first direction X in an area overlapping with the semiconductor layer SC11.

[0106] The wiring GLR1_xASW1 functions as the gate electrode of the p-type TFT of the switching element SW11, extends along the second direction Y, and is connected to the selection control signal line Lxsel1 through a contact hole CHR1_xASW1. The wiring GLB1_xASW3 functions as the gate electrode of the p-type TFT of the switching element SW13, extends along the second direction Y, and is connected to the selection control signal line Lxsel3 through a contact hole CHB1_xASW3. The wiring GLR1_xASW1 is arranged adjacent to the wiring GLR1_ASW1 in the second direction Y. The wiring GLB1_xASW3 is arranged adjacent to the wiring GLB1_ASW3 in the second direction Y. A single semiconductor layer SC12 is arranged in a region overlapping the wiring GLR1_xASW1 and the wiring GLB1_xASW3 in a planar view. The semiconductor layer SC12 is shared by the p-type TFTs of the switching elements SW11 and SW13. The wiring GLR1_xASW1 and the wiring GLB1_xASW3 are arranged adjacent to each other in the first direction X in a region overlapping with the semiconductor layer SC12.

[0107] The second wiring L2_R1A functions as the drain electrode of the n-type TFT of the switching element SW11 and also functions as the source electrode of the p-type TFT of the switching element SW11. The second wiring L2_R1A overlaps with the semiconductor layers SC11 and SC12 in a planar view. The second wiring L2_R1A is arranged in a layer above the wiring GLR1_ASW1 and the wiring GLR1_xASW1 and extends in the second direction Y along the wiring GLR1_ASW1 and the wiring GLR1_xASW1 in a planar view. The second wiring L2_R1A does not intersect with the selection control signal line Lsel and is therefore connected to the second wiring L2_R1B, which is arranged in the same layer as the wiring GLR1_ASW1 and the wiring GLR1_xASW1, through a contact hole CH_R1. The second wiring L2_R1B is disposed between the wiring GLR1_ASW1 and the wiring GLB1_ASW3, and extends along the second direction Y.

[0108] The second wiring L2_B1A functions as a drain electrode of the n-type TFT of the switching element SW13 and also functions as a source electrode of the p-type TFT of the switching element SW13. The second wiring L2_B1A overlaps with the semiconductor layers SC11 and SC12 in a planar view. The second wiring L2_B1A is arranged in a layer above the wiring GLB1_ASW3 and the wiring GLB1_xASW3, and extends in the second direction Y along the wiring GLB1_ASW3 and the wiring GLB1_xASW3 in a planar view. The second wiring L2_B1A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_B1B, which is arranged in the same layer as the wiring GLB1_ASW3 and the wiring GLB1_xASW3, through a contact hole CH_B1. The second wiring L2_B1B is disposed between the wiring GLB1_ASW3 and a second wiring L2_G2B, which will be described later, and extends along the second direction Y.

[0109] The first wiring L1A_odd has three branches L1_1A, L1_1B, and L1_1C. The branch L1_1A functions as a source electrode of the n-type TFT of the switching element SW11 and as a drain electrode of the p-type TFT of the switching element SW11. The branch L1_1A also functions as a source electrode of the n-type TFT of the switching element SW13 and as a drain electrode of the p-type TFT of the switching element SW13. The branch L1_1A overlaps with the semiconductor layers SC11 and SC12 in a planar view. The branch L1_1A is disposed between the second wiring L2_R1A and the second wiring L2_B1A and extends along the second direction Y. The first wiring L1A_odd does not intersect with the selection control signal line Lxsel and is therefore connected through a contact hole CHL1A_odd to a first wiring L1B_odd arranged in the same layer as the wiring GLR1_xASW1 and the wiring GLB1_xASW3. The first wiring L1B_odd is arranged between the wiring GLB1_xASW3 and a wiring GLG_xASW2 (described later) and extends along the second direction Y.

[0110] Next, the switching element SW12 will be described. The wiring GLG_ASW2 functions as the gate electrode of the n-type TFTs of the switching elements SW12 and SW22, extends along the second direction Y, and is connected to the selection control signal line Lsel2 through a contact hole CHG_ASW2. The wiring GLG_ASW2 has two U-shaped branches GLGa_ASW2 and GLGb_ASW2, and a semiconductor layer SC13 constituting the n-type TFT of the switching element SW12 is disposed in the region overlapping with the branch GLGa_ASW2 in plan view. Furthermore, a semiconductor layer SC23 constituting the n-type TFT of the switching element SW22 is disposed in the region overlapping with the branch GLGb_ASW2 in plan view. The two branches GLGa_ASW2 and GLGb_ASW2 are disposed adjacent to each other in the first direction X.

[0111] The wiring GLG_xASW2 functions as the gate electrodes of the p-type TFTs of the switching elements SW12 and SW22. It extends along the second direction Y and is connected to the selection control signal line Lxsel2 through a contact hole CHG_xASW2. The wiring GLG_xASW2 has two U-shaped branches GLGa_xASW2 and GLGb_xASW2. A semiconductor layer SC14 constituting the p-type TFT of the switching element SW12 is disposed in a region overlapping with the branch GLGa_xASW2 in a planar view. A semiconductor layer SC24 constituting the p-type TFT of the switching element SW22 is disposed in a region overlapping with the branch GLGb_xASW2 in a planar view. The two branches GLGa_xASW2 and GLGb_xASW2 are disposed adjacent to each other in the first direction X.

[0112] The second wiring L2_G2A functions as the drain electrode of the n-type TFT of the switching element SW12 and as the source electrode of the p-type TFT of the switching element SW12. The second wiring L2_G2A overlaps with the semiconductor layers SC13 and SC14 in a planar view. The second wiring L2_G2A is disposed in a layer above the wiring GLG_ASW2 and the wiring GLG_xASW2, and extends in the second direction Y along the branch portions GLGa_ASW2 and GLGa_xASW2 in a planar view. The second wiring L2_G2A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_G2B, which is disposed in the same layer as the wiring GLG_ASW2 and the wiring GLG_xASW2, through a contact hole CH_G2. The second wiring L2_G2B is disposed between the wiring GLG_ASW2 and the second wiring L2_B1B and extends in the second direction Y.

[0113] The branch portion L1_1B of the first wiring L1A_odd described above functions as a source electrode of the n-type TFT of the switching element SW12 and also functions as a drain electrode of the p-type TFT of the switching element SW12. The branch portion L1_1B overlaps with the semiconductor layers SC13 and SC14 in a plan view. The branch portion L1_1B is disposed between the second wiring L2_B1A and the second wiring L2_G2A and extends along the second direction Y.

[0114] Next, the switching element SW14 will be described. The wiring GLFPS1_ASW4 functions as the gate electrode of the n-type TFT of the switching element SW14, extends along the second direction Y, and is connected to the selection control signal line Lsel4 through a contact hole CHFPS1_ASW4. In the area overlapping with the wiring GLFPS1_ASW4 in plan view, a semiconductor layer SC15 that constitutes the n-type TFT of the switching element SW14 is arranged.

[0115] The wiring GLFPS1_xASW4 functions as the gate electrode of the p-type TFT of the switching element SW14, extends along the second direction Y, and is connected to the selection control signal line Lxsel4 through a contact hole CHFPS1_xASW4. In the area overlapping with the wiring GLFPS1_xASW4 in plan view, a semiconductor layer SC16 that constitutes the p-type TFT of the switching element SW14 is arranged.

[0116] The second wiring L2_FPS1A functions as the drain electrode of the n-type TFT of the switching element SW14 and also functions as the source electrode of the p-type TFT of the switching element SW14. The second wiring L2_FPS1A overlaps with the semiconductor layers SC15 and SC16 in a planar view. The second wiring L2_FPS1A is arranged in a layer above the wiring GLFPS1_ASW4 and the wiring GLFPS1_xASW4, and extends in the second direction Y along the wiring GLFPS1_ASW4 and the wiring GLFPS1_xASW4 in a planar view. The second wiring L2_FPS1A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_FPS1B, which is arranged in the same layer as the wiring GLFPS1_ASW4 and the wiring GLFPS1_xASW4, through a contact hole CH_FPS1. The second wiring L2_FPS1B is disposed between the wiring GLFPS1_ASW4 and a second wiring L2_FPS2B, which will be described later, and extends along the second direction Y.

[0117] The branch portion L1_1C of the first wiring L1A_odd described above functions as a source electrode of the n-type TFT of the switching element SW14 and also functions as a drain electrode of the p-type TFT of the switching element SW14. The branch portion L1_1C overlaps with the semiconductor layers SC15 and SC16 in a plan view. The branch portion L1_1C is disposed between the second wiring L2_FPS1A and the second wiring L2_R1A and extends along the second direction Y.

[0118] Next, the switching elements SW21 and SW23 will be described. The wiring GLR2_ASW1 functions as the gate electrode of the n-type TFT of the switching element SW21, extends along the second direction Y, and is connected to the selection control signal line Lsel1 through a contact hole CHR2_ASW1. The wiring GLB2_ASW3 functions as the gate electrode of the n-type TFT of the switching element SW23, extends along the second direction Y, and is connected to the selection control signal line Lsel3 through a contact hole CHB2_ASW3. A single semiconductor layer SC21 is arranged in a region overlapping with the wiring GLR2_ASW1 and the wiring GLB2_ASW3 in a planar view. The semiconductor layer SC21 is shared by the n-type TFTs of the switching elements SW21 and SW23. The wiring GLR2_ASW1 and the wiring GLB2_ASW3 are arranged adjacent to each other in the first direction X in a region overlapping with the semiconductor layer SC21.

[0119] The wiring GLR2_xASW1 functions as the gate electrode of the p-type TFT of the switching element SW21, extends along the second direction Y, and is connected to the selection control signal line Lxsel1 through a contact hole CHR2_xASW1. The wiring GLB2_xASW3 functions as the gate electrode of the p-type TFT of the switching element SW23, extends along the second direction Y, and is connected to the selection control signal line Lxsel3 through a contact hole CHB2_xASW3. The wiring GLR2_xASW1 is arranged adjacent to the wiring GLR2_ASW1 in the second direction Y. The wiring GLB2_xASW3 is arranged adjacent to the wiring GLB2_ASW3 in the second direction Y. A single semiconductor layer SC22 is arranged in a region overlapping the wiring GLR2_xASW1 and the wiring GLB2_xASW3 in a planar view. The semiconductor layer SC22 is shared by the p-type TFTs of the switching elements SW21 and SW23. The wiring GLR2_xASW1 and the wiring GLB2_xASW3 are arranged adjacent to each other in the first direction X in a region overlapping with the semiconductor layer SC22.

[0120] The second wiring L2_R2A functions as a drain electrode of the n-type TFT of the switching element SW21 and also functions as a source electrode of the p-type TFT of the switching element SW21. The second wiring L2_R2A overlaps with the semiconductor layers SC21 and SC22 in a planar view. The second wiring L2_R2A is arranged in a layer above the wiring GLR2_ASW1 and the wiring GLR2_xASW1, and extends in the second direction Y along the wiring GLR2_ASW1 and the wiring GLR2_xASW1 in a planar view. The second wiring L2_R2A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_R2B, which is arranged in the same layer as the wiring GLR2_ASW1 and the wiring GLR2_xASW1, through a contact hole CH_R2. The second wiring L2_R2B is disposed between the wiring GLR2_ASW1 and the wiring GLB2_ASW3, and extends along the second direction Y.

[0121] The second wiring L2_B2A functions as a drain electrode of the n-type TFT of the switching element SW23 and also functions as a source electrode of the p-type TFT of the switching element SW23. The second wiring L2_B2A overlaps with the semiconductor layers SC21 and SC22 in a planar view. The second wiring L2_B2A is arranged in a layer above the wiring GLB2_ASW3 and the wiring GLB2_xASW3, and extends in the second direction Y along the wiring GLB2_ASW3 and the wiring GLB2_xASW3 in a planar view. The second wiring L2_B2A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_B2B arranged in the same layer as the wiring GLB2_ASW3 and the wiring GLB2_xASW3 through a contact hole CH_B2. The second wiring L2_B2B is disposed between the wiring GLB2_ASW3 and the second wiring L2_G1B, and extends along the second direction Y.

[0122] The first wiring L1A_even has three branches L1_2A, L1_2B, and L1_2C. The branch L1_2A functions as a source electrode of the n-type TFT of the switching element SW21 and as a drain electrode of the p-type TFT of the switching element SW21. The branch L1_2A also functions as a source electrode of the n-type TFT of the switching element SW23 and as a drain electrode of the p-type TFT of the switching element SW23. The branch L1_2A overlaps with the semiconductor layers SC21 and SC22 in a plan view. The branch L1_2A is disposed between the second wiring L2_R2A and the second wiring L2_B2A and extends along the second direction Y. The first wiring L1_2A does not intersect with the selection control signal line Lxsel, and is therefore connected through a contact hole CHL1_even to the first wiring L1B_even, which is arranged in the same layer as the wiring GLR2_xASW1 and the wiring GLB2_xASW3. The first wiring L1B_even is arranged between the wiring GLB2_xASW3 and the wiring GLG_xASW2, and extends along the second direction Y.

[0123] Next, the switching element SW22 will be described. The second wiring L2_G1A functions as the drain electrode of the n-type TFT of the switching element SW22 and also functions as the source electrode of the p-type TFT of the switching element SW22. The second wiring L2_G1A overlaps with the semiconductor layers SC23 and SC24 in a planar view. The second wiring L2_G1A is arranged in a layer above the wiring GLG_ASW2 and the wiring GLG_xASW2, and extends in the second direction Y along the branch portions GLGb_ASW2 and GLGb_xASW2 in a planar view. The second wiring L2_G1A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_G1B, which is arranged in the same layer as the wiring GLG_ASW2 and the wiring GLG_xASW2, through a contact hole CH_G1. The second wiring L2_G1B is disposed between the wiring GLG_ASW2 and the second wiring L2_B2B, and extends along the second direction Y.

[0124] The branch portion L1_2B of the first wiring L1A_even functions as a source electrode of the n-type TFT of the switching element SW22 and also functions as a drain electrode of the p-type TFT of the switching element SW22. The branch portion L1_2B overlaps with the semiconductor layers SC23 and SC24 in a plan view. The branch portion L1_2B is disposed between the second wiring L2_B2A and the second wiring L2_G1A and extends along the second direction Y.

[0125] Next, the switching element SW24 will be described. The wiring GLFPS2_ASW4 functions as the gate electrode of the n-type TFT of the switching element SW24, extends along the second direction Y, and is connected to the selection control signal line Lsel4 through a contact hole CHFPS2_ASW4. In the area overlapping with the wiring GLFPS2_ASW4 in plan view, a semiconductor layer SC25 that constitutes the n-type TFT of the switching element SW24 is arranged.

[0126] The wiring GLFPS2_xASW4 functions as the gate electrode of the p-type TFT of the switching element SW24, extends along the second direction Y, and is connected to the selection control signal line Lxsel4 through a contact hole CHFPS2_xASW4. In the area overlapping with the wiring GLFPS2_xASW4 in plan view, a semiconductor layer SC26 that constitutes the p-type TFT of the switching element SW24 is arranged.

[0127] The second wiring L2_FPS2A functions as the drain electrode of the n-type TFT of the switching element SW24 and also functions as the source electrode of the p-type TFT of the switching element SW24. The second wiring L2_FPS2A overlaps with the semiconductor layers SC25 and SC26 in a planar view. The second wiring L2_FPS2A is arranged in a layer above the wiring GLFPS2_ASW4 and the wiring GLFPS2_xASW4, and extends in the second direction Y along the wiring GLFPS2_ASW4 and the wiring GLFPS2_xASW4 in a planar view. The second wiring L2_FPS2A does not intersect with the selection control signal line Lsel, and is therefore connected to the second wiring L2_FPS2B, which is arranged in the same layer as the wiring GLFPS2_ASW4 and the wiring GLFPS2_xASW4, through a contact hole CH_FPS2. The second wiring L2_FPS2B is disposed between the wiring GLFPS2_ASW4 and the second wiring L2_FPS1B corresponding to an adjacent odd-numbered pixel column (not shown in FIG. 12), and extends along the second direction Y.

[0128] The branch portion L1_2C of the first wiring L1A_even functions as a source electrode of the n-type TFT of the switching element SW24 and also functions as a drain electrode of the p-type TFT of the switching element SW24. The branch portion L1_2C overlaps with the semiconductor layers SC25 and SC26 in a plan view. The branch portion L1_2C is disposed between the second wiring L2_FPS2A and the second wiring L2_R2A and extends along the second direction Y.

[0129] FIG. 13 is a cross-sectional view showing a schematic configuration example of a portion where the second wiring L2_FPS2B shown in FIG. 12 is electrically connected to the sensor signal line SSL. 13, the second wiring L2_FPS2B is disposed between the insulating layers 11 and 12, i.e., in the same layer as the scanning line GL. The relay electrode R21 is disposed between the insulating layers 12 and 13, i.e., in the same layer as the signal line SL, and is in contact with the second wiring L2_FPS2B through a contact hole CH31 that penetrates the insulating layer 12. The relay electrode R22 is disposed between the insulating layers 13 and 14, i.e., in the same layer as the optical sensor OS, and is in contact with the relay electrode R21 through a contact hole CH32 that penetrates the insulating layer 13. The sensor signal line SSL is disposed between the insulating layers 14 and 15, i.e., in the same layer as the first power supply line SPL1 and the second power supply line SPL2, and is in contact with the relay electrode R22 through a contact hole CH33 that penetrates the insulating layer 14. According to this, the second wiring L2_FPS2B and the sensor signal line SSL are electrically connected, and the detection signal Vdet (detection signal Vdet_FPS2) output from the optical sensor OS is output to the driver IC5 via the sensor signal line SSL, the second wiring L2_FPS2B, the second wiring L2_FPS2A, the first wiring L1A_even and L1B_even.

[0130] In Figure 13, we have described the part where the second wiring L2_FPS2B and the sensor signal line SSL (more specifically, the sensor signal line SSL corresponding to the optical sensor OS located in the even-numbered pixel column) are electrically connected, but the same applies to the part where the second wiring L2_FPS1B and the sensor signal line SSL (more specifically, the sensor signal line SSL corresponding to the optical sensor OS located in the odd-numbered pixel column) are electrically connected.

[0131] FIG. 14 is a plan view showing a schematic configuration example of a portion where the second wiring L2_FPS2B shown in FIG. 12 is electrically connected to the sensor signal line SSL. The second wiring L2_FPS2B is routed from the contact hole CH_FPS2 shown in FIG. 12 to the contact hole CH31 shown in FIG. 14 so as to pass under the selection control signal line Lsel (Lsel4). The second wiring L2_FPS2B is connected to an island-shaped relay electrode R21 through the contact hole CH31. The relay electrode R21 is connected to an island-shaped relay electrode R22 through a contact hole CH32. The relay electrode R22 is connected to the sensor signal line SSL through a contact hole CH33. The sensor signal line SSL extends to the display area DA and is electrically connected to the corresponding optical sensor OS. The second wiring L2_FPS2B is adjacent to the second wiring L2_R2B in the first direction X nearer the display area DA than the selection control signal line Lsel. The relay electrodes R21, R22 and the sensor signal line SSL overlap with the second wiring L2_R2B in a plan view.

[0132] In Figure 14, we have described the part where the second wiring L2_FPS2B and the sensor signal line SSL (more specifically, the sensor signal line SSL corresponding to the optical sensor OS located in the even-numbered pixel column) are electrically connected, but the same applies to the part where the second wiring L2_FPS1B and the sensor signal line SSL (more specifically, the sensor signal line SSL corresponding to the optical sensor OS located in the odd-numbered pixel column) are electrically connected.

[0133] The following describes the effects of the display device DSP according to this embodiment using a comparative example. Note that the comparative example is intended to explain some of the effects that can be achieved by the display device DSP according to this embodiment, and does not exclude configurations and effects common to this embodiment and the comparative example from the scope of the present invention.

[0134] 15 is a plan view schematically illustrating a display device DSP1 according to a comparative example. The display device DSP1 according to the comparative example differs from the display device DSP according to the present embodiment in that two driver ICs 5A and 5B are provided on a first flexible printed circuit board 1. The driver IC 5A corresponds to the display mode and the touch sensing mode, and the driver IC 5B corresponds to the detection operation by the optical sensor OS. The display device DSP1 according to the comparative example also differs from the display device DSP according to the present embodiment in that a signal line selection circuit 4A connected to the driver IC 5A, and a sensor signal line selection circuit 4B and a sensor line group 4C connected to the driver IC 5B are provided in a mounting area MA.

[0135] FIG. 16 is a circuit diagram showing the signal line selection circuit 4A, the sensor signal line selection circuit 4B, and the sensor line group 4C shown in FIG. 16, the signal line selection circuit 4A has three output lines Lout_R, Lout_G, and Lout_B for one input line Lin. The input line Lin is a line provided for each pixel column. The input line Lin is a line for transmitting the video signal Sig_RGB output from the driver IC 5A in the display mode.

[0136] The signal line selection circuit 4A is provided with three switching elements for each input line Lin. More specifically, three switching elements SW31-SW33 are provided for one input line Lin_odd corresponding to an odd-numbered pixel column, and three switching elements SW41-SW43 are provided for one input line Lin_even corresponding to an even-numbered pixel column. The switching elements SW31-SW33 and SW41-SW43 each have an n-type TFT and a p-type TFT. The switching elements SW31-SW33 and SW41-SW43 are each connected to one of three selection control signal lines Lsel1-Lsel3 that transmit a positive control signal ASW and one of three selection control signal lines Lxsel1-Lxsel3 that transmit a negative control signal xASW.

[0137] The sensor signal line selection circuit 4B is provided with one switching element SW51 for each input line Lin_FPS. The same number of switching elements SW51 as the number of input lines Lin_FPS are provided, and each switching element SW51 has an n-type TFT and a p-type TFT. Each switching element SW51 is connected to one of the ten selection control signal lines Lsel1_FPS to Lsel10_FPS that transmit the positive control signal ASW_FPS and one of the ten selection control signal lines Lxsel1_FPS to Lxsel10_FPS that transmit the negative control signal xASW_FPS.

[0138] The output wiring Lout_sw51 of the switching element SW51 included in the sensor signal line selection circuit 4B is connected to one of the 216 sensor lines Lout_FPS1 to Lout_FPS216 included in the sensor line group 4C. The detection signal Vdet output from the optical sensor OS is output to the driver IC 5B through the sensor signal line selection circuit 4B and the sensor line group 4C.

[0139] As shown in FIGS. 15 and 16, the display device DSP1 according to the comparative example includes two driver ICs 5A and 5B. Therefore, the mounting area MA of the display device DSP1 according to the comparative example must include a signal line selection circuit 4A connected to the driver IC 5A, and a sensor signal line selection circuit 4B and a sensor line group 4C connected to the driver IC 5B. This creates a problem of making it difficult to narrow the frame. Specifically, the signal line selection circuit 4A requires approximately 205 μm of space in the second direction Y. The sensor signal line selection circuit 4B requires approximately 310 μm of space in the second direction Y. The sensor line group 4C requires approximately 1765 μm of space in the second direction Y. In other words, the display device DSP1 according to the comparative example requires at least 2280 μm (= 205 + 310 + 1765 μm) of space in the second direction Y.

[0140] In contrast, the display device DSP according to this embodiment has only one driver IC, and the mounting area MA only needs to accommodate the signal line / sensor signal line selection circuit 4 connected to the driver IC 5, making it possible to make the mounting area MA smaller than that of the display device DSP1 according to the comparative example. Specifically, a space of approximately 240 μm in the second direction Y is sufficient to accommodate the signal line / sensor signal line selection circuit 4, making it possible to significantly reduce the mounting area MA compared to that of the display device DSP1 according to the comparative example. This allows for a narrower frame.

[0141] Furthermore, in the signal line / sensor signal line selection circuit 4 according to this embodiment, the semiconductor layers SC11 and SC12 are shared by the switching element SW11 corresponding to the red subpixel SP1 in each pixel PX located in the odd-numbered pixel columns and the switching element SW13 corresponding to the blue subpixel SP3 in each pixel PX located in the odd-numbered pixel columns, which enables space saving and a narrower frame compared to when separate semiconductor layers are provided. Similarly, in the signal line / sensor signal line selection circuit 4 according to this embodiment, the semiconductor layers SC21 and SC22 are shared by the switching element SW21 corresponding to the red subpixel SP1 in each pixel PX located in the even-numbered pixel columns and the switching element SW23 corresponding to the blue subpixel SP3 in each pixel PX located in the even-numbered pixel columns, which enables space saving and a narrower frame compared to when separate semiconductor layers are provided.

[0142] Furthermore, since the display device DSP according to this embodiment has only one driver IC, it is possible to align the center of the driver IC 5 with the center of the display panel PNL and then arrange the driver IC 5 on the first flexible printed circuit board 2. This allows various wires connected to the driver IC 5 to be routed symmetrically, which makes it possible to save space and achieve a narrower frame than, for example, the display device DSP1 according to the comparative example, in which the center of the driver IC and the center of the display panel are arranged as not to be aligned.

[0143] According to the embodiment described above, it is possible to provide a liquid crystal display device with an optical sensor that can achieve a narrow frame.

[0144] In this embodiment, the display device DSP is a liquid crystal display device equipped with an illumination device IL, but this is not limited to this, and the display device DSP may also be an organic electroluminescence display device equipped with an organic light-emitting diode (OLED) as a display element.

[0145] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0146] DSP...display device, PNL...display panel, 5...driver IC, SUB1...first substrate, SUB2...second substrate, LC...liquid crystal layer, SP1, SP2, SP3...sub-pixels, SLR, SLG, SLB...signal line, OS...optical sensor, PC...optical conversion element, Vdet...detection signal, SSL...sensor signal line, L1...first wiring.

Claims

1. a display panel including a first substrate, a second substrate facing the first substrate, and a liquid crystal layer located between the first substrate and the second substrate; a driver IC; The display panel includes: a first signal line for supplying a video signal to a first sub-pixel corresponding to red, a second signal line for supplying a video signal to a second sub-pixel corresponding to green, and a third signal line for supplying a video signal to a third sub-pixel corresponding to blue; an optical sensor including a photoelectric conversion element that outputs a detection signal according to light incident from the liquid crystal layer side; a sensor signal line connected to the optical sensor and transmitting the detection signal to the driver IC; One first wiring drawn from one terminal of the driver IC is connected to four switching elements, three switching elements among the four switching elements are each electrically connected to one of the first signal line, the second signal line, and the third signal line; one of the four switching elements, which is different from the three switching elements, is electrically connected to the sensor signal line; two of the four switching elements electrically connected to the first signal line and the third signal line share one semiconductor layer; two of the four switching elements electrically connected to the second signal line and the sensor signal line do not share a semiconductor layer with other switching elements; two switching elements electrically connected to the first signal line and the third signal line are disposed between two switching elements electrically connected to the second signal line and the sensor signal line; each of the semiconductor layers constituting the four switching elements has a protrusion and a recess in a first direction; the protruding portion of one of the two semiconductor layers adjacent to each other in the first direction faces the recessed portion of the other semiconductor layer; LCD display with optical sensor.

2. each of the four switching elements includes an n-type semiconductor and a p-type semiconductor; two of the four switching elements electrically connected to the first signal line and the third signal line share a first semiconductor layer as n-type semiconductors; p-type semiconductors of two of the four switching elements electrically connected to the first signal line and the third signal line share one second semiconductor layer; The liquid crystal display device with an optical sensor according to claim 1 .

3. The first wiring is When the driver IC is in a display mode for displaying an image, the video signal is transmitted to the first signal line, the second signal line, and the third signal line; When the driver IC is in a detection mode for detecting biological information, the detection signal is transmitted to the driver IC. The liquid crystal display device with an optical sensor according to claim 1 .

4. The driver IC is disposed so that the center of the driver IC is aligned with the center of the display panel. The liquid crystal display device with an optical sensor according to claim 1 .

5. The optical sensor The photoelectric conversion element; a first electrode made of a metal material and in contact with a lower surface of the photoelectric conversion element; a second electrode in contact with an upper surface of the photoelectric conversion element and made of a transparent conductive material; The liquid crystal display device with an optical sensor according to claim 1 .

Images