Indication device

Abstract

A display device with reduced power consumption is provided. A light-emitting element includes a first transistor, a second transistor, and a pair of electrodes. a pixel section including a plurality of pixels each including a first transistor, and a gate of the first transistor being a scanning The source or drain is electrically connected to a signal line. the other of the source and the drain is electrically connected to the gate of the second transistor, The transistor in 2 has either the source or the drain electrically connected to the power supply line, and the source Alternatively, the other of the drains is electrically connected to one of the pair of electrodes, and the first transistor The hydrogen concentration is 5×10 19 / cm 3 The oxide semiconductor layer is as follows: During the period when the display device displays a still image, the scanning lines included in the pixel unit are supplied with There is a period during which the output of the supplied signal is stopped.

Description

[Technical Field]

[0001] The present invention relates to a display device, or to an electronic device equipped with the display device. [Background technology]

[0002] In recent years, liquid crystal display devices and electroluminescence devices using electroluminescence elements have become popular. flat panel displays, typified by electroluminescent (EL) displays (hereinafter referred to as "EL displays"). Ray is mass-produced as the mainstream image display device.

[0003] In the case of active matrix type liquid crystal display devices and EL display devices, each pixel in the pixel area is These transistors are made of silicon (Si) The semiconductor layer is used as an active layer.

[0004] In response to this, image display devices using transistors with oxide active layers have been proposed. (See, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0006] The off-state current is one of the indicators for determining the electrical characteristics of a transistor. When the transistor is in an off state (also called a non-conducting state), In an n-channel transistor, the current that flows between the gate and the source When the applied voltage is equal to or less than the threshold voltage (Vth), the current that flows between the source and drain It refers to the flow.

[0007] By using an amorphous oxide semiconductor thin film as the channel layer of a transistor, Current is set to 10 μA (= 1 × 10 -5 A), preferably less than 0.1 μA (= 1 × 10 -7 A) Unknown Patent Document 1 discloses that the amorphous acid By using a thin film of a nitride semiconductor, the on-off ratio can be increased to 10 3 It can be described as super However, in a transistor that exhibits electrical characteristics of this order, the off-state current This means that there is a demand for further reduction in power consumption of image display devices. To meet the growing needs of today's society, it is necessary to further reduce the off-state current.

[0008] One embodiment of the present invention is a semiconductor device including a plurality of pixels each including a transistor including an oxide semiconductor. The object of the present invention is to provide a display device including a pixel portion, in which power consumption is suppressed. It shall be one. [Means for solving the problem]

[0009] One embodiment of the present invention is a display device in which an oxide semiconductor is used in each pixel of a display portion. The semiconductor device is characterized by having at least a transistor. The photodiode has stable electrical properties, such as extremely low off-state current. In order to realize a transistor with low resistance, one aspect of the present invention is to provide an intrinsic or substantially intrinsic transistor. The concentration of impurities that act as carrier donors is extremely reduced to the extent that the oxide semiconductor (high purity Typically, in one embodiment of the present invention, the hydrogen concentration in the film is is 5 x 10 19 / cm 3 The following transistors are made using oxide semiconductors.

[0010] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a pair of electrodes. The pixel portion has a plurality of pixels each including a light-emitting element. The gate of the transistor is electrically connected to a scanning line, and either the source or the drain is electrically connected to a signal line. the other of the source and drain is electrically connected to the gate of the second transistor. and the second transistor has one of its source and drain electrically connected to a power supply line. the other of the source and drain is electrically connected to one of the pair of electrodes; The first transistor has a hydrogen concentration of 5×10 19 / cm 3 an oxide semiconductor layer The display device is characterized by having:

[0011] In addition, one aspect of the present invention is a method for manufacturing a display device, comprising: a display device having a period in which the output of signals supplied to all scanning lines included in the do.

[0012] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a pair of electrodes. a pixel portion provided with a plurality of pixels each including a light-emitting element having the a control signal for driving the driving circuit unit and an image signal for supplying to the pixels. a signal generating circuit, a memory circuit for storing the image signal for each frame period, and Among the image signals stored for each frame period, the difference between the image signals for successive frame periods a comparison circuit for detecting a difference between the consecutive frame periods, a selection circuit for selecting and outputting the image signal of a signal and an image signal output from the selection circuit are supplied to the drive circuit unit, and the ratio When the comparison circuit does not detect a difference, the display control circuit stops supplying the control signal to the drive circuit unit. The first transistor has a gate electrically connected to a scanning line. One of the source and the drain is electrically connected to a signal line, and the other of which is electrically connected to the gate of the second transistor, In the case of a transistor, either the source or the drain is electrically connected to a power supply line, and the The other of the first transistors is electrically connected to one of the pair of electrodes, and the first transistor is is 5 x 10 19 / cm 3 A display device having an oxide semiconductor layer as follows: be.

[0013] In addition, one aspect of the present invention is a method for controlling a power supply voltage, a clock signal, a power supply voltage ... This is a display device that is a start pulse signal or a reset signal.

[0014] Another embodiment of the present invention is a display device further including a luminescent layer in the pixel.

[0015] In one aspect of the present invention, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 It is a display device that is less than

[0016] In one embodiment of the present invention, the band gap of the oxide semiconductor layer is 2 eV or more. It is a display device.

[0017] In one embodiment of the present invention, the second transistor has a hydrogen concentration of 5×10 19 / cm 3 The display device includes the following oxide semiconductor layer.

[0018] In one aspect of the present invention, the second transistor is a display having a polycrystalline silicon layer. It is a device.

[0019] Another aspect of the present invention is an electronic device including the display device.

[0020] It should be noted that, due to the structure of a transistor, it is difficult to distinguish between the source and the drain. Depending on the operation of the circuit, the high and low potentials may be reversed. In this example, the source and drain are not particularly specified, but are referred to as a first electrode (or a first terminal), a second electrode (or For example, if the first electrode is the source, the second electrode is refers to the drain, and conversely, if the first electrode is the drain, the second electrode is the source. This refers to the

[0021] In this specification, the term "aperture ratio" refers to the area of ​​a region through which light passes per unit area. The ratio of the area occupied by the non-transmitting material to the aperture increases. When the aperture ratio decreases and the area occupied by the light-transmitting member increases, the aperture ratio increases. In a display device, the area occupied by the wiring and capacitance line overlapping the pixel electrode and the size of the transistor are Reducing the size will improve the aperture ratio.

[0022] In particular, in a self-luminous display device in which each pixel contains a light-emitting element, the viewer The ratio of the light-emitting area of ​​the light-emitting element that can be observed from a position facing the display to the pixel area is called the aperture ratio. That's what they say.

[0023] In addition, in this specification, when it is stated that "A and B are connected," it means that A and B are are electrically connected (i.e., there is another element or circuit between A and B) A and B are functionally connected (i.e., A and B are not connected) and B is functionally connected (i.e., A and B are not connected). (When A and B are functionally connected via another circuit) and (When A and B are directly connected) This includes cases where A and B are connected without any other element or circuit between them. This shall be done.

[0024] Furthermore, the terms "first," "second," "third," and "Nth" (N is a natural number) used in this specification mean: The numbers are added to avoid confusion of the components and are not intended to limit the number. The term "first transistor" used in this specification does not cause confusion with other components. In this range, it can be read as "second transistor." [Effects of the Invention]

[0025] According to one embodiment of the present invention, a transistor including a high-purity oxide semiconductor can be used as a display device. By using it in the element part, the off-current is reduced to 1×10 -13 This can be reduced to below A. This allows for a longer data retention period, reducing power consumption when displaying still images, etc. It can be suppressed.

[0026] In addition, the operation of the drive circuit unit is controlled during the period when a still image is displayed by determining whether the image is a still image or a moving image. By stopping the power consumption of the display device, it is possible to further reduce the power consumption of the display device. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 illustrates an example of the configuration of a display device. [Figure 2] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of a pixel. [Figure 3] FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 4] FIG. 4 is a diagram showing the relationship between a writing period and a holding period for a pixel. [Figure 5] FIG. 2 is a cross-sectional view showing an example of the configuration of a pixel. [Figure 6] 1A and 1B are a plan view and a cross-sectional view showing an example of a light-emitting display panel. [Figure 7] FIG. 1 is a block diagram illustrating an example of a display device. [Figure 8] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 9] FIG. 2 is a timing chart of a driver circuit. [Figure 10] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 11] 10A and 10B are diagrams showing an example of a procedure for supplying and stopping a signal to a driver circuit. [Figure 12] 1A and 1B are a plan view and a cross-sectional view showing an example of a light-emitting display panel. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating an example of a transistor. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 18] FIG. 2 is a cross-sectional view showing an example of the configuration of a pixel. [Figure 19] 1A and 1B are diagrams illustrating electronic devices. [Figure 20] 1A and 1B are diagrams illustrating electronic devices. [Figure 21] FIG. 1 is a diagram showing a band structure between the source and drain of a MOS transistor using an oxide semiconductor. [Figure 22] FIG. 20 is a diagram showing a state in which a positive voltage is applied to the drain side in FIG. 19. [Figure 23] 1A and 1B are energy band diagrams of the MOS structure of a MOS transistor using an oxide semiconductor, showing (A) the case where the gate voltage is positive, and (B) the case where the gate voltage is negative. [Figure 24] A diagram showing the band structure between the source and drain of a silicon MOS transistor. [Figure 25] FIG. 10 shows initial characteristics of fabricated transistors. [Figure 26] FIG. 10 is a top view showing a fabricated transistor. [Figure 27] 10A and 10B show electrical characteristics of fabricated transistors. [Figure 28] 10A and 10B are diagrams showing an example of a procedure for supplying and stopping a signal to a driver circuit. DETAILED DESCRIPTION OF THE INVENTION

[0028] An embodiment according to one aspect of the present invention will be described in detail with reference to the drawings. The invention is not limited to the following description, and various modifications and variations are possible without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details and implementations. It should be noted that the present invention is not limited to the following embodiments. In the drawings, the reference numerals indicating the same objects are common among different drawings.

[0029] In the following embodiments and examples, unless otherwise specified, The present invention may be implemented in appropriate combination with other embodiments and examples described in this specification. It is Noh.

[0030] (Embodiment 1) In this embodiment, an example of a display device according to one embodiment of the present invention will be described. An example of the configuration of a pixel provided in a pixel portion of a display device will be described with reference to FIGS. 1 to 6. do.

[0031] FIG. 1 is a diagram showing an example of the configuration of a display device according to one embodiment of the present invention. In the display device, a pixel section 202 in which a plurality of pixels 201 are arranged in a matrix is ​​provided on a substrate 2. 00. The display device includes a circuit for driving the plurality of pixels 201. The pixel 201 includes a scanning line driver circuit 203 and a signal line driver circuit 204. A scanning signal is supplied by a first wiring 121 (scanning line) electrically connected to the circuit 203. The scanning signal determines whether each row is in a selected state or a non-selected state. The selected pixel 201 is connected to the second wiring 1 electrically connected to the signal line driving circuit 204. 22 (signal line), a video voltage (video signal, image signal, video The pixel 201 has a pair of electrodes. A light emitting element is provided, and one electrode of the light emitting element is connected to a power supply for supplying a potential. The wire 123 is electrically connected.

[0032] In FIG. 1, the scanning line driving circuit 203 and the signal line driving circuit 204 are mounted on the substrate 20. However, the present invention is not limited to this configuration. That is, either the scanning line driving circuit 203 or the signal line driving circuit 204 is provided on the substrate 200. Alternatively, only the pixel portion 202 may be provided on the substrate 200. It may be composed of

[0033] In addition, in FIG. 1, a plurality of pixels 201 are arranged in a matrix (stripe arrangement). However, the present invention is not limited to this configuration. As for the layout configuration, not only stripe layout but also delta layout, Bayer layout, etc. can be adopted. This can be done.

[0034] The display method in the pixel unit 202 may be a progressive method, an interlace method, or the like. In addition, RG can be used as a color element controlled by pixels when displaying colors. It is not limited to the three colors of RGBW (W is white) and B (R is red, G is green, B is blue). (representing the color), or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may also be applied to monochrome display devices. It is also possible to do so.

[0035] In addition, in FIG. 1, the number of first wirings 121 and the number of second wirings 122 are the same as that of pixels. Although the present invention is not limited to this configuration, the number of rows and columns corresponds to the number of rows and columns. For example, the first wiring 121 or the second wiring 122 is not shared between adjacent pixels. The pixel 201 may be driven by the pixel driver.

[0036] 2 is an equivalent circuit diagram showing an example of the configuration of the pixel 201 in FIG. The pixel configuration is not limited to that shown in FIG.

[0037] The pixel 6400 includes a first transistor (hereinafter referred to as a switching transistor). A second transistor (hereinafter, sometimes referred to as a driving transistor) 6401 A light-emitting element 6402 and a light-emitting element 6404 are provided.

[0038] The first transistor 6401 has a gate electrically connected to a scanning line 6406 and a first The electrode (one of the source electrode and the drain electrode) is electrically connected to the signal line 6405, and the second The other of the source electrode and the drain electrode is connected to the gate of the second transistor 6402. The second transistor 6402 is electrically connected to the first electrode (source electrode and one of the drain electrodes) is electrically connected to a power supply line 6407, and the second electrode (source The other of the electrode and drain electrode is electrically connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. In addition, in FIG. 2, a capacitance is provided between the gate of the second transistor 6402 and the power supply line 6407. Although the element 6410 is provided, the present invention is not limited to this configuration. Between the gate of the second transistor 6402 and the second electrode of the second transistor 6402 A capacitance element may be provided.

[0039] The common electrode 6408 is electrically connected to a common potential line and is provided with a low power supply potential. Also, the power supply line 6407 is set to be supplied with a high power supply potential. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. A potential that satisfies the condition that the potential is lower than the high power supply potential. Examples of low power supply potential include GND and 0V. The potential difference between the high power supply potential and the low power supply potential is are set to be at least equal to or greater than the forward threshold voltage of the light emitting element 6404. It is necessary.

[0040] In this embodiment, a transistor including an oxide semiconductor layer is used as a first transistor. The first transistor 6401 is an n-channel transistor. The second transistor 6402 is an n-channel transistor. Either a p-channel transistor or a p-channel transistor may be used. The transistor 6402 may have a structure in which an oxide semiconductor layer is used as an active layer, or a silicon When a silicon layer is used as the active layer, the silicon layer is amorphous. Although a silicon layer may be used, it is preferable to use a polycrystalline silicon layer. The second transistor 6402 is an n-channel transistor, and the oxide semiconductor layer The case where the active layer is used will be described.

[0041] Next, an example of a cross-sectional view of a first transistor 6401 in a pixel 6400 is shown in FIG. The transistor 106 shown in FIG. 3 corresponds to the first transistor 6401. The oxide semiconductor layer 103 serving as a channel region has a bottom-gate structure. The first wiring 101 serving as a gate electrode is disposed on the lower side of the insulating film 101, and the oxide semiconductor layer 103 is disposed between the insulating film 101 and the insulating film 102. A first electrode (one of the source electrode and the drain electrode) is disposed on the opposite side of the first wiring 101. ) 102A, and a second electrode (the other of the source electrode and the drain electrode) 102B. Therefore, it is also called an inverted staggered transistor.

[0042] A first wiring 101 is provided on a substrate 111 via an underlying film 112. The wiring 101 functions as a gate of the transistor 106. The scanning line may be the scanning line itself electrically connected to the scanning line driving circuit, or may be a It may also be a wiring that is electrically connected.

[0043] A gate insulating film 113 is provided to cover the first wiring 101. An oxide semiconductor layer 103 is provided on the gate insulating film 113. A first electrode 102A and a second electrode 102B are provided on the body layer 103. The first electrode 102A and the second electrode 102B are electrically connected to the oxide semiconductor layer 103. One functions as a source electrode and the other functions as a drain electrode. The first electrode 102A may be a signal line itself that is electrically connected to the signal line driving circuit. Alternatively, it may be a wiring electrically connected to a signal line.

[0044] In addition, on the oxide semiconductor layer 103, the first electrode 102A, and the second electrode 102B, An oxide insulating layer 114 is provided, which functions as a passivation film. An opening is formed in the layer 114, and the fourth wiring 105 and the second wiring 106 are connected to the opening. The fourth wiring 105 is electrically connected to the second transformer 102B. The gate of the transistor is electrically connected to the gate of the transistor.

[0045] Next, the oxide semiconductor layer 103 will be described.

[0046] The oxide semiconductor layer 103 used in this embodiment is a Impurities that adversely affect electrical characteristics have been reduced to an extremely low level, A typical example of an impurity that adversely affects electrical properties is hydrogen. Hydrogen is an impurity that can act as an electron donor in oxide semiconductors. However, if a large amount of hydrogen is contained in an oxide semiconductor, the oxide semiconductor becomes n-type. In this way, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. As a result, the on / off ratio of the transistor cannot be sufficiently obtained. Therefore, in this specification, the term "high-purity oxide semiconductor" refers to an oxide semiconductor in which hydrogen is It refers to an intrinsic or substantially intrinsic semiconductor that has been reduced to the minimum extent possible. An example of a compound semiconductor is one containing hydrogen at a concentration of at least 5×10 19 / cm 3 Below is Preferably 5 x 10 18 / cm 3 Less than 5 × 10, more preferably 17 / cm 3 Below Below, or 1×10 16 / cm 3 The carrier concentration is less than But 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, preferably is 1 x 10 11 / cm 3 Less than or equal to 6.0 x 10 10 / cm 3 oxide semiconductors that are less than The film is used for a channel formation region of a transistor. Concentration measurement is performed using secondary ion mass spectrometry (SIMS). This can be done using spectroscopy.

[0047] The energy gap of the oxide semiconductor layer 103 is 2 eV or more, preferably 2.5 eV or more. eV or more, more preferably 3 eV or more.

[0048] In this way, the high conductivity obtained by thoroughly removing hydrogen contained in the oxide semiconductor layer By using a high-purity oxide semiconductor layer for a channel formation region of a transistor, Extremely small transistors can be provided.

[0049] For example, a transistor using a high-purity oxide semiconductor layer has a channel length of 3 μm and a channel width of 1 μm. Even when the width is 10 mm, the gate When the gate voltage is in the range of -5V to -20V (off state), the drain current is 1×10 -1 3 It acts to keep it below A.

[0050] Here, the characteristics of a transistor including a high-purity oxide semiconductor layer are shown in FIGS. 27 will be used for the following explanation. In the following explanation, an ideal situation will be assumed for ease of understanding. The following explanation is based on the actual situation and may not reflect all of the information. It should be noted that this is merely a consideration and does not affect the validity of the invention.

[0051] FIG. 21 shows a source-drain band of a transistor using a high-purity oxide semiconductor layer. FIG. 1 is a diagram showing the structure of an oxide semiconductor. The Fermi level of a highly purified oxide semiconductor is higher than that of an ideal oxide semiconductor. In the oxide semiconductor with reduced hydrogen concentration, the minority carrier The electrons (holes in this case) are zero or very close to zero.

[0052] In this case, the work function is φ m , the electron affinity of the oxide semiconductor is χ, and the thermal equilibrium state of the oxide semiconductor is The carrier density (electron density) in the N d , the effective density of states in the conduction band of the oxide semiconductor is N c Then, the condition for the band structure to be flat at the metal-oxide semiconductor interface is φ m =χ-V t ln(N d / N c )

[0053] where V t =k b T / q and k b : Boltzmann constant, T: temperature, q: elementary charge This equation φ m =χ-V t ln(N d / N c ) is the boundary, and if the right side is large, Here, φ m =χ, the Fermi level of the electrode metal at the junction surface The level of the conduction band of the oxide semiconductor matches the band gap of the oxide semiconductor. 05 eV, electron affinity 4.3 eV, intrinsic state (carrier density approx. 1 × 10 -7 / cm 3 )in Assuming that the source and drain electrodes are titanium (Ti) with a work function of 4.3 eV. When using the ion beam, no barrier is formed for electrons, as shown in FIG.

[0054] Figure 22 shows the results of applying a positive voltage to the drain side of a transistor using an oxide semiconductor. Since oxide semiconductors have a large band gap, they can be highly purified and The intrinsic carrier density of an intrinsic or substantially intrinsic oxide semiconductor is zero or very close to zero. However, when a positive voltage is applied to the gate and a voltage is applied between the source and drain, If this is the case, it will be understood that carriers (electrons) can be injected from the source side and flow to the drain side. can be.

[0055] Figure 23(A) shows the energy band diagram of the MOS structure when the gate voltage is positive. The figure shows a transistor using an oxide semiconductor. E represents a gate electrode, GI represents a gate insulating film, and OS represents an oxide semiconductor. In this case, since there are almost no thermally excited carriers in the highly purified oxide semiconductor, However, as shown in Figure 22, carriers are not accumulated near the gate insulating film. The injected carriers can propagate through the

[0056] FIG. 23(B) is an energy band diagram of the MOS structure when the gate voltage is made negative. , and a transistor using an oxide semiconductor are shown. Since the number of carriers (holes) is essentially zero, the current between the source and drain is close to zero. The value is close to

[0057] FIG. 24 shows the band diagram of a transistor using silicon semiconductor. The intrinsic carrier density of silicon semiconductors is 1.45 x 10 10 / cm 3 (300K) at room temperature This is because thermally excited carriers exist even at room temperature. In practice, silicon doped with impurities such as phosphorus or boron is used. Since a silicon wafer is used, the actual 14 / cm 3 The above carriers are silicon In silicon semiconductors, the electrons contribute to the conduction between the source and drain. The band gap of silicon is 1.12 eV, so transistors using silicon semiconductors can be The off-state current varies greatly depending on the temperature.

[0058] In this way, simply applying a wide bandgap oxide semiconductor to a transistor Instead, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration is reduced to 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / c m 3 Less than or equal to 6.0 x 10 10 / cm 3 By making it less than The carriers thermally excited by the temperature are excluded, and only the carriers injected from the source side are used. This allows the transistor to operate with an off-state current of 1×10 -13 A The OFF current is reduced to below 100kJ / s, and the OFF current is extremely stable with almost no change due to temperature changes. A working transistor can be obtained.

[0059] Next, the measured values ​​of the off-state current in the evaluation element (also referred to as TEG) will be described below.

[0060] 200 transistors with L / W=3μm / 50μm are connected in parallel, and L / W=3μm / The initial characteristics of the 10,000 μm transistor are shown in Figure 25. Here, Vg is set to -20 V to The range is shown up to +5V. The top view is shown in Figure 26(A), and a part of it is enlarged. The top view is shown in Figure 26(B). The area surrounded by the dotted line in Figure 26(B) is where L / W = 3 μm / 5 The initial characteristics of the transistor are as follows: For the measurement, the substrate temperature was set to room temperature, and the source-drain voltage (hereafter referred to as drain voltage) The source-gate voltage (hereafter referred to as Vg) is set to 10V. The source-drain current (hereinafter referred to as drain) when the voltage (V) is changed from -20V to +20V The change characteristics of the current (referred to as "current or Id"), i.e., the Vg-Id characteristics, were measured.

[0061] As shown in FIG. 25, a transistor with a channel width W of 10000 μm has a Vd of 1 V and At 10V, the off-state current is 1×10 -13 [A] or less, and the measuring instrument (semiconductor parameter The resolution of the meter-analyzer (Agilent 4156C; Agilent) was 00fA) or less.

[0062] Next, a method for manufacturing the measured transistor will be described.

[0063] First, a silicon nitride layer is formed on a glass substrate as a base layer by a CVD method. A silicon oxynitride layer was formed on the silicon oxynitride layer by a sputtering method as a gate electrode. A tungsten layer was formed. The tungsten layer was then selectively etched to form a gate electrode. poles formed.

[0064] Next, a 100 nm thick silicon oxynitride film was formed on the gate electrode as a gate insulating layer by the CVD method. A base layer was formed.

[0065] Next, an In-Ga-Zn-O metal oxide substrate was deposited on the gate insulating layer by sputtering. Using a get (molar ratio of In2O3:Ga2O3:ZnO=1:1:2), a thickness of 5 Then, the oxide semiconductor layer was selectively etched. An island-shaped oxide semiconductor layer was formed.

[0066] Next, the oxide semiconductor layer was subjected to a first heating process in a clean oven under a nitrogen atmosphere at 450°C for 1 hour. The heat treatment was carried out.

[0067] Next, a titanium layer (150 nm thick) was formed on the oxide semiconductor layer as a source electrode and a drain electrode. The source and drain electrodes were selectively etched. The channel length L of one transistor is 3 μm and the channel width W is 50 μm. By arranging 200 pieces in parallel, the L / W was set to 3 μm / 10,000 μm.

[0068] Next, a protective insulating layer was formed by reactive sputtering so as to contact the oxide semiconductor layer. A silicon oxide layer was formed to a thickness of 300 nm. Here, the silicon oxide layer, which is a protective insulating layer, was selectively The silicon dioxide was then etched to form openings above the gate electrode, source electrode, and drain electrode. Thereafter, a second heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0069] Then, before measuring the Vg-Id characteristics, the device was heated at 150° C. for 10 hours.

[0070] Through the above steps, a bottom-gate transistor was manufactured.

[0071] As shown in Figure 25, the off-state current of the transistor is 1×10 -13 [A] is the level This is because the hydrogen concentration in the oxide semiconductor layer can be sufficiently reduced in the above manufacturing process. The hydrogen concentration in the oxide semiconductor layer is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 / cm 3 Below, or 1 x 1016 atoms / cm 3 The hydrogen concentration in the oxide semiconductor layer is measured as follows. Secondary ion mass spectrometry (SIMS) This is done using endoscopic imaging.

[0072] Although an example using an In-Ga-Zn-O oxide semiconductor has been shown, the present invention is not particularly limited. , other oxide semiconductor materials, for example, In-Sn-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O Sn-Zn-O, Al-Zn-O, In-O, Sn-O, Zn-O, etc. In addition, as the oxide semiconductor material, AlOx is mixed at 2.5 to 10 wt%. In-Al-Zn-O system containing 2.5 to 10 wt% of Si, and In-Zn-O system containing 2.5 to 10 wt% of Si. can also be used.

[0073] The carrier concentration of the oxide semiconductor layer measured by a carrier measurement device was 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / c m 3 Less than or equal to 6.0 x 10 10 / cm 3 That is, the carrier of the oxide semiconductor layer is less than The carrier concentration can be reduced to as close to zero as possible. For example, a MOS capacitor is fabricated, and the results of CV measurement of the MOS capacitor (CV One method is to evaluate the characteristics.

[0074] In addition, the channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. In this case, the operating speed of the circuit can be increased and the off-current value is extremely small, so It is also possible to reduce power consumption.

[0075] Note that when the transistor is off, the oxide semiconductor layer is considered to be an insulator in the circuit design. This can be done.

[0076] Next, the temperature characteristics of the off-state current of the transistor manufactured in this embodiment were evaluated. The temperature characteristics are determined by taking into consideration the environmental resistance of the final product in which the transistor is used and maintaining its performance. Naturally, the smaller the amount of change, the better, as it increases the degree of freedom in product design. .

[0077] The temperature characteristics are measured using a thermostatic chamber at -30, 0, 25, 40, 60, 80, 100, and 12 The substrate on which the transistor was formed was kept at a constant temperature of 60°C. The Vg-Id characteristics were obtained by varying the gate voltage from -20V to +20V.

[0078] Figure 27(A) shows the Vg-Id characteristics measured at each of the above temperatures, overlaid. The area of ​​the off-state current surrounded by the dotted line is shown enlarged in FIG. 27(B). The curve on the right indicated by the arrow is taken at -30℃, and the curve on the left is taken at 120℃. The obtained curve is located between these two curves. The on-current has almost no temperature dependence. As is clear from the enlarged view of Figure 27(B), the off-state current is The resolution of the measuring instrument is close to 1×10 at all temperatures except for the -12 [A] or below In other words, even at a high temperature of 120°C, the off-state current is 1× 10 -12 [A] or less is maintained, and the channel width W is 10,000 μm. Then, 1×10 -16 [A / μm] or less, which shows that the off-state current is extremely small. .

[0079] A transistor using a highly purified oxide semiconductor (purified OS) This is because the temperature dependence of the current is almost nonexistent, as shown in the band diagram of Figure 21. By purifying the conductor, the conductivity type approaches the intrinsic type and the Fermi level Since it is located in the center of the forbidden band, it can be said that it does not show temperature dependence. The energy gap of the semiconductor is 3 eV or more, and the number of thermally excited carriers is extremely low. Also, since the source and drain regions are in a degenerate state, the temperature This is the reason why the dependence does not appear. The transistor operates by Most of the charge transport is due to carriers injected into the nitride semiconductor, and the carrier density is temperature-dependent. This explains the above characteristic (no temperature dependence of off-current).

[0080] As mentioned above, the channel width W of the transistor is 1 × 10 4 The channel length is 3 μm. Even with a device with a size of 10 μm, the off-state current is -13 A or less, and the subthreshold swing Excellent electrical characteristics with a switching value (S value) of 0.1V / dec. (gate insulating film thickness 100nm) In this way, the oxide semiconductor is highly purified to minimize the amount of impurities contained therein. This makes it possible to improve the operation of the transistor. The transistor having the nitride semiconductor layer has an off-state current of 10 aA per 1 μm of channel width. / μm(1×10 -17 A / μm) or less, and further, 1aA / μm (1×10 - 18 A / μm) or less. By using a transistor with an extremely low current value as the first transistor 6401, This allows the retention time of electrical signals such as video signals to be extended. The time is 10 seconds or more, preferably 30 seconds or more, and more preferably 1 minute or more but less than 10 minutes. By increasing the interval between writes, the effect of suppressing power consumption can be increased.

[0081] On the other hand, for example, in a transistor using low-temperature polysilicon, the off-current is 1×10 -1 2 Therefore, the oxide semiconductor In transistors having a low-temperature polysilicon structure, the retention is higher than in transistors with low-temperature polysilicon. When the capacitance is the same (about 0.1 pF), the voltage retention period is 10 5 Stretch it out to about twice its size. In addition, in the case of a transistor having amorphous silicon, the channel width is 1 The off-state current per μm is 1×10 -13 A / μm or more. Therefore, the retention capacity is When the capacitance is the same (about 0.1 pF), the transistor using a high-purity oxide semiconductor has a higher capacitance. Compared to transistors using amorphous silicon, the voltage retention period is 10 4 More than double It can be stretched out.

[0082] As an example, a pixel with a transistor using low-temperature polysilicon can display 60 frames per second. This is the same for still images. Similarly, if the rate is reduced (the interval between writes is extended), the voltage of the pixel decreases and the display On the other hand, when a transistor including the above-described oxide semiconductor layer is used, In this case, the off-state current is small, so the retention period for one signal write is 10 5 Double 1600 Even with a small number of image signal writes, the static image on the display can be displayed in approximately 10 seconds. It is possible to display still images. Since the retention period can be extended, it is particularly useful when displaying still images. For example, the frequency of writing signals can be reduced when displaying a single still image. The number of times that the pixels are written during a period (about 1600 seconds) is When using a transistor, 10 5 On the other hand, the oxide semiconductor layer When a transistor having such a configuration is used, it is possible to reduce the number of times to one.

[0083] Figure 4 shows the relationship between the write period and the hold period (also called one frame period) in the display area. In FIG. 4, periods 251 and 252 correspond to the retention periods, and periods 261 and The period 262 corresponds to the period for writing to the display portion. Transistors can have a long retention period, which is particularly useful when displaying still images. This significantly reduces the number of times the pixel is written, resulting in fewer display changes. When displaying still images or the like, it is possible to reduce power consumption.

[0084] In addition, in the case of still image display, the voltage applied to the gate of the driving transistor during the holding period is Taking into consideration the voltage retention rate of the driving transistor, a refresh operation may be performed as needed. The voltage value (initial value) immediately after writing a signal to the gate of the The refresh operation can be performed when the voltage drops to a predetermined level. It is preferable to set the pressure so that flickering is not noticeable compared to the initial value. If the display object is a video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. It is preferable to perform a refresh operation (rewrite) every time the display object If the value is a character, the reset is performed every time the value is 10% lower than the initial value, preferably 3% lower. A fresh operation (rewrite) is preferable.

[0085] Next, as an example of a method for driving the light emitting element 6404, a method for performing analog gray scale driving will be described. The gate of the second transistor 6402 is connected to the forward voltage of the light emitting element 6404 plus the voltage of the second transistor 6403. A voltage equal to or higher than the Vth of the transistor 6402 is applied. The voltage refers to the voltage required to achieve a desired brightness, and includes at least the forward threshold voltage. For example, a video signal (image signal) that causes the second transistor 6402 to operate in a saturation region By inputting the current, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is set to the second transistor 6402. It is recommended to set the potential higher than the gate potential of the transistor 6402. By making the video signal analog, A current corresponding to a video signal is passed through the light emitting element 6404, and analog gray scale driving can be performed. do.

[0086] In addition, the voltage input voltage driving method allows for area gradation display using multiple pixels and for displaying different luminescent colors. Color representation by combining multiple pixels (e.g., R, G, B) (e.g., R+G, G In the case of a voltage input voltage driving method, the second The gate of the transistor 6402 is connected to the second transistor 6402 so that the second transistor 6402 is turned on sufficiently. In other words, the second transistor 64 is input with a signal that can be in either one of two states: on or off. The second transistor 6402 is operated in the linear region. In order to achieve this, the voltage of the power supply line 6407 is set lower than the gate potential of the second transistor 6402. Specifically, the threshold voltage of the second transistor 6402 is set to the potential of the power supply line. A voltage signal that gives a potential equal to or greater than the sum of the voltages may be input to the signal line 6405 .

[0087] In addition, whether the light emitting element 6404 is driven by analog gradation or by voltage input voltage, The off current of the switching transistor 6401 is, for example, 1×10 -16 Suppressed to below A Therefore, the gate potential of the second transistor 6402 is held for a long period. Therefore, even if the number of times of writing image signals is small, still images can be displayed on the display unit. This reduces the frequency of writing signals, which leads to lower power consumption. The pixel configuration shown in FIG. 2 is not limited to this. For example, a new pixel configuration may be added to the pixel shown in FIG. Switches, resistors, capacitors, transistors, logic circuits, etc. may be added.

[0088] In particular, an example of a light-emitting element is a light-emitting element that utilizes electroluminescence. The light-emitting element that uses electroluminescence is either an organic compound or Generally, the former is an organic EL element, and the latter is an inorganic EL element. It is called the L element.

[0089] An organic EL element consists of a pair of electrodes (anode and cathode) and an organic compound layer between the electrodes. The potential of the anode is made higher than the potential of the cathode, and the layer containing the organic compound is Holes are injected from the cathode and electrons are injected from the cathode. The electrons and holes (carriers) contain organic compounds. When they recombine in the layer, they emit light.

[0090] Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements are made of a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor- The thin-film inorganic EL element is an acceptor recombination type luminescence element. The luminescent layer is sandwiched between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner-shell electron transition of the metal ion. This is the localized light emission that is utilized.

[0091] In this embodiment, an organic EL element is used as the light-emitting element. The present invention is not limited to this configuration. It is also possible to use

[0092] Next, a cross-sectional structure of a display device having a light-emitting element will be described with reference to FIG. 5(A), 5(B), and 5(C) are driving transistors 7001 and 7011. The transistor 7021 may be a transistor using a high-purity oxide semiconductor layer, or a silicon In this embodiment, the driving transistor 7 When a high-purity oxide semiconductor layer was used as the active layer of 001, 7011, and 7021, I will explain.

[0093] The light-emitting element exemplified in this embodiment has a pair of electrodes (a first electrode and a second electrode) between which a light-emitting element is formed. The first electrode and the second electrode are sandwiched between the EL layer (electroluminescence layer). One of the electrodes functions as an anode and the other functions as a cathode.

[0094] The material used for the anode is a metal or alloy with a large work function (specifically, 4.0 eV or more). , conductive compounds, or mixtures thereof are preferred. Specifically, indium oxide-oxide containing tin oxide (ITO: Indium Tin Oxide), silicon or silicon oxide Indium oxide-tin oxide and indium oxide-zinc oxide (IZO) Zinc Oxide, tungsten oxide and zinc oxide containing indium oxide (I Other examples include gold (Au), platinum (Pt), nickel (Ni), and titanium. W, chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co) , copper (Cu), palladium (Pd), or nitrides of metallic materials (e.g., titanium nitride), etc. Examples include:

[0095] The material used for the cathode is a metal or alloy with a small work function (specifically, 3.8 eV or less). , an electrically conductive compound, or a mixture thereof is preferred. Elements belonging to Group 1 or 2, such as lithium (Li) and cesium (Cs), Potassium metal, magnesium (Mg), calcium (Ca), strontium (Sr) and other Alkali metals or alkaline earth metals are also included. For example, MgAg, AlLi) can also be used. Rare earth metals such as terbium (Yb) or alloys containing rare earth metals can also be used. . In addition, when an electron injection layer in contact with the second electrode is provided as part of the EL layer, a large work function is required. Various conductive materials, such as Al, Ag, and ITO, can be used as the second electrode, regardless of their size. These conductive materials can be applied by sputtering, inkjet printing, spin coating, etc. It is possible to form a film using the above.

[0096] The EL layer can be configured as a single layer structure, but is usually configured as a laminated layer structure. The laminated structure of the EL layer is not particularly limited, and may be a layer containing a substance with high electron transport properties (electron transport layer) or a layer containing a substance with high hole transporting properties (hole transport layer), a layer containing a substance with high electron injection properties layer (electron injection layer), layer containing a material with high hole injection properties (hole injection layer), bipolar (electron and a layer containing a material with high hole transporting properties (a material with high hole transporting properties), a layer containing a light-emitting material (a light-emitting layer), etc. For example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron It can be constructed by appropriately combining a charge injection layer and a charge generating layer. A configuration in which a plurality of EL layers separated by intermediate layers are provided between a first electrode and a second electrode. Good too.

[0097] In order to extract light from the light emitting element, at least one of the first electrode and the second electrode is The light-emitting element formed on the substrate is formed of a conductive film having a light-transmitting property. When light emitting elements are classified according to the direction of attachment, they are taken out from the surface of the substrate on which the light emitting element is formed. Surface emission, bottom emission, where light is extracted from the surface opposite to the side where the light emitting element is formed on the substrate, There are three typical double-sided injection methods, where the light is extracted from both the side where the element is formed and the opposite side. The present invention can be applied to any light-emitting element with any emission structure. .

[0098] When an EL layer is laminated on the first electrode, the periphery of the first electrode is covered with a partition wall. The film may be an organic resin film such as polyimide, acrylic resin, polyamide, or epoxy resin, or an inorganic It may be formed using an insulating film or organic polysiloxane, but for example, a photosensitive resin material may be used. When a photosensitive resin material is used, the opening of the partition wall is preferably The sidewalls of the wafer become sloped surfaces with a continuous curvature, and the process of forming a resist mask can be eliminated. Cut.

[0099] A color filter may be formed between the substrate and the light emitting element. The inkjet method and other droplet ejection methods, printing methods, and etching using photolithography technology are used. They may be formed by a coating method or the like.

[0100] In addition, when an overcoat layer is formed on the color filter and then a protective insulating layer is formed, By providing an overcoat layer, the unevenness caused by the color filter can be smoothed. Forming a protective insulating film can prevent impurities from diffusing from the color filter to the light-emitting element. do.

[0101] A light emitting element is formed on the protective insulating layer, overcoat layer, and insulating layer on the transistor. When forming the transistor, the protective insulating layer, the overcoat layer, and the insulating layer are penetrated and the source of the transistor is formed. A contact hole is formed that reaches the electrode or the drain electrode. If the holes are laid out and formed at positions overlapping the partition walls, the reduction in the aperture ratio can be suppressed. Therefore, it is preferable.

[0102] Next, an example of the configuration of a pixel having a light emitting element with a bottom emission structure will be described. A cross-sectional view of a cut surface including a driving transistor 7011 and a light-emitting element 7012 is shown in FIG. ) shown.

[0103] The driving transistor 7011 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate electrode has a drain electrode, a gate insulating layer, and a gate electrode. A wiring layer is provided to electrically connect the two.

[0104] In addition, an insulating layer 7031 is formed to cover the driving transistor 7011, and the insulating layer 703 A color filter 7033 having an opening is provided on the conductive film 1. 7017 is an overcoat layer 7034 formed to cover the color filter 7033 and It is formed on the protective insulating layer 7035. The electrode and the conductive film 7017 are formed by an overcoat layer 7034, a protective insulating layer 7035, and an insulating layer The conductive film 7017 is electrically connected to the conductive film 7031 through an opening formed therein. A first electrode 7013 of the light-emitting element 7012 is provided in contact with the first electrode 7013 .

[0105] The light-emitting element 7012 has an EL layer 7014 between a first electrode 7013 and a second electrode 7015. It is sandwiched between the two.

[0106] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), A film made of indium zinc oxide, indium tin oxide with added silicon oxide, etc. may be used. This can be done.

[0107] Here, the case where the first electrode 7013 of the light-emitting element 7012 is used as a cathode will be described. When the first electrode 7013 is used as a cathode, a metal with a small work function is suitable. In FIG. 5A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through (preferably 5 For example, an aluminum film or M film having a thickness of 20 nm is used. A g-Ag alloy film is used for the first electrode 7013 .

[0108] After the light-transmitting conductive film and the aluminum film are stacked, selective etching is performed. A light-transmitting conductive film 7017 and a first electrode 7013 may be formed in this case. Etching can be preferably performed using the same mask.

[0109] The second electrode 7015 formed on the EL layer 7014 is made of a material having a large work function. A shielding film 7016, for example, a metal that blocks light, is formed on the second electrode 7015. In this embodiment, the second electrode 7015 is made of an ITO film. and a Ti film is used as the shielding film 7016 .

[0110] The color filter 7033 is covered with an overcoat layer 7034, and a protective insulating layer In FIG. 5(A), the overcoat layer 7034 is shown as being thin. However, the overcoat layer 7034 flattens the unevenness caused by the color filter 7033. There are.

[0111] Also, a layer formed on the overcoat layer 7034 and the protective insulating layer 7035 and a drain The contact hole reaching the electrode 7030 is arranged at a position overlapping with the partition wall 7019. .

[0112] In the case of the pixel structure shown in FIG. 5A, light emitted from the light-emitting element 7012 is reflected by the light emitting element 7012 as shown by the arrow. The light is then emitted to the first electrode 7013 side, passes through the color filter 7033, and exits the display device. do.

[0113] The gate electrode, source electrode, and drain electrode of the driving transistor 7011 are A light-transmitting conductive film is used as a channel formation region of the driving transistor 7011. It is preferable to use a light-transmitting high-purity oxide semiconductor layer. ), the light emitted from the light emitting element 7012 passes through the color filter 7033. The light is not only emitted through the driving transistor 7011 but also passes through the driving transistor 7011. Furthermore, the channel of the driving transistor 7011 can be By using a light-transmitting high-purity oxide semiconductor layer as a formation region, The off-current of the transistor 7011 can be reduced to an extremely low level, so it is possible to maintain a long life compared to conventional transistors. Therefore, the area of ​​the electrode for forming the capacitance can be reduced. can be improved.

[0114] Next, the configuration of a pixel having a light-emitting element with a dual emission structure will be described. FIG. 5B shows a cross-sectional view of a cut surface including a driving transistor 7021 and a light-emitting element 7022. vinegar.

[0115] The driving transistor 7021 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate electrode has a drain electrode, a gate insulating layer, and a gate electrode. A wiring layer is provided to electrically connect the two.

[0116] An insulating layer 7041 is formed to cover the driving transistor 7021, and the insulating layer 704 A color filter 7043 having an opening is provided on the conductive film 1. 7027 is an overcoat layer 7044 formed to cover the color filter 7043 and It is formed on the insulating layer 7045. The drain electrode of the driving transistor 7021 The conductive film 7027 is formed by an overcoat layer 7044, an insulating layer 7045, and an insulating layer 7041. The light-emitting element is electrically connected to the conductive film 7027 through an opening formed in the conductive film 7027. A first electrode 7023 of the electrode 7022 is provided in contact therewith.

[0117] The light-emitting element 7022 has an EL layer 7024 between a first electrode 7023 and a second electrode 7025. It is sandwiched between the two.

[0118] Here, the case where the first electrode 7023 of the light-emitting element 7022 is used as a cathode will be described. Note that the light-transmitting conductive film 7027 is the same as the conductive film 7017 shown in FIG. The first electrode 7023 may be formed in the same manner as the first electrode 7013 shown in FIG. The EL layer 7024 may be formed in the same manner as the EL layer 7014 shown in FIG. Therefore, detailed description will be omitted here.

[0119] The second electrode 7025 formed on the EL layer 7024 functions as an anode here. A material with a large work function, for example, a transparent conductive material such as ITO, IZO, or ZnO, is preferred. In this embodiment, the second electrode 7025 is formed of ITO.

[0120] The color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are , the color filter 7033 and the overcoat layer 703 included in the pixel illustrated in FIG. 4 and the protective insulating layer 7035 may be formed in a similar manner.

[0121] In the case of the element structure shown in FIG. 5B, light emitted from the light-emitting element 7022 is As shown in the figure, the light is emitted to both the first electrode 7023 side and the second electrode 7025 side, and the first electrode 70 The light from the 23 side passes through the color filter 7043 and exits the display device.

[0122] In FIG. 5B, a light-transmitting electrode is used as a gate electrode, a source electrode, and a drain electrode. 7 shows an example in which the driving transistor 7021 is formed using a conductive film having a thickness of 1000 . A part of the light emitted from the element 7022 is reflected by the color filter 7043 and the driving transistor It passes through 7021 and is ejected.

[0123] Also, a layer formed on the overcoat layer 7044 and the protective insulating layer 7045 and a drain The contact hole reaching the electrode 7040 is arranged at a position overlapping with the partition wall 7029. The layout is such that the contact hole reaching the drain electrode and the partition wall 7029 overlap each other. By doing so, the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side are made almost the same. It is possible.

[0124] However, if both display surfaces of a light-emitting element with a dual emission structure are used for full color display, Since the light from the electrode 7025 side does not pass through the color filter 7043, a separate color filter is required. It is preferable that a sealing substrate having a filter be provided above the second electrode 7025 .

[0125] Next, the structure of a pixel having a light-emitting element with a top emission structure will be described. FIG. 5C shows a cross-sectional view of a cut surface including a driving transistor 7001 and a light-emitting element 7002. vinegar.

[0126] The driving transistor 7001 includes an insulating layer, an oxide semiconductor layer, a source electrode, and a The gate electrode has a drain electrode, a gate insulating layer, and a gate electrode. A wiring layer is provided to electrically connect the two.

[0127] In addition, an insulating layer 7051 is formed to cover the driving transistor 7001, and an insulating layer 705 An insulating layer 7053 having an opening is provided on the first electrode 7003. It is formed on an insulating layer 7055 formed to cover the driving transistor 7053. The drain electrode and the first electrode 7003 of the gate electrode 7001 are connected to the insulating layer 7055 and the insulating layer 7060. The electrical connection is made through an opening formed in 51.

[0128] The insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene resin, or poly Resin materials such as amide and epoxy can be used. low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor In addition, the insulating film formed by these materials can be used in multiple layers. The insulating layer 7053 may be formed by stacking layers. Depending on the material, methods such as sputtering, SOG, spin coating, dipping, and sputtering may be used. Ray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), A roller knife, roll coater, curtain coater, knife coater, etc. can be used. By forming the insulating layer 7053, for example, unevenness caused by the driving transistor can be flattened. In addition, a layer formed on the insulating layer 7055 and the insulating layer 7053 and the drain electrode 7 The contact hole reaching 050 is arranged at a position overlapping with the partition wall 7009 .

[0129] The light-emitting element 7002 has an EL layer 7004 between a first electrode 7003 and a second electrode 7005. In the light-emitting element 7002 illustrated in FIG. 5C, the first electrode 700 The case where 3 is used as a cathode will be explained.

[0130] The first electrode 7003 may be made of the same material as the first electrode 7013 shown in FIG. However, in the light-emitting element having a top emission structure shown in FIG. 5C, the first electrode 7003 is transparent. It is preferable that the electrode does not have optical transparency and has high reflectivity. By using such an electrode, the light extraction efficiency can be improved.

[0131] The first electrode 7003 is, for example, an aluminum film or a film containing aluminum as a main component. An alloy film or an aluminum film with a titanium film laminated thereon is preferable. In this example, a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order is used as the first electrode 7003. do.

[0132] The EL layer 7004 may be formed in the same manner as the EL layer 7014 shown in FIG. The second electrode 7005 may be formed in the same manner as the second electrode 7025 shown in FIG. 5(B). Therefore, a detailed description will be omitted here.

[0133] In the case of the element structure shown in FIG. 5C, light emitted from the light emitting element 7002 is The light is emitted toward the second electrode 7005 as shown.

[0134] When full color display is performed using the structure of FIG. 5C, for example, the light emitting element 7002 is One adjacent light-emitting element is a red light-emitting element and the other is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element was added to create a total of four types of light-emitting elements. A light-emitting display device capable of full-color display may be manufactured.

[0135] In addition, all of the light emitting elements arranged in the structure of FIG. 5(C) are white light emitting elements. A sealing substrate having a color filter or the like is disposed above each light-emitting element including the element 7002. A light emitting display device capable of full color display may be manufactured by using a structure in which the light emitting element is a monochromatic element such as white. By forming a material that emits light and combining it with a color filter or color conversion layer, full color -Display can be performed.

[0136] If necessary, an optical film such as a circular polarizing plate may be provided.

[0137] Next, the appearance and The cross section will be explained with reference to FIG. 6. FIG. 6(A) shows a cross section of a transistor formed on a first substrate. A plan view of a panel in which a transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 6(B) corresponds to a cross-sectional view taken along line HI in FIG. 6(A).

[0138] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504a are provided on a first substrate 4501. A sealant 450 is applied to surround the gate driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. 5. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 4 504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The pixel portion 4502 and the signal line 4507 are sealed together. The driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are exposed to the outside air. Highly airtight and low outgassing protective film (lamination film, purple) It is preferable to package (enclose) the device in a UV-curable resin film or a cover material.

[0139] In addition, a pixel portion 4502 and a signal line driver circuit 4503a are provided over the first substrate 4501. , 4503b, and the scanning line driver circuits 4504a, 4504b have a plurality of transistors. In FIG. 6B, a transistor 4510 included in a pixel portion 4502 and a signal line driver The transistor 4509 included in the driving circuit 4503a is shown as an example. Insulating layers 4542-4545 are provided on the insulating layers 4540-4545. The source voltage of the transistor 4510 is connected to the contact hole formed in the 2-4545. The electrode or drain electrode 4848 and the first electrode layer 4517 of the light emitting element 4511 are electrically connected. It continues.

[0140] In this embodiment, the transistor 4509 included in the signal line driver circuit 4503a and a transistor 4510 included in the pixel portion 4502, The transistors having the following structures are used.

[0141] The oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4542. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing it in a position that overlaps with the channel formation region of the compound semiconductor layer, Change in threshold voltage of transistor 4509 before and after bias and temperature stress test In this specification, the BT stress test (bias-temperature stress test) The stress test is a test in which a high gate voltage is applied to a transistor in a high-temperature atmosphere. In addition, the conductive layer 4540 has a potential equal to that of the gate electrode of the transistor 4509. It may be the same or different and may function as a second gate electrode. The potential of the conductive layer 4540 may be GND, 0 V, or may be in a floating state.

[0142] The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer 4512, a second electrode The light-emitting element 4511 has a stacked structure of the layer 4513, but is not limited to the structure shown here. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the extracted light.

[0143] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form the sidewalls of the partition walls 4520 with a continuous curvature. It is preferable to form it so as to have a flat surface.

[0144] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it is completed or not.

[0145] The second electrode is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511. A protective film may be formed over the layer 4513 and the partition wall 4520. As the protective film, a silicon nitride film , a silicon nitride oxide film, a DLC film, etc. can be formed.

[0146] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504 b, or various signals and potentials given to the pixel portion 4502 are It is supplied by 8b.

[0147] The connection terminal electrode 4515 has the same conductive property as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from a film. The source electrode and the drain electrode are formed from the same conductive film.

[0148] The connection terminal electrode 4515 is formed by connecting a terminal of the FPC 4518a and an anisotropic conductive film 4519. are electrically connected via

[0149] The substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as aluminum is used.

[0150] In addition to inert gases such as nitrogen and argon, UV-curable resins can also be used as filler 4507. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0151] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0152] Note that the present invention is not limited to the configuration shown in Fig. 6. That is, the signal line driver circuit 4503a, 4503b and the scanning line driver circuits 4504a and 4504b are individually mounted on a separately prepared substrate. The driving circuit may be implemented using a crystalline semiconductor film or a polycrystalline semiconductor film. Alternatively, only or a part of the signal line driver circuit, or only or a part of the scanning line driver circuit may be separated. The circuit may be implemented in a manner similar to that described above.

[0153] (Embodiment 2) In this embodiment, a configuration for further reducing the power consumption of the display device will be described. In addition to suppressing power consumption in the pixel section of the display device, A configuration for reducing power consumption in the above will be described.

[0154] 7 shows an example of a block diagram of a display device. However, the present invention is not limited to the configuration of FIG. However, it is not limited to the above.

[0155] The display device 1000 shown in FIG. 7 includes a display panel 1001, a signal generating circuit 1002, a memory circuit The circuit 1003, the comparator circuit 1004, the selector circuit 1005, and the display control circuit 1006 are also included. The display panel 1001 also includes a driver circuit section 1007 and a pixel section 1008. The circuit portion 1007 includes a gate line driver circuit 1009A and a signal line driver circuit 1009B. The gate line driver circuit 1009A and the signal line driver circuit 1009B have a plurality of pixels. It has a function of driving the pixel portion 1008 .

[0156] The transistors described in Embodiment Mode 1 are used for forming the pixel portion 1008. That is, as a switching transistor, an n-channel transistor having a high-purity oxide semiconductor layer is used. The driving transistor is a transistor having a high purity oxide semiconductor layer. A structure using a silicon layer may be used. In this case, the driving transistor is also an n-channel transistor having a high-purity oxide semiconductor layer. The case where a transistor is applied will be described.

[0157] In this embodiment, a switch, which is one of the transistors constituting the pixel portion 1008, As a transistor for switching, an n-channel transistor having a high-purity oxide semiconductor layer is used. By using a memory, it is possible to extend the time for which data such as image signals are held. Therefore, when displaying a still image or the like, the frequency of writing signals can be reduced. This makes it possible to reduce the power consumption of the display device.

[0158] Furthermore, in this embodiment, when a still image is displayed, all signals included in the pixel unit are and / or all the scanning lines. By operating the pixel circuitry in this manner, it is possible to reduce power consumption not only in the pixel portion but also in the driver circuit portion. That is, during the period when the display device displays a still image, all the signals included in the pixel unit There is a period during which the output of signals supplied to the scanning lines and / or all scanning lines is stopped. In the embodiment, as a configuration for realizing low power consumption of the drive circuit unit, 1000 is a signal generating circuit 1002, a memory circuit 1003, a comparison circuit 1004, a selection circuit 10 05, and a display control circuit 1006.

[0159] The signal generating circuit 1002 includes a gate line driving circuit 1009A and a signal line driving circuit 1009B. It has the function of generating the signal (control signal) required to drive B. The circuit 1002 outputs a control signal to the drive circuit unit 1007 via wiring. The image signal (also called a video voltage, a video signal, or video data) is stored in the memory circuit 100 via the In other words, the signal generating circuit 1002 has a function of outputting the signal to the driving circuit section 1007. and a circuit for generating and outputting an image signal to be supplied to the pixel unit. is.

[0160] Specifically, the signal generating circuit 1002 outputs a control signal to the gate line driving circuit 1009A. and a high power supply potential Vdd and a low power supply potential Vss which are power supply voltages to the signal line driver circuit 1009B. and a start pulse SP for the gate line driving circuit is supplied to the gate line driving circuit 1009A. , a clock signal CK is supplied to the signal line driver circuit 1009B. The signal generating circuit 1002 also supplies a moving image signal SP and a clock signal CK. Alternatively, the image signal Data for displaying a still image is output to the memory circuit 1003 .

[0161] In addition, moving images are created by switching between multiple time-divided images at high speed. Specifically, it refers to an image that is recognized as a moving image by the human eye 60 times per second (60 By switching images more than one frame, the human eye perceives it as a moving image with less flicker. On the other hand, still images are different from moving images in that they are composed of multiple frames. Although it operates by switching multiple images time-divided over a period at high speed, it is For example, the image signal does not change between the nth frame and the (n+1)th frame. This means that.

[0162] The signal generating circuit 1002 also has the function of generating an image signal, a latch signal, etc. The signal generating circuit 1002 may also include a gate line driving circuit 1009A and / or The signal line driver circuit 1009B is connected to the relay 1006 for stopping the output of the pulse signal of each driver circuit. The set signal and the Res signal may be output. The signal may be composed of multiple signals such as a first clock signal, a second clock signal, and a third clock signal. .

[0163] The high power supply potential Vdd is a potential higher than the reference potential, and the low power supply potential is a potential lower than the reference potential. The potential at which a transistor is at a high power supply potential and a low power supply potential is also called a potential at which a transistor is at a low power supply potential. It is desirable that the potential be such that it can operate.

[0164] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage, respectively. It is possible to do this.

[0165] In addition, the image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal. In the case of a signal, it is converted into a digital signal via an A / D converter or the like, and stored in the memory circuit 100. 3.

[0166] The memory circuit 1003 includes a plurality of frame memory circuits for storing image signals relating to a plurality of frames. The frame memory is, for example, a DRAM (Dynamic Random Access Memory). Random Access Memory), SRAM (Static Random The memory may be configured using a memory element such as a memory access memory (RAM).

[0167] The frame memory 1010 can store an image signal for each frame period. The number of frame memories is not particularly limited. The image signal of 010 is selectively read out by a comparison circuit 1004 and a selection circuit 1005. This is what is done.

[0168] The comparison circuit 1004 compares the image signals of successive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out the image signals, comparing them, and detecting the difference. When a difference is detected by the comparison of the image signals in the comparison circuit 1004, the difference is detected. On the other hand, the comparison circuit 1004 determines that the period of consecutive frames is a moving image. If no difference is detected by comparing the image signals of the two, the difference is In other words, the difference in the comparator circuit 1004 is By detecting the image signal of the successive frame periods, the image signal for displaying a moving image is converted into the image signal It is judged whether the signal is a video signal for displaying a still image or a still image. The difference obtained by the comparison is detected when it exceeds a certain level. It may be set so that it is determined that the

[0169] The selection circuit 1005 includes a plurality of switches, for example, switches formed of transistors. When the image signal for displaying a moving image is judged by detecting the difference in the comparison circuit, The image signal is selected from the frame memory 1010 in which the image signal is stored, and the display control circuit The comparison circuit 1004 outputs the image between the frames to the comparison circuit 1006. If no difference in the image signal is detected, the image displayed between successive frames is a still image. In this case, the display control circuit 100 controls the latter image signal during the consecutive frame periods. It is sufficient to configure it so that it does not output to 6.

[0170] The display control circuit 1006 receives an image signal, a high power supply potential Vdd, a low power supply potential Vss, a start Regarding the control signals of the pulse SP, the clock signal CK, and the reset signal Res, the drive circuit This is a circuit for switching on or off the supply to the comparison circuit 1007. If it is determined to be a moving image by 04, that is, if the difference in the image signal between consecutive frames is extracted In the display control circuit 1006, an image signal is supplied from a selection circuit 1005 to a display control circuit 1006. An image signal is supplied to a driving circuit unit 1007 via a display control circuit 1006. The signal is supplied to a drive circuit unit 1007 via a display control circuit 1006. The comparator circuit 1004 judges that it is a still image, that is, extracts the difference between the image signals during successive frames. If the image signal is not output, the image signal is not supplied from the selection circuit 1005, and the display control circuit 1 006, the image signal is not supplied to the driver circuit unit 1007. The display control circuit 1006 stops supplying the signal to 1007.

[0171] In addition, if the period of time that is determined to be a still image is short, the restriction will be applied. Of the control signals, the high power supply potential Vdd and the low power supply potential Vss may not be stopped. In this case, frequent stopping and restarting of the high power supply potential Vdd and the low power supply potential Vss can This is preferable because it can reduce the increase in power consumption that occurs when the power consumption is increased.

[0172] The image signal and the control signal are stopped when each pixel in the pixel unit 1008 can hold an image signal. It is desirable to supply the image signal again after the retention period of each pixel. In order to prevent this, the display control circuit 1006 is caused to resupply the image signal and control signal that it previously supplied. The configuration may be such that:

[0173] Note that supplying a signal means supplying a predetermined potential to a wiring. The supply of a predetermined potential to the wiring is stopped, and a wiring to which a predetermined fixed potential is supplied, for example, a low voltage wiring, is supplied. It means to electrically connect to the wiring to which the power supply potential Vss is supplied. The electrical connection with the wiring to which a predetermined potential is supplied is cut off, and the wiring is left in a floating state. cormorant.

[0174] As mentioned above, the video signal is compared to determine whether it is a moving image or a still image, and the clock signal and start By selectively restarting or stopping the supply of control signals such as pulses to the drive circuit, the drive The power consumption in the circuit section 1007 can be reduced.

[0175] Next, the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit section 1007 are An example of the configuration of the shift register that constitutes this is shown in FIG.

[0176] The shift register shown in FIG. 8A includes first pulse output circuits 10_1 to N-th pulse output circuits 10_2. The shift register shown in FIG. The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the A first clock signal CK1 is output from the first wiring 11, a second clock signal CK2 is output from the second wiring 12, and a third clock signal CK3 is output from the third wiring 13. The third wiring 13 transmits the third clock signal CK3, and the fourth wiring 14 transmits the fourth clock signal C. In the first pulse output circuit 10_1, a start signal K4 is supplied from the fifth wiring 15. The first start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the first pulse (called the previous signal OUT(n-1)(SR)) is input. The output circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages later. Similarly, in the n-th pulse output circuit 10_n in the second stage or later, the (n+2)-th pulse output circuit in the second stage or later The signal from the pulse output circuit 10_(n+2) (called the subsequent signal OUT(n+2)(SR)) Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or the stage two stages before. The first output signal (OUT(1)(SR) to OUT(N)) is input to the pulse output circuit. ) (SR)), a second output signal (OUT(1) to OUT(N)) input to another wiring, etc. As shown in FIG. 8(A), the last two stages of the shift register are Since the subsequent signal OUT(n+2)(SR) is not input, for example, a sixth A second start pulse SP2 is sent from the line 17, and a third start pulse SP is sent from the seventh line 18. Alternatively, a signal generated inside a separate shift register may be input. For example, the (N+1)th pulse output signal that does not contribute to the pulse output to the pixel unit may be used. A first pulse output circuit 10_(N+1) and a second pulse output circuit 10_(N+2) are provided (dummy The second start pulse (SP2) and the third start pulse (SP3) are sent from the dummy stage. A configuration may be adopted in which a signal equivalent to the pulse (SP3) is generated.

[0177] The first clock signal (CK1) to the fourth clock signal (CK4) are as shown in FIG. The first clock signal (C The fourth clock signal (CK1) to the fourth clock signal (CK4) are delayed by 1 / 4 cycle in order. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used. The clock signal CK controls the driving of the pulse output circuit. Depending on the route, it may be called GCK or SCK, but here we will explain it as CK.

[0178] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal The inverter has an input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 8(B)). .

[0179] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 8(A) and 8(B), for example, In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the third wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. It continues.

[0180] 8A and 8B, the first pulse output circuit 10_1 has a fourth input terminal A start pulse is input to the fifth input terminal 24, and a subsequent signal OUT(3)(SR) is output to the fifth input terminal 25. is input, and the first output signal OUT(1)(SR) is output from the first output terminal 26, The second output terminal 27 outputs the second output signal OUT(1).

[0181] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 8(C).

[0182] In FIG. 8C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor 39; The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the power supply. The second terminal is electrically connected to the first terminal of the ninth transistor 39. The third transistor 33 is electrically connected to the gate of the fourth transistor 34. The transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first The fourth transistor 34 has a first terminal electrically connected to the output terminal 26 of the power supply. The second terminal is electrically connected to the line 52 and the second terminal is electrically connected to the first output terminal 26 . The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal the gate of the first transistor 32 and the gate of the fourth transistor 34; The gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 One terminal is electrically connected to the power supply line 51, and the second terminal is connected to the gate and and the gate of the fourth transistor 34, the gate of which is connected to the fifth input terminal 25. The seventh transistor 37 has a first terminal electrically connected to the power supply line 51. the second terminal of the eighth transistor 38 is electrically connected to the second terminal of the eighth transistor 39, and the gate of the eighth transistor 39 is The eighth transistor 38 is electrically connected to the third input terminal 23. A gate of the second transistor 32 and a gate of the fourth transistor 34 are electrically connected to each other. The ninth transistor 39 is electrically connected to the second input terminal 22. , the first terminal is connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. , and the second terminal is electrically connected to the gate of the third transistor 33 and the gate of the tenth transistor The gate is electrically connected to the gate of the transistor 40 , and the gate is electrically connected to the power supply line 51 . The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal a terminal electrically connected to the second output terminal 27 and a gate of the ninth transistor 39; The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate is The gate of the fourth transistor 34 is electrically connected to the gate of the second transistor 32. do.

[0183] In FIG. 8C, the gate of the third transistor 33, the gate of the tenth transistor 40 The connection point between the gate and the second terminal of the ninth transistor 39 is a node NA. The gate of the second transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor the second terminal of the sixth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38 The connection point between the terminal and the gate of the eleventh transistor 41 is referred to as a node NB.

[0184] When the pulse output circuit in FIG. 8C is the first pulse output circuit 10_1, the first input A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP1 is input to the fourth input terminal 24, and a The second output terminal 26 receives the next stage signal OUT(3)(SR), and outputs the signal OUT(1)( SR) is output, and OUT(1) is output from the second output terminal 27.

[0185] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 9. When the shift register is a gate line driving circuit, 9, period 61 corresponds to the vertical blanking period, and period 62 corresponds to the gate selection period.

[0186] The driving circuit shown in Fig. 8 and Fig. 9 is fabricated using multiple n-channel transistors. In the dynamic circuit, when displaying still images and dynamic images, supply or stop of the potential of each wiring The procedure will be explained below.

[0187] First, when the operation of the drive circuit unit 1007 is stopped, the display control circuit 1006 The start pulse SP is stopped. Then, after the start pulse SP is stopped, the pulse output is After the clock signal CK reaches the final stage of the soft register, the clock signal CK is stopped. The high power supply potential Vdd and the low power supply potential Vss of the drive circuit are stopped (see FIG. 11(A)). When the operation of the display control circuit 1007 is to be resumed, the display control circuit 1006 first A high power supply potential Vdd and a low power supply potential Vss are supplied to the driver circuit portion 1007. The lock signal CK is supplied, and then the supply of the start pulse SP is resumed (see FIG. 11(B)). (see).

[0188] Next, we fabricated a multi-channel transistor using the examples shown in Figures 8 and 9. In the drive circuit, the operation of changing from a still image display to a moving image display, or the driving transistor The operation of rewriting the voltage applied to the gate of the For details of the procedure for supplying or stopping the potential of each wiring to the drive circuit unit, see Figure 28. 28 shows a wiring for supplying a high power supply potential (VDD) to the shift register. Wiring that supplies the low power supply potential (VSS), wiring that supplies the start pulse (SP), and Wiring for supplying the first clock signal (CK1) to wiring for supplying the fourth clock signal (CK4) 10 is a diagram showing a change in potential of a wiring before and after a frame period (T1).

[0189] In the display device of this embodiment, the drive circuit unit is constantly operating to display moving images and still images. Furthermore, the display of a still image can be performed without constantly operating the drive circuit for refresh operations. Therefore, as shown in FIG. 28, a high power supply is applied to the shift register. potential (VDD), the first clock signal (CK1) to the fourth clock signal (CK4), and The period during which control signals such as a start pulse and a start pulse are supplied, and the period during which no control signals are supplied are The period T1 shown in FIG. 28 is the period during which the control signal is supplied, i.e., the period during which the moving image is This corresponds to the period during which the image is displayed and the period during which the refresh operation is performed. corresponds to a period in which no control signal is supplied, that is, a period in which a still image is displayed.

[0190] In FIG. 28, the period during which the high power supply potential (VDD) is supplied is not limited to the period T1. 28. In FIG. 28, the first clock During the period in which the fourth clock signal (CK1) to the fourth clock signal (CK4) are supplied, the high power supply potential ( VDD) is supplied until the high power supply potential (VDD) is stopped. are.

[0191] As shown in FIG. 28, the first clock signal (CK1) to the fourth clock signal (CK2) are K4) is a high-potential signal before the start of period T1, and then a clock signal with a fixed period. After the period T1 is over, the clock signal starts oscillating as a low potential signal. The above configuration may be adopted.

[0192] As described above, in the display device of this embodiment, a high voltage is applied to the shift register during the period T2. potential (VDD), the first clock signal (CK1) to the fourth clock signal (CK4), and The supply of control signals such as a start pulse and a start pulse is stopped. During this time, the shift register operates by controlling the conduction or non-conduction of each transistor. The pulse signal output also stops. Therefore, the power consumed in the shift register, and reducing the power consumed in the pixel unit driven by the shift register. This makes it possible to:

[0193] Please note that the above refresh operation takes into consideration the possibility that the quality of the displayed still image may deteriorate. In the display device of this embodiment, the driving circuitry of each pixel is The high purity silicon dioxide mentioned above is used as a switching element to control the voltage applied to the gate of the transistor. This allows for extremely low off-state current. Therefore, the voltage applied to the gate of the driving transistor of each pixel can be reduced to It is possible to reduce voltage fluctuations. In other words, when displaying a still image, the operation of the shift register Even if the period of time during which the image is stopped is long, deterioration of the image quality can be reduced. , it is possible to maintain the quality of the displayed still image even if the period is 3 minutes. For example, a display that rewrites 60 times per second and refreshes once every 3 minutes Compared to display devices that operate in this way, power consumption can be reduced to approximately 1 / 10,000. It is possible.

[0194] Note that the above-mentioned stopping of the high power supply potential (VDD) means stopping the low power supply potential (V SS), and the high power supply potential (VDD) is stopped when the high power supply potential The potential of the wiring to be supplied may be set to a floating state.

[0195] In addition, the potential of the wiring to which the high power supply potential (VDD) is supplied is increased, that is, during the period T1 When increasing the power supply potential from a low power supply potential (VSS) to a high power supply potential (VDD) before It is preferable to control the potential change so that it is gentle. If the change in potential is steep, it will become noise and an incorrect pulse will be output from the shift register. The shift register may be a shift register included in the gate line driving circuit. If the faulty pulse is a signal that turns on the transistor, The voltage applied to the gate of the driving transistor changes depending on the pulse, and the image of the still image In view of the above, in FIG. 28, the high power supply potential (V DD) is shown in the figure, where the rising edge of the signal is slower than the falling edge. In particular, in the display device of this embodiment, when a still image is displayed in the pixel portion, The supply of high power supply potential (VDD) to the shift register is stopped and resupplied as appropriate. In other words, the change in the potential of the wiring that supplies the high power supply potential (VDD) appears as noise. If the noise affects the pixel section, it will directly lead to deterioration of the displayed image. In the display device of this type, a change in the potential of the wiring (especially an increase in the potential) is detected as noise. It is important to control it so that it does not invade the pixel area.

[0196] In the explanation of FIGS. 8 and 9, the configuration of the drive circuit that does not supply the reset signal Res is described. However, a configuration for supplying the reset signal Res will be described with reference to FIG.

[0197] The shift register shown in FIG. 10A includes first pulse output circuits 10_1 to N-th pulse output circuits 10_2. The shift register shown in FIG. 10(A) has a shift register output circuit 10_N (N is a natural number of 3 or more). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the first path (called the previous signal OUT(n-1)(SR)) is input. The pulse output circuit 10_1 receives a signal from the third pulse output circuit 10_3, which is two stages later. Similarly, in the n-th pulse output circuit 10_n of the second stage or later, the (n+ 2) from the pulse output circuit 10_(n+2) (post-stage signal OUT(n+2)(SR) Therefore, the pulse output circuit of each stage outputs the pulses from the next stage and / or the two stages before it. The first output signal OUT((1)(SR) to OUT(N) ) (SR)), a second output signal (OUT(1) to OUT(N)) input to another wiring, etc. Also, a reset signal Res is output from the sixth wiring 16 to the pulse output circuit of each stage. is supplied.

[0198] The pulse output circuit shown in Figure 10 differs from the pulse output circuit shown in Figure 8 in that The point is that it has a sixth wiring 16 for supplying a bit signal Res, and the points regarding other parts are the same as those described above. The same as the explanation for FIG.

[0199] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input Terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal 25, a first output terminal 26, a second output terminal 27, and a sixth input terminal 28. (See Figure 10(B)).

[0200] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 10(A) and 10(B) are electrically connected to any of the first to fourth wirings 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 _2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. is connected.

[0201] In addition, in FIGS. 10A and 10B, the first pulse output circuit 10_1 has a fourth input A start pulse is input to the terminal 24, and a subsequent signal OUT(3)(S R) is input, and the first output signal OUT(1)(SR) is output from the first output terminal 26. The second output terminal 27 outputs the second output signal OUT(1), and the sixth input terminal 2 A reset signal Res is input from 8.

[0202] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0203] In FIG. 10C, the first transistor 31 has a first terminal electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the first transistor. The second terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The third transistor 33 is electrically connected to the gate of the fourth transistor 34. The transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 22. The fourth transistor 34 has a first terminal electrically connected to the output terminal 26 of the first transistor. The power supply line 52 is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the power supply line 52. The gate of the second transistor 32 and the gate of the fourth transistor 34 are electrically connected to each other. , and the gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 is The first terminal is electrically connected to the power supply line 51, and the second terminal is connected to the gate of the second transistor 32. and the gate of the fourth transistor 34, the gate of which is connected to the fifth input terminal 25 The seventh transistor 37 has a first terminal electrically connected to the power supply line 51. , and a second terminal electrically connected to the second terminal of the eighth transistor 38, is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate of the second transistor 32 and the gate of the fourth transistor 34. The ninth transistor 39 is electrically connected to the second input terminal 22. The first terminal is connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. the second terminal is electrically connected to the gate of the third transistor 33 and the tenth transistor The gate of the resistor 40 is electrically connected to the power supply line 51. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the second output terminal 27, and the gate is the first terminal of the ninth transistor 39. The first terminal of the eleventh transistor 41 is electrically connected to the power supply line 52. , the second terminal is electrically connected to the second output terminal 27, and the gate is The gate of the first transistor 32 and the gate of the fourth transistor 34 are electrically connected to each other. The gate of the second transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor 35, the second terminal of the transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The first terminal of 38 and the gate of eleventh transistor 41 provide a reset signal Res. The reset signal Res is electrically connected to the wiring 53 for resetting the second transistor. The gate of the fourth transistor 32, the gate of the fifth transistor 35, 2 terminal, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and By supplying a signal of a high power supply potential level to the gate potential of the eleventh transistor 41, This signal is used to forcibly drop the output from the pulse output circuit to a low power supply potential level signal. be.

[0204] In FIG. 10C, the gate of the third transistor 33, the gate of the tenth transistor 40 The connection point of the gate of the ninth transistor 39 and the second terminal of the ninth transistor 39 is a node NA. , the gate of the second transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor the second terminal of the sixth transistor 35, the second terminal of the sixth transistor 36, the third terminal of the eighth transistor 38 The connection point between the first terminal and the gate of the eleventh transistor 41 is referred to as a node NB.

[0205] When the pulse output circuit in FIG. 10C is the first pulse output circuit 10_1, A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. The clock signal CK2 is input to the third input terminal 23, and the third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The second output terminal 26 receives the next stage signal OUT(3)(SR), and outputs the signal OUT(1)( SR) is output from the second output terminal 27, OUT(1) is output from the sixth input terminal A reset signal Res is input to 28.

[0206] In addition, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The timing chart is the same as that shown in FIG.

[0207] Figure 10 shows an example of a driving circuit made using multiple n-channel transistors. In the circuit, when displaying still images and moving images, the supply or stop of the potential of each wiring The procedure will be explained.

[0208] First, when the operation of the drive circuit unit 1007 is stopped, the display control circuit 1006 Then, after the start pulse SP stops, the pulse output shifts. After the clock signal CK reaches the final stage of the reset register, the clock signal CK is stopped. Next, the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage are supplied. (See FIG. 11C). When the operation of the driving circuit unit 1007 is to be restarted, First, the display control circuit 1006 drives the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage. Then, a reset signal Res is supplied to the circuit unit 1007. Then, a clock The signal CK is supplied, and then the supply of the start pulse SP is resumed (see FIG. 11(D)).

[0209] As explained in Fig. 10, in addition to the configurations in Fig. 8 and Fig. 9, a reset signal is supplied. This reduces malfunctions caused by signal delays when switching between still and moving images. This is preferable because it is possible to

[0210] In addition, when displaying a still image, the transistors constituting the driving circuit section are provided with The common potential electrode may be separated from the common potential line and placed in a floating state. When the drive circuit is to be operated again after the still image mode, the common potential electrode is connected to the common potential line. In this way, it is possible to prevent malfunction of the transistors in the drive circuit section.

[0211] FIG. 12(A) shows an example of such a display panel 1800, and FIG. 12(B) shows its cross section. FIG. 1 is a diagram illustrating a surface structure. The display panel 1800 is provided with driver circuits 1802 and 1804 and a pixel portion 1806. A common potential electrode 1808 is disposed so as to overlap the region where the driving circuit 1802 is provided. Between the common potential electrode 1808 and the common potential terminal 1812, there is provided a control circuit for controlling connection / disconnection between the two. A switch element 1810 is provided.

[0212] As shown in FIG. 12B, the common potential electrode 1808 is connected to the transistor 1803 of the driver circuit. A common potential electrode 1808 is provided on the transistor 1803. This allows the transistor 1803 to be electrostatically shielded, preventing variations in threshold voltage and parasitic channels. This prevents this from happening.

[0213] The switch element 1810 may have the same configuration as the transistor 1803. These elements have extremely low leakage current in the off state, which allows for the operation of the display panel. This contributes to stabilizing the operation of the switch element when displaying a still image. Even if the common potential electrode is left floating by turning off the resistor 1810, the potential remains constant. This has the effect of keeping the temperature constant.

[0214] In this way, transistors made of oxide semiconductors with a wide band gap are used. At the same time, a common potential electrode is provided to block the external electric field, thereby stopping the operation of the drive circuit. In addition, the potential of the common potential electrode can be controlled by the driving circuit. By controlling the display appropriately according to the operation, the operation of the display panel can be stabilized. .

[0215] As described above, each pixel includes a transistor using a high-purity oxide semiconductor. This allows the voltage to be held by the storage capacitor for a longer period than before, It is possible to reduce power consumption when displaying still images. The output of signals supplied to all signal lines and / or all scanning lines included in the pixel portion is stopped. By operating the driver circuit section so as to stop the power consumption of not only the pixel section but also the driver circuit section, The force can also be reduced.

[0216] (Embodiment 3) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 is An example of a manufacturing method thereof will be described. An example of a structure of a transistor and an example of a manufacturing method thereof will be described.

[0217] First, FIGS. 13A and 13B show an example of a plan view and a cross-sectional structure of a transistor. FIG. 13A is a plan view of a transistor 410 having a top-gate structure, and FIG. 13B is a plan view of a transistor 410 having a top-gate structure. FIG. 13(B) is a cross-sectional view taken along line C1-C2 of FIG.

[0218] The transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a first the first electrode (one of the source electrode and the drain electrode) 415a, the second electrode (one of the source electrode and the drain electrode) the other of the drain electrodes 415b, the gate insulating layer 402, and the gate electrode 411. The first electrode 415a and the second electrode 415b are connected to the first wiring 414a and the second wiring 414b, respectively. 4b is provided adjacent to and electrically connected to the substrate.

[0219] Note that the transistor 410 shown in FIG. 13A has a single-gate structure. However, the present invention is not limited to this configuration. A transistor having a multi-gate structure having a plurality of channel forming regions may also be used.

[0220] Next, a process for manufacturing the transistor 410 will be described with reference to FIGS. and explain.

[0221] First, an insulating layer 407 is formed on a substrate 400 as a base film.

[0222] There is no particular limitation on the substrate that can be used as the substrate 400, but it is necessary to use a substrate that can withstand at least the subsequent heat treatment. If the temperature of the subsequent heat treatment is high, It is preferable to use a substrate having a strain point of 730° C. or higher. A specific example of the substrate 400 is a glass substrate. Plates, crystallized glass substrates, ceramic substrates, quartz substrates, sapphire substrates, plastic substrates Specific examples of the glass substrate material include aluminosilicate glass. Examples of glass include glass, aluminoborosilicate glass, and barium borosilicate glass.

[0223] The insulating layer 407 may be a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, Alternatively, an oxide insulating layer such as an aluminum oxynitride layer is preferably used. The formation method can be a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the insulating layer 407, an insulating layer is formed by a sputtering method. In this embodiment, the insulating layer 407 is preferably formed by sputtering. Specifically, the substrate 400 is transferred to a processing chamber. After that, a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and silicon or A silicon oxide target is used to deposit silicon oxide as an insulating layer 407 on a substrate 400. During the film formation, the substrate 400 may be at room temperature or may be heated.

[0224] As a specific example of the film formation conditions, quartz (preferably synthetic quartz) is used as a target, and the substrate is The plate temperature was 108°C, the distance between the substrate 400 and the target (TS distance) was 60 mm, and the pressure was 0 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A silicon oxide film was formed by RF sputtering under a gas atmosphere (flow rate 25 sccm = 1:1). The film thickness is 100 nm. The target is quartz (preferably synthetic quartz). A silicon target can be used instead of the silicon target. Oxygen gas may be used instead of the argon mixed gas. The sputtering gas used in this process has a concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides of ppm. High purity gases that have been removed to the ppb level are used.

[0225] In addition, when forming the insulating layer 407, the insulating layer 407 is formed while removing residual moisture in the processing chamber. By forming the insulating layer 407, hydrogen, a hydroxyl group, or moisture can be prevented from being contained in the insulating layer 407. It is preferable that:

[0226] To remove the residual moisture in the processing chamber, an adsorption type vacuum pump may be used. , a cryopump, an ion pump, or a titanium sublimation pump can be used. As an exhaust means, it is preferable to add a cold trap to the turbo pump. The processing chamber evacuated using a lion pump contains hydrogen atoms and hydrogen atoms such as water (H2O). Since the compounds and the like are exhausted, the insulating layer 407 formed in the processing chamber is free of hydrogen atoms as much as possible. It is preferable because it is less likely to get caught.

[0227] There are two types of sputtering methods: RF sputtering, which uses a high-frequency power supply; DC sputtering method using a DC power supply, pulsed DC sputtering method using a pulsed bias The RF sputtering method is mainly used to deposit insulating films, while the DC The sputtering method is mainly used when forming a metal film.

[0228] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The device can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0229] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. A sputtering device that uses a sputtering method can be used.

[0230] In addition, as a film formation method using the sputtering method, a target material and a sputtering agent are mixed during film formation. Reactive sputtering that chemically reacts with Tagas components to form a compound thin film. There are also methods such as the bias sputtering method, in which a voltage is also applied to the substrate during film formation.

[0231] The insulating layer 407 is not limited to a single-layer structure, and may have a multilayer structure. From the side, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A stacked structure of a nitride insulating layer such as silicon nitride and the oxide insulating layer may be used.

[0232] For example, a silicon dioxide layer containing high-purity nitrogen from which hydrogen and moisture have been removed is placed between the silicon oxide layer and the substrate. A sputtering gas is introduced and a silicon nitride layer is formed using a silicon target. In the same way as for the silicon oxide layer, the silicon nitride layer is also formed while removing the residual moisture in the processing chamber. In addition, when forming a silicon nitride layer, it is preferable to heat the substrate during film formation. May be heated.

[0233] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, the silicon nitride The silicon dioxide layer and the silicon nitride layer are deposited in the same processing chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced to the silicon wafers mounted in the processing chamber. A silicon nitride layer is formed using a target, and then the sputtering gas is changed to a sputtering gas containing oxygen. The silicon oxide layer is then deposited using the same silicon target. When using a silicon nitride film, the silicon nitride layer and the silicon oxide layer are formed successively without exposure to the atmosphere. This prevents impurities such as hydrogen and moisture from adsorbing on the surface of the silicon nitride layer. Cut.

[0234] Next, an oxide semiconductor layer is formed over the insulating layer 407 by a sputtering method.

[0235] In order to minimize the amount of hydrogen, hydroxyl groups, and moisture contained in the oxide semiconductor layer, As a treatment, the substrate 400 on which the insulating layer 407 is formed is placed in the preheating chamber of the sputtering device. It is preferable to preheat the substrate 400 to remove impurities such as hydrogen and moisture adsorbed on the substrate 400 and evacuate the substrate. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. The heating is preferably performed on the substrate 400 before the gate insulating layer 402 to be formed later is formed. In addition, the substrate on which the first electrode 415a and the second electrode 415b are formed later is It is preferable to carry out the same process for 400. However, these preheating processes can be omitted. That's fine.

[0236] Before the oxide semiconductor layer was formed by sputtering, argon gas was introduced. Then, reverse sputtering is performed to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. Inverse sputtering, no voltage is applied to the target side, and the target is sputtered in an argon atmosphere. A plasma is generated near the substrate by applying a voltage to the substrate side using a high frequency power supply under atmospheric pressure. The argon atmosphere can be replaced by nitrogen, helium, or oxygen. etc. may also be used.

[0237] The target for the oxide semiconductor layer is a metal oxide target whose main component is zinc oxide. Other examples of metal oxide targets include In, Ga and a metal oxide target containing Zn (composition ratio: In2O3:Ga2O3:Zn O=1:1:1 [mol%], In:Ga:Zn=1:1:0.5 [atom%]) In addition, as a target of a metal oxide containing In, Ga, and Zn, In:Ga:Zn=1:1:1[atom%] or In:Ga:Zn=1:1:2[a It is also possible to use a target having a composition ratio of SiO2 of 2 wt.%. It is also possible to use a target containing 10% or more by weight of metal oxide. The filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a high-temperature metal oxide target, the deposited oxide semiconductor layer can be made into a dense film. It is possible.

[0238] Note that the oxide semiconductor layer is formed under a rare gas (typically, argon) atmosphere or an oxygen atmosphere. The reaction may be carried out under an atmosphere of air or under an atmosphere of a rare gas (typically argon) and oxygen. The sputtering gas used in forming the oxide semiconductor layer is a gas containing hydrogen, water, a hydroxyl group, a hydride, or the like. High-purity gas in which the concentration of impurities has been removed to ppm level, preferably ppb level. Use.

[0239] The oxide semiconductor layer is formed by holding the substrate in a processing chamber maintained in a reduced pressure state and removing residual water in the processing chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the metal oxide. In order to remove residual moisture in the processing chamber, an adsorption type vacuum cleaner is used. It is preferable to use an air pump. For example, a cryopump, an ion pump, or a titanium sub-pump. It is preferable to use a displacement pump. A cold trap may be added. A processing chamber evacuated using a cryopump. is, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H2O) (more preferably a carbon atom) Since the exhaust gases such as the oxygen-containing compounds are exhausted, the oxide semiconductor layer formed in the treatment chamber is In addition, the concentration of impurities can be reduced by leaving the substrate at room temperature during the formation of the oxide semiconductor layer. Alternatively, the mixture may be heated to a temperature below 400°C.

[0240] An example of the film formation conditions for the oxide semiconductor layer is as follows: the substrate temperature is room temperature; Distance: 110 mm, pressure: 0.4 Pa, DC power: 0.5 kW, oxygen and argon ( The conditions are as follows: oxygen flow rate 15 sccm; argon flow rate 30 sccm. When a pulsed direct current (DC) power supply is used, the powdery substances (particles, dust) generated during film formation can be easily removed. The thickness of the oxide semiconductor layer is preferably 100 nm or less because the thickness of the oxide semiconductor layer can be reduced and the thickness distribution can be uniform. The film thickness may be 2 nm or more and 200 nm or less, and preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the oxide semiconductor material used, and the thickness is determined appropriately depending on the material. You just need to select the

[0241] Specific examples of oxide semiconductor layers formed by the above method include quaternary metal oxides. In-Sn-Ga-Zn-O, which is a ternary metal oxide, and In-Ga-Zn-O, which is a ternary metal oxide. -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn- O, Sn-Al-Zn-O, and binary metal oxides In-Zn-O and Sn-Zn-O , Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, S The oxide semiconductor layer may be an oxide semiconductor layer such as ZnO or Zn—O. The layer may contain Si. Furthermore, these oxide semiconductor layers may be amorphous. Alternatively, it may be either non-single crystalline or single crystalline. In this embodiment, a sputtering method using In-Ga-Zn-O as a target is used. An amorphous In-Ga-Zn-O film is formed by this.

[0242] In addition, as the oxide semiconductor layer, InMO3(ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. Multiple metal elements. For example, M may be Ga, Ga and Al, Ga and Mn, or Examples include Ga and Co. Note that InMO3(ZnO) m Structures represented by (m>0) Among the oxide semiconductor films, the oxide semiconductor having a structure containing Ga as M is referred to as the In-G It can be called an a-Zn-O oxide semiconductor.

[0243] Next, the oxide semiconductor layer is subjected to a first photolithography process to form island-shaped oxide semiconductor layers 4 The oxide semiconductor layer 412 is formed into an island-shaped oxide semiconductor layer 412 (see FIG. 14A). A resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0244] The oxide semiconductor layer can be etched by either dry etching or wet etching. Well, you can use both.

[0245] When dry etching is performed, parallel plate RIE (Reactive Ion Etc.) hing method and ICP (Inductively Coupled Plasma) Inductively coupled plasma etching can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0246] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Although a gas containing fluorine (a fluorine-based gas, for example, carbon tetrafluoride (C )) is preferred, F4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3 ), hydrogen bromide (HBr), oxygen (O2), and the addition of helium (He) or argon A gas containing a rare gas such as argon (Ar) can also be used.

[0247] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia hydrogen peroxide solution (for example, a volume ratio of 31% by weight hydrogen peroxide solution to 28% by weight ammonia water) In addition, a solution in which ITO is mixed with water in a ratio of 5:2:2 can be used. 7N (manufactured by Kanto Chemical Co., Ltd.) may also be used. The conditions (time, temperature, etc.) may be adjusted as appropriate depending on the material of the oxide semiconductor.

[0248] Also, when wet etching is performed, the etching solution is released along with the etched material. The etchant waste liquid containing the removed material is purified and The material contained in the oxide semiconductor layer may be reused from the waste liquid after etching. By recovering and reusing materials (for example, rare metals such as indium), resources can be used effectively. It can be utilized.

[0249] In this embodiment, a wet etching solution using a mixture of phosphoric acid, acetic acid, and nitric acid is used. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 412 by a thermal etching method.

[0250] Next, first heat treatment is performed on the oxide semiconductor layer 412. The temperature of the first heat treatment is 40 The temperature is set to 0°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is heated under a nitrogen atmosphere for 4 hours. After heat treatment at 50°C for 1 hour, the oxide semiconductor was The first heat treatment prevents water and hydrogen from re-entering the oxide semiconductor layer 412. Hydrogen, water, hydroxyl groups, etc. can be removed.

[0251] The heat treatment device is not limited to an electric furnace, but may be a device that uses heat conduction from a heating element such as a resistance heating element or the like. A device for heating the object to be treated by thermal radiation may be provided. For example, a GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. Inert gas (typically, a rare gas such as argon) or nitrogen gas can be used. do.

[0252] For example, as the first heat treatment, the material is placed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved and heated to a high temperature inert gas. You can also use GRTA, which is a method of heating food from the inside. Processing becomes possible.

[0253] It is preferable that the atmosphere during the first heat treatment does not contain water, hydrogen, etc. Alternatively, gases such as nitrogen, helium, neon, and argon introduced into the heat treatment device may be used. The purity of the material should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more. Therefore, it is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less. It's nice.

[0254] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the island-shaped oxide semiconductor layer 412 is crystallized and becomes microcrystalline or polycrystalline. For example, the oxide semiconductor layer may be a microcrystalline oxide semiconductor layer with a crystallinity of 80% or more. Even when the first heat treatment is performed, the island-shaped oxide semiconductor layer 412 is not crystallized and remains as an amorphous oxide semiconductor layer. In some cases, the oxide semiconductor layer becomes a semiconductor layer. In addition, microcrystalline parts (grain size 1 nm) are formed in the amorphous oxide semiconductor layer. and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed. In some cases, this may be the case.

[0255] The first heat treatment on the oxide semiconductor layer is performed before processing into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heat treatment apparatus. The plate is removed and subjected to a photolithography process.

[0256] In the first heat treatment, impurities such as hydrogen, water, and a hydroxyl group are removed from the oxide semiconductor layer. The main purpose of this heat treatment is to remove oxygen vacancies in the oxide semiconductor layer. Therefore, it is recommended to carry out an oxidation treatment after the first heat treatment. As a specific example of the oxidation treatment, the first heat treatment is followed by an oxygen atmosphere. or a method of performing heat treatment in an atmosphere containing nitrogen and oxygen (nitrogen:oxygen volume ratio = 4:1) Alternatively, a method of performing plasma treatment in an oxygen atmosphere can be used.

[0257] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is carried out by After the film formation, a source electrode and a drain electrode are laminated on the oxide semiconductor layer, and then the source electrode and This may be performed either after forming the gate insulating layer on the drain electrode or after forming the gate insulating layer on the drain electrode.

[0258] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film may be formed by sputtering or vacuum deposition. , metal materials such as Cr, Ta, Ti, Mo, W, and Y, and alloy materials containing such metal materials as components; Examples of conductive metal oxides include oxides of metals such as iodide. Indium (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy Gold (In2O3-ZnO) or the above metal oxide material with silicon or silicon oxide Also, Si, Ti, Ta, W, Mo, Cr, Nd, A containing elements such as Sc and Y that prevent the occurrence of hillocks and whiskers in Al films. l material may be used, in which case the heat resistance can be improved.

[0259] The conductive film may have a single layer structure or a stacked structure of two or more layers. , a single layer structure of aluminum film containing silicon, and a titanium film laminated on an aluminum film. Layer structure: an aluminum film is layered on a Ti film, and a Ti film is layered on top of that. In addition, there are metal layers such as Al and Cu and layers of Cr, Ta, Ti, Mo, W, etc. Any high melting point metal layer may be laminated.

[0260] Next, a resist mask is formed on the conductive film by a second photolithography process. After selectively etching the first electrode 415a and the second electrode 415b, a resist The first electrode 415a is a source electrode and a drain electrode. The second electrode 415b functions as one of the source and drain electrodes. Here, the ends of the first electrode 415a and the second electrode 415b are tapered. Etching to form the desired shape improves the coverage of the gate insulating layer that is stacked on top. It is preferable to use a resist mask for forming the first electrode 415a and the second electrode 415b. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0261] In this embodiment, the first electrode 415a and the second electrode 415b are formed by sputtering. A titanium film having a thickness of 150 nm is formed.

[0262] In addition, when the conductive film is etched, the oxide semiconductor layer 412 is removed and the insulating film thereunder is removed. The materials and etching conditions must be adjusted appropriately so that the layer 407 is not exposed. Therefore, in this embodiment, an In—Ga—Zn—O based oxide semiconductor layer is used as the oxide semiconductor layer 412. An oxide semiconductor is used, a titanium film is used as a conductive film, and an ammonia hydrogen peroxide solution is used as an etchant. The oxide semiconductor layer 412 However, the present invention is not limited to this configuration. That is, part of the oxide semiconductor layer 412 is etched by a second photolithography process. Alternatively, the oxide semiconductor layer may have a groove (a depression).

[0263] The exposure to light during the resist mask formation in the second photolithography process is done using ultraviolet light or KrF Laser light or ArF laser light may be used. The width of the gap between the bottom end of the first electrode and the bottom end of the second electrode determines the width of the transistor to be formed later. The channel length L of the photoresist is determined. Note that when exposure is performed with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nanometers to a few tens of nanometers. olet) is used to perform exposure when forming a resist mask in the second photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. In this case, the operating speed of the transistor can be increased, and the off-current value is extremely small. This allows for reduction in power consumption of the transistor.

[0264] Next, the insulating layer 407, the oxide semiconductor layer 412, the first electrode 415a, and the second electrode 415 A gate insulating layer 402 is formed on b (see FIG. 14C).

[0265] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The silicon layer can be formed as a single layer or a multilayer.

[0266] It is preferable that the gate insulating layer 402 not contain hydrogen. Therefore, the sputtering method can minimize hydrogen in the film formation atmosphere. It is preferable to form a silicon oxide film by sputtering. When forming a film, a silicon target or a quartz target is used as the target. The etching is carried out using oxygen or a mixed gas of oxygen and argon as the starting gas.

[0267] The gate insulating layer 402 is formed by sequentially depositing an oxide film on the first electrode 415a and the second electrode 415b. Alternatively, a silicon oxide layer and a silicon nitride layer may be stacked. A silicon oxide (SiO) layer with a thickness of 5 nm to 300 nm is used as an insulating layer. x (x>0) and forming a second gate insulating layer on the first gate insulating layer. A silicon nitride layer (SiN y (y>0)) is laminated to form a gate insulating film with a thickness of 100 nm. In this embodiment, the pressure is 0.4 Pa, the high frequency power supply is 1.5 kW, and oxygen and and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere. A silicon oxide layer with a thickness of 100 nm is formed by F sputtering.

[0268] Next, a resist mask is formed by a third photolithography process and selectively etched. By removing a part of the gate insulating layer 402 by etching, the first electrode 415a, the second electrode 415b, and the Openings 421a and 421b are formed so as to reach the second electrode 415b (see FIG. 14(D)). When the resist mask is formed by the ink-jet method, a photomask is not used. This reduces manufacturing costs.

[0269] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. The gate electrode 411, the first wiring 414a, the second wiring 414b, and the like are formed by the photolithography process of 4. Form 414b.

[0270] The gate electrode 411, the first wiring 414a, and the second wiring 414b are made of molybdenum, Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium The metal material or the alloy material mainly composed of these is used to form a single layer or a laminate. The gate electrode 411, the first wiring 414a, and the second wiring 414b are two layers. Specific examples of the structure include a molybdenum layer stacked on an aluminum layer, and a molybdenum layer stacked on a copper layer. A titanium nitride layer or a tantalum nitride layer is laminated on a copper layer. or a structure in which a molybdenum layer is laminated on a titanium nitride layer. Specific examples of the layer structure include a tungsten layer or a tungsten nitride layer and an aluminum and and a titanium nitride or titanium layer. A gate electrode layer may be formed using a light-transmitting conductive film. A specific example of the light-transmitting conductive film is a light-transmitting conductive film. Examples of the film include a film made of an oxide.

[0271] In this embodiment, the gate electrode 411, the first wiring 414a, and the second wiring 414b are A titanium film having a thickness of 150 nm is formed by sputtering.

[0272] Next, a second heat treatment (preferably a second heat treatment) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the temperature is 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarization insulating layer is formed over the transistor 410.

[0273] In addition, heat treatment in air at 100°C to 200°C for 1 hour to 30 hours is also performed. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to Then, the temperature was increased to a temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times. In addition, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heat treatment under reduced pressure is preferable because it can shorten the heating time. .

[0274] Through the above process, high-purity acid with reduced concentrations of hydrogen, water, hydrides, and hydroxides is obtained. A transistor 410 having a nitride semiconductor layer 412 can be formed (FIG. 14(E)). The transistor 410 is the same as the first transistor 6401 described in Embodiment 1. etc. can be applied.

[0275] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 410. The protective insulating layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a nitride layer, or the like. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer. The planarization insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, polyimide, or polyimide. Heat-resistant organic materials such as polyamide and epoxy resins can be used. In addition to organic materials, low-k materials, siloxane resins, PSG (ringa Glass, BPSG (borophosphorus glass), etc. can also be used. A planarization insulating layer may be formed by stacking a plurality of insulating films.

[0276] Here, the siloxane-based resin is a Si- It corresponds to a resin containing an O-Si bond. Siloxane-based resins have organic groups (e.g. An alkyl group or an aryl group or a fluoro group may be used. It's okay to do so.

[0277] The method for forming the planarizing insulating layer is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A fukota or the like can be used.

[0278] As described above, when forming an oxide semiconductor layer, residual moisture in the reaction atmosphere is removed. By this, the concentrations of hydrogen and hydride in the oxide semiconductor layer can be reduced.

[0279] The transistor having an oxide semiconductor layer described in this embodiment is used to form a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. Furthermore, it is possible to switch between still images and moving images without any malfunction. .

[0280] (Fourth embodiment) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 is An example of a manufacturing method thereof will be described. An example of a structure of a transistor and an example of a manufacturing method thereof will be described with reference to FIGS. do.

[0281] 15A to 15E show examples of cross-sectional structures of transistors. The transistor 390 has a bottom gate structure and is also called an inverted staggered transistor. This transistor 390 may be replaced with the first transistor 6401 described in Embodiment 1. The transistor 390 can be used as a single-gate transistor. However, the present invention is not limited to this configuration. A multi-gate transistor having a plurality of channel formation regions may be used.

[0282] 15A to 15E, a transistor 390 is fabricated on a substrate 394. The method will be explained.

[0283] First, a conductive film is formed on a substrate 394, and then a gate electrode is formed by a first photolithography process. The end of the gate electrode 391 is tapered, so that the upper stacked It is preferable to use a resist mask in an ink jet printing process, since this improves the coverage of the gate insulating layer. If the resist mask is formed by the ink-jet method, the photomask Since no additional materials are used, the manufacturing cost can be reduced.

[0284] Here, the material of the substrate 394 is the same as that of the substrate 400 described in the third embodiment. The material and film formation method of the gate electrode 391 can be the same as those of the embodiment. The gate electrode 411 described in 3 can be used.

[0285] Note that an insulating film serving as a base film may be provided between the substrate 394 and the gate electrode 391 . The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 394, and is a silicon nitride film. A silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. The insulating film may be formed as a single layer structure or a laminated structure of a plurality of films selected from these.

[0286] Next, a gate insulating layer 397 is formed on the gate electrode 391 .

[0287] The gate insulating layer 397 is formed by depositing an oxide film using a plasma CVD method, a sputtering method, or the like. silicon layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, or aluminum oxide layer The gate insulating layer 397 can be formed as a single layer or a stacked layer. To prevent a large amount of hydrogen from being contained, a gate insulating layer 397 is formed by sputtering. When a silicon oxide film is formed by sputtering, A silicon or quartz target is used as the target, and oxygen is used as the sputtering gas. The process is carried out using oxygen or a mixed gas of oxygen and argon.

[0288] The gate insulating layer 397 is made up of a silicon nitride layer and a silicon oxide layer in this order from the gate electrode 391 side. For example, a sputtered film may be used as the first gate insulating layer. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. Just do that.

[0289] Next, an oxide semiconductor layer 393 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. (See FIG. 15(A)).

[0290] Here, the material, the film formation method, and the like of the oxide semiconductor layer 393 are the same as those of the oxide semiconductor layer described in Embodiment 3. The same semiconductor layer as the island-shaped oxide semiconductor layer 412 can be used.

[0291] For example, the oxide semiconductor layer 393 is formed by a sputtering method under the following conditions: The distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, and the direct current (DC) The conditions are a power supply of 0.5 kW and an oxygen atmosphere (oxygen flow rate 100%). When a pulsed direct current (DC) power supply is used, the powdery substances (particles, dust, etc.) generated during film formation can be easily removed. This is preferable because the thickness of the oxide semiconductor layer 393 can be reduced and the thickness distribution can be made uniform. The thickness of the film is preferably 2 nm to 200 nm, more preferably 5 nm to 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be selected.

[0292] Note that before the oxide semiconductor layer 393 was formed, argon gas was introduced to generate plasma. and removing dust adhering to the surface of the gate insulating layer 397. is preferred.

[0293] In addition, hydrogen, a hydroxyl group, and moisture are preferably contained in the gate insulating layer 397 and the oxide semiconductor layer 393. In order to prevent this from being included, the pre-heating chamber of the sputtering equipment is used as a pre-treatment for film formation. A substrate 394 on which a gate electrode 391 is formed, or a substrate on which a gate insulating layer 397 is formed The substrate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 1 The temperature should be between 50°C and 300°C. In addition, this preheating is preferably performed by heating the first electrode 39 before forming the protective insulating layer 396. The same process may be carried out on the substrate 394 on which the first electrode 5a and the second electrode 395b have been formed.

[0294] Next, the oxide semiconductor layer is subjected to a second photolithography process to form island-shaped oxide semiconductor layers 3 The island-shaped oxide semiconductor layer 399 is processed into the oxide semiconductor layer 399 (see FIG. 15B). Regarding the method for forming the island-shaped oxide semiconductor layer 412 described in Embodiment 3, The same as the law can be adopted.

[0295] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate electrode 396 are formed. It is preferable to remove resist residues and the like adhering to the surface of the gate insulating layer 397.

[0296] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The film may be formed by sputtering, vacuum deposition, or the like. The alloy may contain elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or any of these elements. Alloys containing these elements or alloys that combine multiple of these elements can be used. Also, manganese, magnesium, zirconium, beryllium, or thorium One or more materials may be used. A specific example of the light-transmitting conductive film is a light-transmitting conductive oxide film. Examples include membranes.

[0297] The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing silicon, and a two-layer structure of titanium film laminated on aluminum film. The structure is a Ti film, an aluminum film is layered on top of the Ti film, and a Ti film is layered on top of that. Examples include a three-layer structure that is formed by depositing a film.

[0298] Next, a resist mask is formed on the conductive film by a third photolithography process. After selectively etching the first electrode 395a and the second electrode 395b, a resist The mask is then removed (see FIG. 15(C)). Here, when etching the conductive film, an acid is used. The gate insulating layer 397 is not exposed when the oxide semiconductor layer 399 is removed. It is necessary to appropriately adjust the material and etching conditions. The oxide semiconductor layer 399 is an In-Ga-Zn-O oxide semiconductor, and the conductive film is Using a titanium film, ammonia hydrogen peroxide (ammonia, water, hydrogen peroxide water) was used as an etchant. By using the mixture, part of the oxide semiconductor layer 399 is not etched. However, the present invention is not limited to this configuration. By this process, a part of the oxide semiconductor layer 399 is etched to form an oxide semiconductor layer having a groove (depression). It may also be a conductive layer.

[0299] The third photolithography process involves the exposure of resist masks to ultraviolet light or KrF Laser light or ArF laser light may be used. The gap width between the bottom end of the first electrode 395a and the bottom end of the second electrode 395b determines the width of the gap. The channel length L of the transistor to be used is determined. When performing exposure, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. Ultraviolet) as a resist mask in the third photolithography step Exposure to extreme ultraviolet light provides high resolution and a large depth of focus. The channel length L of the transistor to be formed later is set to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and an extremely small off-state current. This allows for reduction in power consumption of the transistor.

[0300] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and etching further changes the shape. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also reduces the number of photolithography steps required, making it possible to simplify the process.

[0301] Also, the exposed surface is treated with plasma using gases such as N2O, N2, or Ar. Adsorbed water and the like attached to the surface of the oxide semiconductor layer 399 may be removed. Alternatively, the plasma treatment may be performed using a mixed gas of argon and argon. The plasma treatment is then carried out.

[0302] Next, after the plasma treatment, the exposed oxide semiconductor A protective insulating film 396 is formed in contact with the layer 399, the first electrode 395a, and the second electrode 395b. (see FIG. 15D). At this time, the oxide semiconductor layer 399 and the protective insulating layer 396 To prevent hydrogen, hydroxyl groups, or moisture from being contained in the processing chamber, remove any residual moisture from the processing chamber. In addition, it is preferable to form a protective insulating layer 396. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump It is preferable to use a titanium sublimation pump. A cryopump with a cold trap may be used. The gas-evaporated processing chamber is filled with, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O). Therefore, the concentration of impurities contained in the protective insulating layer 396 formed in the treatment chamber can be reduced. do.

[0303] In this embodiment, an oxide insulating layer is formed as the protective insulating layer 396. As a method for forming the oxide semiconductor layer 399, the first electrode 395a, and the second electrode 395b, The substrate 394 on which the pole 395b is formed is left at room temperature or heated to a temperature below 100°C. Then, a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and a silicon semiconductor is formed. A silicon oxide layer is formed using the target. Instead of the silicon layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer may be used. A silicide layer or the like can also be used.

[0304] For example, a silicon target with a purity of 6N and doped with boron (resistivity 0.0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0.4 Pa, direct current (DC) power supply 6kW, oxygen (oxygen flow rate 100%) atmosphere, pulse DC A silicon oxide layer is formed by sputtering. The thickness of the silicon oxide layer is 300 nm. It is also possible to use quartz (preferably synthetic quartz) instead of the silicon target. The sputtering gas may be oxygen or a mixed gas of oxygen and argon.

[0305] Furthermore, when the protective insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other, the The heat treatment is preferably performed at 0° C. The oxide semiconductor layer 399 Impurities such as hydrogen, moisture, hydroxyl groups, or hydrides are diffused into the protective insulating layer 396. In this case, the impurities contained in the oxide semiconductor layer 399 can be further reduced.

[0306] By the above steps, an oxide semiconductor having reduced concentrations of hydrogen, moisture, hydroxyl groups, or hydrides can be obtained. A transistor 390 can be formed having a semiconductor layer 392 (see FIG. 15(E)). As described in this embodiment, when an oxide semiconductor layer is formed, the residual gas in the reaction atmosphere is The residual water is removed to reduce the concentrations of hydrogen and hydrides in the oxide semiconductor layer. This results in an intrinsic or substantially intrinsic semiconductor.

[0307] Note that an insulating layer may be further provided on the protective insulating layer 396. An insulating layer 398 is formed on the edge layer 396. The insulating layer 398 may be a silicon nitride film, a nitride film, or the like. A silicon oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like may be used. stomach.

[0308] The insulating layer 398 is formed by placing the substrate 394, which has been formed up to the protective insulating layer 396, on the substrate 394 for 10 minutes. The sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is heated to a temperature of 0°C to 400°C. A silicon nitride film is formed using a silicon semiconductor target. In the same manner as the protective insulating layer 396, the insulating layer 398 is also formed while removing the remaining moisture in the processing chamber. When the insulating layer 398 is formed, the substrate 394 is heated to 100° C. to 400° C. By heating, hydrogen or moisture contained in the oxide semiconductor layer 399 is removed from the insulating layer 398 In this case, heat treatment must be performed immediately after the protective insulating layer 396 is formed. It's okay.

[0309] A silicon oxide layer is formed as a protective insulating layer 396, and a silicon nitride layer is formed as an insulating layer 398. When forming a silicon layer, the silicon oxide layer and the silicon nitride layer are formed in the same processing chamber. A silicon target can be used for film formation. An etching gas containing oxygen is introduced first. A silicon oxide layer is formed using a silicon target installed in the processing chamber, and then The etching gas was then switched to a nitrogen-containing etching gas and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are formed without being exposed to the atmosphere. Since it can be formed continuously, impurities such as hydrogen and moisture are absorbed on the surface of the silicon oxide layer. It is to be noted that a silicon oxide layer is formed as the protective insulating layer 396, and the insulating After a silicon nitride layer is stacked as the layer 398, hydrogen or Heat treatment (at a temperature of 100° C. to 400° C.) is performed to diffuse moisture into the oxide insulating layer. It is more preferable that:

[0310] After the protective insulating layer 396 is formed, the heat treatment is continued in the atmosphere at 100°C or more and 200°C or less for 1 hour or more and 3 hours. The heating treatment may be performed for 0 hours or less. This heating treatment is performed by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then the heating temperature may be increased. This heating treatment may be repeated several times to lower the temperature from the temperature of the oxide insulating film to room temperature. Before forming the insulating layer, the heating treatment may be carried out under reduced pressure. It is possible.

[0311] The above process is carried out at temperatures below 400°C, so the thickness is less than 1mm and the length of each side is 1m. It can also be applied to manufacturing processes that use glass substrates with temperatures exceeding 400°C. All processes can be performed at the processing temperature, so the energy required to manufacture the display panel is reduced. Consumption can be reduced.

[0312] The transistor having an oxide semiconductor layer described in this embodiment is used to form a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. Furthermore, it is possible to switch between still images and moving images without any malfunction. .

[0313] (Embodiment 5) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 will be described. An example of a manufacturing method thereof will be described. An example of the structure of a transistor and an example of a manufacturing method thereof will be described with reference to FIG. 16. .

[0314] 16A to 16D show examples of cross-sectional structures of transistors. The transistor 360 shown in FIG. 1 is called a channel protection type (also called a channel stop type). This transistor is one of the bottom gate structures that are used in transistors, and is also called an inverted staggered transistor. The transistor 360 can be used as the first transistor 6401 described in Embodiment 1. Although the transistor 360 is a transistor with a single gate structure, The present invention is not limited to this configuration, and may be applied to a semiconductor device having a plurality of gate electrodes and a channel forming region. The transistor may have a multi-gate structure having a plurality of gate electrodes.

[0315] 16A to 16D, a transistor 360 is fabricated on a substrate 320. The method will be explained.

[0316] First, a conductive film is formed on the substrate 320, and then a gate electrode is formed by a first photolithography process. The substrate 320 is made of the same material as that of the substrate 3 described in the fourth embodiment. The same materials as those of 94 can be used. The gate electrode 391 may be the same as the gate electrode 391 described in the fourth embodiment.

[0317] Next, a gate insulating layer 322 is formed on the gate electrode 361. The material of the gate insulating layer 322 is The material may be the same as that of the gate insulating layer 397 described in the fourth embodiment. In this embodiment, the gate insulating layer 322 is formed by plasma CVD to a thickness of 1 A silicon oxynitride layer having a thickness of 00 nm or less is formed.

[0318] Next, an oxide semiconductor layer having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer by a second photolithography process. The material, film formation method, processing method, etc. of the oxide semiconductor layer are the same as those of the island-shaped oxide semiconductor layer described in the fourth embodiment. The same material as the conductor layer 399 can be used. In this embodiment, the oxide semiconductor layer The film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. do.

[0319] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor The layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. By not using the heat treatment, water or hydrogen is prevented from being mixed into the oxide semiconductor layer again, and the oxide semiconductor layer 332 is obtained. (See FIG. 16(A)).

[0320] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0321] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0322] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300°C. In this case, the temperature is set to 100°C. The silicon oxide film is formed by sputtering using a rare gas (typically In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. A silicon oxide film can be formed in contact with the oxide semiconductor layer by sputtering under atmospheric pressure. The oxide insulating layer 366 formed on the surface of the silicon dioxide film 361 is resistant to moisture, hydrogen ions, and OH ions. - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside, typically silicon oxide. film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film, etc. You can be there.

[0323] At this time, hydrogen, a hydroxyl group, or moisture is added to the oxide semiconductor layer 332 and the oxide insulating layer 366. To prevent the inclusion of moisture in the oxide insulating layer 366, the remaining moisture in the processing chamber is removed. It is preferable to do so. Regarding the method for removing the residual moisture in the processing chamber, see other embodiments. The method described in can be used.

[0324] Next, a second heat treatment (preferably a second heat treatment) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. It is preferable to carry out the heating at a temperature of 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Then, heating is performed while part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366. It's hot.

[0325] In this embodiment, the oxide semiconductor layer 364 is formed in a region that is not covered with the oxide insulating layer 366. The oxide insulating layer 332 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The oxide semiconductor layer 332 in the region not covered by the oxide semiconductor layer 66 is then etched under a nitrogen or inert gas atmosphere. Alternatively, when heat treatment is performed under reduced pressure, dehydrogenation occurs and an oxygen deficiency occurs, resulting in low resistance. For example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere is recommended. .

[0326] The oxide semiconductor layer 332 provided with the oxide insulating layer 366 is subjected to heat treatment in a nitrogen atmosphere. As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 16 In FIG. 1B, the oxide semiconductor layer 362 has a structure shown by hatched areas and white areas.

[0327] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process. After selectively etching the first electrode 365a and the second electrode 365b, a resist The mask is removed (see FIG. 16(C)).

[0328] The materials for the first electrode 365a and the second electrode 365b include Al, Cr, Cu, Ta, An element selected from Ti, Mo, and W, or an alloy containing the above-mentioned element, or The metal conductive film may have a single layer structure or an alloy film made up of a combination of elements. Alternatively, it may have a laminated structure of two or more layers.

[0329] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor layer is reduced by heat treatment for oxidation, a part of the oxide semiconductor layer is selectively treated with excess oxygen. As a result, the channel forming region 363 overlapping with the gate electrode 361 becomes an I-type. The low-resistance source region 364a overlaps the first electrode 365a, and the low-resistance source region 364b overlaps the second electrode 365b. The overlapping low-resistance drain region 364b is formed in a self-aligned manner. A transistor 360 is formed.

[0330] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By doing so, the heating time can be shortened.

[0331] Note that in the oxide semiconductor layer overlapping with the second electrode 365b (and the first electrode 365a), By forming a low-resistance drain region 364b (or a low-resistance source region 364a) This improves the reliability of the transistor. By forming the region 364b, the drain electrode is connected to the low resistance drain region 364b and the channel The conductive layer 363 can be structured so that the conductivity can be changed stepwise. Therefore, the second electrode 365b is connected to a wiring that supplies a high power supply potential VDD. In this case, even if a high electric field is applied between the gate electrode 361 and the second electrode 365b, a low resistance The drain region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible to achieve a more precise configuration.

[0332] Next, a protective insulating layer 365a was formed on the first electrode 365a, the second electrode 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See FIG. 16(D)).

[0333] The transistor having an oxide semiconductor layer described in this embodiment is used to form a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. It is also possible to switch between still images and moving images without any malfunction. do.

[0334] (Embodiment 6) This embodiment shows another example of a transistor that can be applied to the display device disclosed in this specification. The transistor 350 described in this embodiment is the same as that used in each pixel of the pixel portion in Embodiment 1. It can be used for the transistor 6401 and the like.

[0335] The transistor 350 shown in FIG. 17(D) is a transistor having a single gate structure. However, the present invention is not limited to this configuration. The transistor may have a multi-gate structure having a plurality of forming regions.

[0336] 17A to 17D, a transistor 350 is fabricated on a substrate 340. The process will be explained.

[0337] First, a conductive film is formed on the substrate 340, and then a gate electrode is formed by a first photolithography process. In this embodiment, the gate electrode 351 is formed with a thickness of 150 nm. The tungsten film is formed by sputtering.

[0338] Next, a gate insulating layer 342 is formed on the gate electrode 351. A silicon oxynitride film with a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Complete.

[0339] Next, a conductive film is formed on the gate insulating layer 342, and a conductive film is formed by a second photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form the source electrode 355a and the drain electrode 355b. After the rain electrode 355b is formed, the resist mask is removed (see FIG. 17(A)).

[0340] Next, an oxide semiconductor layer 345 is formed (see FIG. 17B). The oxide semiconductor layer 345 is formed by using an In-Ga-Zn-O metal oxide target. Subsequently, the oxide semiconductor layer 345 is formed by a third photolithography process. The oxide semiconductor layer is processed into an island shape by the above process.

[0341] In the step of forming the oxide semiconductor layer 345, the oxide semiconductor layer 345 is formed by removing residual moisture in the treatment chamber and then oxidizing the oxide semiconductor layer 345. By forming the oxide semiconductor layer 345, hydrogen, hydroxyl groups, or It is preferable to prevent moisture from being contained in the processing chamber. The methods described in other embodiments can be used.

[0342] Next, first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor The conductor layer was subjected to heat treatment at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. By preventing this, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 346 is (See Figure 17(C)).

[0343] In the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. You may also perform a GRTA.

[0344] Next, the oxide insulating layer 356 is formed in contact with the oxide semiconductor layer 346. The oxide insulating layer 356 has a thickness of at least 1 nm, and impurities such as water and hydrogen are not contained in the oxide insulating layer 356. The oxide insulating layer can be formed by a method that does not mix oxides (for example, a sputtering method). If hydrogen is contained in the edge layer 356, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized by the hydrogen. Oxygen is extracted from the oxide semiconductor layer, lowering the resistance of the back channel of the oxide semiconductor layer. This can lead to the formation of a parasitic channel. It is important to use a deposition method that results in layer 356 containing as little hydrogen as possible. .

[0345] Note that the material, the deposition method, and the like of the oxide insulating layer 356 are the same as those of the protective layer in Embodiment 4. The same insulating layer as the insulating layer 396 can be used.

[0346] Next, a second heat treatment (preferably a second heat treatment) is carried out in an inert gas atmosphere or an oxygen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. The body layer is heated while in contact with oxide insulating layer 356.

[0347] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the resistance is reduced by heat treatment for oxidation, the oxide semiconductor layer is made to have an oxygen-excess state. As a result, an i-type oxide semiconductor layer 352 is formed. 350 is formed.

[0348] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100°C or higher and 200°C or lower. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By performing this heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer, and a normally-off transistor can be obtained. This improves the reliability of the display device.

[0349] Note that an insulating layer may be further provided over the oxide insulating layer 356. An insulating layer 343 is formed on the insulating layer 356 (see FIG. 17(D)). The materials and film-forming methods are the same as those for the protective insulating layer 398 in the fourth embodiment. It is possible.

[0350] A planarization insulating layer may be provided for the purpose of planarizing the surface of the insulating layer 343.

[0351] The transistor having an oxide semiconductor layer described in this embodiment is used to form a display portion of a display device. By using this in a pixel that forms a storage capacitor, the off-current can be reduced. This allows the voltage to be maintained for a longer period, reducing power consumption when displaying still images, etc. In addition, by stopping the control signal when displaying a still image, it is possible to reduce power consumption. It is also possible to switch between still images and moving images without any malfunction. do.

[0352] (Embodiment 7) In this embodiment mode, one mode of a display device in which a luminescent layer is provided in a pixel portion will be described.

[0353] FIG. 18 is a cross-sectional view of a pixel portion of a bottom emission structure, and shows the transistors (drive a light-emitting element 7211 electrically connected to the transistor 7211; 2 is a cross-sectional view of a section including 212.

[0354] The transistor 7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer over a substrate. a source electrode layer, a drain electrode layer, a gate insulating layer, and a gate electrode layer; A wiring layer is provided to electrically connect the respective layers.

[0355] An insulating layer 7231 is formed to cover the transistor 7211. A luminous layer 7233 having an opening is provided. A light-transmitting conductive film 7217 is formed over the overcoat layer 7234 and the insulating layer 7235. The drain electrode 7230 of the transistor 7211 and the conductive film 721 7 is a luminous layer 7233, an overcoat layer 7234, an insulating layer 7235, and an insulating layer 723 The light-emitting element 7217 is electrically connected to the light-emitting element 7218 through an opening formed in the conductive film 7217. The first electrode 7213 of the light-emitting element 7212 is provided in contact with the first electrode 7213 of the light-emitting element 7212. The EL layer 7214 is sandwiched between a first electrode 7213 and a second electrode 7215. A shielding film 7216 is provided on the second electrode 7015 .

[0356] Note that the transistor 7211 and the light-emitting element 7212 are described in Embodiments 3 to 6. Since the method can be used to fabricate the semiconductor device, detailed description thereof will be omitted here.

[0357] The luminous layer 7233 contains a luminous material and stores the light emitted by the adjacent light emitting element. Even after the optical element stops emitting light, the luminous material contained in the luminous layer 7233 continues to emit light. In this embodiment, copper activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. Phosphors that use sulfides such as trontium (SrS) as a base material and add an activator, or phosphors that use rare earth elements Alkaline earth aluminates activated with rare earth elements can also be used. Specific examples of earth aluminates include CaAl2O4:Eu, CaAl2O4:Nd, and S r4Al 14 O 25 :Eu, Sr4Al 14 O 25 :Dy, SrAl2O4:Eu, and In addition, when inorganic particles are used as the phosphorescent material, the particle size If the particle size is less than 1 nm, the phosphorescence may be lost. In this case, the flatness of the luminous layer may be impaired, making it difficult to fabricate the light-emitting device. Therefore, the particle size is preferably 1 nm or more and 10 μm or less.

[0358] The time that the phosphorescent layer 7233 continues to emit light can be changed depending on the type of phosphorescent material. In other words, the amount of time that light continues to be emitted, or the so-called afterglow time, varies depending on the type of phosphorescent material. The material can be selected depending on the application. For example, if the display content does not need to be rewritten frequently, Electronic devices (e.g., electronic paper) equipped with display devices for use in various applications have long afterglow times. It is preferable to select and use a phosphorescent material. Electronic devices with display devices for certain applications (for example, television sets) have a decay time It is preferable to select and use a short-lived phosphorescent material.

[0359] The luminous layer 7233 may also contain a binder polymer. droplet ejection methods such as inkjet methods using dispersed liquids, printing methods, spin coating methods, It can be formed by appropriately selecting an etching method using photolithography technology. do.

[0360] In addition, in order to flatten the unevenness of the surface of the luminous layer 7233, the surface of the luminous layer 7233 is It is preferable to cover the insulating layer 7234 with an overcoat layer 7234. It is preferable to cover it with an overcoat layer 7234 and 235. A contact hole formed in the protective insulating layer 7235 and reaching the drain electrode 7230 is disposed at a position overlapping with the partition wall 7219.

[0361] The position where the luminous layer 7233 is provided is not limited to between the user of the display device and the light emitting element. For example, a light-emitting element with a dual emission structure in which an EL layer is sandwiched between a pair of light-transmitting electrodes is In this case, when the light-emitting element has light-transmitting properties, the phosphorescent layer 7233 is In other words, the phosphorescent layer and the display layer can be arranged on the rear side of the light-emitting layer when viewed from the user of the device. It is also possible to place a light emitting element between the user of the display device and the light emitting element. When the light source is placed between the user and the luminous layer, the luminous layer does not necessarily have to be translucent. The range of material choices can be expanded. Specifically, phosphorescent materials with particle sizes of 100 μm or less can be used. It will be available.

[0362] As described above, the display device described in this embodiment includes a high-purity oxide semiconductor layer. In addition to the transistor having the off-state current, a light-storing layer is included in the pixel portion. In addition to having a transistor with reduced capacitance in the pixel, the pixel also has a phosphorescent layer, which allows the light-emitting element Even if the light emission interval is long, the flicker is not noticeable. That is, the display device described in this embodiment reduces power consumption and is capable of displaying still images. It can be made to be of excellent quality.

[0363] (Embodiment 8) In this embodiment, an electronic device including the display device described in the above embodiment will be described. However, the electronic devices to which the present invention can be applied are not limited to the specific examples shown below. It is not something that can be determined.

[0364] The electronic device shown in FIG. 19(A) is a portable game machine, and includes a housing 9630, a display portion 9631, Speaker 9633, operation keys 9635, connection terminal 9636, recording medium reading unit 9672, etc. The portable gaming machine also reads the programs or data recorded on the recording medium. and a function to share information with other portable gaming machines via wireless communication. The functions of the portable gaming machine are not limited to these, and various functions may be included. It can have the ability.

[0365] The electronic device shown in FIG. 19B is a digital camera. , speaker 9633, operation keys 9635, connection terminal 9636, shutter button 9676 The digital camera has a function to take still images and a function to take videos. functions for automatically or manually correcting captured images; It has functions such as saving the image, displaying the captured image information on the display unit, and receiving TV images. The functions of the digital camera are not limited to these, and various functions may be used. It is possible.

[0366] The electronic device shown in FIG. 19C is a television receiver, and includes a housing 9630, a display portion 9631, The television receiver includes a speaker 9633, operation keys 9635, a connection terminal 9636, etc. A function that processes television radio waves and converts them into image signals, and processes image signals to produce signals suitable for display. and a function for converting the frame frequency of the image signal. However, the functions of the television set are not limited to these, and the television set can have a variety of functions.

[0367] The electronic device shown in FIG. 20A is a computer, and includes a housing 9630, a display portion 9631, Speaker 9633, operation keys 9635, connection terminal 9636, pointing device 96 81, external connection port 9680, etc. The computer stores various information (still images, video The function to display text images, etc. on the display, and various software (programs) a function to control processing by wireless or wired communication, a communication function to Functions for connecting to various computer networks, and transmission or However, the functions of a computer are not limited to these. It can have a variety of functions.

[0368] The electronic device shown in FIG. 20B is a mobile phone, and includes a housing 9630, a display portion 9631, a switch The mobile phone has a speaker 9633, operation keys 9635, a microphone 9638, etc. , functions to display various information (still images, videos, text images, etc.), calendar, date or The function to display the time, etc. on the display, the function to operate or edit the information displayed on the display, It may have a function to control the processing by various software (programs). The functions of the mobile phone are not limited to these, and the mobile phone can have a variety of functions.

[0369] The electronic device shown in FIG. 20C is an electronic paper device, and includes a housing 9630, a display portion 9631, The electronic paper has operation keys 9635 and the like. Functions for displaying images, calendars, dates, or times on the display, The function of manipulating or editing the information displayed on the screen, using various software (programs) It should be noted that the functions of electronic paper are not limited to these. The electronic paper can have various functions. Examples include electronic books (also called e-books), posters, and train rides. Examples include in-car advertisements for goods.

[0370] The electronic device shown in FIG. 20D is a digital photo frame. The display unit 9703 is capable of displaying various images. For example, by displaying image data taken with a digital camera, it can be used as a regular photo frame. It can function similarly.

[0371] The digital photo frame is equipped with an operation panel, external connection terminals (USB terminal, USB cable, etc.) It has a terminal that can be connected to various cables, a recording medium insertion section, etc. It may be incorporated on the same surface as the display unit, but providing it on the side or back improves the design. For example, it is preferable to insert a digital camera into the recording medium insertion section of a digital photo frame. Insert the memory that stores the image data taken by the camera and import the image data. Image data can be displayed on the display portion 9703 .

[0372] The digital photo frame may also have a function that allows wireless transmission and reception of information. In this case, the desired image data is wirelessly imported into the digital photo frame and displayed. However, the functions of the digital photo frame are not limited to these. , can have a variety of functions.

[0373] By applying the display device according to one embodiment of the present invention to these electronic devices, it is possible to display still images and the like. Therefore, it is more suitable for displaying still images than for displaying moving images. This is a product for electronic devices such as digital cameras, electronic paper, and digital photo frames, which are often used. When a display device according to one embodiment of the present invention is used, the effect of reducing power consumption is significant. Particularly preferred. [Explanation of symbols]

[0374] 1000 display devices 1001 Display panel 1002 Signal generation circuit 1003 Memory circuit 1004 Comparison circuit 1005 selection circuit 1006 Display control circuit 1007 Drive circuit section 1008 Pixel section 1009A Gate line driver circuit 1009B Signal line driver circuit 1010 frame memory

Claims

1. a pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, A power supply potential is applied to the conductive film. Display device.

2. A display device having a function of changing the frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, A power supply potential is applied to the conductive film. Display device.

3. a pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, a power supply potential is applied to the conductive film; The power supply potential is applied to a common electrode of the light-emitting element. Display device.

4. A display device having a function of changing the frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, and a second transistor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, a power supply potential is applied to the conductive film; The power supply potential is applied to a common electrode of the light-emitting element. Display device.

5. a pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitor has a function of holding a potential of a gate electrode of the first transistor; the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, A power supply potential is applied to the conductive film. Display device.

6. A display device having a function of changing the frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitor has a function of holding a potential of a gate electrode of the first transistor; the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, A power supply potential is applied to the conductive film. Display device.

7. a pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitor has a function of holding a potential of a gate electrode of the first transistor; the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, a power supply potential is applied to the conductive film; The power supply potential is applied to a common electrode of the light-emitting element. Display device.

8. A display device having a function of changing the frequency of writing an image signal to a pixel portion, the display device includes the pixel portion, a gate line driving circuit, and a conductive film; the pixel portion includes a light-emitting element, a first transistor, a second transistor, and a capacitor; the first transistor has a channel formation region in a polycrystalline silicon layer; the second transistor has a channel formation region in an oxide semiconductor layer, one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; a potential corresponding to an image signal is supplied to a gate electrode of the first transistor via the second transistor; the first transistor has a function of supplying a current to the light-emitting element, the capacitor has a function of holding a potential of a gate electrode of the first transistor; the gate line driving circuit has a function of supplying a signal to a gate electrode of the second transistor; the gate line driving circuit includes a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film; a periphery of the conductive film overlaps with a region between the pixel portion and the gate line driving circuit, a power supply potential is applied to the conductive film; The power supply potential is applied to a common electrode of the light-emitting element. Display device.

9. In any one of claims 5 to 8, one electrode of the capacitance element is always electrically connected to the gate electrode of the first transistor; Display device.

10. In any one of claims 1 to 9, the oxide semiconductor layer is an In—Ga—Zn—O-based, In—Sn—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, In—Sn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, Zn—O-based, or In—Al—Zn—O-based oxide semiconductor; Display device.

Images