Display substrate and display device

Abstract

A display substrate (10) and a display device (30), the display substrate (10) comprises a first conductive structure (110), the first conductive structure (110) comprises a first surface (111) and a third surface (113) facing each other, and a second surface (112) and a fourth surface (114) facing each other, the first surface (111) and the second surface (112) are made of the same material, the first surface (111) and the second surface (112) respectively form different included angles with a plate surface of a base substrate (101), a first surface microstructure (11) is disposed on the first surface (111), and a second surface microstructure (12) is disposed on the second surface (112), The first surface microstructure (11) has a first cross section (11a) perpendicular to the base substrate (101), the first cross section (11a) has a first orthogonal projection (C1C2) on the third surface (113), the length of the first orthogonal projection (C1C2) is shorter than the length of the first surface microstructure (11) at the first cross section (11a), the second surface microstructure (12) has a second cross section (12a) perpendicular to the base substrate (101), the second cross section (12a) has a second orthogonal projection (D1D2) on the fourth surface (114), the length of the second orthogonal projection (D1D2) is shorter than the length of the second surface microstructure (12) at the second cross section (12a). The display substrate (10) can effectively improve the yield.

Description

[Technical Field]

[0001] This application claims priority from Chinese Patent Application No. 202110000866.2, filed on January 4, 2021, the entire contents of which are hereby incorporated by reference into this application.

[0002] An embodiment of the present disclosure provides a display substrate and a display device. [Background technology]

[0003] In the display field, organic light-emitting diode (OLED) display panels have the following characteristics: self-luminance, high contrast, low energy consumption, wide viewing angle, fast response time, usability in flexible panels, wide operating temperature range, and ease of fabrication, and thus have broad future potential. Semiconductor device technology, which is the core of display devices, is also rapidly advancing. Compared to conventional display devices, organic light-emitting diodes (abbreviated as OLEDs) are current-type light-emitting devices that have the following characteristics: self-luminance, fast response time, wide viewing angle, and can be fabricated on a flexible base, and are therefore increasingly being applied in the field of high-performance display technology. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a first conductive structure located on the base substrate, the first conductive structure having a first surface and a second surface away from the base substrate, the first surface and the second surface being made of the same material, the first surface and a plate surface of the base substrate forming a first included angle, the second surface and a plate surface of the base substrate forming a second included angle different from the first included angle, a first surface microstructure disposed on the first surface, and a second surface microstructure disposed on the second surface, the first conductive structure further comprising a third surface and a fourth surface adjacent to the base substrate, the third surface being The third surface faces the first surface, the fourth surface faces the second surface, the first surface microstructure has a first cross section perpendicular to the base substrate, the first cross section having a first orthogonal projection at the third surface, the length of the first orthogonal projection being shorter than the length of the first surface microstructure at the first cross section, the second surface microstructure has a second cross section perpendicular to the base substrate, the second cross section having a second orthogonal projection at the fourth surface, the length of the second orthogonal projection being shorter than the length of the second surface microstructure at the second cross section.

[0005] In some examples, the distance between the ends of the first cross section and the distance between the ends of the second cross section are each greater than 0.1 microns and less than 1 micron.

[0006] In some examples, the first surface microstructure at least partially overlaps the third surface and the second surface microstructure at least partially overlaps the fourth surface in a direction perpendicular to the base substrate.

[0007] In some examples, at least one of the third surface and the fourth surface is a flat surface.

[0008] In some examples, the area of ​​the orthogonal projection of the first surface microstructure on the third surface is smaller than the surface area of ​​the first surface microstructure, and the area of ​​the orthogonal projection of the second surface microstructure on the fourth surface is smaller than the surface area of ​​the second surface microstructure.

[0009] In some examples, the minimum thickness of the first conductive structure at the first surface microstructure is less than the average thickness of the first conductive structure and greater than 3 / 5 of the average thickness of the first conductive structure.

[0010] In some examples, the first surface microstructure has a first endpoint, a first intermediate point, and a second endpoint in the first cross section, and the second surface microstructure has a third endpoint, a second intermediate point, and a fourth endpoint, wherein the distance between the first intermediate point and the third surface is not equal to any of the distances between the first and second endpoints and the third surface, and the distance between the second intermediate point and the fourth surface is not equal to any of the distances between the third and fourth endpoints and the fourth surface.

[0011] In some examples, the first included angle is greater than 0 degrees and the second included angle is equal to 0 degrees.

[0012] In some examples, the first surface microstructure has a first end point and a second end point in the first cross section, and the second surface microstructure has a third end point and a fourth end point in the second cross section, and the distance from the plate surface of the base substrate to the midpoint of the line segment formed by the first end point and the second end point is different from the distance from the midpoint of the line segment formed by the third end point and the fourth end point.

[0013] In some examples, the distance between the first endpoint and the second endpoint is greater than the distance between the third endpoint and the fourth endpoint.

[0014] In some examples, the display substrate further comprises a first insulating layer located on a side of the first conductive structure closest to the base substrate, the first insulating layer comprising a first portion and a second portion in direct contact with a third surface and a fourth surface of the first conductive structure, respectively, and a minimum thickness of the first portion being smaller than a minimum thickness of the second portion.

[0015] In some examples, the display substrate further comprises a second conductive structure located on a side of the first insulating layer closest to the base substrate, and a first portion of the first insulating layer covers at least a portion of the second conductive structure.

[0016] In some examples, the first surface microstructure does not overlap the second conductive structure in a direction perpendicular to the base substrate.

[0017] In some examples, the first conductive structure is electrically connected to the second conductive structure through a first via that penetrates the first insulating layer, and the first surface microstructure overlaps at least a portion of the first via in a direction perpendicular to the base substrate.

[0018] In some examples, the first insulating layer comprises a first sublayer and a second sublayer stacked together, the second sublayer being farther from the base substrate than the first sublayer, the first sublayer having a first side exposed by the first via, the second sublayer having a second side exposed by the first via, and at least one of the first side and the second side being in direct contact with a third surface of the first conductive structure.

[0019] In some examples, the angle between the first side and the base substrate is larger than the angle between the second side and the base substrate.

[0020] In some instances, the second sub-layer is more dense than the first sub-layer.

[0021] In some examples, the oxygen content of the first surface is higher than the oxygen content of the third surface.

[0022] In some examples, the first surface microstructure has a first end point and a second end point in the first cross section, and the distances between the point of the first cross section closest to the third surface and the first end point and the second end point are not equal.

[0023] In some examples, the first surface microstructure comprises a first concave structure and the second surface microstructure comprises a second concave structure.

[0024] In some examples, the display substrate further comprises a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged as a plurality of pixel columns and a plurality of pixel rows along a first direction and a second direction intersecting the first direction, each of the plurality of sub-pixels comprising a first transistor, a second transistor, a third transistor and a storage capacitor on the base substrate, a first pole of the second transistor being electrically connected to a first capacitor electrode of the storage capacitor and a gate of the first transistor, a second pole of the second transistor being arranged to receive a data signal, a gate of the second transistor being arranged to receive a first control signal, and the second transistor being arranged to receive the first control signal. a first electrode of the first transistor electrically connected to a second capacitor electrode of the storage capacitor and electrically connected to a first electrode of a light-emitting element; a second electrode of the first transistor arranged to receive a first power supply voltage; the first transistor arranged to control a current for driving the light-emitting element by controlling a voltage of the gate of the first transistor; a first electrode of the third transistor electrically connected to the first electrode of the first transistor and the second capacitor electrode of the storage capacitor; and a second electrode of the third transistor arranged to be connected to a detection circuit.

[0025] In some examples, the components in the first direction and the second direction of the center distance between the orthogonal projection of the first surface microstructure on the base substrate and the orthogonal projection of the second surface microstructure on the base substrate are smaller than the average size in the first direction and the second direction of each of the multiple subpixels, respectively.

[0026] In some examples, the sub-pixels in each pixel column emit light of the same color.

[0027] In some examples, the first surface microstructure comprises a first concave structure, the second surface microstructure comprises a second concave structure, and the first concave structure and the second concave structure are arranged along the extension direction of the first conductive structure and toward subpixels of the same color.

[0028] In some examples, the display substrate further comprises an extension portion protruding from the gate of the first transistor, the extension portion extending from the gate of the first transistor along the second direction, at least partially overlapping with and electrically connected to the first pole of the second transistor in a direction perpendicular to the base substrate.

[0029] In some examples, the active layer of the second transistor comprises a first pole contact region, a second pole contact region, and a channel region located between the first pole contact region and the second pole contact region, and a first pole of the second transistor is electrically connected to the first pole contact region, the extension, and the first capacitor electrode, respectively, through a second via.

[0030] In some examples, the second via extends along the first direction and exposes at least a portion of a surface of the extension and two side surfaces opposing each other in the first direction.

[0031] In some examples, the extension portion divides the second via into a first groove and a second groove, a first pole of the second transistor fills the first groove and the second groove and covers the two side surfaces of the extension portion, the first pole of the second transistor has a first portion, a second portion and a third portion, the second portion covers the surface of the extension portion, the first portion covers the first groove, the third portion covers the second groove, and the first portion and the third portion further each cover the two side surfaces of the extension portion.

[0032] In some examples, the first conductive structure is a first pole of the second transistor, and the first surface microstructure and the second surface microstructure are both located on a third portion of the first pole of the second transistor.

[0033] In some examples, the size of the first surface microstructure in the first direction is less than one-tenth the maximum size of the third portion in the first direction.

[0034] In some examples, the size of the first surface microstructure in the first direction is less than one-tenth the maximum size of an orthogonal projection of the second via on the base substrate in the first direction.

[0035] In some examples, each of the plurality of subpixels further comprises the light-emitting element, wherein the light-emitting element comprises a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the first electrode being closer to the base substrate than the second electrode, and the first electrode of the light-emitting element being electrically connected to a first pole of a first transistor of the subpixel in which the light-emitting element is located via a third via.

[0036] In some examples, the first electrode of the light-emitting element comprises a first electrode portion, a second electrode portion, and a third electrode portion connected sequentially in the first direction, the first electrode portion is used to electrically connect to the first pole of the corresponding first transistor and overlaps with the first pole of the corresponding first transistor in a direction perpendicular to the base substrate, and the third electrode portion of the light-emitting element at least partially overlaps with the opening region of the light-emitting element in a direction perpendicular to the base substrate.

[0037] In some examples, the sum of the maximum size of the first electrode portion in the first direction and the maximum size of the second direction is smaller than the sum of the maximum size of the third electrode portion in the first direction and the maximum size of the second electrode portion in the second direction, and the sum of the maximum size of the second electrode portion in the first direction and the maximum size of the third electrode portion in the first direction and the maximum size of the third electrode portion in the second direction is smaller than the sum of the maximum size of the third electrode portion in the first direction and the maximum size of the third electrode portion in the second direction.

[0038] In some examples, the display substrate comprises a plurality of first surface microstructures and a plurality of second surface microstructures, a portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures overlap with the first electrode portion in a direction perpendicular to the base substrate, and another portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures overlap with the third electrode portion in a direction perpendicular to the base substrate, and the distribution density of the first surface microstructures and the second surface microstructures overlapping with the first electrode portion is higher than the distribution density of the first surface microstructures and the second surface microstructures overlapping with the third electrode portion.

[0039] In some examples, the average size in the second direction of the second electrode portion of the first electrode of the light-emitting element is smaller than the average size in the second direction of the first electrode portion, and is also smaller than the average size in the second direction of the third electrode portion.

[0040] In some examples, the plurality of pixel rows comprises a first pixel row, the first pixel row is divided into a plurality of pixel portions, each pixel portion comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the second direction, the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged to emit light of three primary colors, respectively, the display substrate further comprises a first scan line extending along the second direction, the first scan line is electrically connected to gates of second transistors in the first sub-pixel, the second sub-pixel, and the third sub-pixel to provide the first control signal.

[0041] In some examples, the first scan line overlaps with the second electrode portion of the first electrode of the light emitting element of the first sub-pixel in a direction perpendicular to the base substrate.

[0042] In some examples, the display substrate further includes a color filter layer located on a side of the first electrode of the light-emitting element that is closest to the base substrate, and the color filter layer includes a plurality of color filter portions that respectively correspond to the first sub-pixel, the second sub-pixel, and the third sub-pixel, and light emitted from the first sub-pixel, the second sub-pixel, and the third sub-pixel passes through the corresponding color filter portions and is emitted from the display substrate to form display light.

[0043] In some examples, the color filter portion corresponding to the first sub-pixel and the color filter portion corresponding to the second sub-pixel both overlap the second surface microstructure in a direction perpendicular to the base substrate.

[0044] In some examples, in a direction perpendicular to the base substrate, each of the plurality of color filter portions overlaps with a third electrode portion of a first electrode of a light-emitting element of a corresponding subpixel, and does not overlap with a first electrode portion of a first electrode of a light-emitting element of the corresponding subpixel.

[0045] In some examples, the first scanning line is located on the side of the color filter layer closest to the base substrate, and in a direction perpendicular to the base substrate, the portion of the second electrode portion of the first electrode of the light-emitting element of the first sub-pixel that overlaps with the first scanning line further overlaps with the color filter portion corresponding to the first sub-pixel.

[0046] In some examples, the first scan line comprises a first portion and a second portion that are alternately connected, and the second portion has a ring structure.

[0047] In some examples, in a direction perpendicular to the base substrate, a first electrode of the light-emitting element of the first sub-pixel overlaps a first portion of the first scan line but does not overlap a second portion of the first scan line.

[0048] In some examples, the display substrate further includes a plurality of first signal lines extending along the first direction, and in a direction perpendicular to the base substrate, the plurality of first signal lines overlap with second portions of the first scanning lines to define a plurality of first hollow regions arranged along the second direction.

[0049] In some examples, the geometric centers of the corresponding first hollow regions in each pixel portion are not aligned in a straight line.

[0050] In some examples, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first subpixel overlaps with at least one of the plurality of first hollow regions, and the color filter portion corresponding to the second subpixel does not overlap with any of the plurality of first hollow regions.

[0051] In some examples, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first subpixel overlaps one of the plurality of first hollow regions and has a first overlapping area, and the color filter portion corresponding to the second subpixel overlaps another of the plurality of first hollow regions and has a second overlapping area, the first overlapping area and the second overlapping area being different.

[0052] In some examples, the absolute value of the difference between the first overlapping area and the second overlapping area is greater than (n*λ), where λ is the greater of the wavelengths of light emitted by the first and second sub-pixels.

[0053] In some examples, the display substrate comprises a plurality of first surface microstructures and a plurality of second surface microstructures, some of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with a first portion of the first scan line in a direction perpendicular to the base substrate, and other portions of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with a second portion of the first scan line in a direction perpendicular to the base substrate, and the distribution density of the first surface microstructures and the second surface microstructures overlapping with the second portion of the first scan line in the direction perpendicular to the base substrate is higher than the distribution density of the first surface microstructures and the second surface microstructures overlapping with the first portion of the first scan line.

[0054] In some examples, the first overlap area is larger than the area of ​​an orthogonal projection of each of the plurality of first surface microstructures or the second surface microstructures onto the base substrate, and the second overlap area is larger than the area of ​​an orthogonal projection of each of the plurality of first surface microstructures or the second surface microstructures onto the base substrate.

[0055] In some examples, the pixel portion further includes a fourth sub-pixel arranged to emit white light, and among the plurality of first hollow regions, none of the first hollow regions adjacent to the fourth sub-pixel overlaps with the color filter layer in a direction perpendicular to the base substrate.

[0056] In some examples, the plurality of first signal lines comprise a plurality of data lines connected in one-to-one correspondence to the plurality of pixel columns, and for the first pixel row, the plurality of data lines are divided into a plurality of data line groups corresponding one-to-one to the plurality of pixel portions, each data line group comprising a first data line, a second data line, and a third data line connected to the first sub-pixel, the second sub-pixel, and a third sub-pixel, respectively, and for each of the pixel portions, the first data line, the second data line, and the third data line connected to the corresponding pixel portion are all located between the first sub-pixel and the third sub-pixel.

[0057] In some examples, the display substrate further includes a plurality of power supply lines extending along the first direction, the plurality of power supply lines being arranged to provide the first power supply voltage to the plurality of sub-pixels, and at least one pixel column being interposed between each of the plurality of power supply lines and any one of the plurality of data lines.

[0058] In some examples, the display substrate comprises a plurality of first surface microstructures and a plurality of second surface microstructures, a portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures being distributed on the plurality of data lines, and another portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures being distributed on the plurality of power lines, and the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of data lines is higher than the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of power lines.

[0059] In some examples, the second subpixel is directly adjacent to the third subpixel, the third subpixel has a first side and a second side opposite to each other in the second direction, and the second data line and the third data line are located on the first side of the third subpixel and between the second subpixel and the third subpixel.

[0060] In some examples, the second electrode portion of the first electrode of the light-emitting element of the third subpixel is recessed in a direction away from the second side of the third subpixel with respect to the first electrode portion and the third electrode portion.

[0061] In some examples, the second data line and the third data line each at least partially overlap the color filter layer in a direction perpendicular to the base.

[0062] In some examples, the pixel unit further includes a fourth sub-pixel arranged to emit white light, and each of the data line groups further includes a fourth data line connected to the fourth sub-pixel; The fourth data line does not overlap the color filter layer in a direction perpendicular to the base substrate.

[0063] In some examples, the plurality of pixel rows further includes a second pixel row immediately adjacent to the first pixel row in the first direction, the second pixel row including a fifth sub-pixel, a sixth sub-pixel, and a seventh sub-pixel arranged sequentially along the second direction, the fifth sub-pixel being located in the same pixel column as the first sub-pixel, the sixth sub-pixel being located in the same pixel column as the second sub-pixel, and the seventh sub-pixel being located in the same pixel column as the third sub-pixel.

[0064] In some examples, the color filter portion corresponding to the first sub-pixel has a side adjacent to the fifth sub-pixel, and the side is parallel to the second direction.

[0065] In some examples, the display substrate further includes a second scan line extending along the second direction, the second scan line electrically connected to gates of third transistors in the fifth, sixth, and seventh sub-pixels to provide the second control signal.

[0066] In some examples, the second scan line comprises a first portion and a second portion that are alternately connected, and the second portion has a ring structure.

[0067] In some examples, in a direction perpendicular to the base substrate, the plurality of first signal lines overlap with second portions of the second scanning lines to define a plurality of second hollow regions arranged sequentially along the second direction.

[0068] In some examples, the first conductive structure is one of the plurality of first signal lines, the first surface microstructure and the second surface microstructure are located on the first signal line, and the first surface microstructure at least partially overlaps a second hollow region corresponding to the first signal line in a direction perpendicular to the base substrate.

[0069] In some examples, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first subpixel overlaps with one second hollow region of the plurality of second hollow regions and has a third overlapping area, the color filter portion corresponding to the second subpixel overlaps with another second hollow region of the plurality of second hollow regions and has a fourth overlapping area, and the color filter portion corresponding to the third subpixel overlaps with yet another second hollow region of the plurality of second hollow regions and has a fifth overlapping area, and the third overlapping area, the fourth overlapping area, and the fifth overlapping area are all different.

[0070] In some examples, the second pole of the third transistor is electrically connected to a detection portion extending along the second direction through a fourth via, and the detection portion is electrically connected to a detection line extending along the first direction, thereby connecting the second pole of the third transistor to the detection circuit through the detection portion and the detection line.

[0071] In some examples, the first conductive structure is a second pole of the third transistor, the first surface microstructure and the second surface microstructure are located on the second pole of the third transistor, and the first surface microstructure at least partially overlaps the fourth via in a direction perpendicular to the base substrate.

[0072] In some examples, the active layer of the third transistor comprises a first pole contact region, a second pole contact region, and a channel region located between the first pole contact region and the second pole contact region, and the first pole of the third transistor is electrically connected to the first pole contact region of the third transistor through a fifth via.

[0073] In some examples, the first conductive structure is a first pole of the third transistor, the first surface microstructure and the second surface microstructure are located on the first pole of the third transistor, and the first surface microstructure at least partially overlaps the fifth via in a direction perpendicular to the base substrate.

[0074] At least one embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a first conductive structure located on the base substrate, the first conductive structure having a first surface and a second surface away from the base substrate, the first surface and the second surface being made of the same material, a first surface microstructure being disposed on the first surface, and a second surface microstructure being disposed on the second surface, the first surface microstructure having a first cross section perpendicular to the base substrate, the second surface microstructure having a second cross section perpendicular to the base substrate, the first surface microstructure having a first end point and a second end point on the first cross section, and the second surface microstructure having a third end point and a fourth end point on the second cross section, and the distances of the midpoint of the line connecting the first end point and the second end point and the midpoint of the line connecting the third end point and the fourth end point relative to the surface of the base substrate are different.

[0075] In some examples, the minimum thickness of the first conductive structure at the first surface microstructure is less than the average thickness of the first conductive structure and greater than 3 / 5 of the average thickness of the first conductive structure.

[0076] In some examples, the first conductive structure further comprises a third surface and a fourth surface adjacent to the base substrate, and in a direction perpendicular to the base substrate, the first surface microstructure at least partially overlaps the third surface and the second surface microstructure at least partially overlaps the fourth surface.

[0077] In some examples, at least one of the third surface and the fourth surface is a flat surface.

[0078] In some examples, the area of ​​the orthogonal projection of the first surface microstructure on the third surface is smaller than the surface area of ​​the first surface microstructure, and the area of ​​the orthogonal projection of the second surface microstructure on the fourth surface is smaller than the surface area of ​​the second surface microstructure.

[0079] In some examples, the first surface microstructure further has a first intermediate point located between the first endpoint and the second endpoint in the first cross section, and the second surface microstructure further has a second intermediate point located between the third endpoint and the fourth endpoint in the second cross section, wherein the distance between the first intermediate point and the third surface is not equal to any of the distances between the first endpoint and the second endpoint and the third surface, and the distance between the second intermediate point and the fourth surface is not equal to any of the distances between the third endpoint and the fourth endpoint and the fourth surface.

[0080] In some examples, the first surface and a plane of the base substrate form a first included angle, and the second surface and a plane of the base substrate form a second included angle that is different from the first included angle.

[0081] In some examples, the first included angle is greater than 0 degrees and the second included angle is equal to 0.

[0082] In some examples, the display substrate further comprises a first insulating layer located on a side of the first conductive structure closest to the base substrate, the first insulating layer comprising a first portion and a second portion in direct contact with a third surface and a fourth surface of the first conductive structure, respectively, and a minimum thickness of the first portion being smaller than a minimum thickness of the second portion.

[0083] In some examples, the display substrate further comprises a second conductive structure located on a side of the first insulating layer closest to the base substrate, and a first portion of the first insulating layer covers at least a portion of the second conductive structure.

[0084] In some examples, the first surface microstructure does not overlap the second conductive structure in a direction perpendicular to the base substrate.

[0085] In some examples, the first conductive structure is electrically connected to the second conductive structure through a first via that penetrates the first insulating layer, and the first surface microstructure overlaps at least a portion of the first via in a direction perpendicular to the base substrate.

[0086] In some examples, the first insulating layer comprises a first sublayer and a second sublayer stacked together, the second sublayer being farther from the base substrate than the first sublayer, the first sublayer having a first side exposed by the first via, the second sublayer having a second side exposed by the first via, and at least one of the first side and the second side being in direct contact with a third surface of the first conductive structure.

[0087] In some examples, the angle between the first side and the base substrate is larger than the angle between the second side and the base substrate.

[0088] In some instances, the second sub-layer is more dense than the first sub-layer.

[0089] In some examples, the oxygen content of the first surface is higher than the oxygen content of the third surface.

[0090] At least one embodiment of the present disclosure further provides a display device, comprising a display substrate according to any one of the above embodiments.

[0091] In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. Obviously, the drawings described below do not limit the present invention, but only relate to some embodiments of the present invention. [Brief explanation of the drawings]

[0092] [Figure 1A] FIG. 1A is a schematic diagram 1 of a display substrate according to at least one embodiment of the present disclosure. [Figure 1B] FIG. 1B is a schematic diagram 2 of a display substrate according to at least one embodiment of the present disclosure. [Figure 2A] FIG. 2A is a schematic diagram 3 of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a pixel circuit diagram 1 of a display substrate according to at least one embodiment of the present disclosure. [Figure 2C]FIG. 2C is a pixel circuit diagram 2 of a display substrate according to at least one embodiment of the present disclosure. [Figure 2D] 2D to 2F are signal timing diagrams of a method for driving a pixel circuit according to an embodiment of the present disclosure. [Figure 2E] 2D to 2F are signal timing diagrams of a method for driving a pixel circuit according to an embodiment of the present disclosure. [Figure 2F] 2D to 2F are signal timing diagrams of a method for driving a pixel circuit according to an embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram 4 of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a cross-sectional view taken along the line II' in FIG. 3A. [Figure 3C] 3C to 3E are schematic diagrams of display substrates according to other embodiments of the present disclosure. [Figure 3D] 3C to 3E are schematic diagrams of display substrates according to other embodiments of the present disclosure. [Figure 3E] 3C to 3E are schematic diagrams of display substrates according to other embodiments of the present disclosure. [Figure 4A] FIG. 4A is a schematic plan view of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic plan view of a semiconductor layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 4C] FIG. 4C is a schematic plan view of a second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 4D] FIG. 4D is a schematic plan view of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] FIG. 5A is a schematic diagram 1 of a display panel in accordance with at least one embodiment of the present disclosure. [Figure 5B] FIG. 5B is a schematic diagram 2 of a display panel in accordance with at least one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0093] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without creative work fall within the scope of protection of the present disclosure.

[0094] Unless otherwise defined, technical or scientific terms used in this disclosure have common meanings that can be understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but merely serve to distinguish between different components. Similarly, similar terms such as "one," "an," or "the" do not limit the number but mean the presence of at least one. Similar terms such as "comprise" or "include" refer to the element or component described before the term including the element or component listed thereafter and their equivalents, without excluding other elements or components. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but may also include electrical connections, whether directly or indirectly connected. Terms such as "top," "bottom," "left," "right," and the like are used only to indicate relative positions, and if the absolute position of the described object changes, the relative positions may change accordingly.

[0095] As display panels become thinner and lighter, especially in large display applications, they are prone to failure due to external stress. For example, during manufacturing or use, the signal lines of the display panel are prone to break under the action of external stress, resulting in panel failure.

[0096] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a first conductive structure located on the base substrate, the first conductive structure having a first surface and a second surface away from the base substrate, the first surface and the second surface being made of the same material, the first surface and a plate surface of the base substrate forming a first included angle, and the second surface and a plate surface of the base substrate forming a second included angle different from the first included angle, a first surface microstructure disposed on the first surface, a second surface microstructure disposed on the second surface, and the first conductive structure further comprising a third surface and a fourth surface adjacent to the base substrate, the third surface facing the first surface and the fourth surface facing the second surface, the first surface microstructure having a first cross section on a first projection plane perpendicular to the plate surface of the base substrate, the first cross section having a first orthogonal projection on the third surface, the length of the first orthogonal projection being shorter than the length of the first cross section, the second surface microstructure having a second cross section on the first projection plane, the second cross section having a second orthogonal projection on the fourth surface, the length of the second orthogonal projection being shorter than the length of the second cross section.

[0097] The display substrate of the embodiment of the present disclosure has a first surface microstructure and a second surface microstructure respectively arranged on the first surface and the second surface of the first conductive structure, thereby releasing stress of the first conductive structure at different angles or in different directions, and avoiding failure of the panel caused by stress concentration.

[0098] The first and second surface microstructures in the embodiments of the present disclosure can be realized as a number of specific structures, and the present disclosure is not limited thereto. For example, the first stress structure and the second surface microstructure can be grooves, protrusions, or through-holes, which can effectively increase the surface area of ​​the conductive structure, thereby helping to relieve stress.

[0099] 1A shows a schematic diagram of a display substrate 10 according to at least one embodiment of the present disclosure. As shown in FIG. 1A , the display substrate 10 includes a first conductive structure 110 disposed on a base substrate 101. The first conductive structure 110 has a first surface 111 and a second surface 112 facing away from the base substrate 101. The first surface 111 and the surface of the base substrate 101 form a first included angle α, and the second surface 112 and the surface of the base substrate 101 form a second included angle different from the first included angle. For example, the first included angle α is greater than 0, i.e., the first surface 111 is an oblique surface. For example, the second included angle is 0, i.e., the second surface 112 is parallel to the surface of the base substrate. A first surface microstructure 11 is disposed on the first surface 111, and a second surface microstructure 12 is disposed on the second surface 112.

[0100] For example, the maximum size of the orthogonal projection of the first surface microstructure 11 on the first surface 111 is larger than the maximum size of the orthogonal projection of the second surface microstructure 12 on the second surface 112. For example, the maximum size of the first surface microstructure 11 in a direction perpendicular to the first surface 111 is larger than the maximum size of the second surface microstructure 12 in a direction perpendicular to the second surface 112. Since the first surface 111 is more inclined than the second surface 112 with respect to the base substrate and stress is more concentrated, setting the size of the first surface microstructure 11 to be larger helps to release stress more uniformly.

[0101] For example, the maximum size of the first surface microstructure 11 in orthogonal projection on the first surface 111 is 0.15 to 0.35 microns, e.g., 0.22 to 0.28 microns, and the maximum size of the first surface microstructure 11 in a direction perpendicular to the first surface 111 is in the range of 0.03 to 0.1 microns, e.g., 0.05 to 0.08 microns. For example, the line width of the first conductive structure is in the range of 5 to 30 microns. For example, the maximum size of the first surface microstructure 11 in a direction perpendicular to the first surface 111 is 5% to 20% of the average thickness of the first conductive structure.

[0102] For example, the maximum size of the second surface microstructure 12 in the orthogonal projection on the second surface 112 is 0.1 to 0.2 microns, e.g., 0.12 to 0.15 microns, and the maximum size of the second surface microstructure 12 in the direction perpendicular to the second surface 112 is in the range of 0.02 to 0.08 microns, e.g., 0.03 to 0.07 microns. The linewidth of the first conductive structure is in the range of 5 to 30 microns. For example, the maximum size of the second surface microstructure 12 in the direction perpendicular to the second surface 112 is 5% to 20% of the average thickness of the first conductive structure.

[0103] 1A, the first conductive structure 110 further includes a third surface 113 and a fourth surface 114 adjacent to the base substrate 101, the third surface 113 facing the first surface 111, and the fourth surface 114 facing the second surface 112.

[0104] The first surface microstructure 11 has a first cross section 11a perpendicular to the base substrate, and the second surface microstructure has a second cross section 12a perpendicular to the base substrate. For example, as shown in FIG. 1A , the first cross section 11a and the second cross section 12a are both located within the plane of the paper. The first cross section 11a has a first orthogonal projection (C1C2) on the third surface 113, and the length of the first orthogonal projection is shorter than the length of the first surface microstructure 11 at the first cross section 11a, i.e., the length of the curve A1A2. The second surface microstructure 12 has a second cross section 12a on the first projection plane, and the second cross section 12a has a second orthogonal projection (D1D2) on the fourth surface 114, and the length of the second orthogonal projection is shorter than the length of the second surface microstructure 12 at the second cross section 12a, i.e., the length of the curve B1B2.

[0105] The curve A1A2 or B1B2 can effectively increase the surface area of ​​the first surface microstructure 11 or the second surface microstructure 12, thereby improving the stress relief ability of the first surface microstructure 11 and the second surface microstructure 12. For example, the curve A1A2 and / or the curve B1B2 may include an arch, thereby releasing stress more uniformly.

[0106] The first cross section 11a and the second cross section 12a are both projected as linear structures (one-dimensional structures), and the linear structures are related to the shapes of the third and fourth surfaces. As shown in Figure 1A, if the third and fourth surfaces are flat, the first and second orthogonal projections are straight lines, and if the third and fourth surfaces are curved, the first and second orthogonal projections are curved lines.

[0107] For example, when the projection surface is a curved surface, the orthogonal projection of a structure on the projection surface is the projection of the structure formed on the projection surface along the direction of the normal to each point on the projection surface.

[0108] For example, at least one of the third surface 113 and the fourth surface 114 is a flat surface. As shown in Figure 1A, the third surface 113 and the fourth surface 114 are both flat surfaces. In a direction perpendicular to the base substrate 101, the first surface microstructure 11 at least partially overlaps the third surface 113, and the second surface microstructure 12 at least partially overlaps the fourth surface 114.

[0109] The flatness of the third surface 113 and the fourth surface 114 is relative to the scale of the first surface microstructure 11 or the second surface microstructure 12, and the judgment scale of the flatness of the third surface 113 and the fourth surface 114 should be at the same level as the scale of the first surface microstructure 11 or the second surface microstructure 12. For example, the judgment scale in the direction parallel to the third surface 113 or the fourth surface 114 is at the 0.1 micron level, and the judgment scale in the direction perpendicular to the third surface 113 or the fourth surface 114 is at the 0.01 micron level. For example, if the third surface 113 / fourth surface 114 has an uneven structure whose size reaches the 0.1 micron level in the parallel direction and whose size reaches the 0.01 micron level in the perpendicular direction, the third surface 113 / fourth surface 114 is judged to be an uneven surface.

[0110] For example, the area of ​​the orthogonal projection of the first surface microstructure 11 on the third surface 113 is smaller than the surface area of ​​the first surface microstructure, and the area of ​​the orthogonal projection of the second surface microstructure 12 on the fourth surface 114 is smaller than the surface area of ​​the second surface microstructure. Such an arrangement increases the surface area of ​​the first conductive structure, thereby helping to relieve stress.

[0111] For example, along the extension direction of the first conductive structure, the first surface microstructure has a first end point, a first intermediate point, and a second end point, and the second surface microstructure has a third end point, a second intermediate point, and a fourth intermediate point, and the distance between the first intermediate point and the third surface is not equal to any of the distances between the first end point and the second end point and the third surface, and the distance between the second intermediate point and the fourth surface is not equal to any of the distances between the third end point and the fourth end point and the fourth surface.

[0112] 1A, the first surface microstructure 11 and the second surface microstructure 12 comprise a first concave structure and a second concave structure, respectively, where the first concave structure is recessed relative to a reference plane on which the first surface 111 lies and the second concave structure is recessed relative to a reference plane on which the second surface 112 lies. The concave structures increase the surface area of ​​the first conductive structure 110, thereby helping to relieve stress and reducing the risk of the first conductive structure 110 breaking under stress.

[0113] 1A, the first concave structure and the second concave structure face in different directions. For example, the orientation of the first concave structure may be defined as a direction perpendicular to the first surface 111, and the orientation of the second concave structure may be defined as a direction perpendicular to the second surface 112. This helps to distribute stress in the first conductive structure 110 and further reduce the risk of failure. For example, the maximum depth of the concave structure is one-tenth to two-fifths of the thickness of the first conductive structure at the concave structure.

[0114] For example, the minimum thickness of the first conductive structure at the first surface microstructure is less than the average thickness of the first conductive structure and greater than 3 / 5 of the average thickness of the first conductive structure.

[0115] 1A, the first surface microstructure 11 has a first end point A1 and a second end point A2 on the first cross section 11a, and the second surface microstructure 12 has a third end point B1 and a fourth end point B2 on the second cross section 12a. The distance from the plate surface of the base substrate 101 to the midpoint (not shown) of the line segment between the first end point A1 and the second end point A2 is different from the distance from the plate surface of the base substrate 101 to the midpoint (not shown) of the line segment between the third end point B1 and the fourth end point B2. With this arrangement, the first surface microstructure 11 and the second surface microstructure 12 have different heights relative to the base substrate, which helps to further distribute stress in the first conductive structure 110 and reduce the risk of failure.

[0116] For example, the distance L1 between the first end point A1 and the second end point A2 is greater than the distance L2 between the third end point B1 and the fourth end point B2. For example, the maximum size of the first concave structure in a direction perpendicular to the first surface 111 is greater than the maximum size of the second concave structure in a direction perpendicular to the second surface 112.

[0117] For example, the distance L1 between the first end point A1 and the second end point A2 and the distance L2 between the third end point B1 and the fourth end point B2 are greater than 0.1 microns and less than 1 micron, respectively.

[0118] For example, the distance L1 between the first end point A1 and the second end point A2 is greater than the distance L2 between the third end point B1 and the fourth end point B2, that is, the length of the first surface microstructure located on the slope is longer.

[0119] For example, the distance L1 between the first end point A1 and the second end point A2 is 0.15 to 0.35 microns, e.g., 0.22 to 0.28 microns, and the maximum size of the first concave structure in the direction perpendicular to the first surface 111 is 0.03 to 0.1 microns, e.g., 0.05 to 0.08 microns. Within this size range, not only can the conductive structure be prevented from breaking, but also stress can be sufficiently released.

[0120] For example, the distance L2 between the third end point B1 and the fourth end point B2 is 0.1 to 0.2 microns, for example, 0.12 to 0.15 microns, and the maximum size of the second concave structure in the direction perpendicular to the second surface 112 is in the range of 0.02 to 0.08 microns, for example, 0.03 to 0.07 microns.

[0121] Since the first surface 111 is more inclined than the second surface 112 relative to the base substrate, and stress is more concentrated thereon, the larger size of the first concave structure helps to release the stress more uniformly. Furthermore, not setting the above size for the first concave structure and the second concave structure not only ensures that the conductive structure does not break, but also allows for sufficient stress release.

[0122] In at least one embodiment, as shown in FIG. 1A, the first surface microstructure 11 has a first end point A1 and a second end point A2 on the first cross section 11a, and the second surface microstructure 12 has a third end point B1 and a fourth end point B2 on the second cross section 12a, and the distances of the midpoint of the line connecting the first end point A1 and the second end point A2 and the midpoint of the line connecting the third end point B1 and the fourth end point B2 relative to the plate surface of the base substrate 101 are different.

[0123] This arrangement allows the first surface microstructure 11 and the second surface microstructure 12 to have different heights relative to the base substrate, further distributing stress in the first conductive structure 110 and reducing the risk of failure. For example, the roughness of the first surface 111 is higher than that of the third surface 113, and the roughness of the second surface 112 is higher than that of the fourth surface 114. This arrangement improves direct adhesion between the first conductive structure 110 and the insulating layer thereon and prevents the insulating layer from peeling off. For example, during the manufacturing process, the surface of the first conductive structure 110 facing away from the base substrate is slightly oxidized to improve the surface roughness, thereby improving the roughness of the first and second surfaces. For example, the oxygen content of the first surface 111 is higher than that of the third surface 113, and the oxygen content of the second surface 112 is higher than that of the fourth surface 114.

[0124] For example, as shown in FIG. 1A , the display substrate 10 further includes a first insulating layer 103 located on the side of the first conductive structure 110 closest to the base substrate 101. The first insulating layer 103 includes a first portion 103a and a second portion 103b that directly contact the third surface 113 and the fourth surface 114 of the first conductive structure 110, respectively. The minimum thickness d1 of the first portion 103a is smaller than the minimum thickness d2 of the second portion 103b. Note that, as shown in FIG. 1A , the "thickness" here refers to the size of the first insulating layer 103 in a direction perpendicular to the film layer surface. Because the third surface 113 is inclined, this arrangement helps to make the first portion 103a of the first insulating layer 103 thinner, reducing the difficulty of climbing the first portion 103a of the first insulating layer 103 and thereby reducing the risk of fracture of the first conductive structure 110.

[0125] For example, the point of the first surface microstructure closest to the third surface is not the first or second end point, and the distances to the first and second end points are not equal.

[0126] For example, as shown in FIG. 1A, the first concave structure has a smooth curved surface, i.e., the included angle between the tangent of the curved surface and the base substrate 101 changes continuously, and the rate of change of the included angle between the tangent of the curved surface and the base substrate 101 gradually increases in the direction away from the base substrate 101, i.e., the first concave structure is asymmetric, and the inclination angle on the upstream side (the side away from the base substrate) is smaller than the inclination angle on the downstream side (the side close to the base substrate).

[0127] Because the upstream concave surface more easily reflects light from above, this arrangement allows the first conductive structure to better reflect light emitted by the light emitting element located on the side of the first conductive structure away from the base substrate, thereby improving light utilization efficiency, which will be described in detail below with reference to the specific structure of the display substrate.

[0128] 1A, the second concave structure has a smoothly curved surface, and the curved surface is, for example, a symmetrical structure, that is, the included angle between the tangent of the curved surface and the base substrate 101 changes continuously and the rate of change is constant. Such an arrangement helps to uniformly release the stress on the surface.

[0129] 1A, the display substrate 10 further includes a second conductive structure 120 located on a side of the first insulating layer 103 that is closer to the base substrate, for example, the first insulating layer 103 separating the first conductive structure 110 and the second conductive structure 120. For example, the first insulating layer 103 is formed on the second conductive structure 102, and the first surface 111 of the first insulating layer 103 is formed as a slope due to the presence of the second conductive structure 102.

[0130] For example, the first surface microstructure 11 does not overlap the second conductive structure 120 in a direction perpendicular to the base substrate 101. Because stress in the first surface microstructure 11 is concentrated, particularly in the deepest part of the first surface microstructure 11, arranging the first surface microstructure 11 so that it does not overlap the second conductive structure 120 reduces the risk of a short circuit between the first conductive structure 110 and the second conductive structure 120 caused by fracture of the first surface microstructure 11.

[0131] 1A, the display substrate 10 further includes a buffer layer 102 located on the side of the second conductive structure 120 closest to the base substrate, for example, the buffer layer 102 directly contacts the base substrate 101. The buffer layer 102 serves to improve the flatness of the base substrate 101 and to improve the adhesion of the second conductive structure 120 to the base substrate 101. When the base substrate 101 is an organic flexible substrate, the buffer layer 102 can also effectively block external oxygen or moisture to protect the circuit structure on the substrate.

[0132] 1B is a schematic diagram of a display substrate according to another embodiment of the present disclosure, showing only the first surface microstructure 11. As shown in FIG. 1B, the first conductive structure 110 is electrically connected to the second conductive structure 120 through a via 130 in the insulating layer 103, and the via 130 at least partially overlaps the first surface microstructure 11 in a direction perpendicular to the base substrate 101.

[0133] Since stress is concentrated at the vias, arranging the surface microstructure 11 corresponding to the vias 130 helps to relieve stress at the vias and reduce the risk of breakage.

[0134] 1B , the first insulating layer 103 includes a first sublayer 131 and a second sublayer 132 stacked together, with the second sublayer 132 being farther from the base substrate 101 than the first sublayer 131. A via 130 penetrates the first sublayer 131 and the second sublayer 132. The first sublayer 131 includes a first side surface 131a exposed by the via 130, and the second sublayer 132 includes a second side surface 132a exposed by the via 130. At least one of the first side surface 131a and the second side surface 132a is in direct contact with the third surface 133 of the first conductive structure 130. As shown in FIG. 1B , the first side surface 131a is in direct contact with the third surface 133 of the first conductive structure 130.

[0135] As shown in FIG. 1B, the included angle (tilt angle) between the first side surface 131a and the base substrate 101 is β1, and the included angle between the second side surface 132a and the base substrate 101 is β2, where β1 is smaller than β2.

[0136] This arrangement, on the one hand, reduces the slope of the via 130 in the first insulating layer 103, thereby preventing the risk of the via being cut off due to being too sloped, and, on the other hand, prevents the via from being too gentle and taking up too much space.

[0137] For example, during the manufacturing process, the first sub-layer 131 may be formed by a high temperature deposition process and the second sub-layer 132 may be formed by a low temperature deposition process, so that the density of the second sub-layer 132 is higher than that of the first sub-layer 131, and then the first insulating layer is etched by a dry etching process, so that the tilt angle of the first sub-layer 131 is smaller than that of the second sub-layer 132.

[0138] 2A is a block diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 2A, a display substrate 10 includes a plurality of sub-pixels 100 arranged in an array. For example, each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. For example, the display substrate is an organic light-emitting diode (OLED) display substrate, and the light-emitting element is an OLED. The display substrate may further include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the sub-pixels to drive them. If necessary, the display substrate may further include power lines, detection lines, etc.

[0139] The pixel circuit includes a driving sub-circuit for driving the light-emitting element to emit light, and a detecting sub-circuit for detecting the electrical characteristics of the sub-pixel to realize external compensation. The embodiments of the present disclosure do not limit the specific structure of the pixel circuit.

[0140] 2B shows a schematic diagram of a 3T1C pixel circuit for the display substrate. If necessary, the pixel circuit may further include a compensation circuit, a reset circuit, etc., and the embodiments of the present disclosure are not limited thereto.

[0141] 2A and 2B, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. A first electrode of the second transistor T2 is electrically connected to a first capacitor electrode of the storage capacitor Cst and the gate of the first transistor T1, a second electrode of the second transistor T2 is arranged to receive a data signal GT, the second transistor T2 is arranged to write the data signal DT to the gate of the first transistor T1 and the storage capacitor Cst in response to a first control signal G1, a first electrode of the first transistor T1 is electrically connected to a second capacitor electrode of the storage capacitor Cst and is arranged to be electrically connected to a first electrode of the light-emitting element, and a second electrode of the first transistor T1 is arranged to receive a first power supply voltage V1 (e.g., a high power supply voltage VDD), and The first transistor T1 is configured to control the current for driving the light-emitting element by controlling the gate voltage of the first transistor T1, the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode of the storage capacitor Cst, and the second electrode of the third transistor T3 is connected to the detection line 230 and then to an external detection circuit 21, which is configured to detect electrical characteristics of a sub-pixel in response to a second control signal G2 to realize external compensation, such as the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element, etc. The external detection circuit 21 is a common circuit, such as a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and will not be described again in the embodiments of the present disclosure.

[0142] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure will be described using thin film transistors as examples. The source and drain of the transistors used herein may have symmetrical structures, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, to distinguish between the two poles of a transistor other than the gate, one pole is referred to as the first pole and the other pole as the second pole. Furthermore, transistors can be classified as N-type transistors or P-type transistors according to their characteristics. When a transistor is a P-type transistor, its on-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage) and its off-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage). When a transistor is an N-type transistor, its on-voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltage) and its off-voltage is a low-level voltage (e.g., 0 V, −5 V, −10 V, or other suitable voltage). In the following description, the transistor in FIG. 2B is an N-type transistor, but this is not intended to limit the present disclosure.

[0143] Hereinafter, the operating principle of the pixel circuit shown in FIG. 2B will be explained with reference to the signal timing diagrams shown in FIGS. 2D to 2F. FIG. 2D shows a signal timing diagram during the display process of the pixel circuit, and FIGS. 2E and 2F show signal timing diagrams during the detection process of the pixel circuit.

[0144] For example, as shown in Figure 2D, the display process of each frame image includes a data writing and reset stage 1 and a light emitting stage 2. Figure 2C shows the timing waveforms of each signal in each stage. One operation process of the 3T1C pixel circuit includes: In the data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both ON signals, the second transistor T2 and the third transistor T3 are turned ON, and the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2. The first switch K1 is turned OFF, and the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (e.g., the anode of an OLED) via the detection line 230 and the third transistor T3. The first transistor T1 is turned ON, generating a driving current to charge the first electrode of the light-emitting element to an operating voltage. In the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both OFF signals, and due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change. The first transistor T1 operates in saturation, and the current does not change, driving the element to emit light.

[0145] 2E shows a signal timing diagram for detecting the threshold voltage of the pixel circuit. One operation process of the 3T1C pixel circuit includes the following: the first control signal G1 and the second control signal G2 are both ON signals, the second transistor T2 and the third transistor T3 are ON, and the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2; the first switch K1 is OFF; the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element via the detection line 230 and the third transistor T3; the first transistor T1 is ON and charges node S until the first transistor T1 is OFF; and the digital-to-analog converter samples the voltage of the detection line 230 to obtain the threshold voltage of the first transistor T1. This process may be performed, for example, when the display device is turned off.

[0146] For example, Figure 2F shows a signal timing diagram when the pixel circuit detects carrier mobility. One working process of the 3T1C pixel circuit includes: In the first stage, the first control signal G1 and the second control signal G2 are both on signals, so the second transistor T2 and the third transistor T3 are on, transmitting the data signal DT to the gate of the first transistor T1 via the second transistor T2. The first switch K1 is off, and the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line 230 and the third transistor T3. In the second stage, the first control signal G1 is off signal, the second control signal G1 is on signal, so the second transistor T2 is off and the third transistor T3 is on, turning off the first switch K1 and the second switch K2 to float the detection line 230. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, so the first transistor T1 operates in saturation and the current does not change, driving the element to emit light. The digital-to-analog converter then samples the voltage of the detection line 230 and combines it with the magnitude and duration of the light-emitting current to calculate the carrier mobility of the first transistor T1. For example, the process may be performed in a blanking phase between display phases.

[0147] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be realized.

[0148] 2A, the display substrate 10 may further include a data driving circuit 23 and a scan driving circuit 24. The data driving circuit 23 is configured to transmit data signals such as the data signal DT as needed (e.g., to input an image signal for the display device), and the pixel circuit of each sub-pixel is further configured to receive the data signal and apply it to the gate of the first transistor. The scan driving circuit 24 is configured to output various scan signals, including the first control signal G1 and the second control signal G2, and is, for example, a gate driving circuit (GOA) fabricated on an integrated circuit chip (IC) or directly on the display substrate.

[0149] For example, the display substrate 10 further includes a control circuit 22. For example, the control circuit 22 is configured to control the data driving circuit 23 to apply data signals and the gate driving circuit 24 to apply scanning signals. One example of the control circuit 22 is a timing control circuit (T-con). The control circuit 22 may take various forms, such as including a processor 121 and a memory 127, where the memory 121 includes executable code and the processor 121 executes the executable code to perform the detection method.

[0150] For example, processor 121 may be a central processing unit (CPU) or other form of processing device having data processing and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0151] For example, the memory 127 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage medium, and the processor 121 may execute functions expected by the program instructions. The computer-readable storage medium may also store various application programs and various data, such as electrical characteristic parameters acquired by the above-mentioned detection method.

[0152] 3A is a schematic diagram of a subpixel of a display substrate 10 according to at least one embodiment of the present disclosure. As shown in FIG. 3A, the display substrate 10 includes a base substrate 101, on which a plurality of subpixels 100 are disposed. The subpixels 100 are distributed as a pixel array along a first direction D1 and a second direction D2. The pixel array includes a plurality of pixel columns and a plurality of pixel rows, with the column direction being the first direction D1 and the row direction being the second direction D2, and the first direction D1 and the second direction D2 intersecting, e.g., perpendicular to each other.

[0153] For example, the subpixels in each pixel row are divided into multiple pixel portions, and each pixel portion is arranged to emit full-color light. Figure 3A illustrates one pixel portion for illustrative purposes, and the implementation of the present disclosure is not limited to this layout. Figure 3B illustrates a cross-sectional view taken along line I-I' in Figure 3A. As shown in Figure 3A, the pixel portion includes a first subpixel P1, a second subpixel P2, and a third subpixel P3 sequentially arranged along a second direction D2. The first subpixel P1, the second subpixel P2, and the third subpixel P3 are used to emit light of three primary colors (RGB), respectively. For example, the first subpixel P1 is a red subpixel, the second subpixel P2 is a blue subpixel, and the third subpixel P3 is a green subpixel.

[0154] For example, the pixel unit may further include a fourth sub-pixel P4 for emitting white light. For example, the fourth sub-pixel P4 is located between the first sub-pixel P1 and the second sub-pixel P2, but the embodiment of the present disclosure does not limit the location of the fourth sub-pixel P4.

[0155] 3A and 3B in combination, the display substrate 10 includes a first conductive layer 501, a first insulating layer 201, a semiconductor layer 104, a second insulating layer 202, a second conductive layer 502, a third insulating layer 203, and a third conductive layer 503, which are sequentially arranged on a base substrate 101.

[0156] 3A , the specific structure of the subpixel of the display substrate 10 will be described below. For convenience of description, in the following description, T1g, T1s, T1d, and T1a represent the gate, first pole, second pole, and active layer of the first transistor T1, respectively; T2g, T2s, T2d, and T2a represent the gate, first pole, second pole, and active layer of the second transistor T2, respectively; T3g, T3s, T3d, and T3a represent the gate, first pole, second pole, and active layer of the third transistor T3, respectively; and Ca, Cb, and Cc represent the first capacitor electrode, second capacitor electrode, and third capacitor electrode of the storage capacitor Cst, respectively.

[0157] In addition, the term "same layer arrangement" described in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and these structures may be made of the same or different materials. The term "integral structure" in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and these structures are connected to each other, and these structures may be made of the same or different materials.

[0158] 3A and 3B , the first conductive layer 501 includes a shielding layer 170, whose orthogonal projection on the base substrate 101 covers the orthogonal projection on the base substrate 101 of the active layer T1a of the first transistor T1. The first transistor T1 functions as a driving transistor of the pixel circuit, and the stability of its electrical characteristics is very important for the light-emitting characteristics of the light-emitting element. The shielding layer 170 is an opaque layer, which prevents light from entering the active layer of the first transistor T1 from the back surface of the base substrate 101, causing the threshold voltage of the first transistor T1 to drift and thereby affecting the light-emitting characteristics of the corresponding light-emitting element connected thereto.

[0159] For example, the shielding layer 170 is an opaque conductive material such as a metal or metal alloy material, etc. Such an arrangement can reduce the back channel phenomenon in the base substrate 101 caused by charge trapping.

[0160] For example, the semiconductor layer 104 includes an active layer T1a of a first transistor T1, an active layer T2a of a second transistor T2, and an active layer T3a of a third transistor T3.

[0161] For example, the semiconductor layer 104 further includes a first capacitor electrode Ca of the storage capacitor Cst, and the first capacitor electrode Ca is obtained by conducting the semiconductor layer 104, that is, the first capacitor electrode Ca is disposed in the same layer as the active layer T1a of the first transistor T1, the active layer T2a of the second transistor, and the active layer T3a of the third transistor.

[0162] For example, the second conductive layer 502 comprises a gate T1g of the first transistor T1, a gate T2g of the second transistor T2, and a gate T3g of the third transistor T3.

[0163] For example, the display substrate 10 uses a self-alignment process to conduct (e.g., dope) the semiconductor layer 104 using the second conductive layer 502 as a mask, and conducts the portion of the semiconductor layer 104 that is not covered by the second conductive layer 502, thereby obtaining the first capacitor electrode Ca, and conducts the portions of the active layer of each transistor located on both sides of the channel region to form first and second pole contact regions, respectively, which are used to electrically connect to the first and second poles of the transistors, respectively.

[0164] For example, the third conductive layer 503 includes a first pole T1s and a second pole T1d of the first transistor T1, a first pole T2s and a second pole T2d of the second transistor T2, and a first pole T3s and a second pole T3d of the third transistor T3.

[0165] For example, the third conductive layer 503 further includes a second capacitor electrode Cb of the storage capacitor Cst. For example, as shown in FIG. 3B, the second capacitor electrode Cb is disposed in the same layer as the second pole T1d of the first transistor T1 and is connected to each other as an integral structure. As shown in FIG. 3B, the first capacitor electrode Ca and the second capacitor electrode Cb overlap each other in a direction perpendicular to the base substrate 101 to form the storage capacitor Cst.

[0166] 2C shows a pixel circuit diagram of a display substrate according to another embodiment of the present disclosure. For example, the storage capacitor Cst further includes a third capacitor electrode Cc, which is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is electrically connected to the second capacitor electrode Cb through via No. 7 shown in FIG. 3A to form a parallel capacitor structure and increase the capacitance of the storage capacitor Cst. For example, in the direction perpendicular to the base substrate 101, the third capacitor electrode Cc, the second capacitor electrode Cb, and the first capacitor electrode Ca all overlap each other.

[0167] 3B , the third capacitor electrode Cc is located on the first conductive layer 501. For example, the shielding layer 170 is disposed on the same layer as the second capacitor electrode Cb of the storage capacitor Cst, and they are made of the same material. For example, the shielding layer 170 and the second capacitor electrode Cb of the storage capacitor Cst are the same electrode block. In this case, the shielding layer 170 is connected to the first electrode T3s of the third transistor T3, thereby preventing the potential of the shielding layer from changing during display operation and affecting the threshold voltage of the transistor because the shielding layer is floating.

[0168] 3A and 3B in combination, for each subpixel, the first transistor T1 and the second transistor T2 are aligned along the second direction D2 and disposed in parallel in the second direction D2. For example, in the first direction D1, the first transistor T1 and the second transistor T2 are located on the same side of the second capacitor electrode Cb, and the third transistor T3 and the second capacitor electrode Cb are located on opposite sides of each other.

[0169] For example, the display substrate 10 further includes an extension portion 180 protruding from the gate T1g of the first transistor T1, and the extension portion 180 extends from the gate T1g of the first transistor T1 along the second direction D2, and at least partially overlaps with and is electrically connected to the first pole T2s of the second transistor T2 in a direction perpendicular to the base substrate 101.

[0170] As shown in FIG. 3B , the first pole T2s of the second transistor T2 is electrically connected to its first pole contact region Ta1, the extension portion 180 (i.e., the gate T1g of the first transistor T1), and the first capacitor electrode Ca through a via 800 (an example of a second via in the present disclosure). The first pole T2s of the second transistor T2 is electrically connected to the three portions through a single via, which reduces the layout space occupied and improves wiring density, thereby improving pixel density, compared to electrically connecting the three portions through multiple vias. As shown in FIG. 3B , the via 800 is formed in the third insulating layer 203, and the extension portion 180 and a portion of the second insulating layer 202 located below the extension portion 180 are located in the via 800 to divide the via 800 into two groove portions, i.e., a first groove V1 and a second groove V2. The second groove V2 is closer to the third transistor T3 than the first groove V1. The first pole T2s of the second transistor T2 is filled in the via 800, covers the first groove V1 and the second groove V2, and has a surface parallel to or inclined relative to the base substrate.

[0171] 3A and 3B in combination, the first pole T2s of the second transistor T2 extends along a first direction D1, straddles (intersects with) the extension portion 180, and is electrically connected to the first capacitor electrode Ca through the via 800 (i.e., via number 2 in FIG. 3A). For example, the extension portion 180 has a first side surface and a second side surface opposing each other in the first direction. For example, the via 800 extends along the first direction D1 and exposes the surface of the extension portion 180 and at least a portion of the first side surface and the second side surface. The first pole T2s of the second transistor T2 includes a first portion S1, a second portion S2, and a third portion S3, and the first portion S1, the second portion S2, and the third portion S3 are sequentially connected in the first direction D1. The second portion S2 overlaps the extending portion 180, the first portion S1 and the third portion S3 are located on either side of the second portion S2 in the first direction D1, the third portion S3 is located on the side of the second portion S2 closest to the third transistor T3, the first portion S1 fills the first groove V1, and the third portion S3 fills the second groove V2. For example, through the via 800, the first portion S1 is electrically connected to the first electrode contact region T2a1 of the active layer T2a of the second transistor T2, the second portion S2 is in direct contact with the extending portion 180, thereby increasing the contact area and reducing resistance, and the third portion S3 is electrically connected to the first capacitor electrode Ca.

[0172] For example, the first pole T2s of the second transistor T2 extends along the first direction and covers two side surfaces of the extension portion 180 through the via 800, for example, the first portion S1 covers the first side surface and the third portion S3 covers the second side surface. In this way, the first pole T2s of the second transistor T2 and the extension portion 180 have a large contact area, thereby reducing the contact resistance therebetween.

[0173] 3B , the display substrate 10 may further include a connection portion 720, which overlaps the extension portion 180 in a direction perpendicular to the base substrate 101 and is disposed in the same layer as the first capacitor electrode Ca. The connection portion 720 connects the first capacitor electrode Ca and the first electrode contact region T2a1 of the second transistor T2 as an integral structure. The connection portion 720 is shielded by the extension portion 180 and is therefore not conductive. When the second transistor T2 is turned on and transmits a data signal from the second electrode T2d of the second transistor T2 to the first electrode T2s and the gate T1g of the first transistor T1, the connection portion 720 is turned on under the action of the data signal from the extension portion 180 and the first electrode T2s of the second transistor T2 above it, thereby electrically connecting the first electrode T2s of the second transistor T2 and the first capacitor electrode Ca. In this way, a dual channel structure is formed between the first pole T2s of the second transistor T2 and the first capacitor electrode Ca, which helps to reduce the channel resistance.

[0174] 3B, the connection part 720 connects the first capacitor electrode Ca and the first pole contact area T2a1 of the second transistor T2 as an integral structure, so that the first pole contact area T2a1 of the second transistor T2 is also included within the range of the first capacitor electrode Ca. In this way, the first capacitor electrode Ca has a large area and overlaps the third capacitor electrode Cc to a large extent, thereby increasing the capacitance value of the storage capacitor Cst.

[0175] 3B, the third capacitor electrode Cc may at least partially overlap the first electrode contact region T2a1 of the second transistor T2 in a direction perpendicular to the base substrate, thereby increasing the overlapping area with the first capacitor electrode and the capacitance value of the storage capacitor Cst. For example, the third capacitor electrode Cc does not overlap the channel region T2a0 of the second transistor T2 in a direction perpendicular to the base substrate 101. This is to prevent the potential of the third capacitor electrode Cc from adversely affecting the operation of the second transistor T2, such as preventing the second transistor T2 from being turned off normally due to the potential of the third capacitor electrode Cc acting on the channel region T2a0 of the second transistor T2, resulting in large leakage current.

[0176] 3A, the display substrate 10 may further include a first scan line 150 and a second scan line 160 connected to each pixel row. For example, the first scan line 150 and the second scan line 160 are located on the second conductive layer 502 and extend along the second direction D2.

[0177] For example, the first scan line 150 is integral with the gate T2g of the second transistor T2 of the sub-pixel in the corresponding row, and the second scan line 160 is integral with the gate T3g of the third transistor T3 of the sub-pixel in the corresponding row.

[0178] For example, as shown in FIG. 3A, for each row subpixel, a corresponding first scan line 150 and a corresponding second scan line 160 are located on both sides of the first transistor T1 of the row subpixel along the first direction D1.

[0179] For example, each first scanning line 150 includes a first portion 151 and a second portion 152 that are alternately connected, the second portion 152 has a ring structure, and the size of the second portion 152 in the first direction D1 is larger than the size of the first portion 151. Similarly, each second scanning line 160 includes a first portion 161 and a second portion 162 that are alternately connected, the second portion 162 has a ring structure, and the size of the second portion 162 in the first direction D1 is larger than the size of the first portion 161.

[0180] For example, the display substrate has a plurality of first surface microstructures and a plurality of second surface microstructures, some of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with a first portion of the first scan line in a direction perpendicular to the base substrate, and other portions of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with a second portion of the first scan line in a direction perpendicular to the base substrate, and the distribution density of the first surface microstructures and the second surface microstructures overlapping with the second portion of the first scan line in the direction perpendicular to the base substrate is higher than the distribution density of the first surface microstructures and the second surface microstructures overlapping with the first portion of the first scan line.

[0181] This arrangement can improve the stress relief effect, since the stress in the second portion having the annular structure is more concentrated than the stress in the first portion having the strip structure.

[0182] For example, the first overlap area is larger than the area of ​​a normal projection of each of the plurality of first surface microstructures or the second surface microstructures onto the base substrate, and the second overlap area is larger than the area of ​​a normal projection of each of the plurality of first surface microstructures or the second surface microstructures onto the base substrate.

[0183] If the area of ​​the release structure is too large, excessive stress release is likely to occur, causing the panel to fail. If the area of ​​the surface microstructure is smaller than the overlap area, the stress in that area can be sufficiently released, ensuring the stability of the panel in that area.

[0184] The distribution density of the surface microstructures in the present disclosure refers to the number of surface microstructures distributed in a unit area of ​​the substrate.

[0185] For example, the display substrate 10 further includes a plurality of signal lines extending along the first direction D1, which may be, for example, data lines, power lines, auxiliary electrode lines, etc. As shown in Fig. 3A, each second portion 152 intersects with at least one data line in a direction perpendicular to the base substrate 101 to define a plurality of first hollow regions H1 arranged along the second direction D2, and each second portion 162 intersects with at least one data line in a direction perpendicular to the base substrate 101 to define a plurality of second hollow regions H2 arranged along the second direction D2.

[0186] By arranging the portion of the scan line that intersects with the signal line as a ring structure, i.e., a dual channel structure, it is possible to effectively improve the yield of devices. For example, at the intersection of the signal line and the scan line, electrostatic breakdown due to parasitic capacitance is likely to occur, causing a short circuit. If a short circuit is detected in one channel of the ring structure during the detection process, the channel can be removed (e.g., by laser cutting), and the circuit structure can still operate normally through the other channel.

[0187] For example, as shown in FIG. 3A , the signal lines include a plurality of data lines DL, which are connected to the subpixels in each column of the subpixel array in a one-to-one correspondence to provide data signals to the subpixels. For each pixel row, the data lines are divided into a plurality of data line groups corresponding to the pixel portions in the pixel row in a one-to-one correspondence. As shown in FIG. 3A , each data line group includes a first data line DL1 connected to the first subpixel P1, a second data line DL2 connected to the second subpixel P2, a third data line DL3 connected to the third subpixel P3, and a fourth data line DL4 connected to the fourth subpixel P4. For each pixel portion, the data lines DL1 to DL4 connected to the corresponding pixel portion are all located between the first subpixel P1 and the third subpixel P3. This arrangement provides space for the placement of detection lines and power supply lines.

[0188] 2A, the display substrate 10 further includes a plurality of detection lines 230 extending along a first direction D1. The detection lines 230 are connected to detection sub-circuits (e.g., third transistors T3) of the sub-pixels 100 and are used to connect the detection sub-circuits to an external detection circuit. For example, at least one column of sub-pixels is interposed between each detection line 230 and one of the plurality of data lines DL, i.e., the detection line 230 is not directly adjacent to any of the data lines DL. For example, as shown in FIG. 2A, for each pixel portion, the first data line DL1 and the fourth data line DL4 are located between the first sub-pixel P1 and the fourth sub-pixel P4, the second data line DL2 and the third data line DL3 are located between the second sub-pixel P2 and the third sub-pixel P3, and the detection line 230 is located between the fourth sub-pixel P4 and the second sub-pixel P2.

[0189] This arrangement prevents a data line from being directly adjacent to the corresponding detection line, which would cause a resistive / capacitive load and signal delay on the data line, thereby further avoiding defects such as display unevenness caused by the delay. Furthermore, since the signal transmitted through the data line DL is typically a high-frequency signal, arranging the detection line 230 and the data line DL so that they are not directly adjacent to each other prevents the detection line 230 from receiving high-frequency signal crosstalk during the external compensation charge sampling process, which would affect the sampling accuracy.

[0190] 3A, four subpixels of the pixel unit share one sensing line 230, and the sensing line 230 is electrically connected to the second pole T3d of the third transistor T3 of each of the four subpixels through sensing portions 231 extending along the second direction D2. The sensing line 230 is electrically connected to the sensing portion 231 through a via, and the sensing portion 231 is electrically connected to the second pole T3d of the third transistor T3 through via number 10. The first pole T3s of the third transistor T3 is electrically connected to the first pole contact region T3a1 of the third transistor T3 through via number 6, and the second pole T3d of the third transistor T3 is electrically connected to the second pole contact region T3a2 of the third transistor T3 through via number 5.

[0191] For example, the third transistor T3 and the second capacitor electrode Cb are disposed on the same layer and connected as an integral structure.

[0192] For example, as shown in FIG. 3A , the display substrate 10 further includes a plurality of power lines 240 extending along a first direction D1. The power lines 240 are arranged to provide a first power supply voltage, e.g., a high power supply voltage VDD, to the subpixels. The power lines 240 are located on a third conductive layer 503. As shown in FIG. 3A , at least one pixel column is interposed between each of the power lines 240 and one of the data lines DL. That is, the power lines 240 are not directly adjacent to any of the data lines DL. This arrangement avoids the resistive-capacitive load that would otherwise be generated by the data lines being directly adjacent to the power lines, resulting in signal delays on the data lines, and further avoids defects such as color shift and display unevenness that result from the delays.

[0193] For example, none of the power supply lines 240 overlaps with the detection units 231 in the direction perpendicular to the base substrate 101, i.e., the power supply lines 240 are arranged to correspond to the intervals between adjacent detection units 231. This arrangement reduces the overlap of signal lines, thereby effectively reducing the parasitic capacitance between the signal lines and the resulting signal delay.

[0194] 3B , the power line 240 is electrically connected to the second pole T1d of the first transistor T1 of a subpixel (e.g., the first subpixel P1) that is directly adjacent to the power line 240 through the via 3, for example, the power line is integral with the second pole T1d of the first transistor T1. For example, the power line 240 is electrically connected to the second pole T1d of the first transistor T1 of a subpixel that is not directly adjacent to the power line 240 through the connecting electrode 241. For example, the connecting electrode 241 is electrically connected to the second pole T1d of the first transistor T1 of the second or fourth subpixel through the via 11.

[0195] For example, the display substrate has a plurality of first surface microstructures 11 and a plurality of second surface microstructures 12, a portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures are distributed on the plurality of data lines DL, and another portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures are distributed on the plurality of power lines, and the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of data lines is higher than the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of power lines.

[0196] Since the dynamic voltage applied to the data lines is more sensitive to stress, it is helpful to set the distribution density of the surface microstructures on the data lines higher to improve the stability of the panel.

[0197] For example, the connection electrode 241 and the detection portion 231 are both located on the first conductive layer 501 .

[0198] For example, in the direction perpendicular to the base substrate, the connection electrode 241 does not overlap with the detection line 230. As shown in Figure 3B, the connection electrode 241 is cut at a position corresponding to the detection line 230 so as not to overlap with the detection line 230, thereby reducing the parasitic capacitance.

[0199] For example, the first surface microstructure and the second surface microstructure of the present disclosure may be disposed on any signal line or any conductive structure of the display substrate of the present disclosure, for example, disposed in a portion corresponding to the via of the signal line or conductive structure, thereby helping to release stress at the via of the signal line or conductive structure and reducing the risk of breakage.

[0200] For example, the distance between the first surface microstructure and the second surface microstructure is less than 1 / 10 of the size of one sub-pixel, and such an arrangement can effectively release stress within the pixel size range.

[0201] For example, the components in the first direction and the second direction of the center distance between the orthogonal projection of the first surface microstructure on the base substrate and the orthogonal projection of the second surface microstructure on the base substrate are smaller than the average size in the first direction and the second direction of each of the multiple subpixels, respectively.

[0202] For example, the size of a sub-pixel is limited by the signal lines immediately adjacent to it and located on both sides thereof. For example, as shown in FIG. 3B , the average size (length) of each sub-pixel in the first direction is the average distance between the corresponding first scan line 150 and second scan line 160, and the average size (width) of each sub-pixel in the second direction is the average distance between the corresponding data line DL and detection line 230 / power line 240.

[0203] For example, the length and width of one sub-pixel are 100 to 500 microns, respectively, and the center distance between the orthogonal projections of the first surface microstructure 11 and the second surface microstructure 12 on the base substrate is 5 to 20 microns.

[0204] For example, the first surface microstructure 11 and the second surface microstructure 12 are arranged along a first direction D1, and are located on, for example, signal lines (e.g., data lines, power lines, detection lines, etc.) extending along the first direction D1. For example, as shown in Fig. 3A, the first surface microstructure 11 and the second surface microstructure 12 are located on the same power line 240, the first surface microstructure 11 has a first concave structure, and the second surface microstructure 12 has a second concave structure, and the first concave structure and the second concave structure face sub-pixels of the same color, for example, the angles between the orthogonal projection of the normals of the first concave structure and the second concave structure on the base substrate and the first direction D1 are both acute angles, i.e., face sub-pixels in the same column.

[0205] For example, the sub-pixels in each pixel column (i.e., the sub-pixels located in the same column) emit light of the same color. When light emitted from a light-emitting element is obliquely incident on the concave structure, the concave structure can reflect the light to the light-emitting element (e.g., the cathode of the light-emitting element). With the above arrangement, the concave structure can reflect the light to the sub-pixels of the same color as the light, thereby avoiding cross-color of the light of sub-pixels of different colors.

[0206] Hereinafter, the first pole T2s of the second transistor T2 will be exemplified as the first conductive structure of the present disclosure to exemplify the display substrate of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0207] For example, the first surface microstructure 11 is located on an inclined surface of the second pole T2 of the second transistor T2 relative to the base substrate, for example, on at least one of the first portion, second portion, and third portion of the second pole T2 of the second transistor T2, and the second surface microstructure 12 is located on a surface of the second pole T2s of the second transistor T2 parallel to the base substrate, for example, on at least one of the first portion, second portion, and third portion of the second pole T2 of the second transistor T2.

[0208] 3A-3B, the first surface microstructure 11 is located on the third portion S3 of the second pole T2 of the second transistor T2, and the third portion S3 has two slopes (an example of the first surface of the first conductive structure of the present disclosure) with respect to the substrate to fill the via 800 (or the first and second grooves V2), and the first surface structure 11 is located on at least one of the two slopes. For example, as shown in FIG. 3B, the first surface microstructure 11 is located on the slope close to the third transistor T3.

[0209] For example, in some other examples, the first surface microstructure 11 may be located on a first portion S1 of the second pole T2 of the second transistor T2, the first portion S1 having a slope (an example of the first surface of the first conductive structure of the present disclosure) relative to the base substrate to fill the via 800, and the first surface microstructure 11 is located on the slope.

[0210] For example, as shown in Figure 3B, the second surface microstructure is located in the third portion S3 that fills the second groove and forms a surface parallel to the surface of the base substrate. Because the conductive structure is subjected to a large stress in the groove, arranging the surface microstructure in the third portion S3 that fills the groove helps relieve the stress.

[0211] In other examples, the second surface microstructure 12 is disposed on the surfaces of the first portion S1, the second portion S2, and the third portion S3 of the second pole T2 of the second transistor T2 that are parallel to the plane of the base substrate (examples of the second surface of the first conductive structure of the present disclosure). For example, the first portion S1 of the second pole T2 of the second transistor T2 may include a portion that is located in the via 800 and in direct contact with the semiconductor layer 104, and the second surface microstructure 12 may be disposed on the upper surface of the portion, thereby reducing stress.

[0212] For ease of illustration, the concave structures of the first surface microstructure 11 and the second surface microstructure 12 are shown blank in Figure 3B, and in an actual structure, the concave structures may be filled with at least the surrounding insulating layer, for example, completely filled with the fourth insulating layer 204.

[0213] Because the size of the via 800 is relatively large, by arranging the first surface microstructure 11 and the second surface microstructure 12 on the second pole T2s of the second transistor T2, the stress on the second pole T2s of the second transistor T2 can be effectively reduced and the risk of failure can be reduced.

[0214] For example, the size of the first surface microstructure in the first direction is smaller than one-tenth the maximum size of the third portion S3 in the first direction.

[0215] For example, the size of the first surface microstructure 11 or the second surface microstructure 12 in the first direction D1 (i.e., the size along the direction of the cross-sectional line I-I' in Figure 3B) is smaller than one-tenth of the maximum size of the via 800 in the first direction D1 of the orthogonal projection on the base substrate 101, for example, 2% to 5%.

[0216] 3A and 3B, each subpixel further includes a light-emitting element 125, which may be, for example, an organic light-emitting diode, and which includes a first electrode 123, a light-emitting layer 124, and a second electrode 122 stacked in sequence. For example, the light-emitting element 125 has a top-emission structure, in which the first electrode is reflective and the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode is made of a high-work-function material and functions as an anode, such as an ITO / Ag / ITO stacked structure, and the second electrode 122 is made of a low-work-function material and functions as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0217] For example, the display substrate 10 further includes a fourth insulating layer 204 and a fifth insulating layer 205 located between the third conductive layer 503 and the first electrode 123 of the light-emitting element. For example, the fourth insulating layer 204 is a passivation layer, for example, an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, or other silicon oxide, silicon nitride, or silicon nitroxide, and the fifth insulating layer 205 is an organic insulating material, for example, polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), or other organic insulating material. For example, the fifth insulating layer 205 is a planarization layer.

[0218] For example, the display substrate 10 further includes a pixel defining layer 206 located on the first electrode 123 of the light-emitting element 125, the pixel defining layer 206 being made of an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc. The first electrode 123 of the light-emitting element 125 is electrically connected to the first pole T1s of the first transistor T1 and the second capacitor electrode Cb through a via 700 (i.e., via number 8 in FIG. 3A ), which penetrates, for example, the fourth insulating layer 204 and the fifth insulating layer 205.

[0219] 3A and 3B, the first electrode 123 of the light-emitting element includes a first electrode portion 123a, a second electrode portion 123b, and a third electrode portion 123c, which are sequentially connected in a first direction D1. The first electrode portion 123a is electrically connected to the first pole T1s of the corresponding first transistor T1 and overlaps the first pole T1s of the corresponding first transistor T1 in a direction perpendicular to the base substrate 101. The third electrode portion 123c is in direct contact with the light-emitting layer 124 and overlaps an opening region (not shown) of the light-emitting element in a direction perpendicular to the base substrate. That is, the third electrode portion 123c corresponds to the effective light-emitting region of the light-emitting element and does not overlap the via 700 in a direction perpendicular to the base substrate, thereby avoiding adverse effects on the light-emitting efficiency of the light-emitting material due to the interface at the via 700. The second electrode portion 123b connects the first electrode portion 123a and the third electrode portion 123c. For example, the opening region of a light-emitting element is an opening region in the pixel definition layer 206 that is arranged corresponding to the light-emitting element, and the opening region exposes the first electrode 123 of the light-emitting element and accommodates at least a portion of the light-emitting layer of the light-emitting element.

[0220] As shown in FIG. 3A, the average size in the second direction D2 of the second electrode portion 123b of the first electrode 123 of the light-emitting element is smaller than the average size in the second direction D2 of the first electrode portion 123a, and is also smaller than the average size in the second direction D2 of the third electrode portion 123c.

[0221] For example, the sum of the maximum size in the first direction and the maximum size in the second direction of the first electrode portion is smaller than the sum of the maximum size in the first direction and the maximum size in the second direction of the third electrode portion, and the sum of the maximum size in the first direction and the maximum size in the second direction of the second electrode portion is smaller than the sum of the maximum size in the first direction and the maximum size in the second direction of the third electrode portion.

[0222] For example, the display substrate has a plurality of first surface microstructures 11 and a plurality of second surface microstructures 12, a portion of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with the first electrode portion in a direction perpendicular to the base substrate, and another portion of the plurality of first surface microstructures and the plurality of second surface microstructures overlap with the third electrode portion in a direction perpendicular to the base substrate, and the distribution density of the first surface microstructures and the second surface microstructures overlapping with the first electrode portion is higher than the distribution density of the first surface microstructures and the second surface microstructures overlapping with the third electrode portion.

[0223] Because the first electrode portion is close to the pixel driving region and at least partially overlaps with the first transistor T1, for example, in a direction perpendicular to the base substrate, which causes stress in the pixel driving region to be more concentrated, the above arrangement can effectively relieve stress in the driving region and improve the performance of the display substrate.

[0224] As shown in FIG. 3A, in the first direction D1, the first scanning line 150 is located between the first electrode portion 123a and the third electrode portion 123c, and the second electrode portion 123b overlaps with the first scanning line 150 in a direction perpendicular to the base substrate. By reducing the size of the second electrode portion 123b in the second direction D2, the overlapping area between the second electrode portion 123b and the first scanning line 150 is reduced, which helps to reduce the parasitic capacitance.

[0225] For example, the second electrode portion 123b overlaps the first portion 151 of the first scan line 150 in the direction perpendicular to the base substrate 101, but does not overlap the second portion 152 of the first scan line 150 in the direction perpendicular to the base substrate 101.

[0226] Since the second portion 152 of the first scanning line 150 overlaps with a signal line (e.g., a power line, a detection line, a data line, etc.) in the first direction D1, the second portion 152 is prone to failure such as a short circuit and needs to be repaired during the repair process. By arranging the first electrode of the light emitting element so as not to overlap with the second portion 152 of the first scanning line 150, the difficulty of repairing the second portion 152 can be reduced.

[0227] As shown in FIG. 3A, the first subpixel P1 has a first side and a second side facing each other in the second direction D2, a power supply line 240 is arranged on the first side, and data lines DL (the first data line DL1 and the fourth data line DL4) are arranged on the second side, and the second electrode portion 123b is recessed toward the first side relative to the first electrode portion 123a and the third electrode portion 123c, i.e., recessed in a direction away from the second side, i.e., the distance between the second electrode portion 123b and the power supply line is smaller than the distance between the second electrode portion 123b and the data line.

[0228] Since the power line 240 transmits a constant voltage and the data line DL transmits a high-frequency signal, by arranging the second electrode portion 123b close to the power line, it is possible to prevent the high-frequency signal on the data line DL from affecting the potential of the first electrode of the light-emitting element and thereby affecting the display gradation.

[0229] 3A , the second subpixel P2 is directly adjacent to the third subpixel P3, and the third subpixel P3 has a first side and a second side facing each other in the second direction. The second data line DL2 and the third data line DL3 are located on the first side of the third subpixel P3 and between the second subpixel P2 and the third subpixel P3. The detection line 230 is located on the second side of the third subpixel P3. The second electrode portion of the first electrode of the light-emitting element of the third subpixel is recessed from the first electrode portion and the third electrode portion in a direction away from the second side of the third subpixel. That is, the distance between the second electrode portion and the detection line 230 is smaller than the distance between the second electrode portion and the data line DL2.

[0230] Since the detection line 230 transmits a low-frequency detection signal and the data line DL transmits a high-frequency signal, by arranging the second electrode portion close to the detection line, it is possible to prevent the high-frequency signal on the data line DL from affecting the potential of the first electrode of the light-emitting element and thereby affecting the display gradation.

[0231] For example, the light-emitting elements OLED of each sub-pixel are arranged to emit white light, and the display substrate 10 further includes a color filter layer through which the white light is emitted to achieve a full-color display. For example, the light-emitting layer 124 is formed on the entire surface by a combination of an open mask and a deposition process, thereby avoiding a patterning process for the light-emitting layer using, for example, a fine metal mask (FMM), which would limit the resolution of the display substrate due to the limited precision of the FMM.

[0232] For example, the light-emitting elements of the display substrate 10 according to some embodiments of the present disclosure may have a bottom-emission structure. For example, as shown in FIGS. 3A and 3B , a color filter layer is located on the side of the first electrode of the light-emitting element closest to the base substrate 101, for example, between the fourth insulating layer 204 and the fifth insulating layer 205. The color filter layer includes a plurality of color filter sections 190 corresponding to the subpixels other than the white subpixel. That is, the first subpixel P1, the second subpixel P2, and the third subpixel P3 each correspond to one color filter section 190. Light emitted by the light-emitting elements of the first subpixel P1, the second subpixel P2, and the third subpixel P3 passes through the color filter section 190 to form display light. Because light from the white subpixel does not need to pass through the color filter layer, no color filter section is provided corresponding to the fourth subpixel P4.

[0233] For example, adjacent color filter units are overlapped in a direction perpendicular to the base substrate, and the first or second surface microstructure is disposed at the corresponding overlapping location, and the surface microstructure can effectively relieve the stress in the overlapping area due to the uneven stress caused by the overlapping color filters.

[0234] For example, the color filter portion corresponding to the first sub-pixel and the color filter portion corresponding to the second sub-pixel overlap the second surface microstructure in a direction perpendicular to the base substrate.

[0235] 3A and 3B in combination, each color filter unit 190 overlaps with the first electrode unit 123a of the first electrode of the light-emitting element of the corresponding subpixel, but does not overlap with the third electrode unit 123c of the first electrode of the light-emitting element. This is because the color filter layer needs to be arranged corresponding only to the light-emitting layer of the light-emitting element. As shown in FIG. 3B, the third electrode unit 123c of the first electrode of the light-emitting element, the light-emitting layer 124, and the color filter unit 190 overlap with each other in the direction perpendicular to the base substrate.

[0236] For example, as shown in Figures 3A and 3B, in the direction perpendicular to the base substrate 101, the portion of the second electrode portion 123b of the first electrode of the light-emitting element of the first sub-pixel P1 that overlaps with the first scanning line 150 further overlaps with the color filter portion 190 corresponding to the first sub-pixel P1. Since the color filter unit 190 is located between the first scanning line 150 and the first electrode 123 of the light-emitting element in a direction perpendicular to the base substrate, and the fifth insulating layer 205 on the color filter unit 190 is a planarization layer, the formation of the color filter unit 190 does not affect the height of the fifth insulating layer 205 in the color filter unit relative to the base substrate, i.e., does not change the distance between the first electrode of the light-emitting element and the first scanning line 150. However, the dielectric constant of the color filter unit 190 is lower than that of the fifth insulating layer 205. Therefore, by forming the color filter unit 190 between the second electrode unit 123b and the first scanning line 150 and overlapping them, it helps to further reduce the parasitic capacitance between the first electrode of the light-emitting element and the first scanning line.

[0237] The inventor discovered that when multiple first hollow areas H1 or second hollow areas H2 are arranged regularly in the second direction D2, a certain regular continuity occurs, which causes a periodic diffraction phenomenon, resulting in a clear difference in the reflection of ambient light at the metal line locations in the hollow areas and non-hollow areas, thereby causing display unevenness.

[0238] On the other hand, as shown in Figure 3A, in one pixel area, the geometric centers of multiple first hollow areas H1 are not in a straight line, which reduces the regularity of the first hollow areas being arranged in the same direction and helps to reduce display unevenness caused by periodic diffraction.

[0239] On the other hand, the display substrate according to the embodiment of the present disclosure utilizes a color filter layer to selectively shield multiple hollow areas located in the same row and corresponding to one pixel portion, thereby breaking the arrangement rule of the pixel portion in the hollow areas, weakening the diffraction effect, and improving the display uniformity.

[0240] As shown in FIG. 3A, in the first direction D1, the color filter section corresponding to one pixel row (first pixel row) is located between the first scanning line 150 corresponding to that pixel row and the second scanning line 160 corresponding to the next pixel row (second pixel row) that is directly adjacent to that pixel row.

[0241] For example, the second pixel row includes a fifth sub-pixel P5, a sixth sub-pixel P6, and a seventh sub-pixel P7 sequentially arranged along the second direction D2, where the fifth sub-pixel P5 and the first sub-pixel P1 are located in the same column, the sixth sub-pixel P6 and the second sub-pixel P2 are located in the same column, and the seventh sub-pixel P7 and the third sub-pixel P3 are located in the same column. For example, sub-pixels located in the same column emit light of the same color.

[0242] 3B , the first electrode of the light-emitting element of each subpixel further extends in the first direction D1 and overlaps the second capacitor electrode Cb of the subpixel in the next pixel row perpendicular to the base substrate. Under normal conditions, a fourth insulating layer 204 and a fifth insulating layer 205 are interposed between the first electrode of the light-emitting element and the second capacitor electrode Cb of the subpixel in the next row. If the pixel circuit of the subpixel fails, a repair hole may be formed between the first electrode of the light-emitting element and the second capacitor electrode Cb of the subpixel in the next row. For example, the fourth insulating layer 204 may be removed with a laser, and the first electrode of the light-emitting element may be filled in the repair hole to electrically connect it to the second capacitor electrode Cb of the subpixel in the next row, which in turn may be electrically connected to the first electrode of the light-emitting element of the corresponding subpixel. Therefore, the first electrode of the light-emitting element of the failed subpixel and the first electrode of the light-emitting element of the subpixel in the next row are electrically connected, thereby repairing the failed subpixel. In FIG. 3A, via number 9 indicates the location of the repair hole.

[0243] For example, the color filter portions 190 corresponding to the first pixel row each have a side adjacent to the second pixel row, and for example, the side is linear and parallel to the second direction D2.

[0244] For example, in the direction perpendicular to the base substrate, the color filter section 190 corresponding to the first sub-pixel P1 overlaps with at least one of the multiple first hollow regions H1, and the color filter section 190 corresponding to the second sub-pixel P2 does not overlap with any of the multiple first hollow regions H1.

[0245] For example, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first subpixel P1 overlaps one of the multiple first hollow regions H1 and has a first overlapping area, and the color filter portion corresponding to the second subpixel P2 overlaps another of the multiple first hollow regions H1 and has a second overlapping area, which are different from the first overlapping area.

[0246] For example, the absolute value of the difference between the first overlapping area and the second overlapping area is greater than (n*λ)2 (i.e., an integral multiple of the square of the wavelength), where λ is the longer of the wavelengths of the light emitted from the first sub-pixel P1 and the second sub-pixel P2. The greater the absolute value of the difference between the first overlapping area and the second overlapping area, the less the influence of light diffraction on the display effect.

[0247] As shown in FIG. 3A, in a direction perpendicular to the base substrate, the color filter section 190 corresponding to the first subpixel P1 overlaps one of the multiple first hollow regions H1, while the color filter section 190 corresponding to the second subpixel P2 and the color filter section 190 corresponding to the third subpixel P3 do not overlap any of the multiple first hollow regions H1.

[0248] As shown in FIG. 3A, the second portion 162 of the second scan line 160 corresponding to the second pixel row overlaps with the power line 240, the data line DL, and the detection line 230 in a direction perpendicular to the base substrate, thereby defining a plurality of second hollow regions H2 arranged sequentially along the second direction D2.

[0249] 3A, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first subpixel P1 overlaps one of the plurality of second hollow regions H2 and has a third overlapping area A3, the color filter portion corresponding to the second subpixel P2 overlaps another of the plurality of second hollow regions H2 and has a fourth overlapping area A4, and the third subpixel P3 overlaps yet another of the plurality of second hollow regions H2 and has a fifth overlapping area A5, where the third overlapping area A3, the fourth overlapping area A4, and the fifth overlapping area A5 are all different from each other. For example, as shown in FIG. 3B, A3>A4>A5.

[0250] As shown in Figure 3A, among the multiple first hollow regions H1, none of the first hollow regions H1' adjacent to the fourth subpixel P4 overlaps with the color filter layer in a direction perpendicular to the base substrate, and among the multiple second hollow regions H2, none of the second hollow regions H2' adjacent to the fourth subpixel P4 overlaps with the color filter layer in a direction perpendicular to the base substrate.

[0251] As shown in Figure 3A, the first hollow region H1'' directly adjacent to the first hollow region H1' in the second direction D2 does not overlap with the color filter layer in a direction perpendicular to the base substrate, and the second hollow region H2'' directly adjacent to the second hollow region H2' in the second direction D2 does not overlap with the color filter layer in a direction perpendicular to the base substrate.

[0252] Since the fourth sub-pixel P4 emits white light and the diffraction of white light has little effect on the display uniformity, the hollow area adjacent to the fourth sub-pixel P4 does not need to be shielded.

[0253] For example, as shown in Figure 3B, the first data line DL1, the second data line DL2, and the third data line DL3 all overlap with the color filter layer in the direction perpendicular to the base substrate, which can prevent the data lines from reflecting light and causing display irregularities.

[0254] For example, the fourth data line DL4 does not overlap the color filter layer.

[0255] As shown in FIG. 3B, in a direction perpendicular to the base substrate, the detection line 230 overlaps with the color filter layer, and the overlapping area is smaller than the overlapping area between any of the first data line DL1, the second data line DL2, and the third data line DL3 and the color filter layer.

[0256] Since the fourth data line DL4 and the detection line 230 are closer to the fourth sub-pixel P4 than the first data line DL1, the second data line DL2, and the third data line DL3, and the fourth sub-pixel P4 emits white light, and the diffraction of white light has little effect on the display uniformity, the fourth data line DL4 and the detection line 230 have little effect on the reflection of the light emitted by the first sub-pixel P4, and there is no need to shield the fourth data line and the detection line.

[0257] In some other examples, as shown in FIG. 3C, the first surface microstructure 11 and the second surface microstructure 12 are located on the same power line 240, i.e., the power line 240 functions as the first conductive structure, and the first surface microstructure 11 at least partially overlaps with the second hollow region H2 corresponding to the power line 240 in a direction perpendicular to the base substrate.

[0258] Since the power line 240 is inclined toward the second hollow region H2 and is subjected to a large stress, arranging the first surface microstructure 12 at a location corresponding to the second hollow region H2 of the power line 240 helps to relieve the stress and improve yield.

[0259] In yet other examples, as shown in FIG. 3D, the first surface microstructure 11 and the second surface microstructure 12 are located at the second pole T3d of the third transistor T3, i.e., the second pole T3d of the third transistor T3 functions as the first conductive structure, and the first surface microstructure at least partially overlaps with via number 10 (an example of the fourth via of the present disclosure) in a direction perpendicular to the base substrate.

[0260] In yet another example, as shown in FIG. 3E, the first surface microstructure 11 and the second surface microstructure 12 are located on the first pole T3s of the third transistor T3, i.e., the first pole T3s of the third transistor T3 functions as the first conductive structure, and the first surface microstructure at least partially overlaps with via number 6 in a direction perpendicular to the base substrate.

[0261] 3D and 3E, the first surface microstructure 11 and the second surface microstructure 12 are indicated by black dots. Because the gradient of the first conductive structure at the via is large and the stress is large, arranging the first surface microstructure at the position corresponding to the via of the first conductive structure helps to relieve the stress.

[0262] At least one embodiment of the present disclosure further provides a method for manufacturing the display substrate. Hereinafter, with reference to Figures 3A-3B and 4A-4D, a method for manufacturing a display substrate according to an embodiment of the present disclosure will be described by taking one subpixel as an example, but the embodiments of the present disclosure are not limited thereto. Figures 4A-4D each show the patterns of the first conductive layer, semiconductor layer, second conductive layer, and third conductive layer of one subpixel (e.g., first subpixel P1).

[0263] The manufacturing method includes the following steps S61 to S65.

[0264] Step S61: forming a first conductive material layer, and then performing a patterning process on the first conductive material layer to form the first conductive layer 501 shown in Figure 4A, i.e., the shielding layer 170 and the third capacitor electrode Cc of the storage capacitor Cst, and further forming the detection part 231 and the connection electrode 241, which are insulated from each other.

[0265] Step S62: forming a first insulating layer 201 on the first conductive layer 501, forming a semiconductor material layer on the first insulating layer, and performing a patterning process on the semiconductor material layer to form the semiconductor layer 104 shown in FIG. 4B, i.e., forming an active layer T1a of a first transistor T1, an active layer T2a of a second transistor T2, and an active layer T3a of a third transistor T3 that are spaced apart from each other.

[0266] Step S63: forming a second insulating layer 202 on the semiconductor layer 104, forming a second conductive material layer on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive layer 502 shown in Figure 4C, i.e., forming a gate T1g of the first transistor T1, a gate T2g of the second transistor T2, and a gate T3g of the third transistor T3, which are insulated from each other. An extension portion 180 is also shown in Figure 4C.

[0267] For example, as shown in FIG. 4C, the second conductive layer 502 further includes a first scan line 150 and a second scan line 160 that are insulated from each other.

[0268] For example, the line width of the first scan line 150 and the second scan line 160 is in the range of 5 to 15 microns.

[0269] For example, the first scan line 150 is integral with the gate T2g of the second transistor T2 of the sub-pixel in the corresponding row, and the second scan line 160 is integral with the gate T3g of the third transistor T3 of the sub-pixel in the corresponding row.

[0270] In step S64, the semiconductor layer 204 is conductively treated (e.g., doped) using the second conductive layer 502 as a mask using a self-alignment process, thereby converting the portions of the semiconductor layer 204 not covered by the second conductive layer 502 into conductive materials, thereby obtaining the first capacitor electrode Ca. The active layers of each transistor located on both sides of the channel region are converted into conductive materials to form first and second pole contact regions, respectively, which are used to electrically connect to the first and second poles of the transistors. Figure 4B shows the first and second pole contact regions T1a1 and T1a2 of the active layer T1a of the first transistor T1, the first and second pole contact regions T2a1 and T2a2 of the active layer T2a of the second transistor T2, and the first and second pole contact regions T3a1 and T3a2 of the active layer T3a of the third transistor T3. A connection portion 720 is also shown in Figure 4B.

[0271] For example, before the semiconductor layer 104 is converted into a conductor, an etching process is performed on the second insulating layer 202 to etch all of the areas of the second insulating layer 202 that are not covered with the second conductive layer 502, i.e., the second insulating layer 103 overlaps the second conductive layer 502 in the direction perpendicular to the base substrate 101. In this way, when the areas of the semiconductor layer 204 that are not covered with the second conductive layer 202 are converted into a conductor by ion implantation, the implanted ions are not stopped by the second insulating layer 202.

[0272] Step S65: forming a third insulating layer 203 on the second conductive layer 502, forming a third conductive material layer on the third insulating layer 203, and performing a patterning process on the third conductive material layer to form the third conductive layer 503 shown in FIG. 4D, i.e., forming the first pole T1s and second pole T1d of the first transistor T1, the first pole T2s and second pole T2d of the second transistor T2, and the first pole T3s and second pole T3d of the third transistor T3.

[0273] For example, the third conductive layer 503 further includes a data line DL, a detection line 230 and a power line 240, which are insulated from each other.

[0274] For example, the line width of the data line DL is in the range of 5 to 15 microns, the line width of the detection line 230 is in the range of 5 to 30 microns, and the line width of the power line 240 is in the range of 5 to 30 microns.

[0275] For example, as shown in Figure 4D, the power line 240 is integral with the second pole T1d of the first transistor T1 of the subpixel immediately adjacent thereto. For example, each data line 110 is integral with the second pole T2d of the second transistor T2 of the subpixel connected thereto.

[0276] For example, the material of the semiconductor material layer includes, but is not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (sexithiophene, polythiophene, etc.).

[0277] For example, the first conductive material layer is a light-shielding conductive material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials made of the above metals. For example, the first conductive material layer may be a molybdenum-titanium alloy, and may have a thickness of, for example, 50 to 100 nanometers.

[0278] For example, the materials of the second conductive material layer and the third conductive material layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials made of the above metals, or conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0279] For example, the second conductive material layer has a laminated structure of molybdenum titanium alloy and copper, where the thickness of the molybdenum titanium alloy is 30 to 50 nanometers and the thickness of the copper is 300 to 400 nanometers.

[0280] For example, the third conductive material layer has a laminated structure of molybdenum titanium alloy and copper, where the thickness of the molybdenum titanium alloy is 30 to 50 nanometers and the thickness of the copper is 400 to 700 nanometers.

[0281] For example, the material of the semiconductor material layer includes, but is not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (sexithiophene, polythiophene, etc.).

[0282] For example, the semiconductor layer is made of indium gallium zinc oxide and has a thickness of 30 to 50 nanometers.

[0283] For example, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may be inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, or other silicon oxides, silicon nitride, or silicon nitroxide, or may be insulating materials containing metal nitroxides, such as aluminum oxide, titanium nitride, etc. For example, these insulating layers may be organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc., but the embodiments of the present disclosure are not limited thereto.

[0284] For example, the first insulating layer 201 is made of silicon oxide and has a thickness of 300 to 500 nanometers. For example, the second insulating layer 202 is made of silicon oxide and has a thickness of 100 to 160 nanometers. For example, the third insulating layer is made of silicon oxide and has a thickness of 400 to 600 nanometers.

[0285] For example, referring to FIG. 3B, a fourth insulating layer 204, a color filter layer and a fifth insulating layer 205 may be sequentially formed on the third conductive layer 503, a first electrode 123 of the light-emitting element may be formed on the fifth insulating layer 205, a pixel defining layer 206 may be formed on the first electrode 123, and then a light-emitting layer 124 and a second electrode 122 may be sequentially formed, thus forming the display substrate 10 shown in FIG. 3A.

[0286] For example, the formation of the color filter layer may include steps of first forming a red color filter layer, performing a patterning process on the red color filter layer to form color filter portions corresponding to red subpixels, then forming a green color filter layer, performing a patterning process on the green color filter layer to form color filter portions corresponding to green subpixels, and then forming a blue color filter layer, and performing a patterning process on the blue color filter layer to form color filter portions corresponding to blue subpixels.

[0287] For example, the red color filter layer, the green color filter layer, and the blue color filter layer each have a thickness of 2000 to 3000 nanometers, that is, the thickness of each color filter portion is 2000 to 3000 nanometers.

[0288] For example, cross color can be avoided by forming a light-shielding portion between adjacent sub-pixels by overlapping color filter portions.

[0289] For example, the first surface microstructure and the second surface microstructure can be formed by etching the conductive structure or the signal line of the display substrate to form a concave structure, or by plasma treating the surface of the conductive structure or the signal line.

[0290] At least one embodiment of the present disclosure further provides a display panel, which includes any of the above-mentioned display substrates 10. Note that the display substrate 10 according to at least one embodiment of the present disclosure may or may not include a light-emitting element 125, that is, the light-emitting element 125 may be formed in a panel factory after the manufacturing of the display substrate 10. When the display substrate 10 itself does not include a light-emitting element 125, the display panel according to the embodiment of the present disclosure not only includes the display substrate 10 but also includes a light-emitting element 125.

[0291] For example, the display panel is an OLED display panel, and accordingly, the provided display substrate 10 is an OLED display substrate. As shown in FIG. 5A , for example, the display panel 20 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 10. The encapsulation layer 801 is disposed to seal the light-emitting elements on the display substrate 10 and prevent external moisture and oxygen from penetrating the light-emitting elements and driving circuits and damaging the device. For example, the encapsulation layer 801 may include an organic thin film or a structure in which organic thin films and inorganic thin films are alternately stacked. For example, a water-absorbing layer (not shown) may be disposed between the encapsulation layer 801 and the display substrate 10 to absorb water vapor or sol remaining in the initial manufacturing process of the light-emitting elements. The cover plate 802 may be, for example, a glass cover plate. For example, the cover plate 802 and the encapsulation layer 801 may be integral with each other.

[0292] 5B , the display panel includes an adhesive layer 901 and a metal sealing layer 902 disposed on the display substrate 10. In addition to the sealing function, the metal sealing layer 902 can also support and fix the display substrate 10, for example, in large-size applications, to support the display substrate 10 and reduce stress impact on the display substrate 10. For example, the display substrate 10 has a bottom emission structure, and the metal sealing layer 902 does not block display light.

[0293] At least one embodiment of the present disclosure further provides a display device 30, which includes any of the display substrates 10 or display panels 20 described above, as shown in FIG. 6 , and the display device of this embodiment may be any product or component having a display function, such as a display, an OLED panel, an OLED television, electronic paper, a mobile phone, a tablet PC, a laptop, a digital photo frame, or a navigator.

[0294] For example, the patterning process may use a conventional photoetching process, which includes steps such as applying a photoresist, exposing, developing, drying, and etching.

[0295] The above are only exemplary embodiments of the present invention, and do not limit the protection scope of the present invention, which is determined by the appended claims.

Claims

1. A display substrate comprising: a base substrate; and a first conductive structure located on the base substrate; the first conductive structure has a first surface and a second surface away from the base substrate, the first surface and the second surface being made of the same material, the first surface and the plate surface of the base substrate forming a first included angle, the second surface and the plate surface of the base substrate forming a second included angle different from the first included angle, a first surface microstructure disposed on the first surface, and a second surface microstructure disposed on the second surface; the first conductive structure further has a third surface and a fourth surface adjacent to the base substrate, the third surface facing the first surface, and the fourth surface facing the second surface; the first surface microstructure has a first cross section perpendicular to the base substrate, the first cross section having a first orthogonal projection at the third surface, the length of the first orthogonal projection being shorter than the length of the first surface microstructure at the first cross section; A display substrate, wherein the second surface microstructure has a second cross section perpendicular to the base substrate, the second cross section having a second orthogonal projection at the fourth surface, the length of the second orthogonal projection being shorter than the length of the second surface microstructure at the second cross section.

2. 2. The display substrate of claim 1, wherein in a direction perpendicular to the base substrate, the first surface microstructure at least partially overlaps the third surface, the second surface microstructure at least partially overlaps the fourth surface, and at least one of the third surface and the fourth surface is a flat surface.

3. 3. A display substrate as described in claim 1 or 2, wherein the area of ​​the orthogonal projection of the first surface microstructure on the third surface is smaller than the surface area of ​​the first surface microstructure, and the area of ​​the orthogonal projection of the second surface microstructure on the fourth surface is smaller than the surface area of ​​the second surface microstructure.

4. A display substrate described in any one of claims 1 to 3, wherein the minimum thickness of the first conductive structure at the first surface microstructure is smaller than the average thickness of the first conductive structure and greater than 3 / 5 of the average thickness of the first conductive structure.

5. the first surface microstructure has a first end point, a first intermediate point, and a second end point in the first cross-section, and the second surface microstructure has a third end point, a second intermediate point, and a fourth end point in the second cross-section; a distance between the first intermediate point and the third surface is not equal to a distance between the first end point and the third surface, and a distance between the second end point and the third surface; The display substrate of claim 1 , wherein the distance between the second intermediate point and the fourth surface is not equal to any of the distances between the third end point and the fourth end point and the fourth surface.

6. The display substrate of claim 1 , wherein the first included angle is greater than 0 degrees and the second included angle is equal to 0 degrees.

7. the first surface microstructure has a first end point and a second end point in the first cross-section, and the second surface microstructure has a third end point and a fourth end point in the second cross-section; a distance from a surface of the base substrate to a midpoint of a line segment formed by the first end point and the second end point is different from a distance from a midpoint of a line segment formed by the third end point and the fourth end point, The display substrate of claim 6 , wherein a distance between the first end point and the second end point is greater than a distance between the third end point and the fourth end point.

8. a first insulating layer located on a side of the first conductive structure adjacent to the base substrate; 8. The display substrate of claim 6, wherein the first insulating layer has a first portion and a second portion that are in direct contact with the third surface and the fourth surface of the first conductive structure, respectively, and the minimum thickness of the first portion is smaller than the minimum thickness of the second portion.

9. a second conductive structure located on a side of the first insulating layer adjacent to the base substrate; the first surface microstructure does not overlap the second conductive structure in a direction perpendicular to the base substrate; the first conductive structure is electrically connected to the second conductive structure through a first via that penetrates the first insulating layer; The display substrate of claim 8 , wherein the first surface microstructure overlaps at least a portion of the first via in a direction perpendicular to the base substrate.

10. the first insulating layer comprises a first sub-layer and a second sub-layer stacked together, the second sub-layer being farther from the base substrate than the first sub-layer; 10. The display substrate of claim 9, wherein the first sublayer has a first side exposed by the first via, the second sublayer has a second side exposed by the first via, and at least one of the first side and the second side is in direct contact with the third surface of the first conductive structure.

11. The display substrate of claim 10 , wherein an included angle between the first side surface and the base substrate is smaller than an included angle between the second side surface and the base substrate.

12. A display substrate described in any one of claims 1 to 11, wherein the first surface microstructure has a first end point and a second end point in the first cross section, and the distances between the point of the first cross section closest to the third surface and the first end point and the second end point are not equal.

13. The display substrate of any one of claims 1 to 12, wherein the first surface microstructure comprises a first concave structure and the second surface microstructure comprises a second concave structure.

14. further comprising a plurality of sub-pixels located on the base substrate; the plurality of sub-pixels are arranged as a plurality of pixel columns and a plurality of pixel rows along a first direction and a second direction intersecting the first direction; each of the plurality of sub-pixels comprises a first transistor, a second transistor, a third transistor and a storage capacitor on the base substrate; a first pole of the second transistor electrically connected to a first capacitor electrode of the storage capacitor and to a gate of the first transistor, a second pole of the second transistor configured to receive a data signal, a gate of the second transistor configured to receive a first control signal, and the second transistor configured to write the data signal to the gate of the first transistor and to the storage capacitor in response to the first control signal; a first electrode of the first transistor is electrically connected to a second capacitor electrode of the storage capacitor and is arranged to be electrically connected to a first electrode of a light-emitting element, a second electrode of the first transistor is arranged to receive a first power supply voltage, and the first transistor is arranged to control a current for driving the light-emitting element by controlling a voltage of a gate of the first transistor; 14. The display substrate of claim 1, wherein a first electrode of the third transistor is electrically connected to a first electrode of the first transistor and a second capacitor electrode of the storage capacitor, and a second electrode of the third transistor is arranged to be connected to a detection circuit.

15. 15. The display substrate of claim 14, wherein components in the first direction and the second direction of the center distance between the orthogonal projection of the first surface microstructure on the base substrate and the orthogonal projection of the second surface microstructure on the base substrate are smaller than the average size in the first direction and the second direction of each of the plurality of subpixels, respectively.

16. 16. The display substrate according to claim 14, further comprising an extension portion protruding from the gate of the first transistor, the extension portion extending from the gate of the first transistor along the second direction, at least partially overlapping with and electrically connecting to the first pole of the second transistor in a direction perpendicular to the base substrate.

17. 17. The display substrate of claim 16, wherein the active layer of the second transistor comprises a first pole contact region, a second pole contact region, and a channel region located between the first pole contact region and the second pole contact region, and the first pole of the second transistor is electrically connected to the first pole contact region, the extension portion, and the first capacitor electrode through a second via, respectively.

18. The display substrate of claim 17 , wherein the second via extends along the first direction and exposes at least a portion of a surface of the extension and two side surfaces facing each other in the first direction.

19. the extending portion divides the second via into a first groove and a second groove, the first electrode of the second transistor fills the first groove and the second groove and covers the two side surfaces of the extending portion; the first pole of the second transistor comprises a first portion, a second portion, and a third portion; 19. The display substrate of claim 18, wherein the second portion covers the surface of the extension portion, the first portion covers the first groove, the third portion covers the second groove, and the first portion and the third portion further cover the two side surfaces of the extension portion, respectively.

20. 20. The display substrate of claim 19, wherein the first conductive structure is a first pole of the second transistor, and the first surface microstructure and the second surface microstructure are both located on a third portion of the first pole of the second transistor.

21. The display substrate of claim 20 , wherein the size of the first surface microstructure in the first direction is less than one-tenth of the maximum size of the third portion in the first direction.

22. 22. The display substrate of claim 20 or 21, wherein the size of the first surface microstructure in the first direction is smaller than one tenth of the maximum size of the second via in the first direction of an orthogonal projection on the base substrate.

23. Each of the plurality of sub-pixels further includes the light-emitting element, and the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are sequentially stacked, the first electrode being closer to the base substrate than the second electrode, and the first electrode of the light-emitting element being electrically connected to a first pole of a first transistor of the sub-pixel in which the light-emitting element is located via a third via; the first electrode of the light-emitting element includes a first electrode portion, a second electrode portion, and a third electrode portion connected in sequence in the first direction, the first electrode portion being used to electrically connect to a first pole of a corresponding first transistor and overlapping with the first pole of the corresponding first transistor in a direction perpendicular to the base substrate; 23. The display substrate according to claim 14, wherein the third electrode portion of the light emitting element at least partially overlaps the opening region of the light emitting element in a direction perpendicular to the base substrate.

24. a sum of a maximum size of the first electrode portion in the first direction and a maximum size of the third electrode portion in the second direction is smaller than a sum of a maximum size of the third electrode portion in the first direction and a maximum size of the third electrode portion in the second direction; 24. The display substrate of claim 23, wherein a sum of a maximum size in the first direction and a maximum size in the second direction of the second electrode portion is smaller than a sum of a maximum size in the first direction and a maximum size in the second direction of the third electrode portion.

25. the display substrate comprises a plurality of first surface microstructures and a plurality of second surface microstructures, a portion of the plurality of first surface microstructures and the plurality of second surface microstructures overlapping with the first electrode portion in a direction perpendicular to the base substrate, and another portion of the plurality of first surface microstructures and the plurality of second surface microstructures overlapping with the third electrode portion in a direction perpendicular to the base substrate; 25. The display substrate of claim 23, wherein the distribution density of the first surface microstructure and the second surface microstructure overlapping the first electrode portion is higher than the distribution density of the first surface microstructure and the second surface microstructure overlapping the third electrode portion.

26. A display substrate described in any one of claims 23 to 25, wherein the average size in the second direction of the second electrode portion of the first electrode of the light-emitting element is smaller than the average size in the second direction of the first electrode portion, and is also smaller than the average size in the second direction of the third electrode portion.

27. the plurality of pixel rows comprises a first pixel row, the first pixel row is divided into a plurality of pixel portions, each pixel portion comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along the second direction; 27. The display substrate of claim 23, further comprising a first scan line extending along the second direction, the first scan line being electrically connected to gates of second transistors in the first, second, and third sub-pixels to provide the first control signal.

28. a color filter layer located on a side of the first electrode of the light-emitting element that is closer to the base substrate; 28. The display substrate of claim 27, wherein the color filter layer includes a plurality of color filter portions corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, and light emitted from the first sub-pixel, the second sub-pixel, and the third sub-pixel passes through the corresponding color filter portions and exits the display substrate to form display light of three basic colors.

29. 29. The display substrate of claim 28, wherein, in a direction perpendicular to the base substrate, each of the plurality of color filter units overlaps with a third electrode unit of a first electrode of a light-emitting element of a corresponding sub-pixel, but does not overlap with a first electrode unit of a first electrode of a light-emitting element of the corresponding sub-pixel.

30. the first scan line is located on a side of the color filter layer that is close to the base substrate; 30. The display substrate of claim 29, wherein a portion of a second electrode portion of a first electrode of a light-emitting element of the first sub-pixel that overlaps with the first scan line further overlaps with a color filter portion corresponding to the first sub-pixel in a direction perpendicular to the base substrate.

31. the first scanning line includes a first portion and a second portion that are alternately connected, and the second portion further includes a plurality of first signal lines that have an annular structure and extend along the first direction; The display substrate of any one of claims 28 to 30, wherein, in a direction perpendicular to the base substrate, the plurality of first signal lines overlap with second portions of the first scanning lines to define a plurality of first hollow regions arranged along the second direction.

32. 32. The display substrate of claim 31, wherein, in a direction perpendicular to the base substrate, the color filter portion corresponding to the first sub-pixel overlaps with at least one of the plurality of first hollow regions, and the color filter portion corresponding to the second sub-pixel does not overlap with any of the plurality of first hollow regions.

33. In a direction perpendicular to the base substrate, a color filter portion corresponding to the first sub-pixel overlaps one of the plurality of first hollow regions and has a first overlapping area, and a color filter portion corresponding to the second sub-pixel overlaps another of the plurality of first hollow regions and has a second overlapping area; The display substrate of claim 31 , wherein the first overlapping area and the second overlapping area are different.

34. the display substrate comprises a plurality of first surface microstructures and a plurality of second surface microstructures, some of the first surface microstructures and the plurality of second surface microstructures overlap with first portions of the first scan lines in a direction perpendicular to the base substrate, and other portions of the first surface microstructures and the plurality of second surface microstructures overlap with second portions of the first scan lines in a direction perpendicular to the base substrate; 34. The display substrate of claim 33, wherein the distribution density of the first surface microstructures and the second surface microstructures overlapping the second portion of the first scan line in a direction perpendicular to the base substrate is higher than the distribution density of the first surface microstructures and the second surface microstructures overlapping the first portion of the first scan line.

35. the first overlapping area is greater than an area of ​​an orthogonal projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate; 35. The display substrate of claim 34, wherein the second overlap area is greater than an area of ​​an orthogonal projection of each of the plurality of first surface microstructures or the second surface microstructures on the base substrate.

36. the pixel unit further includes a fourth sub-pixel arranged to emit white light; A display substrate as described in any one of claims 31 to 35, wherein among the plurality of first hollow regions, none of the first hollow regions adjacent to the fourth sub-pixel overlaps with the color filter layer in a direction perpendicular to the base substrate.

37. the plurality of first signal lines include a plurality of data lines connected to the plurality of pixel columns in one-to-one correspondence; For the first pixel row, the plurality of data lines are divided into a plurality of data line groups corresponding one-to-one to the plurality of pixel portions, and each data line group includes a first data line, a second data line, and a third data line connected to the first sub-pixel, the second sub-pixel, and a third sub-pixel, respectively; 37. The display substrate of claim 31, wherein for each pixel portion, the first data line, the second data line, and the third data line connected to the pixel portion are all located between the first sub-pixel and the third sub-pixel.

38. further comprising a plurality of power lines extending along the first direction; 38. The display substrate of claim 37, wherein the plurality of power supply lines are arranged to provide the first power supply voltage to the plurality of sub-pixels, and at least one pixel column is interposed between each of the plurality of power supply lines and any one of the plurality of data lines.

39. the display substrate has a plurality of first surface microstructures and a plurality of second surface microstructures, a portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures are distributed to the plurality of data lines, and another portion of the plurality of first surface microstructures and a portion of the plurality of second surface microstructures are distributed to the plurality of power lines; 39. The display substrate of claim 38, wherein the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of data lines is higher than the distribution density of the plurality of first surface microstructures and the plurality of second surface microstructures on the plurality of power lines.

40. the second sub-pixel is directly adjacent to the third sub-pixel, the third sub-pixel having first and second sides opposing each other in the second direction; 40. The display substrate of claim 37, wherein the second data line and the third data line are located on a first side of the third sub-pixel and between the second sub-pixel and the third sub-pixel.

41. the second data line and the third data line at least partially overlap the color filter layer in a direction perpendicular to the base substrate; the pixel unit further includes a fourth sub-pixel arranged to emit white light; each of the data line groups further includes a fourth data line connected to the fourth sub-pixel; 41. The display substrate of claim 37, wherein the fourth data line does not overlap the color filter layer in a direction perpendicular to the base substrate.

42. A display device comprising the display substrate according to any one of claims 1 to 41.

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