Current-mode signal path for an integrated radio-frequency pulse generator

Abstract

The current-mode end-to-end signal path includes a digital-to-analog converter (DAC) operating in current mode and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Description

[Technical Field]

[0001] The present disclosure relates to integrated radio frequency (RF) pulse generators, and more particularly to utilizing a current-mode end-to-end signal path to reduce power consumption and increase linearity between a digital-to-analog converter (DAC) and adjacent stages in the signal chain. [Background technology]

[0002] Quantum computing generally refers to the use of quantum mechanical phenomena to perform computing and information processing functions. Quantum computing can be contrasted with classical computing, which typically operates on binary values ​​using transistors. That is, while classical computers can operate with two basis states, 0 or 1, quantum computers operate with quantum bits ("qubits") that contain probability-based superpositions of both 0 and 1, can involve multiple qubits, and can utilize interference. Quantum computing is emerging as a new paradigm that solves a wide variety of problems that represent undesirable scaling for traditional classical high-performance computers. The ability to generate arbitrary waveforms with variable amplitude and low distortion is desirable for multiple aspects, including qubit control, in the field of quantum computing. A key circuit within an arbitrary waveform generator (AWG) is the digital-to-analog converter (DAC), which is useful in a variety of applications, including wireless transmitters and qubit-controlled pulse implementations. Minimizing power consumption for such designs is beneficial, particularly in the area of ​​cryogenic signal generation for qubit control. There are several challenges in designs that utilize voltage-mode representation for signal paths, including high dynamic range requirements at block interfaces, which leads to nonlinear behavior and the generation of unwanted distortion products. Another challenge is the significant power consumption per block, which does not allow for power efficiencies gained from current recycling. Summary of the Invention

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements of particular embodiments or claims, nor to delineate the scope of particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, and / or computer program product facilitates an integrated radio frequency pulse generator system, and more particularly, utilizes a current-mode end-to-end signal path to reduce power consumption and improve linearity between a digital-to-analog converter (DAC) and adjacent stages in the signal chain. This can facilitate achieving a favorable set of tradeoffs between power consumption and distortion.

[0004] According to one embodiment, a system for generating a radio frequency signal comprises: a digital-to-analog converter (DAC) operating in current mode; and an upconverting mixer operating in current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

[0005] According to one aspect, the system further comprises a radio frequency (RF) attenuator operating in current mode with the DAC and the upconverting mixer.

[0006] According to one aspect, the system further comprises an output component operating in current mode with the DAC, the upconverting mixer, and the RF attenuator.

[0007] According to one aspect, the system further comprises an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction.

[0008] According to one aspect, at least one of the DAC, the upconverting mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component.

[0009] In one embodiment, a system for generating a radio frequency signal comprises: a digital-to-analog converter (DAC) operating in current mode; and a baseband filter and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC, the baseband filter, and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

[0010] According to one aspect, the system further comprises a radio frequency (RF) attenuator operating in current mode with the DAC, the baseband filter, and the upconverting mixer.

[0011] According to one aspect, the system further comprises output components operating in current mode with the DAC, the baseband filter, the upconverting mixer, and the RF attenuator.

[0012] According to one aspect, the system further comprises an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction.

[0013] According to one aspect of the system, at least one of the DAC, the baseband filter, the upconverting mixer, the RF attenuator, the output component, or the offset component is a cryo-electronic component.

[0014] According to one embodiment, the system further comprises two or more DACs in quadrature, two or more upconversion mixers in quadrature, and an adder that generates a sum of the output signals of the upconversion mixers.

[0015] According to one embodiment, a method comprises using a digital-to-analog converter (DAC) operating in current mode; and using an upconverting mixer operating in current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and wherein the DAC generates a baseband signal.

[0016] According to one aspect, the method further comprises using a radio frequency (RF) attenuator operating in current mode in conjunction with the DAC and the upconverting mixer.

[0017] According to one aspect, the method further comprises using output components operating in current mode with the DAC, the upconverting mixer, and the RF attenuator.

[0018] According to one aspect, the method further comprises applying current-mode offset cancellation to use an offset component to facilitate local oscillator (LO) leakage signal reduction.

[0019] According to one aspect, at least one of the DAC, the upconverting mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component.

[0020] In one embodiment, a method comprises using a digital-to-analog converter (DAC) operating in current mode; and using a baseband filter and an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC, the baseband filter, and the upconverting mixer are represented as currents, and where the DAC generates a baseband signal.

[0021] According to one aspect, the method further comprises using a radio frequency (RF) attenuator operating in current mode with the DAC, the baseband filter, and the upconverting mixer.

[0022] According to one aspect, the method further comprises using output components operating in current mode with the DAC, the baseband filter, the upconverting mixer, and the RF attenuator.

[0023] According to one aspect, the method further comprises applying current-mode offset cancellation using an offset component to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the DAC, the baseband filter, the upconverting mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component.

[0024] According to one embodiment, the method further comprises using two or more DACs in quadrature, two or more upconversion mixers in quadrature, and an adder that generates a summed output of the output signals of the upconversion mixers.

[0025] In one embodiment, a computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the program instructions being executable by a processor to cause the processor to perform the following steps: use a digital-to-analog converter (DAC) operating in current mode; and use an upconverting mixer operating in current mode and operably coupled to the DAC, where analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and where the DAC generates a baseband signal.

[0026] According to one aspect of the computer program product, the program instructions are executable by the processor to further cause the processor to use a radio frequency (RF) attenuator operating in current mode with the DAC and the upconverting mixer. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 shows a block diagram of an exemplary system implementation that implements an integrated radio frequency (RF) pulse generator that utilizes a current-mode signal path.

[0028] [Figure 2] An exemplary framework of a methodology for integrating a radio frequency (RF) pulse generator utilizing a current-mode end-to-end signal path is presented.

[0029] [Figure 3] 1 illustrates an example architecture of a radio frequency (RF) pulse generator signal chain.

[0030] [Figure 4] 1 illustrates an example architecture of one current-mode implementation of an end-to-end signal path from a digital-to-analog converter (DAC) to an output.

[0031] [Figure 5]1 illustrates an exemplary schematic diagram of one transistor-level implementation of a baseband filter, an upconverting mixer, and a radio frequency (RF) attenuator.

[0032] [Figure 6] 1 illustrates an exemplary schematic diagram of one transistor-level implementation of a baseband filter, an upconverting mixer, and a radio frequency (RF) attenuator.

[0033] [Figure 7] 1 shows exemplary simulation results of the overall radio frequency (RF) pulse generator signal chain.

[0034] [Figure 8] 1 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0035] [Figure 9] 1 illustrates a block diagram of an exemplary non-limiting cloud computing environment in accordance with one or more embodiments of the present disclosure.

[0036] [Figure 10] 1 illustrates a block diagram of exemplary non-limiting abstraction model layers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0037] The following detailed description is merely illustrative and is not intended to limit the embodiments and / or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any express or implied information presented in the foregoing Summary section or the Detailed Description section. One or more embodiments will now be described with reference to the drawings, in which like reference numerals are utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that one or more embodiments may be practiced in various instances without these specific details.

[0038] The present disclosure generally relates to an RF pulse generator system and method that implements a current-mode end-to-end path from a digital-to-analog converter (DAC) to an output, thereby enabling a set of favorable tradeoffs in power consumption and distortion to be achieved. The signal path elements are the DAC, baseband filter, mixer, attenuator, and output chain components. Implementing the entire chain in current mode can provide advantages. It should be understood that in embodiments, a radio frequency digital-to-analog converter (RFDAC) can optionally be utilized.

[0039] Embodiments integrate an RF pulse generator that utilizes a current-mode transconductance-capacitance filter that receives the output current from a DAC and generates a filtered current. Current-mode signal processing is well-suited for low-distortion applications because it reduces voltage swings at various nodes of interest. Another advantage of current-mode circuits is that they enable current reuse, whereby bias and signal currents from one stage are shared with other stages (typically by stacking circuit stages). Reuse improves the power efficiency of the circuit by reducing the total current drawn from the power supply. However, conventional current-mode input filters using operational amplifiers consume a significant amount of power and are limited to high-frequency applications. The embodiments disclosed and claimed herein offer a promising solution to this problem by introducing a current-mode signal path design into the implementation of an integrated RF pulse generator. Implementing an efficient current-mode filter stage can be a key part in realizing the proposed end-to-end current-mode signal path, which is developed for low power consumption through the exploitation of current recycling and for increased end-to-end linearity by minimizing voltage-to-current and current-to-voltage conversions. Low power signal requirements are an advantage for the system in efficiently implementing the signal chain. Furthermore, the integrated RF pulse generator solution allows for a cascaded solution using current-mode techniques.

[0040] Quantum computing utilizes qubits as its essential units instead of classical computing bits. A qubit (e.g., a quantum binary digit) is the quantum mechanical analogue of a classical bit. While a classical bit can use only one of two basis states (e.g., 0 or 1), a qubit can use a superposition of those basis states (e.g., α|0>+β|1>, where α and β are complex scalars (|α| 2 +|β| 2=1), theoretically allowing some qubits to hold exponentially more information than the same number of classical bits. Thus, quantum computers (e.g., computers that use qubits instead of simply classical bits) could theoretically quickly solve problems that would be extremely difficult for classical computers. A classical computer's bits are simple binary digits, either 0 or 1. Almost any device with two distinct states—such as a switch, valve, magnet, coin, or similar binary-type state measurement—can function to represent a classical bit. Qubits, with their quantum mystique, can occupy a superposition of 0 and 1 states. Qubits cannot have intermediate values ​​such as 0.63; when a qubit's state is measured, the result is either 0 or 1. However, in the course of a computation, a qubit can behave as if it were a mixture of, for example, 63 percent 0 and 37 percent 1 states. A typical quantum program requires coordination of the quantum and classical parts of the computation. One way to think about a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, translating the algorithm into an executable form, running experiments or simulations, and analyzing the results. A concept that runs through these processes is the use of intermediate representations. An intermediate representation (IR) of an operation is neither the source language description itself nor the target machine instructions, but something in between. A compiler may utilize some IR during the process of translating and optimizing a program. The input is source code describing the quantum algorithm and compile time parameters. The output is a combined quantum / classical program expressed using high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic; thus, measurements of algorithm outputs provide a likely solution within a confidence interval specific to the algorithm. Operations are repeated until a satisfactory solution with high probability can be achieved.

[0041] By processing information using the laws of quantum mechanics, quantum computers offer novel means for performing computational tasks such as molecular computing, optical photons, optimization, and many more. Many algorithms and system components are introduced to efficiently perform these computational tasks. In particular, radio frequency (RF) pulse generators (often incorporating one or more digital-to-analog converters) are useful in a variety of applications, including wireless transmitters and the implementation of control pulses for qubits. Several challenges exist in designs utilizing voltage-mode representations for signal paths, including high dynamic range requirements at block interfaces, which lead to nonlinear behavior and the generation of distortion products at higher amplitudes. Another challenge is the significant power consumption per block, which precludes the power efficiency benefits gained from current recycling. Thus, embodiments herein propose a current-mode end-to-end signal path to facilitate achieving a favorable set of tradeoffs for power consumption and distortion. These benefits can be best realized by implementing the entire chain in current mode.

[0042] FIG. 1 shows a block diagram of an exemplary system 100 that can access and process data using the illustrated variable computing components according to one or more embodiments described herein. System 100 can facilitate the process of evaluating and identifying large amounts of data in various forms, using machine learning, and training neural networks or other types of models. System 100 can also generate predictive recommendations at an individual level in the context of one or more embodiments described herein. Aspects of a system (e.g., system 100, etc.), apparatus, or process described in this disclosure may constitute machine-executable components embodied within a machine, e.g., embodied in one or more computer-readable medium(s) associated with one or more machines. Such components, when executed by one or more machines (e.g., computers, computing devices, virtual machines, etc.), can cause the machine to perform the operations described herein. Repeated descriptions of similar elements used in one or more embodiments described herein have been omitted for the sake of brevity.

[0043] System 100 facilitates an integrated radio frequency (RF) pulse generator utilizing a current-mode signal path. Embodiments relate to retaining the following elements of the signal path: digital-to-analog converter (DAC) 102, baseband filter 104, upconverting mixer 106, radio frequency (RF) attenuator 108, output component 112 (e.g., a current-mode amplifier), and offset component 114. Implementing the entire chain in current mode can provide advantages. While FIG. 1 illustrates the use of baseband filter 104, upconverting mixer 106, and RF attenuator 108 together, other embodiments may omit one or more of these components and cascade the components in any suitable manner.

[0044] System 100 may optionally include a server device, one or more networks, and one or more devices (not shown). System 100 may also include or be associated with a digital-to-analog converter 102, which operates in a current mode in which the analog inputs and analog outputs of a system block are represented as currents. For example, the digital signal input to DAC 102 may be baseband digital I and Q data representing any suitable signal, such as, but not limited to, a signal for a wireless transmitter or a signal for implementing control pulses for qubits. The analog output of DAC 102 in the form of a current may be directed to baseband filter 104. The baseband current output of baseband filter 104 is frequency converted to an RF frequency by upconverting mixer 106, which is driven by a local oscillator (LO) signal. Optionally, the LO signal waveform may use a complementary metal-oxide semiconductor (CMOS) rail-to-rail level, such as that generated by a CMOS inverter. The radio frequency (RF) attenuator 108 operates in conjunction with the DAC 102, the baseband filter 104, and the upconverting mixer 106. The output component 112 receives the output current of the RF attenuator 108. In some embodiments, the output component 112 can include an impedance transformation component (e.g., a transformer or a current-mode amplifier). A corresponding signal chain can produce an output current signal using the DAC 102, the baseband filter 104, the upconverting mixer 106, and the RF attenuator 108. Any DC offset in the baseband signal (e.g., a DC offset in the output current of the baseband filter 104) is converted by the upconverting mixer into an unwanted LO tone (LO “leakage”) in the output of the RF pulse generator system 100. To suppress such LO leakage, DC offset cancellation can be applied by the offset component 114, which adds a compensating DC offset to the baseband signal.The DAC 102, the baseband filter 104, the upconverting mixer 106, the RF attenuator 108, the output component 112, or the offset component 114 may be a cryoelectronic component (eg, an electronic component capable of operating at cryogenic temperatures).

[0045] In one implementation, a current-mode end-to-end path from the digital-to-analog converter (DAC) 102 to the output component 112 facilitates achieving a favorable set of tradeoffs for power consumption and distortion. In this signal path, the DAC 102 operates in current mode to implement an integrated DAC solution, in which the baseband filter 104, embedded with the upconverting mixer 106 and RF attenuator 108, operates in current mode, where analog input and output signals between system blocks are represented as currents. The upconverting mixer 106 is driven by an LO signal, which may optionally use complementary metal-oxide semiconductor (CMOS) rail-to-rail levels. The radio frequency (RF) attenuator 108 operates in conjunction with the DAC 102, baseband filter 104, and upconverting mixer 106. This methodology facilitates low output signal requirements, enabling an efficient implementation of the signal chain. Thus, the current-mode signal path of an integrated RF pulse generator solution can help reduce power consumption through the use of current recycling, improve end-to-end linearity by minimizing voltage-to-current and current-to-voltage conversions, and enable cascaded solutions using current-mode techniques.

[0046] System 100 may be any suitable computing device or set of computing devices that may be communicatively coupled to devices, non-limiting examples of which include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated test system, a network storage device, a communication device, a web server device, a network switch device, a network routing device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device may be any device that can communicate information with system 100 and / or any other suitable device that may utilize information provided by system 100. It should be understood that system 100, components, models, or devices may be deployed with communication components (not shown) that enable communication between systems, components, models, devices, etc. in one or more networks.

[0047] The components of system 100 may be connected either directly or through one or more networks. Such networks may include cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs), and may include wired and wireless networks, including, by way of non-limiting example, cellular, WAN, Wireless Fidelity (Wi-Fi), Wi-Max, WLAN, radio communications, microwave communications, satellite communications, optical communications, acoustic communications, or any other suitable communications technology. Furthermore, the aforementioned systems and / or devices have been described with respect to interactions between several components. It can be understood that such systems and components may include these components or subcomponents designated therein, some of the designated components or subcomponents, and / or additional components. Subcomponents may also be implemented as components communicatively coupled to other components rather than comprising a parent component. Furthermore, one or more components and / or subcomponents may be combined into a single component that provides aggregate functionality. Components may also interact with one or more other components not specifically described herein for brevity but known to those skilled in the art.

[0048] The computer processing systems, methods, apparatus, and / or computer program products of the present application can be used to solve new problems that arise through advances in technology, computer networks, the Internet, and the like.

[0049] In today's digital world, one of the largest growth areas in electronics continues to be wireless communications applications. Modern radio frequency systems, such as 3G / 4G / 5G base stations, are based on wideband, multi-channel architectures. To facilitate flexibility in signal generation, modulation, and processing, current RF transmitters typically employ one or more high-speed digital-to-analog converters (DACs). These high-speed DACs provide arbitrary waveform generation capabilities for RF signals, which are useful in other applications. One such application is the control of qubits in quantum computing, where it is necessary to generate RF control pulses with varying amplitude and low distortion (high spectral purity). Minimizing power consumption for such RF pulse generators is beneficial, particularly in the context of cryogenic signal generation for qubit control. Design challenges utilizing voltage-mode representations for signal paths include high dynamic range requirements at block interfaces, which leads to nonlinear behavior and the generation of distortion products at higher amplitudes. Thus, these embodiments propose a promising solution to this challenge by introducing a current-mode signal path design into the implementation of an integrated RF pulse generator system. Through this method, impedance levels are lower, resulting in lower signal swings and allowing system 100 to operate at lower supply voltages. For a given supply voltage, dynamic range can be maximized, with noise level becoming one of the limitations, if not the only limitation. Also, the overall impedance at the interface node is lower, which translates into greater bandwidth.

[0050] FIG. 2 illustrates an exemplary framework 200 of a methodology for integrating a radio frequency (RF) pulse generator utilizing a current-mode end-to-end signal path. In some aspects of this framework, at 202, a digital-to-analog converter (DAC) is operated in current mode, and at 204, an upconverting mixer operably coupled to the DAC is operated in current mode. At 206, the analog inputs and analog outputs of the DAC and upconverting mixer are represented as currents, and the DAC generates a baseband signal. At 208, the methodology utilizes a radio frequency (RF) attenuator operating in current mode along with the DAC and upconverting mixer. It should be understood that a subset of steps 204, 206, or 208 may optionally be present. Thus, this framework integrates a DAC interface with the upconverting mixer and RF attenuator to generate an output, thereby providing the entire chain operating in current mode (or optionally implementing sub-elements of the chain in current mode). Functionality is implemented in current mode, and any two blocks interface in current mode. At certain stages, current-mode signals are utilized, and these signals can be attenuated and multiplied. Starting with the baseband filters, current-mode signals are scaled up / down within the circuit stages, at the interfaces between stages, and, optionally, within impedance matching networks, where the impedance matching networks are part of the output component stage. These methods can reduce end-to-end power consumption through the exploitation of current recycling and increase end-to-end linearity (reducing distortion) by minimizing voltage-to-current and current-to-voltage conversions. Low output signal requirements aid in efficient implementation of the signal chain, and the method enables cascaded solutions using current-mode techniques.

[0051] FIG. 3 illustrates an exemplary architecture of an RF pulse generator signal chain, including two or more DACs (303, 305) in quadrature, two or more baseband filters 306, 308 in quadrature, two or more upconverting mixers in quadrature, and a summer that generates a summed output of the upconverting mixers' respective output signals. Unlike conventional systems, in this embodiment, each sub-block is implemented in current mode, and all analog signals transferred between the sub-blocks are represented as currents. It should be understood that the inputs (e.g., digital words) to the DACs (303, 305) are digital. One way to generate complex signals is to modulate a carrier signal frequency with a local oscillator using a vector modulator. In RF applications, baseband digital I and Q signals are generated using an arbitrary waveform generator (AWG) that includes two or more synchronized digital-to-analog converters (DACs). The RF pulse generator signal chain architecture 300 receives baseband digital BBI 302 and BBQ 304 signals. Multi-bit baseband digital-to-analog converters (DACs) 303 and 305 use digital bits to convert them to analog signals according to the signal bandwidth and sampling clock frequency. This allows current output, and the filtered and amplified current is provided to upconverting mixers 310 and 312. The signal is processed through low-pass filters 306 and 308 to reject out-of-band noise components originating from the DACs (303, 305). The filtered signal is mixed and upconverted by upconverting mixers 310 and 312 using two carriers (LO-Q and LO-I) with quadrature phases of 0 and 90 degrees for I and Q. The resulting signals are combined using signal combiner 311 to create a single sideband signal representation.For example, if an (x*y) function needs to be implemented in single sideband representation, then the variable x can be expressed as a combination of 0 and 90 degrees, and the variable y can be expressed as a combination of 0 and 90 degrees. These two variables can then be multiplied and added, similar to the scalar product of two vectors. The output of this function is processed through the driver DRV 314. The matching network MN 316 is a component typically composed of passive elements that do not add distortion. The matching network 316 transforms the resistor 318 (e.g., 50 ohms) to the impedance required by the driver to maximize power transfer. In the RF pulse generator system 300, the outputs of the DACs (303, 305) are filtered and upconverted using I-channel and Q-channel mixers, and the resulting signals are combined and presented through the driver and matching network to a rated load (e.g., 50 ohms) at the output 320. The filter implementation and the interface between the filter and other elements of the signal chain are important in such designs. Continuous-time filters are well suited for high dynamic range and low power effective filter implementations. Conventional current-mode input filters using operational amplifiers consume significant amounts of power and have limitations in high frequency applications. Continuous-time G. m -C filters generally provide a high input impedance, which results in higher distortion production. m -C type filters are well suited for high frequency applications, but are very limited in the dynamic range they support because their input is typically a voltage.

[0052] Current-mode signal processing is well suited for low-distortion applications because it reduces voltage swings at various nodes of interest. Another advantage of current-mode circuits is current reuse, whereby bias and signal currents from one stage are shared with other stages (e.g., commonly by stacking circuit stages). Reuse improves the power efficiency of the circuit by reducing the total current drawn from the power supply. However, conventional current-mode input filters using, for example, operational amplifiers, consume significant amounts of power and have limitations for high-frequency applications. Efficient current-mode filter stages can facilitate the realization of end-to-end current-mode signal paths for low power consumption through the exploitation of current reuse and can enhance end-to-end linearity by minimizing voltage-to-current and current-to-voltage conversions. Low output signal requirements are advantageous for efficient implementation of the signal chain.

[0053] 4 shows an example architecture of one current-mode implementation of the end-to-end RF pulse generator signal path from DAC to output. The architecture illustrated in 400 is a simplified diagram of this current-mode implementation, where two DACs (DAC-I 402 and DAC-Q 404) are utilized to generate the I and Q portions of the baseband signal. The voltage V DD 406, 408 and binary scaled current sources I 0...k , 410, 412, 414, and 416 are used to generate DAC outputs 426 and 428 that are proportional to the binary input code. The differential current switches 418 and 422 operate at a sampling frequency of Fs, but the net currents injected into the DAC outputs 426 and 428 can be centered around zero (bipolar current signaling) by subtracting a DC current using current sources 420 and 424. These currents are expressed as I FS / 2, where I FSis the full-scale current range of the DAC. Using a current-mode architecture allows this DC current subtraction using a simple "dot" current source.

[0054] The DAC outputs 426 and 428 are currents and are delivered to two differential baseband filters BBF-I 430 and BBF-Q 432. The outputs of the baseband filters provide some scaling of the current by using multiple current sources in parallel. It will be appreciated that current reuse is possible as the output currents of the baseband filters 430, 432 provide bias currents for the upconversion mixers 434, 436 and the RF attenuator 438. This is typically done with well-known current mirrors, and the output currents are then fed to an in-phase local oscillator (LO) signal F LOI and quadrature LO signal F LOQThe output of the baseband filters 430 and 432 passes through upconverting mixers 434 and 436, driven by . The upconverted current output from the mixers goes to an RF attenuator 438, which functions by dumping some of the upconverted current to a positive power supply (away from the output load). The amount of attenuation achieved depends on how many of the differential current switches are operated to dump their output currents. The use of individual differential current switches allows for switching the attenuation with low latency and coarse step sizes. (For finer, slower changes in gain and signal level, the number of active current sources creating the output currents of the baseband filters 430 and 432 can be varied, thereby providing a programmable 1:P current mirror ratio.) The current attenuation provided by the RF attenuator 438 attenuates both the signal and noise by a scalar amount with no loss in dynamic range. The output of the RF attenuator 438 is delivered to an output component (e.g., 112 in FIG. 1), which in this case is an impedance-matching transformer 439 that provides a differential-to-single-ended conversion (i.e., a balun function). Based on the turns ratio of the transformer 439, it can also provide passive current amplification (PCA). The PCA transformer is a passive current amplification block that uses a differential input signal for current and provides a single-ended output to a 50-ohm load. This final stage converts the current-mode signaling to some amount of (relatively small) voltage swing. This architecture is one combination in which attenuation is performed in a series current path. Current attenuation and amplification can be performed in many series and parallel combinations based on the available voltage headroom and linearity requirements.

[0055] 5 shows an example schematic diagram of a transistor-level implementation 500 of an RF pulse generator system for a single-phase (I) RF output signal. (Parallel copies of these transistor circuits can be used to generate quadrature (Q) RF signal components, as shown in the block diagram of FIG. 4.) To generate a differential signal, the transistor-level implementation 500 is formed from two half circuits, with the top half circuit providing the positive signal (e.g., i outp ), and the lower half of the circuit generates a negative signal (e.g., i outn ) to generate a baseband filter 512. Similar components in the two halves are identified by the same reference numerals, with the script "a" for the top half and the script "b" for the bottom half. For brevity, these components will be described herein using their unscripted reference numerals. The implementation 500 includes a baseband filter 512, an upconversion mixer 506, and an RF attenuator 520. The embodiment of the baseband filter 512 shown in FIG. 5 has a frequency response that is proportional to the transconductance (G m ) and capacitance (C). As shown in the figure, m1 507 and G m2 509 represent the transconductance of a transistor, and C1 523 and C2 525 represent capacitors.

[0056] In this embodiment, a current i receives input from a digital-to-analog converter (DAC) 521. in The input current mode interface for 502 is a common gate stage M NC1 / M NC2 The exemplary baseband filter provided by (510, 519) has a low input impedance suitable for a current mode interface, whereas the conventional continuous time G m -C filters generally provide a high input impedance.

[0057] Transistor M N2 513 and MN1 The negative feedback loop implemented using 516 is NC1 By adjusting the current in 510, the input impedance at low frequencies (within the loop bandwidth) is further reduced, which in turn reduces the input impedance of the current source device M PB This coincides with that of M NC1 510, resulting in a very low input impedance. NC2 Stabilize the current in 519. By Kirchhoff's law of current (KCL), M NC1 510 and M NC2 When the current in 519 is stabilized (kept constant), the input current i in A change equal to the change in 502 occurs in transistor M N1 At higher frequencies, two poles are introduced by the capacitors C1 523 and C2 525, which in turn causes the N1 The current in 516 is the input current i in 502. The filtering provided by these two poles is classically known as a biquad filter, and such a filter has a quadratic transfer function. When filtering is performed, the current mirror transistor M N1 516 and M NMX 518 (e.g., used as a baseband VGA or BBVGA) provides the effective gain. The ratio of these two transistors provides the current gain, thus realizing the effective gain block. As shown in the drawing, the transistor width (number of effective fingers) can be varied to provide a programmable current gain. In the transmitter aspect, filtering is performed first, then the current gain is obtained. This order can be changed for processing smaller signals or for lower sensitivity. This is a technique that allows for a current mode architecture. Then, transistor M NMX The output current i of 518 (used as BBVGA, for example) out527 is delivered directly to the upconverting mixer 506 and RF attenuator 520 stages. The output current of the RF attenuator 520 then goes to the output component (112 in FIG. 1), which in this case is the matching network transformer M N-xfmr 522. Finally, the matching network transformer M N-xfmr 522 provides the RF signal to the output 524. As illustrated in this schematic, any implementation stage utilizes current-mode signaling, with the blocks interfaced in current mode. Signals can be attenuated and multiplied, so the components shown in the conventional architecture achieve a current gain, where the gain can be greater or less than one. Starting with the baseband filter, it is possible to scale the current interface up / down in current mode (e.g., transistor M N1 516 and M NMX 518). It is also possible to select the parameters (eg, turns ratio) of the matching network transformer MN-xfmr 522 to provide current gain.

[0058] 6 shows an example schematic diagram of a transistor-level implementation 600 of an RF pulse generator system for a single-phase (I) RF output signal. (Parallel copies of these transistor circuits can be used to generate quadrature (Q) RF signal components, as shown in the block diagram of FIG. 4.) To generate a differential signal, the transistor-level implementation 600 is formed from two half circuits, with the top half circuit providing the positive signal (e.g., i outp ), and the lower half of the circuit generates a negative signal (e.g., i outn) to generate a baseband filter 612. Similar components in the two halves are identified by the same reference numerals, with the script "a" used for the top half and the script "b" used for the bottom half. For brevity, these components will be described herein using their unscripted reference numerals. Implementation 600 is similar to implementation 500 (FIG. 5), but uses an additional folded-cascode stage 601 with a quiescent current adjustment element that allows operation with various ratios of dynamic current to quiescent current. Transistor-level implementation 600 includes a baseband filter 612, an upconverting mixer 606, and an RF attenuator 620. The embodiment of baseband filter 612 shown in FIG. 6 has a frequency response that is proportional to the transconductance (G m It is similar to the conventional Gm-C filter in that it depends on the values ​​of the capacitance (C) and the capacitance (C).

[0059] As shown in the transistor-level implementation 600 diagram, G m1 607 and G m2 609 represent the transconductance of a transistor, and C1 623 and C2 625 represent capacitors. In this embodiment, a current i in The input current mode interface for 602 is a common gate stage M NC1 / M NC2 The exemplary baseband filter provided by (610, 619) has a low input impedance suitable for a current mode interface, whereas the conventional continuous time G m -C filters generally provide high input impedance. N2 613 and M N1 The negative feedback loop implemented using 616 is NC1 By adjusting the current in 610, the input impedance at low frequencies (within the loop bandwidth) is further reduced, which in turn reduces the input impedance of the current source device M PB This coincides with that of M NC1610, resulting in a very low input impedance. NC2 Stabilize the current in 619. By Kirchhoff's law of current (KCL), M NC1 610 and M NC2 When the current in 619 is stabilized (kept constant), the input current i in A change equal to the change in 602 occurs in transistor M N1 At higher frequencies, two poles are introduced by the capacitors C1 623 and C2 625, which causes the N1 The current in 616 is the input current i in 602 is (low-pass) filtered.

[0060] The filtering provided by these two poles is classically known as a biquad filter, and such a filter has a quadratic transfer function. N1 The current in 616 is forwarded to upconverting mixer 606 by a well-known current mirror circuit. Implementation 600 (in contrast to implementation 500) uses an additional folded-cascode stage 601 in this path, so that there are now two current mirrors capable of providing effective current gain. These current mirrors are connected to transistors M N1 616 and M NMC 630, and the mirror formed by transistor M MX 632 and M NMX 618. Together, these two current mirror stages can be used as a baseband VGA or BBVGA, where the current gain is N1 616 and M NMC 630, and the width ratio of the transistor M MX 632 and M NMX618. As shown in the drawing, the transistor width (number of effective fingers) can be varied to provide programmable current gain. While the use of two current mirror stages provides additional flexibility in adjusting the current gain of the signal path, the main advantage of implementation 600 is that the addition of folded cascode stage 601 provides a mechanism for adjusting the ratio of dynamic (i.e., signal) current to quiescent (i.e., static bias) current. Specifically, transistor M BFC 634 (which acts as a current source) can be used as a quiescent current regulation element because it has its own DC bias current and the NMC The difference between the DC bias currents of 630 MX 632 determines the quiescent (i.e., static bias) current in the current mirror transistor M MX 632 and M NMX In the case of a large current gain provided by 618, the upconverting mixer 606 and RF attenuator 620 operate at a smaller DC current level, so that M MX Significant power savings can be realized by reducing the quiescent current in 632 (thereby increasing the ratio of dynamic current to quiescent current), a technique that enables current-mode architectures with improved power efficiency.

[0061] Next, transistor M NMX 618 (used as a BBVGA, for example) output current i out627 is delivered directly to the upconverting mixer 606 and RF attenuator 620 stages. The output current of the RF attenuator 620 then goes to the output component (112 in FIG. 1), which in this case is the matching network transformer M N-xfmr 622. Finally, the matching network transformer M N-xfmr 622 provides the RF signal to the output 624. As illustrated in this schematic, any implementation stage utilizes current-mode signaling, with the blocks interfaced in current mode. Signals can be attenuated and multiplied, so the components shown in the conventional architecture achieve a current gain, where the gain can be greater than or less than one. Starting with the baseband filter, it is possible to scale the current interface up / down in current mode (e.g., by using transistors M N1 616, M NMC 630, M MX 632, and M NMX 618). It is also possible to select the parameters (eg, turns ratio) of the matching network transformer MN-xfmr 622 to provide current gain.

[0062] Figure 7 shows an example simulation result of the overall radio frequency pulse generator signal chain. The spectrum shown in this figure was obtained by performing a fast Fourier transform (FFT) of the output signal. In this circuit simulation, a 10-bit DAC operating at a 1 GHz sampling rate generates an 85 MHz sine wave input that is applied to the current-mode end-to-end signal path. The upconverting mixer is driven by a 5.355 GHz LO signal. The I and Q signals are chosen to create a lower sideband tone 704 at a frequency of 5.355 - 0.085 = 5.27 GHz. As shown in the simulation result 700, over a 1 GHz wideband (4.5 to 5.5 GHz), the maximum distortion product 702 is 57 dB, which is below the desired tone 704, resulting in a simulated spurious-free dynamic range (SFDR) of 57 dB. Over the same 1 GHz wideband, the simulated signal-to-noise and distortion ratio (SNDR) is 52.7 dB. Considering that the signal-to-noise ratio (SNR) of an ideal 10-bit DAC is only 62 dB, these simulated SFDR and SNDR figures represent excellent performance, especially for such a power-efficient implementation: a voltage-mode single-sideband (SSB) upconverter, a voltage-dependent RF attenuator, an operational transconductance amplifier (OTA) based baseband filter, and a reference high-input impedance G m Prior art has implemented functionality similar to the -C filter implementation. Voltage-mode SSB upconverters cause nonlinearities. Voltage-dependent RF attenuators introduce signal loss and additional circuit loading. OTA-based baseband filter implementations use higher power and area. Finally, the reference high input impedance G mThe -C filter implementation is more nonlinear. However, the embodiments disclosed herein facilitate a cascaded solution using current-mode techniques, enabling an input current-mode interface. Furthermore, the proposed embodiments minimize voltage-to-current and current-to-voltage conversions, improving end-to-end linearity and reducing distortion. These embodiments also take advantage of low output signal requirements and leverage current steering to minimize signal loss within the signal chain. Finally, these embodiments utilize current mirroring, utilizing less area and power, creating an inherent bridge between the baseband current output and the RF current input. This allows for reduced end-to-end power consumption through current reuse.

[0063] The current-mode solution provides a strategy for current reuse and low distortion optimized for the requirements of cryogenic waveform generation. In these embodiments, in contrast to conventional techniques, voltage is generated only at the final output stage, interfacing the remaining stages with low impedance, thus leading to high linearity and high bandwidth. The techniques described in this disclosure are also applicable to other high-bandwidth communication systems and can be implemented in commercial CMOS technologies. The approach of the exemplary embodiments described herein provides an innovative strategy for implementing CMOS-controlled pulse-generating analog circuits that enables increased scalability of future quantum computing systems and can serve as a building block for cryo-CMOS implementations.

[0064] To provide a context for various aspects of the disclosed subject matter, Figure 8 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 8 illustrates a block diagram of an exemplary non-limiting operating environment that may facilitate one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0065] 8, a suitable operating environment 800 for implementing various aspects of the disclosure may also include a computer 812. The computer 812 may also include a processing unit 814, a system memory 816, and a system bus 818. The system bus 818 couples system components including, but not limited to, the system memory 816 to the processing unit 814. The processing unit 814 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 814. The system bus 818 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), CardBus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (registered trademark) (IEEE 1394), and Small Computer System Interface (SCSI).

[0066] The system memory 816 may also include volatile memory 820 and nonvolatile memory 822. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 812, such as during start-up, is stored in the nonvolatile memory 822. The computer 812 may also include removable and non-removable, volatile and non-volatile computer storage media. FIG. 8 illustrates, for example, disk storage 824. Disk storage 824 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 824 may also include storage media separately from or in combination with other storage media. A removable or non-removable interface, such as interface 826, is typically used to facilitate connection of the disk storage 824 to the system bus 818. FIG. 8 also illustrates software that acts as an intermediary between the basic computer resources and users described within the suitable operating environment 800. Such software may also include, for example, an operating system 828. Operating system 828 , which can be stored on disk storage 824 , acts to control and allocate resources of the computer 812 .

[0067] System applications 830 take advantage of the management of resources by operating system 828 through program modules 832 and program data 834, stored, for example, in either system memory 816 or disk storage 824. It should be understood that the present disclosure may be implemented with various operating systems or combinations of operating systems. Users enter commands or information into computer 812 through input devices 836. Input devices 836 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, and the like. These and other input devices connect to processing unit 814 through system bus 818 via interface ports 838. Interface ports 838 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 840 use several of the same types of ports as input devices 836. Thus, for example, a USB port may be used to provide input to computer 812 and to output information from computer 812 to output device 840. Output adapter 842 is provided to illustrate that there are some output devices 840, such as monitors, speakers, and printers, among other output devices 840, that require special adapters. Output adapters 842 include, by way of example and not limitation, video and sound cards that provide a means of connection between output device 840 and system bus 818. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer(s) 844.

[0068] The computer 812 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 844. The remote computer 844 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device or other common network node, and may generally include many or all of the elements described relative to the computer 812. For purposes of simplicity, only a memory storage device 846 is shown with the remote computer 844. The remote computer 844 is logically connected to the computer 812 through a network interface 848 and is then physically connected via a communication connection 850. The network interface 848 encompasses wired and / or wireless communication networks such as a local area network (LAN), a wide area network (WAN), a cellular network, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 850 refer to the hardware / software utilized to connect network interface 848 to system bus 818. For clarity of illustration, communications connection(s) 850 are shown internal to computer 812, but could also be external to computer 812. The hardware / software for connecting to network interface 848 could also include, by way of example only, internal and external technologies such as ordinary telephone-grade modems, cable modems, modems including DSL modems, ISDN adapters, Ethernet cards, etc.

[0069] Referring now to FIG. 9 , an exemplary cloud computing environment 950 is illustrated. As shown, the cloud computing environment 950 includes one or more cloud computing nodes 910 with which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or cellular phone 954A, a desktop computer 954B, a laptop computer 954C, and / or an automobile computer system 954N, may communicate. Although not shown in FIG. 9 , the cloud computing node 910 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, etc.) with which the local computing devices used by the cloud consumers can communicate. The nodes 910 may communicate with each other, which may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 950 to provide infrastructure, platform, and / or software as a service without the cloud consumer having to maintain resources on their local computing devices. It should be understood that the types of computing devices 954A-954N illustrated in FIG. 9 are intended to be exemplary only, and that computing node 910 and cloud computing environment 950 can communicate with any type of computerized device through any type of network and / or network-addressable connection (e.g., using a web browser).

[0070] 10, a set of functional abstraction layers provided by cloud computing environment 950 (FIG. 9) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 10 are intended to be exemplary only, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0071] Hardware and software layer 1060 includes hardware and software components. Examples of hardware components include mainframe 1061, RISC (Reduced Instruction Set Computer) architecture-based servers 1062, servers 1063, blade servers 1064, storage devices 1065, and network and networking components 1066. In some embodiments, software components include network application server software 1067, quantum platform routing software 1068, and / or quantum software (not shown in FIG. 10 ).

[0072] The virtualization layer 1070 provides an abstraction layer from which the following example virtual entities can be provided: virtual servers 1071, virtual storage 1072, virtual networks including virtual private networks 1073, virtual applications and operating systems 1074, and virtual clients 1075.

[0073] In one example, management layer 1080 may provide the functions described below. Resource provisioning 1081 provides dynamic procurement of computing resources and other resources utilized to perform tasks within the cloud computing environment. Metering and pricing 1082 provides cost tracking and charging or billing for the consumption of resources as they are utilized within the cloud computing environment. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 1083 provides access to the cloud computing environment for consumers and system administrators. Service level management 1084 provides cloud computing resource allocation and management to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 1085 provides advance arrangements and procurement for cloud computing resources that anticipate future requirements according to SLAs.

[0074] The workload layer 1090 provides examples of functionality for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this layer include mapping and navigation 1091, software development and lifecycle management 1092, virtual classroom instructional delivery 1093, data analytics processing 1094, transaction processing 1095, and quantum state preparation software 1096.

[0075] The present invention may be a system, method, apparatus, and / or computer program product integrated at any conceivable level of technical detail. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium itself is not considered to be a transitory signal, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0076] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a respective computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in the computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider).In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0077] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium capable of instructing a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium having the instructions stored thereon comprises a product having instructions that implement aspects of the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams. The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational acts to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0078] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in the blocks may occur out of the order depicted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending on the functionality involved, or the blocks may possibly be executed in the reverse order. It may also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0079] While the present subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one computer and / or multiple computers, those skilled in the art will recognize that the present disclosure can also be combined with or practiced in conjunction with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the computer-implemented methods of the present invention can be practiced with single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, and other computer system configurations, including computers, handheld computing devices (e.g., PDAs, phones), and microprocessor-based or programmable consumer or industrial electronic devices. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0080] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functionalities. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of example, both an application running on a server and the server may be a component. One or more components may reside within a process and / or thread of execution, and a component may be localized on one computer and / or distributed between two or more computers. In other examples, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes, for example, according to signals comprising one or more data packets (e.g., data from one component interacting with other components in a local system, a distributed system, and / or with other systems via signals over a network such as the Internet). As another example, a component may be a device having specific functionality provided by mechanical parts operated by electrical or electronic circuitry operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides specific functionality without mechanical parts through electronic components that may include a processor or other means for executing software or firmware that provides at least part of the functionality of the electronic component.In one aspect, the component can emulate an electronic component via a virtual machine, for example, in a cloud computing system.

[0081] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specifically stated otherwise or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, "X uses A or B" is satisfied if X uses A, if X uses B, or if X uses both A and B, in any of the foregoing examples. Furthermore, the articles "a" and "an," as used in this specification and the accompanying drawings, should generally be construed to mean "one or more" unless specifically stated otherwise or clear from the context to refer to the singular form. The terms "example" and / or "exemplary" are used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0082] The term "processor" as used herein may refer to virtually any computing processing unit or device, including, but not limited to, a single-core processor; a single processor with software multithreading execution capabilities; a multi-core processor; a multi-core processor with software multithreading execution capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Furthermore, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or improve the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "memory," "storage," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory" or a "memory component" entity embodied in a component that includes memory. It should be recognized that memory and / or memory components described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to, these and any other suitable types of memory.

[0083] The foregoing includes merely exemplary systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many more combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "includes," "has," and "possesse" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising," as "comprising" is interpreted when used as a transitional term in a claim.

[0084] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications or technical improvements found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. (Other possible items) (Item 1) a current-mode digital-to-analog converter (DAC); and an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; 1. A system for generating a radio frequency signal, comprising: (Item 2) Item 10. The system of item 1, further comprising a radio frequency (RF) attenuator operating in current mode with the DAC and the upconversion mixer. (Item 3) Item 3. The system of item 2, further comprising an output component operating in current mode with the DAC, the upconverting mixer, and the RF attenuator. (Item 4) 4. The system of any one of items 1 to 3, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction. (Item 5) 5. The system of claim 3, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the DAC, the upconverting mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component. (Item 6) 1. A system for generating a radio frequency signal, comprising: a current-mode digital-to-analog converter (DAC); and a baseband filter and an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the baseband filter, the DAC, and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; A system comprising: (Item 7) 7. The system of claim 6, further comprising a radio frequency (RF) attenuator operating in current mode with the DAC, the baseband filter, and the upconversion mixer. (Item 8) 8. The system of claim 7, further comprising an output component operating in current mode with the DAC, the baseband filter, the upconversion mixer, and the RF attenuator. (Item 9) 9. The system of any one of items 6 to 8, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction. (Item 10) 10. The system of claim 8 or 9, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the DAC, the baseband filter, the upconverting mixer, the RF attenuator, the output component, or the offset component is a cryo-electronic component. (Item 11) 11. The system of any one of items 6 to 10, further comprising two or more DACs in a quadrature relationship, two or more upconversion mixers in a quadrature relationship, and an adder that generates a summed output of the output signals of the upconversion mixers. (Item 12) using a digital-to-analog converter (DAC) operating in current mode; and using an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein the analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; A method for providing (Item 13) Item 13. The method of item 12, further comprising using a radio frequency (RF) attenuator operating in current mode with the DAC and the upconversion mixer. (Item 14) Item 14. The method of item 13, further comprising using output components operating in current mode with the DAC, the upconverting mixer, and the RF attenuator. (Item 15) 15. The method of any one of items 12 to 14, further comprising applying current-mode offset cancellation to use an offset component to facilitate local oscillator (LO) leakage signal reduction. (Item 16) Item 16. The method of item 15, wherein at least one of the DAC, the upconverting mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component. (Item 17) using a digital-to-analog converter (DAC) operating in current mode; and using a baseband filter and an upconverting mixer operating in current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC, the baseband filter, and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; A method for providing (Item 18) Item 18. The method of item 17, further comprising using a radio frequency (RF) attenuator operating in current mode with the DAC, the baseband filter, and the upconversion mixer. (Item 19) 20. The method of claim 18, further comprising using output components operating in current mode with the DAC, the baseband filter, the upconversion mixer, and the RF attenuator. (Item 20) 20. The method of claim 19, further comprising applying current-mode offset cancellation to use an offset component to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the DAC, the baseband filter, the upconversion mixer, the output component, the RF attenuator, or the offset component is a cryo-electronic component. (Item 21) 21. The method of any one of items 17 to 20, further comprising using two or more DACs in quadrature, two or more up-conversion mixers in quadrature, and an adder that generates a summed output of the output signals of the up-conversion mixers. (Item 22) 1. A computer program product comprising a computer-readable storage medium having program instructions embodied thereon, using a digital-to-analog converter (DAC) operating in current mode; and using an upconverting mixer operating in current mode and operably coupled to the DAC, wherein the analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; the program instructions are executable by the processor to cause the processor to Computer program products. (Item 23) 23. The computer program product of claim 22, wherein the program instructions are executable by the processor to further cause the processor to use a radio frequency (RF) attenuator operating in current mode with the DAC and the upconverting mixer.

Claims

1. a digital-to-analog converter (DAC) operating in current mode; an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; and a radio frequency (RF) attenuator coupled to the upconverting mixer; A system comprising: the DAC, the upconverting mixer, and the RF attenuator are cryoelectronic components; Current-mode signals transmitted between the DAC and an output component in the system are converted to voltage swings only at the output of the output component. A system for generating a radio frequency signal.

2. 10. The system of claim 1, further comprising the radio frequency (RF) attenuator operating in current mode with the DAC and the upconverting mixer.

3. 3. The system of claim 2, wherein the output components operate in current mode with the DAC, the upconverting mixer, and the RF attenuator.

4. The system of claim 1 , further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction.

5. 4. The system of claim 3, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the output component or the offset component is a cryo-electronic component.

6. 1. A system for generating a radio frequency signal, comprising: a digital-to-analog converter (DAC) operating in current mode; a baseband filter and an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the baseband filter, the DAC, and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; and a radio frequency (RF) attenuator coupled to the upconverting mixer; Equipped with the DAC, the upconverting mixer, and the RF attenuator are cryoelectronic components; Current-mode signals transmitted between the DAC and an output component in the system are converted to voltage swings only at the output of the output component. system.

7. The system of claim 6 , comprising the radio frequency (RF) attenuator operating in current mode with the DAC, the baseband filter, and the upconverting mixer.

8. 8. The system of claim 7, wherein the output components operate in current mode with the DAC, the baseband filter, the upconverting mixer, and the RF attenuator.

9. The system of claim 6 , further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction.

10. 10. The system of claim 8, further comprising an offset component that applies current-mode offset cancellation to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the baseband filter, the output component, or the offset component is a cryo-electronic component.

11. 7. The system of claim 6, further comprising: two or more DACs in quadrature; two or more upconverting mixers in quadrature; and an adder that generates a sum of output signals of the upconverting mixers.

12. using a digital-to-analog converter (DAC) operating in current mode; using an upconverting mixer operating in a current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; and using a radio frequency (RF) attenuator coupled to the upconversion mixer Equipped with the DAC, the upconverting mixer, and the RF attenuator are cryoelectronic components; Current-mode signals transmitted between the DAC and the output component are converted to voltage swings only at the output of the output component. method.

13. The method of claim 12, wherein the radio frequency (RF) attenuator operates in current mode together with the DAC and the upconverting mixer.

14. The method of claim 13, wherein the output components operate in current mode together with the DAC, the upconverting mixer, and the RF attenuator.

15. 15. The method of claim 14, further comprising applying current-mode offset cancellation to use an offset component to facilitate local oscillator (LO) leakage signal reduction.

16. The method of claim 15, wherein at least one of the output component or the offset component is a cryo-electronic component.

17. using a digital-to-analog converter (DAC) operating in current mode; using a baseband filter and an upconverting mixer operating in current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC, the baseband filter, and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; and using a radio frequency (RF) attenuator coupled to the upconversion mixer Equipped with the DAC, the upconverting mixer, and the RF attenuator are cryoelectronic components; Current-mode signals transmitted between the DAC and the output component are converted to voltage swings only at the output of the output component. method.

18. The method of claim 17, wherein the radio frequency (RF) attenuator operates in current mode together with the DAC, the baseband filter, and the upconverting mixer.

19. The method of claim 18, wherein the output components operate in current mode together with the DAC, the baseband filter, the upconverting mixer, and the RF attenuator.

20. 20. The method of claim 19, further comprising applying current-mode offset cancellation using an offset component to facilitate local oscillator (LO) leakage signal reduction, wherein at least one of the baseband filter, the output component, or the offset component is a cryo-electronic component.

21. 18. The method of claim 17, further comprising using two or more DACs in quadrature, two or more upconverting mixers in quadrature, and a summer to generate a summed output of the output signals of each of the upconverting mixers.

22. 1. A computer program comprising program instructions, A procedure using a digital-to-analog converter (DAC) operating in current mode; using an upconverting mixer operating in current mode and operably coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal; and using a radio frequency (RF) attenuator coupled to the upconverting mixer. the program instructions are executable by the processor to cause the processor to the DAC, the upconverting mixer, and the RF attenuator are cryoelectronic components; Current-mode signals transmitted between the DAC and the output component are converted to voltage swings only at the output of the output component. Computer program.

23. The computer program of claim 22, wherein the radio frequency (RF) attenuator operates in current mode together with the DAC and the upconverting mixer.

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