Method for stripping and cleaning semiconductor structures

Abstract

A method for removing oxide and cleaning a silicon-on-insulator structure is disclosed. The method may include immersing the silicon-on-insulator structure in a stripping bath to strip the oxide from a surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure is immersed in an ozone bath containing ozone. The ozone-treated silicon-on-insulator structure may be immersed in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to clean the structure.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Non-Provisional Patent Application No. 17 / 670,167, filed February 11, 2022, which is incorporated by reference in its entirety.

[0002] The field of the disclosure relates to methods for removing oxide from silicon-on-insulator (SOI) structures and methods for cleaning such structures. [Background technology]

[0003] Semiconductor structures, such as silicon-on-insulator structures ("SOI" structures), are sometimes subjected to an anneal prior to downstream processing. This anneal can result in the formation of an oxide (SiO2) on the surface of the SOI structure. This oxide is typically removed from the top surface of the structure. After the oxide is removed, when the structure is cleaned, some areas on the surface of the silicon-on-insulator structure form raised protrusions or "bumps" on the wafer surface. Previous attempts to remove the protrusions, such as by lengthening the duration of the stripping process, have not been successful in eliminating the protrusion formation.

[0004] A need exists for a method for removing oxide on the top surface of an SOI structure and a method for cleaning the structure that reduces or eliminates raised protrusions from the surface of the SOI structure.

[0005] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0006] One aspect of the present disclosure relates to a method for stripping and cleaning the surface of a silicon-on-insulator structure. The silicon-on-insulator structure includes a handle structure, a silicon top layer, and a dielectric layer disposed between the handle structure and the silicon top layer. The silicon-on-insulator structure has an oxide film on the top surface of the silicon-on-insulator structure. The silicon-on-insulator structure is immersed in a stripping bath to strip the oxide film from the surface of the silicon-on-insulator structure and produce a stripped silicon-on-insulator structure. The stripping bath includes hydrofluoric acid and a surfactant. The stripped silicon-on-insulator structure is immersed in an ozone bath including ozone to produce an ozone-treated silicon-on-insulator structure. The ozone-treated silicon-on-insulator structure is immersed in an SC-1 bath including ammonium hydroxide and hydrogen peroxide to produce an SC-1-treated silicon-on-insulator structure.

[0007] Various refinements of the features noted in connection with the foregoing aspects of the present disclosure exist. Additional features may also be incorporated into the foregoing aspects of the present disclosure as well. These refinements and additional features may exist individually or in any combination. For example, the various features described below in connection with any of the illustrated embodiments of the present disclosure may be incorporated, alone or in any combination, into any of the foregoing aspects of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a cross-sectional view of a donor structure having a donor wafer with a dielectric layer thereon. [Figure 2] FIG. 2 is a cross-sectional view of a donor structure during ion implantation. [Figure 3] FIG. 10 is a cross-sectional view of a donor structure bonded to a handle structure. [Figure 4] FIG. 2 is a cross-sectional view of the bonded wafer structure when the donor structure is cleaved at the cleavage plane. [Figure 5] A method for removing oxide and cleaning silicon-on-insulator structures. [Figure 6] 1 is another embodiment of a method for removing oxide and cleaning a silicon-on-insulator structure. [Figure 7] 1 is another embodiment of a method for removing oxide and cleaning a silicon-on-insulator structure. [Figure 8] 1 is a reproduction of an AFM image of nano-sized defects formed by a conventional method of cleaning a silicon-on-insulator structure by removing oxide. [Figure 9] 9 is a graph illustrating the height of the defect shown in Figure 8. Corresponding reference characters indicate corresponding parts throughout the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present disclosure provides a method for stripping and cleaning the surface of a semiconductor structure. In some embodiments, oxides (e.g., SiO2) are removed from the surface of the semiconductor structure by immersing the semiconductor structure in a stripping bath containing hydrofluoric acid and a surfactant. After stripping, the semiconductor structure is immersed in a bath containing ozone to remove defects (e.g., nanoscale defects) before a subsequent cleaning operation, preventing the defects from acting as an etch mask and forming protrusions on the surface of the semiconductor structure.

[0010] The present method can generally be applied to remove oxide from any semiconductor structure (e.g., a single layer structure or a bonded structure), such as any bonded wafer structure from which it is desired to remove oxide. The semiconductor structure to be cleaned according to embodiments of the present disclosure has a front surface, a back surface, a periphery, and a central axis. The semiconductor structure may be of any diameter suitable for use by those skilled in the art, including, for example, substrates with a diameter of about 200 mm, about 300 mm, greater than about 300 mm, or even about 450 mm.

[0011] In some embodiments, the structure being processed may be a silicon-on-insulator structure. Such a structure may include a handle wafer, a silicon layer (sometimes referred to as a "silicon device layer" or a "silicon top layer"), and a dielectric layer disposed between the handle wafer and the silicon layer. The following is just one example of a method for fabricating a silicon-on-insulator structure; other methods may be used unless otherwise specified.

[0012] An example of a donor structure 30 that may be bonded to a handle structure to form a bonded wafer structure is shown in FIG. 1. The donor structure 30 may be formed with a dielectric layer 15 deposited on the front side of the donor wafer 12. Alternatively, the dielectric layer 15 may be grown or deposited on the handle wafer, or a dielectric layer may be grown on both the donor wafer and the handle wafer, and it should be understood that these structures may be bonded in any of a variety of configurations, without limitation. A suitable donor wafer 12 may be composed of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, and any combination thereof. In some embodiments, the donor wafer is composed of single crystal silicon.

[0013] Dielectric layer 15 may be any electrically insulating material suitable for use in SOI structures, such as materials containing SiO, SiN, aluminum oxide, or magnesium oxide. In some embodiments, dielectric layer 15 is SiO (i.e., the dielectric layer consists essentially of SiO). In embodiments in which the dielectric layer is silica (SiO), the dielectric layer may be referred to as a "buried oxide" or "BOX" layer 15. Dielectric layer 15 may be applied according to any technique known in the art, such as thermal oxidation, wet oxidation, thermal nitridation, or a combination of these techniques.

[0014] For example, as shown in FIG. 2 , ions (e.g., hydrogen atoms, helium atoms, or a combination of hydrogen and helium atoms) may be implanted at a substantially uniform depth below the front surface 22 of the donor structure to define the cleave plane 17. It should be understood that when helium ions and hydrogen ions are co-implanted into the structure to form the cleave plane 17, they may be implanted simultaneously or sequentially. In some embodiments, the ions are implanted prior to the deposition of the dielectric layer 15. If the implantation occurs prior to the deposition of the dielectric layer 15, the subsequent growth or deposition of a dielectric layer on the donor wafer 12 is preferably performed at a temperature low enough to prevent premature separation or cleavage of the donor layer along the plane 17 (i.e., prior to the wafer bonding processing step).

[0015] The handle structure 10 (FIG. 3) may include a handle wafer made of any suitable material for fabricating multilayer structures, such as silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, quartz, and combinations thereof. The handle structure 10 may include a dielectric layer deposited on the handle wafer, or, as in other embodiments, may consist solely of the handle wafer (i.e., without a dielectric layer). The handle wafer and donor wafer may be single-crystal silicon wafers, or may be single-crystal silicon wafers sliced ​​from single-crystal ingots grown according to conventional Czochralski crystal growth methods.

[0016] As shown in FIG. 3 , the front surface of the dielectric layer 15 of the donor structure is preferably bonded to the front surface of the handle structure 10, forming a bonded wafer structure 20 through a bonding process. The dielectric layer 15 and the handle structure 10 may be bonded together, with surface activation performed, for example, by exposing the surfaces of the structures to a plasma containing oxygen or nitrogen. The wafers are then pressed together, forming a bond therebetween at a bonded interface 18. In general, wafer bonding may be achieved using essentially any technique known in the art, provided that the energy employed to achieve the formation of the bonded interface is sufficient to ensure that the integrity of the bonded interface is maintained during subsequent processing (i.e., layer transfer due to separation along the cleavage or separation plane 17 of the donor wafer).

[0017] Once fabricated, the bonded wafer structure 20 is placed in a cleaving device for separating (i.e., cleaving) a portion of the donor wafer along the cleave plane from the bonded wafer structure to form a layered semiconductor structure (e.g., an SOI structure). Generally, the cleaving device may induce this fracture using techniques known in the art, such as thermally and / or mechanically induced cleaving techniques.

[0018] Referring to Figure 4, upon separation, two structures 30, 31 are formed. Because separation of the bonded wafer structure 20 occurs along the cleave plane 17 of the donor structure 12 (Figure 3), portions of the donor structure remain part of both structures (i.e., portions of the donor wafer are transferred along with the dielectric layer 15). Structure 30 includes portions of the donor wafer. Structure 31 is an SOI structure and includes the handle structure 10, the dielectric layer 15, and a silicon top layer 25 (the portion of the donor wafer that remains after cleaving) disposed on top of the dielectric layer 15. In embodiments in which both the donor structure and the handle structure include dielectric layers, the dielectric layers combine to form the dielectric layer 15 of the SOI structure.

[0019] The cleaving device used to separate the bonded wafer structures along the cleave plane may be a mechanical cleaving device in which separation is induced or achieved by mechanical force, either alone or in addition to annealing. For example, the bonded structures may be placed in a fixture in which a mechanical force is applied perpendicular to opposing sides of the bonded structures to pull a portion of the donor structure away from the bonded structure.

[0020] An exemplary cleaving device includes a suction cup that applies a mechanical force near the cleave tip of the bonded wafer structure 20. Separation of a portion of the donor wafer may be initiated by applying a mechanical wedge or blade to the edge of the bonded wafer at the cleave plane 17 to initiate propagation of a crack along the cleave plane 17. The mechanical force applied by the suction cup then pulls the portion of the donor structure from the bonded structure, thus forming an SOI structure. Mechanical cleaving devices are commercially available, such as Debond & Cleave Tools from Silicon Genesis Corporation (San Jose, California).

[0021] In an alternative embodiment, the cleaving device is a thermal cleaving device in which fracture is achieved by annealing the bonded structure. For example, thermal cleaving may be performed under inert (e.g., argon or nitrogen) atmosphere or ambient conditions at temperatures between about 200°C and about 800°C, or between about 250°C and about 650°C, for at least about 10 seconds, at least about 1 minute, at least about 15 minutes, at least about 1 hour, or even at least about 3 hours (higher temperatures require shorter annealing times, and vice versa). The thermal cleaving device may be a belt furnace, in which propagation of the cleave is achieved at the leading edge of the bonded structure (i.e., in the direction of travel of the structure through the furnace) and progresses toward the trailing edge of the bonded wafer structure. Other types of cleaving devices may also be used.

[0022] The layers of the SOI structure 31 (handle structure 10, dielectric layer 15, and silicon top layer 25) can generally have any thickness that enables the layers to function as described herein. In some embodiments, the silicon top layer 25 is relatively thin (e.g., about 0.1 μm to about 0.3 μm thick) and the dielectric layer 15 is relatively thick (about 1.0 μm or greater).

[0023] The methods described herein for fabricating SOI structures are exemplary methods, and other methods may be used without departing from the scope of this disclosure.

[0024] Referring to FIG. 5, a method 100 of the present disclosure is illustrated. The method of the present disclosure may be described herein with reference to a silicon-on-insulator structure, although in some embodiments, other semiconductor structures may be processed by the disclosed method. In a first step 110, the silicon-on-insulator structure 101 is immersed in a stripping bath to remove oxide (e.g., SiO) from the top surface of the silicon-on-insulator structure 101, producing a stripped silicon-on-insulator structure 112. The stripping bath includes hydrofluoric acid and a surfactant. In some embodiments, the surfactant is a non-ionic surfactant. In some embodiments, the non-ionic surfactant includes an ether group. In some embodiments, the ether-based surfactant is a polyoxyalkylene alkyl ether. Commercially available ether-based surfactants include TRITON® X-series (Dow Chemical Company, Midland, Michigan) and NCW1001 and NCW1002 (Wako Chemicals USA, Richmond, Virginia).

[0025] In some embodiments, a megasonic acoustic field may be applied to the various cleaning baths described herein during stripping or cleaning of semiconductor substrates. Typical frequencies for megasonic cleaning may range from 750 kHz to about 1.5 MHz. Megasonic cleaning induces cavitation, which promotes particle removal from the surface of the substrate. In other embodiments, a megasonic acoustic field is not applied during the various stripping and cleaning processes described herein.

[0026] The amount of surfactant in the stripping bath may be any effective amount that enables the stripping bath to function as described herein. In some embodiments, the amount of surfactant is at least 0.01 wt. %, or, as in other embodiments, at least about 0.025 wt. %, or at least 0.05 wt. %, or 0.01 wt. % to about 0.1 wt. %, or 0.025 wt. % to 0.075 wt. The ratio of deionized water to hydrofluoric acid (HF) (v:v) may be less than 100:1, less than 50:1, less than 25:1, at least 1:1, at least 5:1, 1:1 to 100:1, or 1:1 to 25:1. The time the silicon-on-insulator structure is immersed in the stripping bath may be at least 5 minutes, at least 10 minutes, 5 minutes to about 60 minutes, or about 5 minutes to about 30 minutes. In some embodiments, the stripping bath does not contain acetic acid.

[0027] The stripping bath (and additional baths mentioned below) may be held by any suitable container, such as a container that is part of a wet soak station apparatus. An example of such a system is the GAMA Automated Wet Station available from Naura-Akrion, Inc. (Allentown, Pennsylvania), which may include multiple containers for immersing structures in different baths. Multiple semiconductor structures (e.g., at least 5, 10, 25, or 50 or more) can be loaded into a wafer carrier (or "cassette" or "boat"), and one or more carriers can be immersed in a bath held within a container. Components used to secure the structures in the baths are typically high-purity components such as PTFE, quartz, coated aluminum, or stainless steel. Commercially available cleaning equipment is available from Echo Giken Co., LTD. (Tokyo, Japan) and Akrion Systems LLC (Allentown, Pennsylvania). In other embodiments, the structures may be immersed in the baths in a "cassette-less" system.

[0028] According to embodiments of the present disclosure, "immersing" the silicon-on-insulator structure in a stripping bath or other baths described below involves completely immersing the silicon-on-insulator structure in the bath. Generally, and according to embodiments of the present disclosure, the substrate is not rotated during cleaning in such immersion steps.

[0029] In a second step 120 of the method, the exfoliated silicon-on-insulator structure 111 is immersed in an ozone bath to produce an ozone-treated silicon-on-insulator structure 121. The ozone bath includes ozone (O). In some embodiments, the concentration of ozone in the ozone bath is at least 5 ppm, or at least 10 ppm, or at least 20 ppm, or between 5 ppm and 40 ppm. The exfoliated silicon-on-insulator structure 111 may be immersed in the ozone bath for at least 1 minute, at least 5 minutes, or at least 10 minutes (e.g., between 1 and 30 minutes, or between 5 and about 20 minutes).

[0030] In a third step 130, the ozone-treated silicon-on-insulator structure 121 is immersed in an SC-1 bath to produce an SC-1-treated silicon-on-insulator structure 131. An "SC-1" bath is an aqueous cleaning bath known to those skilled in the art and is sometimes referred to as a "Standard Clean-1" or "RCA-1" bath.

[0031] The SC-1 bath includes ammonium hydroxide (NH4OH) and hydrogen peroxide (HO2). The amount of ammonium hydroxide in the SC-1 bath may be at least 0.1 wt%, at least 0.5 wt%, or at least 1.0 wt% (e.g., 0.1 wt% to 5 wt%, or 1 wt% to 3 wt%). The amount of hydrogen peroxide in the SC-1 bath may be at least 0.5 wt%, at least 1 wt%, at least 2 wt%, 0.5 wt% to 10 wt%, or 2 wt% to about 5 wt%.

[0032] In another embodiment of the method, as shown in FIG. 6, after immersion in the SC-1 bath, the SC-1-treated silicon-on-insulator structure 131 is immersed in an SC-2 bath to form an SC-2-treated silicon-on-insulator structure 141. An "SC-2" bath is an aqueous cleaning bath known to those skilled in the art and is sometimes referred to as a "Standard Clean-2" or "RCA-2" bath. The SC-2 bath contains hydrochloric acid (HCl). In some embodiments, the SC-2 bath contains at least 0.01 wt. % hydrochloric acid, at least 0.1 wt. % hydrochloric acid, at least 0.25 wt. % hydrochloric acid, 0.01 wt. % to 5 wt. % hydrochloric acid, or 0.1 wt. % to 5 wt. % hydrochloric acid. The silicon-on-insulator structure may be immersed in the SC-2 bath for at least 5 minutes, at least 7.5 minutes, or 5 to 20 minutes.

[0033] Another embodiment of a method for stripping and cleaning the surface of a silicon-on-insulator structure is shown in FIG. 7. The stripped silicon-on-insulator structure 111 (i.e., the structure after immersion in the stripping bath in step 110) is rinsed in a rinsing step 115 by contacting the structure with deionized water (DIW), such as by immersion in DIW. In a second rinsing step 135, the SC-1 treated silicon-on-insulator structure 131 is rinsed with DIW. The SC-2 treated structure 141 may undergo a third rinsing step 150, such as by contacting (e.g., immersing) the structure 141 with DIW. The rinsed silicon-on-insulator structure may be dried in a drying step 160. For example, the structure may be dried in an isopropyl alcohol vapor (IPA) dryer (Marangoni drying).

[0034] The various baths described herein may be at room temperature (about 25° C.). In other embodiments, heated baths are used (e.g., at least 30° C., at least 40° C., at least 60° C., 30° C. to 95° C., or 30° C. to 80° C.).

[0035] The methods for stripping and cleaning the surface of a silicon-on-insulator structure described above and shown in Figures 5 to 7 are exemplary and may include additional steps, the order of various steps may be changed, or one or more steps may be omitted.

[0036] Compared to conventional methods for removing oxide from silicon-on-insulator structures, the disclosed method offers several advantages. Without being bound by theory, it is believed that the surfactant used during oxide stripping creates nano-sized defects on the surface of the silicon-on-insulator structure. The nano-sized defects may be surfactants or contaminants bound to the surfactants. Because of their nano-sized size, the defects are undetectable by conventional wafer inspection tools (e.g., a KLA-Tencor Surfscan SPx Wafer Surface Analysis System). It is believed that the defects act as an etch mask during subsequent cleaning steps (SC-1 cleaning). Ozone treatment has been found to remove defects prior to the cleaning step and reduce or eliminate raised protrusions from the surface of the SOI structure. [Example]

[0037] The processes of the present disclosure are further illustrated by the following examples, which should not be construed in a limiting sense.

[0038] Example 1 Raised protrusions on the SOI surface by conventional methods A 200 mm SOI structure was fabricated using the method described herein. The SOI structure was annealed to form an oxide (SiO2) on the top surface of the silicon device layer of the SOI structure. The structure was immersed in an HF bath with surfactant, rinsed with DIW, and then immersed in an SC-1 bath. Figure 8 is a reproduction of an AFM image of the SOI structure, showing nanoscale raised protrusions on the structure surface. Figure 9 is an AFM graph showing the height of the raised protrusions. When a 200 mm SOI structure with an oxide (SiO2) on the top surface of the silicon device layer of the SOI structure was immersed in an ozone bath before SC-1 cleaning, the AFM image showed that the defects were removed.

[0039] As used herein, the terms "about," "substantially," "essentially," and "approximately," when used in conjunction with a dimension, concentration, temperature, or other physical or chemical property or range of properties, are meant to cover variations that may exist at the upper and / or lower limits of the property or range of properties, including, for example, variations due to rounding, measurement method, or other statistical variations.

[0040] When introducing elements of the disclosure or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that additional elements may be present other than the listed elements. The use of specific directional terms (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require a particular orientation of the items being described.

[0041] Since various changes may be made in the above structures and methods without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense. [Explanation of symbols]

[0042] 10...Handle structure 12...Donor wafer 15...Dielectric layer 17 … Cleavage plane 18 … Bonding interface 20... Bonded wafer structure 22…Front 25... Silicon top layer 30...Donor structure 31 … SOI Structure

Claims

1. immersing the silicon-on-insulator structure in a stripping bath containing hydrofluoric acid and a surfactant to strip the oxide film from the surface of the silicon-on-insulator structure, thereby producing a stripped silicon-on-insulator structure; immersing the peeled silicon-on-insulator structure in an ozone bath containing ozone to produce an ozone-treated silicon-on-insulator structure; immersing the ozone treated silicon-on-insulator structure in an SC-1 bath containing ammonium hydroxide and hydrogen peroxide to produce an SC-1 treated silicon-on-insulator structure. Including, a silicon-on-insulator structure comprising a handle structure, a silicon top layer, and a dielectric layer disposed between the handle structure and the silicon top layer; A method for stripping and cleaning the surface of a silicon-on-insulator structure, wherein the silicon-on-insulator structure has an oxide film on the top surface of the silicon-on-insulator structure.

2. 10. The method of claim 1, further comprising immersing the SC-1 treated silicon-on-insulator structure in an SC-2 bath containing hydrochloric acid to form an SC-2 treated silicon-on-insulator structure.

3. 3. The method of claim 2, further comprising the step of rinsing the SC-1 treated silicon-on-insulator structure with water prior to the step of immersing the SC-1 treated silicon-on-insulator structure in an SC-2 bath.

4. 3. The method of claim 2, comprising drying the SC-2 treated silicon-on-insulator structure by contacting the SC-2 treated silicon-on-insulator structure with isopropyl alcohol vapor.

5. 5. The method of claim 4, further comprising the step of rinsing the SC-2 treated silicon-on-insulator structure with water prior to the step of drying the SC-2 treated silicon-on-insulator structure.

6. The method of claim 1 , wherein the stripping bath comprises at least about 0.01% by weight of a surfactant.

7. The method of claim 1 , wherein the surfactant is a non-ionic surfactant.

8. The method according to claim 7, wherein the nonionic surfactant is an ether surfactant containing an ether group.

9. The method of claim 8, wherein the ether surfactant is a polyoxyalkylene alkyl ether.

10. 10. The method of claim 1, wherein the ozone bath comprises at least 20 ppm ozone.

11. 10. The method of claim 1, wherein the exfoliated silicon-on-insulator structure is immersed in an ozone bath for at least 5 minutes.

12. 10. The method of claim 1, wherein the exfoliated silicon-on-insulator structure is immersed in an ozone bath for 5 to 20 minutes.

13. The method of claim 1 , wherein the silicon-on-insulator structure is immersed in a stripping bath for at least 5 minutes.

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