Semiconductor Devices

Abstract

To improve driving capability of a semiconductor device.SOLUTION: A semiconductor device has a first transistor and a second transistor. A first terminal of the first transistor is electrically connected with first wiring, and a second terminal of the first transistor is electrically connected with second wiring. A gate of the second transistor is electrically connected with third wiring, a first terminal of the second transistor is electrically connected with the third wiring line, and a second terminal of the second transistor is electrically connected with a gate of the first transistor. In each of the first transistor and second transistor, a channel region is formed of an oxide semiconductor. An off-current of each of the first transistor and second transistor per channel width of 1 μm is 1aA or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the disclosed invention is semiconductor devices, display devices, liquid crystal display devices, and driving methods thereof. It is related to. [Background technology]

[0002] Semiconductor devices consisting of transistors of only one polarity are being developed. Currently, development of semiconductor devices consisting only of N-channel transistors is underway. (For example, Patent Documents 1 to 3).

[0003] In such a semiconductor device, for example, one of the source and drain is connected to a power supply line. a first transistor having the other of its source and drain connected to the output; and one or more second transistors connected between the gate and each wiring. do.

[0004] In order to make the amplitude voltage of the output signal of the semiconductor device equal to the power supply voltage, the first transistor The potential of the transistor gate is often made higher (or lower) than the power supply voltage by capacitive coupling. To achieve this, the gate of the first transistor must be floating. To this end, one or more second transistors are connected to the gate of the first transistor. All transistors must be turned off. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-328643 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-179479 [Patent Document 3] Japanese Patent Application Laid-Open No. 2004-064528 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology, even when the second transistor is turned off, The charge held by the gate of the first transistor is lost over time due to the off-current of the first transistor. This reduces the driving capability of the semiconductor device.

[0007] In view of the above problems, an object of one embodiment of the present invention is to achieve better operation. Another object of one embodiment of the present invention is to improve the driving capability of a semiconductor device. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the third wiring. a first terminal of the second transistor electrically connected to the third wiring; a second terminal of the second transistor electrically connected to the gate of the first transistor; The first transistor and the second transistor each have a channel region formed of an oxide semiconductor. and the off-state current of the first transistor and the second transistor is 1 aA / μm or less. It is a semiconductor device.

[0009] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, the first terminal of the first transistor being connected to a first wiring; and a second terminal of the first transistor is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the third wiring. The first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the second transistor is , electrically connected to the gate of the first transistor, and the gate of the third transistor is The first terminal of the third transistor is electrically connected to the fourth wiring, and the first terminal of the third transistor is electrically connected to the fifth wiring. the second terminal of the third transistor is electrically connected to the second wiring, and the fourth The gate of the fourth transistor is electrically connected to a fourth wiring. The terminal of the fourth transistor is electrically connected to the fifth wiring, and the second terminal of the fourth transistor is electrically connected to the first wiring. The gates of the first to fourth transistors are electrically connected to the gates of the transistors. In the first to fourth transistors, a channel region is formed using an oxide semiconductor. The semiconductor device has an off-state current of 1 aA / μm or less.

[0010] Another embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the first wiring. The terminal of the second transistor is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the first wiring. and a first terminal of the second transistor is electrically connected to the first wiring. The second terminal of the second transistor is electrically connected to the gate of the first transistor. The first transistor and the second transistor each have a channel region formed of an oxide semiconductor. and the off-state current of the first transistor and the second transistor is 1 aA / μm or less. This is a semiconductor device.

[0011] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, the first terminal of the first transistor being connected to a first wiring; and a second terminal of the first transistor is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the first wiring. A first terminal of the second transistor is electrically connected to the first wiring, and a second terminal of the second transistor is , electrically connected to the gate of the first transistor, and the gate of the third transistor is The first terminal of the third transistor is electrically connected to the third wiring, and the first terminal of the third transistor is electrically connected to the fourth wiring. the second terminal of the third transistor is electrically connected to the second wiring, and the fourth The gate of the first transistor is electrically connected to the third wiring, and the first The terminal of the fourth transistor is electrically connected to the fourth wiring, and the second terminal of the fourth transistor is electrically connected to the first wiring. The gates of the first to fourth transistors are electrically connected to the gates of the transistors. In the first to fourth transistors, a channel region is formed using an oxide semiconductor. The semiconductor device has an off-state current of 1 aA / μm or less.

[0012] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and N (N is a natural number) ) third transistors and N fourth transistors, and the first transistor The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is The gate of the second transistor is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the first wiring. The first terminal of the second transistor is electrically connected to the first wiring, and the second The second terminal of the transistor is electrically connected to the gate of the first transistor, and N The gates of the third transistors are electrically connected to N third wirings, respectively, and N third wirings are connected to N third wirings. All of the first terminals of the N transistors are electrically connected to the fourth wiring. All of the second terminals of the transistors are electrically connected to the second wiring, and N fourth The gates of the transistors are electrically connected to N third wirings, and N fourth wirings. All of the first terminals of the transistors are electrically connected to the fourth wiring, and N fourth transistors are All of the second terminals of the first transistor are electrically connected to the gate of the second transistor. A first transistor, a second transistor, N third transistors, and N fourth transistors The transistor has a channel region formed of an oxide semiconductor, and includes a first transistor and a second transistor. the off-state currents of the first transistor, the N third transistors, and the N fourth transistors are The semiconductor device has a resistance of 1 aA / μm or less.

[0013] In the above semiconductor device, the oxide semiconductor preferably has a structure including a non-single-crystal region. In the semiconductor device, it is preferable that the oxide semiconductor layer is formed in a direction perpendicular to the surface of the oxide semiconductor. It is preferable to have a non-single crystal region in which the c-axis is oriented.

[0014] Another embodiment of the present invention is an electronic device including the above semiconductor device and an operation switch. .

[0015] For example, in this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, This includes the case where X and Y are directly connected. Here, X and Y are objects (e.g. For example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, and may be applied to any connection relationship shown in drawings or text. This also includes connections other than those shown in the text.

[0016] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, There is a configuration in which one or more electrodes (such as a diode) are connected between X and Y. The expression "electrically connected" is sometimes used to mean the same thing as "connected." "Connected to" includes "functionally connected" and "directly connected." do.

[0017] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation There is a configuration in which one or more circuits (e.g., a memory circuit, a control circuit, etc.) are connected between X and Y. In addition, even if another circuit is inserted between X and Y, the signal output from X may be transmitted to Y. In this case, X and Y are considered to be functionally connected.

[0018] For example, in this specification, Y is formed on X, or Y is formed on X. When explicitly stating that Y is formed directly on top of X, It is not limited to cases where there is no direct contact, that is, when there is another object between X and Y. Here, X and Y represent the object (for example, a device, an element, a circuit, a wiring, an electric pole, terminal, conductive film, layer, etc.

[0019] Thus, for example, it may be explicitly stated that layer Y is formed on (or on) layer X. In this case, layer Y is formed directly on top of layer X, and layer Y is formed directly on top of layer X. Another layer (for example, layer Z) is formed on top of it, and layer Y is formed directly on top of it. The other layer (for example, layer Z) may be a single layer or a multi-layer ( Laminated) may also be used.

[0020] Furthermore, the same applies when it is explicitly stated that Y is formed above X. It is not limited to Y being directly on top of X, and there may be another object between X and Y. For example, if a layer Y is formed above a layer X, In this case, layer Y is formed directly on layer X, and layer Y is formed directly on layer X. Another layer (e.g., layer Z) is formed, and layer Y is formed directly on top of it. The other layer (for example, layer Z) may be a single layer or a multi-layer (laminated layer). ) is also acceptable.

[0021] In addition, Y is formed on X, Y is formed on X, or Y is formed above X. When explicitly stating that "Y is formed diagonally above X," this also includes the case where Y is formed diagonally above X. do.

[0022] The same applies to the case where there is a Y below an X, or a Y below an X.

[0023] For example, in this specification, etc., anything explicitly stated as singular is treated as singular. However, it is not limited to this, and multiple numbers are also possible. In particular, if something is explicitly stated as plural, it is preferable that it be plural. However, it is not limited to this and may be singular.

[0024] For example, in this specification, terms such as "first," "second," and "third" refer to various elements, members, and regions. , layer, or area to describe it separately from the others. Thus, the first, second, third The terms "and" and "are" do not limit the number of elements, members, regions, layers, areas, etc. For example, "first" can be replaced with "second" or "third", etc.

[0025] For example, in this specification, "above," "upward," "under," "below," "sideways," etc. "to the right," "to the left," "diagonally," "to the back," "to the front," "inside," "outside," or Spatial location words such as "in" indicate the relationship between one element or feature and another. It is often used to simply show a series of events in a diagram. These spatial orientation terms can include directions in addition to those depicted in the diagram. For example, if it is explicitly stated that Y is above X, it is limited to Y being above X. The device in the diagram can be flipped or rotated 180 degrees so that Y is below X. Thus, the phrase "on" can include the direction of "on." In addition to the above, the direction of "under" can be included. However, it is not limited to this, and the data in the figure Since the vise can be rotated in various directions, the phrase "on" can be used to refer to "on" and In addition to the "down" and "sideways", "right", "left", "diagonally", "backwards", and "hands" directions, Other directions such as "in front of," "into," "outside," or "into" may be included. This means that it can be interpreted appropriately depending on the situation.

[0026] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0027] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current. [Effects of the Invention]

[0028] According to one embodiment of the present invention, better operation can be achieved or the driving capability of a semiconductor device can be improved. It is possible to improve one's strength. [Brief explanation of the drawings]

[0029] [Figure 1]1A to 1C are an example of a circuit diagram of a semiconductor device according to a first embodiment and an example of a schematic diagram for explaining the operation of the semiconductor device. [Figure 2] FIG. 2 is an example of a schematic diagram for explaining the operation of the semiconductor device in the first embodiment. [Figure 3] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 4] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 5] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart for explaining the operation of the semiconductor device. [Figure 6] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 7] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 11] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 12] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 13] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 14] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 15] 10A to 10C are examples of diagrams illustrating a manufacturing process of a semiconductor device in Embodiment 5. [Figure 16] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 18] FIG. 20 is an example of a block diagram of a display device according to a sixth embodiment. [Figure 19]FIG. 20 is an example of a block diagram of a display device according to a sixth embodiment. [Figure 20] 13A and 13B are an example of a circuit diagram of a pixel according to Embodiment 7 and an example of a cross-sectional view of the pixel. [Figure 21] FIG. 20 is an example of a cross-sectional view of a pixel according to a seventh embodiment. [Figure 22] 13 is an example of a timing chart illustrating the operation of the pixel according to the seventh embodiment. [Figure 23] FIG. 13 is an example of a diagram illustrating a semiconductor device according to a fifth embodiment. [Figure 24] FIG. 13 is an example of a diagram illustrating a semiconductor device according to a fifth embodiment. [Figure 25] FIG. 13 is an example of a diagram illustrating a semiconductor device according to a fifth embodiment. [Figure 26] FIG. 13 is an example of a diagram illustrating a semiconductor device according to a fifth embodiment. [Figure 27] FIG. 19 is an example of a diagram illustrating an electronic device according to an eighth embodiment. [Figure 28] FIG. 19 is an example of a diagram illustrating an electronic device according to an eighth embodiment. [Figure 29] 10A to 10C are examples of diagrams illustrating a manufacturing process of a semiconductor device in Embodiment 9. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications can be made to the embodiments. It should not be construed as being limited to the contents of the description. In the drawings, parts or parts having similar functions are indicated by the same reference numerals, and the same parts or parts having similar functions are indicated by the same reference numerals. A detailed description of parts having similar functions will be omitted.

[0031] The contents (or even a part of the contents) described in one embodiment may be used in one or more The contents (including the contents of the embodiment and other embodiments) described in the embodiment (including the contents of the embodiment and other embodiments) The following may be applied, combined, or substituted for the above:

[0032] (Embodiment 1) In this embodiment, an example of a semiconductor device and an example of a method for driving the semiconductor device will be described. In particular, an example of a circuit using a bootstrap operation and an example of a method for driving the circuit will be described. We will explain about this.

[0033] First, an example of the configuration of the semiconductor device according to this embodiment will be described.

[0034] FIG. 1A illustrates an example of a semiconductor device according to this embodiment. The semiconductor device illustrated in FIG. , a transistor 101 and a transistor 102. The first terminal of the transistor 101 The first terminal of the transistor 101 is connected to a wiring 111, and the second terminal of the transistor 101 is connected to a wiring 112. The first terminal of the transistor 102 is connected to the wiring 113. The second terminal of the transistor 101 is connected to the gate of the transistor 102. is connected to the wiring 113. Note that the semiconductor device of this embodiment mode is The configuration is not limited to this, and various other configurations are possible.

[0035] The connection point between the gate of the transistor 101 and the second terminal of the transistor 102 is , denoted as node 11.

[0036] Note that the case where the transistors 101 and 102 are N-channel transistors will be described. In an N-channel transistor, the potential difference between the gate and source is greater than the threshold voltage. is also greater than .

[0037] The semiconductor layer of the transistor constituting the semiconductor device of this embodiment is formed of an oxide semiconductor. By using an oxide semiconductor as the semiconductor layer, Improving the S value of the transistor, reducing the off-state current of the transistor, and / or increasing the breakdown voltage of the transistor Improvements can be made.

[0038] In this specification, the terms "active elements" and "passive elements" are used interchangeably. Even if you do not specify the location where all terminals of the capacitor, resistor, etc. are connected, In particular, a person skilled in the art may be able to compose an embodiment of the invention. If there are multiple cases where the terminal is connected to a specific point, Therefore, it is not necessary to limit it to active elements (transistors, diodes, etc.), passive elements. Only some of the terminals of elements (capacitance elements, resistance elements, etc.) are connected to those terminals. By specifying the location where the invention is to be implemented, it may be possible to configure an aspect of the invention.

[0039] In this specification, the term "circuit" refers to a circuit that is connected to at least a terminal. A person skilled in the art may be able to identify the invention by specifying the circuit. A person skilled in the art can identify the invention by at least specifying the function. Therefore, even if the function of a circuit is not specified, the If a specific part is specified, it is disclosed as one aspect of the invention and constitutes one aspect of the invention. Or, for a circuit, it is possible to specify the terminal and the connection point without specifying the terminal. However, if the function is specified, it is disclosed as one aspect of the invention and is not an aspect of the invention. It is possible to configure the following.

[0040] Next, an example of a potential applied to each wiring will be described.

[0041] A potential V1 is applied to the wiring 111. In other words, a constant voltage ( For example, a voltage V1 is supplied to the wiring 111. Alternatively, a potential V1 and a potential V2 (potential V In other words, the wiring 111 is provided with a signal When a potential V1 is applied to the wiring 111, The wiring 111 functions as a power supply line. On the other hand, the wiring 111 is supplied with a potential V1 or a potential V2. When the signal is selectively applied, the wiring 111 functions as a signal line (for example, a clock signal line). However, the potential applied to the wiring 111 is not limited to the potential V1 and the potential V2. can also be given various potentials.

[0042] Furthermore, a signal is output from the wiring 112. Therefore, the wiring 112 functions as a signal line. Note that the potential of the wiring 112 is, for example, higher than or equal to V2 and lower than or equal to V1.

[0043] The wiring 113 is selectively supplied with a potential V1 or a potential V2 (potential V2<potential V1). In other words, a signal is input to the wiring 113. Therefore, the wiring 113 is However, the potential applied to the wiring 113 is a potential V1 and a potential V For example, a constant voltage can be supplied to the wiring 113. As another example, the wiring 113 may be connected to an analog signal or a signal having three or more potentials. It is possible to input

[0044] When potential A is applied to a node, wiring, electrode, or terminal, these potentials are This explanation will be given assuming that it is equal to

[0045] In this specification, expressions such as "equal" or "same" indicate differences within the margin of error. For example, when we say "the potential (or voltage) is equal," The error may be within a range of at least ±10%, and more preferably ±5%. More preferably, it is ±3%. Alternatively, the range of potential fluctuation due to leakage current, etc. Range of potential fluctuation due to feedthrough, etc., range of potential fluctuation due to noise, etc., measuring equipment The range of measurement error due to factors such as process variations, etc. , is included within the margin of error.

[0046] Next, an example of the operation of the semiconductor device of this embodiment will be described. When the potential V1 is applied to the wiring 111, and when the potential V1 and the potential V2 are selectively applied to the wiring 111, Two types of operation will be explained below.

[0047] An example of the operation of the semiconductor device of this embodiment when a potential V1 is applied to the wiring 111 will be described below. I will explain.

[0048] Assume that the initial value of the potential of the node 11 and the initial value of the potential of the wiring 112 are equal to the potential V2. When a potential V1 is applied to the wiring 113, the transistor 102 is turned on. The wiring 113 and the node 11 are electrically connected. Then, the potential of the wiring 113 is supplied to the node 11. Therefore, the potential of node 11 begins to rise. Eventually, when the potential of node 11 reaches V2 + Vt h101 (Vth101 is the threshold voltage of transistor 101), transistor 1 01 turns on, so wiring 111 and wiring 112 become conductive. Then, since the potential of wiring 11 1 is supplied to wiring 112, the potential of wiring 112 begins to rise (see Fig. 1(B) for reference).

[0049] After that, when the potential of node 11 reaches V1 - Vth102 (Vth102 is the threshold voltage of transistor 102: V2 + Vth101 < V1 - Vth102 is satisfied), transistor 102 turns off, so wiring 113 and node 11 become non-conductive. Then, node 11 becomes a floating state. After that, the potential of wiring 112 continues to rise and eventually rises to a value equal to potential V 1. As the potential of wiring 112 rises, the potential of node 11 reaches V1 + Vth101 + Va (Va is a positive number) due to the parasitic capacitance between the gate of transistor 101 and the second terminal (see Fig. 1(C)). This is the so-called bootstrap operation.

[0050] When potential V2 is applied to wiring 113, transistor 102 turns off, so wiring 113 and node 11 become non-conductive. That is, node 11 becomes a floating state. In this case, the operation of the semiconductor device shown in Fig. 1(A) depends on the potential of node 11 before potential V2 is applied to wiring 113. For example, assume that the potential of node 11 before potential V2 is applied to wiring 113 is less than V2 + Vth101. When potential V2 is applied to wiring 113 in this state is applied, transistor 101 turns off, so wiring 111 and wiring 112 become non-conductive ​Therefore, the potential of the wiring 112 remains at the value before the potential V2 is applied to the wiring 113. For example, the potential of the node 11 before the potential V2 is applied to the wiring 113 is V2+V In this state, when a potential V2 is applied to the wiring 113, Since the transistor 101 is turned on, the wiring 111 and the wiring 112 are in a conductive state. Therefore, the potential of the wiring 112 becomes equal to the potential V1, and the potential of the node 11 becomes equal to the potential V2. The wrap operation results in V1 + Vth101 + Va.

[0051] In the semiconductor device of this embodiment, when the potential V1 and the potential V2 are selectively applied to the wiring 111, An example of the operation will be described.

[0052] Assume that the initial value of the potential of the node 11 and the initial value of the potential of the wiring 112 are equal to the potential V2. When a potential V1 is applied to the wiring 113 and a potential V2 is applied to the wiring 111, the transistor Since the starter 102 is turned on, the wiring 113 and the node 11 are brought into a conductive state. The potential of line 113 is supplied to node 11, so the potential of node 11 begins to rise. When the potential of the node 11 reaches V2+Vth101, the transistor 101 turns on. Therefore, the wiring 111 and the wiring 112 are electrically connected. Since the potential is supplied to the line 112, the potential of the line 112 becomes equal to the potential V2 (see FIG. 2(A)). (see).

[0053] Thereafter, when the potential of the node 11 reaches V1-Vth102, the transistor 102 turns on. Therefore, the wiring 113 and the node 11 are not electrically connected to each other. It becomes floating (see Figure 2(B)).

[0054] After that, a potential V1 is applied to the wiring 111. At this time, the node 11 remains in a floating state. Therefore, the potential of the node 11 remains at V1-Vth102. The starter 101 remains on, and the wiring 111 and the wiring 112 remain in a conductive state. That is, the potential of the wiring 111 continues to be supplied to the wiring 112. At the same time that 1 is given, the potential of the wiring 112 starts to rise, and the potential V As the potential of the wiring 112 rises, the potential of the node 11 rises to a value equal to 1. Due to the parasitic capacitance between the gate and the second terminal of transistor 101, V1 + Vth101 + Va (Va is a positive number) (see Figure 2(C)). This is called bootstrap operation. be.

[0055] Note that when a potential V2 is applied to the wiring 113, the transistor 102 is turned off. There is no electrical continuity between the wiring 113 and the node 11. That is, the node 11 is in a floating state. In this case, the operation of the semiconductor device illustrated in FIG. 2A is the same as that before the potential V2 is applied to the wiring 113. It depends on the potential of the node 11. For example, In this state, the potential V2 is applied to the wiring 113. When the transistor 101 is turned off, the wiring 111 and the wiring 112 are not electrically connected. Therefore, the potential of the wiring 112 remains at the value before the potential V2 is applied to the wiring 113. In addition, for example, if the potential of the node 11 before the potential V2 is applied to the wiring 113 is V2+ In this state, when a potential V2 is applied to the wiring 113, Since the transistor 101 is turned on, the wiring 111 and the wiring 112 are in a conductive state. Therefore, the potential of the wiring 112 becomes equal to the potential of the wiring 111. When V1 is applied, the potential of the wiring 112 becomes equal to the potential V1, and the potential V2 is applied to the wiring 111. is applied, the potential of the wiring 112 becomes equal to the potential V2.

[0056] As described above, in the semiconductor device of this embodiment, by using the bootstrap operation, Therefore, the potential of the wiring 112 can be set to be equal to the potential of the wiring 111 .

[0057] In addition, in the conventional technology, the S value of the transistor is large. The time from when the potential V1 is applied to the output of the transistor 102 until the transistor 102 is turned off is longer. Or, the timing when the potential of the node 11 starts to rise due to the bootstrap operation Or the potential of node 11 is low. Or the transistor The potential difference between the gate of the wiring 101 and the second terminal is small. The rise time of the potential has become longer. Or, the load that can be connected to the wiring 112 is small. Alternatively, the channel width of the transistor 101 is increased. The area had become larger.

[0058] In contrast to this, in the semiconductor device of this embodiment, the semiconductor of the transistor constituting the semiconductor device is Since an oxide semiconductor is used as the dielectric layer, the S value can be reduced. For example, the S value of the transistor 102 is small, and therefore the driving capability of the device can be improved. In other words, the time from when the potential V1 is applied to the wiring 113 until the transistor 102 is turned off is Since the time between the first and second transistors can be shortened, the potential of node 11 rises due to the bootstrap operation. The timing at which the potential of node 11 starts to rise can be advanced. If the voltage at node 11 is increased, the voltage at node 11 can be increased. As a result, the potential difference between the first terminal and the second terminal of the wiring 112 can be increased. Alternatively, when a large load is connected to the wiring 112, the rise time of the Alternatively, the channel width of the transistor 101 can be reduced to drive the load. As a result, the layout area can be reduced. If the S value of the transistor 101 is small, the rise time of the potential of the wiring 112 can be shortened. can be done.

[0059] In addition, in conventional technology, the off-state current of the transistor was large. In both cases, the amount of charge lost from node 11 was large. Or, the potential of node 11 decreased. Or, the time during which the potential of the node 11 can be maintained at a value higher than V1+Vth101 is Or it was difficult to lower the drive frequency. The range of drive frequencies over which the device can operate has been narrowed.

[0060] In contrast, in the semiconductor device of this embodiment, the off-state of the transistors constituting the semiconductor device is Therefore, the driving capability of the semiconductor device can be improved. A small off-current of transistor 102 reduces the amount of charge lost from node 11. Therefore, the potential drop of the node 11 can be suppressed. The time that the potential of 1 can be maintained at a value higher than V1+Vth101 can be extended. As a result, the driving frequency can be lowered, and the semiconductor device of this embodiment operates This allows for a wider range of drive frequencies that can be used.

[0061] When the potential V1 and the potential V2 are selectively applied to the wiring 111, the potential of the node 11 is After rising to V1-Vth102, it rises further due to the bootstrap operation. That is, the potential difference between the gate and the second terminal of the transistor 101 can be increased. As a result, the rise time of the potential of the wiring 112 can be shortened. Even if a large load is connected to the wiring 112, the load can be driven. The channel width of the register 101 can be reduced, thereby reducing the layout area. It is possible.

[0062] When the potential V1 or the potential V2 is selectively applied to the wiring 111, the potential V1 is applied to the wiring 113. After the potential V1 is applied to the wiring 111, the potential V2 is applied to the wiring 112. Therefore, the semiconductor device of this embodiment has a shift register circuit. It can be used as part of a road.

[0063] Next, an example of the function of each transistor will be described.

[0064] The transistor 101 has a function of controlling electrical continuity between the wiring 111 and the wiring 112. That is, the transistor 101 functions as a switch. The controller 101 has a function of controlling the timing of supplying the potential of the wiring 111 to the wiring 112. Alternatively, the transistor 101 controls the timing at which the potential of the wiring 112 is increased. Alternatively, the transistor 101 has a function of connecting the gate of the transistor 101 and the second The timing at which the potential of node 11 is increased is controlled by the parasitic capacitance between the terminals. However, the transistor 101 has at least one of the above-described functions. That's fine.

[0065] The transistor 102 has a function of controlling electrical continuity between the wiring 113 and the node 11. That is, the transistor 102 functions as a switch. When the potential of the wiring 113 is higher than the potential of the node 11, the node 102 When the potential of the wiring 113 is lower than the potential of the node 11, The transistor 102 has a function of making the line 113 and the node 11 non-conductive. Alternatively, the transistor 102 functions as a diode. The transistor 1 has a function of controlling the timing of supplying the potential to the node 11. Node 11 has a function of controlling the timing of increasing the potential of node 11. The transistor 102 has a function of controlling the timing at which the node 11 is brought into a floating state. However, it is sufficient that the transistor 102 has at least one of the above-described functions.

[0066] Next, an example of a potential applied to each wiring will be described. By controlling the temperature, the semiconductor device of this embodiment can be given various functions, or This can improve the driving performance of the body device.

[0067] For example, when the potential V1 or the potential V2 is selectively applied to the wiring 113, It is possible to apply a potential higher than the potential V1 or a potential lower than the potential V1 to the wiring 11. By applying a potential higher than or lower than the potential V1 to 111, The semiconductor device having this configuration can function as a level shift circuit.

[0068] When a potential higher than the potential V1 is applied to the wiring 111, the potential applied to the wiring 111 is It is preferably higher than 1 time and not higher than 4 times the potential V1. More preferably, it is 1.2 times or higher. The ratio is preferably from 1.5 to 2.3 times.

[0069] Note that when a potential lower than the potential V1 is applied to the wiring 111, the potential applied to the wiring 111 is It is preferably 0.2 times or more and less than 1 times V1, more preferably 0.3 times or more, It is 0.9 times or less, and more preferably 0.5 times or more and 0.7 times or less.

[0070] For example, when the potential V1 is applied to the wiring 111, the potential V1 is applied to the wiring 113. Specifically, the potential applied to the wiring 113 is The potential is preferably higher than one time and lower than or equal to three times the potential applied to the wiring 111. Preferably, it is 1.3 times or more and 2.5 times or less. More preferably, it is 1.5 times or more and 2 times or less. When the potential applied to the wiring 113 is high, the potential V1 is applied to the wiring 113. This reduces the time it takes for transistor 102 to turn off after node 1 The timing at which the voltage of 1 starts to rise due to bootstrap operation can be accelerated. If the timing at which the potential of the node 11 starts to rise is too early, the potential of the node 11 can be increased. Therefore, the potential difference between the gate and the second terminal of the transistor 101 can be increased. As a result, the rise time of the potential of the wiring 112 can be shortened. Alternatively, even if a large load is connected to the wiring 112, the load can be driven. Since the channel width of the transistor 101 can be reduced, the layout area can be reduced. It can be reduced.

[0071] Next, an example of the threshold voltage of each transistor will be described. By setting the value appropriately, the driving capability of the semiconductor device can be improved.

[0072] For example, it is preferable that the threshold voltage of the transistor 102 is as small as possible. The threshold voltage of the transistor 102 is preferably smaller than the threshold voltage of the transistor 101 . Preferably, the threshold voltage of transistor 102 is 0.1 times the threshold voltage of transistor 101. The ratio is preferably 0.3 times or more and less than 1 time. More preferably, the ratio is 0.3 times or more and less than 0.9 times. Preferably, the ratio is 0.5 to 0.7. In other words, the time from when the potential V1 is applied to the wiring 113 until the transistor 102 is turned off is Since the time between the first and second transistors can be shortened, the potential of node 11 rises due to the bootstrap operation. The timing at which the potential of node 11 starts to rise can be advanced. If the potential of the node 11 is high, the gate of the transistor 101 As a result, the potential difference between the first terminal and the second terminal of the wiring 112 can be increased. The rise time can be shortened. Alternatively, the channel width of the transistor 101 can be reduced. Therefore, the layout area can be reduced.

[0073] Furthermore, for example, the threshold voltage of the transistor 101 is determined by the driving voltage of the semiconductor device (for example, the potential V 1 - potential V2). In particular, the threshold voltage of the transistor 101 is It is preferable that the voltage is 1 / 50 or more and 1 / 2 or less of the driving voltage of the semiconductor device. Preferably, it is 1 / 40 or more and 1 / 7 or less. More preferably, it is 1 / 30 or more and 1 / 8 or less. The threshold voltage of the transistor 101 is set to be lower than the driving voltage of the semiconductor device. By reducing the power consumption, it is possible to prevent malfunction of the semiconductor device and ensure that the semiconductor device operates normally. Cut.

[0074] Next, an example of the size of each transistor will be described. By setting the value to such a value, the driving capability of the semiconductor device of this embodiment can be improved. .

[0075] For example, the channel width of transistor 101 is larger than the channel width of transistor 102. Preferably, the channel width of the transistor 101 is larger than that of the transistor 102. The channel width of the optical fiber 102 is 2 times or more and 100 times or less. More preferably, the channel width is 5 times or more and 50 times or less. More preferably, it is 10 times or more and 30 times or less.

[0076] The current supply capacity can be controlled by the channel width (W) of the transistor. Specifically, the larger the channel width of a transistor, the greater the current supply capability of the transistor. However, the factor that controls the current supply capacity of the transistor is the For example, the channel length (L) of a transistor, the W / The L ratio, the potential difference between the gate and source of the transistor (Vgs), etc. Specifically, the current supply capacity of the transistor can be controlled by adjusting the channel length of the transistor. The smaller the value, the larger the W / L ratio of the transistor, or the larger the Vgs of the transistor. Therefore, in this specification and the like, The statement "the transistor has a large channel width" should be interpreted as "the transistor has a small channel length." "Large W / L ratio of transistor" or "Large Vgs of transistor" It should be noted that this is correct.

[0077] Next, a semiconductor device having a different structure from the semiconductor device shown in FIG. 1A will be described.

[0078] For example, in the semiconductor device illustrated in FIG. 1A, the gate and / or The wiring to which the first terminal is connected is not limited to the wiring 113, and various other wirings may be used. It is possible.

[0079] FIG. 3A shows the semiconductor device shown in FIG. 1A in which the gate of the transistor 102 is disposed. In the semiconductor device shown in FIG. 3A, the wiring 113 is connected to the wiring 111. When potential V2 is applied, the potential of node 11 can be set to a value equal to potential V2. .

[0080] FIG. 3B shows the first terminal of the transistor 102 in the semiconductor device shown in FIG. 3B is connected to the wiring 111. A potential V1 can be supplied to the wiring 111 having a lower wiring resistance than the wiring 113. Therefore, the potential of the node 11 can be increased quickly.

[0081] FIG. 3C shows the semiconductor device shown in FIG. 1A in which the gate of the transistor 102 is arranged. When the first terminal of the transistor 102 is connected to the wiring 111, In the semiconductor device shown in FIG. 3C, the wiring 113 can be omitted. The number of wires and signals can be reduced.

[0082] In addition, for example, in the semiconductor device shown in FIG. 1(A) and FIGS. 3(A) to 3(C), the node 1 By increasing the capacitance between the line 112 and the line 112, This allows the potential of the node 11 to be increased.

[0083] Specifically, for example, in the semiconductor device shown in FIG. 1(A) and FIG. 3(A) to (C), A capacitor element can be connected between the node 11 and the wiring 112. One electrode of the transistor 101 is made of the same material as the gate of the transistor 101, and the other electrode of the transistor 101 is connected to the node 11. The other electrode of the capacitor 121 is preferably connected to the It is preferable that the second terminal of the first electrode be made of the same material as the second terminal of the first electrode and be connected to the wiring 112. In this way, contact holes and the like can be omitted, making it possible to reduce the layout area. Cut.

[0084] Alternatively, for example, in the semiconductor device shown in FIG. 1(A) and FIG. 3(A) to (C), The material that constitutes the gate of transistor 101 and the material that constitutes the second terminal of transistor 101 The area where the material that forms the gate of transistor 101 overlaps with the material that forms the gate of transistor 102 is It is possible to make the area larger than the area where the material constituting the first terminal of O1 overlaps with the material constituting the first terminal of O1. The material that forms the gate of the transistor 101 and the second terminal of the transistor 101 are The area where the materials that make up the gate of the transistor 101 and the material that makes up the transistor overlap is The area is greater than 1 time and less than 5 times the area of ​​the material that forms the first terminal of the resistor 101. It is more preferable that the ratio is 1.5 times or more and 4 times or less. is more than two times and less than three times.

[0085] FIG. 3D shows the gate and the gate of the transistor 101 in the semiconductor device shown in FIG. 1 shows an example in which a capacitor 121 is connected between the terminals of the first and second capacitors.

[0086] In addition, for example, in the semiconductor device shown in FIGS. 3A to 3D, The first terminal of the transistor 101 and the gate or the first terminal of the transistor 102 are connected to different wirings. It is possible.

[0087] FIG. 4A shows the first terminal of the transistor 101 in the semiconductor device shown in FIG. When the gate of the transistor 101 is connected to the wiring 111A and the gate of the transistor 102 is connected to the wiring 111B, An example of this case is shown below.

[0088] FIG. 4B shows the first terminal of the transistor 101 in the semiconductor device shown in FIG. The first terminal of the transistor 102 is connected to the wiring 111A, and the second terminal of the transistor 102 is connected to the wiring 111B. An example of this is shown below.

[0089] FIG. 4C shows the first terminal of the transistor 101 in the semiconductor device shown in FIG. The gate of the transistor 101 is connected to the wiring 111A, the gate of the transistor 102 is connected to the wiring 111B, and the An example is shown in which the first terminal of the transistor 102 is connected to the wiring 111B.

[0090] The wiring 111A and the wiring 111B have the same function as the wiring 111. A potential V1 is supplied to the wiring 111A and the wiring 111B. The potentials applied to the wiring 111A and 111B can be different from each other. 4(A) to 4(C) by applying a potential higher than the potential V1 or a potential lower than the potential V1. The semiconductor device shown in C) functions as a level shift circuit. In addition, by applying a potential higher than the potential V1 to the wiring 111B, the potential of the node 11 As another example, when a potential higher than the potential V1 is applied to the wiring 111B, the rise time can be shortened. By applying a low potential, the timing at which the transistor 102 is turned off can be accelerated. This can be done.

[0091] In this specification and the like, an example of a transistor is a multi-layer transistor having two or more gate electrodes. A multi-gate transistor can be used. Since the multiple channel regions corresponding to the gate electrodes are connected in series, multiple transistors can be used. Therefore, the multi-gate structure allows for further off-state It is possible to reduce the current and improve the breakdown voltage of the transistor (improving reliability). The multi-gate structure allows the drain and source to be connected together when the transistor operates in the saturation region. Even if the voltage between the drain and source changes, the current between the drain and source does not change much, and the slope is flat. A voltage-current characteristic with a flat slope can be obtained. Using this, it is possible to realize an ideal current source circuit or an active load with a very high resistance. As a result, it is possible to realize differential circuits and current mirror circuits with good characteristics. do.

[0092] An example of a transistor is a structure in which gate electrodes are arranged above and below a channel. The structure in which gate electrodes are arranged above and below the channel can be applied to the transistor. By doing so, the circuit configuration becomes like multiple transistors connected in parallel. As a result, the channel area increases, and the current value can be increased. The structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0093] An example of a transistor is a transistor having a structure in which a gate electrode is disposed above a channel region. structure in which the gate electrode is located below the channel region, normal stagger structure, inverted stagger structure , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in parallel. A transistor having a structure in which channel regions are connected in series can be used.

[0094] An example of a transistor is a transistor in which a source electrode and a drain electrode are formed in a channel region (or a part thereof). A transistor with an overlapping gate electrode can be used. By making the structure such that the source electrode and drain electrode overlap the channel This can prevent charges from accumulating in a part of the region, causing unstable operation.

[0095] In this specification, etc., in a drawing or text that describes one embodiment, However, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore, When a figure or text describing a part is provided, the figure or text of that part can be extracted, and the content thus extracted is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitor elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described in singular or plural, it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transitors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to

[0096] constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer and M < N) elements to constitute an aspect of the invention. In addition, in this specification, etc., when at least one specific example is describedThe invention is also disclosed as an aspect of the invention and may constitute an aspect of the invention. It is Noh.

[0097] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it is not necessarily stated in words. However, the content is disclosed as one aspect of the invention and constitutes one aspect of the invention. Similarly, even if a part of the drawings is taken out, it can be regarded as one embodiment of the invention. This is disclosed as an embodiment of the invention and can be considered as one aspect of the invention.

[0098] (Embodiment 2) In this embodiment, an example of a configuration of a semiconductor device and an example of a method for driving the semiconductor device will be described. In particular, an inverter circuit and a buffer circuit using the semiconductor device described in Embodiment 1 will be described. An example of a circuit and an example of a method for driving the inverter circuit and the buffer circuit will be described. do.

[0099] First, an example of the configuration of the semiconductor device according to this embodiment will be described.

[0100] FIG. 5A shows an example of the configuration of a semiconductor device. The semiconductor device shown in FIG. A transistor 101, a transistor 102, a transistor 103, and a transistor 104 , wiring 112, wiring 113, wiring 114, and wiring 115. The transistors 101 to 104 are formed using an oxide semiconductor material. The transistor 103 and the transistor 104 are N-channel.

[0101] FIG. 5A shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. The gate of the transistor 103 is connected to the wiring 11. The first terminal of the transistor 103 is connected to the wiring 115. The second terminal of the transistor 103 is connected to the wiring 112. The first terminal of the transistor 104 is connected to a wiring 114, and the second terminal of the transistor 104 is connected to a wiring 115. The second terminal of the transistor 104 is connected to the gate of the transistor 101. However, the structure of the semiconductor device of this embodiment mode is not limited to that shown in FIG. 5A and may have various other structures. It is possible to do this.

[0102] Next, an example of a potential applied to each wiring will be described.

[0103] The potential V1 and the potential V2 are selectively applied to the wiring 114. A signal is input to the wiring 114. Therefore, the wiring 114 functions as a signal line. Here, it is assumed that the inverted signal of the signal input to the wiring 113 is input to the wiring 114. Therefore, when a potential V2 is applied to the wiring 113, a potential V1 is applied to the wiring 114. When a potential V1 is applied to the wiring 113, a potential V2 is applied to the wiring 114. However, the present invention is not limited to this, and the same potential may be applied to the wiring 113 and the wiring 114. It is possible.

[0104] A potential V2 is applied to the wiring 115. In other words, a constant voltage ( For example, a voltage V2 is supplied to the wiring 115. Therefore, the wiring 115 functions as a power supply line. However, the potential applied to the wiring 115 is not limited to the potential V2, and various other potentials may be applied. For example, the wiring 115 can be supplied with a potential V1 and a potential V2. By applying a potential V1 to the wiring 115, , a reverse bias can be applied to the transistors 103 and 104. , the shift in the threshold voltage of these transistors can be suppressed.

[0105] Next, an example of the operation of the semiconductor device shown in FIG. When a potential V2 is applied to the wiring 113 and a potential V1 is applied to the wiring 114, Two types of operation will be explained: when V1 is applied to the wiring 114 and when V2 is applied to the wiring 114. do.

[0106] FIG. 5B is a timing chart for explaining the operation of the semiconductor device shown in FIG. 5A. 5B shows an example of the potential of the wiring 113 (potential V113) and the potential of the wiring 114. the potential of the node 11 (potential V114), the potential of the node 11 (potential V11), and the potential of the wiring 112 (potential V114). V112).

[0107] The operation when the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114 will be described below. I will explain.

[0108] When a potential V2 is applied to the wiring 113 and a potential V1 is applied to the wiring 114, the transistor Since 104 is turned on, the wiring 115 and the node 11 are in a conductive state. The transistor 102 is turned off, and the wiring 113 and the node 11 are not electrically connected. Since the potential of the wiring 115 is supplied to the node 11, the potential of the node 11 is V2 Therefore, the transistor 101 is turned off, and the wiring 111 and the wiring 11 At this time, the transistor 103 is turned on, and the wiring 115 and the wiring 2 are in a non-conductive state. The wiring 112 is electrically connected to the wiring 115. Therefore, the potential of the wiring 112 becomes equal to the potential V2 (see FIG. 6A).

[0109] The operation when a potential V1 is applied to the wiring 113 and a potential V2 is applied to the wiring 114 will be described below. I will explain.

[0110] When a potential V1 is applied to the wiring 113 and a potential V2 is applied to the wiring 114, the transistor 104 is turned off, and the wiring 115 and the node 11 are in a non-conductive state. The resistor 102 is turned on, and the wiring 113 and the node 11 are brought into a conductive state. Since the potential of the wiring 113 is supplied to the node 11, the potential of the node 11 starts to rise. Eventually, the potential of the node 11 rises to V2+Vth101. The transistor 101 is turned on, and the wiring 111 and the wiring 112 are brought into a conductive state. Since the resistor 103 is turned off, the wiring 115 and the wiring 112 are not electrically connected. In this way, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is It starts to rise (see Figure 6(B)).

[0111] After that, the potential of the node 11 rises to V1-Vth102. Since the node 102 is turned off, the wiring 113 and the node 11 are not electrically connected. At this time, the potential of the wiring 112 continues to rise. Therefore, the potential of the node 11 is determined by the parasitic capacitance between the gate and the second terminal of the transistor 101. This causes the voltage to rise to V1 + Vth101 + Va. This is the so-called bootstrap operation. Thus, the potential of the wiring 112 rises to a value equal to the potential V1 (see FIG. 6C). .

[0112] As described above, the semiconductor device of this embodiment mode can achieve the following by using the bootstrap operation: The potential of the wiring 112 can be set equal to the potential of the wiring 111 or the potential of the wiring 115. can.

[0113] In addition, in the conventional technology, the S value of the transistor is large. The time it takes for transistor 102 to turn off after V1 is applied has become longer. Or, the timing at which the potential of node 11 starts to rise due to the bootstrap operation is delayed. Alternatively, the potential of the node 11 is low. Alternatively, the potential of the transistor 101 is low. The potential difference between the gate and the second terminal is small. The rise time was long. Or the load that can be connected to the wiring 112 was small. Alternatively, the channel width of the transistor 101 is increased. Alternatively, the fall time of the potential of the wiring 112 becomes longer. Alternatively, the potential V1 is applied to the wiring 114 until the transistor 101 is turned off. Alternatively, the time required for the transistor 101 and the transistor 102 to be transferred from the wiring 111 to the transistor 102 was increased. The current flowed through the wiring 115 via the 103 for a long time. Or, the power consumption increased. there was.

[0114] In contrast to this, in the semiconductor device of this embodiment, the semiconductor of the transistor constituting the semiconductor device is Since an oxide semiconductor is used as the dielectric layer, the S value can be reduced. For example, the S value of the transistor 102 is small, and therefore the driving capability of the device can be improved. In other words, the time from when the potential V1 is applied to the wiring 113 until the transistor 102 is turned off is Since the time between the first and second transistors can be shortened, the potential of node 11 rises due to the bootstrap operation. The timing at which the potential of node 11 starts to rise can be advanced. If the voltage at node 11 is increased, the voltage at node 11 can be increased. As a result, the potential difference between the first terminal and the second terminal of the wiring 112 can be increased. Alternatively, when a large load is connected to the wiring 112, the rise time of the Alternatively, the channel width of the transistor 101 can be reduced to drive the load. As a result, the layout area can be reduced. If the S value of the transistor 101 is small, the rise time of the potential of the wiring 112 can be shortened. As another example, when the S value of the transistor 103 is small, the potential of the wiring 112 can be increased. As another example, the S value of the transistor 104 is small. As a result, the transistor 101 is turned off after the potential V1 is applied to the wiring 114. Therefore, the time required for the wiring 111 to In addition, current flow to the wiring 115 through the transistor 103 can be suppressed. This makes it possible to reduce power consumption.

[0115] In the conventional technology, the off-state current of the transistor is large. The amount of charge leaking from the node 11 was large, or the potential of the node 11 was low, or The time during which the potential of the gate 11 can be maintained at a value higher than V1+Vth101 is shortened. It is also difficult to slow down the driving frequency. The range of possible drive frequencies was narrow.

[0116] In contrast, the off-state current of the transistor included in the semiconductor device of this embodiment is small. Therefore, the driving capability of the semiconductor device can be improved. The transistor 102 and the transistor 104 have small off-state currents, so that the Therefore, the amount of charge leaking from the node 11 can be reduced. That is, the potential of the node 11 can be maintained at a value higher than V1+Vth101. This allows the drive frequency to be lowered. Therefore, it is possible to widen the range of drive frequencies in which the semiconductor device of this embodiment can operate. This can be done.

[0117] The signal output from the wiring 112 is an inverted signal of the signal input to the wiring 114. That is, the semiconductor device of this embodiment mode can function as an inverter circuit. Alternatively, the signal output from the wiring 112 can be the non-inverted signal of the signal input to the wiring 113. That is, the semiconductor device of this embodiment has a function as a buffer circuit. It is possible.

[0118] Next, an example of the function of each transistor will be described.

[0119] The transistor 103 has a function of controlling electrical continuity between the wiring 115 and the wiring 112. That is, the transistor 103 functions as a switch. The switch 103 has a function of controlling the timing at which the potential of the wiring 115 is supplied to the wiring 112. Alternatively, the transistor 103 controls the timing at which the potential of the wiring 112 is decreased. However, the transistor 103 has at least one of the above functions. That's fine.

[0120] The transistor 104 has a function of controlling electrical continuity between the wiring 115 and the node 11. That is, the transistor 104 functions as a switch. The switch 104 has a function of controlling the timing at which the potential of the wiring 115 is supplied to the node 11. Alternatively, the transistor 104 controls the timing at which the potential of the node 11 is decreased. However, the transistor 104 has at least one of the above functions. That's fine.

[0121] Next, variations in the potential applied to each wiring will be described. By appropriately controlling the potential, the semiconductor device of this embodiment mode can be given various functions. Alternatively, the driving capability of the semiconductor device can be improved.

[0122] For example, when the potential V1 and the potential V2 are selectively applied to the wiring 113 or the wiring 114, A potential higher than the potential V1 or lower than the potential V1 may be applied to the wiring 111. As a result, the semiconductor device of this embodiment can function as a level shift circuit. It can have:

[0123] Note that a potential higher than the potential V1 is applied to the wiring 111. It is preferably more than 1 time and not more than 4 times the value of V1. More preferably, it is 1.2 times or more. More preferably, it is 1.5 times or more and 2.3 times or less.

[0124] Note that a potential lower than the potential V1 is applied to the wiring 111. In this case, the potential is V It is preferably 0.2 times or more and less than 1 time of 1. More preferably, it is 0.3 times or more and less than 0. It is preferably 0.9 times or less, and more preferably 0.5 times or more and 0.7 times or less.

[0125] For example, when the potential V1 and the potential V2 are selectively applied to the wiring 114, 13 is selectively given a potential lower than the potential V1 and a potential higher than the potential V2. In this case, the rise time of the potential of the wiring 114 is longer than the rise time of the potential of the wiring 113. Alternatively, the fall time of the potential of the wiring 114 is often shorter than the rise time of the potential of the wiring 114. The potential fall time of the wiring 114 is often shorter than that of the wiring 113. It is often connected to 13 via an inverter circuit.

[0126] For example, when the potential V1 and the potential V2 are selectively applied to the wiring 113, 14 is selectively given a potential lower than the potential V1 and a potential higher than the potential V2. In this case, the rise time of the potential of the wiring 113 is longer than the rise time of the potential of the wiring 114. Alternatively, the fall time of the potential of the wiring 113 is often shorter than the rise time of the potential of the wiring 113. The potential fall time of the wiring 113 is often shorter than that of the wiring 114. It is often connected to 14 via an inverter circuit.

[0127] Next, an example of the threshold voltage of each transistor will be described. By setting the value appropriately, the driving capability of the semiconductor device can be improved.

[0128] For example, the threshold voltage of transistor 103 is different from the threshold voltage of transistor 101 and / or It is preferable that the threshold voltage of the transistor 103 is larger than that of the transistor 102. The threshold voltage is preferably greater than one and less than three times the threshold voltage of the transistor 101. More preferably, it is 1.2 times or more and 2.5 times or less. Even more preferably, it is 1.5 times or more. More than twice as much.

[0129] Also, for example, the threshold voltage of the transistor 104 is the threshold voltage of the transistor 101 and / or It is preferable that the threshold voltage of the transistor 102 is higher than that of the transistor 102. The threshold voltage of transistor 04 is more than 1 time and less than 3 times the threshold voltage of transistor 101. It is preferable that the ratio is 1.2 times or more and 2.5 times or less. It is even more preferable that the ratio is 1. More than five times and less than two times.

[0130] For example, the sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 103 is It is preferable that the potential V1 is smaller than the driving voltage of the semiconductor device (for example, potential V1-potential V2). The sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 103 is It is preferable that the voltage is 1 / 100 times or more and 1 / 2 times or less of the drive voltage of the device. , 1 / 50 times or more and 1 / 5 times or less. More preferably, 1 / 30 times or more and 1 / 10 times or less. The sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 103 is Since the voltage is smaller than the driving voltage of the semiconductor device, malfunction of the semiconductor device is prevented, and the semiconductor device can be made to operate normally.

[0131] Next, an example of the size of each transistor will be described. By setting the value to such a value, the driving capability of the semiconductor device of this embodiment can be improved. .

[0132] For example, when transistor 101 is turned on, the potential difference between the gate and source is is often smaller than the potential difference between the gate and source when transistor 103 turns on. Therefore, the channel width of the transistor 101 is smaller than the channel width of the transistor 103. In particular, the channel width of the transistor 101 is preferably larger than that of the transistor 102. It is preferable that the width is greater than 1 time and less than 10 times the channel width of O3. The ratio is preferably 1.3 times or more and 5 times or less, and more preferably 1.5 times or more and 3 times or less.

[0133] Furthermore, for example, the load of the wiring 112 is often larger than the load of the node 11. Therefore, the channel width of the transistor 103 is larger than the channel width of the transistor 104. In particular, it is preferable that the channel width of the transistor 103 is It is preferable that the width is more than 1 time and not more than 10 times the width of the panel. More preferably, it is 1.5 times. It is more preferably from 2 to 5 times.

[0134] Also, for example, the channel length of the transistor 103 and / or the channel length of the transistor 104 Specifically, the channel length of the transistor 103 is preferably as long as The channel length of the transistor 101 and / or the channel length of the transistor 102 are greater than the channel length of the transistor 101 and / or the channel length of the transistor 102. Alternatively, the channel length of the transistor 104 is preferably It is preferable that the length of the transistor 102 is longer than the length of the transistor 102 and / or the channel length of the transistor 102. By increasing the channel length of the transistor 103 and / or the channel length of the transistor 104, As a result, the amount of shift in the threshold voltage of the transistor 103 and / or the transistor 104 is Therefore, the reliability of the semiconductor device can be improved.

[0135] Next, a semiconductor device having a different structure from the semiconductor device shown in FIG. 5A will be described.

[0136] For example, the transistor 103 and the transistor 104 are the semiconductor device shown in FIG. It may also be provided in the semiconductor devices shown in FIGS. 3(A) to 3(D) and 4(A) to 4(C). 3(A) to (D) in which the transistor 103 and the transistor 104 are provided. The semiconductor device shown in FIGS. 4A to 4C has the same function as the semiconductor device shown in FIG. 5A. and has a similar effect.

[0137] FIG. 7A shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. An example of setting 04 is shown below.

[0138] FIG. 7B shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. An example of setting 04 is shown below.

[0139] FIG. 7C shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. In the semiconductor device shown in FIG. 7C, the wiring 113 is omitted. This allows the number of wires and signals to be reduced.

[0140] FIG. 8A shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. An example of setting 04 is shown below.

[0141] FIG. 8B shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. An example of setting 04 is shown below.

[0142] FIG. 8C shows a semiconductor device in which the transistor 103 and the transistor 104 are added to the semiconductor device in FIG. An example of setting 04 is shown below.

[0143] Also, for example, the semiconductor devices shown in FIGS. 5(A), 7(A) to 7(C), and 8(A) to 8(C) In this arrangement, the transistor 104 can be omitted. By omitting this, the number of transistors can be reduced, which reduces the layout area. It can be made easier.

[0144] FIG. 9A shows a case where the transistor 104 is omitted from the semiconductor device shown in FIG. An example of this case is shown below.

[0145] FIG. 9B shows a case where the transistor 104 is omitted from the semiconductor device shown in FIG. An example of this case is shown below.

[0146] Next, an example of a circuit (also called a control circuit) having a function of controlling a semiconductor device will be described. do.

[0147] 10 shows a circuit 130 for controlling a semiconductor device. The semiconductor device shown in FIG. 5(A) is used. For example, the semiconductor device is not limited to the semiconductor device shown in Embodiment 1. The semiconductor device, the semiconductor device described in this embodiment, or the semiconductor device described in other embodiments It is possible to use:

[0148] The circuit 130 has a function of applying a potential to each wiring of the semiconductor device. The function of controlling the timing of signal output and voltage supply to each wiring of a semiconductor device is Has.

[0149] The circuit 130 includes a circuit 131, a circuit 132, a circuit 133, and a circuit 134. The circuit 131 has a function of supplying a voltage V1 to the wiring 111. The circuit 132 has a function of supplying a signal to the wiring 113. The circuit 133 has a function of supplying a signal to the wiring 114. 15. In this way, the circuit 131, the circuit 132, and the circuit 133 has a function as a signal generating circuit or a timing generator circuit. The circuit 131 and the circuit 134 function as a voltage generating circuit or a regulator circuit. do.

[0150] The circuits 131 to 134 are amplifier circuits, bipolar transistors, and MOS transistors, respectively. resistors, capacitance elements, resistance elements, coils, DC voltage sources, AC voltage sources, DC current sources and switches It can be composed of at least one of the following:

[0151] Note that a protective circuit 140 can be connected to the wiring 113 and the wiring 114. The protection circuit 140 includes a plurality of transistors 141 and a plurality of transistors 142 . A first terminal of the transistor 141 is connected to the wiring 115, and a second terminal of the transistor 141 is connected to the wiring 115. The terminal of the transistor 141 is connected to the wiring 113 or the wiring 114. A first terminal of the transistor 142 is connected to the wiring 111. The second terminal of the transistor 142 is connected to the wiring 113 or the wiring 114. The gate of the transistor 42 is connected to the wiring 113 or the wiring 114. One of the transistors 142 can be omitted.

[0152] This embodiment mode can be combined with other embodiment modes as appropriate.

[0153] (Embodiment 3) In this embodiment, an example of a semiconductor device and an example of a method for driving the semiconductor device will be described. In particular, an example of a NOR circuit and a NAND circuit using the semiconductor device described in Embodiment 2 will be described. An example of a method for driving the NOR circuit and the NAND circuit will be described below.

[0154] First, a configuration for providing the semiconductor device shown in the second embodiment with a function as a NOR circuit is described. We will explain about this.

[0155] In the semiconductor device described in Embodiment 2, N (N is a self-transistor) is provided between the wiring 115 and the wiring 112. A number of transistors 103 (referred to as transistors 103_1 to 103_N) are connected in parallel. The gates of the N transistors 103 are connected to N wirings 114 (wirings 11 4_1 to 114_N). Between the wiring 115 and the node 11, N Transistors 104 (shown as transistors 104_1 to 104_N) are connected in parallel. The gates of the N transistors 104 are connected to N wirings 114, respectively. For example, The first terminal of the transistor 103_i (i is any one of 1 to N) is connected to the wiring 115. a first terminal of the transistor 103_i connected to a wiring 112; The gate of the transistor 103_i is connected to the wiring 114_i. A first terminal of the transistor 104_i (any one of the transistors 104_i to N) is connected to the wiring 115. The second terminal of the transistor 104_i is connected to the node 11. The gate of the transistor 104_i is connected to the wiring 114. With this configuration, the semiconductor device according to the second embodiment has an N-input It can function as a NOR circuit.

[0156] FIG. 11A shows an example of a NOR circuit in which the above-described configuration is added to the semiconductor device shown in FIG. 7C. Shows.

[0157] FIG. 11B shows an example of a NOR circuit in which the above configuration is added to the semiconductor device shown in FIG. 5A. In the NOR circuit shown in FIG. 11B, the wiring 113 has N wirings 114. The inverted signal of the signal input to either of them may be input.

[0158] Next, an example of the operation of the NOR circuit using the semiconductor device shown in Embodiment 2 will be described with reference to FIG. The semiconductor device shown in (A) will be described as an example. When a potential V1 is applied to one of the wires 114, a potential V2 is applied to all of the N wires 114. Two types of operation will be explained.

[0159] The operation when a potential V1 is applied to at least one of the N wires 114 will be described. Here, a potential V1 is applied to the wiring 114_1, and the other wirings (wirings 114_2 to 114_N) is applied with a potential V2. Assume that a potential V2 is applied to 15. Therefore, the transistor 104_1 is turned on. Therefore, the transistors 104_2 to 104_N are turned off, and the wiring 115 and the node 11 At this time, the transistor 102 is turned on, and the wiring 111 and the node Thus, the node 11 is connected to the potential of the wiring 115 and the potential of the wiring 111. Therefore, the potential of the node 11 is equal to the potential of the wiring 115 (potential V2). The potential of the node 11 exceeds V2 and is lower than the potential of the wiring 111 (potential V1). +Vth101 is assumed to be less than 101. Therefore, transistor 101 is turned off. At this time, the wiring 111 and the wiring 112 are brought into a non-conductive state. The wiring 115 and the wiring 103_N are turned on and the transistors 103_2 to 103_N are turned off. Thus, the potential of the wiring 115 is supplied to the wiring 112. Therefore, the potential of the wiring 112 becomes equal to the potential V2 (see FIG. 12A).

[0160] The operation when the potential V2 is applied to all of the N wires 114 will be described. It is assumed that a potential V1 is applied to the wiring 111 and a potential V2 is applied to the wiring 115. Since the transistors 104_1 to 104_N are turned off, the wiring 115 and the node 11 are not conductive. At this time, the transistor 102 is turned on, and the wiring 111 and the node 1 Then, the potential of the wiring 111 is supplied to the node 11, The potential of node 11 starts to rise. Eventually, the potential of node 11 rises to V2+Vth101. Therefore, the transistor 101 is turned on, and the wiring 111 and the wiring 112 At this time, the transistors 103_1 to 103_N are turned off. Thus, the wiring 115 and the wiring 112 are in a non-conductive state. Since the potential of the wiring 112 is supplied to the node 11, the potential of the wiring 112 starts to rise. The potential of the transistor 102 rises to V1-Vth102. Therefore, the transistor 102 is turned off. Therefore, the wiring 111 and the node 11 are not electrically connected to each other. Then, the node 11 is in a floating state. At this time, the potential of the wiring 112 continues to rise. The potential is V1+Vth due to the parasitic capacitance between the gate and the second terminal of the transistor 101. The voltage rises to 101+Va. This is the so-called bootstrap operation. The potential of 12 rises to a value equal to the potential V1 (see FIG. 12(B)).

[0161] It is desirable that the channel widths of the N transistors 103 are equal to each other. Due to limitations in the arrangement, it is difficult to make the channel widths of the N transistors 103 equal to each other. In this case, the channel widths of at least two of the N transistors 103 are set equal to each other. By making the channel widths equal to each other, the circuit design becomes easier and the operation This is because the above-mentioned problem can be prevented. The same applies to the transistor 104. .

[0162] The N transistors 103 drive the wiring 112, so they must have a large driving capability. Therefore, it is preferable that the channel width of at least one of the N transistors 103 is It is preferably larger than the channel width of at least one of the N transistors 104 . In particular, the channel width of at least one of the N transistors 103 is Preferably, the channel width is greater than 1 and less than 10 times the channel width of at least one of the channels 104. More preferably, it is 1.5 times or more and 7 times or less. Even more preferably, it is 2 times or more and 5 times or less. The following is the result.

[0163] When the potential V2 is applied to the N wirings 114, the potential of the node 11 is Therefore, it is preferable that the value of N transistors be set so that the N transistors 101 are turned off. The channel width of at least one of the transistors 104 is greater than the channel width of the transistor 102. In particular, it is preferable that the channel width of at least one of the N transistors 104 is It is preferable that the thickness is greater than 1 time and less than 10 times the channel width of the transistor 102. Preferably, it is 2 times or more and 5 times or less. More preferably, it is 2.5 times or more. Above, it is 3.5 times or less.

[0164] Next, a configuration for providing the semiconductor device shown in the second embodiment with a function as a NAND circuit will be described. This article explains:

[0165] A structure for providing the semiconductor device shown in Embodiment 2 with the function of a NAND circuit will be described below. In the semiconductor device described in Embodiment 2, the wiring 115 and the wiring 112 are separated from each other by a N (N is a natural number) transistors 103 (referred to as transistors 103_1 to 103_N) ) are connected in series. The gates of the N transistors 103 are connected to the N wirings 114 (wirings 114_1 to 114_N). N transistors 104 (referred to as transistors 104_1 to 104_N) are connected in series. The gates of the N transistors 104 are connected to N wirings 114, respectively. For example, the first terminal of the transistor 103_i (i is any one of 1 to N) is The second terminal of the transistor 103_i+1 is connected to the second terminal of the transistor 103_i. is connected to the first terminal of the transistor 103_i-1 and is connected to the gate of the transistor 103_i. The output of the transistor 104_i (i is any one of 1 to N) is connected to the wiring 114_i. The first terminal of the transistor 104_i+1 is connected to the second terminal of the transistor 104_i+2. The second terminal of the transistor 104_i is connected to the first terminal of the transistor 104_i-1. The gate of the transistor 104_i is connected to the wiring 114_i. The second terminal of the transistor 103_1 is connected to the wiring 112. The second terminal of the transistor 104_1 is connected to a wiring 115. The first terminal of the transistor 104_N is connected to the wiring 115. With such a configuration, the semiconductor device according to the second embodiment functions as an N-input NAND circuit. It can have the ability.

[0166] FIG. 13A shows one example of a NAND circuit in which the above-described configuration is added to the semiconductor device shown in FIG. 7C. Here is an example.

[0167] FIG. 13B shows a NAND circuit in which the above configuration is added to the semiconductor device shown in FIG. 5A. The wiring 113 is connected to one of the N wirings 114. Just input the signal.

[0168] Next, an example of the operation of a NAND circuit using the semiconductor device described in Embodiment 2 will be described with reference to FIG. 3(A) will be described as an example. Here, at least N wirings 114 are In the case where a potential V2 is applied to one of the wires 114, the potential V1 is applied to all of the N wires 114. This section explains two different operations:

[0169] The operation when a potential V2 is applied to at least one of the N wires 114 will be described. Here, a potential V1 is applied to the wiring 114_1, and the other wirings (wirings 114_2 to 114_N) is applied with a potential V2. Assume that a potential V2 is applied to 15. Therefore, the transistor 104_1 is turned on. Therefore, the transistors 104_2 to 104_N are turned off, and the wiring 115 and the node 11 At this time, the transistor 102 is turned on, and the wiring 111 and the node Then, the potential of the wiring 111 is supplied to the node 11. The potential of the node 11 starts to rise. Eventually, the potential of the node 11 becomes V2+Vth101 Therefore, the transistor 101 is turned on, and the wiring 111 and the wiring 11 At this time, the transistor 103_1 is turned on, and the transistor Since 103_2 to 103_N are turned off, the wiring 115 and the wiring 112 are in a non-conductive state. In this way, the potential of the wiring 111 is supplied to the wiring 112, and therefore the potential of the wiring 112 Then, the potential of the node 11 rises to V1-Vth102. Therefore, the transistor 102 is turned off, and the wiring 111 and the node 11 are not electrically connected. Then, the node 11 is in a floating state. At this time, the potential of the wiring 112 rises. Therefore, the potential of the node 11 is connected to the gate of the transistor 101 and the second terminal The parasitic capacitance between the This is a trapping action. Thus, the potential of the wiring 112 rises to a value equal to the potential V1. (See Figure 14(A)).

[0170] The operation when the potential V1 is applied to all of the N wires 114 will be described. It is assumed that a potential V1 is applied to the wiring 111 and a potential V2 is applied to the wiring 115. The transistors 104_1 to 104_N are turned on, so that the wiring 115 and the node 11 are electrically connected. At this time, the transistor 102 is turned on, and the wiring 111 and the node 11 Thus, the node 11 is connected to the potential of the wiring 115 and the potential of the wiring 111. Therefore, the potential of the node 11 exceeds the potential of the wiring 115 (potential V2), The potential of the node 11 is lower than the potential of the wiring 111 (potential V1). Therefore, the transistor 102 is turned off, and the wiring 111 and the wiring The line 112 is in a non-conductive state. At this time, the transistors 103_1 to 103_N are turned on. Therefore, the wiring 115 and the wiring 112 are electrically connected. is supplied to the wiring 112, the potential of the wiring 112 becomes equal to the potential V2 (see FIG. 14(B)).

[0171] It is desirable that the channel widths of the N transistors 103 are equal to each other. Due to limitations in the arrangement, it is difficult to make the channel widths of the N transistors 103 equal to each other. In this case, the channel widths of at least two of the N transistors 103 are set equal to each other. By making the channel widths equal to each other, the circuit design becomes easier and the operation This is because the above-mentioned problem can be prevented. The same applies to the transistor 104. .

[0172] In order to shorten the fall time of the potential of the wiring 112, N transistors 103 However, if the channel width is too large, the layout becomes unreliable. Therefore, the channel width of the N transistors 103 is reduced. At least one channel width is N times or less the channel width of the transistor 101. It is preferable that the ratio is 1 / 3 or more and 3 times or less. It is even more preferable that the ratio is 1 / 2. More than double, but less than double.

[0173] When the potential V1 is applied to all of the N wirings 114, the potential of the node 11 is set to V2+ To make Vth101 or less, the channel width of the N transistors 104 is preferably large. However, if the channel width is too large, the layout area will become large. Therefore, the channel width of at least one of the N transistors 104 is It is preferable that the width is N times or less the channel width of the capacitor 102. More preferably, it is 1 / 3 times or more. More preferably, it is 1 / 2 to 2 times.

[0174] As described above, the NOR circuit or Therefore, the NOR circuit and the NAND circuit of this embodiment can be configured. The circuit can provide the same effects as those of the semiconductor device shown in the first and second embodiments.

[0175] This embodiment mode can be combined with other embodiment modes as appropriate.

[0176] (Fourth embodiment) In this embodiment, an example of a semiconductor device and an example of a method for driving the semiconductor device will be described. In particular, an example of a decoder circuit using the semiconductor device described in Embodiment 3 and a decoder circuit thereof will be described. An example of a method for driving the inverter circuit will be described.

[0177] First, an example of the configuration of the semiconductor device according to this embodiment will be described.

[0178] FIG. 16 shows an example of a decoder circuit according to this embodiment. The decoder circuit shown in FIG. m is a natural number) NOR circuits 201 (referred to as NOR circuits 201_1 to 201_m). do.

[0179] The m NOR circuits 201 are each the NOR circuit shown in the third embodiment. It is good.

[0180] Each of the m NOR circuits 201 has N (N is a natural number, 2 N >m) bit control signal is input The N-bit control signal is composed of the control signals D1 to DN and the control signals Db1 to DbN. The control signals Db1 to DbN are inverted signals of the control signals D1 to DN. Different control signals are input to the m NOR circuits 201. For example, The control signals D1 to DN are input to the NOR circuit 201_1. The NOR circuit 201_3 receives the control signal Db1 and the control signals D2 to DN. 1, the control signal Db2 and the control signals D3 to DN are input. In this way, m NOR circuits By making the control signals input to the m NOR circuits 201 different from each other, 1 is used to combine the signals output from the other NOR circuits 201. Specifically, any one of the m NOR circuits 201 can be set to a value different from The signal output from the NOR circuit 201 is set to H level, and the signals output from the other NOR circuits 201 are set to H level. , the control signals D1 to DN and the control signals Db1 to Db By changing the value of N every predetermined time (for example, every gate selection period), the NOR circuit 20 1_1 to NOR circuit 201_m can output an H-level signal in sequence. Alternatively, the m NOR circuits 201 can output H-level signals in any order. can.

[0181] The control signals D1 to DN are transmitted through N wirings 212 (shown as wirings 212_1 to 212_N). The control signals Db1 to DbN are input to the decoder circuit via N wirings 213 ( The signals are input to the decoder circuit via lines 213_1 to 213_N. The output signals of the circuits 201 are output to m wirings 211 (wirings 211_1 to 211_m). will be done.

[0182] The control signals Db1 to DbN are generated by inverting the control signals D1 to DN using an inverter circuit or the like. In order to generate the control signals Db1 to DbN, As the inverter circuit for this purpose, the semiconductor device described in Embodiment 1 or the like can be used. be.

[0183] The decoder circuit can be configured using not only NOR circuits but also NAND circuits. As the NAND circuit, the NAND circuit shown in the third embodiment may be used. 7 shows a circuit diagram of a decoder circuit configured using NAND circuits. The decoder circuit is different from the decoder circuit shown in FIG. 16 in that instead of m NOR circuits 201, m NAND circuits 202 (referred to as NAND circuits 202_1 to 202_m) are used. They differ in points.

[0184] In the decoder circuit shown in FIG. 17, the output from any one of the m NAND circuits 202 The signal input to the NAND circuit 202 becomes L level, and the signals output from the other NAND circuits 202 become H level. Therefore, m inverter circuits 203 (inverter circuits 203) are used as needed. It is possible to provide m NAND circuits 202 (shown as 203_1 to 203_m). The signal is output to m wirings 211 via m inverter circuits 203 .

[0185] As described above, the NOR circuit or the NAND circuit shown in the third embodiment is used to Therefore, the decoder circuit of this embodiment can be configured as follows: The same effects as those of the semiconductor devices shown in the first and second embodiments can be obtained.

[0186] This embodiment mode can be combined with other embodiment modes as appropriate.

[0187] (Embodiment 5) In this embodiment mode, an example of a structure of a semiconductor device and an example of a manufacturing process of the semiconductor device will be described. In particular, a thin-film transistor in which a channel formation region is made of an oxide semiconductor will be described. An example of a thin film transistor and an example of a manufacturing process of the thin film transistor will be described.

[0188] <Transistor configuration example> FIG. 15D shows a transistor 450 (for example, a thin film transistor) which is an example of the configuration of a semiconductor device. The transistor 450 shown in FIG. 15(D) is an inverted staggered thin-film transistor. Also, in Figure 15(D), a thin film transistor with a single gate structure is shown. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions may also be used. The thin film transistor can be an n-type transistor. However, a p-type transistor may also be used.

[0189] The transistor 450 includes a gate electrode layer 411 provided over a substrate 400 and a gate electrode layer A gate insulating layer 402 covering the gate electrode layer 411 and an oxide semiconductor layer provided on the gate electrode layer 411 406a, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer 406a. The transistor 450 has an insulating layer 412 and a The insulating layer 412 and the insulating layer 418 are not essential. Since it is not a component, it can be omitted as appropriate.

[0190] The oxide semiconductor layer 406a may include a quaternary metal oxide such as In—Sn—Ga—Zn—O. , ternary metal oxides such as In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O system, and binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al-Zn- O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, In-O-based, Sn- O-based, Zn-O-based, etc. are used.

[0191] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0192] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0 and m is not a natural number). Also, M is used instead of Ga. Used InMO3(ZnO) m (m>0 and m is not a natural number) M is a gallium (Ga), aluminum (Al), or iron ( One selected from the group consisting of iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. It represents a metal element or a plurality of metal elements. For example, M may be Ga and Al, Ga and and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. The above composition is derived from the crystal structure and is merely an example. In addition, the oxide semiconductor represented by In-Ga-Zn-O in this specification The material is InGaO3(ZnO) m (m>0 and m is not a natural number) and m is a natural number. The fact that it is not a number can be confirmed by ICP-MS analysis or RBS analysis.

[0193] The hydrogen concentration in the oxide semiconductor layer is 5×10 19 (atoms / cm 3 ) or less is preferable. Desirable.

[0194] <Transistor manufacturing method> Next, a method for manufacturing the above-described thin film transistor will be described with reference to FIGS. 15(A) to 15(D). This will be explained in light of the above.

[0195] First, a gate electrode layer 411 is formed on a substrate 400, and then a gate electrode layer 411 is formed on the substrate 400. The gate insulating layer 402 is formed as shown in FIG. 1. After that, an oxide semiconductor layer 406 is formed (see FIG. 15(A)).

[0196] For example, a glass substrate can be used as the substrate 400. The glass substrate is made of a non-alkali material. The alkali-free glass substrate is preferably an aluminosilicate glass substrate. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass The substrate 400 may be a ceramic substrate, a quartz substrate, a safa substrate, or the like, in addition to a glass substrate. The surface of an insulating substrate made of an insulator such as a metal substrate, or a semiconductor substrate made of a semiconductor material such as silicon The surface of a conductive substrate made of a conductor such as metal or stainless steel is covered with an insulating material. The material coated with the edge material can be used. Although synthetic resin substrates generally tend to have low heat resistance, they can be used in the subsequent manufacturing process. Any material that can withstand the processing temperature can be used as the substrate 400 .

[0197] The gate electrode layer 411 is formed by forming a conductive layer on the substrate 400 and selectively etching the conductive layer. The gate electrode layer 411 can be formed by a method such as a sputtering method. PVD (Physical Vapor Deposition) method and Plasma C Using CVD methods such as VD (Chemical Vapor Deposition) The gate electrode layer 411 can be formed of aluminum, chromium, copper, or tin. Metallic materials selected from tantalum, titanium, molybdenum, and tungsten, or materials containing the above elements, The material can be an alloy containing manganese, magnesium, zirconium, or the like. Alternatively, a material containing one or more of aluminum and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A material containing one or more elements selected from the above may be used.

[0198] Alternatively, the gate electrode layer 411 may be formed using a conductive metal oxide. Metal oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (Z nO), indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) Indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxides The oxide material may contain silicon or silicon oxide.

[0199] The gate electrode layer 411 may have a single-layer structure or a stacked structure of two or more layers. In this embodiment, after the gate electrode layer 411 is formed, heat treatment is performed at a relatively high temperature. Therefore, the gate electrode layer 411 is made of a material that is heat-resistant enough to withstand this heat treatment. It is desirable to form the insulating film using a material having heat resistance, such as titanium or tantalum. , tungsten, molybdenum, etc. Also, by adding impurity elements, Polysilicon with enhanced conductivity may also be used.

[0200] The gate insulating layer 402 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 402 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or oxide. It is preferable to form the film so as to contain aluminum oxide, hafnium oxide, tantalum oxide, etc. The gate insulating layer 402 may have a single-layer structure or a stacked structure of two or more layers. The thickness of the gate insulating layer can be, for example, 10 nm or more and 500 nm or less.

[0201] The gate insulating layer 402 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. By using high-k materials, gate leakage can be reduced. a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or The thin film may have a laminated structure with at least one of a thin film layer and an aluminum oxide layer.

[0202] Note that the gate insulating layer 402 is formed so as not to contain impurities such as hydrogen and water as much as possible. When the gate insulating layer 402 contains hydrogen or water, the oxide semiconductor The hydrogen penetrates into the oxide semiconductor layer 406a, and oxygen in the oxide semiconductor layer 406a is extracted by hydrogen. This is because there is a risk that the characteristics of the transistor may deteriorate.

[0203] For example, when the gate insulating layer 402 is formed by a sputtering method or the like, It is desirable to form the film in a state where residual moisture in the processing chamber is removed. For this purpose, it is preferable to use an adsorption type vacuum pump. A turbo pump or a titanium sublimation pump can be used. A cold trap may be added. The chamber is sufficiently free of hydrogen, water, and other impurities contained in the gate insulating layer 402. The concentration of can be reduced.

[0204] In addition, the high density plasma CVD method using microwaves (for example, frequency 2.45 GHz) This is advantageous in that a high-quality gate insulating layer 402 that is dense and has a high dielectric strength can be formed. The oxide semiconductor layer 406a and the high-quality gate insulating layer 402 are in close contact with each other, so that the interface The level can be reduced to improve the interface characteristics. 11 / cm 3 It is preferable to use a high density plasma device that can achieve a plasma density of at least this level. The interface characteristics with the gate insulating layer 402 are improved, and impurities of the oxide semiconductor, particularly water, are prevented from being removed. By eliminating oxygen and water, gate bias and thermal stress tests (BT tests: for example, 8 5°C, 2 x 10 6 V / cm, 12 hours, etc.) Therefore, it is possible to obtain a stable transistor that does not undergo any degradation.

[0205] When the gate electrode layer 411 is formed, impurities such as hydrogen and water are present at a concentration of about several ppm. It is desirable to use a high-purity gas with a concentration reduced to about several ppb.

[0206] Note that the oxide semiconductor layer (highly purified oxide) to be made i-type or substantially i-type in a later step Since the semiconductor layer is extremely sensitive to the interface state and the interface charge, Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor layer is Therefore, high-density plasma CV using μ-wave (2.45 GHz) is required. D is preferable because it can form a dense, high-quality insulating film with high dielectric strength. The close contact between the oxide semiconductor and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because the film quality as a gate insulating layer is good. It is also possible to reduce the interface state density with the oxide semiconductor layer and form a good interface. It is important to

[0207] The oxide semiconductor layer 406 is grown under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Sputtering is performed under a mixed atmosphere of rare gas (typically argon) and oxygen. The oxide semiconductor layer 406 can be formed in an atmosphere containing, for example, hydrogen, water, or hydroxide. Impurities such as bases and hydrides are reduced to a concentration of about several ppm (preferably a concentration of about several ppb). Preferably, a vacuumed high purity gas atmosphere is used.

[0208] Before the oxide semiconductor layer 406 was formed by a sputtering method, argon gas was introduced. The reverse sputtering that generates plasma is performed to remove the powder adhering to the surface of the gate insulating layer 402. It is preferable to remove the substance (also called particles or dust). No voltage was applied to the target side, and voltage was applied to the substrate side using an RF power supply in an argon atmosphere. This method generates plasma near the substrate and modifies the surface. Alternatively, nitrogen, helium, oxygen, etc. may be used.

[0209] The oxide semiconductor layer 406 is made of a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system , Zn—O-based, etc.

[0210] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0211] In this embodiment, the oxide semiconductor layer 406 is an In—Ga—Zn—O-based oxide semiconductor. An amorphous oxide semiconductor layer 406 is formed by a sputtering method using a target. It shall be so decided.

[0212] A substrate for forming an In-Ga-Zn-O-based oxide semiconductor layer 406 by sputtering is used. The target is In:Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, a target having a composition ratio of In:Ga:Zn=1:1: 1 [atom ratio] (x=1, y=1), (i.e., In2O3:Ga2O3:ZnO= A target having a composition ratio of 1:1:2 (molar ratio) may also be used. The compound semiconductor target is In:Ga:Zn=1:1:0.5 [atom ratio] or a target having In:Ga:Zn=1:1:2 [atomic ratio], In:Ga A target with a composition ratio of Zn=1:0:1 (atom ratio) (x=0, y=1) was used. It is also possible to use a target containing 2% by weight or more and 10% by weight or less of SiO2. The oxide semiconductor layer 406 can be formed by using a method similar to that described above, so that the oxide semiconductor layer 406 contains SiOx (x>0).

[0213] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 95% or more. The relative density is preferably 99.9% or more. By using such a material, the oxide semiconductor layer 406 can be formed with a dense structure.

[0214] When the oxide semiconductor layer 406 is formed, for example, the substrate is placed in a treatment chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the sputtering gas from which hydrogen and water have been removed while removing the remaining moisture in the processing chamber. The oxide semiconductor layer 406 is formed using the target. By forming the oxide semiconductor layer 406, impurities contained in the oxide semiconductor layer 406 can be removed. This reduces the amount of residuals in the processing chamber. To remove moisture, it is preferable to use the above-mentioned adsorption type vacuum pump. For example, The processing chamber is evacuated using a cryopump, and hydrogen and water are removed, so oxides The concentration of impurities contained in the semiconductor layer 406 can be reduced.

[0215] The oxide semiconductor layer 406 is formed under the following conditions: the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon It is possible to apply conditions such as a mixed atmosphere. This reduces dust (powder or flake-like material formed during film formation) and improves film thickness distribution. The thickness of the oxide semiconductor layer 406 is preferably greater than or equal to 2 nm and less than or equal to 200 nm. However, depending on the oxide semiconductor material and application, the thickness is preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the material and application. That's fine.

[0216] Next, the oxide semiconductor layer 406 is selectively etched to form an island-shaped oxide semiconductor layer 406a After that, a conductive film is formed to cover the gate insulating layer 402 and the oxide semiconductor layer 406a. The conductive layer is then etched to form the source and drain electrode layers 408. a and 408b are formed (see FIG. 15(B)).

[0217] The oxide semiconductor layer can be etched by either dry etching or wet etching. The oxide semiconductor layer is etched into a desired shape. To achieve this, we have set the etching conditions (etching gas, etching solution, etc.) according to the material. The heating time, temperature, etc. should be set appropriately.

[0218] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the amount of power applied to the substrate-side electrode Temperature, etc. must be set appropriately.

[0219] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), Carbon tetrachloride (CCl4, etc.) and gases containing fluorine (fluorine-based gases, e.g. For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and A gas to which a rare gas such as uranium (He) or argon (Ar) is added may also be used.

[0220] The etching solution that can be used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia solution, hydrogen peroxide solution (31% by weight: 28% by weight ammonia solution, 5% by weight ammonia solution) :2:2) and other etching solutions such as ITO07N (Kanto Chemical Co., Ltd.) are also available. That's fine.

[0221] Next, the oxide semiconductor layer 406a is preferably subjected to first heat treatment. By performing the treatment, excess water (including a hydroxyl group) and water in the oxide semiconductor layer 406a are removed. The temperature of the first heat treatment is, for example, 400°C or higher and 750°C or lower. The first heat treatment is performed at a temperature of 400° C. or higher and lower than the distortion point of the substrate. The substrate 400 is introduced into an electric furnace using a body or the like, and the heating is performed in a nitrogen atmosphere at 450°C for 1 hour. During this time, the oxide semiconductor layer 406a is not exposed to the air and is kept free from water and hydrogen. It is preferable to prevent this.

[0222] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction or heat radiation from a medium such as a heated gas. For example, a lamp-heated RTA ( LRTA (Lamp Rapid Thermal Anneal) equipment, heated gas Gas Rapid Thermal Angle (GRTA) neal) equipment, or an RTA equipment equipped with both lamp heating and gas heating. When a gas-heated device is used, the gas used is a rare gas such as argon. An inert gas such as nitrogen or argon that does not react with the material to be treated by heat treatment is used. .

[0223] For example, as the first heat treatment, the substrate is placed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C. GRTA process involves placing a substrate in the chamber, heating it for a few minutes, and then removing the substrate from the inert gas atmosphere. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a long-term heat treatment, it can be applied even to temperature conditions that exceed the heat resistance temperature of the substrate. For example, when using a glass substrate, the substrate may shrink at temperatures exceeding the heat resistance temperature (distortion point). However, this is not a problem if the heat treatment is performed for a short time. Alternatively, the inert gas may be replaced with a gas containing oxygen. This is because the heat treatment can reduce defects caused by oxygen deficiency.

[0224] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less. In ultra-dry air with 20 ppm or less of H2O, and more preferably in ultra-dry air with 1 ppm or less of H2O. The first heat treatment may be carried out in dry air. Water (including hydroxyl groups), hydrogen, and the like in the compound semiconductor layer 406 can be removed.

[0225] By performing the above-described first heat treatment, hydrogen contained in the oxide semiconductor layer 406 is reduced. Preferably, hydrogen contained in the oxide semiconductor layer 406 is removed, and the main It can be highly purified so that impurities other than the components are not included as much as possible.

[0226] Note that the first heat treatment performed on the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, the first heat treatment may be performed on the compound semiconductor layer 406. After the substrate is removed from the device, etching using a mask or the like is performed.

[0227] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after the formation of the oxide semiconductor layer. After a source electrode layer and a drain electrode layer are stacked over the oxide semiconductor layer, After forming the protective insulating film on the drain electrode layer, the step of forming the protective insulating film may be performed at any step.

[0228] The source and drain electrode layers 408a and 408b cover the oxide semiconductor layer 406a. As described above, the conductive layer is formed and then selectively etched. The conductive layer can be formed by sputtering or vacuum deposition. Gold selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten metal materials, alloy materials containing the above elements, or alloy materials combining the above elements Manganese, magnesium, zirconium, beryllium, yttrium, etc. Alternatively, one or more materials selected from aluminum may be used. , titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Materials containing one or more selected elements may also be used.

[0229] The source electrode layer and the drain electrode layer 408a and 408b may have a single-layer structure. For example, a single layer structure of an aluminum film containing silicon may be used. , a two-layer structure in which a titanium film is laminated on an aluminum film, and an aluminum film is laminated on a titanium film Furthermore, a three-layer structure in which a titanium film is laminated on an aluminum film can be used.

[0230] When the conductive layer is subjected to heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer 406a, It is preferable to use a conductive layer that has heat resistance sufficient to withstand this heat treatment.

[0231] The oxide semiconductor layer 406a is formed of a material selected from the group consisting of SiO 2 and SiO 3 so that the oxide semiconductor layer 406a is not removed when the conductive layer is etched. The material and etching conditions are adjusted appropriately.

[0232] In this embodiment, a titanium film is used as the conductive layer, and an In- Using Ga-Zn-O oxide, ammonia hydrogen peroxide (ammonia, A mixture of water and hydrogen peroxide is used.

[0233] Note that when the conductive layer is etched, only part of the oxide semiconductor layer 406a is etched. In this case, the oxide semiconductor layer 406a may have a groove (depression). The mask used in the process may be formed by an inkjet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0234] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and ashing can further deform the shape. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0235] Next, gases such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar) are used. The plasma treatment is performed to remove the oxide semiconductor layer from the exposed surface. Removes adsorbed water, etc. Also, plasma treatment is performed using a mixture of oxygen and argon gas. may be performed.

[0236] Next, the oxide semiconductor layer 406a and the source and drain electrode layers 408a and 408b are An insulating layer 412 is formed to cover b (see FIG. 15C).

[0237] The insulating layer 412 is formed by sputtering, CVD, or the like, to prevent impurities such as water and hydrogen from being introduced into the insulating layer 412. The insulating layer 412 can be formed by using a method that does not mix substances. Then, hydrogen penetrates into the oxide semiconductor layer 406a, and the back surface of the oxide semiconductor layer 406a is heated. The channel becomes low resistance (N-type) and a parasitic channel is formed. 412, it is important not to use hydrogen in the film formation method so that the film contains as little hydrogen as possible. It is essential.

[0238] The insulating layer 412 may be made of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or titanium oxide. It is preferable to form the insulating film so as to contain palladium or the like. In particular, it is preferable to form the insulating film by using a sputtering method. Note that the insulating layer 412 may have a single layer structure or a stacked layer structure. The thickness of the insulating layer 412 is not particularly limited, but may be, for example, 10 nm or more and 500 nm or less. The thickness can be set to 50 nm or less, preferably 50 nm or more and 200 nm or less.

[0239] Next, the oxide semiconductor layer 406a is subjected to a first treatment under an inert gas atmosphere or an oxygen atmosphere. The second heat treatment is preferably performed to remove the oxide semiconductor layer. By supplying oxygen to the oxygen vacancies in 406a, an i-type (intrinsic semiconductor) or an oxide as close to i-type as possible is formed. Furthermore, by performing the second heat treatment, a transistor semiconductor layer can be formed. The temperature of the second heat treatment is 200 The second heat treatment is performed at a temperature of from 250°C to 450°C, preferably from 250°C to 350°C. For example, heat treatment can be performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0240] Through the above steps, the transistor 450 can be formed.

[0241] An insulating layer 418 may be further formed on the insulating layer 412. The insulating layer 418 is resistant to moisture and Hydrogen ions and OH - It does not contain impurities such as these, and blocks them from entering from the outside. It is preferable to use an inorganic insulating material having such properties, for example, a silicon nitride film, an aluminum nitride film, A silicon nitride oxide film, an aluminum oxynitride film, or the like is used. The silicon nitride film is formed using the RF sputtering method. Therefore, this is a preferable method for forming the insulating layer 418 (see FIG. 15D).

[0242] Note that the oxide semiconductor layer 406a may vary depending on the conditions of the first heat treatment and the second heat treatment or the material of the oxide semiconductor layer 406a. That is, part of the oxide semiconductor layer 406a is crystallized, and microcrystals are formed in the oxide semiconductor layer 406a. In this way, the oxide semiconductor layer 406a may be formed as a non-crystalline oxide semiconductor layer. By using a structure having a crystalline region, it is possible to obtain a transistor with higher field effect mobility and on-current. In addition, when the oxide semiconductor layer 406a has an amorphous structure, a plurality of This can reduce variations in characteristics between elements.

[0243] By performing the above-described first heat treatment, hydrogen contained in the oxide semiconductor layer 406 is reduced. Preferably, hydrogen contained in the oxide semiconductor layer 406 is removed, and the oxide semiconductor layer 40 It is possible to highly purify the material so that it contains as few impurities as possible other than the main component of 6. In this case, the defect level formed by excess hydrogen atoms can be reduced. The hydrogen concentration in the semiconductor layer 406 is 5×1019 (atoms / cm 3 ) or less is preferable. In addition, the carrier density of the oxide semiconductor layer 406 is 1×10 14 cm -3 Less than 1x, preferably 10 12 cm -3 less than 1.45 × 10 10 cm -3 Less than is preferred. That is, the carrier density of the oxide semiconductor layer 406 is close to zero. The gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

[0244] When such a highly purified oxide semiconductor layer 406 is used for a channel formation region, The off-current of the transistor can be reduced. The off-current is determined by direct or indirect recombination. The oxide semiconductor layer has a wide band gap, so the flow is due to the generation and recombination of holes and electrons. However, since a large amount of thermal energy is required for electron excitation, direct and indirect recombination In the off state, the number of holes, which are minority carriers, is essentially zero, so Direct recombination and indirect recombination are unlikely to occur, and the off-state current can be reduced to an unlimited extent. The transistor has excellent characteristics, reducing the on-state current and improving the on-state current and field-effect mobility. It becomes a transistor.

[0245] As described above, the highly purified oxide semiconductor layer functions as a path, and carriers The electron affinity χ of the oxide semiconductor and the Fermi level, ideally the Fermi level coincides with the intrinsic Fermi level, and the source and drain By appropriately selecting the work function of the electrode and the oxide semiconductor layer, the carrier density of the oxide semiconductor layer can be reduced. In addition, it becomes possible to inject carriers from the source electrode and the drain electrode, and an n-type transistor A p-type transistor and a p-type transistor can be fabricated appropriately.

[0246] Furthermore, the intrinsic carrier density of a highly purified oxide semiconductor is extremely high compared to that of silicon. The intrinsic carrier density of silicon and oxide semiconductors is Fermi-Dirac distribution and It can be calculated from the approximate formula of the Boltzmann distribution, and the intrinsic carrier density of silicon, n i is 1.45 x 10 10 cm -3 , oxide semiconductor (here, In-Ga-Zn-O layer) Intrinsic carrier density n i is 1.2 x 10 -7 cm -3 The former is a more intrinsic carrier than the latter. Density is 10 17 times larger. That is, the intrinsic carrier density of oxide semiconductors is is found to be extremely low.

[0247] In this embodiment mode, a case where a thin film transistor having a bottom gate structure is manufactured will be described. However, one embodiment of the present invention is not limited to this, and a thin film transistor having a top gate structure may be fabricated. You can also do this.

[0248] <Motoring mechanism of transistors using oxide semiconductors> Next, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 23 to 26. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of them necessarily reflect the actual situation. Please note that this is merely speculation.

[0249] Figure 23 shows a cross section of an inverted staggered transistor (thin film transistor) using an oxide semiconductor. FIG. 1 is a cross-sectional view of a gate electrode layer (GE) on which an oxide semiconductor layer ( On the OS, a source electrode layer (S) and a drain electrode layer (D) are provided. There are.

[0250] 24(A) and 24(B) show energy band diagrams ( Figure 24(A) shows the case where the potential difference between the source and drain is zero (equipotential, V D = 24(B) shows the case where the drain potential is set higher than the source potential. In case (V D >0).

[0251] 25(A) and 25(B) show the energy balance in the cross section taken along the line B-B' in FIG. FIG. 25(A) shows a gate diagram (schematic diagram). G ) is given This indicates the on-state where carriers (electrons) flow between the source and drain. Also, in FIG. 25(B), a negative potential (-V G ) was applied 10 shows the case where the transistor is in the OFF state (state where minority carriers do not flow).

[0252] Figure 26 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0253] Since electrons in metals are degenerate, the Fermi level is located within the conduction band. The compound semiconductor is n-type, and its Fermi level (E f ) is located in the center of the band gap Intrinsic Fermi level (E i) and is located closer to the conduction band. It is known that hydrogen is a donor and one of the factors that causes n-type formation. It is known that element deficiency is also a factor in causing n-type mutations.

[0254] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying the material so that it is not susceptible to oxygen deficiency, it is made into an intrinsic (i-type) material, or by removing the oxygen deficiency, it is made into an intrinsic (i-type) material. In other words, instead of adding impurity elements to make it i-type, By removing impurities such as hydrogen and water and oxygen vacancies as much as possible, highly purified i-type (intrinsic) This allows the Fermi level (E f ) is the intrinsic Fermi level (E i ) can be made to the same extent as

[0255] The band gap (E g ) is 3.15 eV, the electron affinity (χ) is The work of titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, the metal-oxide semiconductor At the interface, no Schottky-type barrier is formed for electrons.

[0256] That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the surface, an energy band diagram (schematic diagram) such as that shown in FIG. 24(A) is displayed.

[0257] In Figure 24(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, then flow toward the drain. The height of (h) changes depending on the gate voltage and drain voltage. When a voltage is applied, the barrier height in Figure 24(A) without voltage application, i.e., the band gap Top (E g ) or lower.

[0258] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. They move near the interface with the body (the lowest energetically stable part of the oxide semiconductor).

[0259] Also, as shown in FIG. 25(B), a negative potential (reverse bias) is applied to the gate electrode (GE1). Therefore, the number of holes, which are minority carriers, is essentially zero, so the current approaches zero. The value is close to

[0260] For example, if the channel width W of a thin-film transistor is 1×10 4 μm and a channel length of 3 μm Even if the off-state current is 10 -13 A or less, and the subthreshold A switching value (S value) of 0.1 V / dec. (gate insulating layer thickness 100 nm) was obtained.

[0261] In this way, it is possible to purify the oxide semiconductor to the extent possible so that it does not contain impurities other than the main component. This allows the thin film transistor to operate satisfactorily. The off-state current is 1×10 -20 A (10zA (zeptoamperes)) to 1 x 10 -19 It is possible to reduce it to about A (100zA).

[0262] The oxide semiconductor described above is designed to prevent fluctuations in electrical characteristics by preventing hydrogen, moisture, Impurities such as hydroxyl groups or hydrides (also called hydrogen compounds) are intentionally excluded, and Oxygen, the main component of oxide semiconductors, is also reduced during the removal process. By supplying the oxide semiconductor, it is possible to obtain a highly purified and electrically i-type (intrinsic) oxide semiconductor. do.

[0263] Therefore, the less hydrogen there is in the oxide semiconductor, the better. The concentration is 5 x 10 19 (atoms / cm 3 ) below, hydrogen contained in oxide semiconductor The hydrogen concentration in the oxide semiconductor is measured using the secondary ion mass spectrometry (SIM) method. Analysis method (SIMS: Secondary Ion Mass Spectroscopy ) can be used.

[0264] In addition, there are very few carriers (close to zero) in highly purified oxide semiconductors. Rear density is 1x10 12 cm -3 less than 1.45 x 10 10 cm -3 Less than That is, the carrier density of the oxide semiconductor layer is made close to zero. Because there are very few carriers, the off-current can be reduced in thin film transistors. The smaller the off-current, the better. The current value per 1 μm is 100 aA (i.e., 100 aA / μm) or less, preferably 1 0 aA (i.e., 10 aA / μm) or less, more preferably 1 aA (i.e., 1 aA / μm) or less Furthermore, since there is no pn junction and no hot carrier degradation, The electrical properties of the film transistor are not affected.

[0265] In this way, the oxide semiconductor layer is highly purified by thoroughly removing hydrogen contained in the oxide semiconductor layer. A thin film transistor using the oxide semiconductor layer in a channel formation region of the thin film transistor is The off-state current can be made extremely small. In this case, the oxide semiconductor layer can be regarded as an insulator when designing a circuit. The semiconductor layer is a semiconductor layer formed of amorphous silicon when the thin film transistor is in a conductive state. It is possible to expect a higher current supply capacity than the body layer.

[0266] In addition, thin film transistors having low-temperature polysilicon are manufactured using oxide semiconductors. The off-state current is estimated to be about 10,000 times larger than that of the thin-film transistors Therefore, in thin film transistors with oxide semiconductors, low-temperature poly Compared to thin film transistors with silicon, the storage capacitance is equivalent (about 0.1 pF). When applying voltage, the voltage retention period can be extended by approximately 10,000 times. When displaying at 60 frames per second, the retention period for one signal write is increased by 10,000 times. Even with a small number of image signal writes, the display It is possible to display still images in the display area.

[0267] The transistor described in this embodiment may be used in the semiconductor device described in any of Embodiments 1 to 3. By applying this, the driving capability of the semiconductor device can be improved.

[0268] (Embodiment 6) In this embodiment, an example of a display device will be described.

[0269] FIG. 18A shows an example of a display device. The display device shown in FIG. 18A includes a circuit 5361 , a circuit 5362, a circuit 5363_1, a circuit 5363_2, and a pixel portion 5364. In the pixel portion 5364, a plurality of wirings 5371 are arranged extending from the circuit 5362. A plurality of wirings 5372 are arranged extending from the circuit 5363_1 and the circuit 5363_2. In the intersecting regions of the plurality of wirings 5371 and the plurality of wirings 5372, The elements 5367 are arranged in a matrix.

[0270] The circuit 5361 is a timing chart in which the circuit 5362, the circuit 5363_1, and the circuit 5363_2 operate. For this purpose, the circuit 5361 has a function of controlling the timing of the video signal 53 60, a signal, a voltage or For example, the circuit 5361 supplies a current to the circuit 5362. start signal (SSP), clock signal for source driver circuit (SCK), Inverted clock signal for driver circuit (SCKB), data for video signal (DATA), latch signal The circuit 5361 supplies a signal (LAT). A start signal (GSP) for the gate driver circuit is input to the line 5363_2. The clock signal (GCK) for the gate driver circuit and the inverted clock signal (GCKB) for the gate driver circuit are Thus, the circuit 5361 includes a controller, a control circuit, a timing It is assumed to have the function of a generator, power supply circuit, regulator, etc.

[0271] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB) supplied from the circuit 5361. , DATA, LAT) to output video signals to multiple wirings 5371. In other words, the circuit 5362 has a function as a source driver circuit. Let's say.

[0272] The circuit 5363_1 and the circuit 5363_2 receive the signal (GSP, GCK, GCKB) to output gate signals to multiple wirings 5372. That is, the circuit 5363_1 and the circuit 5363_2 are gate driver circuits. It is possible to function as such.

[0273] Note that in the display device illustrated in FIG. 18A, the circuit 5363_1 and the circuit 5363_2 Since the same signal is supplied, the circuit 5363_1 and the circuit 5363_2 are roughly equivalent. In many cases, gate signals are output to multiple wirings 5372 at the same timing. The loads of the circuits 5363_1 and 5363_2 can be reduced. An example of the embodiment is not limited to this. For example, as shown in FIG. 18(B), Separate signals can be input to the circuits 5363_1 and 5363_2. As a result, the circuit 5363_1 controls some (for example, odd-numbered rows) of the plurality of wirings 5372, and Another part of the wiring 5372 (for example, the even-numbered rows) can be controlled by a circuit 5363_2. Therefore, the driving frequencies of the circuits 5363_1 and 5363_2 can be reduced. do.

[0274] As shown in FIG. 18B, the display device includes a circuit 5365 and a lighting device 5366. The circuit 5365 receives the backlight control signal from the circuit 5361. The amount of power or time to be supplied to the lighting device 5366 is controlled in accordance with the signal (BLC). This allows the brightness (or average brightness) of the lighting device 5366 to be displayed. Therefore, the backlight area control can be performed. Alternatively, when the image is dark overall, the brightness of the lighting device 5366 can be reduced. If the image is bright overall, the brightness of the illumination device 5366 can be increased. In this way, the contrast ratio can be improved or power consumption can be reduced.

[0275] The plurality of wirings 5371 and the plurality of wirings 5372 function as signal lines. In particular, the plurality of wirings 5371 are used as source signal lines (also called video signal lines). In particular, the plurality of wirings 5372 are gate signal lines (scanning signal lines or The signal line functions as a select signal line.

[0276] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted. In this case, a circuit having the same function as the circuit 5363_1 and the circuit 5363_2 is newly provided. It is possible to do this.

[0277] The pixel portion 5364 is provided with one or more wirings (for example, , capacitance lines, power supply lines, gate signal lines and / or source signal lines) can be arranged. In such a case, a circuit for controlling the potential of the newly provided wiring is also newly provided. In particular, when a liquid crystal element or an electrophoretic element is used as the display element, It is preferable to provide a capacitance line in the pixel portion 5364. In particular, an EL element is used as a display element. When using the LCD panel, it is preferable to provide a power source in the pixel portion 5364 .

[0278] Next, the display device shown in FIG. 18A includes a circuit 5362, a circuit The pixel portion 5364 and the circuit 5363_1 are formed on the same substrate 5380. The circuit 5361 of the display device shown in FIG. It may be formed on a substrate separate from 64.

[0279] Note that the display device shown in FIG. 18A includes a circuit 5361 and a circuit The path 5362 can be formed on a substrate separate from the pixel portion 5364. The driving frequencies of the circuits 5361 and 5362 are as follows: , the circuit 5361 and the circuit 5362 are often low, so the circuit 5363_1 and the circuit 5363_2 It is preferable that the circuit 5361 and the circuit 536 are formed on a substrate different from that of the circuit 536. Since the driving frequency of the display device 2 can be increased, the display device can be made larger. The circuit 5363_1 and the circuit 5363_2 can be formed on the same substrate as the pixel portion 5364. Therefore, the display device can be manufactured at low cost.

[0280] Note that the display device shown in FIG. 18A includes a circuit 5362a (circuit A circuit 5361 and a part of the circuit 5362 are formed on the same substrate as the pixel portion 5364. 62b (another part of the circuit 5362) may be formed on a substrate different from that of the pixel portion 5364. The circuit 5362a may include a switch, a shift register, and / or a selector. Therefore, it is possible to use a circuit with a relatively low driving frequency. Since the driving frequency of the circuit 5362b can be increased, the display device can be made larger. Alternatively, the circuit 5362a, the circuit 5363_1, and the circuit 5363_2 can be Since it can be formed on the same substrate as the display device 64, the display device can be manufactured at low cost.

[0281] Note that the display device shown in FIG. 18A includes a circuit 5361a (circuit A circuit 5361b (part of the circuit 5361) is formed on the same substrate as the pixel section 5364, and 61) can be formed on a substrate different from that of the pixel portion 5364.

[0282] Note that a circuit (also called an external circuit) formed on a substrate other than the pixel portion 5364 is A signal, a voltage, and a signal are input to a circuit or wiring formed on the same substrate as the pixel portion 5364 via 5381. , or current, etc.

[0283] The external circuit uses the TAB (Tape Automated Bonding) method. It can be mounted on an FPC (Flexible Printed Circuit). Alternatively, the external circuit may be implemented using the COG (Chip on Glass) method. This allows the pixel portion 5364 to be mounted on the same substrate 5380 .

[0284] It is preferable that the external circuit be formed on a single crystal substrate or an SOI substrate. This will improve the drive frequency, drive voltage, or reduce the variation in the output signal. can be done.

[0285] The display device of this embodiment is formed by applying the semiconductor devices shown in the first to fourth embodiments. In particular, the circuits 5362 and 5363 can be implemented by the circuits described in Embodiments 1 to 3. The semiconductor device described in Embodiment 4 can be used. The driving capability of the circuits (for example, the circuit 5362 and the circuit 5363) can be improved. Therefore, the pixel resolution can be improved. It is possible.

[0286] In this specification and the like, the term "display element," "display device having a display element," "light-emitting ... A light-emitting device, which is a device having a light-emitting element, can be formed in various forms or can be formed from various elements. Examples of the display element, the display device, the light-emitting element, or the light-emitting device include: EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements) LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) , transistors (transistors that emit light according to current), electron-emitting devices, liquid crystal devices, electrons Ink, electrophoretic element, grating light valve (GLV), plasma display Panel (PDP), Digital Micromirror Device (DMD), Piezoelectric Ceramic Disk The contrast, brightness, reflectivity, transmittance, etc. change due to electromagnetic effects such as play. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting devices is a field emission display. Flat panel display (FED) or SED (Surface Emitting Diode) type e-conduction Electron-emitter Display) An example of a display device using a liquid crystal element is a liquid crystal display (transmission type liquid crystal display). Play, Transflective LCD, Reflective LCD, Direct View LCD Display devices using electronic ink or electrophoretic elements include: An example of such a display is electronic paper.

[0287] An example of an EL element is a device having an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. An example of an EL layer is a device that uses light emission (fluorescence) from singlet excitons. those that utilize emission from triplet excitons (phosphorescence), and those that utilize emission from singlet excitons (fluorescence). those that utilize light (photoluminescence) and those that utilize light emission from triplet excitons (phosphorescence), Those formed by organic matter, those formed by inorganic matter, and those formed by organic matter those made of inorganic materials, those made of polymeric materials, and those made of low molecular weight materials. or those containing high molecular weight materials and low molecular weight materials. However, the present invention is not limited to this, and various EL elements can be used.

[0288] An example of a liquid crystal element is a liquid crystal display element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed from a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is achieved by the electric field (horizontal electric field, vertical electric field or oblique electric field) applied to the liquid crystal. Specifically, an example of a liquid crystal element is , nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, Motropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal ( PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma ad The LCD driving method is also The following are the modes: TN (Twisted Nematic) and STN (Super Twisted Nematic) sted nematic mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (M ulti-domain Vertical Alignment) mode, PVA(P atterned Vertical Alignment) mode, ASV (Adva nced Super View) mode, ASM (Axially Symmetry c aligned micro-cell) mode, OCB (Optically C compensated birefringence mode, ECB (Electro Cally Controlled Birefringence mode, FLC (F erroelectric Liquid Crystal) mode, AFLC (Ant iFerroelectric Liquid Crystal mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest There are various modes, such as the Black mode and the Blue Phase mode. However, these are not limited to these. In addition, various liquid crystal elements and driving methods thereof can be used.

[0289] One example of a display method for electronic paper is a method using molecules (optical anisotropy) , dye molecule orientation, etc.), those displayed by particles (electrophoresis, particle migration, particle rotation, phase Changes in color, etc.), those displayed by moving one edge of the film, color / phase changes of molecules Some are indicated by the absorption of light by molecules, while others are indicated by the combination of electrons and holes. Specifically, electronic paper can be used. Examples of display methods include microcapsule electrophoresis, horizontal migration electrophoresis, and vertical migration electrophoresis. Type electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, electrification Toner, electronic liquid powder (registered trademark), magnetophoretic type, magnetic thermal type, electrowetting , light scattering (transparent / cloudy change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bilayer Stable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, leucocyte Color development and fading by dyes, photochromic, electrochromic, electrodeposition , flexible organic EL, etc. However, it is not limited to these, and electronic paper and its Various display methods can be used. Here, the display method of electronic paper is By using microcapsule electrophoresis, the drawback of the electrophoretic method is that the electrophoretic particles It can solve the problem of particle aggregation and precipitation. It can also be used as an electronic paper display method. By using the EL display panel (registered trademark), high speed response, high reflectivity, wide viewing angle, low power consumption, It has merits such as memory properties.

[0290] In addition, display devices that require a light source, such as liquid crystal displays (transmissive liquid crystal displays), , Transflective LCD, Reflective LCD, Direct-view LCD, Projection LCDs, display devices using grating light valves (GLVs), digital An example of a light source for a display device using a digital micromirror device (DMD) is an Electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. However, it is not limited to this, and various light sources can be used. can be done.

[0291] In this specification and the like, it is possible to form a transistor using various substrates. The type of substrate is not limited to a specific one. Examples include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, and glass substrates. Plate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate, stainless steel Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, possible Examples include flexible substrates, laminated films, paper containing fibrous materials, or base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and Examples of flexible substrates include soda lime glass. Polyethylene naphthalate (PET), Polyethersulfone (PE Examples include plastics such as acrylic, or flexible synthetic resins such as acrylic. Examples of laminated films include polypropylene, polyester, vinyl, and polyfluorine. Examples of the base film include polyester, polyvinyl chloride, and vinyl chloride. In particular, semiconductor substrates, single layer By manufacturing transistors using crystalline substrates or SOI substrates, Small size transistor with little variation in size or shape, high current capacity When a circuit is constructed using such transistors, the circuit can be This allows for reduced power consumption or higher circuit integration.

[0292] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. As the substrate, in addition to the substrate on which the above-mentioned transistor can be formed, a paper substrate, a cellophane substrate, etc. substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, Polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled These substrates include raw polyester, leather substrates, and rubber substrates. This allows for the formation of transistors with good characteristics and low power consumption. This allows for the manufacture of devices that are less likely to break, more heat resistant, lighter in weight, or thinner.

[0293] All of the circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc. do.

[0294] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function is formed on a certain substrate. Another part of the circuitry required to achieve a given function is formed on a different substrate. For example, some of the circuits required to realize a specific function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuit required for the semiconductor device is formed is called COG ( By using the IC chip on glass, the IC is connected to the glass substrate. It is possible to place the chip on the board. Alternatively, the IC chip can be mounted on the board using TAB (Tape Auto) technology. omated Bonding), COF(Chip On Film), SMT(Su Surface Mount Technology, or a printed circuit board, etc. It is possible to connect it to the base board.

[0295] Note that transistors constituting the driver circuits (for example, the circuit 5362 and the circuit 5363), and / or the transistor described in Embodiment 5 as a transistor included in the pixel portion 5354. can be used.

[0296] (Embodiment 7) In this embodiment, an example of a pixel and a method of driving the pixel will be described. An example of a pixel including a display element having such a property and an example of a method for driving the pixel will be described below.

[0297] 20A shows an example of a circuit diagram of a pixel. The pixel 5450 includes a transistor 5451, The transistor 5451 includes a capacitor 5452 and a display element 5453. , and the wiring 5461. The second terminal of the transistor 5451 is connected to the capacitor 5452. One electrode of the display element 5453 is connected to one electrode (also called a pixel electrode) of the display element 5453. The gate of the transistor 5451 is connected to a wiring 5462. The electrode is connected to a wiring 5463. The other electrode of the display element 5453 is connected to an electrode 5454 ( It is connected to a common electrode, a counter electrode, or a cathode electrode.

[0298] Note that one electrode of the display element 5453 is shown as an electrode 5455 .

[0299] The display element 5453 preferably has a memory property. The driving method is microcapsule type electrophoresis method, microcup type electrophoresis method. , horizontal movement electrophoresis method, vertical movement electrophoresis method, twist ball method, powder movement method formula, electronic liquid powder (registered trademark) method, cholesteric liquid crystal element, chiral nematic liquid crystal, Antiferroelectric liquid crystal, polymer dispersed liquid crystal, charged toner, electrowetting method, electro There are methods such as electrochromism and electrodeposition.

[0300] Figure 20(B) shows a cross-sectional view of a pixel using a microcapsule-type electrophoretic method. A plurality of microcapsules 5480 are disposed between 5454 and the electrode 5455. The microcapsules 5480 are fixed by a resin 5481. The resin 5481 is The resin 5481 preferably has a light-transmitting property. The space formed by the electrode 5455 and the microcapsule 5480 contains air or The electrode 5454 and the electrode 5455 may be filled with a gas such as an inert gas. or forming a layer containing an adhesive or the like on both surfaces to fix the microcapsules 5480. It is also possible.

[0301] The microcapsule 5480 comprises a membrane 5482, a liquid 5483, particles 5484, and particles 5485. The liquid 5483, the particles 5484, and the particles 5485 are arranged in the film 5482. The film 5482 is transparent. The liquid 5483 is a dispersion liquid. The liquid 5483 separates the particles 5484 and 5485 into the membrane 5482. It is preferable that the liquid 5483 is transparent and colorless. The particles 5484 and 5485 are different colors. One of the particles 5485 is black, and the other of the particles 5484 and 5485 is white. The particles 5484 and the particles 5485 are charged so that their charge densities are different from each other. For example, one of the particles 5484 and 5485 is positively charged, and the other of the particles 5484 and 5485 is positively charged. The other of the electrodes 5454 and 5485 is negatively charged. When a potential difference occurs between the particles 5484 and 5485, the particles 5484 and 5485 move according to the direction of the electric field. In this way, the reflectance of the display element 5453 changes, thereby controlling the gradation. However, the structure of the microcapsules 5480 is not limited to the above. For example, the liquid 5483 can be colored. The particles enclosed therein can be one type, or three or more types. As another example, the particles 5484 and the particles 5485 may be colored in more than just white and black. Red, green, blue, cyan, magenta, yellow, emerald green, vermilion, etc. It is possible to select from.

[0302] The film 5482 is made of a light-transmitting material (for example, acrylic resin (for example, polymethacrylic polymer resins such as urea resin or gum arabic, The membrane 5482 is preferably gelatinous. This provides flexibility, It is possible to improve bending strength and mechanical strength, which improves flexibility. Alternatively, the microcapsules 5480 can be uniformly distributed without gaps in the film. The substrate may be arranged on a substrate such as

[0303] As the liquid 5483, it is preferable to use a light-transmitting oily liquid. 483, alcohol-based solvents (e.g., methanol, ethanol, isopropanol) , butanol, octanol or methyl cellosolve, etc.), esters (e.g., ethyl acetate or butyl acetate, etc.), aliphatic hydrocarbons (e.g., acetone, methyl ethyl ketone, methyl Ketones such as isobutyl ketone, pentane, hexane, or octane, alicyclic hydrocarbons (e.g., cyclohexane or methylcyclohexane), a phenyl group having a long chain alkyl group, Aromatic hydrocarbons such as benzenes (e.g., benzene, toluene, xylene, hexylbenzene) , butylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene benzene, dodecylbenzene, tridecylbenzene or tetradecylbenzene, etc.), halo chlorinated hydrocarbons (e.g., methylene chloride, chloroform, carbon tetrachloride, or dichloroethane) (e.g., carboxylic acid salts, water, or other oils). or a mixture of at least two of these materials or A mixture of at least two or more substances may also contain surfactants.

[0304] The particles 5484 and 5485 are each made of a pigment. The pigments that make up 5485 are preferably different colors. 4 is preferably made of a black pigment, and particles 5485 are preferably made of a white pigment. Black pigments include aniline black and carbon black. White pigments Examples of such antimony oxides include titanium dioxide, zinc oxide (zinc oxide), and antimony trioxide. These pigments contain charge control agents (e.g., electrolytes, surfactants, metal soaps, resins, rubbers, oils, , varnish or compound, etc.), dispersing agents (e.g. titanium-based coupling agents, aluminum Addition of a rubber-based coupling agent or a silane-based coupling agent, a lubricant or a stabilizer It is possible to do this.

[0305] FIG. 21A shows an image in the case where a twist ball method is used as the method of the display element 5453. The twist ball method changes the reflectance by rotating the display element. The difference from FIG. 20(B) is that the electrode 5454 and the electrode 5455 In place of the microcapsules 5480, twist balls 5486 are placed between them. The twist ball 5486 is formed around the particle 5487. The particles 5487 are each composed of a hemispherical surface and a cavity 5488. The particle 5487 is a spherical particle painted in a certain color and a different color. The hemispheres are painted white and black. Therefore, a potential difference is generated between the electrode 5454 and the electrode 5455. By rotating the particle 5487, the particle 5487 can be rotated according to the direction of the electric field. The tee 5488 is filled with a liquid. The liquid is the same as the liquid 5483. However, the twist ball 5486 is not limited to the structure shown in FIG. For example, the structure of the twist ball 5486 can be cylindrical or elliptical, etc. be.

[0306] FIG. 21B shows a display element 5453 using a microcup type electrophoresis method. The microcup array is made of UV-curable resin and has multiple A microcup 5491 having a recess is filled with charged pigment particles dispersed in a dielectric solvent 5492. The sealing layer 5494 is then formed by filling the cavity 5493 with the resin and sealing it with the sealing layer 5494. An adhesive layer 5495 may be formed between the dielectric solvent 5492 and the electrode 5455. For this purpose, it is possible to use a non-colored solvent, or a colored solvent such as red or blue. Although the illustration shows a case where there is one type of charged pigment particles, it is also possible to use two types of charged pigment particles. The microcups have a wall structure that separates the cells, so they are resistant to shocks and The contents of the microcups are sealed, so they can withstand pressure. The effects of environmental changes can be reduced.

[0307] FIG. 21C shows a display element 5453 using an electronic liquid powder (registered trademark) method. The cross section of the pixel in this case is shown. Electronic Liquid Powder (registered trademark) exhibits fluidity and has the properties of fluid and particles. In this method, the cells are separated by partition walls 5504, and electronic powder is placed inside the cells. Fluid (registered trademark) 5502 and electronic liquid powder (registered trademark) 5503 are placed. (registered trademark) 5502 and electronic liquid powder (registered trademark) 5503, which are white particles and black particles However, Electronic Liquid Powder (registered trademark) 5502 and Electronic Liquid Powder (registered trademark) The type of the liquid powder 5503 is not limited to this. For example, the liquid powder 5502 and For the electronic liquid powder (registered trademark) 5503, colored particles of two colors other than white and black are used. As another example, Electronic Liquid Powder (registered trademark) 5502 and Electronic Liquid Powder (registered trademark) It is possible to omit either the mark 5503 or the mark 5504.

[0308] A signal is input to the wiring 5461. In particular, the wiring 5461 is connected to the display element 5 A signal (for example, a video signal) for controlling the gradation of 453 is input. In this way, the wiring 5461 is a signal line or a source signal line (also called a video signal line or a source line). A signal is input to the wiring 5462. In particular, the wiring 5462 is connected to a signal (for example, For example, gate signals, scanning signals, selection signals, etc. are input. 462 functions as a signal line or gate signal line (also called a scanning signal line or gate line). A constant voltage is supplied to the wiring 5463. 3 is connected to the capacitor 5452. Therefore, the wiring 5463 is a power supply line or a capacitor. A constant voltage is supplied to the electrode 5454. The electrode 5454 is often common to a plurality of pixels or all pixels. Therefore, the electrode 5454 is a common electrode (also called a counter electrode or a cathode electrode). It shall have the function of (hereinafter referred to as)

[0309] Note that signals input to the wiring 5461, the wiring 5462, the wiring 5463, and the electrode 5454 The voltage is not limited to the above, and various other signals or voltages may be input. For example, a signal can be input to the wiring 5463. Therefore, the potential of the electrode 5455 can be controlled. Therefore, the wiring 5463 can function as a signal line. As another example, the voltage supplied to the electrode 5454 may be changed. This allows the voltage applied to the display element 5453 to be adjusted. The amplitude voltage of the signal input to the line 5461 can be reduced.

[0310] The transistor 5451 has a function of controlling the conduction state between the wiring 5461 and the electrode 5455. Alternatively, the transistor 5451 supplies the potential of the wiring 5461 to the electrode 5455. Alternatively, the transistor 5451 has a function of controlling the timing of supplying the pixel 54 50. In this way, the transistor 5451 The transistor functions as a switch or a selection transistor. The transistor 5451 is an N-channel type. When an H signal is input to wire 5462, it turns on, and when an L signal is input to wire 5463, it turns off. However, the polarity of the transistor 5451 is not limited to an N-channel type. Transistor 5451 can be a P-channel type. 451 turns on when an L signal is input to wiring 5462, and turns on when an H signal is input to wiring 5462. The capacitor 5452 is connected to an electrode 5455 and a wiring 5463. Alternatively, the capacitor 5452 has a function of holding a potential difference between the electrode 5455 and the This function keeps the potential at a predetermined value, so that the transistor 5451 is turned off. Even if the voltage is applied to the display element 5453, the voltage can be continuously applied to the display element 5453. The transistor 5451 and the transistor 452 function as a storage capacitor. The functions of the capacitor element 5452 are not limited to those described above, and they may have various other functions. It is possible to do this.

[0311] Next, an outline of the operation of the pixel of this embodiment will be described. The control is performed by applying a voltage to the display element 5453 to generate an electric field in the display element 5453. The voltage applied to the display element 5453 is controlled by the potential of the electrode 5454 and the This is done by controlling the potential of the electrode 5455. Specifically, the control of the potential of the electrode 5454 This is done by controlling the voltage supplied to the electrode 5454. The control is performed by controlling a signal input to the wiring 5461. The signal input to 61 is input to the electrode 5455 by turning on the transistor 5451. are supplied to.

[0312] The strength of the electric field applied to the display element 5453, the direction of the electric field applied to the display element 5453, the display The gray scale of the display element 5453 can be controlled by controlling the time for which an electric field is applied to the display element 5453. It should be noted that no potential difference is generated between the electrode 5454 and the electrode 5455. This allows the gray scale of the display element 5453 to be maintained.

[0313] Next, an example of the operation of the pixel of this embodiment will be described. The diagram shows a period T having a selected period and a non-selected period. This refers to the period between the start time of one selected period and the start time of the next selected period.

[0314] During the selection period, an H signal is input to the wiring 5462, so that the potential of the wiring 5462 (potential V5 462) becomes H level. Therefore, the transistor 5451 is turned on. The wiring 5461 and the electrode 5455 are electrically connected. The signal is supplied to the electrode 5455 via the transistor 5451. The potential of 5455 (shown as potential V5455) is equal to the value of the signal input to the wiring 5461. At this time, the capacitor 5452 has a potential difference between the electrode 5455 and the wiring 5463. During the non-selection period, an L signal is input to the wiring 5462, so that Therefore, the transistor 5451 is turned off, and the potential of the wiring 54 61 and the electrode 5455 are in a non-conductive state. Then, the electrode 5455 is in a floating state. In this case, the capacitor 5452 is connected between the electrode 5455 and the wiring 5463 during the selection period. Therefore, the potential of the electrode 5455 is maintained at the same level as the potential of the wiring 546 during the selection period. The value of the signal input to the transistor 1 remains the same as that of the signal input to the transistor 1. Even when the starter 5451 is turned off, a voltage can continue to be applied to the display element 5453. As described above, by controlling the signal input to the wiring 5461 during the selection period, The voltage applied to the display element 5453 can be controlled. The gradation is controlled by controlling the signal input to the wiring 5461 during the selection period. It can be done.

[0315] Note that the potential of the electrode 5455 in the non-selection period is determined by the off-state current of the transistor 5451, the Feedthrough of transistor 5451, charge injection of transistor 5451 The signal input to the wiring 5461 during the selection period may differ due to the influence of the do.

[0316] As shown in FIG. 22B, during a part of the selection period, the potential of the electrode 5455 is set to Therefore, the same signal is continuously transmitted to the wiring 5461. Even if the input continues, the potential of the electrode 5455 is changed during a part of the selection period. This allows the electric field strength of the display element 5453 to be changed. Or, the response speed can be increased. Or, the response speed between pixels can be increased. This can reduce variations in the brightness and prevent unevenness or afterimages. To realize this driving method, the selection period may be divided into a period T1 and a period T2. In the period T1, the signal input to the wiring 5461 is set to the same value as that of the electrode 5454. Note that during the period T2, the signal input to the wiring 5461 is It is recommended to use various values ​​to control the gradation of 453. Note that the time period T1 is too long. This reduces the time required to write a signal for controlling the gray level of the display element 5453 to the pixel 5450. Therefore, it is preferable that the period T1 is shorter than the period T2. The period T1 is preferably 1% or more and 20% or less of the selected period. % or more and 15% or less, and more preferably 5% or more and 10% or less.

[0317] Next, the gradation of the display element 5453 is controlled by the time for which a voltage is applied to the display element 5453. An example of the operation of the pixel of this embodiment will be described below. The chart has a period Ta and a period Tb. The period Ta has N (N is a natural number) has a period T. Each of the N periods T is the same as the period T shown in FIGS. 22(A) to (B). The period Ta is a period (e.g., an address period, a writing period, an image rewriting period, etc.) for changing the gradation of the display element 5453. The period Tb is a period (holding period) for holding the gradation of the display element 5453 during the period Ta.

[0318] Assume that a voltage V0 is supplied to the electrode 5454. Therefore, a potential V0 is applied to the electrode 5454. Assume that a signal having at least three values is input to the wiring 5463. The potentials of the three values of the signal are, respectively, a potential VH (VH > V0), [[ID=第十四条]] a potential V0, and a potential VL (VL < V0). Therefore, the potentials VH, V0, and VL are selectively applied to the electrode 5455. [[ENT]]

[0319] During the N periods T included in the period Ta, the voltage applied to the display element 5453 can be controlled by controlling the potential applied to the electrode 5455. For example, when the potential VH is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is VH - VL. Thus, a positive voltage can be applied to the display element 5453. When the potential V0 is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is zero. Thus, a voltage of zero can be applied to the display element 5453. When the potential VL is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is VL - VH. Thus, a negative voltage can be applied to the display element 5453. As described above, during the period Ta, a positive voltage (VH - VL) can be applied to the display element 5453. ​​​​​​​), negative voltage (VL-VH), and zero can be applied in various orders. This allows for fine control of the gradation of the display element 5453. Alternatively, afterimages can be reduced. Or, the response speed can be increased.

[0320] In this embodiment, when a positive voltage is applied to the display element 5453, the display element 545 The third gradation is closer to black (also called the first gradation). When pressure is applied, the gray level of the display element 5453 approaches white (also called the second gray level). When zero voltage is applied to the display element 5453, the gray level of the display element 5453 is maintained. It shall be done.

[0321] During the period Tb, the signal input to the wiring 5461 is not written to the pixel 5450. Therefore, in the period Tb, the voltage applied to the electrode 5455 in the N-th period T of the period Ta is The potential is continuously applied to the electrode 5455. In particular, during the period Tb, the display element 5453 It is preferable that the gray level of the display element 5453 be maintained by not generating an electric field therebetween. For this reason, in the N-th period T of the period Ta, a potential V0 is applied to the electrode 5455. As a result, the potential V0 is applied to the electrode 5455 even during the period Tb. Therefore, a voltage of zero is applied to the display element 5453. The gradation can be maintained.

[0322] Note that the closer the gradation that the display element 5453 next displays to the first gradation, the In this case, it is preferable to lengthen the time during which the potential VH is applied to the electrode 5455. It is preferable to increase the number of times that the potential VH is applied to the electrode 5455. The potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455. Alternatively, it is preferable to make the time period T longer by subtracting the time during which the potential VH is at the electrode 5. The number of times that potential VL is applied to electrode 5455 minus the number of times that potential VL is applied to electrode 5455 is It's better to have more.

[0323] Note that the closer the gradation level that the display element 5453 next displays to the second gradation level, the In this case, it is preferable to increase the time for which the potential VL is applied to the electrode 5455. Alternatively, It is preferable to increase the number of times that the potential VL is applied to the electrode 5455. The potential VL is applied to the electrode 5455, and the potential VH is applied to the electrode 5455. Alternatively, it is preferable to make the time period T longer by subtracting the time during which the potential VL is applied to the electrode 5. The number of times that potential VH is applied to electrode 5455 minus the number of times that potential VH is applied to electrode 5455 is It's better to have more.

[0324] During the period Ta, the potentials (potential VH, potential V0, potential V L) not only depends on the next gray scale that the display element 5453 displays, but also on the display It is possible to depend on the gray level that element 5453 has already displayed. Even if the gray scale displayed by the element 5453 is the same, the gray scale already displayed by the display element 5453 may be Different combinations of potentials may be applied to the electrodes 5455.

[0325] For example, in the period Ta for displaying the gradation already displayed by the display element 5453, The longer the time that the potential VH is applied to the electrode 5455, the The longer the time that the potential VL is applied to the electrode 5455 minus the time that the potential VL is applied to the electrode 5455, the The more times the potential VH is applied to the electrode 5455 during the period T, or the more times the potential VH is applied to the electrode 5455 during the period T, the greater the number of times the potential VH is applied to the electrode 5455 during the period T. T, the number of times that the potential VH is applied to the electrode 5455 is less than the number of times that the potential VL is applied to the electrode 5455. The greater the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 during the period Ta, the greater the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 during the period Ta. Alternatively, the potential VL may be applied to the electrode 5455 during the N periods T. Alternatively, during the period Ta, the potential VL is applied to the electrode 5455. It is preferable to lengthen the time obtained by subtracting the time during which the potential VH is applied to the electrode 5455 from the time during which the potential VH is applied to the electrode 5455. Alternatively, the potential VH is calculated by determining the number of times the potential VL is applied to the electrode 5455 during the N periods T. It is advisable to increase the number of times that the voltage is applied to the electrode 5455 minus the number of times that the voltage is applied to the electrode 5455. can be reduced.

[0326] As another example, the gradation already displayed by the display element 5453 may be changed during the period Ta for display. In this case, the longer the time that the potential VL is applied to the electrode 5455, the longer the potential VL is applied to the electrode 5455. The longer the time that the potential VH is applied to the electrode 5455 minus the time that the potential VH is applied to the electrode 5455, , the more times the potential VL is applied to the electrode 5455 among the N periods T, or After the period T, the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455. The greater the value obtained by subtracting the number of times the potential VH is applied, the greater the potential VH is applied to the electrode 5455 during the period Ta. Alternatively, during the N periods T, the potential VH may be applied to the electrode 5455. Alternatively, during the period Ta, the potential VH is applied to the electrode 5455. If the time that the potential VL is applied to the electrode 5455 is increased, Alternatively, the potential VH may be calculated based on the number of times the potential VH is applied to the electrode 5455 during the N periods T. It is advisable to increase the number of times VL is applied to the electrode 5455 minus the number of times VL is applied to the electrode 5455. The image can be reduced.

[0327] It should be noted that the N periods T are all of equal length. However, the length of the N periods T is For example, at least two of the N periods T are different from each other. In particular, it is advisable to weight the lengths of the N periods T. For example, For example, if N=4, and the length of the first period T is time h, then the length of the second period T is The length of the third period T should be time h × 4. The fourth period T should be time h × 4. The length of the period T should be time h × 8. In this way, the length of the N periods T should be weighted. By performing the above, the number of times that the pixel 5450 is selected can be reduced, and the display element 54 The time for applying voltage to 53 can be precisely controlled. This reduces power consumption. It is possible.

[0328] It is possible to selectively apply a potential VH or a potential VL to the electrode 5454. In this case, it is preferable to selectively apply the potential VH and the potential VL to the electrode 5455 as well. For example, when a potential VH is applied to the electrode 5454, when a potential VH is applied to the electrode 5455, When a potential VL is applied to the electrode 5455, A negative voltage is applied to the display element 5453. On the other hand, a potential VL is applied to the electrode 5454. In this case, when a potential VH is applied to the electrode 5455, a positive voltage is applied to the display element 5453. When a potential VL is applied to the electrode 5455, the display element 5453 has zero voltage. In this way, the signal input to the wiring 5461 is converted into a binary (digital) signal. Therefore, the circuit for outputting a signal to the wiring 5461 can be simplified. Cut.

[0329] Note that during the period Tb or part of the period Tb, the wiring 5461 and the wiring 5462 are connected to a signal line. In other words, it is possible to make the wiring 5461 and the wiring 5462 floating. Note that during the period Tb or part of the period Tb, the wiring 5463 It is possible to input no signal. In other words, it is possible to put the wiring 5463 in a floating state. In addition, during the period Tb or a part of the period Tb, a voltage is supplied to the electrode 5454. That is, the electrode 5454 can be floating.

[0330] The display element having a memory property shown in this embodiment is a normal liquid crystal element (for example, a TN liquid crystal element). A larger voltage needs to be applied compared to a display device with a memory function. As a circuit to be used, the semiconductor device according to any one of the first to fourth embodiments using the transistor according to the fifth embodiment is applied. By using the above, the driving voltage can be increased. The breakdown voltage of the transistor is a-Si TFT (amorphous silicon thin film transistor) or p -This is because it is more expensive than Si TFTs (polycrystalline silicon thin film transistors).

[0331] Furthermore, the transistor described in Embodiment 5 is used in a circuit for driving a display element having a memory function. and a transistor 54 which constitutes a pixel together with a display element having a memory function. The transistor described in Embodiment 5 is preferably used as the transistor 51. Since the off-state current of the transistor 5451 can be reduced, The channel width can be reduced. Alternatively, the area of ​​the capacitor 5452 can be reduced. Therefore, the area of ​​the pixel can be reduced. By providing the pixel in the pixel portion of the display device, the display device can be made high-definition. In addition, a circuit for driving a display element having a memory property and a display device including the display element having a memory property are also provided. The element portion can be easily formed on the same substrate.

[0332] (Embodiment 8) In this embodiment, an example of an electronic device will be described.

[0333] 27(A) to 27(H) and 28(A) to 28(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminal Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), 5008, etc.

[0334] FIG. 27(A) shows a portable terminal, which includes, in addition to the above, a switch 5009, an infrared port, 5010, etc. FIG. 27(B) shows a portable image reproduction device equipped with a recording medium. In addition to the above, the device is a device (for example, a DVD player) that includes a second display unit 5002, It can have a recording medium reading unit 5011, etc. Figure 27(E) is a portable television. In addition to the above, the mobile phone may have an antenna 5014. In addition to the above, it may have a recording medium reading unit 5011, etc. FIG. 27(C) shows a projector, which includes a light source 5033, a projection lens, and the like in addition to the above components. 27(F) is a portable gaming machine, and the above-mentioned In addition, it may have a second display unit 5002, a recording medium reading unit 5011, etc. 27(G) is a television receiver, which in addition to the above-mentioned components, has a tuner, an image processing unit, etc. FIG. 27(H) shows a portable television receiver, which can be used in addition to the above. , a charger 5017 capable of transmitting and receiving signals, etc. In addition to the above, the spray may include a support base 5018, etc. 8(B) is a camera, which, in addition to the above, has an external connection port 5019, a shutter button 28(C) shows a computer In addition to the above, a pointing device 5020, an external connection port 501 9, a reader / writer 5021, etc. FIG. 28(D) shows a mobile phone. In addition to the above, there is an antenna 5014, a one-segment unit for a mobile phone / mobile terminal, tuners for minute reception services, etc.

[0335] The electronic devices shown in FIGS. 27(A) to 27(H) and 28(A) to 28(D) are For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a three-dimensional image. In electronic devices with an image receiving unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to save the captured image to a recording medium (external or camera). It can have functions such as saving the captured image to a built-in memory, displaying the captured image on the display, etc. Note that the electronic devices shown in FIGS. 27(A) to 27(H) and 28(A) to 28(D) The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0336] Next, application examples of the semiconductor device will be described.

[0337] FIG. 28(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0338] FIG. 28(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0339] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0340] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0341] 28G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0342] FIG. 28(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 28(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0343] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc.

[0344] The semiconductor device according to the first to fourth embodiments is mounted on the electronic device according to the present embodiment. In particular, the first to third embodiments are preferably used as a circuit for driving a display unit of an electronic device. It is preferable to mount the semiconductor device of the fourth embodiment. By incorporating the device as a circuit for driving the display unit of an electronic device, the area of ​​the driving circuit can be reduced. The size of the display can be reduced, and the display area can be enlarged. It is possible to aim higher.

[0345] (Embodiment 9) In this embodiment mode, another example of a structure and a manufacturing method of a semiconductor device according to Embodiment 5 will be described. This will be described with reference to FIG. 29. In this embodiment, the differences from the fifth embodiment will be described in detail. The same points as those in the fifth embodiment are to be referred to.

[0346] First, a gate electrode layer 411 is formed on a substrate 400, and then a gate electrode layer 411 is formed on the substrate 400. The gate insulating layer 402 is then formed on the gate insulating layer 402. A conductor layer 404 is formed.

[0347] The first oxide semiconductor layer 404 is a ternary metal oxide, In-M X -Zn Y -O Z ( Y=0.5 to 5), where M is Selected from group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). The content of In, M, Zn, and O is optional. This includes the case where the M content is zero (i.e., x=0). On the other hand, the In and Zn contents are zero. In other words, the above notation does not include In-Ga-Zn-O, In-Zn-O, etc. Included.

[0348] The first oxide semiconductor layer 404 is a tetravalent oxide semiconductor layer similar to the oxide semiconductor layer 406 in Embodiment 5. The In-Sn-Ga-Zn-O system, which is a monometallic oxide, and the In- Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxides. In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn- Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. can be used. It can also be done as follows.

[0349] In this embodiment, the first oxide semiconductor layer 404 is an In—Ga—Zn—O-based oxide semiconductor. The film is formed by sputtering using a conductive target.

[0350] In order to form the first oxide semiconductor layer 404 of In-Ga-Zn-O system by sputtering, For example, a metal oxide target containing zinc oxide as the main component is used as the target. In addition, the composition of the oxide semiconductor target containing In, Ga, and Zn can be The ratio is In:Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). Example: For example, In:Ga:Zn=1:1:1 [atomic ratio] (x=1, y=1) (i.e., I A target with a composition ratio of ZnO:GaO:ZnO=1:1:2 (molar ratio) Alternatively, an oxide semiconductor target such as In:Ga:Zn=1: A target having a composition ratio of 1:0.5 [atom ratio] or In:Ga:Zn=1: 1:2[atom ratio], In:Ga:Zn=1:0:1[atom ratio](x=0, y=1 In this embodiment, a target having a composition ratio of In order to intentionally crystallize the first oxide semiconductor layer 404, It is preferable to use a semiconductor target.

[0351] Next, the first oxide semiconductor layer 404 is subjected to first heat treatment. Also, a region including the surface of the first oxide semiconductor layer 404 is crystallized (see FIG. 29A). In addition, the first oxide semiconductor layer 404 is subjected to first heat treatment, whereby the first oxide Excess water (including hydroxyl groups), hydrogen, etc. in the compound semiconductor layer 404 can be removed. The first heat treatment temperature is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. The duration of the first heat treatment is 1 minute or more and 24 hours or less.

[0352] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a nitrogen atmosphere. After dehydration or dehydrogenation, the atmosphere is switched to an oxygen atmosphere to Oxygen is supplied to the inside of the oxide semiconductor layer 404.

[0353] Regarding other heat treatment conditions, the first heat treatment in the fifth embodiment may be referred to. Detailed explanation will be omitted.

[0354] The first oxide semiconductor layer 404 is subjected to first heat treatment to form a first oxide semiconductor layer. A non-single-crystal region can be formed in a region including at least the surface of the semiconductor layer 404. The non-single-crystal region formed in the region including the surface of the oxide semiconductor layer 404 is The non-single-crystal region is formed by crystal growth toward the The non-single-crystal region is a plate-shaped non-single-crystal layer having a thickness of 10 nm or less. The region has a non-single-crystal layer in which the c-axis is oriented in a direction approximately perpendicular to the surface of the layer 404. Here, "substantially parallel" refers to a state within ±10° from the parallel direction. "Straight" means within ±10° of the vertical direction.

[0355] Next, the second oxide semiconductor layer 405 is formed over the first oxide semiconductor layer 404 (FIG. 2 9(B)).

[0356] The second oxide semiconductor layer 405 is made of a quaternary metal oxide, similar to the first oxide semiconductor layer 404. In-Sn-Ga-Zn-O system, which is a compound, and In-Ga-Zn- O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, A In-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxide In-Zn -O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, It can be formed using In-Mg-O, In-O, Sn-O, Zn-O, etc. can.

[0357] The second oxide semiconductor layer 405 is made of a material having the same main component as the first oxide semiconductor layer 404. or have the same crystal structure and close lattice constants (mismatch of 1% or less) It is preferable that the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404 have the same main When a material having the above component is used, the first oxide semiconductor layer 4 is formed in the second heat treatment to be performed later. When crystal growth is performed using the non-single-crystal region of 04 as a seed, the second oxide semiconductor layer 405 is crystallized. In addition, when the second oxide semiconductor layer 405 and the first oxide semiconductor layer 406 have the same main component, The interface properties such as adhesion with the compound semiconductor layer 404 and the electrical properties are also improved.

[0358] Alternatively, the second oxide semiconductor layer 405 may contain a different main component from that of the first oxide semiconductor layer 404. When materials with different main components are used, the electrical properties of each layer can be made different. As a result, for example, the second oxide semiconductor layer 405 can be made to have high electrical conductivity. By using a material with high electrical conductivity for the first oxide semiconductor layer 401 and a material with low electrical conductivity for the second oxide semiconductor layer 402, This makes it possible to realize a semiconductor device that reduces the influence of the underlying interface. A good seed crystal is formed in the compound semiconductor layer 404 using a material that is easy to crystallize, and then a second The oxide semiconductor layer 405 is formed and crystallized, whereby the second oxide semiconductor layer 405 is crystallized. Regardless of the ease of the deposition, the crystallinity of the second oxide semiconductor layer 405 can be favorable.

[0359] In this embodiment, the second oxide semiconductor layer 405 is an In—Ga—Zn—O-based oxide semiconductor. The second oxide semiconductor layer 40 is formed by sputtering using a conductive target. The fifth oxide semiconductor layer may be formed by a method similar to that for forming the first oxide semiconductor layer 404. The thickness of the second oxide semiconductor layer 405 is set to be thicker than the thickness of the first oxide semiconductor layer 404. In addition, the thickness of the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 is preferably The second oxide semiconductor layer 405 is formed so that the sum of the above is greater than or equal to 3 nm and less than or equal to 50 nm. It is preferable that the thickness of the oxide semiconductor film be 1000 nm or less. Therefore, the thickness may be selected depending on the material used and the intended use.

[0360] Next, the second oxide semiconductor layer 405 is subjected to second heat treatment, and the first oxide semiconductor layer 404 The non-single-crystal region is used as a seed for crystal growth to form a crystallized second oxide semiconductor layer 405. (See Figure 29(C)).

[0361] The second oxide semiconductor layer 405 is subjected to second heat treatment to convert the first oxide semiconductor layer The non-single-crystal region formed at the interface between the semiconductor layer 404 and the second oxide semiconductor layer 405 The second oxide semiconductor layer 405 is then subjected to crystal growth to form a crystallized second oxide semiconductor layer 405. Furthermore, by performing a second heat treatment, the first oxide semiconductor can be formed. The conductor layer 404 can be a non-single crystalline layer with a higher degree of orientation.

[0362] Note that a region of the first oxide semiconductor layer 404 that overlaps with the irregularities of the gate insulating layer 402 is The second oxide semiconductor layer 405 has a grain boundary and is non-single crystalline. The region where the second oxide semiconductor layer 405 is to be formed has at least a flat surface. The region to be the channel formation region has the same c-axis orientation as the first oxide semiconductor layer 404. Note that the height difference of the surface of the second oxide semiconductor layer 405 is determined by the gate voltage. In the region overlapping with the electrode layer 411 (channel forming region), the thickness is 1 nm or less (preferably 0. In addition, the second oxide semiconductor layer 405 preferably has a thickness of 2 nm or less. In the nucleation region, the a-axis and b-axis of the non-single crystal are also misaligned.

[0363] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the second oxide semiconductor layer 405. In this case, the second oxide semiconductor layer 405 is made of InGaO3 (ZnO). m(m>0 and m is not a natural number), and In2Ga2ZnO7 (In:Ga:Zn:O=2 Such crystals may be formed by the second heat treatment. The c-axis of the second oxide semiconductor layer 405 is aligned in a direction substantially perpendicular to the surface of the second oxide semiconductor layer 405. do.

[0364] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or Zn are stacked in the c-axis direction.

[0365] In the In-Ga-Zn-O oxide semiconductor, the a-axis and b-axis of the layer containing In The conductivity in the direction parallel to the axis is good. This is because the In-Ga-Zn-O oxide semiconductor In the case of ZnO, the electrical conduction is mainly controlled by In, and the 5s orbital of one In is By overlapping with the 5s orbital of the adjacent In, a carrier path is formed. evening.

[0366] The first oxide semiconductor layer 404 has an amorphous region at the interface with the gate insulating layer 402. In the case of such a structure, the second heat treatment is performed to remove the oxide semiconductor layer 404 from the surface thereof. The crystals grow from the crystalline region formed on the lower surface of the first oxide semiconductor layer 404 toward the lower surface of the first oxide semiconductor layer 404. In some cases, the amorphous region may be crystallized. However, depending on the conditions of the heat treatment, the amorphous region may remain.

[0367] The first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 are made of oxide semiconductors having the same main component. When a conductive material is used, the first oxide semiconductor layer 404 is formed as a crystalline oxide semiconductor layer as shown in FIG. The crystal is grown upward toward the surface of the second oxide semiconductor layer 405 as a seed for growth. The first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 have the same crystal structure. Therefore, although indicated by a dotted line in FIG. 29C, the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 are The boundary of the oxide semiconductor layer 406 becomes indistinguishable, and the boundary between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 becomes indistinguishable. The oxide semiconductor layer 406 can sometimes be regarded as the same layer.

[0368] In this manner, by performing the second heat treatment, the second oxide semiconductor layer 405 and the first oxide semiconductor layer 406 are separated. The entire second oxide semiconductor layer 405 is formed from the non-single-crystal region formed at the interface of the second oxide semiconductor layer 404. The second heat treatment can be performed to crystallize the first oxide. The semiconductor layer 404 can be a non-single crystalline layer with a higher degree of orientation.

[0369] The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The time for the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more and 2 hours or less. It is set to 0 hours or less, typically 10 hours.

[0370] In the second heat treatment, nitrogen, oxygen, or a dilute gas such as helium, neon, or argon is also used. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the nitrogen introduced into the heat treatment device , oxygen, or rare gases such as helium, neon, argon, etc., with a purity of 6N or more, preferably It is preferable to use an air pressure of 7N or more. In addition, it is also preferable to use an air pressure of 20 ppm or less of H2O in ultra-dry air. More preferably, the second heat treatment may be carried out in ultra-dry air with an H2O concentration of 1 ppm or less. By such second heat treatment, water (including a hydroxyl group) in the second oxide semiconductor layer 405 is removed. Therefore, impurities can be reduced and the resulting material can be highly purified, resulting in i-type or The first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 are formed to be substantially i-type. It can be achieved.

[0371] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise of the second heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be switched, and after dehydration or dehydrogenation is performed in a nitrogen atmosphere, The atmosphere is then changed to an oxygen atmosphere, whereby oxygen is introduced into the second oxide semiconductor layer 405. can be supplied.

[0372] The heat treatment apparatus used for the second heat treatment can also be referred to the heat treatment apparatus of the fifth embodiment. Detailed explanation will be omitted.

[0373] For the subsequent steps, reference can be made to the fifth embodiment (FIGS. 15(B) to (D)). Cut.

[0374] Through the above steps, a transistor 450 including the oxide semiconductor layer 406a is completed (FIG. 29( See D).

[0375] As described above, by forming a non-single-crystal region in the oxide semiconductor layer 406a, the transistor In this way, the mobility of the transistor can be improved. By applying this to circuits that require high-speed operation, the driving capability of the circuits can be improved.

[0376] The transistor described in this embodiment may be used in the semiconductor device described in any of Embodiments 1 to 3. By applying this, the driving capability of the semiconductor device can be improved.

[0377] In addition, when the transistor described in this embodiment and the transistor described in Embodiment 5 are combined, The present invention can also be applied to the semiconductor devices described in Embodiments 1 to 4. [Explanation of symbols]

[0378] 101 Transistor 102 transistor 103 Transistor 104 transistors 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 121 Capacitor element 130 circuits 131 circuits 132 circuits 133 circuits 134 circuits 140 Protection circuit 141 transistors 142 transistors 201 NOR circuit 202 NAND circuit 203 Inverter Circuit 211 Wiring 212 Wiring 213 Wiring 400 boards 402 Gate insulating layer 404 Oxide semiconductor layer 405 Oxide semiconductor layer 406 Oxide semiconductor layer 406a Oxide semiconductor layer 408a Source electrode layer and drain electrode layer 408b Source electrode layer and drain electrode layer 411 Gate electrode layer 412 Insulating layer 418 Insulating Layer 450 transistors 111A wiring 111B Wiring 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5354 Pixel section 5360 video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5380 PCB 5381 input terminal 5450 pixels 5451 Transistor 5452 Capacitor 5453 Display element 5454 Electrode 5455 Electrode 5461 Wiring 5462 Wiring 5463 Wiring 5480 Microcapsules 5481 Resin 5482 Membrane 5483 liquid 5484 particles 5485 particles 5486 Twist Ball 5487 particles 5488 Cavity 5491 Micro Cup 5492 Dielectric Solvent 5493 Charged pigment particles 5494 Sealing layer 5495 Adhesive layer 5502 Electronic Liquid Powder (registered trademark) 5503 Electronic Liquid Powder (registered trademark) 5504 Bulkhead 5361a circuit 5361b circuit 5362a circuit 5362b circuit

Claims

1. It has a multi-stage circuit, each of the plurality of stages of circuits includes a first transistor to an eighth transistor; In at least one of the multiple stages of circuits, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to a third wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the first wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the third wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; a gate of the seventh transistor is always electrically connected to a gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eighth transistor is always electrically connected to a fourth wiring; the gate of the eighth transistor is always electrically connected to the fourth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a clock signal line, the third wiring has a function as a power supply line, the fourth wiring has a function of inputting a second signal, a gate of the second transistor and a gate of the third transistor are always electrically connected to a gate of the second transistor and a gate of the third transistor included in another circuit among the plurality of stages of circuits; Semiconductor device.

2. It has a multi-stage circuit, each of the plurality of stages of circuits includes a first transistor to an eighth transistor; In at least one of the multiple stages of circuits, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to a third wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the first wiring; the other of the source and the drain of the fourth transistor is always electrically connected to the third wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; a gate of the seventh transistor is always electrically connected to a gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eighth transistor is always electrically connected to a fourth wiring; the gate of the eighth transistor is always electrically connected to the fourth wiring; the first wiring has a function of outputting a first signal, the second wiring has a function as a clock signal line, the third wiring has a function as a power supply line, the fourth wiring has a function of inputting a second signal, a third signal is input to the gate of the second transistor and the gate of the third transistor; a fourth signal is input to a gate of the fourth transistor and a gate of the fifth transistor; a fifth signal is input to the gate of the seventh transistor and the gate of the sixth transistor; a gate of the second transistor and a gate of the third transistor are always electrically connected to a gate of the second transistor and a gate of the third transistor included in another circuit among the plurality of stages of circuits; Semiconductor device.

3. In claim 1 or claim 2, At least one of the second transistor, the fourth transistor, and the sixth transistor has a channel width larger than that of each of the third transistor, the fifth transistor, and the seventh transistor. Semiconductor device.

4. In any one of claims 1 to 3, each of the first to eighth transistors includes a channel formation region in an oxide semiconductor film; Semiconductor device.

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