Photoelectric converter and photoelectric conversion system

Abstract

To provide a technique advantageous for reducing the influence of light incident on a peripheral area of a photoelectric conversion device.SOLUTION: A photoelectric conversion device has a semiconductor layer including a pixel array area having a plurality of pixels, and a peripheral area arranged on the periphery of the pixel array area. The semiconductor layer has a first surface and a second surface. Each pixel in the pixel array area includes a first semiconductor area of a first conductivity type arranged on the side of the first surface, and a second semiconductor area of a second conductivity type arranged on the side of the second surface, and predetermined voltage that may cause an avalanche doubling operation is supplied between the first semiconductor area and the second semiconductor area. The peripheral area includes a third semiconductor area of the first conductive type arranged on the side of the first surface, and a fourth semiconductor area of the second conductive type arranged separate from the third semiconductor area. The fourth semiconductor area includes an extension part extending parallel to the second surface, and voltage is supplied between the third semiconductor area and the fourth semiconductor area.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] Patent Document 1 describes an APD (avalanche photodiode) aimed at reducing crosstalk from pixels and suppressing DCR (dark count rate). The APD includes a high electric field region, a separation region for separating adjacent pixels, and a hole accumulation region for trapping electrons on the sidewall of the separation region, and has a configuration in which the hole accumulation region is electrically connected to an anode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor substrate of a photoelectric conversion device may have a pixel array region and a peripheral region disposed around the pixel array region. When light is incident on the peripheral region unintentionally, charges (electrons and holes) are generated by photoelectric conversion, and these can enter the pixels of the pixel array. Alternatively, when the charges generated by photoelectric conversion recombine to generate light, this can be detected by the pixels of the pixel array, for example, a light-shielding pixel (OB pixel).

[0005] An object of the present invention is to provide an advantageous technique for reducing the influence of light incident on the peripheral region of a photoelectric conversion device.

Means for Solving the Problems

[0006] One aspect of the present invention is a semiconductor layer comprising a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region. And, a wiring structure stacked on the semiconductor layer, The present invention relates to a photoelectric conversion device having, The aforementioned peripheral region is the region between the outer edge of the pixel located at the outermost periphery of the pixel array region and the outer edge of the semiconductor layer. The aforementioned semiconductor layer is On opposite sides It has a first surface and a second surface, The first surface is located on the wiring structure side of the second surface. Each pixel in the pixel array region includes a first semiconductor region of a first conductivity type located on the side of the first plane and a second semiconductor region of a second conductivity type located on the side of the second plane, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region. The peripheral region includes a third semiconductor region of a first conductivity type located on the side of the first plane and a fourth semiconductor region of a second conductivity type located away from the third semiconductor region, and the fourth semiconductor region includes an extension portion extending parallel to the second plane, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region, and the fourth semiconductor region includes a portion extending from the second plane to the first plane. Separation region including The extended portion includes the first semiconductor region and the third semiconductor region. [Effects of the Invention]

[0007] According to the present invention, an advantageous technique is provided for reducing the influence of light incident on the peripheral region of a photoelectric converter. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing the basic configuration of the photoelectric conversion device according to the embodiment. [Figure 2] A diagram showing an example of the sensor board configuration. [Figure 3] A diagram showing an example of a circuit board configuration. [Figure 4] Equivalent circuit diagram of a single pixel and its signal processing unit. [Figure 5] A diagram illustrating the operation of pixels. [Figure 6] A diagram showing a first example of pixel configuration. [Figure 7A] A diagram showing a first example of pixel configuration. [Figure 7B] Figure showing the first configuration example of a pixel. [Figure 8] Figure showing the second configuration example of a pixel. [Figure 9A] Figure showing the second configuration example of a pixel. [Figure 9B] Figure showing the second configuration example of a pixel. [Figure 10] Plan view showing the configuration of the photoelectric conversion device of the first embodiment. [Figure 11] Cross-sectional view showing the configuration of the photoelectric conversion device of the first embodiment. [Figure 12] Plan view showing the configuration of the photoelectric conversion device of the second embodiment. [Figure 13] Cross-sectional view showing the configuration of the photoelectric conversion device of the second embodiment. [Figure 14] Plan view showing the configuration of the photoelectric conversion device of the third embodiment. [Figure 15A] Cross-sectional view showing the configuration of the photoelectric conversion device of the third embodiment. [Figure 15B] Cross-sectional view showing the configuration of the photoelectric conversion device of the third embodiment. [Figure 16A] Cross-sectional view showing the configuration of the photoelectric conversion device of the fourth embodiment. [Figure 16B] Cross-sectional view showing the configuration of the photoelectric conversion device of the fourth embodiment. [Figure 17] Cross-sectional view showing the configuration of the photoelectric conversion device of the fifth embodiment. [Figure 18] Cross-sectional view showing the configuration of the photoelectric conversion device of the sixth embodiment. [Figure 19] Cross-sectional view showing the configuration of the photoelectric conversion device of the seventh embodiment. [Figure 20] Cross-sectional view showing the configuration of the photoelectric conversion device of the eighth embodiment. [Figure 21] Cross-sectional view showing the configuration of the photoelectric conversion device of the ninth embodiment. [Figure 22] Cross-sectional view showing the configuration of the photoelectric conversion device of the tenth embodiment. [Figure 23] Figure showing the configuration of the photoelectric conversion system. [Figure 24] Figure showing the configuration of the photoelectric conversion system. [Figure 25]A diagram showing the configuration of a photoelectric conversion system. [Figure 26] A diagram showing the configuration of a photoelectric conversion system. [Figure 27] A diagram showing the configuration of a photoelectric conversion system. [Figure 28] A diagram showing the configuration of a photoelectric conversion system. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, terms indicating specific directions or positions (e.g., "up," "down," "right," "left," and other terms including these terms) will be used as needed. The use of these terms is for the purpose of facilitating the understanding of embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, a plan view refers to viewing a semiconductor layer from a direction perpendicular to the light incident surface. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. If the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer as viewed macroscopically.

[0012] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and the signal is taken from the cathode side. Therefore, the semiconductor region of the first conductivity type, which has majority carriers of the same polarity as the signal charge, is an N-type semiconductor region, and the semiconductor region of the second conductivity type, which has majority carriers of charges with a different polarity than the signal charge, is a P-type semiconductor region. Note that the present invention also applies when the cathode of the APD is set to a fixed potential and the signal is taken from the anode side. In this case, the semiconductor region of the first conductivity type, which has majority carriers of the same polarity as the signal charge, is a P-type semiconductor region, and the semiconductor region of the second conductivity type, which has majority carriers of charges with a different polarity than the signal charge, is an N-type semiconductor region. The following description will focus on the case where one node of the APD is set to a fixed potential, but the potentials of both nodes may fluctuate.

[0013] In this specification, when the term "impurity concentration" is used, it refers to the net impurity concentration after subtracting the amount compensated by reverse-conductivity impurities. In other words, "impurity concentration" refers to the NET doping concentration. The region where the doping concentration of P-type impurities is higher than that of N-type impurities is a P-type semiconductor region. Conversely, the region where the doping concentration of N-type impurities is higher than that of P-type impurities is an N-type semiconductor region.

[0014] First, the basic configuration and driving method common to the photoelectric conversion device and its driving method in the multiple embodiments described later will be explained with reference to Figures 1, 2, 3, 4, and 5.

[0015] Figure 1 shows the basic configuration of a photoelectric converter 100 according to an embodiment. Here, an example is described in which the photoelectric converter 100 is configured as a stacked type photoelectric converter, but the present invention is also applicable to photoelectric converters other than stacked types. The photoelectric converter 100 may be configured by stacking a plurality of substrates, including a sensor substrate 301 and a circuit board 401, and electrically connecting the plurality of substrates. The sensor substrate 301 may have a first semiconductor layer having a photoelectric conversion element 102, which will be described later, and a first wiring structure. The circuit board 401 may have a second semiconductor layer having a circuit such as a signal processing unit 103, which will be described later, and a second wiring structure. The photoelectric converter 100 may be configured by stacking, for example, a second semiconductor layer, a second wiring structure, a first wiring structure, and a first semiconductor layer in that order. The photoelectric converter described as the following embodiment may be, for example, a back-illuminated type photoelectric converter, but the photoelectric converter according to the present invention may be configured as a front-illuminated type photoelectric converter.

[0016] The sensor substrate 301 and the circuit board 401 may each be chips diced from a wafer, but these substrates are not limited to chips. For example, each substrate may be a wafer. Also, multiple substrates may be stacked in wafer form and then diced, or multiple chips may be stacked or bonded together after being formed into chips.

[0017] The sensor substrate 301 may include a semiconductor layer comprising a pixel array region 12 having multiple pixels and a peripheral region 13 arranged around the pixel array region 12. The region between the outer edge of the pixel array region 12 and the outer edge of the sensor substrate 301 may be the peripheral region 13. Circuit elements such as active elements may or may not be arranged in the peripheral region 13. The circuit substrate 401 may include a semiconductor layer comprising a circuit region 22 for processing signals detected by the pixels of the pixel array region 12.

[0018] Figure 2 shows an example configuration of the sensor substrate 301. Multiple pixels 101 can be arranged in a two-dimensional array in the pixel array region 12 so as to form multiple rows and multiple columns. Each pixel 101 may include a photoelectric conversion element 102, which includes an avalanche photodiode (hereinafter referred to as APD).

[0019] The pixels 101 arranged in the pixel array region 12 may be pixels for forming an image. However, when the sensor substrate 301 or the photoelectric converter 100 is applied to TOF (Time of Flight), each pixel 101 does not necessarily have to be a pixel for forming an image. That is, the pixels 101 may be pixels for measuring the time and amount of light that arrives.

[0020] Figure 3 shows the configuration of the circuit board 401. The circuit board 401 may include, for example, a signal processing unit 103 for processing the charge generated by photoelectric conversion in the photoelectric conversion element 102, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110. One signal processing unit 103 may be provided for one pixel 101. The photoelectric conversion element 102 in Figure 2 and the signal processing unit 103 in Figure 3 may be electrically connected via connecting wiring provided for each pixel 101.

[0021] The vertical scanning circuit 110 may be configured to receive a first control pulse supplied from the control pulse generation unit 115, generate a second control pulse, and supply the second control pulse to each pixel 101. The vertical scanning circuit 110 may include logic circuits such as a shift register and an address decoder. The signal output from the photoelectric conversion element 102 of the pixel 101 may be processed by a signal processing unit 103 provided in conjunction with that pixel 101. The signal processing unit 103 may include a counter and memory, and the memory may hold digital values.

[0022] The horizontal scanning circuit unit 111 may be configured to supply a third control pulse to the signal processing unit 103 that sequentially selects each row in order to read a signal from the memory of each pixel 101 that holds a digital signal. The circuit board 401 may have a plurality of signal lines 113. Signals are output to the plurality of signal lines 113 from the signal processing unit 103 assigned to the pixels 101 of the row selected by the vertical scanning circuit unit 110. The signals output to the plurality of signal lines 113 may be output via the output circuit 114 to an external recording unit or signal processing unit of the photoelectric converter 100.

[0023] In Figure 2, the arrangement of photoelectric conversion elements 102 or pixels 101 in the pixel array region 12 may be one-dimensional. Each signal processing unit 103 may be assigned to at least two photoelectric conversion elements 102 or pixels 101.

[0024] As shown in Figures 2 and 3, multiple signal processing units 103 may be arranged in the region that overlaps with the pixel array region 12 in a plan view. Furthermore, the vertical scanning circuit unit 110, horizontal scanning circuit unit 111, readout circuit 112, output circuit 114, and control pulse generation unit 115 may be arranged so as to overlap with the region between the outer edge of the sensor substrate 301 and the outer edge of the pixel array region 12 in a plan view. In other words, the vertical scanning circuit unit 110, horizontal scanning circuit unit 111, readout circuit 112, output circuit 114, and control pulse generation unit 115 may be arranged in the region that overlaps with the peripheral region 13 of the sensor substrate 301 in a plan view.

[0025] Figure 4 illustrates the equivalent circuits of one pixel 101 in Figure 2 and one signal processing unit 103 in Figure 3. The APD201 generates charge pairs corresponding to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD201. In addition, a voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, may be supplied to the cathode of the APD201. A reverse bias voltage (a predetermined voltage) may be supplied between the anode and cathode, which can cause the APD201 to perform avalanche multiplication. By supplying such a reverse bias voltage between the anode and cathode, the charge generated by the incident light can cause avalanche multiplication, and an avalanche current can be generated.

[0026] The mode in which the APD operates when the voltage between the anode and cathode is greater than the breakdown voltage is called Geiger mode. The mode in which the APD operates when the voltage between the anode and cathode is near or below the breakdown voltage is called linear mode. An APD operating in Geiger mode is called SPAD. For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V. The APD201 may operate in linear mode or in Geiger mode.

[0027] The quench element 202 may be positioned to connect the power supply that provides voltage VH to the APD201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD201 and thereby suppressing avalanche multiplication (quench operation). The quench element 202 also works to restore the voltage supplied to the APD201 to voltage VH by flowing current to compensate for the voltage drop caused by the quench operation (recharge operation).

[0028] The signal processing unit 103 may include a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. The signal processing unit 103 may be a circuit that includes at least one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212. The waveform shaping unit 210 can shape the cathode potential change of the APD201 obtained during photon detection and output a pulse signal. For example, an inverter circuit may be used as the waveform shaping unit 210. In Figure 4, the waveform shaping unit 210 is composed of one inverter, but the waveform shaping unit 210 may include a series connection of multiple inverters, or it may include other circuits that have a waveform shaping effect.

[0029] The counter circuit 211 can count the pulse signal output from the waveform shaping unit 210 and hold the count value. The counter circuit 211 can also be configured to reset the signal held by the counter circuit 211 by supplying a control pulse pRES via the drive line 213. The selection circuit 212 is supplied with a control pulse pSEL from the vertical scanning circuit unit 110 in Figure 3 via the drive line 214 (not shown in Figure 3) in Figure 4, and can switch the electrical connection between the counter circuit 211 and the signal line 113. The selection circuit 212 may include, for example, a buffer circuit for outputting a signal.

[0030] A switch such as a transistor may be placed between the quench element 202 and the APD201, and / or between the photoelectric conversion element 102 and the signal processing unit 103, and the electrical connection may be controlled by the switch. Similarly, the supply of voltage VH and / or voltage VL to the photoelectric conversion element 102 may be controlled by a switch such as a transistor.

[0031] The photoelectric converter 100 may be configured to acquire pulse detection timing using a Time-to-Digital Converter (TDC) and memory instead of the counter circuit 211. The generation timing of the pulse signal output from the waveform shaping unit 210 can be converted into a digital signal by the TDC. A control pulse pREF (reference signal) may be supplied to the TDC via a drive line from the vertical scanning circuit unit 110 in Figure 1 for measuring the timing of the pulse signal. The TDC can acquire a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 210 is relative to the control pulse pREF.

[0032] Figure 5 schematically shows the relationship between the operation of the APD201 and the output signal. Figure 5(a) is a diagram showing the APD201, quench element 202, and waveform shaping unit 210 extracted from Figure 4. Here, the input side of the waveform shaping unit 210 is denoted as node A, and the output side as node B. Figure 5(b) shows the waveform change at node A in Figure 5(a), and Figure 5(c) shows the waveform change at node B in Figure 5(a).

[0033] Between time t0 and time t1, a potential difference of VH-VL is applied to APD201 in Figure 5(a). When a photon is incident on APD201 at time t1, an avalanche multiplication operation is triggered in APD201, causing an avalanche multiplication current to flow through the quench element 202, and the voltage at node A drops. As the voltage drop increases further and the potential difference applied to APD201 decreases, the avalanche multiplication operation of APD201 stops as shown at time t2, and the voltage level at node A no longer drops below a certain value. Subsequently, between time t2 and time t3, a current flows through node A to compensate for the voltage drop from voltage VL, and at time t3, node A settles to its original potential level. At this time, any portion of the output waveform at node A that exceeds a certain threshold is waveform-shaped by the waveform shaping unit 210 and output as a signal at node B.

[0034] Note that the arrangement of the signal line 113, the read circuit 112, and the output circuit 114 is not limited to Figure 3. For example, the signal line 113 may be arranged extending in the row direction, and the read circuit 112 may be located at the end of the signal line 113.

[0035] Here, a first example of the pixel 101 configuration will be described with reference to Figures 6, 7A, and 7B. For convenience, Figures 7A and 7B show an example in which the pixel array region is composed of 4 pixels in a 2x2 grid. An aperture OP is provided around the pixel array region, and a pad electrode PE is placed in the aperture OP. Figure 6(a) schematically shows a plan view of the cathodes and their surroundings of two pixels 101, and Figure 6(b) schematically shows a plan view of the anodes and their surroundings of two pixels 101. Figure 7A schematically shows a cross-sectional view of the two pixels 101 in the opposite direction from Figures 6(a) and (b), and Figure 7B schematically shows a cross-sectional view of the two pixels 101 in the diagonal direction from Figures 6(a) and (b).

[0036] The sensor substrate 301 may include a first semiconductor layer 302 having a first surface S1 and a second surface S2, and a first wiring structure 303. The circuit board 401 may include a second semiconductor layer 402 and a second wiring structure 403. The first wiring structure 303 may be disposed between the first surface S1 of the first semiconductor layer 302 and the circuit board 401. The second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402.

[0037] Each pixel 101 may include a first semiconductor region 311 of a first conductivity type as the cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type as the anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be located on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be located on the side of the second surface S2 of the first semiconductor layer 302. A predetermined voltage capable of causing an avalanche doubling operation may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a semiconductor region 313 of a first conductivity type located in close proximity to the first semiconductor region 311 between the first semiconductor region 311 as the cathode and the second semiconductor region 315 as the anode. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 as the cathode.

[0038] Each pixel 101 may include a semiconductor region 312 of a second conductivity type between a first semiconductor region 311 of a first conductivity type acting as a cathode and a second semiconductor region 315 of a second conductivity type acting as an anode. For example, if semiconductor region 312 is at the same node as the second semiconductor region 315 acting as an anode, semiconductor region 312 can also function as an anode. The region between the first semiconductor region 311 and semiconductor region 312 can become an avalanche multiplication region. Between the first surface S1 and the semiconductor region 312 of the second conductivity type, a semiconductor region 316 of either a first conductivity type or a second conductivity type may be arranged so as to surround the first semiconductor region 311 of the first conductivity type acting as a cathode. If semiconductor region 316 has a first conductivity type, the impurity concentration of the first conductivity type in semiconductor region 316 is lower than the impurity concentration of the first conductivity type in semiconductor region 313 acting as a cathode. If the semiconductor region 316 has a second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 is lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0039] A semiconductor region 316 of either the first or second conductivity type may be positioned between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 of the second conductivity type acting as an anode. If the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. If the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0040] A semiconductor region 317 of the first conductivity type may be positioned between the second semiconductor region 315, which acts as an anode, and the semiconductor region 312, which acts as an anode. The semiconductor region 316 may include the portion positioned between the second semiconductor region 315, which acts as an anode, and the semiconductor region 317 of the first conductivity type, and the portion surrounding the side of the semiconductor region 317 of the first conductivity type.

[0041] Between adjacent pixels 101 in a plurality of pixels 101, a second conductivity type isolation region 314 may be arranged. Between the second conductivity type isolation region 314 and the first surface S1, a second conductivity type contact region 318 may be arranged so as to be electrically connected to the second conductivity type isolation region 314. The impurity concentration of the second conductivity type in the second conductivity type contact region 318 is higher than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second semiconductor region 315 of the second conductivity type acting as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying an anode voltage (anode potential) to the second semiconductor region 315 of the second conductivity type acting as an anode. In the example shown in Figure 6, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 can be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped together, and one or more contact regions 318 may be provided for each group.

[0042] An insulating isolation section 324 may be arranged within the isolation region 314 of the second conductivity type. The insulating isolation section 324 may include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation section 324 may be called a DTI (Deep Trench Isolation). The insulating isolation section 324 or groove may be arranged to penetrate the first semiconductor layer 302, or it may be arranged not to penetrate the first semiconductor layer 302. The insulating isolation section 324 or groove can electrically isolate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101. The insulating isolation section 324 may also consist of a groove, an insulator arranged to cover the inner surface of the groove, and a metal or light-shielding material arranged inside the insulator. Furthermore, the insulating separation portion 324 does not need to penetrate the semiconductor layer.

[0043] A pinning layer 331 (shown by a thick line) may be placed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type as an anode. The pinning layer 331 may also be called a fixed charge film. The pinning layer 331 is placed in contact with the second surface S2 and may be formed, for example, by ALD (Atomic Layer Deposition). The pinning layer 331 may be composed of a material selected from, for example, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide. The pinning layer 331 may consist of multiple layers. The aforementioned film covering the surface (inner surface) of the groove provided in the separation region 314 may also be the pinning layer 331.

[0044] The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. The insulating film 321 may be, for example, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film. The insulating film 321 may be composed of multiple films. A second semiconductor region 315 of the second conductivity type as an anode may be provided with a textured structure 325. The surface of the textured structure 325 may be covered with the pinning layer 331. The textured structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302. This is advantageous for improving near-infrared sensitivity. The textured structure 325 may be composed of grooves provided in the semiconductor layer 302, and a pinning layer 331 and an insulator disposed in the grooves. The pinning layer 331 may be provided so as to cover the exposed surface of the semiconductor layer 302. That is, the pinning layer 331 is disposed along the grooves of the textured structure and the second surface S2. The insulator placed in the groove may be made of an insulating film 321.

[0045] The insulating film 321 may be covered with a planarization layer 322. A microlens 323 may be placed on the planarization layer 322. The example shown in Figures 7A and 7B is a back-illuminated type in which light is incident from the outside through the microlens 323 onto the second surface S of the semiconductor layer 302, but the photoelectric converter 100 may be configured as a front-illuminated type. Although not shown, in addition to the planarization layer 322, a filter layer such as a color filter or an infrared light cut filter may be provided on the second surface S2 side of the semiconductor layer 302.

[0046] The second configuration example of pixel 101 will be described below with reference to Figures 8, 9A, and 9B. For convenience, Figures 9A and 9B show an example in which the pixel array region is composed of 4 pixels in a 2x2 grid. An aperture OP is provided around the pixel array region, and a pad electrode PE is placed in the aperture OP. Figure 8(a) schematically shows a plan view of the cathodes and their surroundings of two pixels 101, and Figure 8(b) schematically shows a plan view of the anodes and their surroundings of two pixels 101. Figure 9A schematically shows a cross-sectional view of the two pixels 101 in the opposite direction from Figures 8(a) and (b), and Figure 9B schematically shows a cross-sectional view of the two pixels 101 in the diagonal direction from Figures 8(a) and (b).

[0047] The sensor substrate 301 may include a first semiconductor layer 302 having a first surface S1 and a second surface S2, and a first wiring structure 303. The circuit board 401 may include a second semiconductor layer 402 and a second wiring structure 403. The first wiring structure 303 may be disposed between the first surface S1 of the first semiconductor layer 302 and the circuit board 401. The second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402.

[0048] Each pixel 101 may include a first semiconductor region 311 of a first conductivity type as the cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type as the anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be located on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be located on the side of the second surface S2 of the first semiconductor layer 302. A predetermined voltage capable of causing an avalanche doubling operation may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a ring-shaped semiconductor region 313 of a first conductivity type located between the first semiconductor region 311 as the cathode and the second semiconductor region 315 as the anode, and positioned in close proximity to the peripheral portion of the first semiconductor region 311. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 as the cathode.

[0049] Each pixel 101 may include a semiconductor region 312 of the second conductivity type, adjacent to the central portion of the first semiconductor region 311, between the first semiconductor region 311 of the first conductivity type acting as the cathode and the second semiconductor region 315 of the second conductivity type acting as the anode. For example, if the semiconductor region 312 is the same node as the second semiconductor region 315 acting as the anode, then the semiconductor region 312 can also function as an anode. The region between the first semiconductor region 311 and the semiconductor region 312 may become an avalanche multiplication region. Between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 acting as the anode, a semiconductor region 316 of either the first or second conductivity type may be located. If the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. If the semiconductor region 316 has a second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type. The semiconductor region 316 may be arranged to surround the semiconductor region 313 of the first conductivity type. The semiconductor region 316 may also include a portion located between the semiconductor region 313 of the first conductivity type and the second semiconductor region 315 of the second conductivity type acting as an anode.

[0050] Between adjacent pixels 101 in a plurality of pixels 101, a second conductivity type isolation region 314 may be arranged. Between the second conductivity type isolation region 314 and the first surface S1, a second conductivity type contact region 318 may be arranged so as to be electrically connected to the second conductivity type isolation region 314. The impurity concentration of the second conductivity type in the second conductivity type contact region 318 is higher than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second semiconductor region 315 of the second conductivity type acting as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying an anode voltage (anode potential) to the second semiconductor region 315 of the second conductivity type acting as an anode. In the example shown in Figure 8, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 can be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped together, and one or more contact regions 318 may be provided for each group.

[0051] An insulating isolation portion 324 may be arranged within the isolation region 314 of the second conductivity type. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation portion 324 may be called a DTI (Deep Trench Isolation). The insulating isolation portion 324 or groove may be arranged to penetrate the first semiconductor layer 302, or it may be arranged not to penetrate the first semiconductor layer 302. The insulating isolation portion 324 or groove can electrically isolate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101.

[0052] A pinning layer 331 (shown by a thick line) may be placed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type as the anode. The pinning layer 331 may also be called a fixed charge film. The pinning layer 331 is placed in contact with the second surface S2 and may be formed, for example, by ALD (Atomic Layer Deposition). The pinning layer 331 may be formed from, for example, polycrystalline silicon, a hafnium oxide film, or an aluminum oxide film. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. The insulating film 321 may be, for example, an SiO film, a SiN film, or a SiON film. A ridged structure 325 may be provided on the second semiconductor region 315 of the second conductivity type as the anode. The surface of the ridged structure 325 may be covered with the pinning layer 331. The ridged structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302. This is advantageous for improving near-infrared sensitivity.

[0053] The insulating film 321 may be covered with a planarization layer 322. A microlens 323 may be placed on the planarization layer 322. The example shown in Figures 9A and 9B is a back-illuminated type in which light is incident from the outside through the microlens 323 onto the second surface S of the semiconductor layer 302, but the photoelectric converter 100 may be configured as a front-illuminated type.

[0054] The configuration of the photoelectric converter 100 of the first embodiment will be described below with reference to Figures 10 and 11. The photoelectric converter 100 of the first embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. In detail, the photoelectric converter of the first embodiment differs from the first configuration example in that, for example, it does not have an insulating separation unit or an uneven structure.

[0055] The photoelectric converter 100 of the first embodiment has a semiconductor layer 302 (or, in other terms, a sensor substrate 301) which includes a pixel array region 12 having a plurality of pixels 101 and a peripheral region 13 arranged around the pixel array region 12. The pixel array region 12 may include an effective pixel region 12E in which pixels (effective pixels) 102 that output signals corresponding to incident light are arranged, and an OB pixel region 12OB in which light-shielded pixels (OB pixels, or light-shielding pixels) 102 are arranged. The OB pixel region 12OB may be arranged along at least a portion of the outer periphery of the effective pixel region 12E. The OB pixel region 12OB may typically be arranged to surround the effective pixel region 12E. At least one, typically a plurality of, pad electrodes PE may be arranged in the peripheral region 13. In the OB pixels 101, the APD 201, which includes an anode and a cathode, is shielded by a light-shielding film LSM. Pixel 101 in OB pixel region 12OB may have the same configuration as pixel 101 in effective pixel region 12E, except that APD201 is shielded by the light-shielding film LSM.

[0056] One or more charge discharge units 1350 may be arranged in the peripheral region 13. In Figure 10(a), one charge discharge unit 1350 is shown as a black circle. Figure 10(b) is a schematic plan view of one charge discharge unit 1350. Here, it is preferable that multiple charge discharge units 1350 are arranged at a predetermined pitch along each of the four sides of the pixel array region 12. It is preferable that this predetermined pitch is larger than the arrangement pitch of multiple pixels 101 in the pixel array region 12. Multiple charge discharge units 1350 may be arranged to form multiple rows along each of the four sides of the pixel array region 12. Multiple charge discharge units 1350 may be arranged in a staggered pattern along each of the four sides of the pixel array region 12.

[0057] As illustrated in Figure 11, the semiconductor layer 302 has a first surface S1 and a second surface S2. Each pixel 101 arranged in the pixel array region 12 (effective pixel region 12E, OB pixel region 12OB) may have a structure similar to the first configuration example described with reference to Figures 6, 7A, and 7B. Hereafter, the explanation will be given with reference to Figures 11, 6, 7A, and 7B. Each pixel 101 may include a first semiconductor region 311 of a first conductivity type as the cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type as the anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be located on the side of the first surface S1 of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be located on the side of the second surface S2 of the first semiconductor layer 302. A predetermined voltage capable of causing an avalanche doubling operation may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a semiconductor region 313 of a first conductivity type located in close proximity to the first semiconductor region 311 between the first semiconductor region 311 as the cathode and the second semiconductor region 315 as the anode. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 as the cathode.

[0058] Each pixel 101 may include a semiconductor region 312 of a second conductivity type between a first semiconductor region 311 of a first conductivity type acting as a cathode and a second semiconductor region 315 of a second conductivity type acting as an anode. Between the first surface S1 and the semiconductor region 312 of the second conductivity type, a semiconductor region 316 of either a first or second conductivity type may be arranged so as to surround the first semiconductor region 311 of the first conductivity type acting as a cathode. If the semiconductor region 316 has a first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 313 acting as a cathode. If the semiconductor region 316 has a second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 is lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0059] A semiconductor region 316 of either the first or second conductivity type may be positioned between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 of the second conductivity type acting as an anode. If the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. If the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0060] A semiconductor region 317 of the first conductivity type may be positioned between the second semiconductor region 315, which acts as an anode, and the semiconductor region 312, which acts as an anode. The semiconductor region 316 may include the portion positioned between the second semiconductor region 315, which acts as an anode, and the semiconductor region 317 of the first conductivity type, and the portion surrounding the side of the semiconductor region 317 of the first conductivity type.

[0061] Between adjacent pixels 101 in a plurality of pixels 101, a second conductivity type isolation region 314 may be arranged. Between the second conductivity type isolation region 314 and the first surface S1, a second conductivity type contact region 318 may be arranged so as to be electrically connected to the second conductivity type isolation region 314. The impurity concentration of the second conductivity type in the second conductivity type contact region 318 is higher than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second semiconductor region 315 of the second conductivity type acting as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying an anode voltage (anode potential) to the second semiconductor region 315 of the second conductivity type acting as an anode.

[0062] An insulating isolation portion 324 may be arranged within the isolation region 314 of the second conductivity type. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation portion 324 may be called a DTI (Deep Trench Isolation). The insulating isolation portion 324 or groove may be arranged to penetrate the first semiconductor layer 302, or it may be arranged not to penetrate the first semiconductor layer 302. The insulating isolation portion 324 or groove can electrically isolate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101.

[0063] A pinning layer 331 (shown by a thick line) may be placed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type as an anode. The pinning layer 331 may also be called a fixed charge film. The pinning layer 331 is placed in contact with the second surface S2 and may be formed, for example, by ALD (Atomic Layer Deposition). The pinning layer 331 may be formed from, for example, polycrystalline silicon, hafnium oxide, or aluminum oxide. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321.

[0064] The peripheral region 13 may include a third semiconductor region 1311 of a first conductivity type located on the side of the first surface S1, and a fourth semiconductor region 1315 of a second conductivity type located spaced apart from the third semiconductor region 1311. The fourth semiconductor region 1315 may include an extension EP extending parallel to the second surface S2. A predetermined voltage may be supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315. The voltage supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315 may be the same as the voltage supplied between the first semiconductor region 311 as an anode and the second semiconductor region 315 as a cathode. A pn ​​junction is formed between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type, and can function as a photodiode by being reverse-biased by the voltage supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315.

[0065] The peripheral region 13 may also include a fifth semiconductor region 1313 of the first conductivity type, having a lower impurity concentration of the first conductivity type than the third semiconductor region 1311, between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. The fifth semiconductor region 1313 may be positioned in close proximity to the third semiconductor region 1311. The fifth semiconductor region 1313 of the first conductivity type is positioned to surround the side of the third semiconductor region 1311. The fifth semiconductor region 1313 of the first conductivity type may include a portion positioned between the third semiconductor region 1311 and the fourth semiconductor region 1315, in contact with the third semiconductor region 1311. The third semiconductor region 1311 of the first conductivity type, the fourth semiconductor region 1315 of the second conductivity type, and the fifth semiconductor region 1313 of the first conductivity type may constitute a charge discharge section 1350. The fifth semiconductor region 1313 of the first conductivity type may function to mitigate the electric field in the vicinity of the third semiconductor region 1311 of the first conductivity type.

[0066] The third semiconductor region 1311 of the first conductivity type may be formed in a region of the same depth (for example, depth from the first surface S1) as the first semiconductor region 311 of the first conductivity type that serves as the cathode of the pixel 101 of the pixel array region 12. Furthermore, the first semiconductor region 311 and the third semiconductor region 1311 may be positioned between the first surface S1 and a first depth. The impurity concentration of the first conductivity type in the third semiconductor region 1311 may be the same as the impurity concentration of the first conductivity type in the first semiconductor region 311 of the pixel 101 of the pixel array region 12. The third semiconductor region 1311 of the first conductivity type may be formed simultaneously with the first semiconductor region 311 of the first conductivity type of the pixel 101 of the pixel array region 12.

[0067] The fourth semiconductor region 1315 of the second conductivity type may be formed in a region of the same depth (for example, depth from the first surface S1) as the second semiconductor region 315 of the second conductivity type that serves as the anode of the pixel 101 of the pixel array region 12. Furthermore, the second semiconductor region 315 and the fourth semiconductor region 1315 may be positioned between the second surface S2 and the second depth. The impurity concentration of the second conductivity type in the fourth semiconductor region 1315 may be the same as the impurity concentration of the second conductivity type in the second semiconductor region 315 of the pixel 101 of the pixel array region 12. The fourth semiconductor region 1315 of the second conductivity type may be formed simultaneously with the second semiconductor region 315 of the second conductivity type of the pixel 101 of the pixel array region 12. The fourth semiconductor region 1315 of the second conductivity type in the peripheral region 13 may be formed integrally with the second semiconductor region 315 of the second conductivity type in the pixel array region 12.

[0068] A semiconductor region 316 of either the first or second conductivity type may be positioned between the fifth semiconductor region 1313 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. If the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 1313. If the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 is lower than the impurity concentration of the second conductivity type in the semiconductor region 1315 of the second conductivity type. The semiconductor region 316 in the peripheral region 13 may have the same conductivity type and the same impurity concentration as the semiconductor region 316 in the pixel array region 12. The semiconductor region 316 may be an epitaxial growth layer.

[0069] Light (or photons) LL can be incident on the semiconductor region 316 of the peripheral region 13, for example, through the aperture OP for the pad electrode PE, or through a region without the light-shielding film LSM. Light LL incident on the semiconductor region 316 of the peripheral region 13 can generate electrons (e-) and holes (h+) through photoelectric conversion. If there is no charge discharge unit 1350 in the peripheral region 13, electrons and holes generated by the light incident on the peripheral region 13 may move to the pixel array region 12, causing an avalanche multiplication operation. Alternatively, electrons and holes generated by the light incident on the peripheral region 13 may recombine to generate light, which may be detected by the pixels 101 in the pixel array region 12. Alternatively, an avalanche multiplication operation may be triggered by the light incident on the peripheral region 13. These may degrade the quality of the image or signal detected by the photoelectric converter 100.

[0070] In the first embodiment, the charge discharge unit 1350 provided in the peripheral region 13 can operate to discharge electrons and holes generated by light incident on the peripheral region 13. Here, if the first conductivity type is n-type and the second conductivity type is p-type, the generated electrons are drawn into the third semiconductor region 1311 of the first conductivity type, and the generated holes are drawn into the fourth semiconductor region 1315 of the second conductivity type.

[0071] In the peripheral region 13, a pinning layer 331 (shown by a thick line) may be arranged on the side of the second surface S2 of the fourth semiconductor region 1315 of the second conductivity type. The pinning layer 331 is arranged to be in contact with the second surface S2 and may be formed, for example, by ALD (Atomic Layer Deposition). The pinning layer 331 may be formed from, for example, polycrystalline silicon, hafnium oxide, or aluminum oxide. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321 such as a SiN film. The pinning layer 331 in the peripheral region 13 may have the same composition as the pinning layer 331 in the pixel array region 12 and may be formed simultaneously with the pinning layer 331 in the pixel array region 12.

[0072] The semiconductor layer 302 may have a second conductivity type isolation region 314 at the boundary region between the pixel array region 12 and the peripheral region 13. The isolation region 314 may be electrically connected to a second semiconductor region 315 of the second conductivity type and supplied with the same potential as the second semiconductor region 315 of the second conductivity type. The second conductivity type isolation region 314 located at the boundary region between the pixel array region 12 and the peripheral region 13 may also constitute a charge discharge unit 1350.

[0073] The light-shielding film LSM may include a light-shielding structure LSS in the boundary region between the pixel array region 12 and the peripheral region 13, for example, in the isolation region 314 in a plan view. In one example, the light-shielding film LSM may be electrically connected to the second semiconductor region 315 of the second conductivity type and / or the fourth semiconductor region 1315 of the second conductivity type via the light-shielding structure LSS. The light-shielding structure LSS may include, for example, one or more walls. These one or more walls may penetrate the pinning layer 331 and be electrically connected to the second semiconductor region 315 of the second conductivity type and / or the fourth semiconductor region 1315 of the second conductivity type.

[0074] The configuration of the photoelectric converter 100 of the second embodiment will be described below with reference to Figures 12 and 13. The photoelectric converter 100 of the second embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The configuration of the charge discharge unit 1350 and / or the voltage supplied to the charge discharge unit 1350 of the photoelectric converter 100 of the first embodiment differ from that of the photoelectric converter 100 of the first embodiment.

[0075] The photoelectric converter 100 of the second embodiment may include a voltage generation unit VG. The voltage generation unit VG can generate a voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type. In other words, the voltage generation unit VG can generate a voltage supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. The voltage generation unit VG can generate the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type by, for example, transforming the voltage supplied to one of the pad electrodes PE among a plurality of pad electrodes PE. The voltage generation unit VG may be located, for example, on a circuit board 401. Alternatively, the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type may be supplied from outside the photoelectric converter 100.

[0076] The voltage supplied to the charge discharge unit 1350, in other words, the voltage supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type, is smaller than the voltage supplied between the anode and cathode of the pixel array region 12. In one example, the voltage supplied to the charge discharge unit 1350 may be less than or equal to half the voltage supplied between the anode and cathode of the pixel array region 12. Alternatively, the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type may be the ground potential in the photoelectric converter 100. This is advantageous for simplifying the structure of the photoelectric converter 100.

[0077] If the electric field generated around the third semiconductor region 1311 of the first conductivity type is sufficiently weak, the fifth semiconductor region 1313, as provided in the charge discharge section 1350 in the first embodiment, may be removed. Figures 12 and 13 illustrate the charge discharge section 1350 with the fifth semiconductor region 1313 removed. This voltage can also be applied to a configuration having an insulating separation section as shown in Figures 7A and 7B.

[0078] The configuration of the photoelectric converter 100 of the third embodiment will be described below with reference to Figures 14, 15A, and 15B. The photoelectric converter 100 of the third embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The photoelectric converter 100 of the third embodiment differs from the photoelectric converter 100 of the first embodiment in that it includes an insulating separation unit 324. Also, for example, the photoelectric converter 100 of the third embodiment differs from the photoelectric converter 100 of the first embodiment in that it includes a bumpy structure 325. Note that the bumpy structure 325 shown in Figures 15A and 15B is the same as that shown in Figures 7A and 7B.

[0079] A second conductivity type isolation region 314 may be arranged between adjacent pixels 101 in a plurality of pixels 101. Similarly, a second conductivity type isolation region 314 may be arranged between the pixel array region 12 and the peripheral region 13. A second conductivity type contact region 318 may be arranged between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314. The impurity concentration of the second conductivity type in the second conductivity type contact region 318 is higher than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second semiconductor region 315 of the second conductivity type acting as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying an anode voltage (anode potential) to the second semiconductor region 315 of the second conductivity type acting as an anode.

[0080] In the pixel array region 12, an insulating isolation portion 324 may be arranged within the isolation region 314 of the second conductivity type. Similarly, in the peripheral region 13, an insulating isolation portion 324 may be arranged within the isolation region 314 of the second conductivity type. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator arranged to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. Such a film may be a pinning layer 331. The insulating isolation portion 324 may be called a DTI (Deep Trench Isolation). The insulating isolation portion 324 or groove may be arranged to penetrate the first semiconductor layer 302, or not to penetrate the first semiconductor layer 302. Also, as shown in Figure 15A, multiple insulating isolation portions may be provided so as to sandwich the aperture OP. The refractive index difference between the insulating material of the insulating isolation portion and the first semiconductor layer 302 can reduce the incidence of light from the aperture OP.

[0081] In the pixel array region 12, the insulating isolation portion 324 or groove can electrically separate the isolation region 314 of the second conductivity type into an isolation region on the side of one pixel 101 and an isolation region on the side of the adjacent pixel 101. Similarly, in the peripheral region 13, the insulating isolation portion 324 or groove can be arranged to electrically separate the isolation region 314 of the second conductivity type into a first isolation region 314A on the side of the pixel array region 12 and a second isolation region 314B on the side of the peripheral region 13. The first wiring structure 303 laminated on the first semiconductor layer 302 may have a first conductive path that provides a potential to the first isolation region 314A, and a second conductive path that provides a potential to the second isolation region 314B. The first conductive path and the second conductive path may be electrically connected within the first wiring structure 303. The conductive path may include, for example, a contact plug, wiring, etc.

[0082] The configuration of the photoelectric converter 100 of the fourth embodiment will be described below with reference to Figures 16A and 16B. The photoelectric converter 100 of the fourth embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The photoelectric converter 100 of the fourth embodiment has a configuration in which the second conductivity type semiconductor region 1315 is removed from the photoelectric converter 100 of the third embodiment. The uneven structure 325 shown in Figures 16A and 16B is the same as that shown in Figures 7A and 7B.

[0083] In the fourth embodiment as well, the charge discharge unit 1350 provided in the peripheral region 13 can operate to discharge electrons and holes generated by light incident on the peripheral region 13. Here, if the first conductivity type is n-type and the second conductivity type is p-type, the generated electrons can be drawn into and discharged into the third semiconductor region 1311 of the first conductivity type. On the other hand, the generated holes can be discharged through the semiconductor region of the second conductivity type, the isolation region 314, and the second semiconductor region 315 of the second conductivity type, which are formed near the surface (near the second surface S2) of the semiconductor region 316 by the charge induced by the pinning layer 331. The semiconductor region of the second conductivity type formed on the surface region of the semiconductor region 316 by the charge induced by the pinning layer 331 functions in the same way as the fourth semiconductor region 1315 (extension EP) described above. If the second conductivity type is p-type, the charge induced by the pinning layer 331 is a hole.

[0084] The configuration of the photoelectric converter 100 of the fifth embodiment will be described below with reference to Figure 17. The photoelectric converter 100 of the seventh embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the second configuration example described with reference to Figures 8, 9A, and 9B. Matters that overlap with those already described will be omitted from the explanation. The first to fourth embodiments can also be applied to the photoelectric converter 100 having the configuration of the second configuration example described with reference to Figures 8, 9A, and 9B. The uneven structure 325 shown in Figure 17 is the same as that in Figures 9A and 9B.

[0085] The configuration of the photoelectric converter 100 of the sixth embodiment will now be described with reference to Figure 18. The photoelectric converter 100 of the sixth embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The uneven structure 325 shown in Figure 18 is the same as the uneven structure 325 shown in Figures 7A and 7B, so its explanation will be omitted.

[0086] The fourth semiconductor region 1315 of the second conductivity type, which constitutes a part of the charge discharge section 1350, may include one or more protrusions P1 that project from the extension section EP toward the first surface S1. The one or more protrusions P1 are semiconductor regions of the second conductivity type. The impurity concentration of the second conductivity type in the one or more protrusions P1 may be lower than the impurity concentration of the second conductivity type in the extension section EP, or it may be the same as the impurity concentration of the second conductivity type in the extension section EP.

[0087] When the fourth semiconductor region 1315 of the second conductivity type includes a plurality of protrusions P1, the plurality of protrusions P1 may be arranged at a predetermined pitch. The direction of the predetermined pitch is, for example, perpendicular to the edge of the pixel array region 12, or parallel to the edge of the pixel array region 12. The predetermined pitch is preferably larger than the arrangement pitch of the plurality of pixels 101 in the pixel array region 12. The arrangement pitch of the plurality of protrusions P1 and the arrangement pitch of the plurality of third semiconductor regions 1311 may be the same or different. The plurality of protrusions P1 and the plurality of third semiconductor regions 1311 may be arranged alternately in a plan view.

[0088] The configuration of the photoelectric converter 100 of the seventh embodiment will now be described with reference to Figure 19. The photoelectric converter 100 of the seventh embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The uneven structure 325 shown in Figure 19 is the same as the uneven structure 325 shown in Figures 7A and 7B, so its explanation will be omitted.

[0089] The fourth semiconductor region 1315 of the second conductivity type, which constitutes part of the charge discharge section 1350, may include at least one second extension section EP2 arranged along the extension section EP between the extension section EP and the first surface S1 so as to be in contact with the extension section EP. The second extension section EP2 is a semiconductor region of the second conductivity type. The impurity concentration of the second conductivity type in the second extension section EP2 may be lower than or the same as the impurity concentration of the second conductivity type in the extension section EP. If the fourth semiconductor region 1315 of the second conductivity type includes multiple second extension sections EP2, the impurity concentration of the second conductivity type in the multiple second extension sections EP2 may decrease in steps as they move away from the second surface S2.

[0090] The configuration of the photoelectric converter 100 of the eighth embodiment will now be described with reference to Figure 20. The photoelectric converter 100 of the eighth embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The uneven structure 325 shown in Figure 20 is the same as the uneven structure 325 shown in Figures 7A and 7B, so its explanation will be omitted.

[0091] The fourth semiconductor region 1315 of the second conductivity type, which constitutes a part of the charge discharge section 1350, may include a plurality of first protrusions P1 that protrude from the extension section EP toward the first surface S1. The plurality of first protrusions P1 are semiconductor regions of the second conductivity type. The impurity concentration of the second conductivity type in the plurality of first protrusions P1 may be lower than the impurity concentration of the second conductivity type in the extension section EP, or it may be the same as the impurity concentration of the second conductivity type in the extension section EP.

[0092] Multiple first protrusions P1 may be arranged at a predetermined pitch. The direction of the predetermined pitch is, for example, perpendicular to the edge of the pixel array region 12, or parallel to the edge of the pixel array region 12. Preferably, the predetermined pitch is larger than the arrangement pitch of multiple pixels 101 in the pixel array region 12. The arrangement pitch of the multiple first protrusions P1 and the arrangement pitch of the multiple third semiconductor regions 1311 may be the same or different. The multiple first protrusions P1 and the multiple third semiconductor regions 1311 may be arranged alternately in a plan view.

[0093] The fourth semiconductor region 1315 of the second conductivity type, which constitutes a part of the charge discharge section 1350, may further include a plurality of second protrusions P2 that protrude from the extension section EP toward the first surface S1. The plurality of second protrusions P2 are semiconductor regions of the second conductivity type. The impurity concentration of the second conductivity type in the plurality of second protrusions P2 may be lower than the impurity concentration of the second conductivity type in the extension section EP, or it may be the same as the impurity concentration of the second conductivity type in the extension section EP.

[0094] Multiple second protrusions P2 may be arranged at a predetermined pitch. The direction of the predetermined pitch is, for example, perpendicular to the edge of the pixel array region 12, or parallel to the edge of the pixel array region 12. Preferably, the predetermined pitch is larger than the arrangement pitch of multiple pixels 101 in the pixel array region 12. The arrangement pitch of the multiple second protrusions P2 and the arrangement pitch of the multiple third semiconductor regions 1311 may be the same or different. Multiple second protrusions P2 and multiple third semiconductor regions 1311 may be arranged alternately in a plan view. Multiple first protrusions P1 and multiple second protrusions P2 may be arranged alternately in a plan view.

[0095] Multiple second protrusions P2 may be arranged such that their depth from the second surface S2 is smaller than that of multiple first protrusions P1, and they overlap with multiple third semiconductor regions 1311 in a plan view.

[0096] The configuration of the photoelectric converter 100 of the ninth embodiment will now be described with reference to Figure 21. The photoelectric converter 100 of the ninth embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The uneven structure 325 shown in Figure 21 is the same as the uneven structure 325 shown in Figures 7A and 7B, so its explanation will be omitted.

[0097] The fourth semiconductor region 1315 of the second conductivity type, which constitutes a part of the charge discharge section 1350, may include a plurality of protrusions P1 that project from the extension section EP toward the first surface S1. The plurality of protrusions P1 are semiconductor regions of the second conductivity type. The impurity concentration of the second conductivity type in the plurality of protrusions P1 may be lower than the impurity concentration of the second conductivity type in the extension section EP, or it may be the same as the impurity concentration of the second conductivity type in the extension section EP.

[0098] Multiple protrusions P1 may be arranged at a predetermined pitch. The direction of the predetermined pitch is, for example, perpendicular to the edge of the pixel array region 12, or parallel to the edge of the pixel array region 12. Preferably, the predetermined pitch is larger than the arrangement pitch of multiple pixels 101 in the pixel array region 12. The arrangement pitch of the multiple protrusions P1 and the arrangement pitch of the multiple third semiconductor regions 1311 may be the same or different. The multiple protrusions P1 and the multiple third semiconductor regions 1311 may be arranged alternately in a plan view. In one example, the shortest distance between the multiple third semiconductor regions 1311 and the first surface S1 is smaller than the maximum depth of the fifth semiconductor region 1313 of the first conductivity type from the first surface S1.

[0099] The configuration of the photoelectric converter 100 of the tenth embodiment will be described below with reference to Figure 22. The photoelectric converter 100 of the sixth embodiment provides an example in which a charge discharge unit 1350 is applied to the photoelectric converter 100 having the configuration of the first configuration example described with reference to Figures 6, 7A, and 7B. Matters that overlap with those already described will be omitted from the explanation. The uneven structure 325 shown in Figure 22 is the same as the uneven structure 325 shown in Figures 7A and 7B, so its explanation will be omitted.

[0100] The fourth semiconductor region 1315 of the second conductivity type, which constitutes a part of the charge discharge section 1350, may include a plurality of protrusions P1 that project from the extension section EP toward the first surface S1. One or more protrusions P1 are semiconductor regions of the second conductivity type. The impurity concentration of the second conductivity type in one or more protrusions P1 may be lower than the impurity concentration of the second conductivity type in the extension section EP, or it may be the same as the impurity concentration of the second conductivity type in the extension section EP.

[0101] In the direction of arrangement of the multiple protrusions P1 parallel to the first surface S1, the width W1 of each of the multiple protrusions P1 is greater than the width W2 of the second conductivity type pixel isolation region 314PX located between adjacent pixels 101 in the multiple pixels 101. Alternatively, in the said arrangement direction, the maximum width of each of the multiple protrusions P1 is greater than the maximum width of the second conductivity type pixel isolation region 314PX located between adjacent pixels 101 in the multiple pixels 101. Alternatively, in the said arrangement direction, the minimum width of each of the multiple protrusions P1 is greater than the minimum width of the second conductivity type pixel isolation region 314PX located between adjacent pixels 101 in the multiple pixels 101.

[0102] The following describes a photoelectric conversion system incorporating the photoelectric conversion device described exemplifiedly throughout the first to fifth embodiments. Figure 23 shows an example of a photoelectric conversion system. The photoelectric conversion device described in the first to fifth embodiments is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. A camera module equipped with an optical system such as a lens and an imaging device is also included in the photoelectric conversion system. The photoelectric conversion system is configured, for example, as an imaging system SYS. The imaging system SYS is an information terminal having a camera or imaging function. The imaging device IS may further include a package PKG that houses the photoelectric conversion device 100 configured as an imaging device IC. The package PKG may include a base on which the imaging device IC is fixed, a cover facing the imaging device IC, and connecting members that connect terminals provided on the base and terminals provided on the imaging device IC. The imaging device (IS) can also mount multiple imaging device ICs side-by-side in a common package (PKG). Furthermore, the imaging device (IS) can also mount imaging device ICs and other semiconductor device ICs in a common package (PKG).

[0103] The imaging system SYS may include an optical system OU that forms an image on the imaging device IS. The imaging system SYS may also include at least one of a control device CU that controls the imaging device IS, a processing device PU that processes signals obtained from the imaging device IS, and a display device DU that displays images obtained from the imaging device IS. The imaging system SYS may also include a storage device MU that stores images obtained from the imaging device IS.

[0104] Figure 24(a) illustrates the configuration of a photoelectric conversion system applied to an in-vehicle camera. The photoelectric conversion system 2300 may have a photoelectric conversion device 100 configured as an imaging device 2310. The photoelectric conversion system 2300 includes an image processing unit 2312 that performs image processing on a plurality of image data acquired by the imaging device 2310, and a parallax acquisition unit 2314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 2300. The photoelectric conversion system 2300 also includes a distance acquisition unit 2316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 2314 and the distance acquisition unit 2316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 2318 may use any of this distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware or by a software module. It may also be implemented by FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), or a combination thereof. The photoelectric conversion system 2300 is connected to the vehicle information acquisition device 2320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2300 is also connected to a control ECU 2330, which is a control unit that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 2318. The photoelectric conversion system 2300 is also connected to a warning device 2340 that issues a warning to the driver based on the judgment result of the collision judgment unit 2318. For example, if the collision judgment result of the collision judgment unit 2318 indicates a high probability of collision, the control ECU 2330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output.The warning device 2340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel. In this embodiment, the photoelectric conversion system 2300 images the area around the vehicle, for example, in front of or behind it. Figure 24(b) shows a photoelectric conversion system configured to image the area in front of the vehicle (image range 2350). The vehicle information acquisition device 2320 sends instructions to the photoelectric conversion system 2300 or the image acquisition device 2310. This configuration can further improve the accuracy of distance measurement. The above describes an example of control to prevent collision with other vehicles, but it can also be applied to control that automatically follows other vehicles or control that automatically stays within the lane. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0105] Figure 25 illustrates the configuration of a photoelectric conversion system configured as a distance image sensor. The distance image sensor 40 comprises an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. The distance image sensor 40 receives light (modulated light or pulsed light) that is projected from a light source device 409 toward the subject and reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0106] The optical system 407 is composed of one or more lenses and guides the image light (incident light) from the subject to the photoelectric converter 408, where it forms an image on the light-receiving surface (sensor part) of the photoelectric converter 408. The photoelectric converter 408 is one of the photoelectric converters from each of the embodiments described above, and a distance signal indicating the distance, which is determined from the light-receiving signal output from the photoelectric converter 408, is supplied to the image processing circuit 404.

[0107] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 408. The distance image (image data) obtained through this image processing is then supplied to the monitor 405 for display or supplied to the memory 406 for storage (recording). With the distance image sensor 40 configured in this way, by applying the aforementioned photoelectric converter, it is possible to acquire, for example, a more accurate distance image as the characteristics of the pixels improve.

[0108] Figure 26 illustrates the configuration of a photoelectric conversion system set up as an endoscopic surgical system. Figure 26 shows a surgeon (physician) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgical system 1150. As shown in the figure, the endoscopic surgical system 1150 consists of an endoscope 1100, surgical instruments 1110, and a cart 1134 equipped with various devices for endoscopic surgery.

[0109] The endoscope 1100 consists of a barrel 1101, the tip of which is inserted into the body cavity of the patient 1132 for a predetermined length, and a camera head 1102 connected to the base end of the barrel 1101. In the illustrated example, the endoscope 1100 is shown as a so-called rigid endoscope having a rigid barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0110] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 1101. A light source device 1203 is connected to the endoscope 1100, and the light generated by the light source device 1203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 1101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 1132. The endoscope 1100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0111] The camera head 1102 contains an optical system and a photoelectric converter. Reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter can be any of the photoelectric converters described in the embodiments described above. The image signal is transmitted as RAW data to the camera control unit (CCU) 1135.

[0112] The CCU1135 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 1100 and the display device 1136. Furthermore, the CCU1135 receives an image signal from the camera head 1102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0113] The display device 1136 displays an image based on an image signal processed by the CCU 1135, under control from the CCU 1135. The light source device 1203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 1100 when photographing the surgical area. The input device 1137 is an input interface to the endoscopic surgical system 1150. The user can input various information and instructions to the endoscopic surgical system 1150 via the input device 1137. The treatment instrument control device 1138 controls the drive of the energy treatment instrument 1112 for purposes such as tissue cauterization, incision, or blood vessel sealing.

[0114] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical area, can be composed of, for example, an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 1203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0115] Furthermore, the light source device 1203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 1102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0116] Furthermore, the light source device 1203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, by irradiating with narrowband light compared to the irradiation light used during normal observation (i.e., white light), predetermined tissues such as blood vessels on the surface of mucosa can be imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light can be irradiated onto body tissue and fluorescence from the body tissue can be observed, or a reagent such as indocyanine green (ICG) can be injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissue to obtain a fluorescence image. The light source device 1203 may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0117] Figure 27(a) illustrates the configuration of a photoelectric conversion system configured as eyeglasses 1600 (smart glasses). The eyeglasses 1600 have a photoelectric conversion device 1602 to which the photoelectric conversion device 100 is applied. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the embodiments described above. In addition, a display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. In addition, multiple types of photoelectric conversion devices may be used in combination. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in Figure 27(a).

[0118] The eyeglasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric converter 1602 and the display device. The control device 1603 also controls the operation of the photoelectric converter 1602 and the display device. The lens 1601 has an optical system formed therein for focusing light onto the photoelectric converter 1602.

[0119] Figure 27(b) illustrates the configuration of a photoelectric conversion system made up of eyeglasses 1610 (smart glasses). The eyeglasses 1610 have a control device 1612, which is equipped with a photoelectric conversion device equivalent to a photoelectric conversion device 1602 and a display device. The lens 1611 has an optical system formed therein for projecting light emitted from the photoelectric conversion device in the control device 1612 and from the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power supply that supplies power to the photoelectric conversion device and the display device, and also controls the operation of the photoelectric conversion device and the display device. The control device may have a gaze detection unit that detects the wearer's gaze. Gaze detection may use infrared light. The infrared light emitter emits infrared light towards the eyeball of the user who is fixating on the displayed image. An imaging unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction means that reduces the light from the infrared light emitter to the display unit in planar view, the deterioration of image quality is reduced.

[0120] The user's gaze towards a displayed image is detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using an image of the eyeball. As an example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used. More specifically, gaze detection processing based on the pupil-corneal reflection method is performed. Using the pupil-corneal reflection method, the user's gaze is detected by calculating a gaze vector representing the orientation (rotation angle) of the eyeball based on the pupil image and the Purkinje image contained in the image of the eyeball.

[0121] The display device of this embodiment includes a photoelectric converter having a light-receiving element, and may control the display image of the display device based on the user's gaze information from the photoelectric converter.

[0122] Specifically, the display device determines a first field of view that the user is fixated on, and a second field of view other than the first field of view, based on gaze information. The first and second field of view may be determined by the control device of the display device, or they may be determined by an external control device and received. Within the display area of ​​the display device, the display resolution of the first field of view may be controlled to be higher than that of the second field of view. In other words, the resolution of the second field of view may be lower than that of the first field of view.

[0123] Furthermore, the display area may have a first display area and a second display area different from the first display area, and a higher priority area may be determined from the first and second display areas based on line-of-sight information. The first and second field-of-sight areas may be determined by the control device of the display device, or they may be determined by an external control device and received. The resolution of the higher priority area may be controlled to be higher than the resolution of the areas other than the higher priority area. In other words, the resolution of areas with relatively lower priority may be set lower.

[0124] AI may be used to determine the first field of view area and the areas with higher priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eye, using the image of the eye and the direction the eye was actually looking in that image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If installed in an external device, it will be transmitted to the display device via communication.

[0125] When display control is based on visual detection, this method is preferably applicable to smart glasses that further include a photoelectric converter for capturing images of the surrounding environment. The smart glasses can display the captured external information in real time.

[0126] The photoelectric converter 100 of the above embodiment may be applied to electronic devices such as smartphones and tablets, as illustrated below. Figure 28 shows an example of the appearance of an electronic device 120 on which the photoelectric converter 100 configured as a solid-state imaging device is mounted. Figure 28A shows the front side of the electronic device 120, and Figure 28B shows the back side of the electronic device 120.

[0127] As shown in Figure 28A, a display 121 for displaying images is positioned in the center of the surface of the electronic device 120. Along the upper edge of the surface of the electronic device 120, front cameras 122-1 and 122-2, which use a photoelectric converter 100, an IR light source 123 that emits infrared light, and a visible light source 124 that emits visible light are positioned.

[0128] Furthermore, as shown in Figure 28B, rear cameras 125-1 and 125-2, which use the photoelectric converter 100, an IR light source 126 that emits infrared light, and a visible light source 127 that emits visible light are arranged along the upper edge of the back of the electronic device 120.

[0129] In the electronic device 120 configured in this way, by applying the photoelectric converter 100 described above, it is possible to capture, for example, images with higher sensitivity. The photoelectric converter 100 can also be applied to other electronic devices such as infrared sensors, distance measuring sensors using active infrared light sources, security cameras, and personal or biometric authentication cameras. This can improve the sensitivity and performance of these electronic devices. Furthermore, it is possible to reduce the power consumption of the system by reducing the power of the light source.

[0130] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0131] 12: Pixel array region, 13: Peripheral region, 301: Sensor substrate, 302: First semiconductor layer, 303: First wiring structure, S1: First surface, S2: Second surface, 311: First semiconductor region, 315: Second semiconductor region, 1311: Third semiconductor region, 1315: Fourth semiconductor region, 1313: Fifth semiconductor region

Claims

1. A photoelectric conversion device comprising a semiconductor layer including a pixel array region having multiple pixels and a peripheral region arranged around the pixel array region, and a wiring structure stacked on the semiconductor layer, The aforementioned peripheral region is the region between the outer edge of the pixel located at the outermost periphery of the pixel array region and the outer edge of the semiconductor layer. The semiconductor layer has a first surface and a second surface opposite to each other, the first surface being located on the wiring structure side of the second surface, Each pixel in the pixel array region includes a first semiconductor region of a first conductivity type arranged on the first surface side and a second semiconductor region of a second conductivity type arranged on the second surface side, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region. The peripheral region includes a third semiconductor region of a first conductivity type arranged on the side of the first surface, and a fourth semiconductor region of a second conductivity type arranged separately from the third semiconductor region, wherein the fourth semiconductor region includes an extension that extends parallel to the second surface, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region includes a portion extending from the second surface to the first surface, The separation region including the extended portion is located between the first semiconductor region and the third semiconductor region. A photoelectric conversion device characterized by the following features.

2. The voltage supplied between the third semiconductor region and the fourth semiconductor region is the predetermined voltage. The photoelectric conversion device according to feature 1.

3. The depth of the extension from the first surface is equal to the depth of the second semiconductor region from the first surface. The photoelectric conversion device according to claim 1 or 2.

4. The invention further comprises a pinning layer arranged in contact with the second semiconductor region and the extended portion. The photoelectric conversion device according to any one of claims 1 to 3.

5. The depth of the third semiconductor region from the first surface is equal to the depth of the first semiconductor region from the first surface. The photoelectric conversion device according to claim 1 or 2.

6. The fourth semiconductor region and the isolation region are electrically connected. The photoelectric conversion device according to any one of claims 1 to 5.

7. A groove is provided within the separation region, and an insulator is arranged so as to cover at least the inner surface of the groove. The photoelectric conversion device according to any one of claims 1 to 6.

8. The groove is arranged to penetrate the semiconductor layer. The photoelectric conversion device according to feature 7.

9. The groove is arranged to electrically separate the isolation region into a first isolation region on the pixel array region side and a second isolation region on the peripheral region side. The second separation region is the extended portion. The photoelectric conversion device according to feature 8.

10. A first conductive path that applies a potential to the first isolation region and a second conductive path that applies a potential to the second isolation region are provided within the wiring structure. The photoelectric conversion device according to feature 9.

11. The first conductive path and the second conductive path are electrically connected within the wiring structure. The photoelectric conversion device according to feature 10.

12. A groove is provided within the separation region. The present invention further comprises a pinning layer disposed so as to be in contact with the second semiconductor region and the fourth semiconductor region and so as to cover the surface of the groove. The photoelectric conversion device according to feature 6.

13. The pixel isolation region of the second conductivity type is arranged between adjacent pixels in the plurality of pixels. The photoelectric conversion device according to any one of claims 6 to 12, characterized in that it is a photoelectric conversion device.

14. The fourth semiconductor region further includes a protruding portion that extends from the extended portion toward the first surface. The photoelectric conversion device according to feature 13.

15. In the peripheral region, a plurality of third semiconductor regions, including the third semiconductor region, are arranged at a predetermined pitch. The fourth semiconductor region further includes a plurality of protrusions projecting toward the first surface from the extended portion, The plurality of protrusions are arranged at the predetermined pitch. The photoelectric conversion device according to feature 14.

16. The plurality of third semiconductor regions and the plurality of protrusions are arranged alternately in a plan view. The photoelectric conversion device according to feature 15.

17. The fourth semiconductor region further includes a plurality of second protrusions projecting toward the first surface from the extended portion, The plurality of second protrusions are arranged at the predetermined pitch, The plurality of protrusions and the plurality of second protrusions are arranged alternately in a plan view. The photoelectric conversion device according to feature 15.

18. The plurality of second protrusions are arranged such that their depth from the second surface is smaller than that of the plurality of protrusions, and they overlap with the plurality of third semiconductor regions in a plan view. The photoelectric conversion device according to feature 17.

19. In the direction parallel to the first surface and in the direction of the arrangement of the plurality of protrusions, the width of each of the plurality of protrusions is greater than the width of the pixel separation region. The photoelectric conversion device according to any one of claims 15 to 18.

20. The fourth semiconductor region further includes at least one second extension disposed along the extension between the extension and the first surface so as to be in contact with the extension, The photoelectric conversion device according to any one of claims 15 to 19, characterized by the features described herein.

21. The peripheral region further includes a fifth semiconductor region of a first conductivity type, which is located between the third semiconductor region and the fourth semiconductor region, in contact with the third semiconductor region, and has a lower impurity concentration of the first conductivity type than the first semiconductor region. A photoelectric conversion device according to any one of claims 1 to 20.

22. The fifth semiconductor region is arranged to surround the third semiconductor region. The photoelectric conversion device according to feature 21.

23. Further comprising a light-shielding film disposed on the second surface, The light-shielding film is electrically connected to the fourth semiconductor region. The photoelectric conversion device according to any one of claims 1 to 22.

24. The peripheral region is provided with a plurality of third semiconductor regions, including the third semiconductor region, arranged at a predetermined pitch. The predetermined pitch is larger than the array pitch of the plurality of pixels. The photoelectric conversion device according to any one of claims 1 to 23.

25. The fourth semiconductor region of the second conductivity type is formed by charges induced near the second surface in the semiconductor layer by a pinning layer arranged along the second surface. The photoelectric conversion device according to any one of claims 1 to 3.

26. The end of the extended portion is spaced apart from the first surface. The photoelectric conversion device according to any one of claims 1 to 25.

27. A photoelectric conversion device according to any one of claims 1 to 26, A photoelectric conversion system characterized by having a signal processing unit that processes the signal output by the aforementioned photoelectric conversion device.

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