Display board and its driving method, display device

Abstract

The display substrate (100) includes a plurality of data lines (DL) extending in a first direction (Y) and a plurality of sub-pixels (2). The sub-pixels (2) include a pixel driving circuit (21) and a light-emitting element (22). The pixel driving circuit (21) includes a current control circuit (211) and a duration control circuit (212) electrically connected to the current control circuit (211) and the light-emitting element (22). The current control circuit (211) is configured to generate a drive signal to drive the light-emitting element (22) to emit light. The duration control circuit (212) is configured to generate a duration control signal to control the duration of conduction between the current control circuit (211) and the light-emitting element (22). The current control circuit (211) and the duration control circuit (212) are electrically connected to the same data line.

Description

[Technical Field]

[0001] This disclosure relates to the field of display technology, and more particularly to display substrates and their driving methods, and display devices. [Background technology]

[0002] The display market is currently developing rapidly, and as consumer demand for a wide range of display products such as laptops, smartphones, televisions, tablets, smartwatches, and fitness wristbands increases, we can expect to see many more new display products emerge in the future. [Overview of the project] [Means for solving the problem]

[0003] In one embodiment, a display board is provided. The display board comprises a plurality of data lines extending in a first direction and a plurality of subpixels. Each subpixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes a current control circuit and a duration control circuit electrically connected to the current control circuit and the light-emitting element. The current control circuit is configured to generate a driving signal to drive the light emission of the light-emitting element. The duration control circuit is configured to generate a duration control signal to control the duration of conduction between the current control circuit and the light-emitting element. The current control circuit and the duration control circuit are electrically connected to the same data line.

[0004] In some embodiments, the plurality of subpixels are arranged in multiple columns along a second direction. The same data line is electrically connected to at least one column of subpixels.

[0005] In some embodiments, at least one row of subpixels is placed between any two adjacent data lines.

[0006] In some embodiments, the display board further comprises a multi-output selection circuit electrically connected to the plurality of data lines, a plurality of data transmission lines electrically connected to the multi-output selection circuit, and a plurality of selection signal lines electrically connected to the multi-output selection circuit. The multi-output selection circuit is configured to transmit data signals transmitted by the plurality of data transmission lines to the plurality of data lines in a time-sharing manner, under the control of selection signals transmitted by the plurality of selection signal lines.

[0007] In some embodiments, the plurality of data lines include at least a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines. The plurality of data transmission lines include at least a plurality of first data transmission lines, a plurality of second data transmission lines, and a plurality of third data transmission lines. The multi-output selection circuit includes a plurality of selection transistor groups electrically connected to the selection signal lines, first data lines, second data lines, and third data lines. The first data transmission line is electrically connected to at least two selection transistor groups and electrically connected to the corresponding first data line via the at least two selection transistor groups. The second data transmission line is electrically connected to at least two selection transistor groups and electrically connected to the corresponding second data line via the at least two selection transistor groups. The third data transmission line is electrically connected to at least two selection transistor groups and electrically connected to the corresponding third data line via the at least two selection transistor groups.

[0008] In some embodiments, the first data transmission line, the second data transmission line, and the third data transmission line are arranged periodically, and / or the first data line, the second data line, and the third data line are arranged periodically.

[0009] In some embodiments, the group of selection transistors includes at least a first selection transistor, a second selection transistor, and a third selection transistor. The control electrode of the first selection transistor is electrically connected to the selection signal line, the first electrode of the first selection transistor is electrically connected to the first data transmission line, and the second electrode of the first selection transistor is electrically connected to the first data line. The control electrode of the second selection transistor is electrically connected to the selection signal line, the first electrode of the second selection transistor is electrically connected to the second data transmission line, and the second electrode of the second selection transistor is electrically connected to the second data line. The control electrode of the third selection transistor is electrically connected to the selection signal line, the first electrode of the third selection transistor is electrically connected to the third data transmission line, and the second electrode of the third selection transistor is electrically connected to the third data line.

[0010] In some embodiments, the same data line is electrically connected to a row of subpixels.

[0011] In some embodiments, the same data line is electrically connected to at least two rows of subpixels. The display substrate is 2 It further comprises a plurality of gate lines extending in the direction. One subpixel is electrically connected to one gate line. The plurality of subpixels are the 1 They are arranged in multiple rows along the direction. Each row of subpixels is electrically connected to at least two gate lines. The at least two gate lines are time-shared by the row of subpixels. multiple To control the reception of data signals transmitted via data lines, the system is configured to transmit scan signals to corresponding subpixels.

[0012] In some embodiments, the number of columns of subpixels electrically connected to the same data line is equal to the number of gate lines electrically connected to the subpixels in the same row.

[0013] In some embodiments, the at least two gate lines are arranged on opposite sides of the row of subpixels.

[0014] In some embodiments, within the same row of subpixels, any two adjacent subpixels are electrically connected to different gate lines.

[0015] In some embodiments, the display board further comprises a base on which the plurality of data lines and the plurality of subpixels are arranged on one side, and a plurality of connection wires provided on the edge of the base. One end of the connection wire is electrically connected to at least one of the data lines, and the other end of the connection wire extends to the other side of the base. If the display board further comprises a multi-output selection circuit and a plurality of data transmission lines, one end of the connection wire is electrically connected to a data transmission line and electrically connected to the plurality of data lines via the multi-output selection circuit.

[0016] In some embodiments, the current control circuit is electrically connected to at least a scan signal terminal, a data signal terminal, a first enable signal terminal, a first voltage signal terminal, and a first node. The current control circuit is configured to generate a drive signal in response to a scan signal received at the scan signal terminal, a data signal received at the data signal terminal, a first enable signal received at the first enable signal terminal, and a first voltage signal received at the first voltage signal terminal. The duration control circuit is electrically connected to at least the data signal terminal, a first reset signal terminal, a second reset signal terminal, a first enable signal terminal, a second enable signal terminal, a first node, and the light-emitting element. The duration control circuit is configured to control the duration of conduction between the first node and the light-emitting element based on a second enable signal received at the second enable signal terminal in response to the data signal and a first reset signal received at the first reset signal terminal, or to control the duration of conduction between the first node and the light-emitting element based on a first enable signal in response to the data signal and a second reset signal received at the second reset signal terminal. Both the current control circuit and the duration control circuit communicate via the data signal terminal. identical It is electrically connected to the data line.

[0017] In some embodiments, the active level period of the first reset signal and the active level period of the second reset signal do not overlap. In the data signal, one of the levels corresponding to the active level of the first reset signal and the level corresponding to the active level of the second reset signal is an active level.

[0018] In some embodiments, during the stage of generating the drive signal, the period during which the data signal level becomes active is shorter than the period during which the scan signal level becomes active.

[0019] In some embodiments, the duration control circuit includes a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit. The first control sub-circuit is electrically connected to at least the data signal terminal, the first reset signal terminal, the second enable signal terminal, and the second node. The first control sub-circuit is configured to transmit the second enable signal to the second node in response to the data signal and the first reset signal. The second control sub-circuit is electrically connected to at least the data signal terminal, the second reset signal terminal, the first enable signal terminal, and the second node. The second control sub-circuit is configured to transmit the first enable signal to the second node in response to the data signal and the second reset information. The third control sub-circuit is electrically connected to the first node, the second node, and the light emitting element. The third control sub-circuit is configured to control the duration of conduction between the first node and the light emitting device under the control of a signal from the second node.

[0020] In some embodiments, the first control subcircuit includes a first transistor, a second transistor, and a first capacitor. The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the second enable signal terminal, and the second electrode of the second transistor is electrically connected to the second node. The first electrode of the first capacitor is electrically connected to the initial signal terminal, and the second electrode of the first capacitor is electrically connected to the third node. The second control subcircuit includes a third transistor, a fourth transistor, and a second capacitor. The control electrode of the third transistor is electrically connected to the second reset signal terminal, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third diode is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the first enable signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node. The first electrode of the second capacitor is electrically connected to the initial signal terminal, and the second electrode of the second capacitor is electrically connected to the fourth node. The third control subcircuit includes a fifth transistor. The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the light-emitting element.

[0021] In some embodiments, the current control circuit includes a data writing sub-circuit, a driving sub-circuit, a compensation sub-circuit, and a light emission control sub-circuit. The data writing sub-circuit is electrically connected to the scanning signal terminal, the data signal terminal, and the fifth node. The data writing sub-circuit is configured to transmit the data signal to the fifth node under the control of the scanning signal. The driving sub-circuit is at least electrically connected to the first node, the fifth node, and the sixth node. The driving sub-circuit is configured to transmit a signal from the fifth node to the first node under the control of the voltage of the sixth node. The compensation sub-circuit is electrically connected to the scanning signal terminal, the first node, and the sixth node. The compensation sub-circuit is configured to transmit a signal from the first node to the sixth node under the control of the scanning signal to compensate the threshold voltage for the driving sub-circuit. The light emission control sub-circuit is electrically connected to the first enable signal terminal, the first voltage signal terminal, and the fifth node. The light emission control sub-circuit is configured to transmit the first voltage signal to the fifth node under the control of the first enable signal.

[0022] In some embodiments, the data writing subcircuit includes a sixth transistor. The control electrode of the sixth transistor is electrically connected to the scan signal terminal, the first electrode of the sixth transistor is electrically connected to the data signal terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node. The drive subcircuit includes a seventh transistor and a third capacitor. The control electrode of the seventh transistor is electrically connected to the sixth node, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the first node. The first electrode of the third capacitor is electrically connected to the sixth node, and the second electrode of the third capacitor is electrically connected to the first voltage signal terminal. The compensation subcircuit includes an eighth transistor. The control electrode of the eighth transistor is electrically connected to the scan signal terminal, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the sixth node. The light emission control subcircuit includes a ninth transistor. The control electrode of the ninth transistor is electrically connected to the first enable signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the ninth transistor is electrically connected to the fifth node.

[0023] In some embodiments, the current control circuit further includes a reset subcircuit. The reset subcircuit is electrically connected to the first reset signal terminal, the initial signal terminal, the sixth node, and the light-emitting element. The reset subcircuit is configured to transmit an initial signal received at the initial signal terminal to the sixth node and the light-emitting element in response to the first reset signal.

[0024] In some embodiments, the reset subcircuit includes a tenth transistor and an eleventh transistor. The control electrode of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the initial signal terminal, and the second electrode of the tenth transistor is electrically connected to the sixth node. The control electrode of the eleventh transistor is electrically connected to the first reset signal terminal, the first electrode of the eleventh transistor is electrically connected to the initial signal terminal, and the second electrode of the eleventh transistor is electrically connected to the light-emitting element.

[0025] In another embodiment, a method for driving a display board is provided. The driving method is used to drive any of the display boards in the above embodiments. The driving method transmits data signals to a plurality of data lines of the display board. The aforementioned subpixel The aforementioned Current control circuit and The aforementioned Data signal by duration control circuit Receive Prepare to believe.

[0026] In some embodiments, the current control circuit includes a data writing subcircuit, a drive subcircuit, a compensation subcircuit, and a light emission control subcircuit. The duration control circuit includes a first control subcircuit, a second control subcircuit, and a third control subcircuit. In the display phase of one frame: , the Stage 1, Stage 2, Stage 3, and Stage 4 further include If the grayscale level displayed by the subpixels of the display board is equal to or greater than the threshold grayscale level, The aforementioned drive method is In the first stage, the first control subcircuit is shut off in response to the first reset signal and the data signal received at the first reset signal terminal. In the second stage, the second control subcircuit is opened in response to the second reset signal and the data signal received at the second reset signal terminal, and the first enable signal received at the first enable signal terminal is transmitted to the second node. This includes If the grayscale level displayed by the subpixels of the display board is less than the threshold grayscale level, The aforementioned drive method isIn the first stage, in response to the first reset signal and the data signal, the first control subcircuit is turned on and the second enable signal received at the second enable signal terminal is transmitted to the second node. In the second stage, in response to the second reset signal and the data signal, the second control subcircuit is turned off. In the third stage, in response to the scan signal received at the scan signal terminal, the data writing subcircuit and the compensation subcircuit are turned on and the data signal is transmitted to the sixth node sequentially via the fifth node, the drive subcircuit, the first node, and the compensation subcircuit to compensate the drive subcircuit for a threshold voltage. In the fourth stage, in response to the first enable signal, the light emission control subcircuit is turned on and the first voltage signal received at the first voltage signal terminal is transmitted to the first node sequentially via the fifth node and the drive subcircuit. including .

[0027] In some embodiments, the data line is configured to store the data signal. The scan signal terminal is configured to transmit the scan signal in the third step, after the data line has stored the data signal, in order to control the conduction between the data writing subcircuit and the supplementary subcircuit.

[0028] In another embodiment, a display device is provided, comprising at least one display board as described in any of the above embodiments.

[0029] In some embodiments, the display board comprises a base and a plurality of connection wires provided on the edge of the base. One end of the plurality of connection wires is located on one side of the base, and the other end of the plurality of connection wires extends to the other side of the base. The display device further comprises a drive chip provided on the other side of the base. The drive chip is electrically connected to the other end of the plurality of connection wires. [Brief explanation of the drawing]

[0030] To better illustrate the inventions in this disclosure, the drawings used in some embodiments of this disclosure are briefly described below. Clearly, the drawings described below are only those for some embodiments of this disclosure, and those skilled in the art can derive other drawings based on these. Furthermore, the drawings in the following description can be considered schematic diagrams, but are not limited to the actual dimensions of the products, the actual processes of the methods, and the actual timing of the signals in the embodiments of this disclosure. [Figure 1] This is a configuration diagram of a display board according to one embodiment. [Figure 2] This is a timing chart corresponding to the display board shown in Figure 1, according to one embodiment. [Figure 3] This is another timing chart corresponding to the display board shown in Figure 1, according to one embodiment. [Figure 4] This is another timing chart corresponding to the display board shown in Figure 1, according to one embodiment. [Figure 5] This is a configuration diagram of a display board according to some embodiments of the present disclosure. [Figure 6] This is a structural diagram of a subpixel according to some embodiments of the present disclosure. [Figure 7] This is a circuit diagram of a subpixel according to some embodiments of the present disclosure. [Figure 8] This is a distribution diagram of pads and pixel driving circuits according to some embodiments of the present disclosure. [Figure 9] This is another distribution diagram of pads and pixel driving circuits according to some embodiments of the present disclosure. [Figure 10] This is a timing chart corresponding to the subpixels of the circuit diagram shown in Figure 7, relating to some embodiments of the present disclosure. [Figure 11] This is another timing chart corresponding to the subpixels of the circuit diagram shown in Figure 7, relating to some embodiments of the present disclosure. [Figure 12] This is a configuration diagram of yet another display board according to some embodiments of the present disclosure. [Figure 13] This is a configuration diagram of yet another display board according to some embodiments of the present disclosure. [Figure 14] This is a timing chart corresponding to the display board shown in Figure 13, according to some embodiments of the present disclosure. [Figure 15] This is another timing chart corresponding to the display board shown in Figure 13, according to some embodiments of the present disclosure. [Figure 16] This is a structural diagram of yet another display substrate relating to some embodiments of the present disclosure. [Figure 17] This is a structural diagram of yet another display substrate relating to some embodiments of the present disclosure. [Figure 18] This is a timing chart corresponding to the display board shown in Figure 17, according to some embodiments of the present disclosure. [Figure 19] This is a structural diagram of yet another display substrate relating to some embodiments of the present disclosure. [Figure 20] This is a structural diagram of yet another display substrate relating to some embodiments of the present disclosure. [Figure 21] This is a diagram illustrating the configuration of a display device according to some embodiments of the present disclosure. [Figure 22] This is a configuration diagram of another display device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0031] Hereinafter, several embodiments of this disclosure will be clearly and completely described with reference to the drawings. Of course, the embodiments described herein are only a selection of, and not all, embodiments of this disclosure. All other embodiments that a person skilled in the art could conceive of based on the embodiments of this disclosure are included within the scope of this disclosure.

[0032] Unless otherwise indicated in the context, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted in an open, comprehensive sense, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties related to this embodiment or its examples are included in at least one embodiment or example of the present disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any specific features, structures, materials, or properties described may be included in any one or more embodiments or examples in any suitable manner.

[0033] In the following, the terms “first” and “second” are merely for illustrative purposes and should not be understood as indicating or implying relative importance or the quantity of the indicated technical features. Accordingly, features defined as “first” and “second” may explicitly or implicitly include one or more such features. In the description of the embodiments of this disclosure, unless otherwise specified, “multiple” means two or more.

[0034] The term "connection" and related expressions may be used when describing certain embodiments. For example, the term "connection" may be used when describing certain embodiments to indicate that two or more components have direct physical or electrical contact with one another.

[0035] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0036] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, the term “case” is optionally interpreted, depending on the context, to mean “when…” or “on the occasion of…” or “in response to a decision” or “in response to detection.” Similarly, depending on the context, the phrases “when…is determined” or “when [the described condition or event] is detected” are optionally interpreted to mean “when…is determined,” or “in response to a decision of…” or “when [the described condition or event] is detected.”

[0038] In this specification, “applicable to…” or “configured to…” means an open and inclusive language that does not exclude devices applied to or configured to perform additional tasks or steps.

[0039] Furthermore, the use of “based on” implies that any process, step, calculation, or other action performed “based on” one or more of the aforementioned conditions or values ​​may, in practice, be based on exceeding additional conditions or values, thus being open and inclusive.

[0040] As used herein, “approximate” or “about” includes the stated value and the mean value within an acceptable range of deviation of a particular value, where the acceptable range of deviation is determined taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., limitations of the measurement system) as considered by those skilled in the art.

[0041] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. The exemplary embodiments of this disclosure should be interpreted as including deviations in shape due to manufacturing, etc., and are not limited to the shapes of the regions illustrated herein. For example, an etching region shown as a rectangle typically has curved characteristics. Accordingly, the regions shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of the regions in the equipment, nor are they intended to limit the scope of the exemplary embodiments.

[0042] The transistors used in the circuits provided in the embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices having the same characteristics. In the embodiments of this disclosure, thin-film transistors will be described as examples.

[0043] In some embodiments, each transistor used in each circuit has a control electrode that is the gate of the transistor, a first electrode that is one of the source and drain of the transistor, and a second electrode that is the other of the drain and source of the transistor. The source and drain of the transistor may be structurally symmetrical, and therefore may not be structurally distinguishable. That is, the first and second electrodes of the transistor in embodiments of this disclosure may not be structurally distinguishable. For example, if the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode of the transistor is the drain. For example, if the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode of the transistor is the source.

[0044] In the circuits provided in the embodiments of this disclosure, “nodes” do not represent actual components, but rather the junctions of related electrical connections in the schematic. In other words, these nodes are equivalent to nodes of correlated electrical connections in the schematic.

[0045] The transistors included in the circuits provided in the embodiments of this disclosure may all be N-type transistors or P-type transistors. Alternatively, some of the transistors included in each circuit may be N-type transistors and some of the transistors may be P-type transistors.

[0046] In this disclosure, “active level” means the level at which the transistor can conduct electricity.

[0047] The following explanation assumes that all transistors in each circuit provided in the embodiments of this disclosure are P-type transistors (in this case, the active level is low). By using the same conduction type for the transistors in each circuit described below, the process flow can be simplified, the difficulty of the process can be reduced, and the productivity of the product (e.g., display board 100 and display device 1000) can be improved.

[0048] In some embodiments of this disclosure, a display board 100, a method for driving the display board, and a display device 1000 are provided. The display board 100, the method for driving the display board, and the display device 1000 will be described below, respectively.

[0049] As shown in Figures 21 and 22, in some embodiments of the present disclosure, a display device 1000 is provided. The display device 1000 may be any device that displays moving images (e.g., video) or still images (e.g., still images), and may display text or graphics. More specifically, it is expected that the embodiments described may be implemented in or associated with various electronic devices. The various electronic devices mentioned above include, but are not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigation devices, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automobile displays (e.g., odometer displays), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays for rear-view cameras in vehicles), electrophotography, electronic signs or indicators, projectors, architectural structures, and packaging and aesthetic structures (e.g., displays for displaying images of jewelry).

[0050] In some embodiments, as shown in Figure 21, the display device 1000 may include at least one display board 100. That is, the display device 1000 may include a single display board 100 or a plurality of display boards 100.

[0051] As shown in Figure 21, if the display device 1000 includes a plurality of display boards 100, the plurality of display boards 100 may be arranged in a splicing manner with respect to each other so that the display device 1000 has a large screen size. In this case, the display boards 100 may be called splicing display boards, and the display device 1000 may be called a splicing display device.

[0052] Of course, as shown in Figure 22, the display device 1000 may further include, for example, a drive chip 200 and other electronic components.

[0053] Exemplary, the drive chip 200 may include, but is not limited to, a source drive circuit for supplying data signals or a power supply circuit for supplying a first voltage signal.

[0054] In some embodiments, as shown in Figure 5, the display board 100 includes a base 1, a plurality of subpixels 2, a plurality of data lines DL, and a plurality of gate lines GL.

[0055] The types of Base 1 described above vary and may be set as needed.

[0056] For example, base 1 may be a rigid base. Examples of materials for the rigid base include glass, quartz, and plastic.

[0057] For example, base 1 may be a flexible base. Examples of flexible base materials include polyethylene terephthalate (PET), polyethylene naphthalate two formiCacid glycol ester (PEN), or polyimide (PI).

[0058] In some examples, the plurality of sub-pixels 2, the plurality of data lines DL, and the plurality of gate lines GL are all disposed on one side of the base 1. The plurality of data lines DL may extend in the first direction Y, and the plurality of gate lines GL may extend in the second direction X. Each sub-pixel 2 is electrically connected to one data line DL and one gate line GL.

[0059] In some examples, as shown in FIG. 5, the plurality of sub-pixels 2 are arranged in a plurality of columns along the second direction X and in a plurality of columns along the first direction X. The number of sub-pixels 2 included in any two adjacent columns of sub-pixels may be the same or different. Also, the number of sub-pixels 2 included in any two adjacent rows of sub-pixels may be the same or different.

[0060] Here, the first direction Y and the second direction X intersect each other. The angle between the first direction Y and the second direction X may be set according to actual needs. Exemplarily, the angle between the first direction Y and the second direction X may be 85°, 88°, 90°, 92° or 95°.

[0061] Exemplarily, the plurality of sub-pixels 2 may include sub-pixels of multiple colors. For example, the plurality of sub-pixels 2 may include red sub-pixels, green sub-pixels, and blue sub-pixels. Of course, the plurality of sub-pixels 2 may also include, for example, white sub-pixels. When the plurality of sub-pixels 2 include red sub-pixels, green sub-pixels, and blue sub-pixels, these three sub-pixels may be arranged horizontally, vertically, or in a "pin" shape. When the sub-pixels 2 include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, these four sub-pixels may be arranged horizontally, vertically, in an array, etc. The present disclosure is not limited thereto.

[0062] In some examples, as shown in FIGS. 5 and 6, in the plurality of sub-pixels 2, each sub-pixel 2 may include a pixel driving circuit 21 and a light-emitting element 22 electrically connected to the pixel driving circuit. The pixel driving circuit 21 may supply a driving signal to the light-emitting element 22 to drive the light emission of the light-emitting element 22.

[0063] Here, the light-emitting element 22 may emit light of different colors depending on the color of the subpixel.

[0064] For example, the light-emitting element 22 in the red subpixel may emit red light, the light-emitting element 22 in the green subpixel may emit green light, the light-emitting element 22 in the blue subpixel may emit blue light, and the light-emitting element 22 in the white subpixel may emit white light.

[0065] Furthermore, for example, the light-emitting elements 22 in the red subpixel, green subpixel, blue subpixel, and white subpixel may all emit blue light. In this case, the red subpixel, green subpixel, and white subpixel may convert the blue light into red light, green light, and white light, respectively, according to the corresponding color conversion material (such as quantum dot material or phosphor material). In this way, it is possible to emit light of the corresponding colors, such as red light, green light, blue light, and white light.

[0066] In other words, the arrangement method of the subpixel 2 can refer to the arrangement method of the light-emitting element 22.

[0067] For example, the light-emitting element 22 is a current-driven element. The light-emitting device 22 may be of various types and may be installed as needed.

[0068] For example, the above-mentioned light-emitting element 22 is As Light Emitting Diodes (LEDs) Micro Light Emitting Diodes (micro LEDs) or Mini Light Emitting Diodes (Mini LEDs) That is .

[0069] When the light-emitting element 22 emits light, the brightness of the light-emitting element 22 is related to the current amplitude of the received drive signal (i.e., current signal) and the duration of the received drive signal.

[0070] For example, if the duration of the drive signal received by the light-emitting element 22 is constant, the brightness of the light-emitting element 22 increases as the current amplitude of the drive signal increases, and decreases as the current amplitude of the drive signal decreases. If the current amplitude of the drive signal received by the light-emitting element 22 is constant, the brightness of the light-emitting element increases as the duration of the drive information received by the light-emitting element 22 increases, and decreases as the duration of the drive signal received by the light-emitting element 22 decreases.

[0071] However, under driving conditions with a low current density drive signal (i.e., a small current amplitude of the drive signal), the light-emitting element 22 is prone to color coordinate offset and low external quantum efficiency, resulting in poor brightness uniformity of the display substrate 100. In other words, it is difficult to accurately display low gradations by simply controlling the current amplitude of the drive signal. Therefore, when controlling the current amplitude of the drive signal, the duration of the drive signal supplied to the light-emitting element 22 can be controlled to accurately display low gradations.

[0072] In some examples, as shown in Figures 5 and 6, the pixel driving circuit 21 includes a current control circuit 211 and a duration control circuit 212 that is electrically connected to the current control circuit 211 and the light-emitting element 22. The current control circuit 211 is configured to generate a drive signal to drive the light emission of the light-emitting element 22. The duration control circuit 212 is configured to generate a duration control signal to control the duration of conduction between the current control circuit 211 and the light-emitting element 22.

[0073] For example, the current control circuit 211 can generate a drive signal, and the light-emitting element 22 can emit light in response to this drive signal. The current amplitude of this drive signal is variable, and accordingly, the brightness of the light emitted by the light-emitting element 22 is also variable. By adjusting the current amplitude of the drive signal from the current control circuit 211, the light-emitting element 22 may display different grayscale levels.

[0074] For example, the duration control circuit 212 is provided between the current control circuit 211 and the light-emitting element 22. The duration control circuit 212 can control whether or not there is conduction between the current control circuit 211 and the light-emitting element 22. That is, when the duration control circuit 212 is not generating a duration control signal, the current control circuit 211 and the light-emitting element 22 are turned off, i.e., there is no conduction. Even if the current control circuit 211 generates a drive signal, it is difficult to apply this drive signal to the light-emitting element 22.

[0075] Furthermore, the duration control signal generated by the duration control circuit 212 can control the duration of conduction between the current control circuit 211 and the light-emitting element 22. That is, when the level of the duration control signal is at an active level, the current control circuit 211 and the light-emitting element 22 can be electrically connected to form a path. When the level of the duration control signal is at an inactive level, the current control circuit 211 and the light-emitting element 22 are turned off. Here, the duty cycle of the duration control signal is variable. That is, the duration for which the level of the duration control signal is at an active level is variable. By adjusting the duty cycle of the duration control signal, the duration of conduction between the current control circuit 211 and the light-emitting element 22 can be adjusted, and furthermore, the brightness duration of the light-emitting element 22 can be adjusted so that the light-emitting element 22 displays different grayscale levels.

[0076] In other words, in this disclosure, the duration control signal generated by the duration control circuit 212 controls the duration for which this drive signal is transmitted to the light-emitting element 22 based on the drive signal having a high current amplitude generated by the current control circuit 211. Together, these control the brightness of the light-emitting element 22, thereby improving the brightness uniformity of the display substrate 100 and enhancing the display effect of the display substrate.

[0077] Here, the range of the high current amplitude of the drive signal may be the range in which the light-emitting element 22 operates at a main wavelength that provides stable high luminous efficiency, good color coordinate uniformity, and stable emission. Therefore, the range of the current amplitude of the drive signal may be the same whether the gradation displayed by the light-emitting device 22 is high gradation or low gradation.

[0078] In one embodiment, as shown in FIG. 1, the sub-pixel has data signal terminals electrically connected to two types of pixel driving circuits, namely, a current data signal terminal electrically connected to a current control circuit and a duration data signal terminal electrically connected to a duration control circuit. The current control circuit can control the current amplitude of the driving signal based on the current data signal transmitted from the current data signal terminal, and the duration control circuit can select the duty ratio of the duration control signal based on the duration data signal transmitted from the duration data signal terminal. Therefore, the data lines included in the display substrate may include a current data line DI electrically connected to the current data signal terminal and a duration data line DT electrically connected to the duration data signal terminal. The i-th current data line DI i and the i-th duration data line DT i are located on opposite sides of the sub-pixels in the i-th column, and two data lines are provided between the sub-pixels in the i-th column and the sub-pixels in the (i + 1)-th column. These two data lines are, for example, the i-th duration data line DT i and the (i + 1)-th current data line DI i+1 , or the i-th current data line DI i and the (i + 1)-th duration data line DT i+1 may also be used. n and i are positive integers.

[0079] For example, between the sub-pixels in the i-th column and the sub-pixels in the (i + 1)-th column, the i-th duration data line DT i and the (i + 1)-th current data line DI i+1 are arranged. The inventors have found that after the current data signal required for a certain sub-pixel among the sub-pixels in the (i + 1)-th column is written into the (i + 1)-th current data line DI i+1 , the (i + 1)-th current data line DI i+1 is in a floating state. In this process, the level of the duration data signal written into the i-th duration data line DT i may change. In this case, the (i + 1)-th current data line DI i+1The current data signal changes due to the change in the level of this duration data signal, which in turn causes a change in the drive signal of a certain subpixel in the (i+1) column's subpixel control circuit. As a result, the brightness displayed by a certain subpixel in the (i+1) column changes, causing a brightness difference problem in the column direction.

[0080] For example, the i-th duration data line DT i The level of the duration data signal written to it is changed from high level to low level. Therefore, the (i+1)th current data line DI i+1 The level of the current data signal in this column is pulled down, and the current amplitude of the drive signal generated by the current control circuit of a certain subpixel in the (i+1) column increases. As a result, the brightness displayed by a certain subpixel in the (i+1) column increases, causing a brightness difference problem in the column direction.

[0081] Based on this, in some examples, as shown in Figure 5, in the subpixel 2 provided in this disclosure, the current control circuit 211 and the duration control circuit 212 are electrically connected to the same data line DL. The current control circuit 211 and the duration control circuit 212, electrically connected to the same data line DL, belong to the same pixel driving circuit 21 of the subpixel 2.

[0082] In other words, in this disclosure, the same subpixel 2 is electrically connected to the same data line DL, and the data signal transmitted by this same data line DL is controlled by the current control circuit 211 and the duration control circuit 212. To You may send it.

[0083] For example, since the current control circuit 211 and the duration control circuit 212 of the same subpixel 2 receive the same data signal, in this disclosure the active level of the data signal is written to the current control circuit 211 and the duration control circuit 212 in a time-sharing manner.

[0084] For example, the active level of the data signal written to the current control circuit 211 may be called the first active level, and the active level of the data signal written to the duration control circuit 212 may be called the second active level. In the display stage of one frame, first, a data signal having the second active level may be written to the duration control circuit 212, thereby causing the duration control circuit 212 to generate a duration control signal (the duty cycle of this duration control signal depends on the grayscale level that the subpixel 2 needs to display). Next, a data signal having the first active level may be written to the current control circuit 211, thereby causing the current control circuit 211 to generate a drive signal (the current amplitude of this drive signal depends on the grayscale level that the subpixel 2 needs to display).

[0085] In this disclosure, identical subpixels 2 are electrically connected to the same data line DL, and the active level of the data signal is written to the current control circuit 211 and the duration control circuit 212 in a time-sharing manner. In this way, the writing and compensation stage corresponding to the current control circuit 211 and the stage corresponding to the duration control circuit 212 that generates the duration control signal are separated, that is, these two stages do not overlap, and the level of the data signal does not substantially change in each stage. Signal crosstalk between two adjacent data lines DL can be effectively avoided, and changes in the level of the data signal written to the current control circuit 211 due to changes in the level of the data signal written to the duration control circuit 212 can be avoided. As a result, it is advantageous for improving the problem of brightness difference in the column direction.

[0086] As a result, in the display board 100 provided by some embodiments of this disclosure, the current control circuit 211 and the duration control circuit 212 included in the pixel driving circuit 21 of the same sub-pixel 2 are electrically connected to the same data line DL, and the active level of the data signal can be written to the current control circuit 211 and the duration control circuit 212 in a time-sharing manner. In this way, the stages of the driving signal generated by the current control circuit 211 and the stages of the duration control signal generated by the duration control circuit 212 do not overlap. This is advantageous in ensuring the stability of the data signal at each stage, avoiding signal crosstalk between two adjacent data lines DL, and further preventing changes in the data signal level written to the current control circuit 211 due to changes in the data signal level written to the duration control circuit 212. As a result, it is advantageous in improving the brightness difference problem in the column direction and improving the display effect of the display board 100.

[0087] Furthermore, since the same subpixel 2 is electrically connected to the same data line DL, the number of data lines DL can be effectively reduced. This reduces the space occupied by data lines DL, and increases the wiring space of the display board 100.

[0088] The sub-pixel 2 described above can have various configurations for the current control circuit 211 and the duration control circuit 212. In this disclosure, the configurations shown in Figures 6 and 7 are illustrative. Of course, the configurations of the current control circuit 211 and the duration control circuit 212 are not limited to the example configurations in this disclosure.

[0089] In some embodiments, as shown in Figures 6 and 7, the current control circuit 211 is electrically connected to at least the scan signal terminal Gate, the data signal terminal data, the first enable signal terminal EM, the first voltage signal terminal VDD, and the first node N1. The current control circuit 211 is configured to generate a drive signal in response to the scan signal received at the scan signal terminal Gate, the data signal received at the data signal terminal data, the first enable signal received at the first enable signal terminal EM, and the first voltage signal received at the first voltage signal terminal VDD. The duration control circuit 212 is electrically connected to at least the data signal terminal Data, the first reset signal terminal Res_A, the second reset signal terminal Res_B, the first enable signal terminal EM, the second enable signal terminal Hf, the first node N1, and the light-emitting device 22. The duration control circuit 212 is configured to generate a drive signal in response to the data signal and the first reset signal received at the first reset signal terminal Res_A, and the second enable signal terminal Hf The system is configured to control the duration of conduction between the first node N1 and the light-emitting element 22 based on a second enable signal received at the second reset signal terminal Res_B, or to control the duration of conduction between the first node N1 and the light-emitting element 22 based on a first enablement signal in response to a data signal and a second reset signal received at the second reset signal terminal Res_B. In other words, the duration control signal is either the first enable signal or the second enable signal.

[0090] In some examples, as shown in Figures 6 and 7, the anode of the light-emitting element 22 is electrically connected to the first node N1, and the cathode of the light-emitting element is electrically connected to the second voltage signal terminal VSS.

[0091] In some examples, the first voltage signal terminal VDD is configured to transmit a DC high-level signal, which is referred to as the first voltage signal. The second voltage signal terminal VSS is configured to transmit a DC low-level signal, which is referred to as the second voltage signal. Here, "high-level" and "low-level" are relative terms, and therefore their voltage values ​​are not limited.

[0092] In some examples, the second enablement signal transmitted by the second enablement signal terminal Hf is a high-frequency pulse signal. Exemplarily, in a display stage of a single frame, the second enablement signal contains multiple pulses. For example, the frequency of the second enablement signal is higher than the frequency of the first enablement signal. For example, the number of times the active level duration occurs in the second enablement signal per unit time is greater than the number of times the active level duration occurs in the first enablement signal.

[0093] For example, during the transmission of the second enablement signal, the second enablement signal may be simultaneously transmitted to multiple subpixels 2 included in the display board 100. For instance, the frequency of the second enablement signal may be divided based on the number of rows of subpixels included in the display board 100. For example, the frame rate of the display board 100 is 60 Hz. That is, the display board 100 displays 60 frames per second, and the display period for each frame may be the same. For example, during the display phase of one frame, the active level of the second enablement signal appears once for every refresh period of 4 or 5 rows of subpixels.

[0094] Here, the frequency of conduction between the current control circuit 211 and the light-emitting element 22 may be controlled by controlling the frequency of the duration control signal, and the duration of conduction between the current control circuit 211 and the light-emitting element 22 may be controlled by controlling the duty cycle of the duration control signal. In the light emission stage of a display stage of one frame, the total light emission duration of the light-emitting device 22 (i.e., the sum of the durations of multiple conductions) is determined by controlling the frequency of conduction between the current control circuit 211 and the light-emitting device 22 and the duration of each conduction.

[0095] If the gradation level displayed by the light-emitting element 22 is equal to or greater than the threshold gradation level, the duration control circuit 212 may use the first enablement signal as the duration control signal. As a result, during the light emission phase, the current control circuit 211 and the light-emitting element 22 are always in a conductive state, that is, a conductive path is always formed between the pixel driving circuit 21 and the light-emitting element 22. In this case, high-gradation display can be achieved by continuously transmitting the driving signal generated by the current control circuit 211 to the light-emitting element 22.

[0096] If the grayscale level displayed by the light-emitting element 22 is below the threshold grayscale level, the duration control circuit 212 may use the second enable signal as the duration control signal. As a result, during the light emission phase, the current control circuit 211 and the light-emitting element 22 alternate between a conductive state and a blocked state under the control of the high-frequency pulse signal of the second enable signal. In this case, the drive signal generated by the current control circuit 211 may be transmitted intermittently to the light-emitting element 22 so that the light-emitting element 22 periodically receives the drive signal. For example, the light-emitting element 22 receives the drive signal for a certain period, then stops receiving the drive signal for a certain period, and then receives the drive signal again for a certain period before stopping receiving the drive signal for a certain period. In this way, the duration for which a conductive path is formed between the pixel drive circuit 21 and the light-emitting element 22 is shortened, the duration for which the drive signal is transmitted to the light-emitting element 22 is shortened, the total light emission duration of the light-emitting element 22 is shortened, and low grayscale level display is achieved.

[0097] In some examples of this disclosure, the current control circuit 211 and the duration control circuit 212 in the same subpixel 2 are electrically connected to the same data line DL via a data signal terminal data. That is, both the current control circuit 211 and the duration control circuit 212 are electrically connected to the same data signal terminal data, and are electrically connected to the same data line DL via this data signal terminal data. The data signal transmitted through this data line DL is transmitted to the current control circuit 211 and the duration control circuit 212 via this data signal terminal data. To It may be sent.

[0098] In one embodiment described above, a multi-output selection circuit 4' is provided, as shown in Figure 1. The multi-output selection circuit 4' is electrically connected to a plurality of current data lines DI, a plurality of duration data lines DT, a first current selection signal line DI_MUX1, a second current selection signal line DI_MUX2, a first duration selection signal line DT_MUX1, and a second duration selection signal line DT_MUX2. The multi-output selection circuit 4' controls the current data signal under the control of the first current selection signal and the second current selection signal. SI The current data is transmitted to the current data line DI via time sharing, and the duration data signal is controlled by the first duration selection signal and the second duration selection signal. ST This is transmitted to the duration data line DT.

[0099] In Figure 2, DI_MUX2 represents the second current selection signal, DT_MUX1 represents the first duration selection signal, and Gate represents the scan signal received by the nth row subpixel. i (Below threshold level) represents the duration data signal received by the subpixels in the nth row and i column when the displayed level is below the threshold level, DT i (greater than threshold gradation) represents the duration data signal received by the subpixels in the nth row and i column when the gradation to be displayed is greater than the threshold gradation, DI i+1 This represents the current data signal received by the subpixel in the nth row and (i+1)th column.

[0100] In the above embodiment, both the current control circuit and the duration control circuit are electrically connected to the scan signal terminal. As can be seen from Figure 2, for two adjacent subpixels in the same row, the write and compensation stage corresponding to the current control circuit of one subpixel and the stage of generating the duration control signal corresponding to the duration control circuit of the other subpixel overlap. When the scan signal is at an active level (i.e., low level), the current data signal is the second current selection signal Under the control of (i+1)th current data line DI i+1 After being written, the level of the second current selection signal becomes inactive, and the (i+1)th current data line DI i+1The floating state occurs. During the stage of generating the duration control signal, after the level of the first duration selection signal becomes the active level, the duration data signal becomes the first duration selection signal Under the control of i-th duration data line DT i It is written to. If the grayscale level displayed by the subpixels in row n and column i is greater than the threshold grayscale level, the level of the duration data signal changes from high to low. Therefore, the (i+1)th current data line DI i+1 The level of the current data signal is pulled down. As a result, the brightness of the subpixels in the nth row and (i+1)th column increases, causing a brightness difference problem in the column direction.

[0101] On the other hand, in this disclosure, only the current control circuit 211 is electrically connected to the scan signal terminal Gate, the duration control circuit 212 is electrically connected to other signal terminals, and the current control circuit 221 and the duration control circuit 212 are electrically connected to the same data line DL. The active level of the data signal is written by time sharing, and at the same time, it can be ensured that the writing and compensation stage corresponding to the current control circuit 211 of a certain subpixel 2 and the stage in which the duration control circuit 212 of another subpixel 2 (this other subpixel 2 and the certain subpixel 2 are located in the same row and adjacent to each other) generate a duration control signal do not overlap. In this way, signal crosstalk between two adjacent data lines DL can be avoided, and it can be avoided that a change in the level of the data signal of the duration control circuit 212 written to a certain subpixel 2 will cause a change in the level of the data signal written to the current control circuit 211 of the other subpixel 2. As a result, it is advantageous for improving the problem of brightness difference in the column direction.

[0102] In some embodiments, as shown in Figures 10 and 11, the active level period of the first reset signal and the active level period of the second reset signal do not overlap. In the data signal, either the level corresponding to the active level of the first reset signal or the level corresponding to the active level of the second reset signal is the active level.

[0103] In other words, when the level of the first reset signal is at the active level, the level of the data signal may be at either the active or inactive level. When the level of the second reset signal is at the active level, the level of the data signal may be at either the active or inactive level. However, the levels of the first reset signal and the second reset signal are inversely related to the data signal level.

[0104] Therefore, there are two relationships between the active level of the data signal, the active level of the first reset signal, and the active level of the second reset signal. One relationship is that when the level of the first reset signal is at the active level, the level of the data signal is at the active level, and when the level of the second reset signal is at the active level, the data signal is at the active level. The other relationship is that when the level of the first reset signal is at the active level, the level of the data signal is at the inactive level, and when the level of the second reset signal is at the active level, the level of the data signal is at the active level.

[0105] In this disclosure, the order in which the level of the first reset signal is at the active level and the level of the second reset signal is at the active level is not limited and can be set as needed.

[0106] For the same subpixel 2, the first reset signal, the second reset signal, and the data signal are set as described above. In the stage of generating the duration control signal, the duration control circuit 212 may use the second enable signal as the duration control signal only under common control of the data signal and the first reset signal, or it may use the first enablement signal as the duration control signal only under common control of the data signal and the second reset signal. This ensures the operational performance of the duration control circuit 212 and ensures that the duration control circuit 212 can select only one of the first enable signal or the second enable signal as the duration control signal, thereby improving the stability of signal selection. Furthermore, it is possible to improve the controllability of the gradation displayed on the light-emitting element 22.

[0107] In some embodiments, as shown in Figure 6, the duration control circuit 212 includes a first control subcircuit 2121, a second control subcircuit 212, and a third control subcircuit 2113.

[0108] In some examples, as shown in Figure 6, the first control subcircuit 2121 is electrically connected to at least the data signal terminal Data, the first reset signal terminal Res_A, the second enable signal terminal Hf, and the second node N2. The first control subcircuit 2121 is configured to transmit the second enable signal to the second node N2 in response to the data signal and the first reset signal.

[0109] For example, if the level of the data signal is at an active level and the level of the first reset signal is at an active level, the first control subcircuit 2121 may transmit the second enablement signal as a duration control signal to the second node N2 under the control of the data signal and the first reset signal.

[0110] In some examples, as shown in Figure 6, the second control subcircuit 2122 is electrically connected to at least the data signal terminal Data, the second reset signal terminal Res_B, the first enable signal terminal EM, and the second node N2. The second control subcircuit 2122 is configured to transmit the first enablement signal to the second node N2 in response to the data signal and the second reset signal.

[0111] For example, if the level of the data signal is at an active level and the level of the second reset signal is at an active level, the second control subcircuit 2122 may transmit the first enablement signal as a duration control signal to the second node N2 under the control of the data signal and the second reset signal.

[0112] In some examples, as shown in Figure 6, the third control subcircuit 2123 is electrically connected to the first node N1, the second node N2, and the light-emitting element 22. The third control subcircuit 2123 is configured to control the duration of conduction between the first node N1 and the light-emitting element 22 under the control of a signal from the second node N2.

[0113] For example, when the first control subcircuit 2121 transmits the second enable signal to the second node N2, the third control subcircuit 2123 may conduct between the first node N1 and the light-emitting element 22 under the control of the second enable signal. Since the second enable signal is a high-frequency pulse signal, the first node N1 and the light-emitting element 22 alternate between a conductive state and a disconnected state. The duration of conduction between the first node N1 and the light-emitting element 22 is the sum of multiple conduction durations.

[0114] When the second control subcircuit 2122 transmits the first enable signal to the second node N2, the third control subcircuit 2123 may conduct between the first node N1 and the light-emitting element 22 under the control of the first enable signal. During the light-emitting phase, the first node N1 and the light-emitting element 22 may always be in a conductive state.

[0115] Here, in the stage of generating the duration control signal based on the setting method of the active levels of the first reset signal, the second reset signal, and the data signal, only one of the first control subcircuit 2121 and the second control subcircuit 212 can be operated. This makes it possible to select the duration control signal and avoid abnormal gradation display of the light-emitting element 22 due to simultaneous operation of the first control subcircuit 2121 and the second control subcircuit 212.

[0116] In some embodiments, as shown in Figure 6, the current control circuit 211 includes a data writing subcircuit 2111, a drive subcircuit 2112, a compensation subcircuit 2113, and a light emission control subcircuit 2114.

[0117] In some examples, as shown in Figure 6, the data writing subcircuit 2111 is electrically connected to the scan signal terminal Gate, the data signal terminal data, and the fifth node N5. The data writing subcircuit 2111 is configured to transmit the data signal to the fifth node N5 under the control of the scan signal.

[0118] For example, if the scan signal level is at an active level, the data writing subcircuit 2111 may be conducted under the control of the scan signal, receive the data signal, and transmit the data signal to the fifth node N5.

[0119] In some examples, as shown in Figure 6, the drive subcircuit 2112 is electrically connected to at least the first node N1, the fifth node N5, and the sixth node N6. The drive subcircuit 2112 is configured to transmit signals from the fifth node N5 to the first node N1 under the control of the voltage of the sixth node N6.

[0120] For example, the signal from the fifth node N5 may be a data signal transmitted by the data writing subcircuit 2111. When the voltage from the sixth node N6 is at an active level, the drive subcircuit 2112 may conduct under the control of the voltage from the sixth node N6 and transmit the signal from the fifth node N5 to the first node N1.

[0121] In some examples, as shown in Figure 6, the compensation subcircuit 2113 is electrically connected to the scan signal terminal Gate, the first node N1, and the sixth node N6. The compensation subcircuit 2113 is configured to transmit the signal from the first node N1 to the sixth node N6 in order to compensate the threshold voltage to the drive subcircuit 2112 under the control of the scan signal.

[0122] For example, the signal from the first node N1 may be a data signal transmitted by the data writing subcircuit 2111. When the level of the scan signal is at an active level, the compensation subcircuit 2113 may be conducted under the control of the scan signal and transmit the signal from the first node N1 to the sixth node N6 in order to compensate the threshold voltage to the drive subcircuit 2112.

[0123] Since both the data writing subcircuit 2111 and the compensation subcircuit 2113 are electrically connected to the scan signal terminal Gate, the data writing subcircuit 2111 and the compensation subcircuit 2113 may conduct simultaneously under the control of the scan signal. The data signal transmitted from the data signal terminal Data may be transmitted sequentially to the sixth node N6 via the data writing subcircuit 2111, the drive subcircuit 2112, and the compensation subcircuit 2113 until the drive subcircuit 211 is turned off and the threshold voltage compensation for the drive subcircuit is completed.

[0124] In some examples, as shown in Figure 6, the light emission control subcircuit 2114 is electrically connected to the first enable signal terminal EM, the first voltage signal terminal VDD, and the fifth node N5. The light emission control subcircuit 2114 is configured to transmit the first voltage signal to the fifth node N5 under the control of the first enable signal.

[0125] For example, if the level of the first enable signal is at the active level, the light emission control subcircuit 2114 may be conducted under the control of the first enable signal, receive the first voltage signal, and transmit the first voltage signal to the fifth node N5.

[0126] Here, when the period control signal controls the conduction between the first node N1 and the light-emitting element 22, the drive subcircuit 2112 generates a drive signal based on the first voltage signal from the fifth node N5 and the data signal written to the sixth node N6, and transmits this drive signal to the light-emitting element 22 in order to drive the light-emitting element 22 to emit light.

[0127] The data signal is written to the current control subcircuit 211 and the duration control subcircuit 212 in a time-sharing manner. The data writing subcircuit 211 is electrically connected to the scan signal terminal Gate, the first control subcircuit 212 is electrically connected to the first reset signal terminal Res_A, and the second control subcircuit 2122 is electrically connected to the second reset signal terminal Res_B. Therefore, the active level period of the scan signal does not overlap with the active level period of the first reset signal and the active level period of the second reset signal. In this way, the step of compensating the threshold voltage for the compensation drive subcircuit 2112 does not overlap with the step of the first control subcircuit 2121 selecting the duration control signal and the step of the second control subcircuit 212 selecting the duration control signal. This is advantageous in avoiding signal crosstalk between two adjacent data lines DL and in avoiding changes in the level of the data signal written to the drive subcircuit 2112 due to changes in the data signal level written to the duration control circuit 212. Furthermore, it is advantageous in improving the problem of brightness difference in the column direction.

[0128] In some embodiments, as shown in Figure 6, the current control circuit 211 further includes a reset subcircuit 2115.

[0129] In some examples, as shown in Figure 6, the reset subcircuit 2115 is electrically connected to the first reset signal terminal Res_A, the initial signal terminal Vinit, the sixth node N6, and the light-emitting element 22. The reset subcircuit 2115 is configured to transmit the initial signal received at the initial signal terminal Vinit to the sixth node N6 and the light-emitting element 22 in response to the first reset signal.

[0130] For example, the reset subcircuit 2115 is electrically connected to the anode of the light-emitting element 22. The initial signal transmitted by the initial signal terminal Vinit may be a DC low-level signal.

[0131] For example, if the level of the first reset signal is at an active level, the reset subcircuit 2115 may be conducted under the control of the first reset signal, receive an initial signal, and transmit an initial signal to the sixth node N6 and the anode of the light-emitting device 22 in order to reset the sixth node N8 and the anode of the light-emitting device 22.

[0132] By providing the reset subcircuit 2115, a reference voltage can be supplied to the sixth node N6 and the anode of the light-emitting element 22, removing residual charge from the previous frame's display and improving the controllability of the pixel driving circuit 21.

[0133] The configurations of each subcircuit included in the current control circuit 211 and each subcircuit included in the duration control circuit 212 will be described in general terms below with reference to Figure 7. Of course, the configurations of each subcircuit included in the current control circuit 211 and each subcircuit included in the duration control circuit 212 are not limited to these.

[0134] In some examples, as shown in Figure 7, the first control subcircuit 2121 includes a first transistor T1, a second transistor T2, and a first capacitor C1.

[0135] For example, as shown in Figure 7, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal Res_A, the first electrode of the first transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0136] For example, if the level of the first reset signal is at an active level (i.e., a low level), the first transistor T1 may conduct under the control of the first reset signal, receive a data signal, and transmit the data signal to the third node N3.

[0137] Exemplary, as shown in Figure 7, the control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the second enable signal terminal Hf, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0138] For example, the voltage at the third node N3 is determined by the level of the data signal. If the level of the data signal transmitted to the third node N3 is low, the voltage at the third node N1 will be low. The second transistor T2 may conduct under the control of the level at the third node N3, receive the second enable signal as a duration control signal, and transmit the second enable signal to the second node N2.

[0139] For example, as shown in Figure 7, the first electrode of the first capacitor C1 is electrically connected to the initial signal terminal Vinit, and the second electrode of the first capacitor C2 is electrically connected to the third node N3.

[0140] The first capacitor C1 has a memory function and can store the data signal transmitted to the third node N3.

[0141] For example, if the level of the above data signal is at an inactive level (i.e., high level), the voltage at the third node N3 is high, and the second transistor T2 may be shut off under the control of the voltage at the third node N1. After the first transistor T1 is shut off, the first capacitor C1 can discharge. As a result, the voltage at the third node N3 is maintained at a high level, and the second transistor T2 is maintained in the shut-off state.

[0142] Furthermore, for example, if the level of the above data signal is low, the voltage at the third node N3 is low, and the second transistor T2 may conduct under the control of this voltage at the third node N1. After the first transistor T1 is shut off, the first capacitor C1 can discharge. As a result, the voltage at the third node N3 is maintained at a low level, the second transistor T2 is maintained in a conducting state, and the second enable signal is continuously transmitted to the second node N2.

[0143] In some examples, as shown in Figure 7, the second control subcircuit 2122 includes a third transistor T3, a fourth transistor T4, and a second capacitor C2.

[0144] Exemplary, as shown in Figure 7, the control electrode of the third transistor T3 is electrically connected to the second reset signal terminal Res_B, the first electrode of the third transistor T3 is electrically connected to the data signal terminal Data, and the second electrode of the third electric transistor T3 is electrically connected to the fourth node N4.

[0145] For example, if the level of the second reset signal is low, the third transistor T3 may conduct under the control of the second reset signal, receive the data signal, and transmit the data signal to the fourth node N4.

[0146] For example, as shown in Figure 7, the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected to the first enable signal terminal EM, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0147] For example, the voltage at the fourth node N4 is determined by the level of the data signal. If the level of the data signal transmitted to the fourth node N4 is low, the voltage at the fourth node N3 will be low. The fourth transistor T4 may conduct under the control of the level at the fourth node N4, receive the first enable signal as a duration control signal, and transmit the first enable signal to the second node N2.

[0148] For example, as shown in Figure 7, the first electrode of the second capacitor C2 is electrically connected to the initial signal terminal Vinit, and the second electrode of the second capacitance C2 is electrically connected to the fourth node N4.

[0149] The second capacitor C2 has a memory function and may store the data signal to be transmitted to the fourth node N4.

[0150] For example, if the level of the above data signal is high, the voltage at the fourth node N4 is high, and the fourth transistor T4 may be shut off under the control of the voltage at the fourth node N3. After the third transistor T3 is shut off, the second capacitor C2 can be discharged. As a result, the voltage at the fourth node N4 is maintained at a high level, and the fourth transistor T4 is maintained in the shut-off state.

[0151] Furthermore, for example, if the data signal level is low, the voltage at the fourth node N4 is low, and the fourth transistor T4 may conduct under the control of the voltage at the fourth node N3. After the third transistor T3 is shut off, the second capacitor C2 can discharge. As a result, the voltage at the fourth node N4 is maintained at a low level, the fourth transistor T4 remains in a conducting state, and the first enable signal is continuously transmitted to the second node N2.

[0152] Here, in the stage of generating the duration control signal based on the setting method of the active levels of the first reset signal, the second reset signal, and the data signal, only the second transistor T2 is conducted and the second enable signal is transmitted to the second node N2 as the duration control, or only the fourth transistor T4 is conducted and the first enablement signal is transmitted to the second node N2 as the duration control signal. This makes it possible to select the duration control signal, and prevents the light-emitting element 22 from displaying abnormal gradation by simultaneously conducting the second transistor T2 and the fourth transistor T4.

[0153] In some examples, as shown in Figure 7, the third control subcircuit 2123 includes a fifth transistor T5.

[0154] Exemplary, as shown in Figure 7, the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the light-emitting element 22.

[0155] For example, when the second transistor T2 transmits the second enable signal to the second node N2, since the second enable signal is a high-frequency pulse signal, the fifth transistor T5 may alternately conduct and disconnect under the control of the second enable signal. As a result, the first node N1 and the light-emitting element 22 alternately enter a conduction state and a disconnection state.

[0156] Furthermore, for example, when the fourth transistor T4 transmits the first enable signal to the second node N2, the fifth transistor T5 maintains a conduction state under the control of the first enable signal so that the first node N1 and the light-emitting element 22 are always connected.

[0157] In some examples, as shown in Figure 7, the data writing subcircuit 2111 includes a sixth transistor T6.

[0158] As an example, as shown in Figure 7, the control electrode of the sixth transistor T6 is electrically connected to the scan signal terminal Gate, the first electrode of the sixth transistor T6 is electrically connected to the data signal terminal Date, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0159] For example, if the scan signal level is low, the sixth transistor T6 may conduct under the control of the scan signal, receive the data signal, and transmit the data signal to the fifth node N5.

[0160] In some examples, as shown in Figure 7, the drive subcircuit 2112 includes a seventh transistor T7 and a third capacitor C3.

[0161] Exemplary, as shown in Figure 7, the control electrode of the seventh transistor T7 is electrically connected to the sixth node N6, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T8 is electrically connected to the first node N1.

[0162] For example, if the level of the sixth node N6 is low, the seventh transistor T7 may conduct under the control of the voltage of the sixth node N6 and transmit the data signal from the fifth node N5 to the first node N1.

[0163] Exemplary, as shown in Figure 7, the first electrode of the third capacitor C3 is electrically connected to the sixth node N6, and the second electrode of the third capacitor C3 is electrically connected to the first voltage signal terminal VDD.

[0164] For example, the third capacitor C3 has a memory function and can store the signal to be transmitted to the sixth node N6, and can also discharge to maintain the level of the sixth node N6.

[0165] In some examples, as shown in Figure 7, the compensation subcircuit 2113 includes an eighth transistor T8.

[0166] Exemplary, as shown in Figure 7, the control electrode of the eighth transistor T8 is electrically connected to the scan signal terminal Gate, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6.

[0167] For example, if the scan signal level is low, the eighth transistor T8 may conduct under the control of the scan signal, and the seventh transistor T7 may be shut off, transmitting the data signal from the first node N1 to the sixth node N6 until the threshold voltage compensation for the seventh transistor T7 is completed.

[0168] Here, after the eighth transistor T8 is shut off, the third capacitor C3 may discharge to maintain the voltage at the sixth node N6.

[0169] In some examples, as shown in Figure 7, the light emission control subcircuit 2114 includes a ninth transistor T9.

[0170] Exemplary, as shown in Figure 7, the control electrode of the ninth transistor T9 is electrically connected to the first enable signal terminal EM, the first electrode of the ninth transistor T9 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the ninth transistor T8 is electrically connected to the fifth node N5.

[0171] For example, if the level of the first enable signal is low, the ninth transistor T9 may conduct under the control of the first enable signal, receive the first voltage signal, and transmit the first voltage signal to the fifth node N5.

[0172] In some examples, as shown in Figure 7, the reset subcircuit 2115 includes a 10th transistor T10 and an 11th transistor T11.

[0173] Exemplary, as shown in Figure 7, the control electrode of the 10th transistor T10 is electrically connected to the first reset signal terminal Res_A, the first electrode of the 13th transistor T10 is electrically connected to the initial signal terminal Vinit, and the second electrode of the 10th transistor T10 is electrically connected to the 6th node N6. The control electrode of the 11th transistor T11 is electrically connected to the first reset signal terminal Res_A, the first electrode of the 11th transistor T11 is electrically connected to the initial signal terminal Vinit, and the second electrode of the 11th transistor T11 is electrically connected to the light-emitting element 22.

[0174] For example, if the level of the first reset signal is low, the tenth transistor T10 and the eleventh transistor T11 may conduct simultaneously under the control of the first reset signal. The tenth transistor T10 may receive the initial signal and reset the sixth node N8 by transmitting the initial signal to the sixth node N6. The eleventh transistor T11 may receive the initial signal and transmit it to the light-emitting element 22 to reset the light-emitting element 22.

[0175] In some embodiments, as shown in Figures 8 and 9, the display board 100 may further include a plurality of pads P located on the side of the pixel driving circuit 21 away from the base 1. The plurality of pads P may include a plurality of anode pads P1 and a plurality of cathode pads P2, where one anode pad P1 and one cathode pad P2 may constitute a pad pair. A single pixel driving circuit 21 may correspond to at least one pad pair.

[0176] In some examples, the display board 100 further includes a plurality of second voltage signal lines. In each pad pair, the anode pad P1 may be electrically connected to one end of the reset sub-circuit 2115 and one end of the third control sub-circuit 2123 in the pixel driving circuit 21 to receive the initial signal transmitted by the reset sub-circuit 211 and the driving signal transmitted by the third control sub-circuit 2123, and the cathode pad P2 may be electrically connected to one second voltage signal line to receive second voltage information transmitted by the second voltage signal line. The cathode pad P2 may be used, for example, as a second voltage signal terminal VSS.

[0177] For example, as shown in Figures 8 and 9, the pixel driving circuit 21 corresponds to one pad pair, and the multiple subpixels 2 included in the display board 100 include red subpixels, green subpixels, and blue subpixels. Here, the red subpixels, green subpixels, and blue subpixels may constitute a pixel unit (as shown by the dashed box in Figures 8 and 9).

[0178] In some examples, the light-emitting element 22 electrically connected to the pixel driving circuit 21 may include an anode electrode pin and a cathode electrode pin. The anode electrode pin may be bonded to an anode pad P1 in this pad pair and electrically connected to a reset sub-circuit 2115 and a third control sub-circuit 2123. The cathode electrode pin may be bonded to a cathode pad P2 in this pad pair and electrically connected to a second voltage signal terminal VSS.

[0179] As an example, as shown in Figures 8 and 9, the orthographic projections of the multiple pads P on the base 1 do not overlap with the orthographic projection of the seventh transistor T7 in each pixel driving circuit 21 on the base 1. This makes it possible to avoid adverse effects on the seventh transistor T7 during the process of bonding the light-emitting element 22 to the corresponding pad and applying pressure, thereby ensuring good driving performance of the seventh transistor T8.

[0180] For example, the light-emitting element 22 may have various structures, which can be selected according to actual requirements. For instance, the structure of the light-emitting element 22 may be an upward-facing, vertical, or downward-facing structure.

[0181] Here, each pad pair can be arranged in various ways, as long as it can satisfy the gap requirements between each pixel unit (a macro-level visible pixel unit consists of light-emitting elements within the pixel unit) (the gap requirements here, for example, the gap between macro-level visible pixel units), and has bonding capability between the light-emitting elements 22 and the pad pair.

[0182] For example, the arrangement of each pad pair is the same as the arrangement of the light-emitting elements 22 in each subpixel.

[0183] For example, in each pixel cell, the light-emitting elements 22 are arranged in a "pin" shape. Therefore, as shown in FIG. 8, the pad pairs corresponding to each pixel cell may be arranged in a "pin" shape. In this case, in the same pixel cell, the centers of each pad pair can form a triangle (for example, an acute triangle). In this way, it is advantageous to ensure that there is a large gap between two adjacent pad pairs and a large gap between two adjacent light-emitting elements 22. Not only can the requirements for the gap between pixel cells be satisfied, but also the difficulty of bonding the light-emitting elements 22 can be reduced.

[0184] In another example, in each pixel unit, the light-emitting elements 22 are arranged horizontally. Therefore, as shown in FIG. 9, the pad pairs corresponding to each pixel cell may be arranged horizontally.

[0185] In the examples of the present disclosure, as shown in FIGS. 8 and 9, it should be understood that any three adjacent sub-pixel rows are respectively the sub-pixels in the (2N - 1)th row, the sub-pixels in the 2Nth row, and the sub-pixels in the (2N + 1)th row. The region between the sub-pixels in the (2N - 1)th row and the sub-pixels in the 2Nth row is the first gap region GA1. The region between the sub-pixels in the 2Nth row and the sub-pixels in the (2N + 1)th row is the second gap region GA2. In the sub-pixels in the (2N - 1)th row and the sub-pixels in the 2Nth row, the pixel driving circuit 21 is closer to the first gap region GA1. In the sub-pixels in the 2Nth row and the sub-pixels in the (2N + 1)th row, the pixel driving circuit 21 is further away from the second gap region GA2. N is a positive integer.

[0186] For example, for the sub-pixels in the (2N - 1)th row and the sub-pixels in the 2Nth row, each pixel driving circuit 21 is arranged symmetrically with respect to the first gap region GA1, and each pixel driving circuit 21 is closer to the first gap region GA1, and each pad pair is further away from the first gap region GA1. For the sub-pixels in the 2Nth row and the sub-pixels in the (2N + 1)th row, each pixel driving circuit 21 is the 2The pixels are arranged symmetrically with respect to the gap region GA2, and each pixel driving circuit is further away from the second gap region GA2, while each pad pair is closer to the second gap region GA2.

[0187] For example, along the first direction Y, the size of the second gap region GA2 is larger than the size of the first gap region GA1.

[0188] In this way, assuming that the gap requirements between each pixel unit are met, the uniformity of the distribution of each pixel unit can be improved, a compact arrangement of the pixel driving circuit 21 can be realized, and the wiring space can be used effectively.

[0189] For example, within the same row, the gap between any two adjacent pixel units is the same. Within the same column, the gap between any two adjacent pixel units is the same.

[0190] In this example, only the positions of the pixel driving circuit 21 and pad pair in each subpixel are restricted, and the specific configuration of the pixel driving circuit 21 is not restricted as to whether it is symmetrical or not. Since the pixel driving circuit 21 includes multiple film layers, in the process of forming multiple film layers, there may be differences in the size of the film layers included in different pixel driving circuits due to unavoidable factors such as process errors. Thus, the pixel driving circuit 21 in the (2N-1)th row subpixel and the pixel driving circuit 21 in the 2Nth row subpixel cannot be arranged strictly symmetrically with respect to the first gap region GA1, and the pixel driving circuit 21 in the 2Nth row subpixel and the pixel driving circuit 21 in the (2N+1)th row subpixel cannot be arranged strictly symmetrically with respect to the second gap region GA2.

[0191] In some embodiments, as shown in Figures 12, 13, 16, and 17, the same data line DL is electrically connected to at least one row of subpixels.

[0192] In some examples, as shown in Figures 12 and 13, one data line DL electrically connects one column of subpixels, i.e., there is a one-to-one correspondence between them. The number of data lines DL is equal to the number of columns of subpixels. In this case, the data signal transmitted by each data line DL is written only to the subpixels of the corresponding column.

[0193] In some other examples, as shown in Figures 16 and 17, a single data line DL may be electrically connected to multiple sub-pixel columns. The number of data lines DL is less than the number of sub-pixel columns. In this case, the data signals transmitted by each data line DL may be written to the corresponding multiple sub-pixel columns in time-sharing mode.

[0194] Here, the same data line DL is electrically connected to at least one row of subpixels, which is advantageous in reducing the number of data lines DL, reducing the space occupied by the data lines DL, and increasing the wiring space of the display board 100.

[0195] In some embodiments, as shown in Figures 12, 13, 16, and 17, at least one sub-pixel row is provided between two adjacent data lines DL.

[0196] In some examples, as shown in Figures 12 and 13, a row of subpixels is provided between two adjacent data lines DL. Thus, each data line DL may be electrically connected to a row of subpixels.

[0197] In other examples, as shown in Figures 16 and 17, multiple sub-pixel rows are provided between any two adjacent data lines DL. Thus, each data line DL may be electrically connected to multiple sub-pixel rows.

[0198] Furthermore, if a sub-pixel cannot be provided between two adjacent data lines DL, a large gap must be created between them to prevent parasitic capacitance from forming. However, this makes it easier to increase the space occupied by the data lines DL on the display board 100 and increases the complexity of the wiring.

[0199] In this disclosure, at least one row of subpixels is provided between any two adjacent data lines DL, thereby separating any two adjacent data lines DL by at least one row of subpixels. This reduces the space occupied by the data lines DL on the display board 100 and reduces the complexity of the wiring, as well as preventing signal crosstalk between two adjacent data lines DL and ensuring the accuracy of the data signals transmitted by each data line DL.

[0200] In some embodiments, as shown in Figures 19 and 20, the display board 100 further includes a plurality of connection wirings 3 provided on the edge of the base 1. The plurality of subpixels 2 included in the display board 100 may be provided on one side of the base 1, and the drive chip 200 included in the display device 1000 may be provided on the other side of the base 1.

[0201] In some examples, each connection wire 3 may be U-shaped. One end of the connection wire 3 is located on one side of the base 1 and may be electrically connected to at least one data line DL (for example, directly or indirectly), and the other end of the connection wire may extend to the other side of the base 1. As shown in Figure 22, the other end of the connection wire 3 may be electrically connected to a drive chip 200. For example, the drive chip 200 may supply a data signal to the connection wire 3, and the connection wire 3 may transmit this data signal to the corresponding data line DL.

[0202] For illustrative purposes, the above arrangement may be called the side wiring method.

[0203] The sub-pixels 2 are electrically connected to the drive chip 200 using a side wiring method, which reduces the size of the bezel of the display board 100, making it easier to design a narrow bezel, or even a bezel-less design.

[0204] Furthermore, if the display device 1000 is spliced ​​with multiple display boards 100, the size of the seams can be effectively reduced and the splicing can be seamlessly achieved by splicing the display boards 100 using a side wiring method. As a result, it is advantageous to realize a narrow bezel or even a bezel-less design.

[0205] The display board 100 provided by this disclosure has a small number of data lines DL. This reduces the number of connection lines 3 accordingly, and further improves the process yield of side wiring, thereby improving the yield of the display board 100 and the display device 1000.

[0206] Furthermore, if one data line DL is electrically connected to multiple rows of subpixels, the number of connection lines 3 can be further reduced, which is advantageous in further improving the process yield of side wiring and thus further improving the yield of the display board 100 and the display device 1000.

[0207] Furthermore, when using the side wiring method, there are various configuration methods to effectively reduce the number of connection wires 3, and these configuration methods can be selected according to actual needs. These various configuration methods include, but are not limited to, the methods exemplified in this disclosure.

[0208] In an exemplary embodiment, as shown in Figures 12 and 13, the display board 100 further includes a multi-output selection circuit 4, a plurality of data transmission lines DTL, and a plurality of selection signal lines Mux.

[0209] In some examples, the multi-output selection circuit 4 may be located on the same side of the sub-pixel 2 and the base 1. The multi-output selection circuit 4 may be electrically connected to multiple data lines DL included in the display board 100.

[0210] In some examples, multiple data transmission lines (DTLs) may be located on the same side of subpixel 2 and base 1. Multiple data transmission lines (DTLs) may extend in the first direction Y and be electrically connected to the multi-output selection circuit 4. Of course, a portion of each data transmission line (DTL) may extend in the first direction Y, while other portions of the data transmission line (DTL) may extend in the second direction X.

[0211] In some examples, multiple selection signal lines Mux may be located on the same side of subpixel 2 and base 1. Multiple selection signal lines Mux may extend in a second direction X and be electrically connected to a multi-output selection circuit 4. Of course, a portion of each selection signal line Mux may extend in a first direction Y, and another portion of the selection signal line Mux may extend in a second direction X.

[0212] In some examples, the multi-output selection circuit 4 is configured to transmit data signals transmitted by multiple data transmission lines DTL to multiple data lines DL in a time-sharing manner, under the control of selection signals transmitted by multiple selection signal lines Mux.

[0213] Note that the number of data transmission lines DTL is smaller than the number of data lines DL, and one data transmission line DTCL corresponds to multiple data lines DL. The multi-output selection circuit 4 has a selection function. Choosing a trust Depending on the signal, the multi-output selection circuit 4 may transmit the data signal transmitted by each data transmission line DTL to one of the corresponding data lines DL for a specific period of time, and then transmit the data signal to another data line DL among the corresponding data lines DL for the next period of time.

[0214] In this case, multiple data lines DL may be electrically connected to a source drive circuit (e.g., a drive chip 200) that generates data signals via multiple data transmission lines DTL. Since the number of data transmission lines DTL is less than the number of data lines DL, the number of pins used for electrical connection to the drive chip 200 can be reduced, which is advantageous in improving the efficiency of electrical connections between the drive chip 200 and the pins, and thus improving the efficiency of the display device 1000.

[0215] Furthermore, if the display board 100 includes connection wiring 3, one end of each connection wiring 3 on the base 1 side may be electrically connected to a single data transmission line DTL. In this way, the connection wiring 3 is electrically connected to a plurality of corresponding data lines DL sequentially via the data transmission line DTL and the multi-output selection circuit 4.

[0216] Since the number of data transmission lines (DTL) is less than the number of data lines (DL), the number of connection wires (3) can be reduced, effectively improving the yield of side wiring.

[0217] In some embodiments, as shown in Figures 12 and 13, a plurality of data lines DL include at least a plurality of first data lines DL1, a plurality of second data lines DL2, and a plurality of third data lines DL3. A plurality of data transmission lines DTL include at least a plurality of first data transmission lines DTL1, a plurality of second data transmission lines DTL2, and a plurality of third data transmission lines DTL3. The multi-output selection circuit 4 may include a plurality of selection transistor groups 41. The selection transistor group 41 may be electrically connected to the selection signal line Mux and the first data line DL1, the second data line DL2, and the third data line DL3.

[0218] For example, each group of selection transistors 41 may be electrically connected to one selection signal line Mux, one first data line DL1, one second data line DL2, and one third data line DL3.

[0219] In some examples, as shown in Figure 13, the first data transmission line DTL1 is electrically connected to at least two selection transistor groups 41, and electrically connected to the corresponding first data line DL1 via at least two selection transistor groups 41.

[0220] Since each selection transistor group 41 is electrically connected to one selection signal line Mux and one first data line DL1, each first data transmission line DTL1 may correspond to at least two selection signal lines Mux and at least two first data lines DL1. The data signal transmitted by the first data transmission line DTL1 is transmitted to the corresponding first data line DL1 under the control of the selection signal transmitted by one selection signal line Mux, and transmitted by the other corresponding first data line DL1 under the control of the selection signal transmitted by the other selection signal line Mux, and the data signal transmitted by the first data transmission line DTL1 is written in a time-sharing manner.

[0221] Exemplary, the first data transmission line DTL1 may be electrically connected to two, three, four, or six select transistor groups 41. Thus, the first data transmission line DTL1 may be electrically connected to two, three, four, or six first data lines DL1.

[0222] In some examples, as shown in Figure 13, the second data transfer line DTL2 is electrically connected to at least two selection transistor groups 41 and electrically connected to the corresponding second data line DL2 via at least two gate transistor groups 41.

[0223] Since each group of selection transistors 41 is electrically connected to one selection signal line Mux and one second data line DL2, each second data transmission line DTL2 may correspond to at least two selection signal lines Mux and at least two second data lines DL2. The data signal transmitted by the second data transmission line DTL2 is transmitted to the corresponding second data line DL2 under the control of the selection signal transmitted by one selection signal line Mux, and transmitted by the other corresponding second data transmission line DTL2 under the control of the selection signal transmitted by the other selection signal line Mux, and the data signal transmitted by the second data transmission line DTL2 is written in a time-sharing manner.

[0224] For example, the second data transmission line DTL2 may be electrically connected to two, three, four, or six select transistor groups 41. Thus, the second data transmission line DTL2 may be electrically connected to two, three, four, or six second data lines DL2.

[0225] In some examples, as shown in Figure 13, the third data transfer line DTL3 is electrically connected to at least two selection transistor groups 41 and electrically connected to the corresponding third data line DL3 via at least two selection transistor groups 41.

[0226] Each group of selection transistors 41 is electrically connected to one selection signal line Mux and one third data line DL3, so that each third data transmission line DTL3 may correspond to at least two selection signal lines Mux and at least two third data lines DL3. The data signal transmitted by the third data transmission line DTL3 is transmitted to the corresponding third data line DL3 under the control of the selection signal transmitted by one selection signal line Mux, and then transmitted by the other corresponding third data transmission line DTL3 under the control of the selection signal transmitted by the other selection signal line Mux, and the data signal transmitted by the third data transmission line DTL3 is written in a time-sharing manner.

[0227] Exemplary, the third data transmission line DTL3 may be electrically connected to two, three, four, or six select transistor groups 41. Thus, the third data transmission line DTL3 may be electrically connected to two, three, four, or six first data lines DL3.

[0228] Selectively, as shown in Figure 13, the number of multiple selection signal lines Mux may be 6, and therefore the number of multiple selection transistor groups 41 is 6. m Even if m is a positive integer. In this case, the first selection signal line MUX1 may be electrically connected to the (6i-5)th selection transistor group 41, the second selection signal line MUX2 may be electrically connected to the (6i-4)th selection transistor group 41, the third selection signal line MUX3 may be electrically connected to the (6i-3)th selection transistor group 41, the fourth selection signal line MUX4 may be electrically connected to the (6i-2)th selection transistor group 41, and the fifth selection signal line MUX5 may be electrically connected to the (6i-1)th selection transistor group. Here, i is The values ​​are taken sequentially from 1 to m. .

[0229] In this case, the connection relationships between each selection transistor group 41 and the data transmission line DTL and data line DL will be schematically explained with reference to Figure 13.

[0230] For example, the i-th first data transmission line DTL1 may be electrically connected to the (6i-5)th selection transistor group 41 and electrically connected to the (6i-5)th first data line DL1 via the (6i-5)th selection transistor group 41, the i-th first data transmission line DTL1 may be electrically connected to the (6i-4)th selection transistor group 41 and electrically connected to the (6i-4)th first data line DL1 via the (6i-4)th selection transistor group 41, the i-th first data transmission line DTL1 may be electrically connected to the (6i-3)th selection transistor group 41 and electrically connected to the (6i-3)th first data line DL1 via the (6i-3)th selection transistor group 41 The i-th first data transmission line DTL1 may be electrically connected to the (6i-2)th selection transistor group 41 and electrically connected to the (6i-2)th first data line DL1 via the (6i-2)th selection transistor group 41, the i-th first data transmission line DTL1 may be electrically connected to the (6i-1)th selection transistor group 41 and electrically connected to the (6i-1)th first data line DL1 via the (6i-1)th selection transistor group 41, and the i-th first data transmission line DTL1 may be electrically connected to the 6ith selection transistor group and electrically connected to the 6ith first data line DL1 via the 6ith selection transistor group.

[0231] For example, the i-th second data transmission line DTL2 may be electrically connected to the (6i-5)th selection transistor group 41 and electrically connected to the (6i-5)th second data line DL2 via the (6i-5)th selection transistor group 41, the i-th second data transmission line DTL2 may be electrically connected to the (6i-4)th selection transistor group 41 and electrically connected to the (6i-4)th second data line DL2 via the (6i-4)th selection transistor group 41, the i-th second data transmission line DTL2 may be electrically connected to the (6i-3)th selection transistor group 41 and electrically connected to the (6i-3)th second data line DL2 via the (6i-3)th selection transistor group 41 The i-th second data transmission line DTL2 may be electrically connected to the (6i-2)th selection transistor group 41 and electrically connected to the (6i-2)th second data line DL2 via the (6i-2)th selection transistor group 41, or the i-th second data transmission line DTL2 may be electrically connected to the (6i-1)th selection transistor group 41 and electrically connected to the (6i-1)th second data line DL2 via the (6i-1)th selection transistor group 41, or the i-th second data transmission line DTL2 may be electrically connected to the 6ith selection transistor group and electrically connected to the 6ith second data line DL2 via the 6ith selection transistor group.

[0232] For example, the i-th third data transmission line DTL3 may be electrically connected to the (6i-5)th selection transistor group 41 and electrically connected to the (6i-5)th third data transmission line DL3 via the (6i-5)th selection transistor group 41, the i-th third data transmission line DTL3 may be further electrically connected to the (6i-4)th selection transistor group 41 and electrically connected to the (6i-4)th third data line DL3 via the (6i-4)th selection transistor group 41, the i-th third data transmission line DTL3 may be further electrically connected to the (6i-3)th selection transistor group 41 and electrically connected to the (6i-3)th third data line DL The i-th third data transmission line DTL3 may be electrically connected to 3, and may be electrically connected to the (6i-2)th selection transistor group 41 and electrically connected to the (6i-2)th third data line DL3 via the (6i-2)th selection transistor group 41, and may be electrically connected to the (6i-1)th selection transistor group 41 and electrically connected to the (6i-1)th third data line DL3 via the (6i-1)th selection transistor group 41, and may be electrically connected to the 6ith selection transistor group DTL3.

[0233] In some examples, as shown in Figures 12 and 13, the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 are arranged periodically. That is, the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be arranged cyclically in a specific order.

[0234] There are several possible arrangement orders, and they may be set according to actual needs.

[0235] For example, as shown in Figures 12 and 13, the arrangement order for one period is: first data transmission line DTL1, second data transmission line DTL2, and third data transmission line DTL3; or second data transmission line DTL2, first data transmission line DTL1, and third data transmission line DTL3; or third data transmission line DTL3, first data transmission line DTL1, and second data transmission line DTL2.

[0236] In some examples, the first data line DL1, the second data line DL2, and the third data line DL3 are arranged periodically, as shown in Figures 12 and 13. That is, the first data line DL1, the second data line DL2, and the third data line DL3 may be arranged cyclically in a specific order.

[0237] There are several possible arrangement orders, and they may be set according to actual needs.

[0238] For example, as shown in Figures 12 and 13, the arrangement order for one period is first data line DL1, second data line DL2, and third data line DL3, or second data line DL2, first data line DL1, and third data line DL3, or third data line DL3, first data line DL1, and second data line DL2.

[0239] For example, as shown in Figures 12 and 13, the arrangement order of data transmission lines DTL may be the same as the arrangement order of data lines DL, which is advantageous in increasing the regularity of the wiring and reducing the complexity of the wiring.

[0240] Selectively, all subpixels 2 electrically connected to the first data line DL1 may be red subpixels, all subpixels 2 electrically connected to the second data line DL2 may be green subpixels, and all subpixels electrically connected to the third data line DL3 may be blue subpixels.

[0241] If subpixel 2 selectively includes a white subpixel, then data line DL may include, for example, a fourth data line DL4, and data transmission line DTL may include, for example, a first data transmission line DL4. The connection relationships between the fourth data line DL4, the fourth data line DTL4 and each selected transistor group 41 are described in the example above and will not be repeated here.

[0242] In some embodiments, as shown in Figure 13, the selection transistor group 41 includes at least a first selection transistor 411, a second selection transistor 412, and a third selection transistor 413.

[0243] In some examples, as shown in Figure 13, the control electrode of the first selection transistor 411 is electrically connected to the selection signal line Mux, the first electrode of the first selection transistor 411 is electrically connected to the first data transmission line DTL1, and the second electrode of the first selection transistor 411 is electrically connected to the first data line DL1.

[0244] For example, if the level of the selection signal transmitted by the selection signal line Mux is low, the first selection transistor 411 may conduct under the control of the selection signal and transmit the data signal from the first data transmission line DTL1 to the first data line DL1.

[0245] In some examples, as shown in Figure 13, the control electrode of the second selection transistor 412 is electrically connected to the selection signal line Mux, the first electrode of the second selection transistor 412 is electrically connected to the second data transmission line DTL2, and the second electrode of the second selection transistor 412 is electrically connected to the second data line DL2.

[0246] For example, if the level of the selection signal transmitted by the selection signal line Mux is low, the second selection transistor 412 may be conducted under the control of the selection signal and transmit the data signal from the second data transmission line DTL2 to the second data line DL2.

[0247] In some examples, as shown in Figure 13, the control electrode of the third selection transistor 413 is electrically connected to the selection signal line Mux, the first electrode of the third selection transistor 413 is electrically connected to the third data transmission line DTL3, and the second electrode of the third selection transistor 413 is electrically connected to the third data line DL3.

[0248] For example, if the level of the selection signal transmitted by the selection signal line Mux is low, the third selection transistor 413 may conduct under the control of the selection signal and transmit the data signal from the third data transmission line DTL3 to the third data line DL3.

[0249] Selectively, as shown in Figure 13, for example, the number of selection signal lines Mux is 6, and the number of selection transistor groups 41 is 6. m That is the case.

[0250] The i-th first data transmission line DTL1 may be electrically connected to the first selection transistor 411 in the (6i-5)th selection transistor group 41 to the 6ith selection transistor group 41. The data signal transmitted by the i-th first data transmission line DTL1 is transmitted in a time-sharing manner to the (6i-5)th first data lines DL1 to the 6ith first data line DL1 under the control of the selection signals transmitted by the first selection signal line MUX1, the second selection signal line MUX2, the third selection signal line MUX3, the fourth selection signal line MUX4, the fifth selection signal line MUX5, and the sixth selection signal line MUX6, and the data signal is written in a time-sharing manner.

[0251] The i-th second data transmission line DTL2 may be electrically connected to the second selection transistor 412 in the (6i-5)th selection transistor group 41 to the 6ith selection transistor group 41. The data signal transmitted by the i-th second data transmission line DTL2 is transmitted in a time-sharing manner to the (6i-5)th second data lines DL2 to the 6ith second data lines DL2, under the control of the selection signals transmitted by the first selection signal line MUX1, the second selection signal line MUX2, the third selection signal line MUX3, the fourth selection signal line MUX4, the fifth selection signal line MUX5, and the sixth selection signal line MUX6, and the data signal is written in a time-sharing manner.

[0252] The i-th third data transmission line DTL3 may be electrically connected to the third selection transistor 413 in the (6i-5)th selection transistor group 41 to the 6ith selection transistor group 41. The data signal transmitted by the i-th third data transmission line DTL3 is transmitted in a time-sharing manner to the (6i-5)th third data lines DL3 to the 6ith third data lines DL3, under the control of the selection signals transmitted by the first selection signal line MUX1, the second selection signal line MUX2, the third selection signal line MUX3, the fourth selection signal line MUX4, the fifth selection signal line MUX5, and the sixth selection signal line MUX6, and the data signal is written in a time-sharing manner.

[0253] Furthermore, if subpixel 2 further includes white subpixels, the selection transistor group 41 may further include, for example, a fourth selection transistor. The electrical connection relationship between the selection transistor group 41 and the fourth selection transistor will not be repeated here, as it is explained in the example above.

[0254] In some examples, as shown in Figures 12 and 13, the same data line DL may be electrically connected to a row of subpixels. That is, the number of data lines DL is equal to the number of rows of subpixels.

[0255] In this embodiment, it is understood that subpixels in the same row may be electrically connected to only one gate line GL. That is, the scanning signal transmitted by each gate line GL can simultaneously control the operation of each data writing subcircuit 2111 and each compensation subcircuit 2113 in the same row of subpixels.

[0256] In another embodiment, as shown in Figures 16 and 17, the same data line DL is electrically connected to at least two columns of subpixels, and one row of subpixels is electrically connected to at least two gate lines GL. The at least two gate lines GL are configured to transmit scan signals to their respective subpixels, thereby controlling the subpixels in that row to receive the data signals transmitted by the data line DL in a time-sharing manner.

[0257] In some examples, each subpixel 2 is electrically connected to one data line DL and one gate line GL out of at least two gate lines GL, so that each gate line GL is electrically connected to only some of the subpixels 2 in the same row. Also, at least two subpixels 2 in the same row are electrically connected to one data line DL.

[0258] Exemplary, at least two subpixels 2 electrically connected to the same data line DL are each electrically connected to different gate lines GL. The active level periods of the scan signals received by at least two subpixels 2 do not overlap. In this way, at least two subpixels 2 operate during different periods (for example, the data writing subcircuits 2111 and compensation subcircuits 2113 in different subpixels 2 can conduct during different periods), and the data signals transmitted on the data line DL are received sequentially, allowing the data signals to be written in a time-sharing manner.

[0259] Note that the number of data lines DL is less than the number of subpixels 2 in the same row.

[0260] By arranging the gate line GL and the data line DL according to the above-described arrangement method, the number of data lines DL included in the display substrate 100 can be effectively reduced. The space occupied by the data line DL can be reduced, and the wiring space of the display substrate 100 can be increased.

[0261] When the display substrate 100 includes the connection wiring 3, one data line DL may be electrically connected to one connection wiring 3. That is, the number of data lines DL may be equal to the number of connection wirings 3. Since the number of data lines DL is less than the number of sub-pixels 2 in the sub-pixels of the same row, the number of connection wirings 3 can also be effectively reduced, and the yield of the side wiring can be effectively increased.

[0262] In some embodiments, as shown in FIGS. 16 and 17, among the sub-pixels in the same row, any two adjacent sub-pixels 2 are electrically connected to different gate lines GL.

[0263] In this way, two adjacent sub-pixels 2 (more adjacent sub-pixels 2) can be electrically connected to the same data line DL. Thereby, for two adjacent sub-pixels 2 between arrange the data line DL, reduce the gap between the data line DL and the sub-pixel 2 that is electrically connected correspondingly, and reduce the complexity of the wiring between the data line DL and the sub-pixel that is electrically connected correspondingly.

[0264] In some embodiments, as shown in FIGS. 16 and 17, the number of columns of sub-pixels 2 electrically connected to the same data line DL is equal to the number of gate lines GL electrically connected to the sub-pixels in the same row.

[0265] In some examples, the number of columns of sub-pixels 2 electrically connected to the same data line DL is n, and the number of gate lines GL electrically connected to the sub-pixels in one row is also n. Among the sub-pixels in the same row, the n sub-pixels 2 electrically connected to the same data line DL are electrically connected to the n gate lines GL in a one-to-one correspondence.

[0266] This enables grouping and controlling sub-pixels in the same row, reducing the complexity of the wiring and the complexity of controlling sub-pixels in the same column.

[0267] Here, the number of columns of sub-pixels 2 electrically connected to the same data line DL, that is, the number of gate lines GL electrically connected to sub-pixels in the same row, can be set according to actual requirements.

[0268] Exemplarily, the number of columns of sub-pixels 2 electrically connected to the same data line DL may be 2, 3, 4, or 6. Therefore, the number of gate lines GL electrically connected to sub-pixels in the same row may also be 2, 3, 4, or 6.

[0269] Optionally, as shown in FIGS. 16 and 17, the number of columns of sub-pixels 2 electrically connected to the same data line DL is 6. Therefore, the number of gate lines GL electrically connected to sub-pixels in the same row is 6. In this case, among the sub-pixels in the same row, the first gate line GL1 may be electrically connected to the (6i - 5)-th sub-pixel 2, the second gate line GL2 may be electrically connected to the (6i - 4)-th sub-pixel, the third gate line GL3 may be electrically connected to the (6i - 3)-th sub-pixel 2, the fourth gate line GL4 may be electrically connected to the (6i - 2)-th sub-pixel, the fifth gate line GL5 may be electrically connected to the (6i - 1)-th sub-pixel 2, and the sixth gate line GL6 may be electrically connected to the 6i-th sub-pixel. The i-th data line DL may be electrically connected from the sub-pixels in the (6i - 5)-th column to the sub-pixels in the 6i-th column.

[0270] For example, as shown in Figure 18, the levels of the scan signal Gate1 transmitted by the first gate line GL1, the scan signal Gate2 transmitted by the second gate line GL2, the scan information Gate3 transmitted by the third gate line GL3, the scan information Gate4 transmitted by the fourth gate line GL4, the scan signal Gate5 transmitted by the fifth gate line GL5, and the scan signal Gate6 transmitted by the sixth gate line GL6 sequentially change to active levels, and the active level periods of any two adjacent scan signals among the six scan signals do not overlap. Therefore, the data writing subcircuit 2111 and compensation subcircuit 2113 in the (6i-5)th subpixel 2, the data writing subcircuit 2111 and compensation subcircuit 2113 in the (6i-4)th subpixel 2, the data writing subcircuit 2111 and compensation subcircuit 2113 in the (6i-3)th subpixel 2, the data writing subcircuit 2111 and compensation subcircuit 2113 in the (6i-2)th subpixel 2, the data writing subcircuit 2111 and compensation subcircuit 2113 in the (6i-1)th subpixel 2, and the data writing subcircuit 2111 and compensation subcircuit 2113 in the 6ith subpixel 2 sequentially receive the data signal transmitted by the i-th data line DL, and the data signal is written in a time-sharing manner.

[0271] In some embodiments, as shown in Figures 16 and 17, at least two gate lines GL electrically connected to the subpixels of the same row are provided on opposite sides of the subpixels of that row. That is, the at least two gate lines GL can be divided into two groups. The gate lines GL of one group may be located on one side of the subpixel row, and the gate lines GL of the other group may be located on the other side of the subpixels of that row. For example, the number of gate lines GL in the two groups may be equal.

[0272] For example, there are six gate lines GL electrically connected to a subpixel in the same row. In this case, three gate lines GL may be located on one side of the subpixel row, and the other three gate lines GL may be located on the other side of the subpixel row.

[0273] The gate line GL arrangement method described above reduces the gap between different gate line GLs and correspondingly electrically connected subpixels 2, thereby reducing the complexity of wiring between different gate line GLs and correspondingly electrically connected subpixels.

[0274] In these embodiments, the number of gate lines GL is relatively large, and consequently, the number of shift registers (for generating scanning signals) that need to be placed on the display board 100 is also relatively large. In this case, the arrangement method for gate lines GL and data lines DL in these embodiments can be applied to a low-resolution display board, thus avoiding adverse effects on the resolution of the display board 100.

[0275] In the embodiment described above, as shown in Figures 3 and 4, for any subpixel in an arbitrary row, after the scan signal level becomes active (i.e., low level), the first current selection signal, the second current selection signal, the first duration selection signal, and the second duration selection signal become low level in a time-sharing manner, and the current data signal and duration data signal are written in a time-sharing manner. Generally, the time interval between signals (indicated by the bidirectional arrows in Figures 3 and 4) is increased to prevent erroneous writing of signals.

[0276] Here, we take the writing and compensation stages corresponding to the current control circuit of a certain subpixel as an example. After the scan signal level becomes low, the current data signal is written to the corresponding current data line DI. After the previous frame is displayed, when the level of the first current selection signal corresponding to this subpixel becomes high, the previously written current data signal is stored in the current data line DI via parasitic capacitance on the current data line DI. In this case, when the next frame is displayed, the current data signal may not be written correctly to the current control circuit (i.e., it may not be written correctly to the control electrode of the drive transistor in the current control circuit).

[0277] For example, in the display of the previous frame, the level of the current data signal is low (voltage value Vdata(n-1)). In the display of the next frame, after the scan signal level becomes low, the current data signal stored in the current data line DI is first written to the current control circuit during the time interval until the level of the first current selection signal changes. After the level of the first current selection signal becomes low, as shown in Figure 3, if the level of the current data signal in the display of the next frame (voltage value Vdata(n)) is higher than the level of the current signal in the display of the previous frame, this data current signal may be continuously written to the current control circuit (as shown in Figure 3, where Vth is the threshold voltage of the current control circuit). As shown in Figure 4, if the level of the current data signal in the display of the next frame (voltage value Vdata(n)) is lower than the level of the current data signal in the display of the previous frame, the writing of the data signal from the previous frame continues (as shown in Figure 4, Vg). As a result, the data signal displayed in this frame is not written correctly, making it difficult for the drive transistor in the current control circuit to turn on correctly, and making it difficult to display the required gradation.

[0278] Therefore, as shown in Figures 10 and 11, in some embodiments of the present disclosure, when the current control circuit 211 generates the drive signal, the period during which the data signal level becomes active is shorter than the period during which the scan signal level becomes active.

[0279] In other words, during the stage of generating the drive signal, the data signal is first transmitted to the corresponding data line DL and may be stored in the parasitic capacitance on the corresponding data line DL. Then, the level of the scan signal becomes the active level, and the data signal is written to the sixth node N6 sequentially via the write subcircuit 2111, the drive subcircuit 2112, and the compensation subcircuit 2113, thereby completing the threshold voltage compensation for the drive subcircuit 211.

[0280] When the current control circuit 211 generates the drive signal, the period during which the data signal level becomes active is set to be shorter than the period during which the scan signal level becomes active. This refreshes the data signal stored on the data line DL before the next frame is displayed, preventing the data signal displayed in the previous frame from remaining. In this way, the refreshed data signal can be received after the scan signal level becomes active, preventing the data signal to be displayed in the next frame from being properly written due to the remaining data signal from the previous frame. As a result, the grayscale level to be displayed can be shown in each subpixel 2, and the display effect of the display board 100 can be enhanced.

[0281] In some examples, when the display board 100 includes a multi-output selection circuit 4, the active level period of the selection signal transmitted by each selection signal line Mux is shorter than the period during which the scan signal level becomes active when the current control circuit 211 generates the drive signal.

[0282] In this way, before the scan signal level reaches the active level, the levels of each selected signal are sequentially changed to the active level, the data signals are written to the corresponding data line DL in a time-sharing manner, and the storage of the corresponding data signals via parasitic capacitance on the data line DL is completed.

[0283] In other examples, when the same data line DL is electrically connected to at least two columns of sub-pixels and one row of sub-pixels is electrically connected to at least two gate lines GL, for each sub-pixel 2, when the current control circuit 211 generates a driving signal, the period during which the level of the data signal becomes the active level is earlier than the period during which the level of the scanning signal becomes the active level. For different sub-pixels 2 that are electrically connected to the same gate line GL and electrically connected to different data lines DL, the scanning signal may have active levels at a plurality of intervals corresponding to the different sub-pixels 2 respectively. In this case, the levels of different data signals both become the active level before the active level of the corresponding scanning signal.

[0284] In some embodiments of the present disclosure, a driving method for a display substrate is provided. The driving method transmits data signals to a plurality of data lines DL of the display substrate 100, and the data signals are received by the current control circuit 211 and the duration control circuit 212 of the same sub-pixel 2. Receive including believing.

[0285] Exemplarily, in the process of driving and displaying the display substrate 100, the active level of the data signal is written to the current control circuit 211 and the duration control circuit 212 in a time-sharing manner.

[0286] In this way, it is separated from the writing and compensation stage corresponding to the current control circuit 211 and the stage of generating the duration control signal corresponding to the duration control circuit 212, that is, they do not overlap, and the level of the data signal does not substantially change in each stage. It is possible to effectively avoid signal crosstalk between two adjacent data lines DL, and avoid the level of the data signal written to the current control circuit 211 from changing due to the change in the level of the data signal written to the duration control circuit 212. As a result, it is advantageous for improving the problem of luminance difference in the column direction.

[0287] In some embodiments, as shown in Figures 6 and 7, the current control circuit 211 includes a data writing subcircuit 2111, a drive subcircuit 2112, a compensation subcircuit 2113, and a light emission control subcircuit 2114. The duration control circuit 212 includes a first control subcircuit 2121, a second control subcircuit 2112, and a third control subcircuit 2123.

[0288] The following schematic explanation of how the display board 100 is driven during the display stage of one frame will be given with reference to the configuration of subpixel 2 shown in Figure 7.

[0289] In some examples, the driving method described above further includes a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4 in the display stage of a single frame. If the gradation levels displayed by the subpixels 2 of the display board 100 are different, the first stage S1 and the second stage S2 will differ slightly. The first stage S1, second stage S2, third stage S3, and fourth stage S4 included in the driving method will be described below based on the gradation displayed by the subpixels 2 of the display board 100.

[0290] For example ,table The grayscale level displayed by the subpixel 2 of the display substrate 100 is equal to or greater than the threshold grayscale level. In this case, a conductive path may always be formed between the pixel driving circuit 21 and the light-emitting element 22, and accordingly, the duration control signal may be used as the first enablement signal.

[0291] In the first stage S1a, as shown in Figure 10, the level of the first reset signal is low, the level of the second reset signal is high, and the level of the data signal is high.

[0292] In response to the first reset signal and data signal received at the first reset signal terminal Res_A, the first control subcircuit 2121 is shut off.

[0293] In the first control subcircuit 2121, the first transistor T1 may conduct under the control of the first reset signal and transmit a data signal to the third node N3. Since the level of the data signal is high, the second transistor T2 in the first control subcircuit 2121 may be blocked under the control of the data signal from the third node N3. In this case, the second enablement signal cannot be transmitted to the second node N2. At this time, the first capacitor C1 in the first control subcircuit 2121 may store the high-level data signal.

[0294] The third transistor T3 of the second control subcircuit 2122 may be blocked under the control of the second reset signal.

[0295] Furthermore, if the current control circuit 211 further includes a reset subcircuit 2115, the tenth transistor T10 and the eleventh transistor T11 in the reset subcircuit 211 may conduct simultaneously under the control of the first reset signal. The tenth transistor T10 may transmit an initial signal to the sixth node N6 in order to reset the sixth node N8. The eleventh transistor T11 may transmit an initial signal to the light-emitting element 22 in order to reset the light-emitting element 22.

[0296] In the second stage S2a, as shown in Figure 10, the level of the first reset signal is high, the level of the second reset signal is low, and the level of the data signal is low.

[0297] In response to the second reset signal and data signal received at the second reset signal terminal Res_B, the second control subcircuit 2122 is activated, and the first enable signal received at the first enable signal terminal EM is transmitted to the second node N2.

[0298] In the second control subcircuit 2122, the third transistor T3 may be conducted under the control of the second reset signal and transmit a data signal to the fourth node N4. Since the level of the data signal is low, the fourth transistor T4 in the second control subcircuit 2122 may be conducted under the control of the data signal from the fourth node N4 and transmit a first enable signal to the second node N2. In this case, the second capacitor C2 in the second control subcircuit 2122 may store the low-level data signal.

[0299] Furthermore, the first transistor T1 in the first control subcircuit 2121 may be interrupted under the control of the first reset signal. In this case, the first capacitor C1 is discharged so that the voltage at the third node N3 is maintained at a high level.

[0300] In the third stage S3a, as shown in Figure 10, the scan signal level is low, the data signal level is low, the first reset signal level is high, and the second reset signal level is high.

[0301] In response to the scan signal received at the scan signal terminal Gate, the data writing subcircuit 2111 and the compensation subcircuit 2113 are activated, and the data signal is transmitted sequentially through the fifth node N5, the drive subcircuit 2112, the first node N1, and the compensation subcircuit 2113 to the sixth node N6, where the threshold voltage is compensated for the drive subcircuit 2112.

[0302] The seventh transistor T7 in the drive subcircuit 2112 may be conducted under the control of an initial signal from the sixth node N6.

[0303] The sixth transistor T6 in the data writing subcircuit 2111 and the eighth transistor T8 in the compensation subcircuit 2113 may conduct simultaneously under the control of the scan signal. The sixth transistor T6 may receive the data signal and transmit it to the sixth node N6 sequentially through the fifth node N5, the seventh transistor T7, the first node N1, and the eighth transistor T8. At this stage, the data signal may be continuously transmitted to the sixth node N6 until the seventh transistor T7 is shut off. This completes the threshold voltage compensation for the seventh transistor T8.

[0304] Furthermore, the first transistor T1 in the first control subcircuit 2121 may be shut off under the control of the first reset signal. In this case, the first capacitor C1 is discharged so that the voltage at the third node N3 is maintained at a high level. The third transistor T3 in the second control subcircuit 2122 may be shut off under the control of the second reset signal. In this case, the second capacitor C2 starts discharging so that the voltage at the fourth node N4 is maintained at a low level, thereby causing the fourth transistor T4 to continuously transmit the first enable signal to the second node N2.

[0305] In the fourth stage S4a, as shown in Figure 10, the level of the first enablement signal is low, the level of the scan signal is high, the level of the first reset signal is high, and the level of the second reset signal is high.

[0306] The light emission control subcircuit 2114 conducts in response to the first enable signal and transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1 sequentially via the fifth node N5 and the drive subcircuit 2112.

[0307] In the light emission control subcircuit 2114, the ninth transistor T9 is conducted under the control of the first enable signal, forming a conductive path between the fifth node N5 and the first voltage signal terminal VDD.

[0308] In the third control subcircuit 2123, the fifth transistor T5 is conducted under the control of the first enable signal from the second node N2, and a conductive path is formed between the first node N1 and the light-emitting element 22.

[0309] The seventh transistor T7 of the drive subcircuit 2112 is conducted and transmits the first voltage signal to the first node N1. The seventh transistor T7 may generate a drive signal based on the voltage value of the data signal written to the sixth node N6 and the voltage value of the first voltage signal.

[0310] At this stage, the first enablement signal causes the first node N1 and the light-emitting element 22 to be continuously connected. In this way, the drive signal can be continuously transmitted to the light-emitting element 22, allowing the light-emitting element 22 to continue emitting light, and furthermore, high-gradation display can be achieved.

[0311] For example, as shown in Figure 11, the grayscale level displayed by the subpixel 2 of the display board 100 is smaller than the threshold grayscale level. In this case, the pixel driving circuit 21 and the light-emitting element 22 alternately enter and exit states, and therefore the duration control signal may be a second enablement signal.

[0312] In the first stage S1b, as shown in Figure 11, the level of the first reset signal is low, the level of the second reset signal is high, and the level of the data signal is low.

[0313] In response to the first reset signal and data signal, the first control subcircuit 2121 is activated, and the second enable signal terminal Hf The second enable signal received is transmitted to the second node N2.

[0314] In the first control subcircuit 2121, the first transistor T1 may be conducted under the control of the first reset signal and transmit the data signal to the third node N3. Since the level of the data signal is low, the second transistor T2 in the first control subcircuit 2121 may be conducted under the control of the data signal from the third node N3 and transmit the second enable signal to the second node N2. In this case, the first capacitor C1 in the first control subcircuit 2121 may store the low-level data signal.

[0315] The third transistor T3 in the second control subcircuit 2122 may be blocked under the control of the second reset signal.

[0316] Furthermore, if the current control circuit 211 further includes a reset subcircuit 2115, the tenth transistor T10 and the eleventh transistor T11 in the reset subcircuit 211 may conduct simultaneously under the control of the first reset signal. The tenth transistor T10 may transmit an initial signal to the sixth node N6 in order to reset the sixth node N6. The eleventh transistor T11 may transmit an initial signal to the light-emitting element 22 in order to reset the light-emitting element 22.

[0317] In the second stage S2b, as shown in Figure 11, the level of the first reset signal is high, the level of the second reset signal is low, and the level of the data signal is high.

[0318] In response to the second reset signal and data signal, the second control subcircuit 2122 is shut off.

[0319] In the second control subcircuit 2122, the third transistor T3 may be conducted under the control of the second reset signal, and a data signal may be transmitted to the fourth node N4. Since the level of the data signal is high, the fourth transistor T4 in the second control subcircuit 2122 may be blocked under the control of the data signal from the fourth node N4. In this case, the first enablement signal cannot be transmitted to the second node N2. In this case, the second capacitor C2 in the second control subcircuit 2122 may store the high-level data signal.

[0320] Furthermore, at this stage, the first transistor T1 in the first control subcircuit 2121 may be shut off under the control of the first reset signal. In this case, the first capacitor C1 may be discharged in order to maintain the voltage at the third node N3 at a low level.

[0321] In the third stage S3b, as shown in Figure 11, the scan signal level is low, the data signal level is low, the first reset signal level is high, and the second reset signal level is high.

[0322] In response to the scan signal received at the scan signal terminal Gate, the data writing subcircuit 2111 and the compensation subcircuit 2113 are activated, and the data signal is transmitted sequentially through the fifth node N5, the drive subcircuit 2112, the first node N1, and the compensation subcircuit 2113 to the sixth node N6, where the threshold voltage is compensated for the drive subcircuit 2112.

[0323] The seventh transistor T7 in the drive subcircuit 2112 may be conducted under the control of an initial signal from the sixth node N6.

[0324] The sixth transistor T6 in the data writing subcircuit 2111 and the eighth transistor T8 in the compensation subcircuit 2113 may conduct simultaneously under the control of the scanning signal. The sixth transistor T6 may receive the data signal and transmit the data signal to the sixth node N6 sequentially through the fifth node N5, the seventh transistor T7, the first node N1, and the eighth transistor T8. At this stage, the data signal may be transmitted continuously to the sixth node N6 until the seventh transistor T7 is cut off. In this case, the threshold voltage compensation for the seventh transistor T8 is completed.

[0325] Furthermore, the third transistor T3 in the second control subcircuit 2122 may be shut off under the control of the second reset signal. In this case, the second capacitor C2 is discharged so that the voltage at the fourth node N4 is maintained at a high level. The first transistor T1 in the first control subcircuit 2121 may be shut off under the control of the first reset signal. In this case, the first capacitor C1 starts discharging so that the voltage at the third node N3 is maintained at a low level, and the second transistor T2 continuously transmits the second enable signal to the second node N2.

[0326] In the fourth stage S4b, as shown in Figure 11, the level of the first enable signal is low, the second enable signal is a high-frequency pulse signal, the level of the scan signal is high, the level of the first reset signal is high, and the level of the second reset signal is high.

[0327] The light-emitting sub-circuit 2114 conducts in response to the first enable signal and transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1 sequentially via the fifth node N5 and the drive sub-circuit 2112.

[0328] In the light emission control subcircuit 2114, the ninth transistor T9 is conducted under the control of the first enable signal, forming a conductive path between the fifth node N5 and the first voltage signal terminal VDD.

[0329] In the third control subcircuit 2123, the fifth transistor T5 alternates between conducting and disconnecting under the control of the second enable signal from the second node N2, thereby causing the first node N1 and the light-emitting element 22 to alternate between conducting and disconnecting.

[0330] In the drive subcircuit 2112, the seventh transistor T7 conducts and transmits a first voltage signal to the first node N1. During the period when the first node N1 and the light-emitting element 22 are conducting, the seventh transistor T7 may generate a drive signal based on the voltage value of the data signal written to the sixth node N6 and the voltage value of the first voltage signal, and transmit the drive signal to the light-emitting element 22 so that the light-emitting element 22 lights up.

[0331] At this stage, the first node N1 and the light-emitting element 22 are alternately in a conductive state and a disconnected state, so the drive signal can be intermittently transmitted to the light-emitting element 22. As a result, the light-emitting element 22 periodically receives the drive signal and emits light periodically. In this way, the total duration of light emission of the light-emitting device 22 can be shortened, and low-gradation level display can be achieved.

[0332] Furthermore, the data line DL on the display board 100 is configured to store data signals. The scanning signal terminal Gate, after storing the data signal on the data line DL in the third stage S3 (i.e., the third stage S3a or the third stage S3b), transmits a scanning signal to control the conduction of the data writing subcircuit 2111 and the compensation subcircuit 2113.

[0333] For example, the data line DL itself has parasitic capacitance. After the data signal is transmitted to the data line DL, the data signal may be stored in the parasitic capacitance of the data line DL.

[0334] For example, the scan signal terminal Gate may transmit a scan signal, which may be supplied from the corresponding gate line GL. In the third stage S3 described above, the data signal level is low (i.e., active level), and the scan signal level is low (i.e., active level). The data line DL receives the data signal, restores the data signal, refreshes itself, and then restores the data signal. The scan signal terminal Gate may then transmit the scan signal, causing the data writing subcircuit 2111 and the compensation subcircuit 2113 to conduct, and the restored data signal on the data line DL to be received and transmitted.

[0335] In this way, the data signal stored on the data line DL is first refreshed, preventing the data signal displayed in the previous frame from remaining. Then, in the display of the next frame, the refreshed data signal can be received after the scan signal level reaches the active level, thereby preventing the data signal to be displayed in the next frame from being properly written due to the remaining data signal from the previous frame. As a result, the grayscale level to be displayed can be shown in each subpixel 2, and the display effect of the display board 100 can be enhanced.

[0336] In some embodiments, as shown in Figure 13, the display board 100 further includes a multi-output selection circuit 4. The driving method for a display board equipped with the multi-output selection circuit 4 will be schematically described below using the timing charts in Figures 14 and 15.

[0337] In the first stage S1 described above (i.e., the first stage S1a or the first stage S1b), selection signals (MUX1 to MUX6) transmitted by multiple selection signal lines Mux are transmitted to the multi-output selection circuit 4. Each selection transistor group 41 in the multi-output selection circuit 4 is made to conduct under the control of the corresponding selection signal, and the data signal from the data transmission line DTL is transmitted to the corresponding data line DL in a time-sharing manner and stored in the parasitic capacitance on the corresponding data line.

[0338] Because there is a time interval between the active levels (i.e., low levels) of the selection signals transmitted by any two adjacent selection signal lines Mux, there is a time interval between the conduction times of any two adjacent transistor groups 41. In this way, data signals from data transmission line DTL may be transmitted to the corresponding data line DL in a time-sharing manner.

[0339] At this stage, the duration of the low level of the first reset signal may be set as needed.

[0340] For example, as shown in Figure 14, after the multi-output selection circuit 4 transmits the data signal to the corresponding data line DL in time-sharing mode, the level of the first reset signal becomes low. The level of the first reset signal is changed to high after the completion of writing the data signal and before the second stage S2.

[0341] In another example, as shown in Figure 15, the multi-output selection circuit 4 transmits the data signal to the corresponding data line DL, while the level of the first reset signal is set to a low level. The level of the first reset signal is changed to a high level before the completion of writing the data signal and before the second stage S2. In this way, the duration of the low level of the first reset signal can be increased, which is advantageous for increasing the duration of writing the data signal.

[0342] In the second stage S2 described above (i.e., the second stage S2a or the second stage S2b), the data signal transmission process is the same as the data information transmission process in the first stage S1, and the method for setting the low-level duration of the second reset signal is the same as the method for setting the high-level duration of the first reset signal, and this will not be repeated here.

[0343] Furthermore, if the duration of the first and second reset signals becomes longer, the frequencies of the first and second reset signals and the data signal will no longer match. In this case, the driver chip 200 may be adjusted to maintain compatibility.

[0344] In the third stage S3 described above (i.e., the third stage S3a or the third stage S3b), before the level of the scan signal is changed to a low level, the multi-output selection circuit 4 completes the time-sharing writing and storage of the data signal.

[0345] If the display duration of one frame is constant, it is understood that the durations of the first stage S1, the second stage S2, and the third stage S3 may each be constant. In this case, assuming that the multi-output selection circuit 4 can transmit data signals to each data line DL in a time-sharing manner, the present disclosure can reduce the duration of the low level (i.e., active level) of each selection signal. This is advantageous in increasing the duration of the low levels of the first reset signal, the second reset signal, and the scan signal, and further in providing sufficient time for writing the data signal and compensating the seventh transistor T7.

[0346] In some other embodiments, as shown in Figure 17, the same data line DL is electrically connected to at least two columns of subpixels, and one row of subpixels is electrically connected to at least two gate lines GL. Referring to the timing chart shown in Figure 18, the driving method of the display board will be schematically explained in an example where the same data line DL is electrically connected to six columns of subpixels, and one row of subpixels is electrically connected to six gate lines (GL1 to GL6).

[0347] As shown in Figure 17, in this example, there are six first reset signal lines RL1 (RL11~RL16) electrically connected to the first reset signal terminal Res_A of the subpixels in the same row, and there are also six second reset signal lines RL2 (RL21~RL26) electrically connected to the second reset signal terminal Res_B of the subpixels in the same row. The connection relationship between the first reset signal line RL1 or the second reset signal line RL2 and the subpixels in the same row may be the same as the connection relationship between the gate line GL and the subpixels in the same column.

[0348] In the first stage S1 described above (i.e., first stage S1a or first stage S1b), the six first reset signal lines (RL11~RL16) each transmit a first reset signal (Res_A1~Res_A6) to the first reset signal terminal Res_A of the corresponding subpixel 2. Since the active level periods of each first reset signal do not overlap, it is advantageous to write the data signal of the same data line DL to different subpixels 2 using time sharing.

[0349] A time interval exists between the active levels (i.e., low levels) of the first reset signals transmitted by any two adjacent first reset signal lines RL1. In this way, the time interval can be used to refresh and store the data signals on each data line DL before the level of each first reset signal becomes active.

[0350] In the second stage S2 described above (i.e., second stage S2a or second stage S2b), the six second reset signal lines (RL21~RL26) each transmit second reset information (Res_B1~Res_B6) to the corresponding second reset signal terminal Res_B of the subpixel 2. Since the active level periods of each second reset signal do not overlap, it is advantageous to write the same data signal DL to different subpixels 2 using time sharing.

[0351] A time interval exists between the active levels (i.e., low levels) of the second reset signals transmitted by any two adjacent second reset signal lines RL2. In this way, the time interval can be used to complete the refresh and storage of the data signals on each data line DL before the level of each second reset signal reaches the active level.

[0352] In the third stage S3 described above (i.e., the third stage S3a or the third stage S3b), the scan signals (Gate1 to Gate6) of the six gate lines GL are each transmitted to the scan signal terminal Gate of the corresponding subpixel. Since the active level periods of each scan signal do not overlap, it is advantageous to write the data signal of the same data line DL to different subpixels 2 using time sharing.

[0353] A time interval exists between the active levels of scan signals transmitted by any two adjacent first gate lines GL. In this way, the time interval can be used to complete the refresh and storage of data signals on each data line DL before the level of each scan signal reaches the active level.

[0354] In some embodiments, the entire period during which the second enablement signal is at an active level (i.e., low level) is in the fourth stage S4. That is, the entire period during which the level of the second enablement signal changes from a high level to a low level is in the fourth stage S4. In the first stage S1, the second stage S2, and the third stage S3, the level of the second enablement signal may be maintained at, for example, an inactive level (i.e., a high level).

[0355] Thus, in the third stage S3, coupling interference of the data signal written to the control electrode of the seventh transistor T7 due to the pull-down of the high frequency of the second enable signal during the threshold voltage compensation process of the seventh transistor T7 can be avoided. Avoiding voltage changes at the control electrode of the seventh transistor T7 is advantageous for enabling the sub-pixel 2 to display the grayscale level correctly. Furthermore, by setting the active level period of the second enablement signal to the fourth stage S4, it is also possible to avoid placing an interference prevention transistor between the fifth transistor T5 and the first node N1. This simplifies the structure of the sub-pixel 2 and improves the commercialization rate of the sub-pixel 2 and the display board 100.

[0356] The above description is merely a specific embodiment of the Disclosure, but the scope of protection of the Disclosure is not limited thereto. Any modification or substitution that a person skilled in the art could conceive of within the technical scope of the Disclosure should be included within the scope of protection of the Disclosure. Accordingly, the scope of protection of the Disclosure must be the same as that of the claims.

Claims

1. Multiple data lines extending in the first direction, It comprises a plurality of subpixels including a pixel driving circuit and a light-emitting element, The pixel driving circuit includes a current control circuit and a duration control circuit electrically connected to the current control circuit and the light-emitting element, wherein the current control circuit is configured to generate a driving signal to drive the light emission of the light-emitting element, and the duration control circuit is configured to generate a duration control signal to control the duration of conduction between the current control circuit and the light-emitting element. The current control circuit and the duration control circuit are electrically connected to the same data line. The current control circuit is electrically connected to at least a scan signal terminal, a data signal terminal, a first enable signal terminal, a first voltage signal terminal, and a first node, and is configured to generate a drive signal in response to a scan signal received at the scan signal terminal, a data signal received at the data signal terminal, a first enable signal received at the first enable signal terminal, and a first voltage signal received at the first voltage signal terminal. The duration control circuit is electrically connected to at least the data signal terminal, the first reset signal terminal, the second reset signal terminal, the first enable signal terminal, the second enable signal terminal, the first node, and the light-emitting element, and the duration control circuit is configured to control the duration of conductivity between the first node and the light-emitting element based on the second enable signal received at the second enable signal terminal in response to the data signal and the first reset signal received at the first reset signal terminal, or to control the duration of conductivity between the first node and the light-emitting element based on the first enable signal in response to the data signal and the second reset signal received at the second reset signal terminal. Display board.

2. The plurality of subpixels are arranged in multiple columns along the second direction, and the same data line is electrically connected to at least one column of subpixels, and / or The plurality of subpixels are arranged in multiple columns along a second direction, the same data line is electrically connected to at least one column of subpixels, and at least one column of subpixels is positioned between any two adjacent data lines. The display board according to claim 1.

3. A multi-output selection circuit electrically connected to the aforementioned multiple data lines, Multiple data transmission lines electrically connected to the multi-output selection circuit, The multi-output selection circuit further comprises a plurality of selection signal lines electrically connected to the aforementioned multi-output selection circuit, The multi-output selection circuit is configured to transmit data signals transmitted by multiple data transmission lines in a time-sharing manner, under the control of the selection signals transmitted by each selection signal line. The display board according to claim 2.

4. The plurality of data lines include at least a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines. The plurality of data transmission lines include at least a plurality of first data transmission lines, a plurality of second data transmission lines, and a plurality of third data transmission lines. The multi-output selection circuit includes a group of selection transistors electrically connected to the selection signal line, the first data line, the second data line, and the third data line. The first data transmission line is electrically connected to at least two groups of select transistors, and electrically connected to the corresponding first data line via the at least two groups of select transistors. The second data transmission line is electrically connected to the at least two selection transistor groups and electrically connected to the corresponding second data line via the at least two selection transistor groups. The third data transmission line is electrically connected to the at least two selection transistor groups and electrically connected to the corresponding third data line via the at least two selection transistor groups. The display board according to claim 3.

5. The first data transmission line, the second data transmission line, and the third data transmission line are arranged periodically. and / or, The first data line, the second data line, and the third data line are arranged periodically. and / or, The group of selection transistors includes at least a first selection transistor, a second selection transistor, and a third selection transistor. The control electrode of the first selection transistor is electrically connected to the selection signal line, the first electrode of the first selection transistor is electrically connected to the first data transmission line, and the second electrode of the first selection transistor is electrically connected to the first data line. The control electrode of the second selection transistor is electrically connected to the selection signal line, the first electrode of the second selection transistor is electrically connected to the second data transmission line, and the second electrode of the second selection transistor is electrically connected to the second data line. The control electrode of the third selection transistor is electrically connected to the selection signal line, the first electrode of the third selection transistor is electrically connected to the third data transmission line, and the second electrode of the third selection transistor is electrically connected to the third data line. The display board according to claim 4.

6. The same data line is electrically connected to at least two rows of subpixels. The display board further comprises a plurality of gate lines extending in a second direction, and one subpixel is electrically connected to one gate line. The plurality of subpixels are arranged in multiple rows along the first direction, and each row of subpixels is electrically connected to at least two gate lines. The at least two gate lines are configured to transmit scan signals to the corresponding subpixels in order to control the reception of data signals transmitted by the plurality of data lines in a time-sharing manner for one row of subpixels. The display board according to claim 2.

7. The number of columns of subpixels electrically connected to the same data line is equal to the number of gate lines electrically connected to the subpixels in the same row, and / or The at least two gate lines are arranged on opposite sides of the subpixel of the row, and / or Within the same row of subpixels, any two adjacent subpixels are electrically connected to different gate lines. The display board according to claim 6.

8. A base on one side in which the plurality of data lines and the plurality of subpixels are arranged, The base further comprises a plurality of connecting wires provided on the edge of the base, one end of each connecting wire being electrically connected to at least one of the data lines, and the other end of each connecting wire being connected to a plurality of connecting wires extending to the other side of the base, If the display board further includes a multi-output selection circuit and a plurality of data transmission lines, one end of the connecting wiring is electrically connected to a data transmission line and electrically connected to the plurality of data lines via the multi-output selection line. The display board according to claim 2.

9. Both the current control circuit and the duration control circuit are electrically connected to the data line via the data signal terminal, The display board according to claim 1.

10. The active level periods of the first reset signal and the active level periods of the second reset signal do not overlap. In the data signal, one of the levels corresponding to the active level of the first reset signal and the level corresponding to the active level of the second reset signal is an active level, and / or In the stage of generating the drive signal, the period during which the data signal level becomes active is shorter than the period during which the scan signal level becomes active. The display board according to claim 9.

11. The aforementioned duration control circuit is At a minimum, a first control subcircuit electrically connected to the data signal terminal, the first reset signal terminal, the second enable signal terminal, and the second node, the first control subcircuit configured to transmit the second enable signal to the second node in response to the data signal and the first reset signal, At a minimum, a second control subcircuit electrically connected to the data signal terminal, the second reset signal terminal, the first enable signal terminal, and the second node, the second control subcircuit configured to transmit the first enable signal to the second node in response to the data signal and the second reset signal, A third control subcircuit electrically connected to the first node, the second node, and the light-emitting element, the third control subcircuit is configured to control the duration of conduction between the first node and the light-emitting device under the control of a signal from the second node, The display board according to claim 9.

12. The current control circuit is, A data writing subcircuit electrically connected to the scan signal terminal, the data signal terminal, and the fifth node, the data writing subcircuit configured to transmit the data signal to the fifth node under the control of the scan signal, At least a drive subcircuit electrically connected to the first node, the fifth node, and the sixth node, configured to transmit a signal from the fifth node to the first node under the control of the voltage of the sixth node, A compensation subcircuit electrically connected to the scanning signal terminal, the first node, and the sixth node, the compensation subcircuit configured to transmit a signal from the first node to the sixth node under the control of the scanning signal in order to compensate the threshold voltage with respect to the drive subcircuit, A light emission control subcircuit electrically connected to the first enable signal terminal, the first voltage signal terminal, and the fifth node, the subcircuit being configured to transmit the first voltage signal to the fifth node under the control of the first enable signal, The display board according to claim 9.

13. A driving method used to drive a display board according to any one of claims 1 to 12, The system includes transmitting data signals to multiple data lines of the display board and receiving data signals by the current control circuit and the duration control circuit of the sub-pixel. A method for driving a display board.

14. The current control circuit includes a data writing subcircuit, a drive subcircuit, a compensation subcircuit, and a light emission control subcircuit, and the duration control circuit includes a first control subcircuit, a second control subcircuit, and a third control subcircuit. The display stages of one frame further include the first stage, second stage, third stage, and fourth stage, If the grayscale level displayed by the subpixels of the display board is equal to or greater than the threshold grayscale level, the driving method In the first step, in response to the first reset signal and the data signal received at the first reset signal terminal, the first control subcircuit is shut off. The second step includes conducting the second control subcircuit in response to the second reset signal and the data signal received at the second reset signal terminal, and transmitting the first enable signal received at the first enable signal terminal to the second node. If the grayscale level displayed by the subpixels of the display board is less than the threshold grayscale level, the driving method In the first stage, in response to the first reset signal and the data signal, the first control subcircuit is activated and the second enable signal received at the second enable signal terminal is transmitted to the second node. In the second stage, in response to the second reset signal and the data signal, the second control subcircuit is shut off. In the third stage, the data writing subcircuit and the compensation subcircuit are activated in accordance with the scan signal received at the scan signal terminal, and the data signal is transmitted to the sixth node sequentially through the fifth node, the drive subcircuit, the first node, and the compensation subcircuit, and the threshold voltage is compensated for the drive subcircuit. The fourth step includes, in response to the first enable signal, conducting the light emission control subcircuit and transmitting the first voltage signal received at the first voltage signal terminal to the first node sequentially via the fifth node and the drive subcircuit, The data line is configured to store the data signal. The scanning signal terminal is configured to transmit the scanning signal in the third stage, after the data line has stored the data signal, in order to control the conduction between the data writing subcircuit and the compensation subcircuit. The driving method according to claim 13.

15. The device comprises at least one display board according to any one of claims 1 to 12. Display device.

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