Indication device

Abstract

To provide a shift resistor that has reduced noise in an output signal and can prevent a deterioration in the characteristics of a transistor.SOLUTION: A display is provided with a first transistor, a second transistor, a third transistor, and a fourth transistor. In the first transistor, a first terminal is connected with first wiring, a second terminal is connected with a gate terminal of the second transistor, and the gate terminal is connected with fifth wiring. In the second transistor, a first terminal is connected with third wiring, and a second terminal is connected with sixth wiring. In the third transistor, a first terminal is connected with second wiring, a second terminal is connected with the gate terminal of the second transistor, and the gate terminal is connected with fourth wiring. In the fourth transistor, a first terminal is connected with the second wiring, a second terminal is connected with the sixth wiring, and the gate terminal is connected with the fourth wiring.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device. In particular, a shift resistance device configured using transistors This relates to a liquid crystal display device having a t-axis. It also relates to a method for driving the liquid crystal display device. This relates to an electronic device having a liquid crystal display as its display unit. [Background technology]

[0002] In recent years, liquid crystal display devices have seen active development due to the increasing number of large display devices such as LCD televisions. In particular, amorphous silicon (hereinafter also called amorphous silicon) is placed on an insulating substrate. Using the transistors configured accordingly, a drive circuit including a pixel circuit and a shift register is constructed. The technology for integrally forming circuits (hereinafter also referred to as internal circuits) is highly beneficial for reducing power consumption and costs. Development is actively underway to make a significant contribution. The internal circuit formed on the insulating substrate is F It is connected to a controller IC (hereinafter also referred to as an external circuit) via a PC or the like, and its operation It will be controlled.

[0003] Among the internal circuits shown above, the one using a transistor made of amorphous semiconductor A shift register has been devised (for example, Patent Document 1). The shift register shown in Patent Document 1 Because the output terminal is floating for a long period, noise shifts into the resistor. There was a problem that occurred in the output signal of the shift register. This Patent Document 1 describes the problem with the shift register. To solve this problem, a shift register configuration was devised in which the output terminal is not made floating. (For example, Non-Patent Document 1) [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Special table 10-500243 [Non-patent literature]

[0005] [Non-Patent Document 1] 2.0inch a-Si:H TFT-LCD with Low Noise Integrated Gate Driver SID'05 Digest P942-945 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In the above Non-Patent Document 1, during the non-selection period, a connection between the output terminal and the negative power supply is described. The transistor turns on. Therefore, the output terminal of the shift register shown in Non-Patent Literature 1 The shift register shown in Non-Patent Document 1 does not float, and the output signal noise is reduced. It can be made smaller.

[0007] However, transistors made of amorphous semiconductors have an on-time and an applied time. It is known that the characteristics deteriorate depending on the voltage applied. In particular, the threshold voltage A threshold voltage shift, which causes the voltage to shift (rise), is one of the major causes of shift register malfunctions. Therefore, in the shift register shown in Non-Patent Document 1, during the non-selection period Because the transistor connected between the output terminal and the negative power supply turns on, this transistor The deterioration of its characteristics can lead to malfunctions.

[0008] In light of these problems, the output signal noise is low during the non-selective period, and the transistor A liquid crystal display device having a shift register that can suppress the degradation of the characteristics of the zista, and An object of the present invention is to provide an electronic device including the liquid crystal display device.

Means for Solving the Problem

[0009] The liquid crystal display device according to the present invention has a pixel portion and a shift register integrally formed with the pixel portion on an insulating substrate. The shift register has a plurality of flip-flops, and each of the plurality of flip-flops turns on at regular intervals during a non-selection period and has a transistor that outputs a power supply potential to an output terminal (scanning line). By this transistor turning on at regular intervals and supplying a power supply potential to the scanning line, each of the plurality of flip-flops suppresses fluctuations in the potential of the scanning line and suppresses characteristic deterioration of the transistor. (scanning line). By this transistor turning on at regular intervals and supplying a power supply potential to the scanning line, each of the plurality of flip-flops suppresses fluctuations in the potential of the scanning line and suppresses characteristic deterioration of the transistor. By this transistor turning on at regular intervals and supplying a power supply potential to the scanning line, each of the plurality of flip-flops suppresses fluctuations in the potential of the scanning line and suppresses characteristic deterioration of the transistor.

[0010] The liquid crystal display device of the present invention has a first pixel and a second pixel having liquid crystal elements, a drive circuit, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring, wherein the first pixel is electrically connected to the drive circuit via the fifth wiring, the second pixel is electrically connected to the drive circuit via the sixth wiring, the drive circuit has a shift register, the shift register has a plurality of flip-flops, and at least one of the plurality of flip-flops has a first transistor, a second transistor, a third transistor, and a fourth transistor, a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a gate terminal of the second transistor, a gate terminal of the first transistor is electrically connected to the fifth wiring, a first terminal of the second transistor is electrically connected to the third wiring, a second terminal of the second transistor is electrically connected to a gate terminal of the third transistor, a gate terminal of the second transistor is electrically connected to the sixth wiring, a first terminal of the third transistor is electrically connected to a fourth wiring, a second terminal of the third transistor is electrically connected to a gate terminal of the fourth transistor, a gate terminal of the third transistor is electrically connected to the second wiring, a first terminal of the fourth transistor is electrically connected to the fifth wiring, a second terminal of the fourth transistor is electrically connected to the scanning line, and the scanning line is electrically connected to the output terminal of the shift register, and the drive circuit supplies a drive signal to the liquid crystal element via the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring, a second terminal of the second transistor is electrically connected to a gate terminal of the third transistor, a gate terminal of the second transistor is electrically connected to the sixth wiring, a first terminal of the third transistor is electrically connected to the fourth wiring, The child is electrically connected to the sixth wire, and the first terminal of the third transistor is electrically connected to the second wire. The terminals are connected, and the second terminal is electrically connected to the gate terminal of the second transistor, and the gate The terminal is electrically connected to the fourth wire, and the first terminal of the fourth transistor is electrically connected to the second wire. The fourth transistor is electrically connected, and the second terminal of the fourth transistor is electrically connected to the sixth wire. The gate terminal of the transistor is electrically connected to the fourth wiring. ru.

[0011] Furthermore, the liquid crystal display device of the present invention comprises a first pixel and a second pixel having liquid crystal elements, and a drive cycle It has a road, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. The first pixel is electrically connected to the drive circuit via the fifth wiring, The second pixel is electrically connected to the drive circuit via the first wiring, and the drive circuit is It has a shift register, and the shift register has multiple flip-flops, and multiple flip-flops. At least one of the flops is the first transistor, the second transistor, the third It has a transistor and a fourth transistor, and the first transistor has a first terminal which is the fifth The wiring is electrically connected, and the second terminal is electrically connected to the gate terminal of the second transistor. The gate terminal is electrically connected to the fifth wire, and the second transistor has the first terminal connected to the fifth wire. The third wire is electrically connected, the second terminal is electrically connected to the first wire, and the third terminal The transistor has its first terminal electrically connected to the gate terminal of the second transistor, and the second terminal The second wire is electrically connected, and the gate terminal is electrically connected to the fourth wire, and the fourth The transistor has its first terminal electrically connected to the first wire and its second terminal electrically connected to the second wire. It is characterized by being electrically connected, with the gate terminal being electrically connected to the fourth wiring. ru.

[0012] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor The first and fourth transistors may be N-channel transistors.

[0013] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor The first and fourth transistors have a semiconductor layer, and the semiconductor layer is made of amorphous silicon. It's okay to have it.

[0014] Furthermore, in the present invention, a capacitive element is placed between the second terminal and the gate terminal of the first transistor. It is also acceptable if they are placed there.

[0015] Furthermore, the liquid crystal display device of the present invention comprises a first pixel and a second pixel having liquid crystal elements, and a drive cycle The road, the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth It has wiring and a seventh wiring, and the first pixel is driven via the fifth wiring The second pixel is electrically connected to the circuit, and the second pixel is electrically connected to the drive circuit via the sixth wiring. The drive circuit is electrically connected and has a shift register, and the shift register has multiple flips It has a flip-flop, and at least one of the multiple flip-flops is the first transistor The second transistor, the third transistor, the fourth transistor and the fifth transistor The first transistor has a first terminal that is electrically connected to a first wire, and a second terminal The child is electrically connected to the gate terminal of the second transistor, and the gate terminal is electrically connected to the fifth wire. The second transistor is electrically connected, with the first terminal electrically connected to the third wire. Two terminals are electrically connected to the sixth wire, and the third transistor has its first terminal connected to the second transistor. The gate terminal of the inverter is electrically connected, and the second terminal is electrically connected to the second wiring. The gate terminal is electrically connected to the fourth wire, and the fourth transistor has the first terminal connected to the sixth The second terminal is electrically connected to the wiring, the second terminal is electrically connected to the second wiring, and the gate terminal is the fourth The fifth transistor is electrically connected to the wiring, and its first terminal is electrically connected to the sixth wiring. The second terminal is electrically connected to the second wire, and the gate terminal is electrically connected to the seventh wire. It is characterized by being connected.

[0016] Furthermore, the liquid crystal display device of the present invention comprises a first pixel and a second pixel having liquid crystal elements, and a drive cycle The road, the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth The first pixel has wiring and the fifth wiring which electrically connects to the drive circuit. The second pixel is electrically connected to the drive circuit via the first wiring. The drive circuit has a shift register, and the shift register has multiple flip-flops. And at least one of the multiple flip-flops is the first transistor, the second transistor It has a third transistor, a fourth transistor and a fifth transistor, In transistor 1, the first terminal is electrically connected to the fifth wire, and the second terminal is connected to the second transistor. The gate terminal of the inverter is electrically connected, and the gate terminal is electrically connected to the fifth wiring. The second transistor has its first terminal electrically connected to the third wire, and its second terminal connected to the sixth The third transistor is electrically connected to the wiring, with the first terminal electrically connected to the second wiring. The second terminal is electrically connected to the gate terminal of the second transistor, and the gate terminal is The fourth transistor is electrically connected to the wiring of the fourth transistor, with the first terminal electrically connected to the first wiring. The second terminal is electrically connected to the second wire, and the gate terminal is electrically connected to the fourth wire. The fifth transistor is connected to the sixth wire, with the first terminal electrically connected to the sixth wire and the second terminal The child is electrically connected to the second wiring, and the gate terminal is electrically connected to the first wiring. It is characterized by the following.

[0017] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor The fourth and fifth transistors are N-channel transistors. That's good too.

[0018] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor The fourth transistor and the fifth transistor each have a semiconductor layer, and the semiconductor layer is made of aluminum Rufus silicone may also be used.

[0019] Furthermore, in the present invention, the second terminal of the first transistor and the gate of the first transistor A capacitive element may be placed between the terminal and the element.

[0020] Furthermore, the liquid crystal display device of the present invention comprises first to fourth pixels having liquid crystal elements, and the first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring The wire, the 5th wire, the 6th wire, the 7th wire, the 8th wire, the 9th wire, and the 1st It has wiring 0, wiring 11, wiring 12, and the first pixel is the fifth The second pixel is electrically connected to the first drive circuit via wiring, and the sixth wiring The third pixel is electrically connected to the first drive circuit via a wire, and the 11th distribution The fourth pixel is electrically connected to the second drive circuit via a wire, and the 12th distribution The first drive circuit is electrically connected to the second drive circuit via a wire, and the first drive circuit is the first shift rail The first shift register has a zista, and the second drive circuit has a second shift register and a first shift register It has multiple flip-flops, and at least one of the multiple flip-flops is The first transistor, the second transistor, the third transistor, and the fourth transistor The first transistor has a first terminal that is electrically connected to a first wire, and a second terminal that It is electrically connected to the gate terminal of the second transistor, and the gate terminal is electrically connected to the fifth wiring. The second transistor is connected to the third wire, with the first terminal electrically connected to the third wire, and the second terminal The child is electrically connected to the sixth wire, and the third transistor has its first terminal electrically connected to the second wire. They are electrically connected, and the second terminal is electrically connected to the gate terminal of the second transistor, The terminal is electrically connected to the fourth wire, and the fourth transistor has its first terminal connected to the second wire. The second terminal is electrically connected to the sixth wiring, and the gate terminal is connected to the fourth wiring. The second shift register is electrically connected to the line and has multiple flip-flops, and multiple At least one of the flip-flops is the fifth transistor, the sixth transistor It has a seventh transistor and an eighth transistor, and the fifth transistor is at the first terminal This is electrically connected to the seventh wire, and the second terminal is electrically connected to the gate terminal of the sixth transistor. The sixth transistor is connected to the first, and its gate terminal is electrically connected to the eleventh wire. Terminal 1 is electrically connected to the 9th wire, and terminal 2 is electrically connected to the 12th wire. The seventh transistor has its first terminal electrically connected to the eighth wire and its second terminal connected to the sixth It is electrically connected to the gate terminal of the transistor, and the gate terminal is electrically connected to the 10th wiring. The eighth transistor has its first terminal electrically connected to the eighth wire, and its second terminal is connected to the It is electrically connected to the 12th wire, and the gate terminal is electrically connected to the 10th wire. It is characterized by the following:

[0021] In this invention, the fifth wiring and the eleventh wiring are electrically connected, and the sixth wiring The wirings of the first and second wires may be electrically connected.

[0022] Furthermore, in the present invention, the fifth wiring and the eleventh wiring are the same wiring, and the sixth wiring The 12th and 2nd wirings may be the same.

[0023] Furthermore, in the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The eighth wiring is electrically connected, the third wiring and the ninth wiring are electrically connected, and the fourth The wiring of part 10 and the wiring of part 10 may be electrically connected.

[0024] Furthermore, in the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The eighth wiring is the same wiring, the third wiring and the ninth wiring are the same wiring, and the fourth The wiring for the first and the wiring for the tenth may be the same.

[0025] Furthermore, in the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The eighth wiring is electrically connected, the third wiring and the ninth wiring are electrically connected, and the fourth The wiring of the first and the tenth wiring are electrically connected, and the fifth and eleventh wiring are electrically connected. The sixth and twelfth wirings may be electrically connected.

[0026] Furthermore, in the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The eighth wiring is the same wiring, the third wiring and the ninth wiring are the same wiring, and the fourth The wiring of the first and the tenth wiring are the same wiring, and the fifth and eleventh wiring are the same wiring. Therefore, the sixth wiring and the twelfth wiring may be the same wiring.

[0027] Furthermore, the liquid crystal display device of the present invention comprises first to fourth pixels having liquid crystal elements, and the first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring The wire, the 5th wire, the 6th wire, the 7th wire, the 8th wire, the 9th wire, and the 1st The first pixel has wiring 0 and the fifth wiring to the first drive circuit Electrically connected, the second pixel is powered to the first drive circuit via the first wiring. Connected electrically, the third pixel is electrically connected to the second drive circuit via the tenth wiring. Connected electrically, the fourth pixel receives electrical power from the second drive circuit via the sixth wiring. They are connected in a specific manner, and the first drive circuit has a first shift register, and the second drive circuit has a first shift register. It has two shift registers, the first shift register has multiple flip-flops, At least one of the multiple flip-flops is the first transistor, the second transistor It has a first transistor, a third transistor and a fourth transistor, and the first transistor is the first The terminal is electrically connected to the fifth wire, and the second terminal is electrically connected to the gate terminal of the second transistor. The second transistor is electrically connected, with its gate terminal electrically connected to the fifth wire. The first terminal is electrically connected to the third wire, and the second terminal is electrically connected to the first wire. The third transistor has its first terminal electrically connected to the gate terminal of the second transistor. The second terminal is electrically connected to the second wire, and the gate terminal is electrically connected to the fourth wire. The fourth transistor has its first terminal electrically connected to the first wiring, and its second terminal connected to the second The wiring is electrically connected, the gate terminal is electrically connected to the fourth wiring, and the second shift A register has multiple flip-flops, and of the multiple flip-flops, at least One is the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor The fifth transistor has a first terminal that is electrically connected to the tenth wire. The second terminal is electrically connected to the gate terminal of the sixth transistor, and the gate terminal is the tenth The sixth transistor is electrically connected to the wiring, with its first terminal electrically connected to the eighth wiring. The second terminal is electrically connected to the sixth wire, and the seventh transistor has the first terminal connected to the The gate terminal of transistor 6 is electrically connected, and the second terminal is electrically connected to the seventh wire. The gate terminal is electrically connected to the 9th wire, and the 8th transistor is connected to the 1st terminal The terminal is electrically connected to the sixth wire, the second terminal is electrically connected to the seventh wire, and the gate terminal The child is characterized by being electrically connected to the ninth wire.

[0028] In this invention, the first wiring and the sixth wiring are electrically connected, and the fifth wiring and The tenth wiring may be electrically connected.

[0029] Furthermore, in the present invention, the first wiring and the sixth wiring are the same wiring, and the fifth wiring and The wiring for the 10th and 10th may be the same wiring.

[0030] Furthermore, in the present invention, the second wiring and the seventh wiring are electrically connected, and the third wiring and The eighth wire is electrically connected, and the fourth and ninth wires are electrically connected. That's good too.

[0031] Furthermore, in the present invention, the second wiring and the seventh wiring are the same wiring, and the third wiring and The eighth and fourth wirings may be the same wiring, and the ninth and fourth wirings may also be the same wiring. stomach.

[0032] Furthermore, in the present invention, the first wiring and the sixth wiring are electrically connected, and the second wiring and The 7th wiring is electrically connected, the 3rd wiring and the 8th wiring are electrically connected, and the 4th The wiring of the first and the wiring of the ninth are electrically connected, and the wiring of the fifth and the wiring of the tenth are electrically connected. It's fine if it is done.

[0033] Furthermore, in the present invention, the first wiring and the sixth wiring are the same wiring, and the second wiring and The seventh wiring is the same wiring, the third wiring and the eighth wiring are the same wiring, and the fourth The wiring of the first and the ninth wire are the same wiring, and the fifth and tenth wires are the same wiring. It's okay to have it.

[0034] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor T, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor The first and eighth transistors may be N-channel transistors.

[0035] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor T, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor The 8th and 1st transistors have a semiconductor layer, and the semiconductor layer is made of amorphous silicon. It's okay to have it.

[0036] Furthermore, in the present invention, the second terminal of the first transistor and the gate of the first transistor A first capacitive element is placed between the terminal and the second terminal of the fifth transistor and the fifth A second capacitive element may be placed between the gate terminal of the transistor and the second capacitive element.

[0037] Furthermore, the liquid crystal display device of the present invention comprises first to fourth pixels having liquid crystal elements, and the first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring The wire, the 5th wire, the 6th wire, the 7th wire, the 8th wire, the 9th wire, and the 1st It has wiring 0, wiring 11, wiring 12, wiring 13, and wiring 14. The first pixel is electrically connected to the first drive circuit via the fifth wiring. The second pixel is electrically connected to the first drive circuit via the sixth wiring, The third pixel is electrically connected to the second drive circuit via the 12th wiring, The fourth pixel is electrically connected to the second drive circuit via the thirteenth wiring, The first drive circuit has a first shift register, and the second drive circuit has a second shift register The first shift register has a number of flip-flops, and the flip At least one of the flops is a first transistor, a second transistor, a third transistor It has a transistor, a fourth transistor and a fifth transistor, and the first transistor is The first terminal is electrically connected to the first wiring, and the second terminal is the gate terminal of the second transistor. The child is electrically connected, and the gate terminal is electrically connected to the fifth wiring, and the second transistor The first terminal of the terminal is electrically connected to the third wire, and the second terminal is electrically connected to the sixth wire. The third transistor has its first terminal electrically connected to the second wiring, and the second terminal is the The gate terminal of transistor 2 is electrically connected, and the gate terminal is electrically connected to the fourth wire. The fourth transistor is connected, with the first terminal electrically connected to the second wiring, and the second terminal The sixth wire is electrically connected, and the gate terminal is electrically connected to the fourth wire, and the fifth The transistor has its first terminal electrically connected to the second wire, and the second terminal connected to the sixth wire. Electrically connected, the gate terminal is electrically connected to the 7th wiring, and the 2nd shift register It has multiple flip-flops, and at least one of the multiple flip-flops is The sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and It has a 10th transistor, and the 6th transistor has its first terminal electrically connected to the 8th wiring. It is connected to the gate terminal of the seventh transistor, and the second terminal is electrically connected to the gate terminal of the seventh transistor. The child is electrically connected to the 12th wire, and the 7th transistor has its first terminal connected to the 10th wire. The second terminal is electrically connected to the thirteenth wire, and the eighth transistor The first terminal is electrically connected to the ninth wire, and the second terminal is connected to the gate of the seventh transistor. The terminal is electrically connected, the gate terminal is electrically connected to the 11th wiring, and the 9th transistor The ZISTA has its first terminal electrically connected to the 13th wire, and its second terminal electrically connected to the 9th wire. The gate terminal is connected to the 11th wire, and the 10th transistor is connected to the 11th wire. The first terminal is electrically connected to the thirteenth wire, and the second terminal is electrically connected to the ninth wire. It is characterized by the gate terminal being electrically connected to the 14th wire.

[0038] In this invention, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring The wiring and the 13th wiring may be electrically connected.

[0039] Furthermore, in the present invention, the fifth wiring and the twelfth wiring are the same wiring, and the sixth wiring The 13th and 12th wirings may be the same.

[0040] Furthermore, in the present invention, the first wiring and the eighth wiring are electrically connected, and the second wiring and The 9th wiring is electrically connected, the 3rd wiring and the 10th wiring are electrically connected, Wiring 4 and wiring 11 are electrically connected, and wiring 7 and wiring 14 are electrically It should be connected.

[0041] Furthermore, in the present invention, the first wiring and the eighth wiring are the same wiring, and the second wiring and The 9th wiring is the same wiring, the 3rd wiring and the 10th wiring are the same wiring, and Wiring 4 and wiring 11 are the same wiring, and wiring 7 and wiring 14 are the same wiring A line is also acceptable.

[0042] Furthermore, in the present invention, the first wiring and the eighth wiring are electrically connected, and the second wiring and The 9th wiring is electrically connected, the 3rd wiring and the 10th wiring are electrically connected, Wiring 4 and wiring 11 are electrically connected, and wiring 5 and wiring 12 are electrically The sixth and thirteenth wires are electrically connected, and the seventh and fourteenth wires are electrically connected. The wires may be electrically connected.

[0043] Furthermore, in the present invention, the first wiring and the eighth wiring are the same wiring, and the second wiring and The 9th wiring is the same wiring, the 3rd wiring and the 10th wiring are the same wiring, and Wiring 4 and wiring 11 are the same wiring, and wiring 5 and wiring 12 are the same wiring It is a line, and the 6th wiring and the 13th wiring are the same wiring, and the 7th wiring and the 14th wiring The wires may be of the same type.

[0044] Furthermore, the liquid crystal display device of the present invention comprises first to fourth pixels having liquid crystal elements, and the first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring The wire, the 5th wire, the 6th wire, the 7th wire, the 8th wire, the 9th wire, and the 1st It has wiring 0, wiring 11, wiring 12, and the first pixel is the fifth The second pixel is electrically connected to the first drive circuit via wiring, and the sixth wiring The third pixel is electrically connected to the first drive circuit via a wire, and the 11th distribution The fourth pixel is electrically connected to the second drive circuit via a wire, and the 12th distribution The first drive circuit is electrically connected to the second drive circuit via a wire, and the first drive circuit is the first shift rail The first shift register has a zista, and the second drive circuit has a second shift register and a first shift register It has multiple flip-flops, and at least one of the multiple flip-flops is The first transistor, the second transistor, the third transistor, the fourth transistor and The first transistor has a fifth transistor, and the first terminal is electrically connected to the fifth wiring. The second terminal is electrically connected to the gate terminal of the second transistor, and the gate terminal The second transistor is electrically connected to the fifth wire, and the first terminal is electrically connected to the third wire. The second terminal is electrically connected to the sixth wire, and the third transistor is connected to the first The terminal is electrically connected to the gate terminal of the second transistor, and the second terminal is electrically connected to the second wiring. The gate terminal is electrically connected to the fourth wire, and the fourth transistor is, The first terminal is electrically connected to the sixth wire, and the second terminal is electrically connected to the second wire. The gate terminal is electrically connected to the fourth wire, and the fifth transistor has its first terminal connected to the sixth The first terminal is electrically connected to the wiring, the second terminal is electrically connected to the second wiring, and the gate terminal is the first The second shift register is electrically connected to the wiring and has multiple flip-flops. At least one of the multiple flip-flops is the sixth transistor, the seventh transistor It has a st, an 8th transistor, a 9th transistor and a 10th transistor, and a 6th The transistor has its first terminal electrically connected to the 11th wire and its second terminal connected to the 7th transistor. The gate terminal of the inverter is electrically connected, and the gate terminal is electrically connected to the 11th wiring. The seventh transistor has its first terminal electrically connected to the ninth wire, and its second terminal connected to the first The 8th transistor is electrically connected to the 2nd wire, and the 1st terminal is electrically connected to the 8th wire. The second terminal is electrically connected to the gate terminal of the seventh transistor, and the gate terminal The 10th wire is electrically connected, and the 9th transistor has its first terminal electrically connected to the 8th wire. It is electrically connected, the second terminal is electrically connected to the 12th wiring, and the gate terminal is connected to the 10th wiring The 10th transistor is electrically connected to the wire, with its first terminal electrically connected to the 8th wire. The second terminal is electrically connected to the twelfth wire, and the gate terminal is electrically connected to the seventh wire. It is characterized by being connected.

[0045] In this invention, the fifth wiring and the eleventh wiring are electrically connected, and the sixth wiring The wirings of the first and second wires may be electrically connected.

[0046] In this invention, the fifth wiring and the eleventh wiring are the same wiring, and the sixth wiring The 12th and 2nd wirings may be the same.

[0047] In this invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The eighth wiring is electrically connected, the third wiring and the ninth wiring are electrically connected, and the fourth The wiring of part 10 and the wiring of part 10 may be electrically connected.

[0048] In this invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The eighth wiring is the same wiring, the third wiring and the ninth wiring are the same wiring, and the fourth The wiring for the first and the wiring for the tenth may be the same.

[0049] In this invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The eighth wiring is electrically connected, the third wiring and the ninth wiring are electrically connected, and the fourth The wiring of the first and the tenth wiring are electrically connected, and the fifth and eleventh wiring are electrically connected. The sixth and twelfth wirings may be electrically connected.

[0050] In this invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The eighth wiring is the same wiring, the third wiring and the ninth wiring are the same wiring, and the fourth The wiring of the first and the tenth wiring are the same wiring, and the fifth and eleventh wiring are the same wiring. Therefore, the sixth wiring and the twelfth wiring may be the same wiring.

[0051] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor T, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor The eighth, ninth, and tenth transistors are N-channel. A transistor of this type is also acceptable.

[0052] Furthermore, in the present invention, the first transistor, the second transistor, and the third transistor T, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor The eighth, ninth, and tenth transistors are semiconductor layers. The semiconductor layer may be amorphous silicon.

[0053] Furthermore, in this invention, the second terminal of the first transistor and the gate of the first transistor A first capacitive element is placed between the terminal and the second terminal of the sixth transistor and the first A second capacitive element may be placed between the gate terminal of the transistor and the second capacitive element.

[0054] The present invention is an electronic device comprising the liquid crystal display device described above.

[0055] The switches described herein can be of various forms, and as an example, There are electrical switches and mechanical switches, etc. In other words, they are devices that can control the flow of electric current. It's fine as long as it's available, and it's not limited to a specific item; various things can be used. For example, tiger You can use an inverter, or a diode (for example, a PN diode, a PIN diode, a shock absorber) You can use a Tokey diode, a diode-connected transistor, or even a thyristor. Alternatively, a logic circuit combining these elements would also suffice. Therefore, a transistor can be used as a switch. When used, the transistor acts simply as a switch, therefore the transistor The polarity (conductivity type) is not particularly limited. However, if a lower off-current is desirable, then the off-current is... It is desirable to use a transistor with the polarity that generates less current. As for ZISTA, there are those that have an LDD area and those that have a multi-gate structure. Furthermore, the potential of the source terminal of the transistor used as a switch is the low-potential side power supply. If it is operating in a state close to (Vss, GND, 0V, etc.), use an N-channel type, and conversely, P-channel operation when the terminal potential is close to the high-potential power supply (Vdd, etc.) It is preferable to use a type because it allows for a larger absolute value of the voltage between the gate and source. Therefore, it allows for more precise operation as a switch.

[0056] Furthermore, a CMOS switch can be constructed using both N-channel and P-channel types. If a CMOS type switch is used, the P-channel or N-channel switch will conduct. Because it can conduct electricity, it can function more accurately as a switch. For example, whether the voltage of the input signal to the switch is high or low, it outputs the correct voltage. It is possible to do this. Also, the voltage amplitude value of the signal to turn the switch on or off can be controlled. Because it can be made smaller, power consumption can also be reduced. Also, as a switch When using a transistor, the input terminal (either the source terminal or the drain terminal) and The output terminal (either the source terminal or the drain terminal) and the terminal that controls conductivity (gate terminal) ) has. On the other hand, when a diode is used as a switch, the terminal that controls the conduction It may not have children. Therefore, the wiring required to control the terminals can be reduced. Yes, it's possible.

[0057] In this specification, "connected" refers to both an electrically connected and a functionally connected This includes both connected and directly connected cases. Therefore, this specification The configuration disclosed in this document shall include relationships other than those specified. For example, a An element that enables an electrical connection between two parts (for example, a switch or a transistor) Even if one or more elements (such as resistors, capacitive elements, inductors, resistors, or diodes) are present Good. Also, circuits that enable functional connections (for example, logic circuits (inverters and NAND) Circuits such as NOR gates and signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits) (etc.) and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, and H signals and L signals) (Level shifter circuits that change the position level, etc.) or voltage sources, current sources, switching circuits, and amplification circuits ( Operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc., are used to measure signal amplitude and current. Circuits that can enlarge things, such as signal generation circuits, memory circuits, and control circuits, with one or fewer in between. It may be positioned above. Alternatively, it may be directly connected without other elements or circuits in between. And it's fine if they're positioned that way.

[0058] Furthermore, if this includes only cases where elements or circuits are connected without any intermediaries, then it is considered a direct connection. It should be written as "present". Also, when writing "electrically connected", use the term "electrical". When they are connected (i.e., connected with another element in between) and functionally When connected (i.e., connected with another circuit in between) and when directly connected When this is the case (i.e., when they are connected without another element or circuit in between) It shall include.

[0059] Furthermore, display elements, display devices, light-emitting elements, and light-emitting devices can be used in various forms. Furthermore, it can have various elements. For example, display elements, display devices, light-emitting elements, and light-emitting devices. As for placement, EL elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic materials) Children), electron emission elements, liquid crystal elements, electronic ink, grating light bulbs (GLV), Plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric sensors Aluminium displays, or carbon nanotubes, etc., are generated by electromagnetic forces. A display medium in which trust changes can be applied. Examples include EL displays, and as display devices using electron emission elements, field emitters. Flat-panel displays (FED) and SED type flat-panel displays (SED: Surface -conduction (electron-emitter, display), etc. Display devices using crystal elements include liquid crystal displays, transmissive liquid crystal displays, and semi-transmissive liquid crystal displays. Liquid crystal displays, reflective liquid crystal displays, and display devices using electronic ink are examples of electronic ink displays. There is paper.

[0060] In this specification, transistors refer to various types of transistors. This is possible. Therefore, there are no limitations on the types of transistors that can be used. For example, Thin-film transients having non-single-crystal semiconductor films, such as amorphous silicon and polycrystalline silicon. TFTs and the like can be applied. This allows for the use of single-crystal semiconductor films. It can be manufactured at lower temperatures, at lower costs, and on larger substrates, and is transparent. It is possible to manufacture transistors that can be fabricated on a light substrate and that can transmit light, and also transistors A zista can be used to control the transmission of light in the display element. Furthermore, semiconductor substrates and SO2 can be used. It can be formed using an I substrate or the like. Also, MOS type transistors, junction type transistors Distors, bipolar transistors, etc. can be applied. This reduces variability. It becomes possible to manufacture transistors with low current output, or transistors with high current supply capability. This allows for the manufacture of small transistors and the construction of circuits with low power consumption. This is possible. Also, compound semiconductors such as ZnO, α-InGaZnO, SiGe, and GaAs can be used. This applies to transistors that have [certain properties], and further, thin-film transistors that are made by thinning these transistors. This allows for manufacturing at low temperatures, including at room temperature, and enables the production of materials with low heat resistance. It is possible to form transistors directly on a substrate, such as a plastic substrate or a film substrate. Furthermore, transistors formed using inkjet or printing methods can be applied. Yes, it is possible. These methods allow for manufacturing at room temperature, manufacturing under low vacuum conditions, and manufacturing on large substrates. It can be manufactured. Furthermore, it can be manufactured without using a mask (reticle). Therefore, the layout of transistors can be easily changed. Also, organic semiconductors or transistors containing carbon nanotubes, and other transistors can be applied. Yes, it is possible. These methods allow for the formation of bendable transistors. Non-single-crystal semiconductor films may contain hydrogen or halogen. Also, transistors The type of substrate on which it is formed can vary and is not limited to a specific type. Therefore, for example, as a substrate, a single crystal substrate, an SOI substrate, a glass substrate, or quartz are possible. Circuit boards, plastic circuit boards, paper circuit boards, cellophane circuit boards, stone circuit boards, stainless steel circuit boards A substrate having stainless steel foil can be used. A transistor is formed on one substrate, and then the transistor is moved to another substrate and then placed on yet another substrate. It may also be placed as follows. Other substrates that can be placed include single crystal substrates, SOI substrates, and glass substrates. Stainless steel substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, stainless steel • Steel substrates, substrates having stainless steel foil, etc. can be used. By using these substrates, transistors with good characteristics can be formed, and also, This allows for the creation of transistors with low power consumption and a more durable device. Furthermore, it can be made heat-resistant.

[0061] Furthermore, transistor configurations can take various forms. They are not limited to a specific configuration. For example, a multi-gate structure with two or more gate electrodes may be used. When a tigate structure is used, the channel regions are connected in series, so multiple This configuration is like having transistors connected in series. By using a multi-gate structure... This reduces the off-current and improves the reliability by increasing the transistor's voltage rating. Furthermore, when operating in the saturation region, even if the voltage between the drain and source changes, the drain and This allows for a flat characteristic curve, where the current between sources does not change much. A structure in which gate electrodes are positioned above and below the Nell is also acceptable. By arranging the components in this way, the channel area increases, thus increasing the current value. This allows for the formation of depletion layers, which can reduce the S value. When gate electrodes are placed above and below, it creates a configuration similar to multiple transistors connected in parallel. This is the result.

[0062] Furthermore, there are structures where the gate electrode is positioned above the channel, and structures where the gate electrode is positioned below the channel. The structure is arranged in a positive staggered structure, an inverse staggered structure, and the channel region is divided into multiple regions. To create a structure where the gate electrodes are connected in parallel or in series. This is possible. Also, the source electrode and drain electrode overlap the channel (or part thereof). It is fine if the source electrode or drain electrode overlaps the channel (or part thereof). By creating such a structure, charge can accumulate in part of the channel, leading to unstable operation. This can be prevented. Furthermore, it is possible to have a configuration with an LDD area. By providing a D region, the off-current is reduced and the transistor's breakdown voltage is improved, thus increasing reliability. Reliability can be improved, and the voltage between the drain and source when operating in the saturation region. Even if the current changes, the current between the drain and source will not change much, resulting in a flat characteristic curve. It is possible.

[0063] Furthermore, various types of transistors can be used in this specification, and various substrates can be used. It can be formed on top. Therefore, the entire circuit is formed on the glass substrate. It may be formed on a plastic substrate, or it may be formed on a single crystal substrate. It may be formed on an SOI substrate, or it may be formed on any substrate. This is also good. By forming the entire circuit on the same board, the number of components can be reduced and cost This can reduce the number of connections to circuit components and improve reliability. It is possible. Alternatively, part of the circuit may be formed on a substrate, and another part of the circuit may be formed on a substrate. The part may be formed on a different substrate. In other words, the entire circuit may not be formed on the same substrate. It is not necessary. For example, part of the circuit can be formed using transistors on a glass substrate, and the circuit Another part is formed on a single crystal substrate, and the IC chip is mounted on COG (Chip On Gla). The IC chip may be connected using ss) and placed on a glass substrate. Alternatively, the IC chip may be connected using TAB(T APE Automated Bonding (APE) or a printed circuit board is used to bond the glass substrate. It may be continued. In this way, because a part of the circuit is formed on the same board, the component points Reducing the number of components lowers costs and also reduces the number of connections to circuit components, thus improving reliability. It can improve performance. Also, parts with high drive voltage or high drive frequency Because this would increase power consumption, such parts should not be formed on the same circuit board. This will prevent an increase in power consumption.

[0064] In this specification, one pixel refers to a single element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and one of those color elements Brightness is expressed using the R (red), G (green), and B (blue) color elements. In the case of a color display device, the smallest unit of an image is a triangular array consisting of a red pixel, a green pixel, and a blue pixel. It shall be composed of elements. Furthermore, the color elements are not limited to three colors, but may include more than three. You can do that, or you can add colors other than RGB. For example, you can add white to make RGBW(W is You may also use white. Alternatively, you could use RGB for, for example, yellow, cyan, magenta, emerald It is also acceptable to add one or more colors such as green or vermilion. Also, for example, a small number of RGB colors For each color, you may add similar colors. For example, R, G, B1, B2. Good. Both B1 and B2 are blue, but their frequencies are slightly different. By using color elements, it is possible to display objects more realistically and reduce power consumption. It is possible to do this. Another example is to use multiple regions to increase the brightness of a single color element. When controlling the depth, one area is considered one pixel. Therefore, as an example, area gradation When performing this, there are multiple areas for controlling the brightness for each color element, and the overall gradation is controlled by these areas. In this representation, one pixel is defined as one area where brightness is controlled. In this case, one color element is composed of multiple pixels. In some cases, the size of the area contributing to the display may differ. Also, for a single color element... In the multiple areas that control brightness, that is, the multiple images that make up a single color element In the basics, the signals supplied to each are slightly different to broaden the field of view. It is permissible to do so. Note that when referring to one pixel (three colors), one pixel refers to three pixels: R, G, and B. Let's assume this is the case. When we write "one pixel (one color)", for each color element, Let's assume that when there are multiple pixels, they are considered as a single pixel.

[0065] In this specification, pixels include cases where they are arranged (arranged) in a matrix. Yes. Here, when we say that pixels are arranged (arranged) in a matrix, it means in the vertical or horizontal direction. This includes cases where they are arranged in a straight line or along a jagged line. Therefore, for example, when displaying full color using three color elements (e.g., RGB) In cases where the dots are arranged in stripes, or where the three color elements are arranged in a so-called delta configuration This includes cases where they are present. Furthermore, it also includes cases where they are in a Bayer configuration. The color elements are not limited to three colors; there can be more, for example, RGBW (W is white) or RG This includes variations of B with the addition of one or more colors such as yellow, cyan, and magenta. The size of the display area for each individual dot may differ. This reduces power consumption. Furthermore, it can extend the lifespan of the display elements.

[0066] Note that a transistor is defined as a device that includes at least a gate, a drain, and a source. It is an element having three terminals, with a channel region between the drain region and the source region. Therefore, current can be passed through the drain region, channel region, and source region. Therefore, the source and drain vary depending on the transistor's structure and operating conditions. It is difficult to determine whether the discrepancy is in the source or the drain. Therefore, in this specification... In this context, the regions that function as both source and drain are referred to as source or drain. There are cases where this is not possible. In such cases, for example, they may be referred to as terminal 1 and terminal 2, respectively. There is. Furthermore, a transistor has at least three components, including the base, emitter, and collector. It may also be an element having terminals. In this case as well, the emitter and collector are the first terminal It may be referred to as "child" or "second terminal."

[0067] Note that "gate" refers to the gate electrode and gate wiring (also called gate wire or gate signal wire, etc.). It refers to the whole including or a part of them. The gate electrode is the channel region. A semiconductor film that forms regions such as LDD (Lightly Doped Drain), This refers to the conductive film in the overlapping portion across the gate insulating film. This is a wiring that connects the gate electrodes of each pixel, or connects the gate electrode to another wire. It refers to a line.

[0068] However, there are also parts that function as both gate electrodes and gate wiring. Such a region can be called a gate electrode or gate wiring. There are also regions where the gate electrode and gate wiring cannot be clearly distinguished. For example, If there is a channel area that overlaps with the gate wiring that is extended and placed, that area The region functions as gate wiring, but it also functions as gate electrode. That area can be called a gate electrode, or it can be called gate wiring.

[0069] Furthermore, the region formed from the same material as the gate electrode and connected to the gate electrode is also a gate electrode. It can also be called a pole. Similarly, it is formed from the same material as the gate wiring and connected to the gate wiring. The area where it is located can also be called gate wiring. Strictly speaking, such an area is a channel. It did not overlap with the region, or it did not have the function to connect to another gate electrode. In some cases, this may occur. However, due to the need to create a margin during manufacturing, gate electrodes and gates It has a region formed from the same material as the wiring, and is connected to the gate electrode and gate wiring. Therefore, such areas can also be called gate electrodes or gate wiring.

[0070] Also, for example, in a multi-gate transistor, the gate electrode of one transistor The gate electrode of another transistor is connected by a conductive film made of the same material as the gate electrode. They are often connected. Such areas are for connecting gate electrodes. Since it is a region, it can also be called gate wiring, but a multi-gate transistor is a single gate It can also be considered a transistor, so it can be called a gate electrode. Those formed from the same material as the electrodes and gate wiring, and arranged in connection with them, It can also be called a gate electrode or gate wiring. Furthermore, for example, connecting the gate electrode and gate wiring... The conductive film in the connected portion can also be called a gate electrode or gate wiring. .

[0071] Note that a gate terminal refers to the gate region, or a part of the gate electrode, or the connection between the gate electrode and the electrical terminal. This refers to some or all of the areas that are connected by air.

[0072] The source refers to the source region, source electrodes, and source wiring (source wire or source signal wire). It refers to the whole including (and so on), or a part of them. The source area is, Semi-liquids containing large amounts of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic) This refers to the conductive region. Therefore, it is a region that contains a small amount of P-type or N-type impurities. The LDD (Lightly Doped Drain) area is not included in the source area. It cannot be. The source electrode is formed from a different material than the source region and is electrically connected to the source region. This refers to the conductive layer in the part where components are continuously arranged. However, the source electrode is the source region. It is sometimes also called a source electrode. Source wiring refers to the connection between the source electrodes of each pixel. Alternatively, it refers to wiring used to connect a source electrode to another wire.

[0073] However, there are also parts that function as both source electrodes and source wiring. It exists. Such a region may be called a source electrode or a source wiring. In other words, there are regions where the source electrode and source wiring cannot be clearly distinguished. If there is a source area that overlaps with the source wiring that is extended and placed, This region functions as a source wire, but it also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring. .

[0074] Furthermore, the region formed from the same material as the source electrode and connected to the source electrode, and the source electrode The part connecting the electrode and the source electrode can also be called the source electrode. The overlapping portion can also be called the source electrode. Similarly, the same material as the source wiring... Areas formed by material and connected to source wiring can also be called source wiring. In a strict sense, such regions may not have the function of connecting to another source electrode. However, due to the need to provide a margin during manufacturing, it is formed from the same material as the source electrode and source wiring. Furthermore, there are regions that are connected to the source electrode and source wiring. Therefore, such regions as well You could also call them source electrodes or source wiring.

[0075] Furthermore, for example, the conductive film in the part connecting the source electrode and the source wiring is also the same as the source electrode. You can call it that, or you can call it source wiring.

[0076] Note that a source terminal refers to the source region, a part of the source electrode, or a part that is electrically connected to the source electrode. This refers to some or all of the connected areas.

[0077] The drain is the same as the source.

[0078] In this specification, semiconductor device refers to semiconductor element (such as transistors and diodes). This refers to a device that has a circuit including [a specific component]. It also refers to any device that can function by utilizing semiconductor properties. However, that is also acceptable. Furthermore, a display device is a device that has a display element (such as a liquid crystal element or a light-emitting element). This refers to a set of multiple pixels, including display elements such as liquid crystal elements and EL elements, and those pixels. It may also refer to the display panel body, in which the peripheral drive circuits that drive the panel are formed on the same circuit board. peripheral drive circuits, which are placed on the circuit board by wire bonding or bumps, so It may also include IC chips connected via chip-on-glass (COG). Furthermore, A flexible cable to which ICs, resistors, capacitive elements, inductors, transistors, etc. are attached. It may also include a flexible printed circuit (FPC) or printed wiring board (PWB). It may also include optical sheets such as polarizing plates and phase difference plates. Furthermore, the backlight unit (Light guide plates, prism sheets, diffusion sheets, reflective sheets, and light sources (LEDs, cold cathode tubes, etc.) It may include ) and ). Also, the light-emitting device may include EL elements and FE This refers to a display device that has self-emissive display elements such as the elements used in D. This refers to a display device that has liquid crystal elements.

[0079] In this specification, a term formed on or on an object is used. The expressions "ru" and "~on top of" or "~on top of" mean "on top of a certain object." This is not limited to direct contact. It also applies to cases where there is no direct contact, that is, when there is something in between. This includes cases where it is sandwiched. Therefore, for example, on top of layer A (or on top of layer A), When we say that layer B is formed, it means that layer B is formed in direct contact with layer A. And, another layer (for example, layer C or layer D) is formed directly in contact with layer A, and on top of that This includes cases where layer B is formed in direct contact with the layer. Also, the notation "above ~" is used. The same applies to "carrying"; it is not limited to being in direct contact with one object, but also to being in contact with another object in between. This also includes cases where layer B is sandwiched in between. Therefore, for example, if layer B is formed above layer A If it is said that layer B is formed directly on top of layer A, then layer B is formed directly on top of layer A. Another layer (for example, layer C or layer D) is formed in contact with it, and layer B is directly in contact with it. This includes cases where it is formed. Furthermore, in the case of "below" or "below" The same applies to combinations, including cases where they are directly in contact and cases where they are not. ru. [Effects of the Invention]

[0080] The present invention makes it possible to suppress the degradation of transistor characteristics. This prevents shift register malfunctions caused by degradation of the shift register's characteristics. This can suppress display malfunctions in liquid crystal displays caused by ZIST malfunctions. [Brief explanation of the drawing]

[0081] [Figure 1] A diagram illustrating Embodiment 1. [Figure 2] A diagram illustrating Embodiment 1. [Figure 3] A diagram illustrating Embodiment 1. [Figure 4] A diagram illustrating Embodiment 1. [Figure 5] A diagram illustrating Embodiment 1. [Figure 6] A diagram illustrating Embodiment 1. [Figure 7] A diagram illustrating Embodiment 1. [Figure 8] A diagram illustrating Embodiment 1. [Figure 9] A diagram illustrating Embodiment 1. [Figure 10] A diagram illustrating Embodiment 1. [Figure 11] A diagram illustrating Embodiment 1. [Figure 12] A diagram illustrating Embodiment 1. [Figure 13] A diagram illustrating Embodiment 2. [Figure 14] A diagram illustrating Embodiment 2. [Figure 15] A diagram illustrating Embodiment 2. [Figure 16] A diagram illustrating Embodiment 2. [Figure 17] A diagram illustrating Embodiment 2. [Figure 18] A diagram illustrating Embodiment 2. [Figure 19] A diagram illustrating Embodiment 3. [Figure 20] A diagram illustrating Embodiment 3. [Figure 21] A diagram illustrating Embodiment 3. [Figure 22] A diagram illustrating Embodiment 3. [Figure 23] A diagram illustrating Embodiment 4. [Figure 24] Figure for explaining Embodiment 4. [Figure 25] Figure for explaining Embodiment 4. [Figure 26] Figure for explaining Embodiment 4. [Figure 27] Figure for explaining Embodiment 5. [Figure 28] Figure for explaining Embodiment 5. [Figure 29] Figure for explaining Embodiment 5. [Figure 30] Figure for explaining Embodiment 5. [Figure 31] Figure for explaining Embodiment 5. [Figure 32] Figure for explaining Embodiment 6. [Figure 33] Figure for explaining Embodiment 6. [Figure 34] Figure for explaining Embodiment 6. <…>​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Figure for explaining Embodiment 9. [Figure 50] Figure for explaining Embodiment 9. [Figure 51] Figure for explaining Embodiment 9. [Figure 52] Figure for explaining Embodiment 9. [Figure 53] Figure for explaining Embodiment 9. [Figure 54] Figure for explaining Embodiment 9. [Figure 55] Figure for explaining Embodiment 9. [Figure 56] Figure for explaining Embodiment 11. [Figure 57] Figure for explaining Embodiment 11. [Figure 58] Figure for explaining Embodiment 11. [Figure 59] Figure for explaining Embodiment 11. [Figure 60] Figure for explaining Embodiment 11. [Figure 61] Figure for explaining Embodiment 12. [Figure 62] Figure for explaining Embodiment 12. [Figure 63] Figure for explaining Embodiment 13. [Figure 64] Figure for explaining Embodiment 12. [Figure 65] Figure for explaining Embodiment 10. [Figure 66] [[ID=​​​​​​​​​​​​​​​​​​​​​​​Figure for explaining Embodiment 10. [Figure 75] Figure for explaining Embodiment 14. [Figure 76] Figure for explaining Embodiment 14. [Figure 77] Figure for explaining Embodiment 14. [Figure 78] Figure for explaining Embodiment 14. [Figure 79] Figure for explaining Embodiment 14. [Figure 80] Figure for explaining Embodiment 14. [Figure 81] Figure for explaining Embodiment 14. [Figure 82] Figure for explaining Embodiment 14. [Figure 83] Figure for explaining Embodiment 14. [Figure 84] Figure for explaining Embodiment 14. [Figure 85] Figure for explaining Embodiment 15. [Figure 86] Figure for explaining Embodiment 17. [Figure 87] Figure for explaining Embodiment 18. [Figure 88] Figure for explaining Embodiment 18. [Figure 89] Figure for explaining Embodiment 18. [Figure 90] Figure for explaining Embodiment 19. [Figure 91] Figure for explaining Embodiment 20. [Figure 92] Figure for explaining Embodiment 1. [Figure 93] Figure for explaining Embodiment 22. [Figure 94] Figure for explaining Embodiment 23. [Figure 95] Figure for explaining Embodiment 23. [Figure 96] Figure for explaining Embodiment 23. [Figure 97] Figure for explaining Embodiment 23. [Figure 98] Figure for explaining Embodiment 23. [Figure 99]A diagram illustrating Embodiment 23. [Figure 100] A diagram illustrating Embodiment 14. [Figure 101] A diagram illustrating Embodiment 14. [Figure 102] A diagram illustrating Embodiment 17. [Figure 103] A diagram illustrating Embodiment 21. [Figure 104] A diagram illustrating Embodiment 16. [Figure 105] A diagram illustrating Embodiment 16. [Modes for carrying out the invention]

[0082] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to many. It is possible to carry out the invention in different forms, without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. This embodiment is not to be interpreted as being limited to its contents.

[0083] (Embodiment 1) This embodiment describes the basic configuration of the shift register of the display device of the present invention with reference to the drawings. Let me explain. Figure 1 shows one of the multiple flip-flops in a shift register. This shows a flip-flop (for example, the first stage). The flip-flop shown in Figure 1 is the first Transistor 1 101, transistor 2 102, transistor 3 103 and It has 4 transistors 104. The flip-flop has the first wiring 111, the second Wiring 112, third wiring 113, fourth wiring 114, fifth wiring 115 and sixth wiring It is connected to 116. In this embodiment, the first transistor 101, the second transistor Transistor 102, the third transistor 103, and the fourth transistor 104 are N-channel Assuming a type 1 transistor, the voltage between its gate and source (Vgs) is the threshold voltage (Vth When it exceeds ), it shall be considered to be in a conductive state. Note that the first wiring 111 and the second wiring 112 may be called the first power line and the second power line, respectively. Also, the third wiring 11 Wirings 3 and 4 114 may also be called the first signal line and the second signal line, respectively.

[0084] The first terminal (either the source terminal or the drain terminal) of the first transistor 101 is the first distribution It is connected to line 111, and the second terminal (the other of the source terminal and drain terminal) is the second transient It is connected to the gate terminal of sta 102, and the gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the second wiring 112, and the second terminal is connected to the second It is connected to the gate terminal of transistor 102, and the gate terminal is connected to the fourth wire 114. The first terminal of the second transistor 102 is connected to the sixth wiring 116, and the second terminal It is connected to the third wiring 113. The first terminal of the fourth transistor 104 is connected to the sixth wiring The second terminal is connected to wire 116, the second terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring It is connected to 114. Note that the second terminal of the first transistor 101 and the second transistor The connection point between the gate terminal of transistor 102 and the first terminal of the third transistor 103 is no Let's call it D121.

[0085] Furthermore, the second terminal of the third transistor 103 and the second terminal of the fourth transistor 104 are This is not limited to being connected to the second wiring 112, but also applies when connected to separate wiring. Good. Also, the gate terminal of the third transistor 103 and the gate of the fourth transistor 104 The terminal is not limited to being connected to the fourth wire 114, but may be connected to a separate wire. It's okay to be there.

[0086] Next, regarding the operation of the flip-flop shown in Figure 1, see the timing chart and Figure 2. Please refer to section 3 for further explanation. Note that in Figure 2, the set period, selection period, and non-selection period are as follows: I will explain this. Note that the non-selection period is the first non-selection period, the second non-selection period and the third non-selection period. The period is divided into selection periods, and the first non-selection period, the second non-selection period, and the third non-selection period are repeated in sequence. It's happening again.

[0087] Furthermore, the first wiring 111 is supplied with a potential of V1, and the second wiring 112 is supplied with a potential of V2. This is the case, provided that V1 > V2.

[0088] However, it is not limited to the first wiring 111 being supplied with the potential of V1, and other potentials may also be supplied. It may be supplied, or a digital or analog signal may be input. The second wiring 112 is not necessarily supplied with the potential of V2, but may be supplied with other potentials. It may be a digital signal or an analog signal.

[0089] Furthermore, signals are input to the third wiring 113, the fourth wiring 114, and the fifth wiring 115. The signal input to the third wiring 113 is the first clock signal, and the fourth wiring 11 The signal input to 4 is the second clock signal, and the signal input to the fifth wiring 115 is This is the start signal. Also, the third wiring 113, the fourth wiring 114, and the fifth wiring 115 The input signal is such that the potential of the H signal is V1 (hereinafter also called the H level), and the potential of the L signal is This is a V2 (hereinafter also referred to as L level) digital signal.

[0090] However, it is not limited to the third wiring 113 being input to the first clock signal, and other A signal may be input, or a constant potential or current may be input. Also, the fourth The wiring 114 is not necessarily limited to receiving a second clock signal; other signals may also be input. It may be done, or a certain potential or current may be input. Also, the fifth wiring 115 It is not limited to the input of a start signal; other signals may be input, A constant potential or current may be input.

[0091] Furthermore, the H signal input to the third wiring 113, the fourth wiring 114, and the fifth wiring 115 The potential of the signal is not limited to V1 and the potential of the L signal is not limited to V2; the potential of the H signal is not limited to the potential of the L signal. If the potential is high, then those potentials are not particularly limited.

[0092] Furthermore, a signal is output from the sixth wiring 116. Signal output from the sixth wiring 116 This is the output signal of the flip-flop, and also the start signal for the next stage flip-flop. Yes. Also, the signal output from the sixth wire 116 is the fifth flip-flop of the next stage. It is input to wiring 115. Also, the signal output from the sixth wiring 116 is the H signal. The voltage at position V1 (hereinafter also referred to as the H level) is the potential of the L signal, and the voltage at position V2 (hereinafter also referred to as the L level). It is a digital signal.

[0093] In Figure 2, signal 213 is a signal input to the third wiring 113, and signal 214 is the Signal 4 is input to wiring 114, and signal 215 is input to wiring 5 115. This is the signal, and signal 216 is the signal output from the sixth wiring 116. Also, potential 221 This is the potential at node 121 in Figure 1.

[0094] First, during period A in Figure 2 and the set period shown in Figure 3(A), signal 213 is at the L level. Signal 214 becomes L level and signal 215 becomes H level. Therefore, the third traffic Transistor 103 and the fourth transistor 104 are turned off, and the first transistor 101 It turns on. At this time, the second terminal of the first transistor 101 becomes the source terminal, and The potential of line 121 (potential 221) is from the potential of the fifth wiring 115 to the first transistor 10 Since it is the value obtained by subtracting the threshold voltage of 1 (Vth101), it becomes V1-Vth101. Therefore, the second transistor 102 turns on, and the potential of the sixth wire 116 becomes the potential of the third wire Since it becomes equal to the potential of 113, it becomes V2. Thus, during the set period, the flip-flow The top circuit keeps the second transistor 102 turned on and outputs an L level signal from the sixth wire 116. do.

[0095] During period B in Figure 2 and the selection period shown in Figure 3(B), signal 213 becomes H level, and signal 2 Signal 14 remains at a low level, and signal 215 is at a low level. Therefore, the third transistor Transistor 103 and the fourth transistor 104 remain off, and the first transistor 1 01 is turned off. At this time, the second terminal of the second transistor 102 becomes the source terminal. Then, the potential of the sixth wire 116 begins to rise. The potential of node 121 (potential 221) is, Since D121 is in a floating state (hereinafter also referred to as the floating state), the second T The sixth wiring is formed by capacitive coupling of the parasitic capacitance between the gate terminal and the second terminal of the transistor 102. It rises simultaneously with the potential of 116 (also called bootstrap action). Therefore, the second traction The voltage Vgs between the gate and source of inverter 102 is Vth102 + α (Vth102: the second The threshold voltage of transistor 102 (α: any positive number) is set to the sixth wire 116. The potential becomes H level (V1). Thus, during the selection period, the flip-flop is no By setting the potential of D121 to V1 + Vth102 + α, the H level is set to the 6th wiring 1 Output can be generated from 16.

[0096] During period C in Figure 2 and the first non-selective period shown in Figure 3(C), signal 213 becomes L level. Signal 214 is at an H level, while signal 215 remains at an L level. Therefore, the third Transistor 103 and the fourth transistor 104 are turned on, and the first transistor 101 remains off. Nodes 121 and 6th wiring 116 are connected to the third trap, respectively. The potential of the second wiring 112 is supplied via transistor 103 and the fourth transistor 104. Therefore, it becomes L level.

[0097] During period D in Figure 2 and the second non-selection period shown in Figure 3(D), signal 213 remains at the L level. Therefore, signal 214 becomes L level, and signal 215 remains L level. Then, the third transistor 103 and the fourth transistor 104 turn off, and the first transistor Zistor 101 remains off. Therefore, node 121 and wiring 116 of the 6th node are L Maintain the level.

[0098] During period E in Figure 2 and the third non-selective period shown in Figure 3(E), signal 213 reaches the H level. Signal 214 remains at a low level, and signal 215 remains at a low level. Therefore , the first transistor 101, the third transistor 103 and the fourth transistor 104 It remains off. Therefore, the wiring 116 of node 121 and 6 remains at the L level. do.

[0099] From the above, the flip-flop in Figure 1 is composed of the third transistor 103 and the fourth transistor Since transistor 104 is turned on only during the first non-selective period, the third transistor 103 and Furthermore, the characteristic degradation (threshold voltage shift) of the fourth transistor 104 can be suppressed. The flip-flop in Figure 1 consists of the first transistor 101 and the second transistor Since Ta102 is turned on only during the set period, and only during the set period and the selected period, The degradation of the characteristics of transistor 101 and transistor 202 can also be suppressed. ru.

[0100] Furthermore, in the flip-flop shown in Figure 1, during the non-selection period, no V2 is supplied to wiring 121 and 6116, which suppresses malfunction of the flip-flop. This is possible because, during the non-selection period, at regular intervals (the first non-selection period) V2 is supplied to the wiring 116 of nodes 121 and 6, and the wiring 116 of nodes 121 and 6 This is because the potential of line 116 can be stably maintained at V2.

[0101] Note that the flip-flop in Figure 1 consists of the first transistor 101 and the second transistor 10 2. The third transistor 103 and the fourth transistor 104 are all N-channel type transistors. It is characterized by being composed of a zista. Therefore, the flip-flop in Figure 1 is Amorphous silicon can be used as the semiconductor layer of the transistor, thus reducing manufacturing costs. This allows for simplification of the process, leading to reduced manufacturing costs and improved yield. Furthermore, it will also be possible to manufacture semiconductor devices such as large display panels. Even if polysilicon or single-crystal silicon is used as the semiconductor layer of the zista, the manufacturing process can be simplified. It can be measured.

[0102] Furthermore, the flip-flop in Figure 1 exhibits characteristic degradation (threshold voltage) as a semiconductor layer of the transistor. Even when using Amophas silicon, which exhibits a significant pressure shift, the transistor characteristics degrade. Because this can be suppressed, it is possible to manufacture semiconductor devices such as display panels with a long lifespan. Cut.

[0103] Here, the first transistor 101, the second transistor 102, and the third transistor 1 The functions of transistors 03 and 4, 104, will be explained. First transistor 101 It has a function to select the timing for supplying the potential to the first wiring 111, and input transistor It functions as a diode. The second transistor 102 controls the potential of the third wiring 113 to the sixth Select the timing to supply power to wiring 116 and bootstrap the potential of node 121. It has the function of increasing the voltage and functions as a bootstrap transistor. Transistor 103 supplies the potential of the second wiring 112 to node 121 at the right time. It has the function of selecting and functions as a switching transistor. The fourth transistor 104 has the function of supplying the potential of the second wiring 112 to the sixth wiring 116, and switches It functions as a sintering transistor.

[0104] Note that if the device performs the same operation as in Figure 1, the arrangement and number of transistors are not limited to those in Figure 1. It is not determined. As can be seen from Figure 3, which explains the operation of the flip-flop in Figure 1, in this implementation In terms of form, there is a set period, a selection period, a first non-selection period, a second non-selection period, and a third non-selection period. During the selection period, it is sufficient if there is continuity as shown by the solid lines in Figures 3(A) to (E). Therefore, if a configuration can be made to operate by arranging transistors etc. in such a way that satisfies this condition, then Energy converters, other elements (resistors, capacitive elements, etc.), diodes, switches, various theories You may also add new circuits or other components.

[0105] For example, as shown in Figure 4, the gate terminal of the second transistor 102 shown in Figure 1 and the second A capacitive element 401 may be placed between the terminals. By placing the capacitive element 401 This allows for more stable bootstrap operation during the selection period. Also, the second Because the parasitic capacitance between the gate terminal and the second terminal of the transistor 102 can be reduced, each transistor The inverter can be switched at high speed. Furthermore, the capacitive element 401 has an insulating layer and Alternatively, a gate insulating film may be used, and the gate electrode layer and wiring layer may be used as conductive layers. A semiconductor using a gate insulating film as a layer and a gate electrode layer and impurities as conductive layers. Layers may be used, or an interlayer film (insulating film) may be used as the insulating layer and a wiring layer and a conductive layer may be used. A light electrode layer may also be used. Note that parts common to the configuration in Figure 1 are indicated using the same reference numerals. I will omit the explanation.

[0106] The flip-flop in Figure 5 can perform the same operation as in Figure 1. As shown in Figure 1, the first transistor 101 may be connected in a diode configuration. The first transistor 101 is connected to a diode, so the first wiring 111 is not This eliminates the need for one wire and one power supply (V1). Note that this is the same as the configuration shown in Figure 1. Where lines are connected, a common symbol is used, and its explanation is omitted.

[0107] Next, Figure 6 shows the shift register having the flip-flop of the embodiment described above. See the explanation below.

[0108] The shift register consists of the first wiring 611, the second wiring 612, the third wiring 613, and the fourth wiring Wire 614, fifth wire 615, sixth wire 616, wires 622_1 to 622_n and n pieces It has (n stages) of flip-flops 601_1~601_n. And the 1+3Nth stage ( Flip-flop 601 (N: 0 or a positive integer) has first wire 611 and second wire 6 12. Connected to the third wiring 613 and the fourth wiring 614. 2+3N stage flip The flop 601 is connected to the first wiring 611, the second wiring 612, the fourth wiring 614 and the fifth wiring It is connected to wiring 615. The 3+3N stage flip-flop 601 is connected to the first wiring 61 1. It is connected to the second wiring 612, the fifth wiring 615, and the third wiring 613. For example, the i-th flip-flop 601_i (flip-flop 601_1~601_ One of n) Flip-flop 601_2 ~ Flip-flop 601_ n-1 represents the i-1 stage flip-flop 601_i-1 and the i+1 stage flip-flop It is connected to flip-flop 601_i+1, and the i-th flip-flop 601_i and the i+1-th flip-flop The connection point with the lip-flop 601_i+1 is wire 622_i (wires 622_1~622 It is connected to one of the _n. Note that the first stage flip-flop 601_1 It is connected to the sixth wire 616 and the second stage flip-flop 601_2, and the first stage flip The connection point between the flip-flop 601_1 and the second flip-flop 601_2 is wire 622. It is connected to _1. Note that the nth flip-flop 601_n is connected to the n-1th flip-flop. It is connected to the top flop 601_n-1 and wiring 622_n.

[0109] Note that in the 1+3N stage flip-flop 601, the first wiring 611 and the second wiring 61 2. The third wiring 613 and the fourth wiring 614 are the first wiring 111 and the second wiring 111 in Figure 1, respectively. It is connected to wiring 112, the third wiring 113, and the fourth wiring 114. 2+3N stage In the lip-flop 601, the first wire 611, the second wire 612, and the fourth wire 114, The fifth wiring 615 corresponds to the first wiring 111, the second wiring 112, and the third wiring in Figure 1, respectively. 113 is connected to the fourth wire 114. The 3+3N stage flip-flop 601 The first wiring 611, the second wiring 612, the fifth wiring 615, and the third wiring 613 are These are the first wiring 111, the second wiring 112, the third wiring 113, and the fourth wiring 61 in Figure 1. It is connected to 4. Also, for example, among the i-th stage flip-flop 601_i, Fifth wiring 115 shown in Figure 1 for flip-flops 601_2 to 601_n-1 And the sixth wiring 116 is connected to the i-1 stage flip-flop 601_i-1, respectively, as shown in Figure 1. The sixth wiring 116, the i+1 stage flip-flop 601_i+1 shown in Figure 1 Wiring 5 is connected to 115. Note that the first stage flip-flop 601_1 is shown in Figure 1. The fifth wiring 115 and the sixth wiring 116 shown correspond to the sixth wiring 616, two-stage wiring, in Figure 6, respectively. It is connected to the fifth wire 115 shown in Figure 1 of the flip-flop 601_2. , the fifth wiring 115 and the sixth wiring 1 of the nth stage flip-flop 601_n shown in Figure 1 16 is the sixth wiring shown in Figure 1 for the (n-1) stage flip-flop 601_n-1. 116 is connected to wiring 622_n in Figure 6.

[0110] Next, Figure 92 shows one configuration of the top view of the shift register shown in Figure 6. The shift register is the shift register using the flip-flop shown in Figure 1, and n The flip-flop 601_n in the first stage and the flip-flop 601_n+1 in the (n+1)th stage As shown, the flip-flop in the shift register in Figure 92 has the first transistor 10 1. Second transistor 102, third transistor 103 and fourth transistor 10 4 is positioned. And each of the flip-flops that the shift register in Figure 92 has This includes the first wiring 611, the second wiring 612, the third wiring 613, the fourth wiring 614 and The fifth wiring 615 is connected. Note that the first transistor 101 and the second transistor The stator 102, the third transistor 103, and the fourth transistor 104 are of the inverse stagger type. This section describes a transistor structure, specifically the channel etch type. However, the first... transistor 101, second transistor 102, third transistor 103 and fourth transistor The transistor 104 may also be channel-protected. Also, the first transistor 101, the second The transistor 102, the third transistor 103, and the fourth transistor 104 are It can also be used as a top-gate transistor.

[0111] Furthermore, the layout diagram of the shift register shown in Figure 92 shows the first conductive film 9201, semiconductor layer It is composed of 9202, contact 9203, and a second conductive film 9204. The first conductive film 9201 functions as a gate electrode. The semiconductor layer 9202 does not contain impurities. It is an intrinsic amorphous semiconductor film. Contact 9203 is the first conductive film 9201 and the second It functions to electrically connect to the conductive film 9204.

[0112] The shift register in Figure 92 sets the wiring width of the first wiring 611 to the wiring width of the third wiring 613, and the The wiring width of the fourth wiring 614 and the fifth wiring 615 can be made smaller than these. Because the current flowing through the first wiring 611 is also flowing through the third wiring 613, the fourth wiring 614 and Because it is smaller than wiring 615 of 5, even if the wiring width of the first wiring 611 is reduced, the shift This is because it has little effect on the operation of the zistor. Similarly, the shift register in Figure 92 is the second The wiring width of wiring 612 is the wiring width of the third wiring 613, the wiring width of the fourth wiring 614 and the fifth The wiring width of wiring 615 can be made smaller. However, the current flowing through the second wiring 612 Since the current is greater than the current flowing through the first wiring 611, the wiring width of the second wiring 612 is It is desirable that the wiring width is greater than that of wiring 611 of 1. Therefore, the shift register in Figure 92 The STA allows for a smaller pitch in the flip-flops of one stage. Also, the shift register in Figure 92 The st allows for efficient arrangement of each transistor. Also, the shift register in Figure 92 allows for efficient arrangement of each transistor. The channel width of the transistor can be increased.

[0113] Furthermore, the shift register in Figure 92 increases the channel width of the second transistor 102. This makes the bootstrapping process easier. Because the second ti Because the channel width of transistor 102 is large, the gate terminal of the second transistor 102 and the This is because the parasitic capacitance between the two terminals becomes large. Also, the shift register in Figure 92 is By increasing the channel width of transistor 102, a higher driving capability can be obtained. Yes, because the channel width of the second transistor 102 is large, the second transistor This is because the current supply capacity of sta 102 will increase. Furthermore, as already mentioned, see Figure 92. The shift register reduces the wiring width of the first wiring 611 and the second wiring 612, and each The area where the transistor can be placed can be increased. In that case, the shift register in Figure 92 is the second By prioritizing a larger channel width for transistor 102, higher driving capability can be obtained. This is possible. Therefore, the channel width of the second transistor is equal to the channel width of the first transistor 1. Channel width of 01, channel width of the third transistor 103, fourth transistor 104 It is desirable to make it larger than the channel width.

[0114] Furthermore, the shift register in Figure 92 has a U-shaped channel for the second transistor 102. This allows the channel width of the second transistor 102 to be increased.

[0115] Furthermore, the features of the layout diagram shown in Figure 92 can be applied to other shift registers as well. Cut.

[0116] Next, regarding the operation of the shift register shown in Figure 6, refer to the timing chart in Figure 7. I will explain.

[0117] Furthermore, the first wiring 611 is supplied with a potential of V1, and the second wiring 612 is supplied with a potential of V2. This is the case, provided that V1 > V2.

[0118] However, it is not limited to the first wiring 611 being supplied with the potential of V1; other potentials may also be supplied. It may be supplied, or a digital or analog signal may be input. The second wiring 612 is not necessarily supplied with the potential of V2, but may be supplied with other potentials. It may be a digital signal or an analog signal.

[0119] Furthermore, the third wiring 613, the fourth wiring 614, the fifth wiring 615, and the sixth wiring 616 are A signal is being input. Input to the third wire 613, the fourth wire 614, and the fifth wire 615. The signal being transmitted is a three-phase clock signal with a phase difference of 120 degrees. The sixth wiring 616 The input signal is a start signal. Also, the third wiring 613, the fourth wiring 614, and The signals input to wiring 5 615 and wiring 616 6 are such that the potential of the H signal is V1 and the L signal It is a digital signal with a potential of V2.

[0120] However, the third wiring 613, the fourth wiring 614, and the fifth wiring 615 each have a phase It is not limited to the input being a three-phase clock signal shifted by 120 degrees each; other signals may also be input. It may be subjected to force, or a certain potential or current may be input. Also, the sixth wiring 61 It is not limited to the input of a start signal to 6; other signals may be input as well. A constant potential or current may be input.

[0121] Furthermore, the third wiring 613, the fourth wiring 614, the fifth wiring 615, and the sixth wiring 616 The potential of the H signal and the potential of the L signal are not limited to V1 and V2, respectively. If the potential is higher than the potential of the L signal, then that potential is not particularly limited.

[0122] Furthermore, a signal is output from wiring 622. For example, wiring 622_i (where i is any positive number) The signal output from ) is the output signal of the i-th stage flip-flop 601_i, and i+ This is also the input signal for the first stage flip-flop 601_i+1.

[0123] In Figure 7, signal 716 indicates the signal input to the sixth wiring 616. Signal 722_1, signal 722_i, signal 722_i+1, and signal 722_n each have one stage. Signals output from wiring 622 at the i-th, i-th, i+1-th, and n-th stages (potential of wiring 622) This indicates that.

[0124] As shown in Figure 7, for example, when the i-th flip-flop 601_i reaches the selection period, The H signal (722_i) is output to line 622_i. At this time, the i+1 stage flip-flop The top 601_i+1 becomes a set period and outputs an L signal to wiring 622_i+1. The i-th stage flip-flop 601_i enters its first non-selection period and sends an L signal to the wiring 622_i. The number is output. At this time, the i+1 stage flip-flop 601_i+1 becomes the selected period. The H signal is output to the rewired 622_i+1. Then, the i-th stage flip-flop 601_ i becomes the second non-selective period, and wiring 622_i remains in a floating state while maintaining an L level. At this time, the i+1 stage flip-flop 601_i+1 becomes the first non-selection period and is wired. The low signal is output to 622_i+1. Then, the i-th stage flip-flop 601_i is... During the non-selection period (3), wiring 622_i remains floating while maintaining an L level. At this point, the i+1 stage flip-flop 601_i+1 becomes the second non-selection period and is wired. 622_i+1 remains in a floating state while maintaining the L level. After that, the i-th flip occurs. Flop 601_i has a first non-selection period, a second non-selection period, and a third non-selection period until the next set period. The non-selection period is repeated sequentially. Similarly, the i+1-th flip-flop 601_i+1 is Until the next set period (the selection period for the i-th flip-flop 601_i), the third non-selection The process repeats in sequence: an elective period, a first non-elective period, and a second non-elective period.

[0125] From the above, the shift register in Figure 6 can use a three-phase clock signal. Therefore, the number of times the device starts up or falls down can be reduced, resulting in power savings. Furthermore, the shift register of this embodiment has each clock signal line (third wiring 613, fourth wiring The number of stages of the flip-flop 601 connected to line 614 (5th wiring 615) is single-phase This reduces the load on each clock signal line to 2 / 3 of the load when using a clock signal. It is possible.

[0126] Note that the shift register in Figure 6 buffers the output signals of each stage's flip-flop 601. Alternatively, the output may be routed to the wiring 622 of each stage, as shown in Figure 8. The shift register of 8 has flip-flops 601 in each stage that are connected via buffers 801 Since it is connected to the wiring 622 of each stage, a wide margin can be obtained during operation. This is because a large load is connected to wiring 622, causing delays and waveform changes in the signal from wiring 622. This is because even if some saturation occurs, it does not affect the operation of the shift register. Note that buffer 80 1 includes inverters, logic circuits such as NAND and NOR, operational amplifiers, and combinations of these. A combined circuit can be used.

[0127] Next, with reference to Figure 9, the display device having the shift register of the above-described embodiment... I will explain.

[0128] The display device has a signal line drive circuit 901, a scan line drive circuit 902, and a pixel section 903, The base unit 903 consists of multiple signal lines S1 that extend in a column direction from the signal line drive circuit 901. ~Sm, multiple scan lines G1~Gn arranged extending in the row direction from the scan line drive circuit 902 and multiple units arranged in a matrix corresponding to signal lines S1 to Sm and scan lines G1 to Gn It has pixels 904. And each pixel 904 is one of the signal lines Sj (signal lines S1 to Sm). It is connected to scan line Gi (any one of scan lines G1 to Gn).

[0129] Note that scan lines G1 to Gn correspond to wiring 622_1 to 622_n in Figures 6 and 8.

[0130] The wiring and electrodes are made of aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. Butene (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg) Scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silica Si (silicon), Phosphorus (P), Boron (B), Arsenic (As), Gallium (Ga), Indium One or more elements selected from (In), tin (Sn), and oxygen (O), or a group thereof. Compounds and alloy materials comprising one or more elements selected from (for example, indium tin) Indium tin with added oxide (ITO), indium zinc oxide (IZO), and silicon oxide. Oxides (ITSO), zinc oxide (ZnO), aluminum neodymium (Al-Nd), magnesium It contains substances such as um-silver (Mg-Ag), or combinations of these compounds. They are formed by combining them with silicon compounds (silicides) (for example, aluminum silicides). (e.g., lycon, molybdenum silicon, nickel silicide, etc.) and compounds of these with nitrogen (e.g.) For example, it is formed by having titanium nitride, tantalum nitride, molybdenum nitride, etc. Si contains many n-type impurities (such as phosphorus) and p-type impurities (such as boron). It is also possible that the inclusion of these impurities improves conductivity, and that it is similar to that of ordinary conductors. Because it behaves in a certain way, it becomes easier to use as wiring or electrodes. Note that silicon is a single crystal. It's fine to use polycrystalline silicon or amorphous silicon. By using single-crystal silicon or polycrystalline silicon, the resistance can be reduced. Furthermore, by using amorphous silicon, it can be manufactured using a simple manufacturing process. Aluminum and silver have high conductivity, which can reduce signal delay, and also... Because it is easy to cut, it is easy to pattern and perform fine machining. Because of its high conductivity, it can reduce signal delay. Note that molybdenum is ITO Oxide semiconductors such as IZO, and silicon, can also cause problems such as material defects when they come into contact with silicon. Because it can be manufactured without any hassle, is easy to pattern and etch, and has high heat resistance. , desirable. Furthermore, titanium comes into contact with oxide semiconductors such as ITO and IZO, and silicon. Even if problems such as material defects occur during manufacturing, and because of its high heat resistance, it is desirable. Furthermore, tungsten is desirable because of its high heat resistance. Neodymium is also heat resistant. Because it is highly heat-resistant, it is desirable. In particular, when used as an alloy of neodymium and aluminum, the heat resistance is improved. Furthermore, aluminum is less likely to cause hillocks, which is desirable. Note that silicon is... It is desirable because it can be formed simultaneously with the semiconductor layer of the transistor and has high heat resistance. Oh, indium tin oxide (ITO), indium zinc oxide (IZO), and silicon oxide are added. Indium tin oxide (ITSO), zinc oxide (ZnO), and silicon (Si) are light-transmitting. Because it possesses light-transmitting properties, it can be used in parts that transmit light, which is desirable. For example, it can be used as a pixel electrode or a common electrode.

[0131] These may form wiring and electrodes in a single layer, or they may have a multilayer structure. By forming it with a single-layer structure, the manufacturing process can be simplified and the process time can be reduced. This allows for cost reduction. Furthermore, by using a multi-layer structure, each material... By leveraging the advantages of one material and mitigating the disadvantages of another material, This allows for the formation of high-performance wiring and electrodes. For example, low-resistance materials (aluminium) By incorporating materials such as aluminum into the multilayer structure, the resistance of the wiring can be reduced. It is possible. Also, if you include materials with high heat resistance, for example, even if the heat resistance is weak, there is another advantage. By creating a laminated structure in which a material containing a net is sandwiched between materials with high heat resistance, wiring and The overall heat resistance of the electrode can be increased. For example, a layer containing aluminum can be added. A laminated structure in which layers containing ribdenum and titanium are sandwiched together is desirable. If there are parts that come into direct contact with the wiring or electrodes of the material, they may negatively affect each other. There are cases like this. For example, one material enters another material and changes its properties. It may fail to fulfill its original purpose, or problems may arise during manufacturing, preventing normal production. This can happen. In such cases, one layer may be sandwiched or covered by another layer. This can solve the problem. For example, indium tin oxide (ITO) and A When contacting luminium, it is advisable to sandwich titanium or molybdenum in between. Also, if you want to bring silicon and aluminum into contact, you can insert titanium or molybdenum in between. That would be preferable.

[0132] Furthermore, the wiring and electrodes described above can also be applied to other display devices and shift registers. It is possible.

[0133] The signal line drive circuit 901 provides the signal lines S1 to Sm with a potential or current corresponding to the video signal. A current is input. Furthermore, the signal line drive circuit 901 is formed on the same substrate as the pixel unit 903. It is not necessary, and it may be formed on a single-crystal substrate such as an IC, or a part of it may be the pixel portion 903. They may be formed on the same substrate, with the remaining portion formed on a single-crystal substrate such as an IC.

[0134] The scan line drive circuit 902 inputs signals to scan lines G1 to Gn and controls scan lines G1 to Gn Select the lines in order from the first row (hereinafter also referred to as scanning). Then, connect to the selected scan lines. Multiple pixels 904 that are selected are also selected simultaneously. The period is called the 1-gate selection period, and the period during which a scan line is not selected is called the deselection period. Furthermore, the scan line drive circuit 902 applies the shift register shown in Figure 6 or Figure 8. This is possible. Furthermore, the scanning line driving circuit 902 is formed on the same substrate as the pixel unit 903. It is characterized by the following:

[0135] Furthermore, if selected, pixel 904 receives signals from the signal line drive circuit 901 via the signal line. A potential or current corresponding to the video signal is input. However, if not selected, No potential or current corresponding to the video signal is input.

[0136] Next, the operation of the display device shown in Figure 9 will be explained with reference to the timing chart in Figure 10. To clarify, in Figure 10, one frame corresponds to the period during which one screen's worth of image is displayed. It indicates a gap. Note that there is no specific limit to the duration of one frame, but if the viewer of the image experiences flickering (flickering) It is preferable to set the shutter speed to 1 / 60th of a second or less to avoid the feeling of a 'whirrer'.

[0137] Note that in the timing chart of Figure 10, the scan line G1 is in the first row, and the scan lines Gi and i are in the i-th row. This indicates the timing at which scan line Gi+1 on the +1st row and scan line Gn on the nth row are selected. They are doing it.

[0138] In Figure 10, for example, the i-th row scan line Gi is selected, and multiple scan lines connected to scan line Gi are selected. A number of pixels 904 are selected. Then, multiple pixels 904 connected to scan line Gi are Each of these has a video signal written to it, and the brightness or transmittance of each display element is video The value will be determined according to the signal. Subsequently, when the scan line Gi of the i-th row is deselected, the scan line of the i+1-th row Scan line Gi+1 is selected, and multiple pixels 904 connected to scan line Gi+1 are selected. And each of the multiple pixels 904 connected to scan line Gi+1 receives a video signal. The data is written, and the brightness or transmittance of each display element becomes a value corresponding to the video signal. Furthermore, each pixel 904 retains the written video signal even when it is deselected. Each display element maintains a brightness or transmittance corresponding to the video signal.

[0139] From the above, each of the scan lines G1 to Gn corresponds to one gate selection period within one frame period. Selected during the 1-gate selection period, and not selected outside of the 1-gate selection period. The length of the interval is roughly equal to the length of one frame divided by n, so Most of the time in between is a non-selection period. In other words, the scan line drive circuit 902 is shown in Figure 6 or When the shift register shown in Figure 8 is applied, the flip-flops shown in Figure 6 or Figure 8 are used. Each of 601_1 to 601_i is the first non-selected for most of the duration of a single frame. The period, the second non-selection period, and the third non-selection period are repeated in sequence. Therefore, scanning The line drive circuit 902 is the flip-flop 601_1~601_i shown in Figures 6 and 8. Because it can suppress the degradation of the transistors it possesses, its lifespan can be extended. Furthermore, the display in Figure 9 shows that the long-life scan line drive circuit 902 is integrally formed with the pixel section 903. The lifespan of the device can also be extended.

[0140] Furthermore, as shown in Figure 9, if it is possible to select a pixel and write a video signal to that pixel, then the drive will work. The number and arrangement of circuits are not limited to those shown in Figure 9.

[0141] For example, as shown in Figure 11, scan lines G1 to Gn are driven by the first scan line drive circuit 1101 The first scan line drive circuit may also be used for scanning. The path 1101 and the second scan line drive circuit 1102 are connected to the scan line drive circuit 902 shown in Figure 9. The configuration is similar, and scan lines G1 to Gn are scanned at the same time. The scan line Gn is driven by the first scan line drive circuit 1101 and the second scan line drive circuit 1102. By scanning, the delay and distortion of the signals output to each of the scan lines G1 to Gn This reduces the scanning speed of scan lines G1 to Gn. In other words, the display device in Figure 11 is As the panel size increases, the wiring resistance and parasitic capacitance of scan lines G1 to Gn also increase. However, the delay and distortion of the signals output to each of the scan lines G1 to Gn are reduced. Therefore, it is possible to make it larger. Furthermore, the display device in Figure 11 has a large panel size. The size increases, or the panel becomes higher resolution and the number of pixels increases, scanning line G1~ Even if it is necessary to scan line Gn at high speed, scan lines G1 to Gn should be scanned at high speed. This makes it possible to increase the size and resolution. Furthermore, the display device shown in Figure 11 This is due to a defect in one of the first scan line drive circuit 1101 and the second scan line drive circuit 1102. Even if this occurs, the other scan lines G1 to Gn can still be scanned, thus providing redundancy. Yes, it is possible. Note that parts common to the configuration in Figure 9 are represented by the same numerals, and their explanations are omitted. Furthermore, the timing chart in Figure 10 can be used for the display device in Figure 11, similar to Figure 9. can.

[0142] In the display device shown in Figure 12, as in Figure 9, pixels are selected and the video signal is written to the pixels. It can be loaded. As shown in Figure 12, the first scan line drive circuit 1201 and the second drive The scan line drive circuit 1202 may scan scan lines G1 to Gn one line at a time. The first scan line drive circuit 1201 and the second scan line drive circuit 1202 are shown in Figure 9. The configuration is similar to the scan line drive circuit 902, but the drive timing is different. First scan line drive Circuit 1201 scans the odd-numbered scan lines, and the second scan line drive circuit 1202 scans the even-numbered lines. By scanning the scan lines, the first scan line drive circuit 1201 and the second scan line drive circuit The drive frequency of the path 1202 can be reduced, and the first scan line drive circuit 1201 and the second scan line The pitch of the flip-flop in the drive circuit 1202 is widened by one stage. In other words, Figure 12 The display device drives the first scan line drive circuit 1201 and the second scan line drive circuit 1202. Because the frequency can be reduced, power saving can be achieved. Furthermore, the display device in Figure 12 is the first The flip-flops in the first scan line drive circuit 1201 and the second scan line drive circuit 1202 Because the pitch is widened by the equivalent of one row, layout can be done efficiently, and the frame can be made smaller. Furthermore, the display device in Figure 12 includes a first scan line drive circuit 1201 and a second scan line drive By arranging circuit 1202 on the left and right sides, the frame can be made symmetrical. Note that the structure in Figure 9 Where there are commonalities with the term, the same symbols are used and their explanations are omitted. Note that the display device in Figure 12... For this, the timing chart in Figure 10 can be used, similar to Figure 9.

[0143] Furthermore, in the display device shown in Figure 44, pixels are selected as shown in Figure 9, and video signals are transmitted to the pixels. Numbers can be written. As shown in Figure 44, the first scan line drive circuit 4402 and The scan line drive circuit 4403 in 2 can scan scan lines G1 to Gn one line at a time. Also, pixel 904 is connected to the left and right signal lines for each row. For example, the multiplier in column j The number 904 pixels are in the i-th row, and are on signal line Sj (one of signal lines S1 to Sm+1). It is connected to (1), and in row i+1 it is connected to signal line Sj+1, and in row i-1 it is connected to signal line Sj +1 connection.

[0144] The operation of the display device shown in Figure 44 will be explained with reference to the timing chart in Figure 45. In Figure 45, the frame period corresponding to the period for displaying one screen's worth of image is defined as follows: To show. Note that there is no particular limit to the duration of one frame, but if the viewer experiences flickering (flickering) of the image... It is preferable to set the delay to 1 / 60th of a second or less so that the (-) sensation is not felt.

[0145] Note that in the timing chart of Figure 45, the scan line G1 is in the first row, and the scan line Gi is in the i-1 row. -1, the scan line Gi on the i-th row, the scan line Gi+1 on the i+1-th row, and the scan line Gn on the n-th row are... This indicates the timing of each selection. In the timing chart in Figure 45, one selection The period is divided into two selected periods: Ta and Tb.

[0146] Note that the display device in Figure 44 has a positive video signal in each signal line, one row at a time, during one frame period. By simply inputting the negative and negative video signals, dot inversion can be performed. The display device in Figure 44 reverses the polarity of the video signal input to each signal line every frame period. This enables frame inversion driving. Note that in the timing chart in Figure 45 This section describes the case where the display device performs dot inversion driving and frame inversion driving.

[0147] In Figure 45, for example, the selection period Ta of scan line Gi in row i is the same as the scan line Gi in row i-1. The selection period of -1 overlaps with the selection period of scan line Gi in row i, and the selection period Tb of scan line Gi in row i+1 overlaps with the selection period of line i+1. The selection period for line Gi+1 overlaps with the selection period Ta. The video signal input to pixel 904 in column j+1 is similar to the video signal input to pixel 9 in row i, column j. It is entered into 04. Also, in the selected period Tb, it is entered into pixel 904 at row i and column j. A signal similar to a video signal is input to pixel 904 in row i+1 and column j-1. During selection period Tb, the video signal input to pixel 904 is the original video signal, and selection During period Ta, the video signal input to pixel 904 is used for pre-charging pixel 904. This is a denominator signal. Therefore, each of the 904 pixels is input during the selection period Ta. The video signal is precharged by the video signal and the input video signal is maintained during the selected period Tb. To hold.

[0148] From the above, the display device in Figure 44 can write video signals to pixel 904 at high speed. Therefore, it is possible to easily achieve larger size and higher resolution. Furthermore, the display device shown in Figure 44 The reason is that each signal line receives a video signal of the same polarity during a single frame period, The signal lines require less charging and discharging, enabling lower power consumption. Furthermore, the display device shown in Figure 44 is a video display. The load on the IC for supplying the signal is significantly reduced, thus reducing the heat generation and power consumption of the IC. This can reduce the amount of noise. Furthermore, the display device in Figure 44 has a first scan line drive circuit 4402 This also allows the drive frequency of the second scan line drive circuit 4403 to be reduced by approximately half.

[0149] Note that the display devices in Figures 9, 11, 12, and 44 have different pixel configurations. Additional wiring may be added. For example, power lines kept at a constant potential, new scan lines and Capacitance lines and other elements may be added. Note that if new scan lines are added, see Figures 6 and 8. A scan line driving circuit that applies the shift register shown may be added.

[0150] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0151] (Embodiment 2) In this embodiment, a flip-flop with a different configuration from that of Embodiment 1 is shown in Figure 13. Regarding parts similar to those in Embodiment 1, a common reference numeral is used, and the same parts or similar components are indicated by the same reference numeral. Detailed explanations of the functional parts will be omitted.

[0152] The flip-flop shown in Figure 13 consists of a first transistor 101 and a second transistor 10 2. Third transistor 103, fourth transistor 104 and fifth transistor 13 It has 05. The flip-flop has the first wiring 111, the second wiring 112, and the third Wiring 113, the fourth wiring 114, the fifth wiring 115, the sixth wiring 116 and the seventh wiring It is connected to 1317. In this embodiment, the fifth transistor 1305 is N-type. A channel-type transistor is defined as such, and the voltage between its gate and source (Vgs) is the threshold voltage (V When it exceeds th), it shall be assumed to be in a conductive state. Note that the 7th wiring 1317 is the 3rd It could also be called a signal line.

[0153] The first terminal (either the source terminal or the drain terminal) of the first transistor 101 is the first distribution It is connected to line 111, and the second terminal (the other of the source terminal and drain terminal) is the second transient It is connected to the gate terminal of sta 102, and the gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the gate terminal of the second transistor 102. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal It is connected to the sixth wiring 116. The first terminal of the fourth transistor 104 is connected to the sixth wiring The second terminal is connected to wire 116, the second terminal is connected to the second wire 112, and the gate terminal is connected to wire 114 It is connected to the first terminal of the fifth transistor 1305, which is connected to the sixth wiring 116. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the seventh wiring 1317. It is being done.

[0154] Furthermore, the second terminal of the third transistor 103, the second terminal of the fourth transistor 104 and The second terminal of the fifth transistor 1305 is not necessarily connected to the second wiring 112. They may not be connected to separate wires. Also, the gate of the third transistor 103 The terminal and the gate terminal of the fourth transistor 104 are connected to the fourth wiring 114. This is not limited to, and they may be connected to separate wiring.

[0155] Next, regarding the operation of the flip-flop shown in Figure 13, see the timing chart in Figure 14. Refer to the explanation. Note that Figure 14 shows the flip-flop shown in Figure 13, and the flip-flop shown in Figure 1. This is a timing chart for when the game operates similarly to a flop. Note that the timing in Figure 2 is shown. Where there are commonalities with the chart, the same symbols are used and explanations are omitted.

[0156] Furthermore, a signal is input to the seventh wiring 1317. The signal is the third clock signal. Also, the signal input to the seventh wiring 1317 is H The potential of the signal is V1 (hereinafter also called the H level), and the potential of the L signal is V2 (hereinafter also called the L level). It is a digital signal (also known as a digital signal).

[0157] However, it is not necessarily the case that the third clock signal is input to the seventh wiring 1317. Other signals may be input, or a constant potential or current may be input.

[0158] In Figure 14, signal 1417 is the signal input to the seventh wiring 1317.

[0159] In the flip-flop shown in Figure 13, the fifth trap occurs during the set period and the second non-selection period. Transistor 1305 is turned on. Then, the sixth wire 116 is connected to the fifth transistor 13 The potential of the second wiring 112 is supplied via 05, thus maintaining the L level.

[0160] From the above, the flip-flop in Figure 13 has a first non-selection period, a second non-selection period, During the third non-selection period, in the first non-selection period and the second non-selection period, the sixth wiring Since V2 is supplied to 116, malfunctions of the flip-flop can be further suppressed. This is because, during the non-selection period, at regular intervals (the first non-selection period and the second non-selection period) ) is supplied to the sixth wiring 116, and the potential of the sixth wiring 116 is stabilized by V2 Because it can be maintained in that state.

[0161] Furthermore, the fifth transistor 1305 of the flip-flop in Figure 13 is used for the set period and Since it turns on only during the non-selective period of 2, it suppresses the degradation of the characteristics of the fifth transistor 1305. It is possible.

[0162] Note that the flip-flop in Figure 13 consists of the first transistor 101 and the second transistor 1 02, the third transistor 103, the fourth transistor 104 and the fifth transistor 1 The 305 is characterized by being composed entirely of N-channel transistors. The flip-flop in Figure 13 uses amorphous silicon as the semiconductor layer of the transistor. Because this can be used, the manufacturing process can be simplified, reducing manufacturing costs and production costs. This can improve retention. Furthermore, it can be used to manufacture semiconductor devices such as large display panels. It also becomes possible to use polysilicon or single-crystal silicon as the semiconductor layer of the transistor. Using cones can also simplify the manufacturing process.

[0163] Furthermore, the flip-flop in Figure 13 exhibits characteristic degradation (threshold) as a semiconductor layer of the transistor. Even when using Amophas silicon, which exhibits a significant voltage shift, the transistor characteristics are inferior. Because degradation can be suppressed, it is possible to manufacture semiconductor devices such as display panels with a long lifespan. can.

[0164] Here, we will explain the function of the fifth transistor 1305. 05 is a mechanism that selects the timing for supplying the potential of the second wiring 112 to the sixth wiring 116. It has the capability to function as a switching transistor.

[0165] If the device performs the same operation as shown in Figure 13, the arrangement and number of transistors should be the same as in Figure 13. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0166] For example, as shown in Figure 15, the gate terminal of the second transistor 102 shown in Figure 13 and A capacitive element 1501 may be placed between the second terminal and the other terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102. This allows each transistor to be switched at high speed. Note that the capacitive element 1501 is Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and wiring layer may be used as the conductive layers. Furthermore, a gate insulating film is used as the insulating layer, and a gate electrode layer and impurities are added as the conductive layer. A semiconductor layer may be used, or an interlayer film (insulating film) may be used as the insulating layer and a conductive layer Linear layers and transparent electrode layers may also be used. Parts common to the configuration in Figure 13 are indicated by the same reference numerals. We will use this to omit the explanation.

[0167] The flip-flop in Figure 16 can perform the same operation as in Figure 13. Figure 16 As shown in Figure 13, the first transistor 101 may be connected in a diode configuration. The first transistor 101 is connected to a diode, so the first wiring 111 is not This allows us to reduce the number of wires and power supplies (V1) by one each. Note the configuration shown in Figure 13. Where there are commonalities, we use the same symbols and omit the explanation.

[0168] Next, Figure 1 shows the shift register having the flip-flop of the above-described embodiment. Refer to section 7 for further explanation. Parts that are common to Figure 6, which was explained earlier, will be described using the same symbols and their explanations will be omitted.

[0169] The shift register consists of the first wiring 611, the second wiring 612, the third wiring 613, and the fourth wiring Wire 614, fifth wire 615, sixth wire 616, wires 622_1 to 622_n and n pieces It has (n stages) of flip-flops 1701_1~1701_n. Each of the flip-flops 1701_1 to 1701_n has a first wiring 611, and a second wiring 611. It is connected to wiring 612, the third wiring 613, the fourth wiring 614, and the fifth wiring 615. Also, for example, the i-th flip-flop 1701_i (flip-flop 1701_ One of 1-1701_n, flip flip 1701_2- flip Flop_n-1 is the i-1 stage flip-flop 1701_i-1 and the i+1 stage It is connected to the flip-flop 1701_i+1, and the i-th flip-flop 1701_i The connection point between this and the i+1 stage flip-flop 1701_i+1 is wire 622_i (wire It is connected to one of the 622_1 to 622_n. Note that the first stage flip Flop 1701_1 is connected to the sixth wire 616 and the second flip-flop 1701_2. The first stage flip-flop 1701_1 and the second stage flip-flop 1701_ The connection point to 2 is connected to wiring 622_1. Note that the nth stage flip-flop 1 701_n is connected to the (n-1) stage flip-flop 1701_n-1 and wiring 622_n. It is being done.

[0170] Note that in the 1+3N stage flip-flop 1701, the first wire is 611 and the second wire is 6 12. The third wiring 613, the fourth wiring 614, and the fifth wiring 615 are the third wirings in Figure 13, respectively. Wiring 111, Wiring 212, Wiring 313, Wiring 414, Wiring 7 It is connected to 1317. In the 2+3N stage flip-flop 1701, the first wiring Wiring 611, the second wiring 612, the fourth wiring 614, the fifth wiring 615, and the third wiring 613 are The first wiring 111, the second wiring 112, the third wiring 113, and the fourth wiring in Figure 13, respectively. Line 114 is connected to the 7th wire 1317. 3+3N stage flip-flop 60 In 1, the first wiring 611, the second wiring 612, the fifth wiring 615, the third wiring 613, The fourth wiring 614 corresponds to the first wiring 111, the second wiring 112, and the third wiring in Figure 13, respectively. It is connected to wire 113, the fourth wire 614, and the seventh wire 1317. Also, for example, stage i Of the flip-flops 1701_i, flip-flops 1701_2 and flip-flops The fifth wiring 115 and the sixth wiring 116 shown in Figure 13 of ROP 1701_n-1 are The sixth wiring 116 shown in Figure 13 for the i-1 stage flip-flop 1701_i-1, The fifth wire 115 shown in Figure 13 is connected to the i+1 stage flip-flop 1701_i+1. It is done. Furthermore, the fifth wiring shown in Figure 13 for the first stage flip-flop 1701_1 is... Wirings 15 and 6, 116, correspond to the sixth wiring 616 and the second flip-flop in Figure 17, respectively. It is connected to the fifth wiring 115 shown in Figure 13 of ROP 1701_2. The fifth wiring 115 and the sixth wiring 116 of the flip-flop 1701_n shown in Figure 13 are Each of these is the sixth wiring 1 shown in Figure 13 for the (n-1) stage flip-flop 1701_n-1. 16. It is connected to wiring 622_n in Figure 17.

[0171] Note that the shift register shown in Figure 17 operates in the same way as the shift register shown in Figure 6. Therefore, the shift register shown in Figure 17 has the timing channel shown in Figure 7. A chart can be used.

[0172] Therefore, the shift register in Figure 17 uses a three-phase clock signal, similar to Embodiment 1. This enables power saving. In addition, the shift register of this embodiment has each Connected to the lock signal lines (third wire 613, fourth wire 614, fifth wire 615) The number of flip-flop 1701 stages required is 2 / 3 of that when using a single-phase clock signal. Therefore, the load on each clock signal line can be reduced.

[0173] Note that the shift register in Figure 17 buffers the output signals of each stage's flip-flop 1701. The output may also be routed through to each stage's wiring 622, as shown in Figure 18. The shift register in Figure 18 has flip-flops 1701 in each stage that control buffer 1801. Since each stage is connected to the wiring 622 via these connections, a wide margin is obtained in operation. This is possible because a large load is connected to wiring 622, causing a delay in the signal from wiring 622. This is because even if delays or waveform distortions occur, it does not affect the operation of the shift register. The FF1801 is used in inverters, logic circuits such as NAND and NOR, operational amplifiers, etc. Circuits combining these elements can be used.

[0174] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the following. Similar to Embodiment 1, a scanning line driving circuit is formed integrally with the pixel section. By applying this embodiment, the lifespan of the display device can be extended.

[0175] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0176] (Embodiment 3) In this embodiment, a flip-flop with a different configuration from Embodiments 1 and 2 is used. This is shown in Figure 19. Note that components similar to those in Embodiment 1 and Embodiment 2 are referred to by the same reference numerals. This is shown using [a specific method / tool], and detailed explanations of identical or similarly functioning parts are omitted.

[0177] The flip-flop shown in Figure 19 consists of a first transistor 101 and a second transistor 10 2. Third transistor 103, fourth transistor 104, fifth transistor 130 5. Transistor 6, 1906; Transistor 7, 1907; Transistor 8, 1 It has transistors 908 and 9, and transistor 1909. The flip-flop is the first Wiring 111, second wiring 112, third wiring 113, fourth wiring 114, fifth wiring 1 15. It is connected to the sixth wiring 116 and the seventh wiring 1317. And the 6th transistor 1906, the 7th transistor 1907, the 8th transistor 1 Transistors 908 and 9, 1909, are N-channel transistors, and their gates and When the voltage between the sources (Vgs) exceeds the threshold voltage (Vth), it becomes a conduction state. Let's assume that.

[0178] The first terminal (either the source terminal or the drain terminal) of the first transistor 101 is the first distribution It is connected to line 111, and the second terminal (the other of the source terminal and drain terminal) is the second transient It is connected to the gate terminal of sta 102, and the gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the gate terminal of the second transistor 102. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal It is connected to the sixth wiring 116. The first terminal of the fourth transistor 104 is connected to the sixth wiring The second terminal is connected to wire 116, the second terminal is connected to the second wire 112, and the gate terminal is connected to wire 114 It is connected to the first terminal of the fifth transistor 1305, which is connected to the sixth wiring 116. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the seventh wiring 1317. The first terminal of the sixth transistor 1906 is connected to the gateway of the eighth transistor 1908. The first terminal is connected to the second terminal, the second terminal is connected to the second wiring 112, and the gate terminal is connected to the second terminal It is connected to the gate terminal of transistor 102. The first terminal of the seventh transistor 1907 is The first wire 111 is connected, and the second terminal is connected to the gate terminal of the eighth transistor 1908. The gate terminal is connected to the first wiring 111. Transistor 8 1908 The first terminal is connected to the third wire 113, and the second terminal is connected to the ninth transistor 1909. It is connected to the terminal. The first terminal of the ninth transistor 1909 is connected to the sixth wire 116. The second terminal is connected to the second wiring 112. 1906 first terminal, 7th transistor, 1907 second terminal and 8th transistor 1 The gate terminal of transistor 908 is connected to node 1922. Also, the eighth transistor 19 The connection point between the second terminal of 08 and the gate terminal of transistor 1909 is at node 192 Let's assume it's 3.

[0179] Furthermore, the second terminal of the third transistor 103, the second terminal of the fourth transistor 104, and The second terminal of transistor 1305 (number 5), the second terminal of transistor 1906 (number 6), and 9 The second terminal of transistor 1909 is not necessarily connected to the second wiring 112. They may be connected to separate wires. Also, the gate terminal of the third transistor 103 and The gate terminal of the fourth transistor 104 is not necessarily connected to the fourth wiring. They may be connected to separate wires. Also, the first terminal of the first transistor 101, The first terminal and the gate terminal of transistor 1907 are It is not limited to being connected to wiring 111; it may be connected to separate wiring. Also, the first terminal of the second transistor 102 and the first terminal of the eighth transistor 1908 It is not limited to being connected to the third wiring 113; it may be connected to a separate wiring. stomach.

[0180] Next, regarding the operation of the flip-flop shown in Figure 19, see the timing chart in Figure 20. Please refer to the explanation. Note that Figure 20 shows the flip-flop of Figure 19 as shown in Figures 1 and 13. This is a timing chart for operation similar to that of a flip-flop. Note that Figure 2 and Where there is commonality with the timing chart in Figure 14, the same symbols are used and the explanation is omitted.

[0181] In Figure 20, potential 2022 is the potential of node 1922 in Figure 19, and potential 2023 is This is the potential at node 1923 in Figure 19.

[0182] In the flip-flop shown in Figure 19, during the third non-selection period, the ninth transistor 190 9 turns on. Then the sixth wire 116 is connected to the ninth transistor 1909. The potential of wiring 112 in 2 is supplied, maintaining an L level.

[0183] Let's specifically explain the on / off control of the ninth transistor, 1909. First, the sixth transistor... Transistors 1906 and 1907 of transistor 7 constitute an inverter, and the 6th When a high level is input to the gate terminal of transistor 1906, the potential of node 1922 (Potential 2022) is approximately V2. However, the potential 2022 at this time is This is determined by the resistance ratio between the sixth transistor 1906 and the seventh transistor 1907. Therefore, it will be a slightly higher value than V2. Also, the gate terminal of the sixth transistor 1906 When an L level is input, the potential of node 1922 changes from the potential of the first wiring 111 to the seventh Since it is the value obtained by subtracting the threshold voltage of transistor 1907 (Vth1907), V1-V This becomes th1907. Therefore, the first non-selection period, the second non-selection period and the third non-selection period During the selection period, node 121 is at L level and node 1922 is at H level, so the 8th Transistor 1908 turns on. Therefore, the ninth transistor 1909 is the third Because it is controlled by the signal input to wiring 113, it is ON during the third non-selective period. During the first and second non-selection periods, it is turned off. On the other hand, during the set period... During the interval and selection period, node 121 will be at the H level and node 1922 will be at the L level. Therefore, the 8th transistor 1908 is turned off. Thus, the 9th transistor 1909 The potential of the gate terminal is the potential of the first non-selective period, which is the period before the set period, i.e., L level. To maintain the state, the ninth transistor, 1909, is turned off.

[0184] From the above, the flip-flop in Figure 19 has a first non-selection period, a second non-selection period, and And during the third non-selection period, V2 is supplied to wiring 116, so the flip-flop Malfunctions can be further suppressed because, during the non-selection period, the sixth wiring 11 This is because V2 can be supplied to 6. Also, the flip-flop in Figure 19 is not selected. Since V2 is supplied to the sixth wiring 116 during the selection period, the noise in the sixth wiring 116 It can be reduced.

[0185] Furthermore, the flip-flop in Figure 19 has a sixth transistor 1906 and a seventh transistor The characteristic degradation of transistors 1907, 1908 (the 8th transistor), and 1909 (the 9th transistor) It can be suppressed because the sixth transistor 1906 has set period and selection period This is because it turns on only during that period. Also, the seventh transistor 1907 is the second after the selection period. During the non-selective period of 1, the period in which the potential of node 1922 rises to V1-Vth1907 This is because it turns on in the first non-selective period. Also, the eighth transistor 1908 is the first non-selective period, the During the second nonselective period and the third nonselective period, the potential at node 1923 is V1-β(β:Vt This is because it only turns on during the period when it rises to h1907+Vth1908). This is because transistor 9, 1909, turns on only during the third non-selective period.

[0186] Note that the flip-flop in Figure 19 consists of the first transistor 101 and the second transistor 1 02, the third transistor 103, the fourth transistor 104, the fifth transistor 13 05, the 6th transistor 1906, the 7th transistor 1907, the 8th transistor Transistors 1908 and 1909 are all composed of N-channel transistors. It is characterized by having the semiconductor of a transistor. Therefore, the flip-flop in Figure 19 is a semiconductor of a transistor. Amorphous silicon can be used as the body layer, thus simplifying the manufacturing process. This allows for reduced manufacturing costs and improved yield. Furthermore, large tables It will also be possible to fabricate semiconductor devices such as display panels. Therefore, the manufacturing process can be simplified even when using polysilicon or single-crystal silicon. .

[0187] Furthermore, the flip-flop in Figure 19 exhibits characteristic degradation (threshold) as a semiconductor layer of the transistor. Even when using Amophas silicon, which exhibits a significant voltage shift, the transistor characteristics are inferior. Because degradation can be suppressed, it is possible to manufacture semiconductor devices such as display panels with a long lifespan. can.

[0188] Here, the sixth transistor 1906, the seventh transistor 1907, the eighth transistor The functions of transistors 1908 and 1909 are described. TA 1906 selects the timing for supplying the potential of the second wiring 112 to node 1922. It has the function of being a switching transistor. The seventh transistor, 1907 It has the function of selecting the timing for supplying the potential of the first wiring 111 to node 1922. It functions as a diode. The eighth transistor 1908 is the power of the third wiring 113. It has a function to select the timing to supply the position to node 1923, and switching transition It functions as a transistor. The ninth transistor 1909 raises the potential of the second wiring 112 to the sixth It has a function to select the timing to supply to wiring 116, and is a switching transistor. It functions.

[0189] If the device performs the same operation as in Figure 19, the arrangement and number of transistors should be the same as in Figure 19. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0190] For example, as shown in Figure 21, the gate terminal of the second transistor 102 shown in Figure 19 and A capacitive element 2101 may be placed between the second terminal and the other terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102. This allows each transistor to be switched at high speed. Note that the capacitive element 2101 is Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and wiring layer may be used as the conductive layers. Furthermore, a gate insulating film is used as the insulating layer, and a gate electrode layer and impurities are added as the conductive layer. A semiconductor layer may be used, or an interlayer film (insulating film) may be used as the insulating layer and a conductive layer Linear layers and transparent electrode layers may also be used. Parts common to the configuration in Figure 19 are indicated by the same reference numerals. We will use this to omit the explanation.

[0191] The flip-flop in Figure 22 can perform the same operation as in Figure 19. Figure 22 As shown in Figure 19, the first transistor 101 may be connected in a diode configuration. The first transistor 101 is connected to a diode, which causes current to flow through the first wiring 111. Because the current drawn becomes smaller, the wiring width of the first wiring 111 can be reduced. Parts that are common to the configuration in Figure 19 are indicated by the same numerals, and their explanations are omitted.

[0192] Furthermore, the flip-flop shown in this embodiment is suitable for the shift registers in Figures 17 and 18. It can be used. Similar to Embodiment 1 and Embodiment 2, a three-phase clock signal is used. This enables power saving. In addition, the shift register of this embodiment is each It is connected to the clock signal lines (third wire 613, fourth wire 614, fifth wire 615). The number of stages in the flip-flop 1701 is 2 / 3 of that when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced.

[0193] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the installation. Similar to Embodiment 1 and Embodiment 2, it is integrally formed with the pixel portion. By applying this embodiment to the scan line drive circuit, the lifespan of the display device can be extended. It is possible.

[0194] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0195] (Embodiment 4) In this embodiment, the configuration differs from that of Embodiments 1, 2 and 3. The top flop is shown in Figure 23. Note that it is the same as in Embodiments 1, 2 and 3. Similar items are indicated using a common code, and details of identical or similarly functioning parts are indicated. I will omit the detailed explanation.

[0196] The flip-flop shown in Figure 23 consists of a first transistor 101 and a second transistor 10 2. Third transistor 103, fourth transistor 104, fifth transistor 130 5. Transistor 6, 1906; Transistor 7, 1907; Transistor 8, 1 908, the 9th transistor; 1909, the 10th transistor; 2310, the 11th transistor It has transistor 2311 and transistor 2312. The first wiring 111, the second wiring 112, the third wiring 113, the fourth wiring 114, the It is connected to wiring 5 115, wiring 6 116 and wiring 7 1317. In this configuration, the 10th transistor 2310, the 11th transistor 2311 and the 1 The transistor 2312 is an N-channel transistor, and the gate and source of it The circuit is considered to conduct when the voltage (Vgs) exceeds the threshold voltage (Vth).

[0197] The first terminal (either the source terminal or the drain terminal) of the first transistor 101 is the first distribution It is connected to line 111, and the second terminal (the other of the source terminal and drain terminal) is the second transient It is connected to the gate terminal of sta 102, and the gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the second wiring 112, and the second terminal is connected to the second It is connected to the gate terminal of transistor 102, and the gate terminal is connected to the fourth wire 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal It is connected to the sixth wiring 116. The first terminal of the fourth transistor 104 is connected to the second wiring It is connected to wire 112, the second terminal is connected to the sixth wire 116, and the gate terminal is connected to the fourth wire It is connected to 114. The first terminal of the fifth transistor 1305 is connected to the second wiring 112. The second terminal is connected to the sixth wire 116, and the gate terminal is connected to the seventh wire 1317. They are connected. The first terminal of the sixth transistor 1906 is connected to the second wiring 112. The second terminal is the gate terminal of the 8th transistor 1908 and the 11th transistor 231 It is connected to the gate terminal of transistor 1, and its gate terminal is connected to the gate terminal of transistor 102. The first terminal of the seventh transistor 1907 is connected to the first wiring 111, and Terminal 2 is the gate terminal of the 8th transistor 1908 and the 11th transistor 2311. It is connected to the gate terminal, and the gate terminal is connected to the first wiring 111. The eighth transistor The first terminal of the ZISTA 1908 is connected to the third wiring 113, and the second terminal is connected to the ninth transistor The gate terminal of transistor 1909 and the gate terminal of transistor 10, 2310 are connected. The first terminal of the ninth transistor 1909 is connected to the second wiring 112, and the second terminal is The sixth wire 116 is connected. The first terminal of the tenth transistor 2310 is the second The second terminal is connected to the gate terminal of the second transistor 102, and the second terminal is connected to the gate terminal of the second transistor 102. The first terminal of the 11th transistor 2311 is connected to the 7th wire 1317, and the 2 The terminal is connected to the gate terminal of the 12th transistor 2312. The first terminal of sta2312 is connected to the second wiring 112, and the second terminal is connected to the second transistor It is connected to the gate terminal of 102. Also, the second terminal of the 11th transistor 2311. The connection point of the gate terminal of the 12th transistor 2312 is designated as node 2324.

[0198] Furthermore, the first terminal of the third transistor 103, the first terminal of the fourth transistor 104, and The first terminal of transistor 1305 (number 5), the first terminal of transistor 1906 (number 6), and the ninth The first terminal of transistor 1909, the first terminal of the tenth transistor 2310, and the 12th The first terminal of transistor 2312 is not necessarily connected to the second wiring 112. They may be connected to separate wires. Also, the gate terminal of the third transistor 103 and The gate terminal of the fourth transistor 104 is not limited to being connected to the fourth wiring 114. They may not be connected and may be connected to separate wires. Also, the first terminal of the first transistor 101 The first terminal of the seventh transistor 1907 and the gate terminal of the seventh transistor 1907 The child is not limited to being connected to the first wiring 111, and may be connected to separate wiring. Good. Also, the first terminal of the second transistor 102 and the terminal of the eighth transistor 1908 Terminal 1 is not necessarily connected to the third wire 113, but may be connected to separate wires. It is also possible to do so. Also, the gate terminal of the fifth transistor 1305 and the eleventh transistor 2 The first terminal of 311 is not necessarily connected to the seventh wire 1317, but can be connected to separate wires. It should be connected.

[0199] Next, regarding the operation of the flip-flop shown in Figure 23, see the timing chart in Figure 24. Refer to the following for explanation. Figure 24 shows the flip-flop of Figure 23, as shown in Figures 1, 13, and 19. This is a timing chart for operation similar to that of the flip-flop shown. (See Figure 2) Common elements in the timing charts of Figures 14 and 20 are explained using the same symbols. Omitted.

[0200] In Figure 24, potential 2424 is the potential of node 2324 in Figure 23.

[0201] In the flip-flop shown in Figure 23, the 10th transistor 231 occurs during the third non-selective period. 0 is turned on. Then, node 121 is connected to the second transistor 2310 via the 10th transistor 2310. Because the potential of wiring 112 is supplied, the L level can be maintained more stably. Furthermore, Figure 2 In the flip-flop 3, during the first non-selection period, the 12th transistor 2312 It turns on. Then, node 121 is connected to the second distribution via the 12th transistor 2312. Because the potential of line 112 is supplied, the L level can be maintained more stably.

[0202] The on / off control of the 12th transistor 2312 will be explained in detail. The on / off control of transistor 2310 is performed by the ninth transistor shown in Embodiment 3. This is similar to the on / off control of the ST1909. First, the flip-flop in Figure 19 is the same as Thus, the sixth transistor 1906 and the seventh transistor 1907 constitute the inverter. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, Node 121 is at an L level and Node 1922 is at an H level, so the 11th transition Transistor 2311 turns on. Therefore, the 12th transistor 2312 is connected to the 7th wiring 131 Because it is controlled by the signal input to 7, it turns on during the second non-selection period, and It is turned off during the first non-selection period and the third non-selection period. On the other hand, during the set period and selection During this period, node 121 will be at the H level and node 1922 will be at the L level, so the 11th Transistor 2311 is turned off. Therefore, the gate terminal of the 12th transistor 2312 The potential of the child remains at the potential of the first nonselective period, which is the period before the set period, i.e., the L level. Therefore, the 12th transistor 2312 is turned off.

[0203] From the above, the flip-flop in Figure 23 has a first non-selection period, a second non-selection period, and During the third non-selection period, V2 was supplied to the sixth wiring 116 and node 121. Therefore, malfunctions of the flip-flop can be further suppressed. This is because during the non-selection period... This is because V2 can be supplied to the sixth wiring 116 and node 121. Furthermore, the flip-flop in Figure 23 has the sixth wiring 116 and node 1 during the non-selection period. Since V2 is supplied to 21, the noise in the sixth wiring 116 and node 121 is reduced. It is possible.

[0204] Furthermore, the flip-flop in Figure 23 has a 10th transistor 2310 and an 11th transistor This makes it possible to suppress the characteristic degradation of transistors 2311 and 2312. This is because the tenth transistor 2310 turns on only during the third non-selective period. Furthermore, the 11th transistor 2311 has a first non-selective period, a second non-selective period and During the 3 non-selective period, the potential of node 2324 is V1-γ(γ:Vth1907+Vth2 This is because it only turns on during the period when it rises to 311). Also, the 12th transistor 2 This is because 312 is only turned on during the second non-selective period.

[0205] Note that the flip-flop in Figure 23 consists of the first transistor 101 and the second transistor 1 02, the third transistor 103, the fourth transistor 104, the fifth transistor 13 05, the 6th transistor 1906, the 7th transistor 1907, the 8th transistor 1908, the 9th transistor; 1909, the 10th transistor; 2310, the 11th transistor Transistors 2311 and 12, transistor 2312, are all N-channel type transistors. It is characterized by being configured in this way. Therefore, the flip-flop in Figure 23 is a transition Because amorphous silicon can be used as the semiconductor layer of the st, the manufacturing process is simplified. This allows for simplification, leading to reduced manufacturing costs and improved yield. This also makes it possible to manufacture semiconductor devices such as large display panels. By using polysilicon or single-crystal silicon as the semiconductor layer, the manufacturing process can be simplified. It is possible.

[0206] Furthermore, the flip-flop in Figure 23 exhibits characteristic degradation (threshold) as a semiconductor layer of the transistor. Even when using Amophas silicon, which exhibits a significant voltage shift, the transistor characteristics are inferior. Because degradation can be suppressed, it is possible to manufacture semiconductor devices such as display panels with a long lifespan. can.

[0207] Here, the 10th transistor 2310, the 11th transistor 2311 and the 12th transistor The function of transistor 2312 will be explained. The tenth transistor 2310 is the second The switch has a function to select the timing for supplying the potential of wiring 112 to node 121. It functions as a junction transistor. The 11th transistor 2311 is connected to the 7th wiring 131 It has a function to select the timing for supplying potential 7 to node 2324, and switching It functions as a transistor. The 12th transistor 2312 controls the potential of the second wiring 112. It has a function to select the timing to supply to node 121, and a switching transistor and It functions in this way.

[0208] If the device performs the same operation as shown in Figure 23, the arrangement and number of transistors should be the same as in Figure 23. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0209] For example, as shown in Figure 25, the gate terminal of the second transistor 102 shown in Figure 23 and A capacitive element 2501 may be placed between the second terminal and the other terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102. This allows each transistor to be switched at high speed. Note that the capacitive element 2501 is Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and wiring layer may be used as the conductive layers. Furthermore, a gate insulating film is used as the insulating layer, and a gate electrode layer and impurities are added as the conductive layer. A semiconductor layer may be used, or an interlayer film (insulating film) may be used as the insulating layer and a conductive layer Linear layers and transparent electrode layers may also be used. Note that parts common to the configuration in Figure 23 are indicated by the same reference numerals. We will use this to omit the explanation.

[0210] The flip-flop in Figure 26 can perform the same operation as in Figure 23. Figure 26 As shown in Figure 23, the first transistor 101 may be connected in a diode configuration. The first transistor 101 is connected to a diode, which causes current to flow through the first wiring 111. Because the current drawn becomes smaller, the wiring width of the first wiring 111 can be reduced.

[0211] Furthermore, the flip-flop shown in this embodiment is suitable for the shift registers in Figures 17 and 18. It can be used. Similar to Embodiments 1, 2 and 3, a three-phase chrome Since a shift signal can be used, power saving can be achieved. Also, the shift of this embodiment The registers are connected to each clock signal line (third wire 613, fourth wire 614, fifth wire 61 5) The number of stages of the flip-flop 1701 connected to it when using a single-phase clock signal Since it becomes 2 / 3 of the combined value, the load on each clock signal line can be reduced.

[0212] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the placement. Similar to Embodiments 1, 2 and 3, pixels By applying this embodiment to the scanning line drive circuit formed integrally with the part, the life of the display device is extended. It can prolong life.

[0213] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0214] (Embodiment 5) In this embodiment, the transistor in the flip-flop is a P-channel type transistor. The application will be explained with reference to Figure 27. Note that it is constructed using a P-channel transistor. The flip-flops used are flip-flops composed of N-channel transistors. The basic configuration is the same. However, the power supply potential and the H level and L level of the signal are inverted. It is.

[0215] Figure 27 shows one of the multiple flip-flops in a shift register (for example, 1 The first flip-flop is shown in Figure 27. The flip-flop shown in Figure 27 is the first trap Transistor 2701, second transistor 2702, third transistor 2703 and fourth It has transistor 2704. The flip-flop has the first wiring 2711, the second Wiring 2712, Wiring 3713, Wiring 4714, Wiring 5715 and It is connected to the sixth wiring 2716. In this embodiment, the first transistor 27 01, second transistor 2702, third transistor 2703 and fourth transistor The TA2704 is a P-channel transistor, and the absolute value of the voltage between its gate and source is (| When Vgs| exceeds the threshold voltage (|Vth|) (when Vgs falls below Vth) (i) and shall be in a conductive state. Note that the first wiring 2711 and the second wiring 2712 These may be called the first power line and the second power line, respectively. Also, the third wiring 2713 and The fourth wiring 2714 may also be called the first signal line and the second signal line, respectively.

[0216] Furthermore, the first transistor 2701, the second transistor 2702, and the third transistor Transistors 2703 and 4, 2704, are the same as the first transistor 101 in Figure 1. , second transistor 102, third transistor 103 and fourth transistor 104 This corresponds to the first wiring 2711, the second wiring 2712, the third wiring 2713, and the Wiring 4 2714, wiring 5 2715, and wiring 6 2716 are the first wires in Figure 1, respectively. Wiring 111, second wiring 112, third wiring 113, fourth wiring 114, fifth wiring 1 15. This corresponds to the sixth wiring 116.

[0217] The first terminal (either the source terminal or the drain terminal) of the first transistor 2701 is the first Connected to wiring 2711, the second terminal (the other of the source and drain terminals) is connected to the second transistor It is connected to the gate terminal of inverter 2702, and the gate terminal is connected to the fifth wiring 2715. The first terminal of the third transistor 2703 is connected to the second wiring 2712, and the second The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 It is connected to 714. The first terminal of the second transistor 2702 is connected to the third wire 2713. The second terminal is connected to the sixth wire 2716. The fourth transistor 27 The first terminal of 04 is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the fourth wiring 2714. The second terminal of 701, the gate terminal of the second transistor 2702, and the third transistor The connection point between 2703 and its second terminal is designated as node 2721.

[0218] Furthermore, the second terminal of the third transistor 2703 and the second terminal of the fourth transistor 2704 The child is not limited to being connected to the second wiring 2712, but may be connected to separate wiring. This is also acceptable. Furthermore, the gate terminal of the third transistor 2703 and the fourth transistor 27 The gate terminal of 04 is not necessarily connected to the fourth wiring 2714, but can be connected to separate wirings. It should be connected.

[0219] Next, regarding the operation of the flip-flop shown in Figure 27, see the timing chart in Figure 28. This will be explained with reference to Figure 29. Note that in Figure 28, the set period, selection period, and non-selection period are shown. Let me explain the intervals. Note that the non-selection period is the first non-selection period, the second non-selection period, and It is divided into three non-selection periods: the first non-selection period, the second non-selection period, and the third non-selection period. This process is repeated in sequence.

[0220] The first wiring 2711 is supplied with a potential of V2, and the second wiring 2712 is supplied with a potential of V1. This is the case, provided that V1 > V2.

[0221] However, it is not limited to the first wiring 2711 being supplied with the potential of V2; other potentials may also be supplied. A power supply may be provided, or a digital or analog signal may be input. Furthermore, it is not limited to the second wiring 2712 being supplied with the potential of V1; other potentials may also be supplied. It may be supplied, or a digital or analog signal may be input.

[0222] Furthermore, signals are input to the third wiring 2713, the fourth wiring 2714, and the fifth wiring 2715. The signal input to the third wiring 2713 is the first clock signal, and the fourth The signal input to wiring 2714 is the second clock signal, which is input to the fifth wiring 2715. The signal being transmitted is the start signal. Also, the third wiring 2713, the fourth wiring 2714 and The signal input to the fifth wiring 2715 is an H signal with a potential of V1 (hereinafter also referred to as the H level). ), is a digital signal with a potential of V2 (hereinafter also referred to as L level).

[0223] However, it is not necessarily the case that the first clock signal is input to the third wiring 2713. Other signals may be input, or a constant potential or current may be input. Also, Wiring 2714 of 4 is not necessarily limited to receiving the second clock signal; other signals may also be present. It may be input, or a certain potential or current may be input. Also, the fifth wiring 2 It is not limited to the input of a start signal to 715; other signals may be input as well. Furthermore, a certain potential or current may be input.

[0224] Furthermore, signals input to the third wiring 2713, the fourth wiring 2714, and the fifth wiring 2715 The potential of the H signal is not limited to V1 and the potential of the L signal is not limited to V2; the potential of the H signal is not limited to the potential of the L signal As long as it is higher than the potential, that potential is not particularly limited.

[0225] Furthermore, a signal is output from the sixth wiring 2716. The signal is the output signal of the flip-flop and the start signal for the next stage flip-flop. Also, the signal output from the sixth wire 2716 is used for the next stage flip-flop. It is input to the fifth wire 2715. Also, the signal output from the sixth wire 2716 is The potential of the H signal is V1 (hereinafter also called the H level), and the potential of the L signal is V2 (hereinafter also called the L level). It is a digital signal (also known as a digital signal).

[0226] In Figure 28, signal 2813 is a signal input to the third wiring 2713, and signal 28 Signal 14 is input to the fourth wiring 2714, and signal 2815 is input to the fifth wiring 2715 The signal is input to the circuit, and signal 2816 is the signal output from the sixth wiring 2716. Furthermore, potential 2821 is the potential of node 2721 in Figure 27.

[0227] First, during period A in Figure 28 and the set period shown in Figure 29(A), signal 2813 and signal 2 814 is at an H level, and signal 2815 is at an L level. Therefore, the third transient Transistors 2703 and 4th transistor 2704 are turned off, and the first transistor 270 1 is turned ON. At this time, the second terminal of the first transistor 2701 becomes the source terminal. The potential of node 2721 (potential 2821) is the same as the potential of the fifth wiring 2715 and the first transient Since it is the sum of the absolute value of the threshold voltage of ST2701 and V2, it becomes V2 + |Vth2701|. Therefore, the second transistor 2702 turns on, and the potential of the sixth wire 2716 becomes the third Since it becomes equal to the potential of wiring 2713, it becomes V1. In this way, during the set period, The flop keeps the second transistor 2702 on and sets the sixth wiring 27 to a high level. Output from 16.

[0228] During period B in Figure 28 and the selection period shown in Figure 29(B), signal 2813 becomes L level. Signal 2814 remains at a high level, and signal 2815 becomes high level. Therefore, The third transistor 2703 and the fourth transistor 2704 remain off, and the first Transistor 2701 turns off. At this time, the second terminal of the second transistor 2702 This becomes the source terminal, and the potential of the sixth wire 2716 begins to decrease. Potential of node 2721 (Potential 2821) indicates that node 2721 is in a floating state (hereinafter also referred to as the floating state). Therefore, the parasitic cavity between the gate terminal and the second terminal of the second transistor 2702 The potential of the sixth wire 2716 decreases simultaneously with the capacitance coupling (bootstrap operation). (Also known as...). Therefore, the voltage Vgs between the gate and source of the second transistor 2702 is - |Vth2702|-α(Vth2702: threshold voltage of the second transistor 2702) (α: any positive number), and the potential of the sixth wire 2716 becomes L level (V2). As shown, during the selection period, the flip-flop changes the potential of node 2721 to V2-|Vth2 By setting it to 702|-α, the L level can be output from the sixth wiring 2716. Cut.

[0229] During period C in Figure 28 and the first non-selective period shown in Figure 29(C), signal 2813 is at the H level. As a result, signal 2814 is at a low level, while signal 2815 remains at a high level. Then, the third transistor 2703 and the fourth transistor 2704 turn on, and the first Transistor 2701 remains off. Node 2721 and wiring 2716 of the sixth The second distribution is via the third transistor 2703 and the fourth transistor 2704, respectively. The potential supplied by line 2712 results in an H level.

[0230] During period D in Figure 28 and the second non-selective period shown in Figure 29(D), signal 2813 is at the H level. The situation remains the same, with signal 2814 at an H level and signal 2815 remaining at an H level. Therefore, the third transistor 2703 and the fourth transistor 2704 are turned off. Therefore, the first transistor 2701 remains off. Thus, node 2721 and Wiring 2716 of 6 maintains an H level.

[0231] During period E in Figure 28 and the third non-selective period shown in Figure 29(E), signal 2813 is at the L level. As a result, signal 2814 remains at the high level, and signal 2815 remains at the high level. Therefore, the first transistor 2701, the third transistor 2703 and the fourth transistor The inverter 2704 remains off. Therefore, the wiring 2721 and the 6th node 27 16 maintains an H level.

[0232] From the above, the flip-flop in Figure 27 is the third transistor 2703 and the fourth Since transistor 2704 turns on only during the first non-selective period, the third transistor 2 This suppresses the characteristic degradation (threshold voltage shift) of transistors 703 and the fourth transistor 2704. This is possible. Note that the flip-flop in Figure 27 is connected to the first transistor 2701 and The two transistors 2702 operate only during the set period, and only during the set period and selection period, respectively. As a result, the characteristics of the first transistor 2701 and the second transistor 2702 deteriorate. It can also be suppressed.

[0233] Furthermore, in the flip-flop shown in Figure 27, during the non-selection period, in the first non-selection period, V1 is supplied to wires 2721 and 2716 of the sixth circuit, causing the flip-flop to malfunction. This can be suppressed. This is because, during the nonselection period, every certain period (the first nonselection period) V1 is supplied to node 2721 and the sixth wiring 2716 in between, node 2721 This is because the potential of the sixth wiring 2716 can be stably maintained at V1.

[0234] Note that the flip-flop in Figure 27 consists of the first transistor 2701 and the second transistor 2702, the third transistor 2703, and the fourth transistor 2704 are all P-channel. It is characterized by being composed of a flip-type transistor. Therefore, the flip-flop in Figure 27 Lop can simplify the manufacturing process, leading to reduced manufacturing costs and improved yield. It is possible to use polysilicon or single-crystal silicon as the semiconductor layer of a transistor. The manufacturing process can also be simplified by using this method.

[0235] Here, the first transistor 2701, the second transistor 2702, and the third transistor The functions of transistors 2703 and 2704 will be described. The 2701 has the function of selecting the timing for supplying potential to the first wiring 2711. It functions as an input transistor. The second transistor 2702 is connected to the third wiring 271 Select the timing to supply potential 3 to the sixth wiring 2716, and the potential of node 2721 It has a function to reduce through bootstrap operation, and a bootstrap transistor The third transistor 2703 controls the potential of the second wiring 2712 at node 2. It has a function to select the timing to supply to 721, and functions as a switching transistor. The fourth transistor 2704 controls the potential of the second wiring 2712 to the sixth wiring 271 It has the function of supplying power to 6 and functions as a switching transistor.

[0236] If the device performs the same operation as shown in Figure 27, the arrangement and number of transistors should be the same as in Figure 27. It is not limited to this. As can be seen from Figure 29, which explains the operation of the flip-flop in Figure 27, In this embodiment, the set period, the selection period, the first non-selection period, the second non-selection period, and During the non-selection period of 3, continuity is maintained as shown by the solid lines in Figures 29(A) to (E). Therefore, the transistors and other components should be arranged to satisfy this condition and be in a configuration that can operate. Transistors, other elements (resistors, capacitors, etc.), diodes, switches Various logic circuits and other elements may be added.

[0237] For example, as shown in Figure 30, the gate terminal of the second transistor 2701 shown in Figure 27. A capacitive element 3001 may be placed between the second terminal and the first terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and impurities may be added as the conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer to form a conductive layer. A wiring layer and a transparent electrode layer may also be used. Note that the configurations in common with those in Figure 27 are the same. The explanation is omitted by using symbols.

[0238] Note that the capacitive element 3001 corresponds to the capacitive element 401 in Figure 4.

[0239] The flip-flop in Figure 31 can perform the same operation as in Figure 27. Figure 31 As shown in Figure 27, the first transistor 2701 is connected in a diode configuration. This may also be the case. The first transistor 2701 is diode-connected, so the first distribution This eliminates the need for wire 2711, allowing for a reduction of one wire and one power supply (V2). Parts that are common to the configuration in Figure 27 are indicated by the same numerals, and their explanations are omitted.

[0240] Furthermore, the flip-flop shown in this embodiment is applied to the shift registers in Figures 6 and 8. This is possible. Similar to Embodiments 1 to 4, a three-phase clock signal is used. This enables power saving. In addition, the shift register of this embodiment has each cross It is connected to the signal lines (third wire 613, fourth wire 614, fifth wire 615) The number of flip-flop 601 stages is reduced to 2 / 3 compared to when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced. However, the first wiring 611 and the potential supplied to the second wiring 612, the third wiring 613, the fourth wiring 614, and the fifth The signals input to wiring 615 and the sixth wiring 616, and the signal output to wiring 622 are The flip-flops composed of N-channel transistors are shown in Figures 6 and 8. Compared to when applied to a full register, the H level and L level are inverted.

[0241] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the installation. Similar to Embodiments 1 to 4, it is integrally formed with the pixel portion. By applying this embodiment to the scan line drive circuit, the lifespan of the display device can be extended. It is possible.

[0242] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0243] (Embodiment 6) In this embodiment, the P-channel transistor is configured differently from that of Embodiment 5. A flip-flop is shown in Figure 32. Note that the same components as in Embodiment 5 are common. Parts are indicated using symbols, and detailed descriptions of identical or similarly functioning parts are omitted.

[0244] The flip-flop shown in Figure 32 consists of a first transistor 2701 and a second transistor 2 702, the third transistor 2703, the fourth transistor 2704 and the fifth transistor It has a 3205. The flip-flop has a first wiring 2711 and a second wiring 2 712, third wiring 2713, fourth wiring 2714, fifth wiring 2715, sixth wiring 2 The wiring 716 and 7 is connected to wiring 3217. In this embodiment, the fifth transistor The ZISTA 3205 is a P-channel transistor, and the absolute value of the voltage between its gate and source is... When (|Vgs|) exceeds the threshold voltage (|Vth|) (when Vgs falls below Vth) (When this happens), it shall be assumed that it becomes conductive. Note that the seventh wiring 3217 shall be called the third signal line. That's fine.

[0245] Note that the fifth transistor 3205 corresponds to the fifth transistor 1305 in Figure 13. Furthermore, the seventh wiring 3217 corresponds to the seventh wiring 1317 in Figure 13.

[0246] The first terminal (either the source terminal or the drain terminal) of the first transistor 2701 is the first Connected to wiring 2711, the second terminal (the other of the source and drain terminals) is connected to the second transistor It is connected to the gate terminal of inverter 2702, and the gate terminal is connected to the fifth wiring 2715. The first terminal of the third transistor 2703 is connected to the second wiring 2712, and the second The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 It is connected to 714. The first terminal of the second transistor 2702 is connected to the third wire 2713. The second terminal is connected to the sixth wire 2716. The fourth transistor 27 The first terminal of 04 is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the fourth wire 2714. The fifth transistor 3205 The first terminal is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the seventh wiring 3217.

[0247] Note that the first terminal of the third transistor 2703 and the first terminal of the fourth transistor 2704 And the first terminal of the fifth transistor 3205 is connected to the second wiring 2712. This is not limited and may be connected to separate wiring. Also, the third transistor 2703 The gate terminal of the fourth transistor 2704 and the gate terminal of the fourth transistor 2714 are connected to the fourth wiring 2714. It is not limited to being connected in this way; they may be connected to separate wires.

[0248] Next, regarding the operation of the flip-flop shown in Figure 32, see the timing chart in Figure 33. Refer to the explanation. Note that Figure 33 is the flip-flop shown in Figure 32, and the flip-flop shown in Figure 27. This is a timing chart for operation similar to a flop. Note that the timing in Figure 28 Where there are commonalities with the rhyming chart, the same symbols are used and explanations are omitted.

[0249] Furthermore, a signal is input to the seventh wiring 3217. The signal is the third clock signal. Also, the signal input to the seventh wiring 3217 is H The potential of the signal is V1 (hereinafter also called the H level), and the potential of the L signal is V2 (hereinafter also called the L level). It is a digital signal (also known as a digital signal).

[0250] However, it is not necessarily the case that the third clock signal is input to the seventh wiring 3217. Other signals may be input, or a constant potential or current may be input.

[0251] In Figure 33, signal 3317 is the signal input to the seventh wiring 3217.

[0252] In the flip-flop shown in Figure 32, the fifth trap occurs during the set period and the second non-selection period. Transistor 3205 is turned on. Then, the sixth wire 2716 is connected to the fifth transistor 3 The potential of the second wiring 2712 is supplied via 205, thus maintaining an H level.

[0253] From the above, the flip-flop in Figure 32 has a first non-selection period, a second non-selection period, During the third non-selection period, in the first non-selection period and the second non-selection period, the sixth wiring Since V1 is supplied to the 2716, malfunctions of the flip-flop can be further suppressed. This is because, during the non-selection period, at regular intervals (the first non-selection period and the second non-selection period) During this time, V1 is supplied to the sixth wiring 2716, stabilizing the potential of the sixth wiring 2716. This is because it allows it to be maintained at V1.

[0254] Furthermore, the flip-flop in Figure 32 has a fifth transistor 3205 which is set for a set period and Since it turns on only during the non-selective period of 2, it suppresses the characteristic degradation of the fifth transistor 3205. It is possible.

[0255] Note that the flip-flop in Figure 32 consists of the first transistor 2701 and the second transistor 2702, the third transistor 2703, the fourth transistor 2704 and the fifth transistor The ZISTA 3205 is characterized by being composed entirely of P-channel type transistors. Therefore, the flip-flop in Figure 32 can simplify the manufacturing process and reduce manufacturing costs. This can reduce waste and improve yield. Furthermore, as a semiconductor layer for transistors, The manufacturing process can also be simplified by using polysilicon or single-crystal silicon.

[0256] Here, we will explain the function of the fifth transistor 3205. 05 selects the timing to supply the potential of the second wiring 2712 to the sixth wiring 276. It has a function and functions as a switching transistor.

[0257] If the device performs the same operation as shown in Figure 32, the arrangement and number of transistors should be the same as in Figure 32. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0258] For example, as shown in Figure 34, the gate terminal of the second transistor 2702 shown in Figure 32. A capacitive element 3401 may be placed between the second terminal and the first terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and impurities may be added as the conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer to form a conductive layer. A wiring layer and a transparent electrode layer may also be used. Note that the configurations in common with those in Figure 32 are the same. The explanation is omitted by using symbols.

[0259] Note that the capacitive element 3401 corresponds to the capacitive element 1501 in Figure 15.

[0260] The flip-flop in Figure 35 can perform the same operation as in Figure 32. Figure 35 As shown in Figure 32, the first transistor 2701 is diode-connected. This is also good. The first transistor 2701 is diode-connected, and the first wiring The 2711 becomes unnecessary, allowing for a reduction of one wire and one power supply (V2). Parts that are common to the configuration in Figure 32 are indicated by the same numerals, and their explanations are omitted.

[0261] Furthermore, the flip-flop shown in this embodiment is suitable for the shift registers in Figures 17 and 18. It can be used. Similar to Embodiments 1 to 5, a three-phase clock signal is used. This enables power saving. In addition, the shift register of this embodiment is each It is connected to the clock signal lines (third wire 613, fourth wire 614, fifth wire 615). The number of stages in the flip-flop 1701 is 2 / compared to when a single-phase clock signal is used. Since it becomes 3, the load on each clock signal line can be reduced. However, the first wiring The potential supplied to 611 and the second wiring 612, and the third wiring 613 and the fourth wiring 614 The signals input to the fifth wiring 615 and the sixth wiring 616, and the output to wiring 622 The signals are each connected to a flip-flop composed of N-channel transistors, as shown in Figure 17 and Compared to when applied to the shift register in Figure 18, the H level and L level are reversed. .

[0262] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the installation. Similar to Embodiments 1 to 5, it is integrally formed with the pixel portion. By applying this embodiment to the scan line drive circuit, the lifespan of the display device can be extended. It is possible.

[0263] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0264] (Embodiment 7) In this embodiment, a flip-flop with a different configuration from Embodiments 5 and 6 is used. This is shown in Figure 36. Note that components similar to those in Embodiments 5 and 6 share the same reference numerals. This is shown using [a specific method / tool], and detailed explanations of identical or similarly functioning parts are omitted.

[0265] The flip-flop shown in Figure 36 consists of a first transistor 2701 and a second transistor 2 702, the third transistor 2703, the fourth transistor 2704, the fifth transistor Transistor 3205, the 6th transistor 3606, the 7th transistor 3607, the 8th transistor It has transistor 3608 and transistor 3609. This refers to the first wiring 2711, the second wiring 2712, the third wiring 2713, and the fourth wiring 271 4. Connected to the fifth wiring 2715, the sixth wiring 2716 and the seventh wiring 3217. In this embodiment, the sixth transistor 3606, the seventh transistor 3607, The eighth transistor 3608 and the ninth transistor 3609 are P-channel type transistors. Let the absolute value of the voltage between its gate and source (|Vgs|) be the threshold voltage (|Vth|). The circuit will be in a conductive state when it exceeds |) (when Vgs falls below Vth).

[0266] The first terminal (either the source terminal or the drain terminal) of the first transistor 2701 is the first Connected to wiring 2711, the second terminal (the other of the source and drain terminals) is connected to the second transistor It is connected to the gate terminal of inverter 2702, and the gate terminal is connected to the fifth wiring 2715. The first terminal of the third transistor 2703 is connected to the second wiring 2712, and the second The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 It is connected to 714. The first terminal of the second transistor 2702 is connected to the third wire 2713. The second terminal is connected to the sixth wire 2716. The fourth transistor 27 The first terminal of 04 is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the fourth wire 2714. The fifth transistor 3205 The first terminal is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the seventh wiring 3217. The sixth transistor 3606 Terminal 1 is connected to the second wire 2712, and terminal 2 is connected to the gateway of the eighth transistor 3208. The gate terminal is connected to the gate terminal of the second transistor 2702. The first terminal of the seventh transistor 3607 is connected to the first wiring 2711, and the second terminal The child is connected to the gate terminal of the eighth transistor 3608, and the gate terminal is connected to the first wiring 27 It is connected to 11. The first terminal of the 8th transistor 3608 is connected to the 3rd wire 2713. The second terminal is connected to the gate terminal of the ninth transistor 3609. The first terminal of transistor 3609 is connected to the second wire 2712, and the second terminal is connected to the sixth It is connected to wiring 2716. Also, the second terminal of the sixth transistor 3606, and the seventh The connection point between the second terminal of transistor 3607 and the gate terminal of the eighth transistor 3608. Let the location be node 3622. Also, the second terminal of the eighth transistor 3608 and the ninth The gate terminal of transistor 3609 is connected to node 3623.

[0267] Note that the first terminal of the third transistor 2703 and the first terminal of the fourth transistor 2704 , the first terminal of the fifth transistor 3205, the first terminal of the sixth transistor 3606 and The first terminal of the ninth transistor 3609 is not necessarily connected to the second wiring 2712. They may not be connected, and may be connected to separate wires. Also, the gateway of the third transistor 2703 The gate terminal and the gate terminal of the fourth transistor 2704 are connected to the fourth wiring 2714. It is not limited to being present, and may be connected to separate wiring. Also, the first transistor 2 The first terminal of 701, the first terminal of the seventh transistor 3607, and the seventh transistor 36 The gate terminal of 07 is not necessarily connected to the first wiring 2711, but can be connected to separate wirings. They may be connected. Also, the first terminal of the second transistor 2702 and the eighth transistor The first terminal of ZISTA 3608 is not necessarily connected to the third wiring 2713, but can be connected separately. It may be connected to the wiring.

[0268] Next, regarding the operation of the flip-flop shown in Figure 36, see the timing chart in Figure 37. Please refer to the following for explanation. Note that Figure 37 shows the flip-flop of Figure 36, as shown in Figures 27 and 32. This is a timing chart for operation similar to that of the flip-flop shown. (See Figure 2) Parts common to the timing charts in Figures 8 and 33 are explained using the same symbols and without further explanation. ru.

[0269] In Figure 37, potential 3722 is the potential of node 3622 in Figure 36, and potential 3723 is This is the potential at node 3623 in Figure 36.

[0270] In the flip-flop of Figure 36, during the third non-selection period, the ninth transistor 360 9 is turned on. Then, the sixth wire 2716 is connected to the ninth transistor 3609 via The potential of the second wiring 2712 is supplied, maintaining an H level.

[0271] Let's specifically explain the on / off control of the ninth transistor 3609. First, the sixth transistor... Transistors 3606 and 3607 of transistor 7 constitute an inverter, When an L level is input to the gate terminal of inverter 3606, the potential of node 3622 (potential) 3722) is approximately V1. However, the potential 3722 at this time is the 6th This is determined by the resistance ratio between transistor 3606 and the seventh transistor 3607. The value is slightly lower than V1. Also, the gate terminal of the sixth transistor 3606 has an H value. When the bell is input, the potential of node 3622 is equal to the potential of the first wiring 2711 and the seventh transistor. Since it is the sum of the absolute value of the threshold voltage of the ZISTRA 3607 and V2, it becomes V2 + |Vth3607|. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, no Since node 2721 is at an H level and node 3622 is at an L level, the 8th transistor 3608 turns on. Therefore, the ninth transistor 3609 is connected to the third wiring 2713. Because it is controlled by the input signal, it turns on during the third non-selection period, and the first It is turned off during the non-selection period and the second non-selection period. On the other hand, during the set period and the selection period Therefore, since node 2721 is at L level and node 3622 is at H level, the 8th node Transistor 3608 is turned off. Therefore, the gate terminal of the ninth transistor 3609 The potential is maintained at the H level, which is the potential of the first non-selective period, the period preceding the set period. Therefore, the ninth transistor, 3609, is turned off.

[0272] From the above, the flip-flop in Figure 36 has a first non-selection period, a second non-selection period, and During the third non-selection period, V1 is supplied to the sixth wiring 2716, so the flip-flop This can further suppress malfunctions of the rop. This is because, during the non-selection period, the sixth This is because V1 can be supplied to wiring 2716. Also, the flip-flop in Figure 36 Because V1 is supplied to the sixth wiring 2716 during the non-selection period, the sixth wiring 27 It can reduce 16 types of noise.

[0273] Furthermore, the flip-flop in Figure 36 has a sixth transistor 3606 and a seventh transistor The characteristic degradation of transistors 3607, 3608 (the 8th transistor), and 3609 (the 9th transistor) It can be suppressed because the sixth transistor 3606 has set period and selection period This is because it turns on only during that period. Also, the seventh transistor 3607 is the second after the selection period. During one non-selective period, the potential of node 3622 decreases to V2+|Vth3607|. This is because it turns on only during the interval. Also, the eighth transistor 3608 is the first non-selective period During the second and third nonselective periods, the potential of node 3623 is V2+δ(δ: This is because it only turns on during the period when it decreases to |Vth3607|+|Vth3608|). Furthermore, the ninth transistor 3609 turns on only during the third non-selective period. .

[0274] Note that the flip-flop in Figure 36 consists of the first transistor 2701 and the second transistor 2702, the third transistor; 2703, the fourth transistor; 2704, the fifth transistor Transistor 3205, the 6th transistor 3606, the 7th transistor 3607, the 8th transistor Transistors 3608 and 3609 are all P-channel type transistors. It is characterized by being made. Therefore, the flip-flop in Figure 36 is a transistor By using polysilicon or single-crystal silicon as the semiconductor layer, the manufacturing process can be simplified. It is possible.

[0275] Here, the sixth transistor 3606, the seventh transistor 3607, and the eighth transistor The functions of transistors 3608 and 3609 are described. Node 3606 selects the timing to supply the potential of the second wiring 2712 to node 3622. It has the function of being a switching transistor. The seventh transistor 360 7 is a function that selects the timing for supplying the potential of the first wiring 2711 to node 3622. It has and functions as a diode. The eighth transistor 3608 is connected to the third wiring 271 It has a function to select the timing for supplying potential 3 to node 3623, and switching It functions as a transistor. The ninth transistor 3609 is at the potential of the second wiring 2712. It has a function to select the timing for supplying to the sixth wiring 2716, and switching transistor It functions as a ZISTA.

[0276] Furthermore, if the operation is the same as that shown in Figure 36, the arrangement and number of transistors should be the same as in Figure 36. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0277] For example, as shown in Figure 38, the gate terminal of the second transistor 2702 shown in Figure 36. A capacitive element 3801 may be placed between the second terminal and the first terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and impurities may be added as the conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer to form a conductive layer. A wiring layer and a transparent electrode layer may also be used. Note that the configurations in common with those in Figure 36 are the same. The explanation is omitted by using symbols.

[0278] The flip-flop in Figure 39 can perform the same operation as in Figure 36. Figure 39 As shown in Figure 36, the first transistor 2701 may be connected in a diode configuration. The first transistor 2701 is connected by a diode, thereby connecting the first wiring 271 Because the current flowing through 1 becomes smaller, the wiring width of the first wiring 2711 can be reduced. Furthermore, parts that are common to the configuration in Figure 36 are indicated by the same reference numerals, and their explanations are omitted.

[0279] Furthermore, the flip-flop shown in this embodiment is suitable for the shift registers in Figures 17 and 18. It can be used. Similar to Embodiments 1 to 6, a three-phase clock signal is used. This enables power saving. In addition, the shift register of this embodiment is each It is connected to the clock signal lines (third wire 613, fourth wire 614, fifth wire 615). The number of stages in the flip-flop 1701 is 2 / 3 of that when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced. However, the first wiring 611 and the potential supplied to the second wiring 612, the third wiring 613, the fourth wiring 614, and the fifth The signals input to wiring 615 and the sixth wiring 616, and the signal output to wiring 622 are Figures 17 and 18 show flip-flops composed of N-channel transistors, respectively. Compared to when applied to the shift register, the H level and L level are inverted.

[0280] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the installation. Similar to Embodiments 1 to 6, it is integrally formed with the pixel portion. By applying this embodiment to the scan line drive circuit, the lifespan of the display device can be extended. It is possible.

[0281] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0282] (Embodiment 8) In this embodiment, the configuration differs from that of Embodiments 5, 6 and 7. The top flop is shown in Figure 40. Note that this is the same as in Embodiments 5, 6 and 7. Similar items are indicated using a common code, and details of identical or similarly functioning parts are indicated. I will omit the detailed explanation.

[0283] The flip-flop shown in Figure 40 consists of a first transistor 2701 and a second transistor 2 702, the third transistor 2703, the fourth transistor 2704, the fifth transistor Transistor 3205, the 6th transistor 3606, the 7th transistor 3607, the 8th transistor Transistor 3608, the 9th transistor 3609, the 10th transistor 4010, the 11th It has transistor 4011 and transistor 4012. The flop is connected to the first wire 2711, the second wire 2712, the third wire 2713, and the fourth Connect to wiring 2714, the fifth wiring 2715, the sixth wiring 2716, and the seventh wiring 3217. In this embodiment, the 10th transistor 4010, the 11th transistor Transistors 4011 and 4012 are P-channel type transistors, and The absolute value of the voltage between the gate and source (|Vgs|) exceeds the threshold voltage (|Vth|). The circuit will be in a conductive state when (Vgs falls below Vth).

[0284] The first terminal (either the source terminal or the drain terminal) of the first transistor 2701 is the first Connected to wiring 2711, the second terminal (the other of the source and drain terminals) is connected to the second transistor It is connected to the gate terminal of inverter 2702, and the gate terminal is connected to the fifth wiring 2715. The first terminal of the third transistor 2703 is connected to the second wiring 2712, and the second The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 It is connected to 714. The first terminal of the second transistor 2702 is connected to the third wire 2713. The second terminal is connected to the sixth wire 2716. The fourth transistor 27 The first terminal of 04 is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the fourth wire 2714. The fifth transistor 3205 The first terminal is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The gate terminal is connected to the seventh wiring 3217. The sixth transistor 3606 Terminal 1 is connected to the second wire 2712, and terminal 2 is connected to the gateway of the eighth transistor 3608. The gate terminal and the gate terminal of transistor 4011 are connected to the second It is connected to the gate terminal of transistor 2702. The seventh transistor 3607 Terminal 1 is connected to the first wire 2711, and terminal 2 is connected to the gateway of the eighth transistor 3608. The gate terminal and the gate terminal of transistor 4011 are connected to the first It is connected to wiring 2711. The first terminal of the eighth transistor 3608 is connected to the third wiring 2 It is connected to 713, and the second terminal is the gate terminal of the 9th transistor 3609 and the 10th terminal It is connected to the gate terminal of transistor 4010. The first of transistor 3609, the ninth The terminal is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The first terminal of the tenth transistor 4010 is connected to the second wiring 2712, and the second terminal It is connected to the gate terminal of the second transistor 2702. Transistor 4 The first terminal of 011 is connected to the seventh wire 3217, and the second terminal is connected to the twelfth transistor 4 It is connected to the gate terminal of 012. The first terminal of the 12th transistor 4012 is the second The second terminal is connected to the wiring 2712, and the second terminal is connected to the gate terminal of the second transistor 2702. It is done. Furthermore, the second terminal of the 11th transistor 4011 and the 12th transistor The connection point of the gate terminal of 4012 will be node 4024.

[0285] Note that the second terminals of the third transistor 2703 and the fourth transistor 2704 , the second terminal of the fifth transistor 3205, the second terminal of the sixth transistor 3606, the second terminal of the ninth transistor 3609, the second terminal of the tenth transistor 4010, and the second terminal of the twelfth transistor 4012 are not necessarily connected to the second wiring 2712 and may be connected to separate wirings. Also, the gate terminals of the third transistor 2703 and the fourth transistor 2704 are not necessarily connected to the fourth wiring 2714 and may be connected to separate wirings. Also, the first terminals of the first transistor 2 701, the first terminal of the seventh transistor 3607, and the gate terminal of the seventh transistor 36 07 are not necessarily connected to the first wiring 2711 and may be connected to separate wirings . Also, the first terminal of the second transistor 2702 and the first terminal of the eighth transistor 36 08 are not necessarily connected to the third wiring 2713 and may be connected to separate wirings. Also, the gate terminal of the fifth transistor 3205 and the first terminal of the eleventh transistor 4011 are not necessarily connected to the seventh wiring 3217 and may be connected to separate wirings.

[0286] Next, the operation of the flip - flop shown in FIG. 40 will be described with reference to the timing chart of FIG. 41. FIG. 41 is a timing chart when the flip - flop of FIG. 40 is operated in the same manner as the flip - flops shown in FIGS. 27, 32, and 36. Note that the parts common to the timing charts of FIGS. 28, 33, and 37 will be described using common reference numerals and the description thereof will be omitted.

[0287] In Figure 41, potential 4124 is the potential of node 4024 in Figure 40.

[0288] In the flip-flop of Figure 40, the 10th transistor 401 is selected during the third non-selective period. 0 is turned on. Then, node 2721 is turned on via the 10th transistor 4010 Because the potential of wiring 2712 is supplied, the H level can be maintained more stably. Furthermore, In the flip-flop of Figure 40, the 12th transistor 401 occurs during the first non-selective period. 2 turns on. Then node 2721 is turned on via the 12th transistor 4012 Because the potential of wiring 2712 is supplied, the H level can be maintained more stably.

[0289] The on / off control of the 12th transistor 4012 will be explained in detail. The on / off control of transistor 4010 is performed by the ninth transistor shown in Embodiment 7. This is similar to the on / off control of the STA3609. First, the flip-flop in Figure 36 is the same as Thus, the sixth transistor 3606 and the seventh transistor 3607 constitute the inverter. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, Node 2721 is at an H level and node 3622 is at an L level, so the 11th transistor Transistor 4011 turns on. Therefore, the 12th transistor 4012 turns on the 7th wiring 3 Because it is controlled by the signal input to 217, it turns on during the second non-selection period, and the first It is turned off during the non-selection period and the third non-selection period. On the other hand, during the set period and selection period Between them, node 2721 is at an L level and node 3622 is at an H level, so the 11th Transistor 4011 turns off. Therefore, the gate terminal of the 12th transistor 4012 The potential of the child is maintained at the potential of the first nonselective period, which is the period before the set period, i.e., the H level. Therefore, the 12th transistor, 4012, is turned off.

[0290] From the above, the flip-flop in Figure 40 has a first non-selection period, a second non-selection period and During the third non-selective period, V1 is supplied to the sixth wiring 2716 and node 2721. Therefore, malfunctions of the flip-flop can be further suppressed. This is because during the non-selection period In between, V1 can be supplied to the sixth wiring 2716 and node 2721. Furthermore, the flip-flop in Figure 40 has the sixth wiring 2716 and Since V1 is supplied to node 2721, the sixth wiring 2716 and node 2721 It can reduce noise.

[0291] Furthermore, the flip-flop in Figure 40 has a 10th transistor 4010 and an 11th transistor This makes it possible to suppress the characteristic degradation of transistors 4011 and 4012. This is because the tenth transistor 4010 turns on only during the third non-selective period. Furthermore, the 11th transistor 4011 has a first non-selective period, a second non-selective period and During the 3 non-selective period, the potential at node 4024 is V2+ε(ε:|Vth3607|+|V This is because it only turns on during the period when it decreases to th4011|). Also, the 12th transistor This is because ZISTA 4012 is only turned on during the second non-selection period.

[0292] Note that the flip-flop in Figure 40 consists of the first transistor 2701 and the second transistor 2702, the third transistor; 2703, the fourth transistor; 2704, the fifth transistor Transistor 3205, the 6th transistor 3606, the 7th transistor 3607, the 8th transistor Transistor 3608, the 9th transistor 3609, the 10th transistor 4010, the 1st Transistor 1 (4011) and transistor 12 (4012) are both P-channel type transistors. It is characterized by being composed of ZISTA. Therefore, the flip-flop in Figure 40 is Even if polysilicon or single-crystal silicon is used as the semiconductor layer of the transistor, the manufacturing process is simple. It can be simplified.

[0293] Here, the 10th transistor 4010, the 11th transistor 4011 and the 12th transistor The function of transistor 4012 is described. The tenth transistor 4010 is the second It has the function of supplying the potential of wiring 2712 to node 2721, and a switching transistor It functions as follows. The 11th transistor 4011 has a potential of the 7th wiring 3217 at the node. It has the function of supplying power to 4024 and functions as a switching transistor. The transistor 4012 has the function of supplying the potential of the second wiring 2712 to node 2721. It functions as a switching transistor.

[0294] If the operation is the same as in Figure 40, the arrangement and number of transistors will be the same as in Figure 23. It is not limited to transistors, other elements (resistors, capacitors, etc.), You may also add new elements such as diodes, switches, and various logic circuits.

[0295] For example, as shown in Figure 42, the gate terminal of the second transistor 2702 shown in Figure 40. A capacitive element 4201 may be placed between the second terminal and the first terminal. This allows for more stable bootstrap operation during the selection period. This allows for a reduction in the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and the gate electrode layer and impurities may be added as the conductive layer. An added semiconductor layer may be used, or an interlayer film (insulating film) may be used as an insulating layer to form a conductive layer. A wiring layer and a transparent electrode layer may also be used. Note that the configurations in common with those in Figure 40 are the same. The explanation is omitted by using symbols.

[0296] The flip-flop in Figure 43 can perform the same operation as in Figure 40. Figure 43 As shown in Figure 40, the first transistor 2701 may be connected in a diode configuration. The first transistor 2701 is connected by a diode, thereby connecting the first wiring 271 Since the current flowing through 1 will decrease, the wiring width of the first wiring 2711 will be reduced.

[0297] Furthermore, the flip-flop shown in this embodiment is suitable for the shift registers in Figures 17 and 18. It can be used. Similar to Embodiments 1 to 7, a three-phase clock signal is used. This enables power saving. In addition, the shift register of this embodiment is each It is connected to the clock signal lines (third wire 613, fourth wire 614, fifth wire 615). The number of stages in the flip-flop 1701 is 2 / compared to when a single-phase clock signal is used. Since it becomes 3, the load on each clock signal line can be reduced. However, the first wiring The potential supplied to 611 and the second wiring 612, and the third wiring 613 and the fourth wiring 614 The signals input to the fifth wiring 615 and the sixth wiring 616, and the output to wiring 622 The signals are each connected to a flip-flop composed of N-channel transistors, as shown in Figure 17 and Compared to when applied to the shift register in Figure 18, the H level and L level are reversed. .

[0298] Furthermore, the shift register shown in this embodiment is displayed in Figures 9, 11, 12, and 44. It can be applied to the installation. Similar to Embodiments 1 to 7, it is integrally formed with the pixel portion. By applying this embodiment to the scan line drive circuit, the lifespan of the display device can be extended. It is possible.

[0299] Note that the shift registers and flip-flops shown in this embodiment are not included in other embodiments described herein. The configuration of the display device shown in the implementation form can be freely combined and implemented. The configurations of the shift registers and flip-flops shown in the embodiment can be freely combined and implemented. It is possible.

[0300] (Embodiment 9) In this embodiment, an example of a pixel having in the display device shown in Embodiments 1 to 8. This will be explained with reference to Figure 46.

[0301] The pixel configuration of Figure 46 will be explained. The pixel shown in Figure 46(A) is transistor 4601 It has a capacitive element 4602 and a display element 4621. The pixels are connected by a first wiring 4611. It is connected to the second wiring 4612 and the third wiring 4613. Also, the display element 4621 As shown in Figure 46(B), the electric field between the pixel electrode 4623 and the counter electrode 4622 is The case in which the light transmittance changes is used in the liquid crystal element 4631. Wiring 4611 may be called a signal line. Also, the second wiring 4612 may be called a scan line. Also, the third wiring 4613 may be called the holding capacity wire.

[0302] Note that transistor 4601 indicates an N-channel type transistor, but P-channel A transistor of type 1 may also be used. In Embodiments 1 to 4, It is preferable to use an N-channel transistor as the 4601. This is because the transistor Because amorphous silicon can be used as the semiconductor layer of the ZISTA, the manufacturing process This is because it allows for simplification, leading to reduced manufacturing costs and improved yield. Yes. Furthermore, it will also be possible to manufacture semiconductor devices such as large display panels. Furthermore, it is also possible to manufacture transistors using polysilicon or single-crystal silicon as the semiconductor layer. The manufacturing process can be simplified. Also, in Embodiments 5 to 8, It is preferable to use a P-channel type transistor as the ZISTA 4601. This is because, This allows for the simplification of the manufacturing process, leading to reduced manufacturing costs and improved yield. Because it can.

[0303] The first wiring 4611 is for the signals shown in the display devices in Figures 9, 11, 12, and 44. It corresponds to one of the lines S1 to Sm. The second wiring 4612 is shown in Figures 9, 11, and 12. This corresponds to one of the scan lines G1 to Gn shown in the display device in Figure 44.

[0304] Note that the third wiring 4613 is not shown in Figures 9, 11, 12, and 44. As already mentioned, you may add to Figures 9, 11, 12, and 44 as needed.

[0305] Furthermore, the capacitive element 4602 serves to maintain the potential of the pixel electrode 4623 of the display element 4621. Therefore, the capacitive element 4602 is connected to the pixel electrode 4623 and the third wiring 4613. Connected in between, but not limited to, so that the potential of the pixel electrode 4623 can be maintained. It is sufficient that it is positioned and connected to the second wiring 4612 of another pixel (for example, the previous row). Alternatively, it may be connected to the counter electrode 4622 or an electrode equivalent to the counter electrode 4622. Good. Also, if the display element 4621 is capacitive, the capacitive element 4602 and the third distribution Line 4613 is not necessarily required.

[0306] To operate, select the first wire 4611 and turn on transistor 4601. Then, the video signal is input from the first wiring 4611 to the pixel electrode 4623 and the capacitive element 4602. This causes the display element 4621 to have a transmittance corresponding to the video signal.

[0307] Here, we will explain a driving method that can improve the image quality of the display device. Possible drive methods include overdrive drive methods and controlling the common line (holding capacitance line). This document explains the driving methods, backlight scanning, and high-frequency driving methods. The methods of operation can be freely combined and implemented.

[0308] First, let's explain the overdrive drive with reference to Figure 47. Figure 47(A) is a table. This shows the time change in output brightness of the indicator element with respect to the input voltage. The dashed line represents the input. The time change in the output brightness of the display element with respect to voltage 1 is shown as the output brightness 1, also represented by the dashed line. This means that the voltage required to obtain the desired output brightness Low is Vi, but the input voltage and If Vi is input directly, the element's response will take time to reach the desired output brightness Low. It takes time that corresponds to the speed.

[0309] Overdrive is a technique to speed up this response time. Specifically, first, By applying a voltage Vo, which is greater than Vi, to the element for a certain period of time, the response speed of the element can be increased. This method involves bringing the output brightness close to the target low value, and then returning the input voltage to Vi. The input voltage at that time is represented as input voltage 2, and the output brightness is represented as output brightness 2. The graph shows that the time to reach the target brightness level (Low) is shorter than the graph for output brightness level 1. It is.

[0310] Note that in Figure 47(A), the case where the output brightness changes positively with respect to the input voltage is shown. As mentioned above, the present invention also includes cases where the output brightness changes negatively in response to the input voltage.

[0311] Refer to Figures 47(B) and 47(C) for the circuitry used to achieve this type of drive. Let me explain. First, referring to Figure 47(B), the input video signal Gi is an analog value (discrete value) In the case where the signal takes an analog value (or is also acceptable), and the output video signal Go is also a signal that takes an analog value, Let me explain. The overdrive circuit shown in Figure 47(B) is an encoding circuit 4701, Fle It includes a memory 4702, a correction circuit 4703, and a DA conversion circuit 4704.

[0312] The input video signal Gi is first input to the encoding circuit 4701 and encoded. The analog signal is converted to a digital signal with the appropriate number of bits. The barrel signal is input to the frame memory 4702 and the correction circuit 4703, respectively. The correction circuit 4703 receives the video signal of the previous frame that was stored in the frame memory 4702. These are also input simultaneously. Then, in the correction circuit 4703, the video signal of the frame and The video signal from the previous frame is corrected according to a pre-prepared numerical table. The corrected video signal is output. At this time, the output switching signal is input to the correction circuit 4703, and the correction is applied. The video signal may be configured to switch between the output of the previously generated video signal and the video signal of the current frame. The corrected video signal or the video signal of that frame is input to the DA conversion circuit 4704. Then, the corrected video signal or the value according to the video signal of that frame is analyzed. The output video signal Go, which is a log signal, is output. In this way, overdrive is activated. This can be achieved.

[0313] Next, referring to Figure 47(C), the input video signal Gi is a signal that takes a digital value, and the output This section explains the case where the force video signal Go is also a signal that takes a digital value. (See Figure 47(C)) The overdrive circuit includes a frame memory 4712 and a correction circuit 4713.

[0314] The input video signal Gi is a digital signal, and first, the frame memory 4712 and the correction circuit The inputs are sent to 4713 and , respectively. The correction circuit 4713 receives the frame memory 4712. The video signal from the previous frame, which was being held, is also input simultaneously. Then, correction circuit 4713 In this process, the video signal of the current frame and the video signal of the previous frame are used to obtain a pre-prepared result. The corrected video signal is output according to the numerical table. At this time, the correction circuit 47 Inputting an output switching signal to 13 switches between the corrected video signal and the video signal of the current frame. It may also be possible to enable output in this way. In this manner, overdrive can be achieved.

[0315] The combination of numerical tables for obtaining the corrected video signal is obtained in 1SF. It is the product of the number of possible gradations and the number of gradations that can be taken in 2SF. The number of these combinations is The smaller the value, the smaller the amount of data stored in the correction circuit 4713, which is preferable. In this embodiment, the subframe displaying the bright image is used to represent the midtones until the brightness reaches its maximum. In this case, the brightness of the dark image is 0, and the subframe displaying the bright image has the highest brightness. From the highest grayscale level to the highest grayscale level, the brightness of the bright image remains constant, so the number of these combinations can be significantly reduced. It can be made smaller.

[0316] Furthermore, in the present invention, the overdrive circuit is configured such that the input video signal Gi is an analog signal. This also includes the case where the output video signal Go is a digital signal. In this case, as shown in Figure 47(B) The DA conversion circuit 4704 can be omitted from the circuit. Also, in the present invention, the overdrive In the live circuit, the input video signal Gi is a digital signal, and the output video signal Go is an analog signal. This also includes cases where it is a number. In this case, the encoding circuit 4701 is taken from the circuit shown in Figure 47(B). You can omit it.

[0317] Next, the drive mechanism for manipulating the potential of the common wire will be explained with reference to Figure 48. Figure 48(A ) is a display device that uses a display element having capacitive properties such as a liquid crystal element, and the scan line This diagram shows multiple pixel circuits when one common line is assigned to each pixel. The pixel circuit shown in Figure 48(A) consists of transistor 4801, auxiliary capacitor 4802, and display element 4 It is equipped with 803, video signal line 4804, scan line 4805, and common line 4806.

[0318] Note that transistor 4801, auxiliary capacitor 4802, display element 4803, video signal line 480 4. Scan line 4805 and common line 4806 are each connected to transistor 460 shown in Figure 46. 1. Capacitive element 4602, display element 4621, first wiring 4611, second wiring 4612, This corresponds to the third wiring 4613.

[0319] The gate terminal of transistor 4801 is electrically connected to scan line 4805, and the transistor Either the source terminal or the drain terminal of the 4801 is electrically connected to the video signal line 4804. The source terminal or drain terminal of transistor 4801 is connected to the other terminal, and the auxiliary capacitor 48 It is electrically connected to one terminal of 02 and to one terminal of the display element 4803. Furthermore, the other terminal of auxiliary capacitor 4802 is electrically connected to common wire 4806.

[0320] First, the pixel selected by scan line 4805 turns on transistor 4801. Therefore, via the video signal line 4804, the display element 4803 and the auxiliary capacitor 4802 are respectively connected. A voltage corresponding to the video signal is applied. At this time, the video signal is connected to common line 4806. If the lowest grayscale is displayed for all connected pixels, or if common line 4 If it was set to display the highest grayscale for all pixels connected to 806, then the pixels There is no need to write the video signal via the video signal line 4804. Instead of writing the video signal via 4, the display is displayed by changing the potential of common line 4806. The voltage applied to element 4803 can be changed.

[0321] Next, Figure 48(B) shows a display device using a display element with capacitive properties, such as a liquid crystal element. In this configuration, when two common lines are arranged for each scan line, multiple pixel circuits This is a diagram illustrating the above. The pixel circuit shown in Figure 48(B) consists of transistor 4811 and auxiliary capacitor 4 812, display element 4813, video signal line 4814, scan line 4815, first common line 48 16. It is equipped with a second common line, 4817.

[0322] The gate terminal of transistor 4811 is electrically connected to scan line 4815, and the transistor Either the source terminal or the drain terminal of the 4811 is electrically connected to the video signal line 4814. The source terminal or drain terminal of transistor 4811 is connected to the other side of the auxiliary capacitor 48 It is electrically connected to one terminal of 12 and to one terminal of the display element 4813. Furthermore, the other terminal of the auxiliary capacitor 4812 is electrically connected to the first common wire 4816. Furthermore, in the pixel adjacent to the pixel in question, the other terminal of the auxiliary capacitor 4812 is the second It is electrically connected to common line 4817.

[0323] The pixel circuit shown in Figure 48(B) has a small number of pixels electrically connected to a single common line. Therefore, instead of writing the video signal via the video signal line 4814, the first common line 48 By changing the potential of 16 or the second common wire 4817, the electric current applied to the display element 4813 is changed. The frequency with which the pressure can be changed increases significantly. Also, source inversion drive or dot Inverted drive becomes possible. Source inverted drive or dot inverted drive improves the reliability of the element. This can raise the pitch and reduce flicker.

[0324] Next, scanning backlights will be explained with reference to Figure 49. Figure 49(A) shows a cold shade This is a diagram showing a scanning backlight with electrodes placed side by side. The scanning backlight shown in Figure 49(A) The system comprises a diffuser plate 4901 and N cold cathode tubes 4902-1 to 4902-N. N cold cathode tubes 4902-1 to 4902-N are placed side by side behind the diffuser plate 4901. Then, the N cold cathode tubes 4902-1 to 4902-N scan by changing their brightness. It is possible.

[0325] The change in brightness of each cold cathode tube during scanning will be explained using Figure 49(C). First, the cold cathode tube... The brightness of the electrode tube 4902-1 is changed for a certain period of time. Then, the cold cathode tube 4902 The brightness of the cold cathode tube 4902-2, which is placed next to -1, is changed for the same amount of time. The brightness is sequentially changed from cold cathode tube 4902-1 to 4902-N. (See Figure 4) In 9(C), the brightness that is changed for a certain period of time is set to be smaller than the original brightness, The brightness may be greater than that. Also, scan from cold cathode tube 4902-1 to 4902-N. However, scanning in the reverse direction from cold cathode tube 4902-N to 4902-1 is also possible.

[0326] Note that the backlight brightness during periods of low brightness is the highest brightness of the subframe into which the dark image is inserted. It is preferable to set it to approximately the same degree. Specifically, when inserting a dark image into 1SF, use 1S When inserting a dark image into 2SF, the maximum brightness Lmax of F is 1. 2. is preferable.

[0327] Furthermore, LEDs may be used as the light source for the scanning backlight. The light will look like Figure 49(B). The scanning backlight shown in Figure 49(B) is It comprises a diffuser plate 4911 and light sources 4912-1 to 4912-N, which are LEDs arranged side by side. When using LEDs as the light source for a scanning backlight, the backlight can be made thinner and lighter. It has the advantage of being able to widen the color reproduction range. Furthermore, LE Similarly, the LEDs placed alongside light sources 4912-1 to 4912-N, each with D placed next to it, are also treated the same way. Since it can scan, it can also be used as a point-scanning type backlight. This will further improve the image quality of the video.

[0328] Next, high-frequency driving will be explained with reference to Figure 50. Figure 50(A) shows the frame frequency. This diagram shows the process when a dark image is inserted and the device is driven at 60Hz. 5001 is the frame. 5002 is the bright image of the current frame, 5003 is the bright image of the next frame, 500 4 is the dark image of the next frame. When driven at 60Hz, the frame rate of the video signal This has the advantage of being easy to maintain consistency with and keeping the image processing circuit simple.

[0329] Figure 50(B) shows the result when a dark image is inserted and the system is driven at a frame frequency of 90Hz. 5011 is the bright image of the frame, 5012 is the dark image of the frame, and 5013 This is a bright image of the first image created from the current frame, the next frame, and the frame after that, 5014 This is a dark image of the first image created from the current frame, the next frame, and the frame after that, 5015 This is a bright image of the second image created from the current frame, the next frame, and the frame after that, 5016 This is a dark image of the second image created from the current frame, the next frame, and the frame after that. 9 When driving at 0Hz, the operating frequency of the peripheral drive circuit does not need to be increased significantly, thus achieving effectiveness. This has the advantage of ultimately improving the image quality of moving images.

[0330] Figure 50(C) shows the results when a dark image is inserted and the system is driven at a frame frequency of 120 Hz. This is a diagram. 5021 is the bright image of the frame, 5022 is the dark image of the frame, and 502 3 is the bright image created from the current frame and the next frame, 5024 is the current frame and the next Dark image created from the frame, 5025 is the bright image of the next frame, 5026 is the next frame Dark image of frame, 5027 is the bright image of the image created from the next frame and the frame after that, 502 Image 8 is a dark image created from the next frame and the frame after that. It runs at 120Hz. In this case, the image quality improvement effect on moving images is remarkable, and there is the advantage of hardly noticing any afterimages. be.

[0331] Figures 51 to 55 show the top view and cross-sectional view of the pixel shown in Figure 46. The LCDs have different operating modes.

[0332] First, Figure 51 shows the pixel structure of a liquid crystal display device, specifically the TN method, which uses a thin-film transistor. Figure 51(A) shows a cross-sectional view and a top view of a pixel when a rangefinder (TFT) is combined. Figure 51(A) is a cross-sectional view of a pixel, and Figure 51(B) is a top view of a pixel. The cross-sectional view of the pixel corresponds to the line segment a-a' in the top view of the pixel shown in Figure 51(B). By applying the present invention to a liquid crystal display device with the pixel structure shown in Figure 51, it is possible to produce liquid crystals at low cost. Display devices can be manufactured.

[0333] The pixel structure of a TN type liquid crystal display device will be described with reference to Figure 51(A). The display device has a core component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers, and liquid crystal is placed between the two substrates. It is manufactured by injecting material. In Figure 51(A), the two substrates are formed by the first substrate 5 These are substrate 101 and the second substrate 5116. The first substrate is used to create the TFT and pixel electrodes. The second substrate is made of a light-shielding film 5114, a color filter 5115, and a fourth conductive film. A layer 5113, a spacer 5117, and a second alignment film 5112 may be fabricated.

[0334] Furthermore, the present invention can be implemented even without fabricating a TFT on the first substrate 5101. If the present invention is implemented without producing the original part, the number of steps will be reduced, thereby lowering the manufacturing cost. This can be done. Furthermore, because the structure is simple, the yield can be improved. On the other hand, When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0335] Note that the TFT shown in Figure 51 is a bottom-gate type TFT using an amorphous semiconductor, It has the advantage of being able to be manufactured inexpensively using a substrate of a certain area. However, the present invention is not limited to this. It is not something that can be done. The usable TFT structure is a bottom-gate type TFT with a channel There are etch-type and channel-protected types. Top-gate type is also acceptable. Furthermore, amorphous materials are also available. Not only semiconductors, but also polycrystalline semiconductors can be used.

[0336] Furthermore, the present invention can be implemented even without fabricating a light-shielding film 5114 on the second substrate 5116. If the present invention is carried out without producing the light-shielding film 5114, the number of steps will be reduced, thus reducing the manufacturing cost. It can reduce waste. Also, because of its simple structure, it can improve yield. This is possible. On the other hand, when the light-shielding film 5114 is manufactured and the present invention is carried out, light leakage occurs when black is displayed. A display device with fewer components can be obtained.

[0337] Furthermore, the present invention can be implemented without fabricating a color filter 5115 on the second substrate 5116. It is possible. If the present invention is carried out without manufacturing the color filter 5115, the number of steps will be Because it decreases, manufacturing costs can be reduced. Also, because the structure is simple, the yield This can improve the quality. On the other hand, the present invention can be realized by manufacturing a color filter 5115. If implemented, a display device capable of displaying in color can be obtained.

[0338] Furthermore, in this invention, a spacer 5117 is not fabricated on the second substrate 5116, and a spherical spacer is used. It can also be implemented by scattering. The present invention can be implemented by scattering spherical spacers. Because the number of steps is reduced, manufacturing costs can be lowered. Also, the structure is simple. Therefore, the yield can be improved. On the other hand, spacer 5117 is manufactured and the main When performing the installation, the position of the spacers does not vary, so the distance between the two circuit boards is uniform. This makes it possible to obtain a display device with less display unevenness.

[0339] Next, the processing applied to the first substrate 5101 will be described. The first substrate 5101 has light-transmitting properties. A suitable substrate is one that has the properties of a quartz substrate, glass substrate, or plastic substrate. The first substrate 5101 may be a light-shielding substrate, such as a semiconductor substrate or SOI (Silicone). An on-in-sulator board is also acceptable.

[0340] First, a first insulating film 5102 may be formed on the first substrate 5101. 02 is a silicon oxide film, silicon nitride film, or silicon oxynitride film (SiOxNy), etc. It may also be an insulating film. Alternatively, a laminate of at least two of these films. A structural insulating film may be used. When carrying out the present invention by forming the first insulating film 5102: This prevents impurities from the substrate from affecting the semiconductor layer and altering the properties of the TFT. Therefore, a highly reliable display device can be obtained. If the present invention is carried out without forming film 02, the number of steps is reduced, thereby lowering manufacturing costs. It is possible to do so. Furthermore, because the structure is simple, it can improve yield.

[0341] Next, a first conductive layer 5103 is formed on the first substrate 5101 or the first insulating film 5102. The first conductive layer 5103 may be formed by processing its shape. The process is preferably as follows: First, the entire surface of the first conductive layer 5103 The film is then deposited. At this time, a film deposition apparatus such as a sputtering apparatus or a CVD apparatus may be used. Next, a photosensitive resist material is formed over the entire surface of the first conductive layer 5103 that has been deposited over the entire surface. Next, using photolithography or laser direct writing, the desired shape is formed. Next, expose the resist material to light. Then, the exposed resist material, or the unexposed material, By removing one of the resist materials by etching, the first conductive material is obtained. A mask can be obtained for shaping layer 5103. After that, the formed mask part Following the turn, the first conductive layer 5103 is removed by etching, thereby creating the desired pattern. The first conductive layer 5103 can be shaped into the surface. There are two methods for etching: chemical methods (wet etching) and physical methods (d There is a lye etching process, but the material of the first conductive layer 5103 and the material under the first conductive layer 5103 The appropriate material will be selected considering the properties of the materials in the layer. Suitable materials include Mo, Ti, Al, Nd, and Cr. Alternatively, a laminated structure of these materials is also possible. These alloys may also be used as a single layer or a laminated structure for the first conductive layer 51. It may be formed as 03.

[0342] Next, a second insulating film 5104 is formed. At this time, a sputtering apparatus or a CVD apparatus is used. Any film deposition apparatus may be used. The material used for the second insulating film 5104 is a thermal oxide film. Suitable examples include silicon oxide films, silicon nitride films, or silicon oxynitride films. These stacked structures may also be used. Note that the second portion in contact with the first semiconductor layer 5105 The insulating film 5104 is particularly preferably a silicon oxide film. This is because using a film-like structure reduces the number of trap levels at the interface with the semiconductor layer 5105. Furthermore, when the first conductive layer 5103 is formed of Mo, the first conductive layer 5103 is in contact with The second insulating film 5104 of the portion is preferably a silicon nitride film. This is because it does not oxidize oxygen.

[0343] Next, the first semiconductor layer 5105 is formed. Then, the second semiconductor layer 5106 is formed in succession. It is preferable to form the first semiconductor layer 5105 and the second semiconductor layer 5106 The shape may be formed by processing. The method of processing the shape is the photolithography described above. Methods such as the i method are preferred. The material used for the first semiconductor layer 5105 is Silicon or silicon germanium (SiGe) is preferred. Also, the second half Suitable materials for the conductive layer 5106 include silicon containing phosphorus, etc.

[0344] Next, a second conductive layer 5107 is formed. At this time, sputtering or printing is used. This is preferable. Furthermore, the material used for the second conductive layer 5107 may be transparent, It may be reflective. If it is transparent, for example, indium oxide and tin oxide Indium tin oxide (ITO) film mixed with silicon oxide, indium tin oxide (ITO) Indium tin silicon oxide (ITSO) film mixed with element, indium oxide mixed with zinc oxide Indium zinc oxide (IZO) film, zinc oxide film, or tin oxide film can be used. It can be done. Note that IZO is a mixture of ITO with 2-20 wt% zinc oxide (ZnO). It is a transparent conductive material formed by sputtering using a GET. On the other hand, reflectivity If available, Ti, Mo, Ta, Cr, W, Al, etc. can be used. Also, T A two-layer structure made by stacking i, Mo, Ta, Cr, W and Al, with Al replaced by Ti, Mo, Ta, Cr Alternatively, a three-layer laminated structure sandwiched between metals such as W may be used. Furthermore, the second conductive layer 5107 is shaped The shape may be formed by processing. Methods for processing the shape include the photolithography method described above. The method is preferable. The etching method is preferably dry etching. Dry etching is preferred. Dry etching is ECR (Electron Cyclotron R esonance and ICP (Inductive Coupled Plasma) This may be carried out using any dry etching apparatus with a high-density plasma source.

[0345] Next, the channel region of the TFT is formed. At this time, the second conductive layer 5107 is used as a mask. Then, etching of the second semiconductor layer 5106 may be performed. In this way, the mask Since the number can be reduced, manufacturing costs can be lowered. The second conductive By etching the semiconductor layer 5106, the removed portion becomes the channel region of the TFT. This is the result. Furthermore, instead of forming the first semiconductor layer 5105 and the second semiconductor layer 5106 consecutively, After the formation of the first semiconductor layer 5105, a stopper is placed in the area that will become the channel region of the TFT. A film may be formed and patterned, and then a second semiconductor layer 5106 may be formed. By doing this, the TFT channel can be analyzed without using the second conductive layer 5107 as a mask. Because it allows for the formation of specific areas, it offers the advantage of greater flexibility in layout patterns. Furthermore, during etching of the second semiconductor layer 5106, etching also occurs up to the first semiconductor layer 5105. To prevent etching defects, the channel region of the TFT is reliably etched without causing any problems. This has the advantage of being able to form.

[0346] Next, a third insulating film 5108 is formed. The third insulating film 5108 is transparent. It is preferable that the material used for the third insulating film 5108 be an inorganic material (silicone oxide). (e.g., silicon nitride, silicon oxide nitride) or low dielectric constant organic compound materials (photosensitive Alternatively, non-photosensitive organic resin materials are preferred. Furthermore, materials containing siloxane are also used. That's also good. Siloxanes have a skeletal structure formed by the bonding of silicon (Si) and oxygen (O). It is a material. As a substituent, it is an organic group containing at least hydrogen (e.g., alkyl group, aromatic carbon Hydrogenated hydrogen is used. A fluoro group may be used as a substituent. Alternatively, At least an organic group containing hydrogen and a fluoro group may be used. The third insulating film 5108 is A laminated structure is also acceptable. Furthermore, the third insulating film 5108 may be formed by processing its shape. The preferred method for processing the shape is the photolithography method described above. At the same time, the second insulating film 5104 is also etched, thereby creating the third insulating film 5108 Furthermore, it is possible to form contact holes with the first conductive layer 5103. The surface of the third insulating film 5108 is preferably as flat as possible. This is because the orientation of the liquid crystal molecules is affected by the unevenness of the surface they come into contact with.

[0347] Next, a third conductive layer 5109 is formed. At this time, sputtering or printing is used. The following is preferable. The material used for the third conductive layer 5109 is the same as that used for the second conductive layer 5107. Similarly, it may be transparent or reflective. The material that can be used as 9 may be the same as that of the second conductive layer 5107. Also, the third conductive layer 5109 may be formed by processing its shape. A method for processing the shape is the second conductive layer 51 It can be the same as 07.

[0348] Next, the first orientation film 5110 is formed. The orientation film 5110 is made of a polymer such as polyimide. A film can be used. After forming the first alignment film 5110, the orientation of the liquid crystal molecules can be controlled. To achieve this, rubbing may be performed. Rubbing is done by rubbing the orientation film with a cloth. This is a process of creating grooves in the orientation film. By performing rubbing, the orientation film is given orientation. It can be held.

[0349] The first substrate 5101, light-shielding film 5114, and color filter 511 were fabricated as described above. 5. A fourth conductive layer 5113, a spacer 5117, and a second alignment film 5112 were fabricated. The second substrate 5116 is bonded to the second substrate 5116 with a gap of several μm using a sealing material, and two pieces are bonded together. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. As shown in Figure 51... In a TN-type liquid crystal panel, the fourth conductive layer 5113 is located on the second substrate 5116. It may be made to cover the entire surface.

[0350] Next, we will explain the characteristics of the pixel structure of a TN-type liquid crystal panel, as shown in Figure 51. Figure 51 The liquid crystal molecule 5118 shown in (A) is an elongated molecule with a long axis and a short axis. Liquid crystal molecule 5 In Figure 51(A), the orientation of 118 is represented by its length. In other words, the elongated liquid crystal molecule 5118 has its long axis oriented parallel to the plane of the paper, and the short The more liquid crystal molecules represented, the closer the orientation of their major axes is to the normal direction of the paper. In other words, the liquid crystal molecule 5118 shown in Figure 51(A) is close to the first substrate 5101. The orientation of the long axis of the second substrate, closer to the 5116, is 90 degrees different. The orientation of the long axis of liquid crystal molecule 5118, which is located in the middle of these, smoothly connects them. This is the orientation. That is, the liquid crystal molecule 5118 shown in Figure 51(A) is on the first substrate 5101 Between the first substrate and the second substrate 5116, the orientation is such that it is twisted 90 degrees.

[0351] Next, referring to Figure 51(B), the image shows the result when the present invention is applied to a TN type liquid crystal display device. An example of a basic layout will be described. The image of a TN-type liquid crystal display device to which the present invention is applied. The components are scan line 5121, video signal line 5122, capacitance line 5123, and TFT 5124. It may also include a pixel electrode 5125 and a pixel capacitance 5126.

[0352] Since scan line 5121 is electrically connected to the gate terminal of TFT5124, the first conductive It is preferable that it is composed of layer 5103.

[0353] The video signal line 5122 is electrically connected to the source or drain terminal of the TFT5124. Therefore, it is preferable that it be composed of a second conductive layer 5107. Also, scan line 51 Since lines 21 and video signal lines 5122 are arranged in a matrix, at least on different layers It is preferable that it be formed with a conductive layer.

[0354] The capacitance line 5123 is arranged parallel to the pixel electrode 5125, thereby forming the pixel capacitance 5126. This is a wiring for achieving the desired result, and it is preferable that it is composed of a first conductive layer 5103. As shown in Figure 51(B), the capacitance line 5123 runs along the video signal line 5122, and the video signal It may be extended to surround line 5122. In this way, video signal line 5122 The phenomenon in which the potential of an electrode that should maintain its potential changes in response to a change in the potential of another electrode, known as a chromosome change. Lost talk can be reduced. Furthermore, the crossover capacitance with the video signal line 5122 can be reduced. Therefore, as shown in Figure 51(B), the first semiconductor layer 5105 is connected to the capacitance line 5123 and the video signal It may be installed in the intersection area of ​​Route 5122.

[0355] The TFT5124 acts as a switch that connects the video signal line 5122 and the pixel electrode 5125. It works. Note that, as shown in Figure 51(B), the source area or drain area of ​​the TFT5124 Even if you arrange one of the drain regions to surround the other of the source or drain region Good. This way, a large channel width can be obtained in a small area, and switching The capacity can be greatly increased. Furthermore, as shown in Figure 51(B), the TFT5124's The terminals may be arranged so as to surround the first semiconductor layer 5105.

[0356] The pixel electrode 5125 is electrically connected to either the source terminal or the drain terminal of the TFT5124. The pixel electrode 5125 receives the signal voltage transmitted by the video signal line 5122. These are electrodes for applying to the crystal element. Furthermore, capacitance lines 5123 and pixel capacitance 5126 are formed. This is also good. This way, the signal voltage transmitted by the video signal line 5122 is retained. It can also have a ratio. Note that the pixel electrode 5125 is rectangular, as shown in Figure 51(B). This is also acceptable. By doing so, the aperture ratio of the pixels can be increased, so the liquid crystal surface The efficiency of the display device is improved. Also, if the pixel electrode 5125 is made of a transparent material... This allows for the creation of a transmissive liquid crystal display. Transmissive liquid crystal displays have high color reproduction capabilities. It can display images with high resolution and high image quality. In addition, the pixel electrode 5125 reflects When made from a material with certain properties, a reflective liquid crystal display device can be obtained. The crystal display device offers high visibility in bright environments such as outdoors, and also has no backlight. Therefore, power consumption can be made very small. Furthermore, the pixel electrode 5125 is transparent. When created using both properties and reflectivity, the advantages of both can be combined. A semi-transmissive liquid crystal display device can be obtained. Furthermore, the pixel electrode 5125 is reflective. If the material is made of a material having this property, the surface of the pixel electrode 5125 may be made uneven. This results in diffuse reflection of the reflected light, which has the advantage of reducing the angular dependence of the intensity distribution of the reflected light. Yes, it is possible to obtain a reflective liquid crystal display that has a constant brightness regardless of the viewing angle. It is possible.

[0357] Next, referring to Figure 52, we see the liquid crystal in VA (Vertical Alignment) mode. The present invention will now be described in relation to a display device. Figure 52 shows a liquid crystal display device in VA mode. By using orientation-controlling protrusions within the pixel structure, the liquid crystal molecules can be controlled to have various orientations. This controls and widens the field of view, a so-called MVA (Multi-domain Vertical) When the present invention is applied to the (al Alignment) method, the cross-sectional view and top view of the pixels are shown. Yes. Figure 52(A) is a cross-sectional view of a pixel, and Figure 52(B) is a top view of a pixel. Furthermore, the cross-sectional view of the pixel shown in Figure 52(A) is the same as the line segment in the top view of the pixel shown in Figure 52(B). This corresponds to a-a'. The present invention is applied to a liquid crystal display device with the pixel structure shown in Figure 52. This results in a liquid crystal display with a wide viewing angle, fast response time, and high contrast. It is possible.

[0358] The pixel structure of an MVA-type liquid crystal display device will be described with reference to Figure 52(A). A display device has a core component called a liquid crystal panel that displays images. The liquid crystal panel is, Two processed substrates are bonded together with a gap of several micrometers, and liquid is applied between the two substrates. It is fabricated by injecting crystalline material. In Figure 52(A), the two substrates are the first substrate The first substrate is 5201, and the second substrate is 5216. The first substrate has a TFT and pixel electrodes. The second substrate is fabricated with a light-shielding film 5214, a color filter 5215, and a fourth guide Electrode layer 5213, spacer 5217, second alignment layer 5212, and orientation control protrusions 521 You may create 9.

[0359] Furthermore, the present invention can be implemented even without fabricating a TFT on the first substrate 5201. If the present invention is implemented without producing the original part, the number of steps will be reduced, thereby lowering the manufacturing cost. This can be done. Furthermore, because the structure is simple, the yield can be improved. On the other hand, When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0360] Note that the TFT shown in Figure 52 is a bottom-gate type TFT using an amorphous semiconductor, It has the advantage of being able to be manufactured inexpensively using a substrate of a certain area. However, the present invention is not limited to this. It is not something that can be done. The usable TFT structure is a bottom-gate type TFT with a channel There are etch-type and channel-protected types. Top-gate type is also acceptable. Furthermore, amorphous materials are also available. Not only semiconductors, but also polycrystalline semiconductors can be used.

[0361] Furthermore, the present invention can be implemented even without fabricating a light-shielding film 5214 on the second substrate 5216. If the present invention is carried out without producing the light-shielding film 5214, the number of steps will be reduced, thus reducing the manufacturing cost. It can reduce waste. Also, because of its simple structure, it can improve yield. This is possible. On the other hand, when the light-shielding film 5214 is manufactured and the present invention is implemented, light leakage occurs when black is displayed. A display device with fewer components can be obtained.

[0362] Furthermore, the present invention can be implemented even without fabricating a color filter 5215 on the second substrate 5216. It is possible. If the present invention is carried out without manufacturing the color filter 5215, the number of steps will be Because it decreases, manufacturing costs can be reduced. Also, because the structure is simple, the yield This can improve the quality. On the other hand, the present invention can be realized by manufacturing a color filter 5215. If implemented, a display device capable of displaying in color can be obtained.

[0363] Furthermore, in this invention, a spacer 5217 is not fabricated on the second substrate 5216, and a spherical spacer is used. It can also be implemented by scattering. The present invention can be implemented by scattering spherical spacers. Because the number of steps is reduced, manufacturing costs can be lowered. Also, the structure is simple. Therefore, the yield can be improved. On the other hand, spacer 5217 is manufactured and the main When performing the installation, the position of the spacers does not vary, so the distance between the two circuit boards is uniform. This makes it possible to obtain a display device with less display unevenness.

[0364] Next, the processing to be performed on the first substrate 5201 may be done using the method described in Figure 51. Therefore, it is omitted. Here, the first substrate 5201, the first insulating film 5202, and the first conductive layer 5 203, second insulating film 5204, first semiconductor layer 5205, second semiconductor layer 5206, The second conductive layer 5207, the third insulating film 5208, the third conductive layer 5209, and the first alignment film 52 10 are the first substrate 5101, the first insulating film 5102, and the first in Figure 51, respectively. Conductive layer 5103, second insulating film 5104, first semiconductor layer 5105, second semiconductor layer 51 06, second conductive layer 5107, third insulating film 5108, third conductive layer 5109, first This corresponds to the orientation film 5110. Although not shown in the diagram, there are also orientation control protrusions on the first substrate side. This may be provided. By doing so, the orientation of liquid crystal molecules can be controlled more reliably. Furthermore, the first alignment film 5210 and the second alignment film 5212 may also be vertical alignment films. This allows the liquid crystal molecules 5218 to be oriented vertically.

[0365] The first substrate 5201, light-shielding film 5214, and color filter 521 were fabricated as described above. 5. A fourth conductive layer 5213, a spacer 5217, and a second alignment film 5212 were fabricated. The second substrate 5216 is bonded to the second substrate 5216 with a gap of several μm using a sealing material, and two pieces are bonded together. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. As shown in Figure 52... In the MVA type liquid crystal panel, the fourth conductive layer 5213 is located on the second substrate 5216 They may be fabricated over the entire surface. Also, in contact with the fourth conductive layer 5213, orientation control protrusions may be provided. 5219 may be manufactured. Note that there are no limitations on the shape of the orientation control projection 5219, but it should not be slippery. A shape with a curved surface is preferable. This allows adjacent liquid crystal molecules 521 Since the orientation of 8 becomes very close, orientation defects are reduced. Also, the second orientation film 5212 Furthermore, defects in the alignment film can occur due to step breakage caused by the orientation control protrusions 5219. It can be reduced.

[0366] Next, we will explain the characteristics of the pixel structure of the MVA type liquid crystal panel, as shown in Figure 52. Figure 5 The liquid crystal molecule 5218 shown in 2(A) is an elongated molecule with a long axis and a short axis. In order to indicate the orientation of child 5218, in Figure 52(A), it is represented by its length. In other words, the elongated liquid crystal molecule 5218 has its long axis oriented parallel to the plane of the paper. The shorter the liquid crystal molecule represented, the closer the orientation of its long axis is to the normal direction of the paper. Let's assume that... In other words, the liquid crystal molecule 5218 shown in Figure 52(A) has its major axis oriented in a certain way. It is oriented to face the direction normal to the target film. Therefore, the portion with the orientation control protrusion 5219 The liquid crystal molecules 5218 are oriented radially around the orientation control protrusions 5219. By adopting this configuration, a liquid crystal display device with a wide viewing angle can be obtained.

[0367] Next, referring to Figure 52(B), when the present invention is applied to an MVA type liquid crystal display device... Next, an example of pixel layout will be described. An MVA-type liquid crystal display device to which the present invention is applied. The pixels are connected by scan line 5221, video signal line 5222, capacitance line 5223, and TFT 52 It comprises 24, a pixel electrode 5225, a pixel capacitance 5226, and an alignment control protrusion 5219. It's fine if you do that.

[0368] Since scan line 5221 is electrically connected to the gate terminal of TFT5224, the first conductive It is preferable that it is composed of layer 5203.

[0369] The video signal line 5222 is electrically connected to the source or drain terminal of the TFT5224. Therefore, it is preferable that it be composed of a second conductive layer 5207. Also, scan line 52 Since lines 21 and video signal line 5222 are arranged in a matrix, at least on different layers It is preferable that it be formed with a conductive layer.

[0370] The capacitance line 5223 is arranged parallel to the pixel electrode 5225, thereby forming the pixel capacitance 5226. This is a wiring for achieving the desired result, and it is preferable that it is composed of a first conductive layer 5203. As shown in Figure 52(B), the capacitance line 5223 runs along the video signal line 5222, and the video signal It may be extended to surround line 5222. In this way, video signal line 5222 The phenomenon in which the potential of an electrode that should maintain its potential changes in response to a change in the potential of another electrode, known as a chromosome change. Lost talk can be reduced. Furthermore, the crossover capacitance with video signal line 5222 can be reduced. Therefore, as shown in Figure 52(B), the first semiconductor layer 5205 is connected to the capacitance line 5223 and the video signal It may be installed in the intersection area of ​​Route 5222.

[0371] The TFT5224 acts as a switch that conducts the video signal line 5222 and the pixel electrode 5225. It works. Note that, as shown in Figure 52(B), the source area or drain area of ​​the TFT5224 Even if you arrange one of the drain regions to surround the other of the source or drain region Good. This way, a large channel width can be obtained in a small area, and switching The capacity can be greatly increased. Furthermore, as shown in Figure 52(B), the TFT5224's performance... The terminals may be arranged so as to surround the first semiconductor layer 5205.

[0372] The pixel electrode 5225 is electrically connected to either the source terminal or the drain terminal of the TFT5224. The pixel electrode 5225 receives the signal voltage transmitted by the video signal line 5222. These are electrodes for applying to the crystal element. Furthermore, capacitance lines 5223 and pixel capacitance 5226 are formed. This is also good. This way, the signal voltage transmitted by the video signal line 5222 is retained. It can also have a ratio. Note that the pixel electrode 5225 is rectangular, as shown in Figure 52(B). This is also acceptable. By doing so, the aperture ratio of the pixels can be increased, so the liquid crystal surface The efficiency of the display device is improved. Also, if the pixel electrode 5225 is made of a transparent material... This allows for the creation of a transmissive liquid crystal display. Transmissive liquid crystal displays have high color reproduction capabilities. It can display images with high resolution and high image quality. In addition, the pixel electrode 5225 reflects When made from a material with certain properties, a reflective liquid crystal display device can be obtained. The crystal display device offers high visibility in bright environments such as outdoors, and also has no backlight. Therefore, power consumption can be made very small. Furthermore, the pixel electrode 5225 is transparent. When created using both properties and reflectivity, the advantages of both can be combined. A semi-transmissive liquid crystal display device can be obtained. Furthermore, the pixel electrode 5225 is reflective. If the material is made of a material having this property, the surface of the pixel electrode 5225 may be made uneven. This results in diffuse reflection of the reflected light, which has the advantage of reducing the angular dependence of the intensity distribution of the reflected light. Yes, it is possible to obtain a reflective liquid crystal display that has a constant brightness regardless of the viewing angle. It is possible.

[0373] Next, referring to Figure 53, we see the liquid crystal in VA (Vertical Alignment) mode. Another example of applying the present invention to a display device will be described. Figure 53 shows a liquid crystal in VA mode. In the pixel structure of the display device, the fourth conductive layer 5313 is patterned, thereby reducing the liquid crystal component. This is a so-called PVA (Pattern View) that controls the child to have various orientations and widens the field of view. When the present invention is applied to the (Ned Vertical Alignment) method, the image These are the basic cross-sectional view and top view. Figure 53(A) is a cross-sectional view of a pixel, and Figure 53(B) is a picture This is a top view of the basic structure. Also, the cross-sectional view of the pixel shown in Figure 53(A) is the same as the pixel shown in Figure 53(B). This corresponds to the line segment a-a' in the top view. In the liquid crystal display device with the pixel structure shown in Figure 53... By applying the present invention, a wide viewing angle, fast response speed, and high contrast can be achieved. A liquid crystal display device can be obtained.

[0374] The pixel structure of a PVA-type liquid crystal display device will be described with reference to Figure 53(A). A display device has a core component called a liquid crystal panel that displays images. The liquid crystal panel is, Two processed substrates are bonded together with a gap of several micrometers, and liquid is applied between the two substrates. It is fabricated by injecting a crystalline material. In Figure 53(A), the two substrates are the first substrate The first substrate is 5301, and the second substrate is 5316. The first substrate has a TFT and pixel electrodes. The second substrate is fabricated and also contains a light-shielding film 5314, a color filter 5315, and a fourth guide A voltage layer 5313, a spacer 5317, and a second alignment film 5312 may be fabricated.

[0375] Furthermore, the present invention can be implemented even without fabricating a TFT on the first substrate 5301. If the present invention is implemented without producing the original part, the number of steps will be reduced, thereby lowering the manufacturing cost. This can be done. Furthermore, because the structure is simple, the yield can be improved. On the other hand, When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0376] Note that the TFT shown in Figure 53 is a bottom-gate type TFT using an amorphous semiconductor, It has the advantage of being able to be manufactured inexpensively using a substrate of a certain area. However, the present invention is not limited to this. It is not something that can be done. The usable TFT structure is a bottom-gate type TFT with a channel There are etch-type and channel-protected types. Top-gate type is also acceptable. Furthermore, amorphous materials are also available. Not only semiconductors, but also polycrystalline semiconductors can be used.

[0377] Furthermore, the present invention can be implemented even without fabricating a light-shielding film 5314 on the second substrate 5316. If the present invention is carried out without producing the light-shielding film 5314, the number of steps will be reduced, thus reducing the manufacturing cost. It can reduce waste. Also, because of its simple structure, it can improve yield. This is possible. On the other hand, when the light-shielding film 5314 is manufactured and the present invention is carried out, light leakage occurs when black is displayed. A display device with fewer components can be obtained.

[0378] Furthermore, the present invention can be implemented even without fabricating a color filter 5315 on the second substrate 5316. It is possible. If the present invention is carried out without manufacturing the color filter 5315, the number of steps will be Because it decreases, manufacturing costs can be reduced. Also, because the structure is simple, the yield This can improve the quality. On the other hand, the present invention can be realized by manufacturing a color filter 5315. If implemented, a display device capable of displaying in color can be obtained.

[0379] Furthermore, in this invention, a spacer 5317 is not fabricated on the second substrate 5316, and a spherical spacer is used. It can also be implemented by scattering. The present invention can be implemented by scattering spherical spacers. Because the number of steps is reduced, manufacturing costs can be lowered. Also, the structure is simple. Therefore, the yield can be improved. On the other hand, spacer 5317 is manufactured and the main When performing the installation, the position of the spacers does not vary, so the distance between the two circuit boards is uniform. This makes it possible to obtain a display device with less display unevenness.

[0380] Next, the processing to be performed on the first substrate 5301 may be done using the method described in Figure 51. Therefore, it is omitted. Here, the first substrate 5301, the first insulating film 5302, and the first conductive layer 5 303, second insulating film 5304, first semiconductor layer 5305, second semiconductor layer 5306, The second conductive layer 5307, the third insulating film 5308, the third conductive layer 5309, and the first alignment film 53 10 are the first substrate 5101, the first insulating film 5102, and the first in Figure 51, respectively. Conductive layer 5103, second insulating film 5104, first semiconductor layer 5105, second semiconductor layer 51 06, second conductive layer 5107, third insulating film 5108, third conductive layer 5109, first This corresponds to the conductive film 5110. Furthermore, the third conductive layer 5309 on the first substrate 5301 side is electrically charged. A polar notch may be provided. This allows for more reliable control of the orientation of liquid crystal molecules. This is possible. In addition, the first alignment film 5310 and the second alignment film 5312 are vertical alignment films. This is also good. By doing so, the liquid crystal molecules 5318 can be oriented vertically.

[0381] The first substrate 5301, light-shielding film 5314, and color filter 531 were fabricated as described above. 5. A fourth conductive layer 5313, a spacer 5317, and a second alignment film 5312 were fabricated. The second substrate 5316 is bonded to the second substrate 5316 with a gap of several μm using a sealing material, and two pieces are bonded together. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. As shown in Figure 53... In a PVA-type liquid crystal panel, the fourth conductive layer 5313 is patterned. The electrode notch 5319 may be fabricated. There are no limitations, but a shape that combines multiple rectangles with different orientations is preferable. This allows for the formation of multiple regions with different orientations, resulting in a liquid crystal display with a wide viewing angle. The device can be obtained. Also, the boundary between the electrode notch 5319 and the fourth conductive layer 5313 The shape of the fourth conductive layer 5313 in this is preferably a smooth curve. This results in the orientation of adjacent liquid crystal molecules 5318 being very close, thus reducing orientation defects. Furthermore, the second alignment film 5312 undergoes a step break due to the electrode notch 5319. This also reduces defects in the alignment film caused by the storage process.

[0382] Next, we will explain the characteristics of the pixel structure of the PVA-type liquid crystal panel, as shown in Figure 53. Figure 5 Liquid crystal molecule 5318, shown in 3(A), is an elongated molecule with a long axis and a short axis. In Figure 53(A), the orientation of 5318 is represented by its length. In other words, the elongated liquid crystal molecule 5318 has its long axis oriented parallel to the plane of the paper, and the short The more finely represented the liquid crystal molecules (5318), the closer the orientation of their major axes is to the direction of the normal to the plane of the paper. Therefore, the liquid crystal molecule 5318 shown in Figure 53(A) has its long axis oriented in the alignment film. It is oriented to face the normal direction. Therefore, the liquid crystal in the part with the electrode notch 5319 Molecules 5318 emit light from the boundary between the electrode notch 5319 and the fourth conductive layer 5313. The elements are oriented in a projectile manner. This state allows for the creation of a liquid crystal display with a wide viewing angle. It is possible.

[0383] Next, referring to Figure 53(B), when the present invention is applied to a PVA-type liquid crystal display device, An example of pixel layout will be described. A PVA-type liquid crystal display device to which the present invention is applied. The pixels consist of scan line 5321, video signal line 5322, capacitance line 5323, and TFT 532 The device comprises 4, a pixel electrode 5325, a pixel capacitance 5326, and an electrode notch 5319. It's okay to be there.

[0384] Since scan line 5321 is electrically connected to the gate terminal of TFT5324, the first conductive It is preferable that it is composed of layer 5303.

[0385] The video signal line 5322 is electrically connected to the source or drain terminal of the TFT5324. Therefore, it is preferable that it be composed of a second conductive layer 5307. Also, scan line 53 Since lines 21 and video signal line 5322 are arranged in a matrix, at least on different layers It is preferable that it be formed with a conductive layer.

[0386] The capacitance line 5323 is arranged parallel to the pixel electrode 5325, thereby forming the pixel capacitance 5326. This is a wiring for achieving the desired result, and it is preferable that it is composed of a first conductive layer 5303. As shown in Figure 53(B), the capacitance line 5323 runs along the video signal line 5322, and the video signal It may be extended to surround line 5322. In this way, video signal line 5322 The phenomenon in which the potential of an electrode that should maintain its potential changes in response to a change in the potential of another electrode, known as a chromosome change. Lost talk can be reduced. Furthermore, the crossover capacitance with video signal line 5322 can be reduced. Therefore, as shown in Figure 53(B), the first semiconductor layer 5305 is connected to the capacitance line 5323 and the image It may be installed in the intersection area of ​​signal line 5322.

[0387] The TFT5324 acts as a switch that connects the video signal line 5322 and the pixel electrode 5325. It works. Note that, as shown in Figure 53(B), the source area or drain area of ​​the TFT5324 Even if you arrange one of the drain regions to surround the other of the source or drain region Good. This way, a large channel width can be obtained in a small area, and switching The capacity can be greatly increased. Furthermore, as shown in Figure 53(B), the TFT5324 The gate terminals may be arranged to surround the first semiconductor layer 5305.

[0388] The pixel electrode 5325 is electrically connected to either the source terminal or the drain terminal of the TFT5324. The pixel electrode 5325 receives the signal voltage transmitted by the video signal line 5322. These are electrodes for applying to the crystal element. Furthermore, capacitance lines 5323 and pixel capacitance 5326 are formed. This is also good. This way, the signal voltage transmitted by the video signal line 5322 is retained. It can also have a ratio. Furthermore, as shown in Figure 53(B), the pixel electrode 5325 is a fourth The electrode notch 53 is shaped to match the shape of the electrode notch 5319 provided in the conductive layer 5313. It is preferable to form a portion where the pixel electrode 5325 is cut out in the area where 19 is absent. By doing so, multiple regions with different orientations of liquid crystal molecules 5318 can be formed, A liquid crystal display device with a wide viewing angle can be obtained. In addition, the pixel electrode 5325 is made transparent. When manufactured using the same materials, a transmissive liquid crystal display can be obtained. The display device can display images with high color reproduction and high image quality. If the elementary electrode 5325 is made of a reflective material, a reflective liquid crystal display device can be obtained. This is possible. Reflective liquid crystal displays have high visibility in bright environments such as outdoors. Furthermore, since a backlight is not required, power consumption can be kept very low. The elementary electrode 5325 was fabricated using both transparent and reflective materials. In combination, a semi-transmissive liquid crystal display device can be obtained that combines the advantages of both. If the electrode 5325 is made of a reflective material, the surface of the pixel electrode 5325 will have irregularities. It is acceptable to let them hold it. By doing so, the reflected light is diffusely scattered, so the angle of the intensity distribution of the reflected light is affected. It has the advantage of reducing occlusion. In other words, it is a reflective type that maintains a constant brightness no matter what angle it is viewed from. A liquid crystal display device can be obtained.

[0389] Next, with reference to Figure 54, we will explain the case in which the present invention is applied to a transverse electric field type liquid crystal display device. Figure 54 shows the switching process performed so that the orientation of the liquid crystal molecules is always horizontal to the substrate. In order to achieve this, among the pixel structures of a liquid crystal display device that applies an electric field in the lateral direction, the pixel electrode 542 By applying a comb-like pattern to electrode 5 and the common electrode 5423, an electric field is applied in the lateral direction. The present invention is applied to the so-called IPS (In-Plane-Switching) method. These are cross-sectional and top views of a pixel in this case. Figure 54(A) is a cross-sectional view of a pixel, and Figure 54( Figure B) is a top view of a pixel. Also, the cross-sectional view of a pixel shown in Figure 54(A) is shown in Figure 54(B). This corresponds to the line segment a-a' in the top view of the pixel shown in Figure 54. By applying the present invention to a crystal display device, in principle, a wide viewing angle and a fast response time for gradation can be achieved. A liquid crystal display device with low dependency can be obtained.

[0390] The pixel structure of an IPS-type liquid crystal display device will be explained with reference to Figure 54(A). A display device has a core component called a liquid crystal panel that displays images. The liquid crystal panel is, Two processed substrates are bonded together with a gap of several micrometers, and liquid is applied between the two substrates. It is fabricated by injecting a crystalline material. In Figure 54(A), the two substrates are the first substrate The first substrate is 5401, and the second substrate is 5416. The first substrate has a TFT and pixel electrodes. The second substrate was fabricated and also had a light-shielding film 5414, a color filter 5415, and a spacer. 5417 and a second alignment film 5412 may be prepared.

[0391] Furthermore, the present invention can be implemented even without fabricating a TFT on the first substrate 5401. If the present invention is implemented without producing the original part, the number of steps will be reduced, thereby lowering the manufacturing cost. This can be done. Furthermore, because the structure is simple, the yield can be improved. On the other hand, When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0392] Note that the TFT shown in Figure 54 is a bottom-gate type TFT using an amorphous semiconductor, It has the advantage of being able to be manufactured inexpensively using a substrate of a certain area. However, the present invention is not limited to this. It is not something that can be done. The usable TFT structure is a bottom-gate type TFT with a channel There are etch-type and channel-protected types. Top-gate type is also acceptable. Furthermore, amorphous materials are also available. Not only semiconductors, but also polycrystalline semiconductors can be used.

[0393] Furthermore, the present invention can be implemented even without fabricating a light-shielding film 5414 on the second substrate 5416. If the present invention is carried out without producing the light-shielding film 5414, the number of steps will be reduced, thus reducing the manufacturing cost. It can reduce waste. Also, because of its simple structure, it can improve yield. This is possible. On the other hand, when the light-shielding film 5414 is manufactured and the present invention is implemented, light leakage occurs when black is displayed. A display device with fewer components can be obtained.

[0394] Furthermore, the present invention can be implemented even without fabricating a color filter 5415 on the second substrate 5416. It is possible. If the present invention is carried out without manufacturing the color filter 5415, the number of steps will be Because it decreases, manufacturing costs can be reduced. Also, because the structure is simple, the yield This can improve the quality. On the other hand, the present invention can be realized by manufacturing a color filter 5415. If implemented, a display device capable of displaying in color can be obtained.

[0395] Furthermore, in this invention, a spacer 5417 is not fabricated on the second substrate 5416, and a spherical spacer is used. It can also be implemented by scattering. The present invention can be implemented by scattering spherical spacers. Because the number of steps is reduced, manufacturing costs can be lowered. Also, the structure is simple. Therefore, the yield can be improved. On the other hand, spacer 5417 is manufactured and the main When performing the installation, the position of the spacers does not vary, so the distance between the two circuit boards is uniform. This makes it possible to obtain a display device with less display unevenness.

[0396] Next, the processing to be performed on the first substrate 5401 may be done using the method described in Figure 51. Therefore, it is omitted. Here, the first substrate 5401, the first insulating film 5402, and the first conductive layer 5 403, second insulating film 5404, first semiconductor layer 5405, second semiconductor layer 5406, The second conductive layer 5407, the third insulating film 5408, the third conductive layer 5409, and the first alignment film 54 10 are the first substrate 5101, the first insulating film 5102, and the first in Figure 51, respectively. Conductive layer 5103, second insulating film 5104, first semiconductor layer 5105, second semiconductor layer 51 06, second conductive layer 5107, third insulating film 5108, third conductive layer 5109, first This corresponds to the target film 5110. Furthermore, the third conductive layer 5409 on the first substrate 5401 side has a pattern. They may be processed to form two comb-like shapes that interlock with each other. The comb-shaped electrodes are electrically connected to either the source terminal or the drain terminal of the TFT5424. The other comb-shaped electrode may be electrically connected to the common electrode 5423. This allows for an effective application of a lateral electric field to the liquid crystal molecule 5418.

[0397] The first substrate 5401, light-shielding film 5414, and color filter 541 were fabricated as described above. 5. The spacer 5417 and the second substrate 5416 on which the second alignment film 5412 was fabricated are placed. The two substrates are bonded together with a gap of several micrometers using a sealing material, and liquid crystal material is poured between them. By doing so, an LCD panel can be manufactured. Although not shown in the diagram, on the second substrate 5416 side A conductive layer may be formed. By forming a conductive layer on the second substrate 5416 side, externally This makes it less susceptible to electromagnetic noise.

[0398] Next, we will explain the characteristics of the pixel structure of the IPS type liquid crystal panel, as shown in Figure 54. Figure 5 Liquid crystal molecule 5418, shown in 4(A), is an elongated molecule with a long axis and a short axis. In Figure 54(A), the orientation of 5418 is represented by its length. In other words, the elongated liquid crystal molecule 5418 has its long axis oriented parallel to the plane of the paper, and the short The more liquid crystal molecules represented, the closer the orientation of their long axes is to the normal direction of the paper. Therefore, the liquid crystal molecule 5418 shown in Figure 54(A) always has its long axis oriented towards the substrate. And it is oriented so as to face horizontally. In Figure 54(A), in the state without an electric field This shows the orientation, but when an electric field is applied to liquid crystal molecule 5418, the direction of its long axis is It rotates in the horizontal plane while always maintaining a horizontal orientation relative to the substrate. This allows for the creation of liquid crystal display devices with a wide viewing angle.

[0399] Next, referring to Figure 54(B), when the present invention is applied to an IPS type liquid crystal display device, An example of pixel layout will be described. An IPS-type liquid crystal display device to which the present invention is applied. The pixels consist of scan line 5421, video signal line 5422, common electrode 5423, and TFT 54 It may also include 24 and a pixel electrode 5425.

[0400] Since scan line 5421 is electrically connected to the gate terminal of TFT5424, the first conductive It is preferable that it is composed of layer 5403.

[0401] The video signal line 5422 is electrically connected to the source or drain terminal of the TFT5424. Therefore, it is preferable that it be composed of a second conductive layer 5407. Also, scan line 54 Since lines 21 and video signal line 5422 are arranged in a matrix, at least on different layers It is preferable that it be formed with a conductive layer. Note that, as shown in Figure 54(B), the video signal line 54 22 refracts within the pixel to match the shape of the pixel electrode 5425 and the common electrode 5423. They may be formed in a curved shape. This allows for a larger aperture ratio of the pixels. Therefore, the efficiency of liquid crystal display devices can be improved.

[0402] The common electrode 5423 is positioned parallel to the pixel electrode 5425, thereby generating a lateral electric field. These are electrodes for the purpose of [doing something], and are composed of a first conductive layer 5403 and a third conductive layer 5409. It is preferable that it is configured as shown in Figure 54(B). The common electrode 5423 is used for video signals. It may extend along line 5422, surrounding the video signal line 5422. As a result, the potent...

Claims

1. It has a gate driver, The gate driver has a first transistor to a tenth transistor, Either the source or the drain of the first transistor is always in contact with the clock signal line. The source or drain of the first transistor, the other of which is always in contact with the output signal line, Either the source or the drain of the second transistor is always in contact with the output signal line. The source or drain of the second transistor, the other of which is always in contact with the power line, Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The gate of the third transistor is always in electrical contact with the first wiring. Either the source or drain of the fourth transistor is always in contact with the gate of the first transistor. The gate of the fourth transistor is always in electrical contact with the second wiring. Either the source or drain of the fifth transistor is always in contact with the gate of the first transistor. The gate of the fifth transistor is always in electrical contact with the gate of the second transistor. Either the source or drain of the sixth transistor is always in contact with the gate of the second transistor. Either the source or drain of the seventh transistor is always in contact with the gate of the sixth transistor. The source or drain of the seventh transistor, the other of which is always in electrical contact with the third wiring, The gate of the seventh transistor is always in electrical contact with the third wiring. Either the source or drain of the eighth transistor is always in contact with the gate of the sixth transistor. The gate of the eighth transistor is always in electrical contact with the gate of the first transistor. Either the source or drain of the ninth transistor is always in contact with the gate of the first transistor. The source or drain of the ninth transistor is always in electrical contact with the power line. The gate of the ninth transistor is always in contact with either the source or the drain of the tenth transistor. The gate of the 10th transistor is always in electrical contact with the gate of the 6th transistor. The source or drain of the 10th transistor, the other of which is always in electrical contact with the fourth wiring, When the source or drain of the third transistor is in a conductive state with the gate of the first transistor via at least the channel forming region of the third transistor, the potential that turns on the first transistor is input to the gate of the first transistor via at least the channel forming region of the third transistor. When the source or drain of the fourth transistor is in a conductive state with the gate of the first transistor via at least the channel forming region of the fourth transistor, the potential that turns off the first transistor is input to the gate of the first transistor via at least the channel forming region of the fourth transistor. When the source or drain of the fifth transistor is in a conductive state with the gate of the first transistor through at least the channel forming region of the fifth transistor, a potential that turns off the first transistor is input to the gate of the first transistor through at least the channel forming region of the fifth transistor. When the source or drain of the sixth transistor is in a conductive state with the gate of the second transistor and the gate of the fifth transistor, at least through the channel formation region of the sixth transistor, a potential controlling the potential of the gate of the second transistor and a potential controlling the potential of the gate of the fifth transistor are input to the gates of the second transistor and the fifth transistor, at least through the channel formation region of the sixth transistor. The signal input to the source or the other drain of the sixth transistor is not input to the source or the other drain of the third transistor. The on / off state of the sixth transistor is controlled by the seventh and eighth transistors. The first transistor has a larger channel width than the third transistor. The first transistor has a larger channel width than the fourth transistor. The first transistor is a display device with a larger channel width than the fifth transistor.

2. In claim 1, Having a pixel section, The pixel portion has an eleventh transistor, The source and drain of the 11th transistor are always in electrical contact with the pixel electrode. The source and drain of the 11th transistor are always in conductivity with the video signal line. The gate of the 11th transistor is always in contact with the output signal line. In a plan view, one of the source and drain of the 11th transistor has a region sandwiched between the other source and drain of the 11th transistor. The aforementioned pixel electrode is a display device having a plurality of notched portions.

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