Control device, display device, and control method

Abstract

To provide a control device, etc., which enable reduction of power consumption thereof.SOLUTION: A control device 20 is a control device for a display panel 10 having such a configuration that a frame period representing a period in which the same image is continuously displayed changes or becomes temporarily stable in a certain range for each frame, however an exact frame period is not known in advance, the control device performs control in such a way that the number of subframe periods is changed to reconstruct the frame period with n subframe periods (n=integer 2 or greater) without relying on an input frame period. The control device 20 comprises: a signal processing unit 50 outputting, in units of a subframe period, an output video signal based on an input first input video signal; and a control unit 60 supplying the display panel 10 with the output video signal output from the signal processing unit 50 and a control signal controlling the operation of the display panel 10.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a control device, a display device, and a control method, and particularly to a control device, a display device, and a control method for controlling the display brightness of a display.

Background Art

[0002] Conventionally, in a display device, techniques for suppressing the visibility of flicker have been studied. For example, a technique has been studied in which the number of sub-frames constituting one frame period is changed according to the duty ratio set corresponding to the luminance information, and the duty ratio within the sub-frame is made the same as the duty ratio of one frame period. Thereby, even when the light emission period is changed by luminance adjustment or the like, flicker generated on the display screen can be suppressed.

[0003] In recent years, video drawing on displays of personal computers, mobile devices, etc. has been performed by a video processing device called a GPU (Graphics Processing Unit). And the display speed of the display is becoming determined by the performance of the GPU. In other words, in recent years, the frame period (frame rate) varies depending on the content processed by the GPU.

[0004] Therefore, Patent Document 1 discloses a control device etc. that can suppress the occurrence of flicker even when the frame period varies. Specifically, Patent Document 1 discloses a control device etc. that changes the number of sub-frames so as to reconstruct the frame period with n (n is an integer of 2 or more) sub-frames regardless of the input frame period and displays an image.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] However, the technology described in Patent Document 1 requires memory in the panel TCON (Timing Controller) to convert the frame rate to subframe rate units, which presents a power consumption challenge.

[0007] Therefore, this disclosure provides a control device, a display device, and a control method capable of reducing power consumption. [Means for solving the problem]

[0008] A control device according to one aspect of the present disclosure is a control device for a display panel in which the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range for each frame or temporarily stabilizes, but the exact frame period is not known in advance, and the control device includes a signal processing unit that changes the number of subframe periods so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods regardless of the input frame period, controls the display of an image, outputs an output video signal based on an input first input video signal in units of the subframe periods, and a control unit that supplies the output video signal output from the signal processing unit and a control signal for controlling the operation of the display panel to the display panel.

[0009] A display device according to one aspect of the present disclosure comprises the control device described above, and a display panel having a gate drive circuit to which the control signal from the control device is input, and a source drive circuit to which the output video signal from the control device is input.

[0010] A control method according to one aspect of the present disclosure is a control method for a display panel in which the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range for each frame or temporarily stabilizes, but the exact frame period is not known in advance, and the control method includes changing the number of subframe periods so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods, regardless of the input frame period, and displaying an image, and further including outputting an output video signal based on the input video signal in units of the subframe periods, and supplying the output video signal and a control signal for controlling the operation of the display panel to the display panel. [Effects of the Invention]

[0011] According to one aspect of this disclosure, a control device and the like that can reduce power consumption can be realized. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] Figure 2 is a schematic circuit diagram showing the configuration of a pixel circuit according to the embodiment. [Figure 3] Figure 3 is a block diagram showing an example of the functional configuration of a display device according to an embodiment. [Figure 4] Figure 4 is a diagram illustrating the overview of the duty cycle control performed by the control unit according to the embodiment. [Figure 5] Figure 5 is a block diagram showing another example of the functional configuration of a display device according to the embodiment. [Figure 6] Figure 6 is a sequence diagram showing the operation of the control device according to the embodiment. [Figure 7] Figure 7 is a schematic diagram illustrating the timing of writing and reading video signals to and from the frame memory of the signal processing unit according to the embodiment. [Figure 8] Figure 8 is a flowchart illustrating the overview of the operation of controlling the light emission period and extinction period of the frame period of the control device according to the embodiment. [Figure 9A] FIG. 9A is a flowchart showing the detailed operation of step S22 shown in FIG. 8. [Figure 9B] FIG. 9B is a flowchart showing the detailed operation of step S23 shown in FIG. 8. [Figure 10] FIG. 10 is a diagram showing an example of details of an operation for controlling a light emission period and a light extinction period of a frame period performed by a control device according to an embodiment. [Figure 11] FIG. 11 is a schematic diagram for explaining writing and reading timings of a video signal to a frame memory included in a signal processing unit according to a modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be specifically described with reference to the drawings.

[0014] Note that each of the embodiments described below shows comprehensive or specific examples. Numerical values, shapes, components, arrangement positions and connection forms of components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. For example, terms indicating relationships between the same or other elements, as well as numerical values and numerical ranges, are not expressions representing only strict meanings, but expressions meaning substantially equivalent ranges, for example, differences of about several percent (for example, about 5%). In addition, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0015] Also, each figure is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, scales etc. in each figure do not necessarily match. Also, in each figure, substantially the same configuration is denoted by the same reference numeral, and overlapping descriptions are omitted or simplified.

[0016] (Embodiment) Hereinafter, a control device and the like according to the present embodiment will be described with reference to FIGS. 1 to 10. In the present embodiment, a case where an organic electroluminescence (EL) element is used in a display device will be described as an example.

[0017] [1. Configuration of Display Device] First, the configuration of a display device including a control device according to an aspect of the present disclosure will be described with reference to FIG. 1. FIG. 1 is a schematic diagram showing a configuration example of a display device 1 according to the present embodiment.

[0018] As shown in FIG. 1, the display device 1 includes a display panel 10 and a control device 20. The display device 1 is driven, for example, by a progressive driving method of an organic EL light-emitting panel.

[0019] [1-1. Configuration of Display Panel] The display panel 10 includes a display unit 12 having a plurality of pixel circuits 30, and also includes a gate driving circuit 14 and a source driving circuit 16 as peripheral circuits of the display unit 12. The display unit 12, the gate driving circuit 14, the source driving circuit 16, the scanning lines 40, and the signal lines 42 are mounted on a panel substrate (not shown) formed of, for example, a resin such as glass or acrylic.

[0020] The display unit 12 displays an image based on video signals (video signals R, G, B) input to the display device 1 from the outside. As shown in FIG. 1, the display unit 12 includes a plurality of pixel circuits 30 arranged in a matrix, and row-shaped scanning lines 40 and column-shaped signal lines 42 are wired. In the display unit 12, an initialization operation, a writing operation, and a light-emitting operation are sequentially executed for each row of the plurality of pixel circuits 30.

[0021] The plurality of pixel circuits 30 are provided in the display panel 10 and arranged in a matrix. More specifically, each of the plurality of pixel circuits 30 is arranged at a position where the scanning line 40 and the signal line 42 intersect. Details will be described later.

[0022] The scan lines 40 are arranged for each row of multiple pixel circuits 30. One end of the scan line 40 is connected to the pixel circuit 30, and the other end of the scan line 40 is connected to the gate drive circuit 14.

[0023] The signal line 42 is arranged for each row of multiple pixel circuits 30. One end of the signal line 42 is connected to the pixel circuit 30, and the other end of the signal line 42 is connected to the source drive circuit 16.

[0024] The gate drive circuit 14, also called a scan line drive circuit, is composed of, for example, a shift register. The gate drive circuit 14 is connected to the scan line 40 and controls the on / off state of each transistor in the pixel circuit 30 by outputting a gate control signal to the scan line 40. In this embodiment, the gate drive circuit 14 outputs, for example, control signal WS, control signal REF, control signal INI, and extinction signal EN to the gate (gate electrode) of each transistor in the pixel circuit 30 as gate control signals to control the on / off state of each transistor in the pixel circuit 30. Control signals WS, REF, INI, and extinction signal EN are examples of control signals.

[0025] The source drive circuit 16 is also called the signal line drive circuit. The source drive circuit 16 is connected to the signal line 42 and supplies the video signal, which is supplied from the control device 20 in frame units, to each pixel circuit 30 by outputting it to the signal line 42. The source drive circuit 16 writes brightness information based on the video signal to each of the pixel circuits 30 in the form of a current value or a voltage value through the signal line 42. The video signal input to the source drive circuit 16 is, for example, digital serial data for each of the three primary colors of RGB (video signals R, G, B). The video signals R, G, B input to the source drive circuit 16 are converted into line-by-line parallel data inside the source drive circuit 16. Furthermore, the line-by-line parallel data is converted into line-by-line analog data inside the source drive circuit 16 and output as a video signal to the signal line 42.

[0026] [1-2. Pixel Circuit Configuration] Multiple pixel circuits 30 are arranged, for example, in an N row and M column configuration. N and M vary depending on the size and resolution of the display screen. For example, at a resolution called HD (High Definition), if pixel circuits 30 corresponding to the three primary colors RGB are adjacent within a row, N is at least 1080 rows and M is at least 1920 × 3 columns. In this embodiment, each pixel circuit 30 has an organic EL element as a light-emitting element.

[0027] The configuration of the pixel circuit 30 will be further explained with reference to Figure 2. Figure 2 is a schematic circuit diagram showing the configuration of the pixel circuit 30 according to this embodiment.

[0028] As shown in Figure 2, the pixel circuit 30 comprises a light-emitting element 32, a drive transistor 33, switch transistors 34, 36, and 37, a selection transistor 35, and a pixel capacitance 38. In Figure 2, the pixel capacitance 38 is also denoted as Cs.

[0029] The light-emitting element 32 has its cathode connected to the power supply Vcath (negative power line) and its anode connected to the source of the drive transistor 33. The light-emitting element 32 emits light with brightness corresponding to the signal voltage of the video signal supplied from the drive transistor 33 when a current corresponding to the signal voltage of the video signal flows through it. The light-emitting element 32 is, for example, an organic EL element such as an OLED (Organic Light Emitting Diode). For example, the pixel circuit 30 (pixel) that constitutes the display panel 10 that displays an image is composed of a light-emitting element 32 that emits light by current drive, including an organic EL element. Note that the light-emitting element 32 is not limited to an organic EL element, but may also be an inorganic EL element or a self-emissive element such as a QLED (Quantum-dot Light Emitting Diode), or it may not be a self-emissive element as long as it is a current-driven element.

[0030] The drive transistor 33 has its gate connected to one electrode of the pixel capacitor 38, its drain connected to the source of the switch transistor 34, and its source connected to the anode of the light-emitting element 32. In Figure 2, the source is further connected to the other electrode of the pixel capacitor 38. The drive transistor 33 converts the signal voltage applied between the gate and source into a current (also referred to as the drain-source current) corresponding to that signal voltage. When the drive transistor 33 turns on, it supplies the drain-source current to the light-emitting element 32, causing the light-emitting element 32 to emit light. The drive transistor 33 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0031] The switch transistor 34 has its gate connected to the scan line 40, one of its source and drain connected to the power supply Vcc, and the other of its source and drain connected to the drain of the drive transistor 33. The switch transistor 34 is ON or OFF in response to the extinction signal EN supplied from the scan line 40. When the switch transistor 34 is ON, it connects the drive transistor 33 to the power supply Vcc, and supplies the current between the drain and source of the drive transistor 33 to the light-emitting element 32. In this embodiment, when the switch transistor 34 is ON and the switch transistor 37 is OFF, the drive transistor 33 is connected to the power supply Vcc, and the current between the drain and source of the drive transistor 33 is supplied to the light-emitting element 32. The switch transistor 34 is composed of, for example, a p-type thin-film transistor (p-type TFT).

[0032] The selection transistor 35 has its gate connected to the scan line 40, one of its source and drain connected to the signal line 42, and the other of its source and drain connected to one electrode of the pixel capacitor 38. The selection transistor 35 is either ON or OFF in response to the control signal WS supplied from the scan line 40. When the selection transistor 35 is ON, it applies the signal voltage of the video signal supplied from the signal line 42 to the electrode of the pixel capacitor 38, and accumulates a charge in the pixel capacitor 38 corresponding to the signal voltage. The selection transistor 35 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0033] The switch transistor 36 has its gate connected to the scan line 40, one of its source and drain connected to the power supply Vref, and the other of its source and drain connected to one electrode of the pixel capacitor 38. The switch transistor 36 is ON or OFF in response to the control signal REF supplied from the scan line 40. When the switch transistor 36 is ON, it sets the electrode of the pixel capacitor 38 to the voltage of the power supply Vref (reference voltage). The switch transistor 36 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0034] The switch transistor 37 has its gate connected to the scan line 40, one of its source and drain connected to the source of the switch transistor 34 and the drain of the drive transistor 33, and the other of its source and drain connected to the power supply Vini. The switch transistor 37 is turned on or off in response to the control signal INI supplied from the scan line 40. The switch transistor 37 turns on when the drive transistor 33 is on and the switch transistor 34 is on and the connection to the power supply Vcc is interrupted, thereby setting the anode of the light-emitting element 32 to the voltage (reference voltage) of the power supply Vini. The switch transistor 37 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0035] The pixel capacitor 38 is a capacitor in which one electrode is connected to the gate of the drive transistor 33, the source of the selection transistor 35, and the source of the switch transistor 36, and the other electrode is connected to the source of the drive transistor 33. The pixel capacitor 38 stores charge corresponding to the signal voltage supplied from the signal line 42. The pixel capacitor 38 stably maintains the voltage between the gate and source electrodes of the drive transistor 33, for example, after the selection transistor 35 and the switch transistor 36 are turned off. In this way, when the selection transistor 35 and the switch transistor 36 are turned off, the pixel capacitor 38 applies a voltage between the gate and source of the drive transistor 33 according to the signal potential due to the stored charge.

[0036] The EL capacitance 39 is a parasitic capacitance inherent in the EL element. After this capacitance charges and the voltage between the electrodes rises, current flows to the EL element, and the EL element begins to emit light.

[0037] Furthermore, the conductivity types of the drive transistor 33, selection transistor 35, switch transistor 36, and switch transistor 37 are not limited to those described above, and n-type and p-type TFTs may be mixed as appropriate. Also, the conductivity type of the switch transistor 34 is not limited to those described above, and may be an n-type TFT. In addition, each transistor is not limited to polysilicon TFTs, but may be composed of amorphous silicon TFTs or the like.

[0038] [1-3. Control device configuration] A control device 20 according to one aspect of this disclosure is a control device for a display panel 10 in which the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range for each frame or temporarily stabilizes, but the exact frame period is not known in advance. The control device 20 reconstructs the display frame period with fixed-length subframes (subframe periods) regardless of the input frame period and performs control for displaying the image. In this embodiment, the subframe period (subframe length) is fixed regardless of the input frame period (input frame length), and the control device 20 performs control to change the number of subframes according to the input frame length. Hereinafter, the control device 20 according to this embodiment will be further described as an aspect of this disclosure with reference to Figure 3. Figure 3 is a block diagram showing an example of the functional configuration of the display device 1 according to the embodiment.

[0039] As shown in Figures 1 and 3, the control device 20 includes a signal processing unit 50 and a control unit 60. The control device 20 is located outside the display panel 10. The control device 20 is formed, for example, on an external system circuit board (not shown). The control device 20 generates various control signals based on a vertical synchronization signal VS, a horizontal synchronization signal HS, and a video duration signal DE supplied from an external source.

[0040] The signal processing unit 50, for example, functions as a scaler and outputs video signals supplied from an external signal source 70 of the display device 1 to the control unit 60 at predetermined intervals. The signal processing unit 50 stores the video signals supplied from the signal source 70 in the frame memory 51, reads the video signals from the frame memory 51 at predetermined intervals, and outputs the read video signals to the control unit 60. The reading and writing of video signals to and from the frame memory 51 will be described later (see Figure 7). The signal source 70 is, for example, a terminal device such as a personal computer or a game console, but is not limited to these.

[0041] The predetermined timing is set based on the duration of one frame. Specifically, the predetermined timing is set in the subframe duration based on the duration of one frame. In this embodiment, the predetermined timing is the unit of the subframe duration. That is, the signal processing unit 50 reads the video signal from the frame memory 51 in units of the subframe duration and outputs the read video signal to the control unit 60. The subframe duration is a period defined based on the number of lines notified in advance, and each frame is represented as n times this subframe duration.

[0042] The subframe duration may be 720Hz (1.39ms) if, for example, the 1-frame duration is 144Hz. In this case, it can be said that each frame is represented as five times the subframe duration. Note that n is not limited to 5. The subframe duration may be set based on the shortest frame duration (1-frame duration) among the frame durations that the GPU mounted on the display device 1 can vary.

[0043] The subframe period may be predetermined and stored in the memory of the signal processing unit 50. In other words, the signal processing unit 50 may determine the subframe period.

[0044] Furthermore, the signal processing unit 50 may acquire information regarding the number of lines per subframe (number of display lines) from the control unit 60 and generate a video signal to output to the control unit 60 based on the acquired information. The signal processing unit 50 may, for example, generate a video signal (an example of an output video signal) by performing predetermined signal processing according to the number of lines on the video signal stored in the frame memory 51 (a video signal acquired from the signal source 70, which is an example of a first input video signal), and output the generated video signal to the control unit 60. Note that the first input video signal and the output video signal may be the same signal. Below, an example in which the first input video signal and the output video signal are the same signal will be described, and the signal will also be simply referred to as the video signal.

[0045] The number of lines per subframe may change, for example, by changing the settings of the display unit 12 by the user (for example, settings such as resolution and display area on the display screen).

[0046] Thus, the signal processing unit 50 may obtain information from the control unit 60 indicating the number of lines in the subframe period of the display panel 10 that displays the image, and generate a video signal to output to the control unit 60 based on this information. For example, the signal processing unit 50 generates a video signal corresponding to this information and outputs it to the control unit 60.

[0047] The number of lines during the subframe period may be predetermined and stored in memory. The signal processing unit 50 may then read this information from memory and generate a video signal to output to the control unit 60 based on the read information.

[0048] The frame memory 51 is a memory device that stores video signals. The frame memory 51 is a "1W1R type" memory, with one write port (W) and one read port (R). In other words, the frame memory 51 can perform writing and reading simultaneously. The frame memory 51 is not particularly limited as long as it has general storage functions, such as semiconductor memory. The frame memory 51 is just one example of a memory.

[0049] The frame memory 51 has a storage capacity capable of storing at least one screen (one frame) of video signals. In this embodiment, in addition to the storage capacity for one screen, the frame memory 51 has a storage capacity corresponding to the predetermined timing described above. The storage capacity of the frame memory 51 will be described later.

[0050] The control unit 60 functions, for example, as a Timing Controller (TCON) and controls the overall operation of the display device 1. The control unit 60 supplies the video signal output from the signal processing unit 50 and control signals for controlling the gate drive circuit 14 and the source drive circuit 16 (an example of a control signal for controlling the operation of the display panel 10) to the display panel 10. Specifically, the control unit 60 generates a gate control signal to control the gate drive circuit 14 so that the video signal is displayed on the display unit 12 at a desired timing, and outputs the generated gate control signal to the gate drive circuit 14. For example, the control unit 60 outputs a gate control signal generated based on the vertical synchronization signal VS, the horizontal synchronization signal HS, and the video period signal DE to the gate drive circuit 14. In this embodiment, the control unit 60 detects the reception of the vertical synchronization signal VS or the video period signal DE.

[0051] In this embodiment, the control unit 60 generates a gate control signal that executes multiple subframe periods, each consisting of an illumination period and an extinction period, at regular time intervals. When the signal processing unit 50 detects a signal indicating the start of a frame period, the control unit 60 generates a gate control signal that executes an initialization period during the extinction period in the subframe period following the subframe period executed at the time of detection. Otherwise, when the control unit 60 does not detect a signal indicating the start of a frame period, it generates a gate control signal that repeatedly executes subframe periods consisting of illumination periods and extinction periods at regular time intervals. The control unit 60 also supplies digital serial data of the video signal to the source drive circuit 16.

[0052] The control unit 60 does not have a frame memory for temporarily holding video signals acquired from the signal processing unit 50. For example, in the control device 20, of the signal processing unit 50 and the control unit 60, only the signal processing unit 50 has a frame memory for storing video signals. In other words, the control unit 60 does not control the timing of supplying the digital serial data of video signals R, G, and B to the source drive circuit 16 (control of frame rate conversion). In this disclosure, this timing control is performed by the signal processing unit 50. In other words, the control unit 60 does not perform the process of delaying the output of video signals.

[0053] The standard for the communication interface between the signal processing unit 50 and the control unit 60 is not particularly limited, but for example, eDP (embedded DisplayPort) may be used. Alternatively, the signal processing unit 50 and the control unit 60 may be connected via an SPI (Serial Peripheral Interface) bus or the like to enable communication.

[0054] Furthermore, the signal processing unit 50 and the control unit 60 may be composed of different IC (Integrated Circuit) chips. For example, the signal processing unit 50 and the control unit 60 may be different IC chips mounted on the same substrate.

[0055] Furthermore, as described above, the control device 20 writes the video signal to its internal frame memory (e.g., frame memory 51) only once, and reads the video signal from the frame memory at least once. In other words, the control device 20 outputs the video signal to the display panel 10 simply by writing the video signal to its frame memory (e.g., frame memory 51) only once, and reading the video signal from the frame memory at least once, after the video signal is supplied from the signal source 70.

[0056] Here, Figure 4 is a diagram illustrating the overview of the duty cycle control performed by the control unit 60 according to this embodiment. The gate control signal shown in Figure 4 is the signal input to the gate of the switch transistor 34.

[0057] The control unit 60 detects a signal indicating the start of a frame period. The signal indicating the start of a frame period may be a vertical synchronization signal VS or a video period signal DE. Hereafter, the frame period will be described as variable, but it may also be fixed.

[0058] The control unit 60 generates a gate control signal to cause the gate drive circuit 14 to perform duty cycle control as shown in Figure 4. More specifically, when the control unit 60 detects the signal, it generates a gate control signal that, after a predetermined time from the time the signal is detected, sequentially starts n (where n is an integer of 2 or more) subframe periods that constitute the frame period, starting from the first subframe period. This gate control signal controls all of the subframe periods to have a predetermined length, and the duty cycle ratio, which is the ratio of the light emission period to the extinction period in the subframe periods, to be the same predetermined ratio.

[0059] Furthermore, each of the multiple subframe periods is not limited to a predetermined period of the same length, but may consist of periods of the same length (not necessarily exactly the same, but including a range that can be considered the same with a certain error). The control unit 60 may control each of the n subframe periods so that they consist of periods of the predetermined same length. Similarly, the duty cycle, which is the ratio of the light emission period to the extinction period, is not limited to a predetermined identical ratio, but may be the same ratio (not necessarily exactly the same ratio, but including a range that can be considered the same ratio with a certain error).

[0060] Furthermore, the control unit 60 generates a gate control signal that controls the extinction period in the first subframe period of the n subframe periods (for example, the hatched period of the gate control signal shown in Figure 4) to include an initialization period for initializing the multiple pixel circuits 30.

[0061] Furthermore, if a signal indicating the start of the next frame period is detected during the execution of the last subframe period of n subframe periods, this predetermined time will be the period from the time the signal is detected during the last subframe period to the end of that last subframe period.

[0062] As illustrated in the example shown in Figure 4, the control unit 60 generates a gate control signal that sets the same duty cycle for each subframe period so that one frame period is composed of multiple subframe periods of the same length, and each subframe period has the same extinction period length. In other words, the control unit 60 controls the duty cycle, which is the ratio of the light emission period to the extinction period, to be the same predetermined ratio.

[0063] However, the control unit 60 generates a gate control signal that includes an initialization period in the extinction period of the first subframe period that constitutes one frame period. Figure 4 shows an example where one frame period is 144 Hz, the subframe period is 720 Hz (1.39 ms), and one frame period consists of five subframe periods. The periods in Figure 4 when the gate control signal is High correspond to the extinction period, and the hatched periods within the periods when the gate control signal is High correspond to the extinction period including the initialization period. Since the switch transistor 34 is a p-type transistor, it is in the off state when the gate control signal is High and in the on state when the gate control signal is Low.

[0064] Note that the configuration of the control device 20 is not limited to the configuration shown in Figure 3. Figure 5 is a block diagram showing another example of the functional configuration of the display device 1 according to this embodiment.

[0065] As shown in Figure 5, the signal processing unit 50 and the control unit 60 may be integrated into a single chip. In other words, the signal processing unit 50 and the control unit 60 may be composed of a single IC chip. In this case, the signal processing unit 50 acquires the information regarding the number of lines per subframe, which is stored in the memory device within the control device 20, by distributing this information within the control device 20.

[0066] As described above, the control device 20 may, for example, have the function of a TCON and may also have the function of a signal processing unit 50 built in.

[0067] [2. Operation of the control device] Next, the operation of the control device 20 configured as described above will be explained with reference to Figures 6 to 10. Figure 6 is a sequence diagram showing the operation of the control device 20 according to this embodiment.

[0068] As shown in Figure 6, when power is supplied to the display device 1, the signal processing unit 50 starts up (S11), requests the number of lines in the subframe from the control unit 60 (S12), and the control unit 60 notifies the signal processing unit 50 of the number of lines in the subframe (subframe period) based on the request (S13). In steps S12 and S13, it can also be said that the signal processing unit 50 reads the number of lines per subframe from the control unit 60. The signal processing unit 50 can read the number of lines per subframe from the control unit 60 by using, for example, the DPCD (DisplayPort Configuration Data) address of eDP.

[0069] The processes in steps S12 and S13 may be performed only once during the initial startup, or they may be performed each time the setting for the number of lines of the display device 1 is changed.

[0070] Next, the signal processing unit 50 detects the start of video when it detects a signal indicating the start of a frame period (S14) and notifies the control unit 60 of the beginning of the frame (S15). The signal processing unit 50 notifies the control unit 60 of the frame in which the display of the acquired video signal will begin. The signal processing unit 50 may, for example, notify the next subframe after the current subframe as the beginning of the frame. In step S15, the signal processing unit 50 notifies, for example, that it will initialize (perform an initialization operation) in the next subframe. If the signal processing unit 50 detects a signal indicating the start of a frame period, it may output to the control unit 60 that the initialization period should be included in the extinction period in the next subframe period after the subframe period being executed at the time of detection.

[0071] Next, the signal processing unit 50 adjusts the frame duration (S16). The signal processing unit 50 adjusts the frame duration so that a subframe duration (initialization) including an initialization period is executed after a predetermined time from the time the signal is detected in step S14. After adjusting the frame duration in step S16, the signal processing unit 50 notifies the control unit 60 of the start of the next subframe.

[0072] Next, the control unit 60 performs an initialization operation to initialize the pixel circuit 30 (S17). When the control unit 60 detects a signal indicating the start of a frame period (when it receives notification of the start of the next subframe), it can also be said that it executes a subframe period that includes the initialization period within the extinction period after a predetermined time from the time the signal was detected. The subframe period that includes the initialization period is also referred to as the subframe period (initialization). The subframe period (initialization) is the first subframe period among the multiple subframe periods that constitute the frame period as a frame period.

[0073] Initialization of the pixel circuit 30 involves applying a reverse bias to the light-emitting element 32 and the EL capacitor 39 to initialize them, and correcting (resetting) the electrode voltage of the pixel capacitor 38 to match the characteristic deviation of the drive transistor 33, before accumulating (writing) the charge corresponding to the signal voltage in the pixel capacitor 38. The initialization period of the pixel circuit 30 is the period during which the light-emitting element 32 and the EL capacitor 39 are initialized by applying a reverse bias, and the electrode voltage of the pixel capacitor 38 is corrected (reset) to match the characteristic deviation of the drive transistor 33. In this embodiment, the light-emitting element 32 is extinguished during the initialization period of the pixel circuit 30. In other words, the initialization period of the pixel circuit 30 is included in the extinguishing period (also called the non-emitting period).

[0074] Next, the signal processing unit 50 adjusts the timing and outputs the video signal to the control unit 60 in accordance with the writing timing (S18). The signal processing unit 50 outputs the video signal to the control unit 60 at time intervals of the subframe period, for example. It can also be said that the signal processing unit 50 performs frame rate conversion processing according to the subframe period.

[0075] Then, after initializing the pixel circuit 30 in step S17, the control unit 60 starts writing the video signal from the signal processing unit 50 to the pixel circuit 30.

[0076] The processes in steps S14 to S18 are repeated every frame.

[0077] Here, the input and output of video signals in the signal processing unit 50 will be explained with reference to Figure 7. Figure 7 is a schematic diagram illustrating the timing of writing and reading video signals to and from the frame memory 51 of the signal processing unit 50 according to this embodiment.

[0078] The horizontal axis in Figure 7 represents time. The upper part of the vertical axis in Figure 7 represents the writing of video signals to the frame memory 51, and can also be said to represent the writing timing of video signals from the signal source 70. The lower part of the vertical axis represents the reading of video signals from the frame memory 51, and can also be said to represent the output timing of video signals to the control unit 60. Figure 7 also shows the input and output timings to the frame memory 51 for six frames of video signals I1 to I6.

[0079] Figure 7 also shows the case where the 1-frame period is 144Hz, the sub-frame period is 720Hz, and the sub-frame period is constant. Times t11, t12, t16, t20, t22, and t24 indicate the start timing of writing to video signals I1, I2, I3, I4, I5, and I6, respectively. Times t13, t15, t17, t19, and t23 indicate the start timing of reading to video signals I2, I2, I3, I3, and I4, respectively. The period between times t17 and t18 is the 1-frame period, which in this embodiment is 6.94ms (144Hz). Time t14 indicates the completion timing of the first output of video signal I2, time t17 indicates the completion timing of the second output of video signal I2, time t18 indicates the completion timing of the first output of video signal I3, and time t21 indicates the completion timing of the second output of video signal I3. Each of the periods between times t14 and t15, between times t18 and t19, and between times t21 and t23 is, for example, a subframe period, which in this embodiment is 1.39 ms (720 Hz).

[0080] As shown in Figure 7, the signal processing unit 50 starts writing the video signal I1 to the frame memory 51 at time t11, and reads the video signal I1 from the frame memory 51 while writing is in progress. This is because, while the video signal I1 is being written to the frame memory 51, a subframe period (1.39 ms (720 Hz)) has elapsed since the previous output, and it is time to output the video signal (a predetermined timing). The read video signal I1 is output to the control unit 60. The video signal I1 is read with almost no delay from the start of writing to the frame memory 51.

[0081] Next, the signal processing unit 50 starts writing the video signal I2 to the frame memory 51 at time t12, and reads the video signal I2 from the frame memory 51 at time t13 while writing is in progress. Time t13 is a predetermined timing (timing for each unit of subframe period). Since the subframe period elapsed immediately after the completion of reading the video signal I1, the reading of the video signal I2 starts immediately after the completion of reading the video signal I1. The read video signal I2 is output to the control unit 60. The video signal I2 is read with almost no delay from the start of writing to the frame memory 51.

[0082] Time t15 is the timing when the video signal is output after time t13. At this point, the frame memory 51 does not contain video signal I3, which is the next frame after video signal I2. In other words, the signal processing unit 50 has not acquired video signal I3. To put it another way, the frame memory 51 contains video signal I2.

[0083] At time t16, writing of the video signal I3 to the frame memory 51 begins. The newly acquired video signal I3 overwrites the output data portion of the video signal I2. While the writing of the video signal I3 is in progress, the reading of the video signal I2 is completed. This means that the video signal I3 has become readable from the frame memory 51. Then, at times t17-t18, the video signal I3 is read from the frame memory 51. Time t17 is a predetermined timing (timing for each unit of the subframe period).

[0084] Here, video signal I3 is read with a delay because video signal I2 is being read at the time writing to frame memory 51 begins. For example, video signal I3 is read with a delay of about half a vertical period from the start of writing to frame memory 51. The delay in reading video signal I3 is greater than that of video signals I1 and I2. Note that one vertical period corresponds to, for example, one frame period.

[0085] Time t23 is a predetermined timing (timing for each unit of the subframe period). Time t21 is not a predetermined timing.

[0086] At time t20, writing of the video signal I4 to the frame memory 51 begins. The newly acquired video signal I4 overwrites the output data portion of the video signal I3. While the writing of the video signal I4 is in progress, the reading of the video signal I3 is completed. This means that the video signal I4 has become readable from the frame memory 51.

[0087] Next, the signal processing unit 50 starts reading the video signal I4 from time t23. The signal processing unit 50 controls the timing of the video signal I4 to be output to the control unit 60.

[0088] Here, since video signal I4 is being read while video signal I3 is being read at the time writing to frame memory 51 begins, video signal I4 is read with a delay. For example, video signal I4 is read with a delay of about 1 vertical period + 1 subframe period (e.g., 1.39 ms) from the time writing to frame memory 51 begins. The delay in reading video signal I4 is greater than that of video signal I3. In this way, the processing delays for the video signals accumulate, and as a result, video signal I4 is read with a delay of about 1 vertical period + 1 subframe period.

[0089] Furthermore, in Figure 7, writing of the video signal I5 to the frame memory 51 begins at time t22. Since the video signal I4 has not yet been output, the video signal I5 cannot overwrite the video signal I4. Therefore, the frame memory 51 should have a storage capacity for storing the video signal I4 (storage capacity for one screen) and a storage capacity for storing the video signal I5 that is written between times t22 and t23. The maximum period between times t22 and t23 is the subframe period. In other words, while receiving the video signal I5, the signal processing unit 50 delays the output of the video signal I4 by up to the submemory period.

[0090] Therefore, the frame memory 51 has a storage capacity for one screen, as well as a storage capacity corresponding to the subframe period (a storage capacity corresponding to the delay). The frame memory 51 may, for example, have a storage capacity capable of storing video signals for one screen and the subframe period. If the frame rate of the subframe period (e.g., 720Hz) is n times the frame rate of the one-frame period (e.g., 144Hz), the frame memory 51 may have a storage capacity for one screen plus 1 / n screens. In this embodiment, since the subframe period is 720Hz (five times one frame), the frame memory 51 has a storage capacity for one screen plus 1 / 5 screens.

[0091] This makes it possible to output each video signal written to the frame memory 51 to the control unit 60 before the written video signals are deleted, in cases where it is required to output each video signal to the control unit 60.

[0092] For example, if the control unit controls the timing of outputting the video signal to the source drive circuit 16, the control unit needs a frame memory to convert the frame rate to a subframe rate unit. In such a control device, the signal processing unit and the control unit each write and read the video signal to the frame memory. In other words, the video signal is written to the frame memory twice, and the video signal is read at least twice.

[0093] On the other hand, in the control device 20 according to this embodiment, the timing control (frame rate conversion) of outputting the video signal to the source drive circuit 16 is performed by the signal processing unit 50 (e.g., scaler) rather than the control unit 60 (e.g., TCON). In other words, in the control device 20, the signal processing unit 50 performs the process of converting the frame rate so that it is in subframe rate units. As a result, the control unit 60 does not need a frame memory for converting the frame rate so that it is in subframe rate units. In such a control device 20, only the writing and reading of the video signal to the frame memory 51 of the signal processing unit 50 is performed. That is, the video signal only needs to be written to the frame memory once, and the video signal only needs to be read at least once. Since power consumption is incurred each time the video signal is written to and read from the frame memory, the power consumption of the control device 20 can be reduced compared to when the control unit controls the timing (frame rate conversion) of outputting the video signal to the source drive circuit 16.

[0094] As described above, the signal processing unit 50 has a frame memory 51 with a storage capacity capable of storing video signals for one screen and for a subframe period (one subframe period), and outputs a video signal (output video signal) based on the video signal (first input video signal) stored in the frame memory 51 in units of subframe periods.

[0095] Furthermore, the storage capacity of the frame memory 51 is not limited to a storage capacity capable of storing video signals for one screen and the duration of one subframe (the duration of one subframe), but may be a storage capacity capable of storing more than one screen's worth of video signals, but less than or equal to one screen's worth and the duration of one subframe (the duration of one subframe).

[0096] Furthermore, by operating as described above, even if the video signal is not written at regular time intervals, the video signal can be read out at regular time intervals (intervals between subframe periods).

[0097] Next, the detailed operation of the control device 20 according to this embodiment will be described with reference to Figures 8 to 10. Figure 8 is a flowchart showing an overview of the operation of the control device 20 according to this embodiment in which the light emission period and the extinction period of the frame period are controlled.

[0098] As shown in Figure 8, first, the control device 20 constantly checks whether it has detected a signal indicating the start of a frame period (S21). The signal indicating the start of a frame period is the vertical synchronization signal VS or the video period signal DE. For example, the signal processing unit 50 performs this check. Step S21 corresponds to step S14 shown in Figure 6.

[0099] In step S21, if the control device 20 detects a signal indicating the start of a frame period (Yes in S21), it executes a subframe period (initialization) that includes an initialization period in the extinction period after a predetermined time from the time the signal was detected (S22). The subframe period (initialization) is the first subframe period among the multiple subframe periods that constitute the frame period. Step S22 corresponds to step S17 shown in Figure 6.

[0100] Next, the control device 20 executes a subframe period (extinction) (S23). The subframe period (extinction) is a subframe period that, as a frame period, excludes the first subframe period from among the multiple subframe periods that constitute the frame period.

[0101] Next, if the control device 20 detects a signal indicating the start of a frame period while executing the subframe period (extinction) in step S23 (Yes in S24), it returns to step S22 and, after a predetermined time, executes the subframe period (initialization) after the end of the currently executing subframe period (extinction). On the other hand, if the control device 20 does not detect a signal indicating the start of a frame period while executing the subframe period (extinction) (No in S24), it returns to step S23 and executes the subframe period (extinction) after the end of the currently executing subframe period (extinction). For example, the determination in step S24 is made by the signal processing unit 50.

[0102] Next, the detailed operation when executing the subframe period (initialization) and the subframe period (extinction) will be explained with reference to Figures 9A to 10. Figure 9A is a flowchart showing the detailed operation of step S22 shown in Figure 8. Figure 9B is a flowchart showing the detailed operation of step S23 shown in Figure 8. Figure 10 is a diagram showing an example of the detailed operation of the control device 20 according to this embodiment that controls the light emission period and the extinction period of the frame period. In Figure 10, as an example, an example is shown in which one frame period is 144 Hz, the subframe period is 720 Hz (1.39 ms), and one frame period consists of five subframe periods.

[0103] First, the detailed operation of step S22 shown in Figure 9A will be explained. That is, as shown in Figure 9A, in step S22, the control unit 60 of the control device 20 starts the subframe period (initialization) (S31) after a predetermined time has elapsed since the signal processing unit 50 detected a signal indicating the start of a frame period. In this embodiment, the control unit 60 starts the subframe period (initialization) using the count value of a line counter (not shown) of the control device 20. In the example shown in Figure 10, the control unit 60 starts the subframe period SF1 (WS extinction) after a predetermined time has elapsed since the signal processing unit 50 detected the vertical synchronization signal VS. The subframe period SF1 (WS extinction) corresponds to the subframe period (initialization). The line counter is, for example, a timer, and counts independently for each line.

[0104] Next, the control unit 60 determines whether the offset time ot1 has elapsed since the start of the subframe period SF1 (WS extinction) (S32).

[0105] In step S32, the control unit 60 determines from the line counter count value that an offset time ot1 has elapsed since the start of the subframe period (initialization) (Yes in S32), and starts the initialization sequence (S33). If the offset time ot1 has not elapsed (No in S32), the control unit 60 will wait until the offset time ot1 has elapsed.

[0106] In this embodiment, the control unit 60 starts the initialization sequence using the count value of an initialization period counter (not shown) in the control device 20. In the example shown in Figure 10, during the subframe period SF1 (WS extinction), after the offset time ot1 has elapsed, the control unit 60 generates a gate control signal with the extinction signal EN and control signal INI set to high levels and outputs it to the gate drive circuit 14, thereby starting the initialization sequence. This allows the light-emitting element 32 of the pixel circuit 30 of the display panel 10 to be extinct. The initialization period counter is, for example, a timer, which counts from the start to the end of the extinction period, which includes the initialization period of the subframe period.

[0107] Next, the control unit 60 determines whether initialization is complete (S34). In this embodiment, the control unit 60 determines that the initialization of the pixel circuit 30 is complete using the count value of the initialization period counter. In the example shown in Figure 10, the control unit 60 completes the initialization in the subframe period SF1 (WS extinction) according to the count value of the initialization period counter, indicating that initialization is complete. After the start of the initialization sequence, the control unit 60 generates a gate control signal by setting the extinction signal EN and the control signal INI to a low level, setting the control signal REF to a high level for a certain period of time, and then setting it to a low level, and outputs this to the gate drive circuit 14 to complete the initialization.

[0108] In step S34, the control unit 60 determines that initialization is complete based on the count value of the initialization period counter (Yes in S34), and then starts writing to the pixel circuit 30 (S35). In this embodiment, the control unit 60 uses the count value of the initialization period counter to perform the writing to the pixel circuit 30. In the example shown in Figure 10, during the subframe period SF1 (WS extinction), the control unit 60 generates a gate control signal that sets the control signal REF to a low level and then the control signal WS to a high level for a certain period of time, according to the count value of the initialization period counter. The control unit 60 then outputs the generated gate control signal to the gate drive circuit 14 to start writing.

[0109] Next, the control unit 60 determines whether the writing is complete (S36). In this embodiment, the control unit 60 uses the count value of the initialization period counter to determine that the writing to the pixel circuit 30 is complete. In the example shown in Figure 10, the control unit 60 completes the writing to the pixel circuit 30 in the subframe period SF1 (WS extinction) according to the count value of the initialization period counter, thus indicating that the writing is complete.

[0110] In step S36, the control unit 60 determines from the count value of the initialization period counter that the write operation is complete (Yes in S36), and then determines whether an offset time ot2 has elapsed since the completion of the write operation (S37).

[0111] In step S37, the control unit 60 determines from the line counter count value that an offset time ot2 has elapsed since the completion of the write operation (Yes in S37), and then terminates the subframe period (initialization) (S38). In other words, the control unit 60 terminates the subframe period SF1 (WS extinction) shown in Figure 10.

[0112] Furthermore, if the offset time ot2 has not elapsed (No in S37), the control unit 60 will wait until the offset time ot2 has elapsed. In this embodiment, the control unit 60 uses the count values ​​of the line counter and the initialization period counter to terminate the subframe period (initialization). In the example shown in Figure 10, the control unit 60 terminates the subframe period SF1 (WS extinction) when the offset time ot2 has elapsed from the time the write operation is completed.

[0113] Next, the detailed operation of step S23 shown in Figure 9B will be described. That is, as shown in Figure 9B, in step S23, the control unit 60 starts a subframe period (extinction) following the subframe period (initialization) or the previous subframe period (extinction) (S41). In this embodiment, the control unit 60 starts the subframe period (extinction) using the count value of the line counter. In the example shown in Figure 10, the control unit 60 starts the subframe period SF2 (EN+INI extinction) from the end of the subframe period SF1 (WS extinction). The subframe period SF2 (EN+INI extinction) corresponds to the subframe period (extinction).

[0114] Furthermore, the control unit 60 starts subframe period SF3 (EN+INI extinction) at the end of subframe period SF2 (EN+INI extinction). The same applies to subframe periods SF4 (EN+INI extinction) and SF5 (EN+INI extinction).

[0115] Next, the control unit 60 determines whether the offset time ot1 has elapsed since the start of the subframe period (extinction) (S42). Note that the offset time ot1 may be set to the same time as the offset time ot1 in step S32, or it may be set to a different time.

[0116] In step S42, the control unit 60 determines from the line counter count value that an offset time ot1 has elapsed since the start of the subframe period (extinction) (Yes in S42), and starts the extinction operation (S43). If the offset time ot1 has not elapsed (No in S42), the control unit 60 waits until the offset time ot1 has elapsed. In this embodiment, the control unit 60 uses the count value of the extinction period counter to start the extinction operation of the pixel circuit 30. In the example shown in Figure 10, for example, in the subframe period SF2 (EN+INI extinction), after the offset time ot1 has elapsed, the control unit 60 generates a gate control signal with the extinction signal EN and the control signal INI at a high level and outputs it to the gate drive circuit 14 to start the extinction operation (extinction period). This makes it possible to extinguish the light-emitting element 32 of the pixel circuit 30 of the display panel 10.

[0117] Next, the control unit 60 determines whether the extinction period has elapsed (S44).

[0118] In step S44, the control unit 60 determines from the count value of the extinction period counter that the extinction period of the pixel circuit 30 has ended (Yes in S44), and then causes the light-emitting element 32 of the pixel circuit 30 to emit light again (S45).

[0119] In this embodiment, the control unit 60 uses the count value of the extinction period counter to determine when the extinction period of the pixel circuit 30 has elapsed. In the example shown in Figure 10, the control unit 60 completes the extinction period of the pixel circuit 30 in the subframe period SF2 (EN + INI extinction) according to the count value of the extinction period counter, thereby indicating that the extinction period has been completed. After the extinction period ends, the control unit 60 generates a gate control signal that sets the extinction signal EN and the control signal INI to a low level and outputs it to the gate drive circuit 14, thereby completing the extinction period. This allows the control unit 60 to re-illuminate the light-emitting element 32 of the pixel circuit 30. In the example shown in Figure 10, the control unit 60 generates a gate control signal that sets the extinction signal EN and the control signal INI to a low level in the subframe period SF2 (EN + INI extinction) according to the count value of the extinction period counter and outputs it to the gate drive circuit 14. As a result, the control unit 60 can complete the quenching period during the subframe period SF2 (EN + INI quenching) and re-illuminate the light-emitting element 32 of the pixel circuit 30.

[0120] Next, the control unit 60 determines whether the offset time ot2 has elapsed since the extinction period ended (S46).

[0121] In step S46, the control unit 60 determines from the line counter count value that an offset time ot2 has elapsed since the end of the extinction period (Yes in S46), and terminates the subframe period (extinction) (S47). If the offset time ot2 has not elapsed (No in S46), the control unit 60 waits until the offset time ot2 has elapsed. In this embodiment, the control unit 60 terminates the subframe period (extinction) using the count values ​​of the line counter and the extinction period counter. In the example shown in Figure 10, the control unit 60 terminates the subframe period SF2 (EN+INI extinction) when an offset time ot2 has elapsed since the end of the extinction period.

[0122] Note that while Figure 10 above uses the vertical synchronization signal VS as an example to illustrate the start of a frame period, it is not limited to this. The video period signal DE may also be used.

[0123] As described above, the control device 20 controls at least the illumination period and the extinction period of a frame period, which is the period during which the same image is continuously displayed. The control device 20 distributes (divides) the extinction period of a frame period by composing each frame period into multiple subframe periods in which the illumination period and the extinction period are repeated at regular time intervals. In this way, the control device 20 can distribute the extinction period in a frame period and repeat the illumination period and the extinction period at regular time intervals by dividing one frame period into multiple subframe periods of a certain length and executing them.

[0124] Furthermore, even if the number of vertical lines is not known in advance, and even if the frame duration always or sometimes fluctuates significantly, the control device 20 can repeat on-duty and off-duty cycles of predetermined lengths at a fixed period called the subframe duration. This makes it possible to prevent flicker from being visible on the display panel 10 that displays the image, even if the frame duration fluctuates significantly. In other words, the flicker phenomenon can be suppressed even if the frame duration fluctuates.

[0125] Furthermore, if the control device 20 detects a signal indicating the start of the next frame period while the last subframe period constituting the frame period is being executed, it starts the first subframe period of the next frame period immediately following the last subframe period. This allows the control device to easily track fluctuations in the frame period, thereby suppressing the flicker phenomenon even when the frame period fluctuates.

[0126] [3. Effects, etc.] A control device 20 according to one aspect of this disclosure is a control device for a display panel 10 in which the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range for each frame or temporarily stabilizes, but the exact frame period is not known in advance. The control device 20 includes a signal processing unit 50 that changes the number of subframe periods to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods regardless of the input frame period, controls the display of an image, and outputs an output video signal based on the input first input video signal in units of subframe periods, and a control unit 60 that supplies the output video signal output from the signal processing unit 50 and a control signal that controls the operation of the display panel 10 to the display panel 10.

[0127] As a result, the control unit 60 does not need a frame memory for converting the frame rate to subframe rate units, and the video can be displayed by writing and reading the video signal to the frame memory 51 of the signal processing unit 50 alone. In other words, the video signal only needs to be written to the frame memory once, and the video signal only needs to be read at least once. Therefore, the control device 20 according to this embodiment can reduce the power consumption required for writing and reading the video signal to the frame memory compared to when the video signal is written and read in the frame memories of the signal processing unit 50 and the control unit 60 respectively.

[0128] Furthermore, the signal processing unit 50 has a frame memory 51 (an example of a memory) having a storage capacity capable of storing more than one screen's worth of first input video signals, but less than or equal to one screen's worth and the subframe period, and outputs an output video signal based on the first input video signals stored in the frame memory 51 in units of the subframe period.

[0129] As a result, the signal processing unit 50 can output the video signal with a delay of up to the duration of a subframe. Therefore, the skipping of acquired video signals in the signal processing unit 50 is suppressed, and the video signal can be output more reliably.

[0130] Furthermore, of the signal processing unit 50 and the control unit 60, only the signal processing unit 50 has a frame memory 51 for storing the first input video signal.

[0131] This eliminates the need for a frame memory in the control unit 60, thereby reducing the cost of the control device 20.

[0132] Alternatively, for example, the signal processing unit 50 may obtain information from the control unit 60 indicating the number of lines (an example of the number of display lines) during the subframe period of the display panel 10, and generate an output video signal based on this information.

[0133] As a result, the signal processing unit 50 can generate a video signal to be output to the control unit 60, that is, to be output to the display panel 10, without acquiring information from outside the control device 20.

[0134] Furthermore, for example, the signal processing unit 50 may read information indicating a preset number of lines during the subframe period of the display panel 10, and generate an output video signal based on the read information.

[0135] As a result, the signal processing unit 50 can generate a video signal to be output to the control unit 60, that is, to be output to the display panel 10, simply by reading information indicating the number of display lines that has been set in advance.

[0136] Furthermore, the signal processing unit 50 and the control unit 60 are configured on a single chip.

[0137] This allows for easy communication between the signal processing unit 50 and the control unit 60 without the need for wiring formed on the circuit board.

[0138] Furthermore, the control unit 60 configures each of the n subframe periods to be a predetermined period of the same length.

[0139] This ensures that the length of each subframe period is the same, making it possible to reduce the visibility of flicker compared to when the lengths differ. In other words, flicker can be suppressed even when the frame duration varies.

[0140] Furthermore, each of the n subframe periods has an illumination period and an extinction period, and the control unit 60 controls the duty cycle, which is the ratio of the illumination period to the extinction period, to be the same predetermined ratio.

[0141] This allows the illumination and extinction periods to be repeated at regular time intervals using multiple subframe periods. Therefore, even if the frame period fluctuates significantly, flicker can be prevented from being seen on the display panel 10 that displays the image. In other words, the flicker phenomenon can be further suppressed even when the frame period fluctuates.

[0142] Furthermore, the pixels constituting the display panel 10 consist of light-emitting elements that emit light by current drive, including organic EL elements.

[0143] This makes it possible to prevent flicker from being visible on the OLED display panel 10 even if the frame duration fluctuates significantly due to the processing power of the GPU, etc. In other words, even if the frame duration fluctuates, the flicker phenomenon on the OLED display panel 10 can be suppressed.

[0144] Furthermore, the frame memory 51 has a storage capacity capable of storing the first input video signal for one screen and for the duration of a subframe.

[0145] This allows the signal processing unit 50 to output the video signal with a delay equal to the subframe period.

[0146] Furthermore, a display device 1 according to one aspect of this disclosure comprises the control device 20 described above, a display panel 10 having a gate drive circuit 14 to which control signals from the control device 20 are input, and a source drive circuit 16 to which output video signals from the control device 20 are input.

[0147] This makes it possible to realize a display device 1 that can reduce power consumption.

[0148] Furthermore, a control method according to one aspect of this disclosure is a control method for a display panel 10 in which the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range for each frame or temporarily stabilizes, but the exact frame period is not known in advance. The control method includes changing the number of subframe periods so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods, regardless of the input frame period, and displaying the image. It also includes outputting an output video signal based on the input video signal in units of subframe periods (S18), and supplying the output video signal and a control signal for controlling the operation of the display panel 10 to the display panel 10 (S22, S23).

[0149] This produces the same effect as the control device 20 described above.

[0150] (Modified example of the embodiment) The control device according to this modified example will be described below with reference to Figure 11. Figure 11 is a schematic diagram illustrating the timing of writing and reading video signals to and from the frame memory 51 of the signal processing unit 50 according to this modified example. In the following description, the differences from the embodiment will be the main focus, and the same or similar content as in the embodiment will be omitted or simplified. The functional configuration of the control device is the same as in the embodiment and will not be described.

[0151] The horizontal axis in Figure 11 represents time. The upper part of the vertical axis in Figure 11 represents the writing of video signals to the frame memory 51, and can also be said to represent the timing of the writing of video signals from the signal source 70. The lower part of the vertical axis represents the reading of video signals from the frame memory 51, and can also be said to represent the timing of the output of video signals to the control unit 60. Furthermore, it shows the input and output timings to the frame memory 51 for six frames of video signals I11 to I16.

[0152] Figure 11 also shows the case where the frame duration is 144Hz and the subframe duration is 720Hz with a constant subframe duration. Times t31, t32, t33, t34, t35, and t36 indicate the start timing of writing to video signals I11, I12, I13, I14, I15, and I16, respectively. Note that the processing shown for video signals I11 to I13 is the same as that shown for video signals I1 to I3 in Figure 7, and therefore the explanation is omitted.

[0153] As shown in Figure 11, after the writing of video signal I14 is completed at time t35, video signal I5 is written before video signal I14 is read. In this embodiment, if a video signal I15 different from video signal I14 is input before the signal processing unit 50 outputs a video signal based on video signal I14 stored in the frame memory 51 to the control unit 60, the signal processing unit 50 stores video signal I15 in the frame memory 51 by overwriting video signal I14 with video signal I15. If the start timing of reading video signal I14 is delayed by about one subframe period from time t35, for example, by about one vertical period + one subframe period from the start timing of writing video signal I14, the signal processing unit 50 overwrites video signal I14 with video signal I15 without reading video signal I14. Thus, if the signal processing unit 50 reads video signal I4, for example, if the read timing of video signal I4 is delayed by more than one frame period from the writing of video signal I4 to the frame memory 51, it will overwrite video signal I4 with the next video signal I5 without reading video signal I4. The signal processing unit 50 will also overwrite video signal I14 with video signal I15 even if the currently stored video signal (for example, video signal I14) has not been read by the start of reception of the next video signal (for example, video signal I15). In other words, the signal processing unit 50 skips video signal I14 (one frame). The frame memory 51 only needs to have a storage capacity equivalent to one screen, for example. Note that video signal I14 is an example of a first input video signal, and video signal I15 is an example of a second input video signal.

[0154] In one aspect of the present disclosure, the signal processing unit 50 of the control device 20 overwrites the video signal I4 with the next video signal I5 (an example of a second input video signal) without reading the video signal I4 if the timing of reading the video signal I4 (an example of a first input video signal) is delayed by one frame period or more from the time the video signal I4 is written to the frame memory 51 (an example of a memory).

[0155] As a result, the frame memory 51 of the signal processing unit 50 does not need to have a storage capacity corresponding to the subframe period. Therefore, the storage capacity of the frame memory 51 can be further reduced.

[0156] (Other embodiments) Although control devices and the like according to one or more embodiments have been described above based on each embodiment, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications that a person skilled in the art could conceive of may be applied to these embodiments, and forms constructed by combining components from different embodiments may also be included in this disclosure.

[0157] For example, in the above embodiment, the frame memory of the signal processing unit was described as a 1W1R type memory, but it may also be a 1WR type memory in which two ports, write and read, are shared.

[0158] Furthermore, in the above embodiments, an example was described in which the pixels constituting the display panel for displaying an image are organic EL elements, but they may also be liquid crystal elements. In this case, the light emission period may be the period during which the backlight is turned on in the backlight scan, and the blackout period may be the period during which the backlight is turned off.

[0159] This makes it possible to prevent flicker from being visible on a liquid crystal display panel even if the frame duration of the backlight scan fluctuates significantly. In other words, it is possible to suppress the flicker phenomenon on a liquid crystal display panel even if the frame duration of the backlight scan fluctuates.

[0160] Furthermore, the control unit in the above embodiment may have memory for functions other than delaying the video signal.

[0161] Furthermore, in the modified embodiment described above, an example was given in which a later acquired video signal is preferentially stored (overwritten). However, the invention is not limited to this, and a video signal that was stored earlier and has not yet been output may be preferentially stored. For example, a later acquired video signal may be discarded without being stored if the video signal that was acquired and stored earlier has not yet been output.

[0162] Furthermore, in the above embodiments, each component may be implemented by being composed of dedicated hardware or by executing a software program suitable for each component. Each component may also be implemented by a program execution unit such as a CPU (Central Processing Unit) or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0163] Furthermore, the order in which each step in the flowchart is performed is illustrative for the purpose of specifically illustrating this disclosure, and may be in a different order. Also, some of the above steps may be performed simultaneously (in parallel) with other steps, and some of the above steps may not be performed.

[0164] Furthermore, the division of functional blocks in the block diagram is just one example; multiple functional blocks can be implemented as a single functional block, a single functional block can be divided into multiple parts, or some functions can be moved to other functional blocks. In addition, the functions of multiple functional blocks with similar functions can be processed in parallel or time-sharing by a single piece of hardware or software.

[0165] Furthermore, the control device according to the above embodiments may be implemented as a single device or as a plurality of devices. When the control device is implemented as a plurality of devices (for example, a signal processing unit and a control unit), the method of communication between the plurality of devices is not particularly limited.

[0166] Furthermore, each component of the control device described in the above embodiments may be implemented as software, or typically as an integrated circuit (LSI). These may be individually integrated onto a single chip, or some or all of them may be integrated onto a single chip. Here, we refer to it as an LSI, but depending on the degree of integration, it may also be called an IC, system LSI, super LSI, or ultra LSI. Moreover, the method of integrated circuit implementation is not limited to LSIs; it may also be implemented using dedicated circuits or general-purpose processors. After LSI manufacturing, an FPGA (Field Programmable Gate Array) that can be programmed or a reconfigurable processor that can reconfigure the connections or settings of circuit cells inside the LSI may be used. Furthermore, if an integrated circuit implementation technology that replaces LSIs emerges due to advances in semiconductor technology or other derived technologies, it is naturally possible to integrate the components using that technology.

[0167] A system LSI is a highly functional LSI manufactured by integrating multiple processing units onto a single chip. Specifically, it is a computer system consisting of a microprocessor, ROM (Read Only Memory), RAM (Random Access Memory), and other components. The ROM stores the computer program. The system LSI achieves its function by operating according to the computer program, with the microprocessor performing its operations.

[0168] Furthermore, one aspect of this disclosure may be a computer program that causes a computer to perform each characteristic step included in the control method shown in Figures 6 and 8 to 9B.

[0169] Furthermore, for example, the program may be a program to be executed by a computer. Also, in one aspect of this disclosure, such a program may be recorded on a computer-readable non-temporary recording medium. For example, such a program may be recorded on a recording medium and distributed or made available. For example, by installing the distributed program on a device having another processor and having that processor execute the program, it becomes possible to have that device perform the above-mentioned processes.

[0170] Furthermore, these general or specific embodiments may be implemented as a system, method, integrated circuit, computer program, or a non-temporary recording medium such as a computer-readable CD-ROM, or as any combination of a system, method, integrated circuit, computer program, or recording medium. The program may be pre-stored on the recording medium or supplied to the recording medium via a wide-area communication network, including the Internet. [Industrial applicability]

[0171] This disclosure is particularly useful in technical fields such as television systems, game consoles, and personal computer displays where high-speed and high-resolution display is required. [Explanation of symbols]

[0172] 1 Display device 10 Display Panel 12 Display section 14 Gate drive circuit 16 Source drive circuit 20 Control device 30-pixel circuit 32 Light-emitting elements 33 drive transistors 34, 36, 37 Switch transistors 35 Selective Transistors 38 pixels capacity 39EL capacity 40 scan lines 42 signal lines 50 Signal Processing Unit 51 frame memory 60 Control Unit 70 Signal source

Claims

1. A control device for a display panel that controls the frame duration, which is the period during which the same image is continuously displayed, when the exact frame duration is unknown in advance, The control device changes the number of subframe periods so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods, regardless of the input frame period, and performs control to display the image. A signal processing unit that outputs an output video signal based on the input first input video signal in units of the subframe period, The system includes a control unit that supplies the output video signal output from the signal processing unit and a control signal for controlling the operation of the display panel to the display panel, The signal processing unit controls the timing of supplying the output video signal to the display panel. The signal processing unit has a memory having a storage capacity capable of storing the first input video signal for more than one screen and less than or equal to one screen and the subframe period, and outputs the output video signal based on the first input video signal stored in the memory in units of the subframe period. Control device.

2. If the timing of reading the first input video signal is delayed by one frame or more from the time the first input video signal is written to the memory, the signal processing unit overwrites the first input video signal with the second input video signal that follows the first input video signal without reading the first input video signal. The control device according to claim 1.

3. Of the signal processing unit and the control unit, only the signal processing unit has the memory for storing the first input video signal. The control device according to claim 2.

4. The signal processing unit obtains information from the control unit indicating the number of display lines in the subframe period of the display panel, and generates the output video signal based on the information. The control device according to any one of claims 1 to 3.

5. The signal processing unit reads information indicating the number of display lines in the subframe period of the display panel, which is a preset number of display lines, and generates the output video signal based on the read information. The control device according to any one of claims 1 to 3.

6. The signal processing unit and the control unit are configured on a single chip. The control device according to any one of claims 1 to 5.

7. The control unit configures each of the n subframe periods to be a predetermined period of the same length. The control device according to any one of claims 1 to 6.

8. Each of the n subframe periods has an illumination period and an extinction period. The control unit controls the duty cycle, which is the ratio of the light emission period to the quenching period, to be the same predetermined ratio. The control device according to any one of claims 1 to 7.

9. The pixels constituting the display panel consist of light-emitting elements that emit light by current drive, including organic EL elements. The control device according to any one of claims 1 to 8.

10. The memory has a storage capacity capable of storing the first input video signal for one screen and for the duration of the subframe. The control device according to any one of claims 1 to 3.

11. A control device according to any one of claims 1 to 10, The display panel comprises a gate drive circuit to which the control signal from the control device is input, and a source drive circuit to which the output video signal from the control device is input. Display device.

12. A control method executed by a control device for a display panel that controls the frame duration, which is the period during which the same image is continuously displayed, when the exact frame duration is unknown in advance, The control device comprises a signal processing unit and a control unit, The control method includes changing the number of subframe periods so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframe periods, regardless of the input frame period, and displaying the image. moreover, The signal processing unit outputs an output video signal based on the input video signal, in units of the subframe period. The control unit includes supplying the output video signal output from the signal processing unit and a control signal for controlling the operation of the display panel to the display panel, In the output in units of the aforementioned subframe period, the signal processing unit controls the timing of supplying the output video signal to the display panel. The signal processing unit has a memory with a storage capacity capable of storing the input video signal for more than one screen and less than or equal to one screen and the subframe period. The control method outputs the output video signal based on the input video signal stored in the memory in units of the subframe period. Control method.

Images