Video operation in follower mode

Abstract

To provide improved systems and methods for synchronizing clock signals between different devices.SOLUTION: A method may include receiving, via a processor, a frame of image data 50, such that the frame of image data 50 may include a vertical active portion 58 and an idle portion 60. The vertical active portion 58 may include data for presenting one or more images via a first display of a first electronic device. The method may also include receiving a signal from a second electronic device during the idle portion 60 of the frame of image data, such that the second electronic device is separate from the first display. The method may then involve initiating processing of the frame of image data in response to the signal being received from the second electronic device.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the priority and benefit of U.S. Provisional Patent Application No. 63 / 078,300, filed on September 14, 2020, which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present disclosure generally relates to using signals between different display devices to utilize different video operation modes in an electronic device.

Background Art

[0003] In this section, various aspects that may be related to the various aspects of the present technology described hereinafter and / or claimed are introduced to the reader. This discussion is considered to be helpful in providing the reader with background art for facilitating a better understanding of the various aspects of the present disclosure. Thus, it should be understood that these descriptions should be read from the above - mentioned perspective and should not be read as an admission of prior art.

[0004] An integrated electronic display may operate using a common clock signal with a corresponding image processing circuit. However, when preparing image data for display via an external display, the common clock signal and the clock signal for the external display may drift relative to each other. Thus, improved systems and methods for synchronizing clock signals between different devices may be useful.

Summary of the Invention

[0005] A summary of certain embodiments disclosed herein is described below. It should be understood that these aspects are presented merely to provide the reader with a summary of certain embodiments and are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may encompass various aspects not described below.

[0006] This disclosure relates in general to electronic displays, and more specifically to improving coordination between two electronic devices to display image data using two electronic displays. As described above, an integrated electronic display may operate based on a common clock signal with the image processing circuitry (e.g., display pipeline) of the electronic device. The image processing circuitry can prepare image data for the electronic display, and the electronic display can display the image data based on the common clock signal. However, an external display may not use the same common clock signal. That is, an external display may use a separate clock signal to coordinate the presentation of image data via the external display. However, when the image processing circuitry is used to provide image data to the electronic display and the external display connected to it, drift between the two clock signals may cause the image data provided to the external display and the electronic device to become out of sync.

[0007] Considering the above, in some embodiments, the image processing circuit of an electronic device may prepare image data for an external display so that the image processing circuit acts as a follower of the external display. That is, the external display may adjust or control the timing of the image processing circuit. In some embodiments, the image processing circuit may receive a frame of image data that includes a period or portion of the image data frame corresponding to an idle state. The image processing circuit may wait for an external trigger signal during the idle state to begin processing the next frame, thereby ensuring that the image processing circuit and the external display remain synchronized. [Brief explanation of the drawing]

[0008] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the following drawings.

[0009] [Figure 1]This is a block diagram of an electronic device having a display, including a hardware accelerator, according to one embodiment of the present disclosure.

[0010] [Figure 2] This is an example of an electronic device shown in Figure 1, according to one embodiment of the present disclosure.

[0011] [Figure 3] This is another example of the electronic device shown in Figure 1, according to one embodiment of the present disclosure.

[0012] [Figure 4] This is another example of the electronic device shown in Figure 1, according to one embodiment of the present disclosure.

[0013] [Figure 5] This is another example of the electronic device shown in Figure 1, according to one embodiment of the present disclosure.

[0014] [Figure 6] This is a block diagram representing different frames of image data according to one embodiment of the present disclosure.

[0015] [Figure 7] This is a flowchart of a method, according to one embodiment of the present disclosure, for adjusting the processing of image frame data using an image processing circuit based on a signal received by an external display.

[0016] [Figure 8] This is a timing diagram of image data frames according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0017] One or more specific embodiments of the present disclosure are described below. These embodiments described are merely examples of the technology disclosed herein. Furthermore, not all features of actual embodiments are shown herein in order to provide a concise description of these embodiments. It should be understood that, as in any engineering or design project, in the development of any such actual implementation, a number of implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints that may vary from implementation to implementation. Furthermore, it should be understood that while development efforts can be complex and time-consuming, they can still be part of the normal business of design, fabrication, and manufacturing for those skilled in the art who are interested in the present disclosure.

[0018] When introducing elements of the various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more elements. The terms “including” and “having” are intended to be inclusive and mean that there may be additional elements beyond those enumerated. Furthermore, it should be understood that the references to “one embodiment,” “an embodiment,” “embodiments,” and “some embodiments” in this disclosure are not intended to be construed as excluding the existence of additional embodiments that incorporate the enumerated features.

[0019] As described above, the image processing circuit of an electronic device may prepare image data for an external display so that the image processing circuit acts as a follower of the external display. In this way, the external display can control the timing of the image processing circuit. Further details regarding the use of the image processing circuit as a follower of an external display are described below with reference to Figures 1 to 8.

[0020] First, FIG. 1 shows a block diagram of an electronic device 10. The electronic device 10 can be any suitable electronic device such as a computer, a mobile phone, a portable media device, a wearable device, a tablet, a television, a virtual reality headset, and a vehicle dashboard. Thus, note that FIG. 1 is only one example of a particular implementation and is intended to illustrate the types of components that can exist within the electronic device 10.

[0021] In the illustrated embodiment, the electronic device 10 includes an electronic display 12, one or more input devices 14, one or more input / output (I / O) ports 16, a processor 18 having one or more processors or processor cores, a local memory 20, a main memory storage device 22, a network interface 24, and a power supply 26. The various components described in FIG. 1 may include hardware elements (e.g., circuits), software elements (e.g., tangible non-transitory computer-readable media storing instructions), or combinations of both hardware and software elements. Note that the various components shown may be combined into fewer components or separated into additional components. For example, the local memory 20 and the main memory storage device 22 can be included in a single component.

[0022] Processor 18 can execute operations such as generating and / or transmitting image data by executing instructions stored in local memory 20 and / or main memory storage device 22. Thus, processor 18 can include one or more processors such as one or more microprocessors, one or more application specific processors (ASICs), one or more field programmable logic arrays (FPGAs), one or more graphics processing units (GPUs). Further, as described above, processor 18 can include one or more separate processing logic cores that each process data according to executable instructions.

[0023] Local memory 20 and / or main memory storage device 22 can store executable instructions and data to be processed by the cores of processor 18. Thus, local memory 20 and / or main memory storage device 22 can include one or more tangible non-transitory computer-readable media. For example, local memory 20 and / or main memory storage device 22 can include rewritable non-volatile memory such as random access memory (RAM), read only memory (ROM), flash memory, hard drive, optical disk, etc.

[0024] The network interface 24 can facilitate communication of data with other electronic devices via a network connection. For example, the network interface 24 (e.g., a radio frequency system) can enable the electronic device 10 to communicate with a personal area network (PAN) such as a Bluetooth® network, a local area network (LAN) such as an 802.11x Wi-Fi® network, and / or a wide area network (WAN) such as a 4G, LTE, or 5G cellular network. The network interface 24 includes one or more antennas configured to communicate via the network connected to the electronic device 10. The power supply 26 may include any suitable energy source such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0025] The I / O port 16 may allow the electronic device 10 to receive input and / or output data using port connections. For example, a portable storage device can be connected to the I / O port 16 (e.g., a Universal Serial Bus, USB) to allow the processor 18 to communicate data with the portable storage device. The I / O port 16 may include one or more speakers that output audio from the electronic device 10. The processor 18 may include one or more coprocessors or other microprocessors configured to complement the capabilities of the primary processor (e.g., a central processing unit).

[0026] The input device 14 can facilitate user interaction with the electronic device 10 by receiving user input. For example, the input device 14 may include one or more buttons, a keyboard, a mouse, a trackpad, and / or similar. The input device 14 may also include one or more microphones that can be used to capture sound. The input device 14 may include a touch sensing component within the electronic display 12. In such embodiments, the touch sensing component can receive user input by detecting the presence and / or location of an object touching the surface of the electronic display 12.

[0027] The electronic display 12 may include a display panel having one or more display pixels. The electronic display 12 can display an image frame based at least partially on corresponding image data by controlling the light emission from the display pixels, thereby presenting a visual representation of information, such as a graphical user interface (GUI) of an operating system, an application interface, a still image, or video content. In some embodiments, the electronic display 12 may be a liquid crystal display (LCD), a self-emissive display such as an organic light-emitting diode (OLED) display, etc.

[0028] The electronic display 12 can receive image data to be displayed via the image processing circuit 27. The image processing circuit 27, or display pipeline, may include one or more circuit components that process the image data provided by the processor 18 in order to enable the display 12 to display the image data. Thus, the image processing circuit 27 may include components for performing various operations such as correction (e.g., application of Bayer filter), noise reduction, image scaling, gamma correction, image enhancement, color space conversion (e.g., between formats such as RGB, YUV, or YCbCr), chroma subsampling, frame rate conversion, image compression / video compression (e.g., JPEG), and computer data storage / data transmission.

[0029] In some embodiments, the electronic device 10 may be communicatively coupled to an external display 28. The external display 28 may correspond to an additional display device such as a monitor or tablet screen. In addition, the external display 28 may include electronic glasses, a handheld device, or any suitable display device that may be external to or separate from the electronic device 10 and capable of presenting image data. Display 12 and the external display 28 may each operate using their respective clock signals provided by their respective clock circuits. As image data is presented over time by Display 12 and the external display 28, the clock signals received from these two clock circuits may drift relative to each other. As a result, the image data drawn on Display 12 and the external display 28 may become asynchronous. To better synchronize the presentation of image data via the external display 28 and the external display 12, the image processing circuit 27 may receive a follower-go signal from the external display 12 during a portion of the time of an image data frame. That is, each frame of image data may include an idle portion in which a follower-go signal can be received from the external display 28. In response to receiving the follower-go signal, the image processing circuit 27 processes the rest of the image data frame and provides the resulting image data to display 12 and external display 28 so that the two displays can present the image data more synchronously. In fact, the follower-go signal ensures that display 12 operates based on the clock signal used to control external display 28, thereby ensuring that the two displays are synchronized.

[0030] As described above, the electronic device 10 may be any suitable electronic device. For illustrative purposes, one embodiment of a suitable electronic device 10, specifically a handheld device 10A, is shown in Figure 2. In some embodiments, the handheld device 10A may be a portable telephone, media player, personal data organizer, handheld game platform, and / or similar. For example, the handheld device 10A may be a smartphone, such as any IPHONE® model available from Apple Inc.

[0031] The handheld device 10A includes an enclosure 29 (e.g., a housing). The enclosure 29 can protect internal components from physical damage and / or shield them from electromagnetic interference. In the illustrated embodiment, the electronic display 12 displays a graphical user interface (GUI) 30 having an array of icons 32. For example, when an icon 32 is selected by either the input device 14 or a touch sensing component of the electronic display 12, a corresponding application program may be launched.

[0032] The input device 14 may extend through the enclosure 29. As previously mentioned, the input device 14 may enable the user to interact with the handheld device 10A. For example, the input device 14 may enable the user to record voice, activate or deactivate the handheld device 10A, navigate the user interface to the home screen, navigate the user interface to a user-configurable application screen, activate voice recognition functionality, provide volume control, and / or toggle between vibration mode and ringing mode. The I / O port 16 may also extend through the enclosure 29. In some embodiments, the I / O port 16 may include, for example, an audio jack for connecting to an external device. As previously mentioned, the I / O port 16 may include one or more speakers that output sound from the handheld device 10A.

[0033] Another embodiment of the preferred electronic device 10 is the tablet device 10B shown in Figure 3. For illustrative purposes, the tablet device 10B can be any iPad® model available from Apple Inc. A further embodiment of the preferred electronic device 10, specifically a computer 10C, is shown in Figure 4. For illustrative purposes, the computer 10C can be any MacBook® or iMac® model available from Apple Inc. Another embodiment of the preferred electronic device 10, specifically a wearable device 10D, is shown in Figure 5. For illustrative purposes, the wearable device 10D can be any Apple Watch® model available from Apple Inc. As shown, the tablet device 10B, the computer 10C, and the wearable device 10D also include an electronic display 12, an input device 14, and an enclosure 29, respectively.

[0034] Figure 6 is a block diagram showing frame portions of image data that may be used according to embodiments described herein. Referring to Figure 6, the image data 50 includes frames N, N+1, and N+2. Each frame of the image data 50 may include a vertical sync (VSYNC) portion 52, a vertical back porch (VBP) portion 54, a vertical front porch (VFP) portion 56, and a vertical active (VACTIVE) portion 58. The VSYNC portion 52 may include information about sync pulses that synchronize image data in vertical rows on the display 12. The VFP portion 56 and VBP portion 54 may provide buffering periods between the VSYNC portion 52 so that portions of the image data 50 that can be seen by the display 12 during the active area (e.g., the VACTIVE portion 58). The VACTIVE portion 58 may then provide image data for rows of pixels that are part of the display 12.

[0035] When image data 50 is used to draw an image on display 12 and an external display 28, the external display 28 may send a follower-go signal during the idle portion 60 of the image data 50. As shown in Figure 6, the idle portion 60 occurs immediately after the VACTIVE portion 58. In some embodiments, the image processing circuit 27 can receive the image data 50 from the processor 18 and process and draw the image displayed by display 12. If the image processing circuit 27 receives a follower-go signal from the external display 28 during the idle portion 60 of the image data 50, the image processing circuit 27 may proceed to the VFP portion 56 and begin processing the next frame of the image data.

[0036] With this in mind, certain applications may involve coordinating the operation of the image processing circuit 27 so that its video timing operation follows that of an external component (e.g., an external display 28). Therefore, the idle portion 60 may be used to facilitate video timing coordination between the image processing circuit 27 and the external display 28 so that the video timing of the image processing circuit 27 can be implicitly adjusted based on an external trigger. By relying on a follower-go signal to advance to the next frame of image data, the image processing circuit 27 can adapt its video timing to avoid drift between two entities operating on clocks derived from different crystals.

[0037] During the idle portion 60, the line counter of the image processing circuit 27 can be incremented at line granularity using the horizontal timing signal that is generated as usual, unless a follower-go signal is received. If a follower-go signal is received during the idle portion 60, the line counter can wait for the subsequent line boundary period before transitioning to the VFP portion 56 and continue counting as usual. By controlling the duration of the idle, the image processing circuit 27 can adjust the frame time to meet the target timing at a granularity of up to 1 line time.

[0038] An external device (e.g., an external display 28) is expected to issue a follower-go signal at a valid time. If the image processing circuit 27 receives a follower-go signal outside of the idle portion 60, the image processing circuit 27 is ignored, and an interrupt may be asserted to indicate an unexpected event due to the absence of a follower-go signal. The line number corresponding to the first such occurrence in the frame is logged by the image processing circuit 27 for debugging purposes.

[0039] If the follower-go signal is not received by the image processing circuit 27 within a configurable time (e.g., the maximum idle period), the image processing circuit 27 may transition to the VFP portion 56 of the subsequent frame with an interrupt asserted to indicate the unexpected event that the idle time has elapsed. The corresponding line number is logged by the image processing circuit 27 for debugging purposes.

[0040] With the above in mind, line interrupts between the VFP section 56, VSYNC section 52, VBP section 54, and VACTIVE section 58 behave normally, but note that the image processing circuit 27 may not configure any line interrupts during the idle section 60. In some embodiments, the image processing circuit 27 remains in the idle section 60 for at least one line to ensure sufficient time for the external display 28 to send a follower-go signal. Therefore, at startup, the image processing circuit 27 may start in the idle section 60 and wait for a follower-go signal before transitioning to the VFP section 56.

[0041] In some embodiments, an entire frame of image data may contain a specific number of lines, such that the VACTIVE portion 58 constitutes a first portion of the line count and the idle portion 60 constitutes a second portion of the line count. Each line within the frame of image data has the same duration. Therefore, the image processing circuit 27 tracks the beginning of each new line and, upon receiving a follower-go signal, may start a new frame of image data at the beginning of the next line. However, if a follower-go signal is not received, the image processing circuit 27 may instead start a new frame of image data at the beginning of a predetermined or specific line number. That is, if a follower-go signal is not received by a predetermined line number, the image processing circuit 27 may start a new frame of image data at the beginning of a predetermined or specific line number.

[0042] Figure 7 shows a flowchart of a method 70 that an image processing circuit 27 can perform to adjust the timing of image data 50 for two or more display devices. Although method 70 is described in a specific order, it should be understood that the method may be performed in any suitable order. In addition, although method 70 is described as being performed by an image processing circuit 27, it should be noted that any suitable processing circuit may perform the method 70 described herein.

[0043] Next, referring to Figure 7, in block 72, the image processing circuit 27 can receive the image data 50, start the line counter, and toggle the line counter at the beginning of the frame. Thus, the image processing circuit 27 can start processing the image data 50 by waiting during the idle period. As an example, Figure 8 shows a timing diagram 100 illustrating the relationship between receiving the follower-go signal and starting the processing of the image data 50, as described above.

[0044] Referring to Figure 8, at time t0, the image processing circuit 27 can start a line counter and begin toggling the line counter until it receives a follower-go signal. Referring back to Figure 7, in block 72, the image processing circuit 27 can determine whether a follower-go signal has been received from an external device (e.g., an external display 28). If no follower-go signal has been received, the image processing circuit 27 proceeds to block 76 to determine whether the maximum idle period has elapsed. The maximum idle period may be configurable by the user and can be modified over time to accommodate expected drift between the clock of the image processing circuit 27 and the clock of the external device, etc. If the maximum idle period has not elapsed, the image processing circuit 27 returns to block 74 and can continue to monitor for a follower-go signal.

[0045] After the maximum idle period has elapsed, the image processing circuit 27 proceeds to block 78, where it may generate an interrupt to log the line number at the end of the maximum idle period. The line number may be used for debugging purposes to determine whether the maximum idle period is sufficient to allow an external device to send a follower-go signal, etc. The image processing circuit 27 then proceeds to block 79, where it may begin processing the image data 50 by starting the VFP portion 56 of the frame of the image data 50.

[0046] Next, the image processing circuit 27 may proceed to block 82 and determine whether a follower-go signal was received after the maximum idle period. If a follower-go signal is received after the maximum idle period has elapsed, the image processing circuit 27 may proceed to block 84, generate an interrupt, and log the line number of the unexpected follower signal. The logged line number may then be used for better synchronization of the idle portion 60 between other frames, such as the image data 50. Next, in block 86, the image processing circuit 27 may determine whether the VACTIVE portion 58 of the image data 50 has finished and proceed to block 88 after the VACTIVE portion 58 has finished. In block 88, the image processing circuit 27 may toggle a line counter and start the idle portion 60 of the image data frame. For example, referring to timing diagram 100, at time t2, the VACTIVE portion 58 finishes and the idle portion 60 begins. If the image processing circuit 27 determines in block 86 that it has not reached the end of the VACTIVE section 58, the image processing circuit 27 can return to block 82.

[0047] Returning to block 74 for a brief reference, the image processing circuit 27 may proceed to block 80 after receiving the follower-go signal. In block 80, the image processing circuit 27 may begin processing the image data 50 by starting the VFP portion 56 of the frame of the image data 50. For example, at time t1 in timing figure 100 of Figure 8, the follower-go signal 102 may have been received by the image processing circuit 27. In some embodiments, the follower-go signal 102 may be a pulse, and the end of the pulse may cause the image processing circuit 27 to proceed to block 80. However, it should be noted that in other embodiments, the image processing circuit 27 may proceed to block 80 at the rising edge of the follower-go signal 102, or at any other appropriate point in time related to the reception of the follower-go signal 102.

[0048] After starting to process the image data frames during the VFP section 56, the image processing circuit 27 proceeds to block 86 and can determine whether the VACTIVE section 58 of the image data 50 has finished. As described above, depending on whether the VACTIVE section 58 has finished, the image processing circuit 27 can proceed to block 88 or return to block 82.

[0049] The specific embodiments described above are presented as examples only, and it should be understood that various modifications and alternative forms are possible. It should be further understood that the claims are not intended to be limited to any particular form of the disclosure, but rather to encompass all modifications, equivalents, and alternative forms within the spirit and scope of this disclosure.

[0050] The techniques presented and claimed herein refer to and apply to material objects and actual examples of a practical nature that demonstrably improve the art, and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any of the claims appended to the end of this specification contain one or more elements expressed as “means for performing a function” or “steps for performing a function,” such elements are intended to be construed in accordance with Section 112(f) of the United States Patent Act. However, with respect to any claims containing elements expressed in any other way, such elements are not intended to be construed in accordance with Section 112(f) of the United States Patent Act.

Claims

1. A method performed by an image processing circuit, Receiving a first frame of image data, wherein the first frame of image data has a plurality of lines, the plurality of lines include an active portion and an idle portion, the active portion having data for presenting one or more images by a first display of a first electronic device, and the idle portion corresponding to a waiting time during which the image processing circuit waits before processing a second frame of image data and receiving a signal from a second electronic device. After the aforementioned waiting time has elapsed, the second frame of the image data is processed after the first frame of the image data, wherein the second electronic device is separate from the first display. A method comprising: adjusting the length of the waiting time in response to the fact that the waiting time has elapsed and the signal has not been received from the second electronic device within the waiting time, wherein the length of the waiting time is adjusted to correspond to the drift between the clock associated with the first electronic device and the clock associated with the second electronic device.

2. The method according to claim 1, further comprising logging in memory for debugging purposes one of the plurality of lines corresponding to the elapsed waiting time if the signal is not received from the second electronic device within the waiting time.

3. Receiving the signal after the aforementioned waiting time has elapsed, The method according to claim 1, further comprising logging one line number from the plurality of lines corresponding to the reception of the signal into memory for debugging purposes.

4. The method according to claim 3, further comprising generating an interrupt by the image processing circuit to log the line number in response to receiving the signal from the second electronic device.

5. The method according to claim 3, wherein the length of the waiting time is adjusted based on the one line number so that the signal can be received within the idle portion.

6. The method according to claim 1, further comprising increasing the line number of one of the plurality of lines in response to the elapsed waiting time and the fact that the signal has not been received from the second electronic device during the waiting time.

7. The method according to claim 1, wherein the signal has pulses.

8. The method according to claim 1, wherein the idle portion of the first frame of the image data is located immediately before the vertical front porch (VFP) portion of the second frame of the image data.

9. The method according to claim 1, wherein the signal has a first transition from a first voltage to a second voltage and a second transition from the second voltage to the first voltage.

10. The display and An electronic device having an image processing circuit, The aforementioned image processing circuit is A frame of image data is received, wherein the frame of image data has a plurality of lines, the plurality of lines include an active portion and an idle portion, the active portion has data for presenting one or more images by the display, and the idle portion corresponds to a waiting time during which the image processing circuit waits before processing a second frame of image data and receiving a signal from a second electronic device. When the idle period ends and in response that the signal has not been received during the waiting time, processing of additional frames of image data is started, where the display is associated with the first clock and the additional display is associated with the second clock. An electronic device configured to adjust the length of the waiting time in response to the completion of the idle period and the fact that the signal has not been received within the waiting time, wherein the length of the waiting time is adjusted to correspond to the drift between the first clock and the second clock.

11. The electronic device according to claim 10, wherein the signal is configured to cause the image processing circuit to synchronously present one or more additional images of the additional frames of the image data by the display and the additional display.

12. The electronic device according to claim 10, wherein the image processing circuit is further configured to log in memory for debugging purposes one of the plurality of lines corresponding to the elapsed waiting time if the signal has not been received from the second electronic device within the waiting time.

13. The electronic device according to claim 12, wherein the image processing circuit is configured to adjust the length of the waiting time based on the one line number so that the signal can be received within the idle portion.

14. The electronic device according to claim 10, wherein the image processing circuit is configured to adjust the length of the waiting time based on the signal received during the active portion so that the signal can be received within the idle portion.

15. It is an image processing circuit, Receiving a first frame of image data, wherein the first frame of image data has a plurality of lines, the plurality of lines include an active portion and an idle portion, the active portion having data for presenting one or more images by a first display of a first electronic device, the idle portion corresponding to a waiting time during which the image processing circuit waits before processing a second frame of image data and receiving a signal from a second electronic device, the second electronic device being separate from the first display, After the aforementioned waiting time has elapsed, processing of the second frame of the image data, which follows the first frame of the image data, is initiated. Image processing circuitry configured to perform one or more operations, including adjusting the length of the waiting time in response to the fact that the signal has not been received from the second electronic device within the waiting time, wherein the length of the waiting time is adjusted to correspond to the drift between the clock associated with the first electronic device and the clock associated with the second electronic device.

16. The one or more of the above operations, It is determined that the aforementioned waiting time has elapsed, and that the signal has not been received from the second electronic device within the aforementioned waiting time. In response to the expiration of the waiting time and the fact that the signal has not been received during the waiting time, processing of additional frames of image data is started on a predetermined line of the plurality of lines. The image processing circuit according to claim 15, further comprising:

17. The image processing circuit according to claim 15, wherein one or more of the operations further include tracking the leading edge of each of the plurality of lines.

18. The image processing circuit according to claim 15, further comprising logging in memory for debugging purposes one of the plurality of lines corresponding to the elapsed waiting time if the signal is not received from the second electronic device within the waiting time of the one or more operations.

19. The one or more of the above operations, Receiving the signal after the aforementioned waiting time has elapsed, The image processing circuit according to claim 15, further comprising logging one line number from the plurality of lines corresponding to the reception of the signal into memory for debugging purposes.

20. The image processing circuit according to claim 19, further comprising one or more operations adjusting the length of the waiting time based on one line number so that the signal can be received within the idle portion.

Images