Circuit devices and display devices

Abstract

To provide a circuit device, etc. capable of reducing cost by conserving storage capacity using subtractive color processing, and suppressing a degradation in image quality caused by the subtractive color processing.SOLUTION: A circuit device 100 comprises: a subtractive color circuit 140 that carries out the subtractive color processing from input image data IMA with pixel data of m bits to a subtractive color-processed image data IMB with the pixel data of n bits, and also carries out error diffusion processing in a spatial direction or a time direction in the subtractive color processing; a storage circuit 115 that stores the subtractive color-processed image data IMB; and an image conversion circuit 150 that carries out image conversion processing, which is at least one of mapping processing and scaling processing with respect to the subtractive color-processed image data IMB stored in the storage circuit 115, outputs output image data IMC, and carries out interpolation processing that generates the pixel data of the output image data IMC from plural sets of pixel data in the subtractive color-processed image data IMB in the image conversion processing.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit device, a display device, and the like.

Background Art

[0002] Patent Document 1 discloses a display device including: a pseudo gradation processing unit that reduces the RGB components of display data from 6 bits to 3 to 5 bits; a frame memory that stores the reduced display data; a gradation correction unit that converts each RGB component of the reduced display data stored in the frame memory to 6 bits using a bit conversion table; and a driving unit that drives a display device using the multi-bit display data.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, after reducing the display data and storing it in the frame memory, the reduced display data is simply returned to the original number of bits using a bit conversion table. Therefore, the image quality simply deteriorates by the amount of reduction in the number of bits of the display data during color reduction.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device including: a color reduction circuit that performs a color reduction process from input image data having m bits of pixel data (where m is an integer of 2 or more) to color-reduced image data having n bits of pixel data (where n is an integer of 1 or more and less than m), and performs an error diffusion process in the spatial or temporal direction in the color reduction process; a storage circuit that stores the color-reduced image data; and an image conversion circuit that performs an interpolation process in which, in an image conversion process which is at least one of a mapping process or a scaling process for the color-reduced image data stored in the storage circuit, the interpolation process that generates pixel data of output image data from a plurality of pixel data of the color-reduced image data.

[0006] Another aspect of this disclosure relates to a display device that includes the circuit device described above and an image display unit that displays an image based on the output image data. [Brief explanation of the drawing]

[0007] [Figure 1] Examples of display device and circuit device configurations. [Figure 2] A first detailed configuration example of a display device and a circuit device. [Figure 3] An explanatory diagram of error diffusion processing in the spatial direction. [Figure 4] An explanatory diagram of FRC as an example of time-direction error diffusion processing. [Figure 5] Detailed configuration example of a distortion correction circuit. [Figure 6] A diagram illustrating the operation of the distortion correction circuit. [Figure 7] Diagram illustrating the interpolation process in the first detailed configuration example. [Figure 8] Examples of images before and after distortion correction. [Figure 9] A second detailed configuration example of the display device and circuit device. [Figure 10] The first example of interpolation processing in the second detailed configuration example. [Figure 11] A second example of interpolation processing in the second detailed configuration example. [Figure 12] A third detailed configuration example of the display device and circuit device. [Modes for carrying out the invention]

[0008] Preferred embodiments of this disclosure will be described in detail below. These embodiments are not intended to unduly limit the scope of the claims, and not all configurations described in these embodiments are necessarily essential.

[0009] 1. Display device and circuit device Figure 1 shows an example of the configuration of the display device 50 and circuit device 100 in this embodiment. The display device 50 includes the circuit device 100, the processing device 200, and the image display unit 300. The display device 50 is, for example, a head-up display device or a display provided on the in-vehicle cluster panel of an automobile.

[0010] The processing unit 200 transmits the input image data IMA to the circuit device 100. The pixel data for each pixel in the input image data IMA is 30 bits. Specifically, the pixel data is 30-bit color data, consisting of 10 bits of red color data, 10 bits of green color data, and 10 bits of blue color data. The processing unit 200 is a so-called SoC, which is a processor such as a CPU or microcomputer. SoC stands for System on Chip. CPU stands for Central Processing Unit.

[0011] The circuit device 100 includes an input circuit 105, a color reduction circuit 140, a memory circuit 115, an image conversion circuit 150, and an output circuit 130. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate.

[0012] The input circuit 105 receives input image data (IMA) from the processing unit 200. The input circuit 105 may be a receiving circuit for various communication interfaces, but examples include LVDS, DVI, DisplayPort, GMSL, or GVIF. LVDS stands for Low Voltage Differential Signaling, DVI stands for Digital Visual Interface, GMSL stands for Gigabit Multimedia Serial Link, and GVIF stands for Gigabit Video Interface.

[0013] The color reduction circuit 140 reduces the pixel data of each pixel in the input image data IMA from 30 bits to 24 bits and outputs the result as the color-reduced image data IMB. Specifically, the color reduction circuit 140 reduces the color data of each color from 10 bits to 8 bits. The pixel data of each pixel in the color-reduced image data IMB becomes 24-bit color data, having 8 bits of R color data, 8 bits of G color data, and 8 bits of B color data.

[0014] Furthermore, the color reduction circuit 140 performs error diffusion processing in the spatial or temporal direction during the color reduction process. Error diffusion processing is the process of spreading the error between the 30-bit pixel data before color reduction and the 24-bit pixel data after color reduction. When the color-reduced image is viewed on average within the range where the error has been diffused, the color corresponding to the color before color reduction is represented. Spatial error diffusion processing is the process of spreading the color reduction error in a certain pixel to the pixel data of surrounding pixels. Temporal error diffusion processing is the process of spreading the color reduction error of a pixel in a certain frame to the pixel data of pixels in frames after that frame.

[0015] The memory circuit 115 temporarily stores the post-color reduction image data IMB and functions as a buffer memory for the image conversion process performed by the image conversion circuit 150. The memory circuit 115 is, for example, a line buffer. Although the image conversion process is an image conversion involving the movement of pixel positions, a line buffer with a number of lines greater than the maximum movement amount of pixel positions in the vertical direction is used. Alternatively, the memory circuit 115 may be a frame memory that buffers the post-color reduction image data IMB for one frame.

[0016] The image conversion circuit 150 performs an image conversion process on the post-color reduction image data IMB and outputs the result as output image data IMC. The image conversion process is a process in which the image is deformed or scaled by coordinate conversion, and specifically, is a mapping process, a scaling process, or a process combining them. The mapping process is a process of converting an image according to an arbitrary mapping between the coordinates on the post-color reduction image data IMB and the coordinates on the output image data IMC. The scaling process is a process of enlarging or reducing an image centered on a reference point on the image.

[0017] Also, the image conversion circuit 150 generates the pixel data of the output image data IMC from the pixel data of a plurality of pixels of the post-color reduction image data IMB by performing an interpolation process in the image conversion process. The pixel data of each pixel of the output image data IMC is 30 bits. That is, in the interpolation process, the image conversion circuit 150 obtains 10-bit R color data of the output image data IMC from the 8-bit R color data of the post-color reduction image data IMB, obtains 10-bit G color data of the output image data IMC from the 8-bit G color data of the post-color reduction image data IMB, and obtains 10-bit B color data of the output image data IMC from the 8-bit B color data of the post-color reduction image data IMB. As will be described later with reference to FIG. 9, the image conversion circuit 150 may output the output image data IMC in which the pixel data of each pixel is 24 bits.

[0018] The output circuit 130 transmits the output image data IMC to the image display unit 300. The output circuit 130 may be a transmission circuit for various communication interfaces, but examples include transmission circuits for LVDS, DVI, DisplayPort, GMSL, or GVIF.

[0019] The image display unit 300 displays an image based on the output image data IMC. Specifically, the image display unit 300 includes a display panel, a display controller that controls the display timing, and a display driver that drives the display panel based on the output image data IMC and timing control signals from the display controller to display an image on the display panel. The display panel is a liquid crystal display panel or a self-emissive display panel, etc. However, the configuration of the image display unit 300 is not limited to this, and may be a HUD 350, for example, as described later in Figure 2.

[0020] In the above, the input image data IMA and output image data IMC were assumed to be 30-bit color, and the reduced-color image data IMB was assumed to be 24-bit color, but this is not limited to this. When m is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than m, the input image data IMA and output image data IMC may be m-bit color, and the reduced-color image data IMB may be n-bit color. For example, the input image data IMA and output image data IMC may be 24-bit color, and the reduced-color image data IMB may be 18-bit color.

[0021] In this embodiment, the circuit device 100 includes a color reduction circuit 140, a storage circuit 115, and an image conversion circuit 150. The color reduction circuit 140 performs a color reduction process from input image data IMA, where the pixel data is m bits, to color-reduced image data IMB, where the pixel data is n bits, and also performs error diffusion processing in the spatial or temporal direction during the color reduction process. The storage circuit 115 stores the color-reduced image data IMB. The image conversion circuit 150 performs an image conversion process on the color-reduced image data IMB stored in the storage circuit 115 to output output image data IMC, and performs interpolation processing during the image conversion process. The image conversion process is at least one of mapping processing or scaling processing. The interpolation process is the process of generating pixel data for the output image data IMC from multiple pixel data of the color-reduced image data IMB.

[0022] According to this embodiment, since the input image data IMA is stored in the storage circuit 115 after color reduction, the storage capacity is reduced by (1-24 / 30)×100%=20% compared to when the input image data IMA is stored in the storage circuit 115 as is. This makes it possible to reduce the cost of the circuit device 100.

[0023] Furthermore, during the color reduction process, error diffusion is performed in the spatial or temporal direction. As a result, the image data is reduced to 24-bit color while maintaining gradation information equivalent to 30-bit color as the average of the diffused range. Then, image conversion processing is performed on the 24-bit color reduced image data IMB, averaging the pixel data in the spatial direction. This results in output image data IMC with smoother gradation than the reduced image data IMB. Specifically, both mapping and scaling processes, which are image conversion processes, involve coordinate transformation. However, in these transformations, the target coordinates may not match the pixel grid. In such cases, the pixel data is interpolated from the pixel data of surrounding pixels, and the pixel data is averaged during this interpolation process. This averaging of pixel data results in smoother gradation, which can be expected to improve image quality.

[0024] While Patent Document 1, mentioned above, describes reducing the number of colors in display data, storing it in frame memory, and then restoring the number of bits, it does not disclose or suggest performing image conversion processing on the color-reduced display data stored in frame memory, nor does it suggest performing interpolation processing during the image conversion process.

[0025] 2. First Detailed Configuration Example The following explanation will use the case where the display device 50 is a head-up display device and the image conversion circuit 150 is a distortion correction circuit 110 as an example.

[0026] Figure 2 shows a first detailed configuration example of the display device 50 and the circuit device 100. The display device 50 includes the processing unit 200, the circuit device 100, and the HUD 350. HUD stands for Head-Up Display. Note that explanations of parts similar to the configuration example in Figure 1 are omitted.

[0027] The HUD350 displays a virtual image in the user's field of view based on output image data (IMC) received from the circuit device 100. The HUD350 includes a display controller, a display driver, a display panel, and a projection optical system. The display panel is a liquid crystal display panel or an OLED display panel, etc. OLED stands for Organic Light Emitting Diode. The projection optical system includes lenses or reflectors, etc., and projects the image displayed by the display panel onto a screen. The screen can be any transparent projection surface that reflects projected light. For example, the screen is the windscreen of a mobile device on which the display device 50 is mounted.

[0028] The configuration of the HUD350 is not limited to the above. For example, instead of a display panel and projection optics, the HUD350 may include a laser light source, a mirror that reflects the laser, and an actuator that drives the mirror to scan the laser. Alternatively, instead of a display panel and projection optics, the HUD350 may include a laser light source and a digital mirror device. The digital mirror device includes an array of micro-mirrors and an actuator that drives each micro-mirror.

[0029] The circuit device 100 includes an input circuit 105, a color reduction circuit 140, a memory circuit 115, a distortion correction circuit 110, and an output circuit 130. The distortion correction circuit 110 is an example of the image conversion circuit 150 shown in Figure 1.

[0030] A detailed example of the error diffusion process performed by the color reduction circuit 140 is explained. Figure 3 shows an explanatory diagram of the error diffusion process in the spatial direction.

[0031] The color reduction circuit 140 selects a pixel to be processed from the input image data IMA and performs color reduction on the pixel data of that pixel. Here, it is assumed that pixels are selected sequentially using a so-called raster scan method. Figure 3 shows the pixel to be processed with hatching and the surrounding 3x3 pixels. The color reduction circuit 140 adds the error propagated from the surrounding pixels to the 30-bit color pixel data, reduces the resulting 30-bit color pixel data to 24-bit color pixel data, and takes the difference as the error data Δr. When the coordinates of the pixel to be processed are (Xs, Ys), the color reduction circuit 140 propagates Δr×C1 to the pixel at (Xs+1, Ys). Similarly, the color reduction circuit 140 propagates Δr×C2, Δr×C3, and Δr×C4 to the pixels at (Xs-1, Ys+1), (Xs, Ys+1), and (Xs+1, Ys+1). C1 to C4 are coefficients, and C1 + C2 + C3 + C4 = 1. Due to this spatial error diffusion, the reduced-color image data (IMB) contains information equivalent to the original 30-bit color.

[0032] Figure 4 shows an explanatory diagram of FRC as an example of time-direction error diffusion processing. FRC stands for Frame Rate Control. The frame rate of the input image data IMA before FRC and the reduced-color image data IMB after FRC are the same. Here, we will explain using R color data as an example, but the same processing is performed on G color data and B color data.

[0033] Figure 4 shows a 4x4 pixel image after FRC (Frequency Reduction). Let's first focus on the top left pixel. Of the 10 bits of R color data in the input image data IMA, the upper 8 bits are used as R, and the lower 2 bits are used as error data. Here, we assume the error is 0.25. The color reduction circuit 140 sets the R color data in the color-reduced image data IMB to R+1 in frame F1, and to R in frames F2, F3, and F4. The average of the R color data in frames F1 to F4 is R+0.25, and the color-reduced image data IMB contains information equivalent to the 30-bit color before color reduction.

[0034] Similarly, errors are diffused in the time direction for other pixels, but the timing of diffusion differs between adjacent pixels. For example, in frames F1, F2, F3, and F4, the top-left pixel is R+1, R, R, R, while the pixel immediately to its right is R, R, R+1, R, indicating that the timing of R+1 is different. As a result, the average of the 4x4 pixels in each frame is R+0.25. This suggests that errors are also diffused in the spatial direction when viewed on a frame-by-frame basis, and that the frames contain information equivalent to the 30-bit color before color reduction.

[0035] Although this explanation uses the case where the error is 0.25 as an example, FRC is also performed in cases where the error is 0.5 or 0.75, so that the average of the four frames is 0.5 or 0.75, and the diffusion timing differs for adjacent pixels.

[0036] Next, the distortion correction circuit 110 will be described. The distortion correction circuit 110 performs distortion correction on the color-reduced image data IMB using a coordinate transformation between the pixel coordinates in the color-reduced image data IMB and the pixel coordinates in the output image data IMC, and outputs the result as the output image data IMC. Distortion correction is an image correction that applies an image distortion to the image that is the opposite of the image distortion when the image is projected by the HUD 350, in order to make the HUD display distortion-free or reduced. Image distortion is caused by the optical system of the HUD. Image distortion caused by the optical system includes image distortion due to the curvature of the screen, image distortion due to the projection optical system of the HUD, or both.

[0037] Figure 5 shows a detailed configuration example of the distortion correction circuit 110. The distortion correction circuit 110 includes a coordinate counter 112, a coordinate transformation circuit 113, and an interpolation circuit 114. Figure 6 is a diagram illustrating the operation of the distortion correction circuit 110. Here, an example is described in which the distortion correction circuit 110 is a reverse warp engine.

[0038] The coordinate counter 112 outputs the pixel coordinates GZC=(x,y) on the output image data IMC. The coordinate transformation circuit 113 transforms the pixel coordinates (x,y) into reference coordinates GZB=(u,v), which are the coordinates on the reduced-color image data IMB. Specifically, the coordinate transformation circuit 113 performs the coordinate transformation using a polynomial or table that associates the pixel coordinates (x,y) with the reference coordinates (u,v). The coordinate transformation circuit 113 transforms the reference coordinates (u,v) into the read addresses of multiple surrounding pixels. The memory circuit 115 outputs multiple pixel data PXD from these read addresses. The interpolation circuit 114 obtains the pixel data of the pixel coordinates (x,y) in the output image data IMC by interpolating the multiple pixel data that have been read.

[0039] Figure 6 shows an example where pixel data P1 to P16 of the surrounding 4x4 pixels of the reference coordinate (u,v) is read out. When u and v are integer values, the reference coordinate (u,v) coincides with the pixel grid of the reduced-color image data IMB. However, u and v are real values ​​and not necessarily integer values. That is, the reference coordinate (u,v) does not necessarily coincide with the pixel grid of the reduced-color image data IMB. The interpolation circuit 114 obtains the pixel data at the reference coordinate (u,v) by interpolating the 4x4 pixel data P1 to P16, and uses that as the pixel data for the pixel coordinate (x,y) in the output image data IMC.

[0040] Figure 7 shows an explanatory diagram of the interpolation process in the first detailed configuration example. The pixel data P1 to P16 read from the memory circuit 115 is 24-bit color. The interpolation circuit 114 performs the interpolation process using 30-bit operations to obtain 30-bit color pixel data PC(x,y) from the 24-bit color pixel data P1 to P16. Specifically, 30-bit operations mean performing 10-bit operations on each color data. The formula for the interpolation process is shown in the middle of Figure 7. PC(x,y) is the pixel data of the pixel coordinates (x,y) in the output image data IMC. αi(u,v) is the interpolation coefficient, which is set according to the reference coordinates (u,v). α1 + α2 + ... + α16 = 4. Also, when α1 to α16 are considered as a 4x4 matrix corresponding to P1 to P16, the sum of each row is 1, and the sum of each column is 1. The interpolation process may be, for example, bilinear interpolation, but is not limited to this; it may also be bicubic interpolation or the like.

[0041] Figure 8 shows examples of images before and after distortion correction. Here, we show an example where an 8-bit monochrome input image is reduced to a 1-bit monochrome image, and then restored to an 8-bit monochrome image through distortion correction.

[0042] The left image shows a portion of the image after color reduction with spatial error diffusion applied. The original 8-bit monochrome image is a gradient image where the color intensity increases from the upper left to the lower right of the region. Although the image is binarized by color reduction, the gradient information is preserved due to spatial error diffusion. In other words, the density of black pixels increases from the upper left to the lower right of the region.

[0043] The right figure is a cropped section of the image after distortion correction, corresponding to the area shown in the left figure. However, because the rectangular area in the left figure shifts to a rhombus-like distorted area due to distortion correction, the left and right figures represent roughly the same area, but are not entirely identical. In distortion correction, an 8-bit monochrome image is generated from a 1-bit monochrome image, and at that time, the pixel data is averaged in the spatial direction through interpolation. This results in a distortion-corrected image with improved gradation while retaining the effect of error diffusion present in the reduced-color image. As explained in Figure 4, FRC also includes spatial error diffusion, which yields the same effect as described above.

[0044] As described above, applying distortion correction after color reduction saves storage capacity in the line buffer or frame memory, and also results in output image data with improved gradation compared to simply reducing the number of colors.

[0045] In this embodiment described above, the image conversion circuit 150 is a distortion correction circuit 110. In the mapping process, the distortion correction circuit 110 converts the pixel coordinates (x,y) on the output image data IMC to reference coordinates (u,v) on the color-reduced image data IMB. The distortion correction circuit 110 generates pixel data PC(x,y) of the pixel coordinates (x,y) in the output image data IMC from a plurality of pixel data P1 to P16 surrounding the reference coordinates (u,v) in the color-reduced image data IMB.

[0046] In the mapping process, the reference coordinates (u,v) do not necessarily coincide with the pixel grid of the reduced-color image data IMB, so interpolation from multiple surrounding pixel data is inevitably required. This interpolation process averages the pixel data in the spatial direction, resulting in output image data IMC with improved gradation while retaining the error diffusion effect present in the reduced-color image.

[0047] In this embodiment, the distortion correction circuit 110 performs distortion correction processing on the color-reduced image data IMB based on the mapping process described above. The distortion correction processing is a process that corrects image distortion caused by the optical system of the HUD 350 that projects the image onto the projection surface based on the output image data IMC.

[0048] According to this embodiment, in the distortion correction process, an image distortion inverse to the image distortion when the image is projected by the HUD350 is applied to the image. As a result, the image distortion applied to the image by distortion correction cancels out the image distortion during projection, resulting in a HUD display with no or reduced distortion.

[0049] In this embodiment, the color reduction circuit 140 performs error diffusion processing in the spatial direction. The distortion correction circuit 110 generates output image data IMC in which the pixel data is m bits by interpolation processing.

[0050] According to this embodiment, the m-bit color input image data IMA is reduced to n-bit color reduced image data IMB and then stored in the storage circuit 115. Through interpolation processing, m-bit color output image data IMC is generated from the n-bit color reduced image data IMB. As explained in Figure 8, by multi-gradation conversion from n-bit color to m-bit color through interpolation processing, the output image data IMC is obtained with improved gradation while inheriting the error diffusion effect contained in the reduced image data IMB.

[0051] In this embodiment, the color reduction circuit 140 may also perform frame rate control processing as a time-direction error diffusion process. The distortion correction circuit 110 may generate output image data IMC in which the pixel data is m bits by interpolation processing.

[0052] As explained in Figure 4, errors are diffused not only in the temporal direction but also in the spatial direction during FRC, and the image data after FRC contains information equivalent to the m-bit color before color reduction. Therefore, by interpolating from n-bit color to m-bit color, the effect of error diffusion contained in the color-reduced image data IMB is inherited, and an output image data IMC with improved gradation is obtained.

[0053] In this embodiment, the memory circuit 115 is either a line buffer that stores image data of multiple lines of the color-reduced image data IMB, or a frame memory that stores frame image data of the color-reduced image data IMB.

[0054] Both line buffers and frame memories are image memories and therefore have relatively large storage capacities. For example, if the pixel data of the input image data (IMA) increases from 24 bits to 30 bits, 1.25 times the storage capacity is required. However, according to this embodiment, the color is reduced to 24 bits, so the storage capacity does not increase. Alternatively, even if the pixel data of the input image data (IMA) remains at 24 bits, storage capacity can be saved by reducing the color to, for example, 18 bits.

[0055] 3. Second Detailed Configuration Example Figure 9 shows a second detailed configuration example of the display device 50 and the circuit device 100. In this second detailed configuration example, the distortion correction circuit 110 outputs 24-bit color output image data (IMC). Note that explanations of parts similar to those in the configuration examples in Figure 1 or Figure 2 are omitted.

[0056] Figure 10 shows the first example of interpolation processing in the second detailed configuration example. The interpolation circuit 114 performs interpolation processing using 30-bit arithmetic, similar to the first detailed configuration example, to obtain 30-bit color pixel data PC(x,y). The interpolation circuit 114 discards the lower two bits from each of the 10 bits of color data in the pixel data PC(x,y) to obtain 24-bit color pixel data. The distortion correction circuit 110 outputs this 24-bit color pixel data as the pixel data of the output image data IMC.

[0057] Figure 11 shows a second example of interpolation processing in the second detailed configuration example. The interpolation circuit 114 calculates the sum of products of the pixel data Pi and the interpolation coefficient αi using a 30-bit operation, and then divides the result of this 30-bit sum of products by 16 to obtain 24-bit color pixel data PC(x,y). Since α1 + α2 + ... + α16 = 4, dividing the result of the sum of products by 16 is equivalent to dividing each color data by 4, and the 10-bit color data for each color is reduced to 8 bits. The distortion correction circuit 110 outputs the 24-bit color pixel data PC(x,y) as the pixel data of the output image data IMC.

[0058] In this embodiment, the image is the same 24-bit color before and after distortion correction, but during distortion correction, it is interpolated using 30-bit calculations and then reduced to 24 bits. As a result, at the 30-bit calculation stage, as explained in Figure 8, a distortion-corrected image with improved gradation is obtained while retaining the effect of error diffusion contained in the reduced-color image. Then, when this image is reduced to 24-bit color, the effect of error diffusion contained in the reduced-color image is appropriately reflected in the distortion-corrected image, and a distortion-corrected output image data (IMC) containing gradation information equivalent to 30-bit color is obtained.

[0059] 4. Third Detailed Configuration Example Figure 12 shows a third detailed configuration example of the display device 50 and the circuit device 100. In the second detailed configuration example, the circuit device 100 further includes a color space conversion circuit 160. Note that explanations of parts similar to the configuration example in Figure 1 or Figure 2 are omitted.

[0060] The processing unit 200 transmits 24-bit color image data (IMD) to the circuit device 100. The input circuit 105 receives the image data (IMD) from the processing unit 200.

[0061] The color space conversion circuit 160 outputs 30-bit color input image data IMA by performing a color space conversion on 24-bit color image data IMD. Specifically, the image data IMD represents colors in a predetermined color space. The color space conversion circuit 160 converts the predetermined color space of the image data IMD to the RGB color space. For example, let the predetermined color space be YUV, and let the YUV components of the pixel data in the image data IMD be DDy, DDu, and DDv, and the RGB components of the pixel data in the input image data IMA be DAr, DAg, and DAb. The color space conversion circuit 160 obtains the pixel data (DAr, DAg, DAb) of the input image data IMA by multiplying the pixel data (DDy, DDu, DDv) of the image data IMD by a 3x3 conversion matrix that represents the color space conversion.

[0062] In the above, the image data IMD was assumed to be 24-bit color and the input image data IMA was assumed to be 30-bit color, but this is not limited to this. When m is an integer greater than or equal to 2 and k is an integer greater than or equal to 1 and less than m, the image data IMD may be k-bit color and the input image data IMA may be m-bit color.

[0063] In this embodiment, the circuit device 100 also includes a color space conversion circuit 160. The color space conversion circuit 160 generates input image data IMA, in which the pixel data is m bits, by performing a color space conversion on image data IMD, in which the pixel data is k bits.

[0064] According to this embodiment, even when image data IMD in a color space other than the RGB color space is input to the circuit device 100, the image data IMD can be converted to image data in the RGB color space. Furthermore, by bit-expanding the pixel data from k bits to m bits during color space conversion, smooth gradation input image data IMA can be obtained without losing as much of the gradation of the image data IMD during color space conversion. Then, by first reducing the color of the input image data IMA and storing it in the memory circuit 115, and then performing distortion correction, output image data IMC containing gradation information corresponding to the gradation information of the input image data IMA can be obtained without increasing the storage capacity of the memory circuit 115.

[0065] The circuit device of this embodiment described above includes a color reduction circuit, a storage circuit, and an image conversion circuit. The color reduction circuit performs a color reduction process from input image data where the pixel data is m bits to color-reduced image data where the pixel data is n bits, and also performs error diffusion processing in the spatial or temporal direction during the color reduction process. m is an integer of 2 or more. n is an integer of 1 or more that is less than m. The storage circuit stores the color-reduced image data. The image conversion circuit performs an image conversion process, which is at least one of a mapping process or a scaling process, on the color-reduced image data stored in the storage circuit to output output image data, and in the image conversion process, it performs interpolation processing to generate pixel data of the output image data from multiple pixel data of the color-reduced image data.

[0066] According to this embodiment, since the input image data is stored in the memory circuit after being color-reduced, storage capacity is saved compared to when the input image data is stored in the memory circuit as is. This makes it possible to reduce the cost of the circuit device. Furthermore, by performing error diffusion processing in the spatial or temporal direction during the color reduction process, the image data is reduced to n-bit color while maintaining gradation information equivalent to m-bit color as the average of the diffused range. Then, by performing interpolation processing in the image conversion process of the n-bit color reduced image data, the pixel data is averaged in the spatial direction, resulting in output image data with smoother gradation than the color-reduced image data.

[0067] In this embodiment, the image conversion circuit may convert pixel coordinates on the output image data to reference coordinates on the color-reduced image data during the mapping process. The image conversion circuit may also generate pixel data for the pixel coordinates in the output image data from a plurality of pixel data surrounding the reference coordinates in the color-reduced image data.

[0068] In the mapping process, the reference coordinates do not necessarily coincide with the pixel grid of the reduced-color image data, so interpolation from multiple surrounding pixel data is inevitably required. This interpolation process averages the pixel data in the spatial direction, resulting in output image data with improved gradation while retaining the error diffusion effect present in the reduced-color image.

[0069] In this embodiment, the image conversion circuit may also perform distortion correction processing on the reduced-color image data through mapping processing.

[0070] In this embodiment, the distortion correction process may also be a process that corrects image distortion caused by the optical system of a head-up display that projects an image onto a projection surface based on output image data.

[0071] According to this embodiment, in the distortion correction process, an image distortion inverse to the image distortion when the image is projected by the head-up display is applied to the image. As a result, the image distortion applied to the image by distortion correction cancels out the image distortion during projection, and a head-up display with no or reduced distortion is obtained.

[0072] In this embodiment, the color reduction circuit may also perform error diffusion processing in the spatial direction. The image conversion circuit may generate output image data in which the pixel data is m bits by interpolation processing.

[0073] According to this embodiment, m-bit color input image data is reduced to n-bit color reduced image data and then stored in a memory circuit. Through interpolation processing, m-bit color output image data is generated from the n-bit color reduced image data. By converting the n-bit color to m-bit color through interpolation processing, output image data with improved gradation is obtained while inheriting the error diffusion effect contained in the reduced image data.

[0074] In this embodiment, the color reduction circuit may also perform frame rate control processing as a time-direction error diffusion process. The image conversion circuit may generate output image data in which the pixel data is m bits by interpolation processing.

[0075] In frame rate control processing, errors are diffused not only in the temporal direction but also in the spatial direction, and the image data after frame rate control processing contains information equivalent to the m-bit color before color reduction. Therefore, by interpolating from n-bit color to m-bit color, the effect of error diffusion contained in the image data after color reduction is inherited, and output image data with improved gradation is obtained.

[0076] In this embodiment, the circuit device may also include a color space conversion circuit. The color space conversion circuit may generate input image data with m bits of pixel data by performing a color space conversion on image data with k bits of pixel data, where k is an integer greater than or equal to 1 and less than m.

[0077] According to this embodiment, even when image data in a different color space than the output image data is input to the circuit device, the color space of that image data can be converted to the same color space as the output image data. Furthermore, by bit-expanding the pixel data from k bits to m bits during color space conversion, smooth gradation input image data can be obtained without losing as much of the gradation of the image data as possible during color space conversion. Then, by first reducing the color of the input image data and storing it in the memory circuit, and then performing distortion correction, output image data containing gradation information corresponding to the gradation information of the input image data can be obtained without increasing the memory capacity of the memory circuit.

[0078] In this embodiment, the memory circuit may be a line buffer that stores image data of multiple lines of the color-reduced image data, or a frame memory that stores frame image data of the color-reduced image data.

[0079] Both line buffers and frame memories are image memories and therefore have relatively large storage capacities. For example, if the pixel data of the input image data increases from 24 bits to 30 bits, 1.25 times the storage capacity is required. However, according to this embodiment, the number of bits is reduced to 24, so the storage capacity does not increase. Alternatively, even if the pixel data of the input image data remains at 24 bits, storage capacity can be saved by reducing the number of bits to, for example, 18 bits.

[0080] Furthermore, the display device of this embodiment includes a circuit device and an image display unit that displays an image based on output image data.

[0081] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of the circuit device, processing device, image display unit, display device, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of symbols]

[0082] 50…Display device, 100…Circuit device, 105…Input circuit, 110…Distortion correction circuit, 112…Coordinate counter, 113…Coordinate transformation circuit, 114…Interpolation circuit, 115…Memory circuit, 130…Output circuit, 140…Color reduction circuit, 150…Image conversion circuit, 160…Color space conversion circuit, 200…Processing device, 300…Image display unit, 350…HUD, GZB…Reference coordinates, GZC…Pixel coordinates, IMA…Input image data, IMB…Image data after color reduction, IMC…Output image data, IMD…Image data, P1~P16…Pixel data, PXD…Pixel data

Claims

1. A color reduction circuit performs a color reduction operation from input image data where the pixel data is m bits (m is an integer of 2 or more) to reduced image data where the pixel data is n bits (n is an integer of 1 or more and less than m), and also performs error diffusion in the spatial or temporal direction during the color reduction operation. A memory circuit for storing the color-reduced image data, An image conversion circuit that performs image coordinate transformation processing on the color-reduced image data stored in the memory circuit and outputs output image data, Includes, The aforementioned image coordinate transformation process is performed as follows: A process for transforming position coordinates in a position coordinate space which is a space of position coordinates indicating the display position of a pixel, the process being at least one of a mapping process or a scaling process, The aforementioned image conversion circuit is The circuit device is characterized in that, in the image coordinate transformation process, the position coordinates on the output image data are transformed into reference coordinates on the color-reduced image data, and the pixel data surrounding the reference coordinates in the color-reduced image data are interpolated in the position coordinate space to generate m-bit pixel data of the position coordinates in the output image data.

2. In the circuit device described in claim 1, The aforementioned image conversion circuit is A circuit device characterized by performing distortion correction processing on the reduced-color image data through the mapping process.

3. In the circuit device described in claim 2, The aforementioned distortion correction process is performed as follows: A circuit device characterized by a process for correcting image distortion caused by the optical system of a head-up display that projects an image onto a projection surface based on the output image data.

4. In a circuit device according to any one of claims 1 to 3, The aforementioned color reduction circuit is A circuit device characterized by performing the error diffusion process in the spatial direction.

5. In a circuit device according to any one of claims 1 to 4, The aforementioned color reduction circuit is A circuit device characterized in that it performs frame rate control processing as the error diffusion processing in the time direction.

6. In a circuit device according to any one of claims 1 to 5, A circuit device characterized by including a color space conversion circuit that generates input image data having m bits of pixel data by performing a color space conversion on image data having k bits of pixel data (where k is an integer greater than or equal to 1 and less than m).

7. In a circuit device according to any one of claims 1 to 6, The memory circuit described above is A circuit device characterized by being a line buffer for storing image data of multiple lines of the color-reduced image data, or a frame memory for storing frame image data of the color-reduced image data.

8. A circuit device according to any one of claims 1 to 7, An image display unit that displays an image based on the output image data, A display device characterized by including

Images