Gaming machine

Abstract

To suppress delay in a sound performance for a display performance.SOLUTION: A Pachinko game machine 1 includes a CPU 310 for executing analysis of command information for each predetermined time, a sound circuit 323 for reproducing sound data in response to an instruction from the CPU 310, and a digital amplifier 305 for amplifying sound data reproduced by the sound circuit 323. When the sound circuit 323 is not in a severe abnormal state, in particular, the analysis of command information by the CPU 310 is continued even if the digital amplifier 305 is in an abnormal state. The time that the digital amplifier 305 is restored from the abnormal state is longer than the predetermined time.SELECTED DRAWING: Figure 49

Description

Technical Field

[0001] The present invention relates to a gaming machine including amplification means for amplifying an audio signal.

Background Art

[0002] Conventionally, a gaming machine including amplification means for amplifying an audio signal has been known (see Patent Document 1). In this gaming machine, an audio synthesis circuit that reproduces an audio signal based on stored data in an audio memory, a digital amplifier (amplification means) that amplifies the audio signal input from the audio synthesis circuit and drives a speaker, and an effect control unit that sets operation parameters in an audio control register of the audio synthesis circuit are provided. Then, when the effect control unit detects an abnormality in the digital amplifier, it sets predetermined operation parameters in the audio control register to mute the audio output.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a conventional gaming machine, when the digital amplifier returns from an abnormal state, there is a risk that the sound effect may be delayed with respect to the display effect. An object of the present invention is to suppress a delay in the sound effect with respect to the display effect.

Means for Solving the Problems

[0005] To achieve the above object, a gaming machine according to a first invention includes analysis means for executing analysis of sound control data at predetermined time intervals, reproduction means for reproducing an audio signal in response to an instruction from the analysis means, and amplification means for amplifying the audio signal reproduced by the reproduction means. If the playback means is in the first abnormal state, the analysis of sound control data by the analysis means will not be performed. The reproduction means It is either a normal state or a second abnormal state. In this case, even if the amplification means is in an abnormal state, the analysis of sound control data by the analysis means continues, and the time it takes for the amplification means to recover from the abnormal state is longer than the predetermined time. In the gaming machine according to the first invention, the analysis means performs analysis of sound control data at predetermined intervals. As a result, even if the analysis of sound control data by the analysis means is interrupted during the period when the amplification means is in an abnormal state, if the amplification means recovers from the abnormal state within the predetermined time, the analysis means can perform analysis of sound control data without delay after recovering from the abnormal state, and sound effects can be performed without delay in response to the display effects. However, in the gaming machine according to the first invention, the time it takes for the amplification means to recover from an abnormal state is longer than a predetermined time. As a result, if the analysis of sound control data by the analysis means is interrupted during the period when the amplification means is in an abnormal state, the amplification means may not be able to recover from the abnormal state within the predetermined time, and after it recovers from the abnormal state, the analysis of sound control data by the analysis means will be performed with a delay, resulting in a delay in sound effects relative to the display effects. Therefore, in the gaming machine according to the first invention, the analysis of sound control data by the analysis means continues even if the amplification means is in an abnormal state, as long as the playback means is not in an abnormal state. As a result, the analysis of sound control data by the analysis means continues even during the period when the amplification means is in an abnormal state. Consequently, a situation in which the analysis of sound control data by the analysis means is performed with a delay after the amplification means recovers from the abnormal state is prevented, and it becomes possible to perform sound effects without delay in response to the display effects. As a result of the above, the gaming machine according to the first invention makes it possible to suppress the delay between the sound effects and the display effects. Here, the sound control data corresponds to the command information described later. The analysis means corresponds to the CPU 310 (step S41-5) described later. The sound signal corresponds to the audio data described later. The playback means corresponds to the sound circuit 323 described later. The amplification means corresponds to the digital amplifier 305 described later. The abnormal state of the playback means corresponds to the severe abnormal state described later. The abnormal state of the amplification means corresponds to the abnormal state described later.

[0006] The gaming machine according to the second invention is, in the gaming machine according to the first invention, With the start of the new sound effects, it is possible to recover from the second abnormal state. Characterized by 。 [Effects of the Invention]

[0007] According to the present invention, it is possible to suppress the delay between the sound effects and the visual effects. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing the overall structure of a pachinko machine. [Figure 2] This diagram shows the front of the game board, schematically illustrating the parts that are particularly necessary for explanation. [Figure 3] This is a block diagram showing the configuration of the control system for a pachinko machine. [Figure 4] This is a block diagram showing the configuration of the launch condition detection circuit and the launch control circuit. [Figure 5] This is a block diagram showing the configuration of the performance control board. [Figure 6] This is the address map of the memory area used by CPU210. [Figure 7] This is a flowchart showing the CPU initialization process. [Figure 8] This is a flowchart showing the main loop processing. [Figure 9] This flowchart shows the evacuation procedure when the power supply is cut off. [Figure 10] This is a flowchart showing timer interrupt handling. [Figure 11] It is a flowchart showing dynamic port output processing. [Figure 12] It is a flowchart showing performance display device output processing. [Figure 13] It is a flowchart showing setting-related processing. [Figure 14] It is a flowchart showing switch management processing. [Figure 15] It is a flowchart showing general drawing start ball detection processing. [Figure 16] It is a flowchart showing special drawing 1 start ball detection processing. [Figure 17] It is a flowchart showing special drawing 2 start ball detection processing. [Figure 18] It is a flowchart showing special symbol random number acquisition processing. [Figure 19] It is a flowchart showing special game management processing. [Figure 20] It is a flowchart showing special drawing change waiting processing. [Figure 21] It is a flowchart showing special drawing change in progress processing. [Figure 22] It is a flowchart showing special drawing stop processing. [Figure 23] It is a flowchart showing processing before the big winning opening is opened. [Figure 24] It is a flowchart showing special electric role opening / closing switching processing. [Figure 25] It is a flowchart showing big winning opening opening control processing. [Figure 26] It is a flowchart showing big winning opening closing valid processing. [Figure 27] It is a flowchart showing big winning opening opening end wait processing. [Figure 28] It is a flowchart showing normal game management processing. [Figure 29] It is a flowchart showing general drawing change waiting processing. [Figure 30] It is a flowchart showing general drawing change in progress processing. [Figure 31] This is a flowchart showing the process during a system shutdown. [Figure 32] This is a flowchart showing the pre-processing steps for opening a standard electric mechanism. [Figure 33] This is a flowchart showing the process for switching between normal electric power supply and switchgear. [Figure 34] This is a flowchart showing the control process for opening a standard electric mechanism. [Figure 35] This is a flowchart showing the process for activating the closing of a standard electric mechanism. [Figure 36] This flowchart shows the normal motorized mechanism release completion wait process. [Figure 37] This is a flowchart showing the control process for the performance display device. [Figure 38] Flowchart for sub-CPU initialization process. [Figure 39] This is a flowchart showing the sub-timer interrupt processing. [Figure 40] This is a flowchart showing the command parsing process. [Figure 41] This is a flowchart showing the process for receiving pending commands. [Figure 42] This is a flowchart showing the process of receiving pre-read commands. [Figure 43] This is a flowchart showing the process of receiving variable commands. [Figure 44] This is a flowchart showing the process of receiving a stop command. [Figure 45] This is a flowchart showing the process of receiving the opening command. [Figure 46] This is a flowchart showing the Vsync interrupt handling process. [Figure 47] This is a flowchart showing the command construction task process. [Figure 48] This is a flowchart showing the sound interrupt processing. [Figure 49] This is a flowchart showing the lamp interrupt processing. [Figure 50] This is a flowchart showing the process for handling interrupts from movable bodies. [Figure 51] This is a block diagram showing the configuration of the sound circuit. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the gaming machine according to the present invention is applied to a pachinko machine 1.

[0010] (Overall configuration of Pachinko machine 1) First, let me explain the overall configuration of Pachinko Machine 1. Figure 1 is a perspective view showing the overall configuration of a pachinko machine. The pachinko machine 1 consists of an outer frame unit 2, an inner frame unit 3, an integrated door unit 4, and a game board unit 10. The outer frame unit 2, the inner frame unit 3, and the integrated door unit 4 are fixed to each other via a hinge mechanism. This allows the inner frame unit 3 to open and close relative to the outer frame unit 2. The integrated door unit 4 can also open and close relative to both the inner frame unit 3 and the outer frame unit 2. The outer frame unit 2 is composed of a rectangular frame (outer frame). The outer frame of the outer frame unit 2 is fixed to the island equipment of the amusement arcade. The inner frame unit 3 is composed of a rectangular frame (inner frame). The inner frame unit 3 is positioned inside the outer frame unit 2. The integrated door unit 4 is formed in the shape of a rectangular door. The integrated door unit 4 includes a transparent plate 4a located approximately in the center, a decorative part 4b located around the transparent plate 4a, a receiving tray unit 5 located below the transparent plate 4a, and a firing handle unit 6 located to the side of the receiving tray unit 5. The transparent plate 4a is formed in a flat shape from a transparent material such as resin or glass. The decorative part 4b is formed from a transparent or translucent resin material and has a shape that bulges forward. At each upper corner of the decorative part 4b, there are sound vents 4c inside which a speaker 22 (see Figure 3) is disposed. Each sound vent 4c is provided with multiple sound vents that allow the sound output by the speaker 22 to pass through. A frame lamp 20 (see Figure 3) is also provided on the decorative part 4b. The frame lamp 20 is composed of multiple light-emitting elements (LEDs) that are driven by dynamic lighting control.

[0011] The receiving unit 5 includes a receiving tray 5a for receiving game balls (loaned balls and prize balls), and various operating means that can be operated by the player. In this embodiment, various operating means include a performance button 5b, a rotary selector 5c, a light intensity adjustment button (not shown), a volume adjustment button (not shown), a directional pad button (not shown), and the like. The performance button 5b consists of an operating section that can be pressed by the player, and a button switch 25 (see Figure 3) that detects the operation of the operating section. The button switch 25 outputs a detection signal to the performance control board 300 (see Figure 3) each time the operating section is pressed. The rotary selector 5c (a so-called "jog dial") comprises an operating unit that can be rotated by the player, and a dial switch 26 (see Figure 3) that detects the rotation of the operating unit. The dial switch 26 outputs a detection signal to the performance control board 300 each time the operating unit is rotated by a predetermined angle (for example, 60°).

[0012] The light intensity adjustment button comprises two operating parts (a first operating part and a second operating part) that can be pressed by the player, and a light intensity adjustment switch 27 (see Figure 3) that detects the pressing operation of each operating part. The light intensity adjustment switch 27 outputs a first detection signal to the performance control board 300 each time the first operating part is pressed, and outputs a second detection signal to the performance control board 300 each time the second operating part is pressed. The volume control button consists of two operating parts (a first operating part and a second operating part) that can be pressed by the player, and a volume control switch 28 (see Figure 3) that detects the pressing operation of each operating part. The volume control switch 28 outputs a first detection signal to the performance control board 300 each time the first operating part is pressed, and outputs a second detection signal to the performance control board 300 each time the second operating part is pressed. The directional pad consists of four operational buttons (up key button, down key button, left key button, and right key button) that can be pressed by the player, and a directional pad switch 29 (see Figure 3) that detects the pressing operation of each operational button. The directional pad switch 29 outputs a first detection signal to the performance control board 300 each time the up key button is pressed, a second detection signal to the performance control board 300 each time the down key button is pressed, a third detection signal to the performance control board 300 each time the left key button is pressed, and a fourth detection signal to the performance control board 300 each time the right key button is pressed.

[0013] Furthermore, a lending operation unit 7 is provided on the upper surface of the receiving tray unit 5. The lending operation unit 7 includes a ball lending button 7a, a return button 7b, and a frequency display device 7c. Here, the pachinko machine 1 is communicatively connected to a CR unit 700 that can read and update information recorded on a prepaid card. When a prepaid card (not shown) is inserted into the CR unit 700, the remaining balance of the redeemable medium recorded on the inserted prepaid card is displayed on the balance display device 7c. Furthermore, when the ball dispensing button 7a is operated while the prepaid card is inserted into the CR unit 700, a predetermined number of game balls are dispensed into the tray 5a. At this time, the remaining balance of the redeemable media recorded on the prepaid card is updated according to the number of game balls dispensed, and the updated remaining balance of the redeemable media is displayed on the balance display device 7c. Furthermore, if the return button 7b is pressed while a prepaid card with remaining credit on the redeemable media is inserted into the CR unit 700, the prepaid card will be returned from the CR unit 700. In this context, prepaid cards include, for example, magnetic storage media and media with embedded storage ICs.

[0014] The firing handle unit 6 includes a handle base (not shown), a handle operating section (not shown), and a firing stop button (not shown). The handle base is attached to the front side of the integrated door unit 4. A bearing is provided on the front side of the handle base. The handle operating section is shaped to allow the player to grip it. A rotating shaft is provided on the back side of the handle operating section. The handle operating section is rotatably mounted to the handle base by the rotating shaft being supported by the bearing portion of the handle base. The handle operating section can be rotated (displaced) between a predetermined initial position and a predetermined limit position. Inside the launch handle unit 6, a biasing means (a spring in this embodiment) is arranged to bias the handle operating section toward the initial position. As a result, the handle operating section is positioned (displaced) in the initial position when not being rotated by the player. The firing stop button is located on the side of the handle control unit. The firing stop button can be pressed by the player.

[0015] Furthermore, the launch handle unit 6 includes a launch volume 411, a touch sensor 412, and a launch stop switch 413. The firing volume 411 is composed of a variable resistor. The firing volume 411 detects the amount of rotation of the handle operating part (the angle by which the handle operating part is rotated). Specifically, the firing volume 411 is composed of a rotating shaft and a resistor whose resistance value changes according to the amount of rotation (rotation angle) of the rotating shaft. The rotating shaft of the firing volume 411 is fixed coaxially with the rotating shaft portion of the handle operating part. As a result, the rotating shaft of the firing volume 411 rotates in response to the rotation of the handle operating part, and the resistance value of the firing volume 411 changes according to the amount of rotation of the handle operating part. The firing volume 411 is electrically connected to the operation detection unit 421 (see Figure 4). The operation detection unit 421 detects the rotation operation (amount of rotation) of the handle operation unit based on the change in the resistance value (voltage value) of the firing volume 411. The touch sensor 412 detects contact (grasp) of the handle control unit by the player based on changes in capacitance. When contact by the player with the handle control unit is detected, the touch sensor 412 outputs a touch signal to the firing condition detection unit 422 (see Figure 4) (the touch signal is set to a high level). On the other hand, when contact by the player with the handle control unit is not detected, the touch sensor 412 stops outputting a touch signal to the firing condition detection unit 422 (the touch signal is set to a low level). The firing stop switch 413 detects when the firing stop button is pressed. When the firing stop button is not pressed, the firing stop switch 413 outputs a firing stop signal to the firing ready condition detection unit 422 (setting the firing stop signal to a high level). On the other hand, when the firing stop button is pressed, the firing stop switch 413 stops outputting the firing stop signal to the firing ready condition detection unit 422 (setting the firing stop signal to a low level).

[0016] (Configuration of game board unit 10) Next, the configuration of the game board unit 10 will be explained. Figure 2 shows the front view of the game board, and schematically illustrates the parts that are particularly necessary for explanation. The game board unit 10 is supported by the inner frame unit 3. Specifically, the game board unit 10 is mounted inside the inner frame of the inner frame unit 3. As a result, the game board unit 10 is positioned on the rear side of the integrated door unit 4. The player can then see the game board 11 (game area 30), which will be described later, through the transparent plate 4a. In this embodiment, the game area 30, which will be described later, is formed between the back of the transparent plate 4a and the front of the game board 11. As shown in Figure 2, the game board unit 10 comprises a set board (not shown), a game board 11 attached to the set board, and various display devices (main image display device 31, sub-image display device 32, movable unit, etc.) attached to the set board.

[0017] The set plate is formed in a box shape with the front side open. An opening consisting of a through hole is provided approximately in the center of the back panel of the set plate. The game board 11 is attached to the front side of the set board. The game board 11 is formed from resin in a flat shape. An opening (not shown) consisting of a through hole is provided approximately in the center of the game board 11. The player can then view the display screen 31a of the main image display device 31 through the opening provided in the game board 11 and the opening provided in the set board. Around the opening on the front of the game board 11, a game area 30 is formed through which the game balls launched in response to the rotation of the launch handle unit 6 flow down. Within the game area 30, two paths are formed for the flow of the game balls: a left-side path formed to the left of the main image display device 31, and a right-side path formed to the right of the main image display device 31. Furthermore, a panel lamp 21 (see Figure 3) is provided in the game area 30 of the game board 11. The panel lamp 21 is composed of multiple light-emitting elements (LEDs) that are driven by dynamic lighting control.

[0018] The main image display device 31 is mounted on the back side of the set board. The main image display device 31 is composed of variable display devices such as a liquid crystal display or a CRT (Cathode Ray Tube) display. The main image display device 31 includes a display screen 31a capable of displaying various types of presentation images (moving images and still images). The display screen 31a can be configured with three first-effect symbol display areas a1 to a3 (not shown) on which the first-effect symbol z1 (not shown) is displayed, and one second-effect symbol display area a4 (not shown) on which the second-effect symbol z2 (not shown) is displayed. The first display symbol z1 is composed of identification information (symbols) such as numbers, letters, symbols, and characters. Each of the first display symbol display areas a1 to a3 allows for the display of the first display symbol z1 changing and stopping. The second display symbol z2 is composed of a color bar. The second display symbol display area a4 allows for the display of the second display symbol z2 changing and stopping.

[0019] The display of changing symbols z1 and z2 refers to a display in which, in each of the first symbol display areas a1 to a3, the first symbol z1 moves (scrolls), and the type of the second symbol z2 displayed in the second symbol display area a4 changes (the color represented by the color bar changes sequentially). The display of stopped symbols z1 and z2 refers to a display in which one type of first symbol z1 is stopped at the lottery result display position in each first symbol display area a1 to a3, and one type of second symbol z2 is displayed in the second symbol display area a4 (the color bar represents a predetermined color). Then, the result of the special symbol lottery (either the first special symbol lottery or the second special symbol lottery) is displayed based on the combination of the first symbol z1 that is stopped and displayed in the three first symbol display areas a1 to a3, and the second symbol z2 that is stopped and displayed in the second symbol display area a4. Furthermore, the display screen 31a can be configured to include reserved symbol display areas b1 and b2 (not shown) where reserved symbols h (not shown) are displayed. The reserved symbol display area b1 displays the reserved symbol h corresponding to the game information during the notification display (special symbol variation display and stop display). The reserved symbol display area b2 displays the reserved symbol h corresponding to the game information for which the notification display is pending.

[0020] The sub-image display device 32 is positioned in front of the main image display device 31. The sub-image display device 32 is composed of a variable display device such as a liquid crystal display or a CRT display. The sub-image display device 32 has a display screen 32a capable of displaying performance images. The sub-image display device 32 can be displaced (moved) along the vertical direction by a drive mechanism (not shown). Specifically, the sub-image display device 32 can be displaced within a predetermined range that includes the origin position (see Figure 2) and a display position (not shown) below the origin position. Furthermore, the sub-image display device 32 positioned (displaced) at the origin position is located above the display screen 31a of the main image display device 31 and does not cover the display screen 31a. On the other hand, the sub-image display device 32 positioned (displaced) at the production position is located on the front side of the display screen 31a of the main image display device 31 and covers a portion of the display screen 31a.

[0021] Below the display screen 31a in the game area 30, a first start opening 51 is provided. The first start opening 51 is an upward-opening ball entry point (a so-called "center hole"), and game balls can be entered at all times. The first start opening 51 allows game balls flowing down the left-side path to enter (but does not allow game balls flowing down the right-side path to enter). A special symbol 1 start port switch 101 (see Figure 3) is installed inside the first start port 51. The special symbol 1 start port switch 101 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the first start port 51 (a game ball entering the first start port 51). The main control board 200 executes the first special symbol lottery in response to the input of the detection signal from the special symbol 1 start port switch 101.

[0022] To the left of the first starting opening 51 in the game area 30, there are three other prize openings: an upper left prize opening 55, a middle left prize opening 56, and a lower left prize opening 57. Each of the other prize openings 55-57 is an upward-opening ball entry point, allowing game balls to enter at all times. Each of the other prize openings 55-57 allows game balls flowing down the left-side path to enter (but does not allow game balls flowing down the right-side path to enter). The game board 11 is equipped with a left prize slot switch 106 (see Figure 3). The left prize slot switch 106 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the upper left prize slot 55, a game ball entering the left middle prize slot 56, and a game ball entering the lower left prize slot 57. The main control board 200, in response to the detection signal input from the left prize slot switch 106, causes the game ball dispensing device 440 to perform a prize ball dispensing operation.

[0023] A starting gate 41 is provided to the right of the display screen 31a in the game area 30. The starting gate 41 is designed to allow game balls to pass through at all times. The starting gate 41 allows game balls flowing down the right-hand path to pass through (but does not allow game balls flowing down the left-hand path to pass through). A gate switch 104 (see Figure 3) is installed at the starting gate 41. The gate switch 104 outputs a detection signal to the main control board 200 in response to the detection of a game ball passing through the starting gate 41 (passage of the starting gate 41 by a game ball). The main control board 200 performs a normal symbol lottery in response to the input of the detection signal from the gate switch 104.

[0024] Below the starting gate 41 in the game area 30, a large prize opening 53 is provided. The large prize opening 53 is equipped with a special electric mechanism (special electric mechanism) 53a (a so-called "attacker") that can be displaced between a closed state that makes it impossible for game balls to enter the large prize opening 53 and an open state that allows game balls to enter the large prize opening 53. The special electric mechanism 53a is opened and closed by the special electric mechanism solenoid 65 (see Figure 3). Normally, the special electric mechanism 53a is closed, making it impossible for game balls to enter the large prize opening 53. However, when the first special symbol lottery or the second special symbol lottery is won, and a jackpot game state is created, the special electric mechanism 53a is opened, making it possible for game balls to enter. The large prize opening 53 allows game balls flowing down the right-hand path to enter (but does not allow game balls flowing down the left-hand path to enter). A count switch 103 (see Figure 3) is installed inside the large prize opening 53. The count switch 103 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the large prize opening 53 (the entry of a game ball into the large prize opening 53). In response to the detection signal input from the count switch 103, the main control board 200 causes the game ball dispensing device 440 to perform the prize ball dispensing operation.

[0025] Below the large prize winning opening 53 in the game area 30, a second starting opening 52 is provided. The second starting opening 52 is equipped with a standard electric mechanism (standard electric mechanism) 52a (a so-called "electric tulip") that can be displaced between a closed state that makes it impossible for game balls to enter the second starting opening 52 and an open state that allows game balls to enter the second starting opening 52. The standard electric mechanism 52a is opened and closed by the standard electric mechanism solenoid 64 (see Figure 3). Normally, the standard electric mechanism 52a is closed at the second start port 52, making it impossible for game balls to enter. However, when the standard symbol lottery is won, the standard electric mechanism 52a is opened, making it possible for game balls to enter. The second start port 52 allows game balls flowing down the right-hand path to enter (but does not allow game balls flowing down the left-hand path to enter). A special symbol 2 start port switch 102 (see Figure 3) is installed inside the second start port 52. The special symbol 2 start port switch 102 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the second start port 52 (the entry of a game ball into the second start port 52). The main control board 200 executes the second special symbol lottery in response to the detection signal input from the special symbol 2 start port switch 102.

[0026] Below the second starting opening 52 in the game area 30, a right-side prize opening 54 is provided. The right-side prize opening 54 is an upward-opening ball entry opening, allowing game balls to enter at all times. The right-side prize opening 54 allows game balls flowing down the right-side path to enter (but does not allow game balls flowing down the left-side path to enter). A right prize slot switch 105 (see Figure 3) is installed inside the right prize slot 54. The right prize slot switch 105 outputs a detection signal to the main control board 200 in response to the detection of a game ball entering the right prize slot 54 (a game ball entering the right prize slot 54). The main control board 200 causes the game ball dispensing device 440 to perform a prize ball dispensing operation in response to the detection signal input from the right prize slot switch 105.

[0027] At the lowest position in the game area 30, there is an outlet 58 for discharging game balls that did not enter (win) any of the winning holes 51 to 57. Here, the inner frame unit 3 includes an outlet passage (not shown) through which the game balls discharged from the game area 30 pass. Specifically, the outlet passage is attached to the back side of the inner frame of the inner frame unit 3. In the pachinko machine 1, all game balls launched into the game area 30 (all game balls discharged from the game area 30) are configured to pass through the outlet passage. That is, game balls launched into the game area 30 are discharged from the game area 30 and flow into the outlet passage by entering one of the prize entry openings 51-57 or by passing through the out opening 58. Specifically, game balls that enter each prize slot 51-57 are detected by switches 101-103, 105, and 106 located within the prize slot, and then guided to the discharge path. Game balls discharged from the out slot 58 are also guided to the discharge path. An out switch 109 (see Figure 3) is installed in the inner frame unit 3. The out switch 109 outputs a detection signal to the main control board 200 in response to the detection of game balls passing through the discharge path (game balls discharged from the game area 30). In this way, all game balls discharged from the game area 30 are detected by the out switch 109. Furthermore, multiple pins (not shown) are arranged in the game area 30 to guide the game balls into each of the prize entry points 51-57 and the starting gate 41.

[0028] The game board 11 is equipped with a main display device 60. The main display device 60 is composed of multiple lighting elements (segments). Each lighting element is composed of a light-emitting element (in this embodiment, an LED). The main display device 60 displays information related to the game. The main display device 60 is composed of a special figure 1 display device, a special figure 2 display device, a regular figure display device, a special figure 1 hold display device, a special figure 2 hold display device, a regular figure hold display device, a round display device, a right-hand shooting display device, a probability variation display device, and a time reduction display device. Specifically, the main display device 60 is composed of 32 lighting elements (LED1 to LED32). In the main display device 60, LEDs 1 to 8 constitute the special feature 1 display device, LEDs 7 to 16 constitute the special feature 2 display device, LEDs 17 and 18 constitute the regular feature display device, LEDs 19 to 23 constitute the round display device, LED 24 constitutes the right-hand shooting display device, LEDs 25 and 26 constitute the special feature 1 hold display device, LEDs 27 and 28 constitute the special feature 2 hold display device, LEDs 29 and 30 constitute the regular feature hold display device, LED 31 constitutes the probability variation display device, and LED 32 constitutes the time reduction display device.

[0029] The Special Symbol 1 display device is capable of displaying the fluctuations and stops of the first special symbol, which consists of numbers and symbols. The Special Symbol 1 display device then displays the result of the first special symbol lottery based on the first special symbol that is stopped. The Special Symbol 2 display device is capable of displaying the fluctuations and stops of the second special symbol, which consists of numbers and symbols. The Special Symbol 2 display device then displays the result of the second special symbol lottery based on the second special symbol that has stopped. Here, the display of special symbols (first special symbol or second special symbol) in the special symbol display device and the display of performance symbols z1 and z2 in the performance symbol display areas a1 to a4 are associated with the timing of when the variable display starts, when the stop display starts, and the lottery result indicated by the stopped display. Furthermore, if the first special symbol (stopped symbol) displayed on the special symbol 1 display device becomes a specific symbol (jackpot symbol), or if the second special symbol (stopped symbol) displayed on the special symbol 2 display device becomes a specific symbol (jackpot symbol), a jackpot game state, which is advantageous to the player, is created.

[0030] The regular symbol display device is capable of displaying the fluctuations and stops of regular symbols, which consist of numbers, patterns, etc. The regular symbol display device then displays the result of the regular symbol lottery based on the regular symbols that have stopped. When the regular symbols that have stopped on the regular symbol display device become a specific symbol (a regular symbol winning symbol), a regular symbol winning game state, which is advantageous to the player, is created.

[0031] The Special Symbol 1 Reserve Display Device shows the number of times the result of the first special symbol lottery has been reserved (Special Symbol 1 Reserve Count). The Special Symbol 2 Reserve Display Device shows the number of times the result of the second special symbol lottery has been reserved (Special Symbol 2 Reserve Count). The regular symbol hold display device shows the number of times the results of the regular symbol lottery have been held in abeyance (number of regular symbol holds). The round display device shows the number of rounds played during a jackpot state (the type of jackpot state). The right-hand side display shows the path the game ball should be launched along (left-side path or right-side path). The probability variation display shows the game state upon power restoration (whether a high probability state for special symbols is active or a low probability state for special symbols is active). The time-saving display device shows the current game status (whether time-saving control is running or stopped).

[0032] Furthermore, the pachinko machine 1 is equipped with one or more movable units (not shown). In this embodiment, one or more movable units are provided in the integrated door unit 4, and one or more movable units are provided in the game board unit 10. Each movable unit of the integrated door unit 4 is positioned on the front of the decorative section 4b, the top surface of the receiving unit 5, etc., and is capable of performing predetermined display actions. Each movable unit of the game board unit 10 is attached to the front side of the set board. Specifically, each movable unit is positioned in the space between the game board 11 and the main image display device 31 (display screen 31a) (hereinafter referred to as the "performance space"). Each movable unit is capable of performing predetermined performance actions within the performance space. Each movable unit comprises a performance element, a drive mechanism, a drive source, and a position detection sensor 24 (see Figure 3). In this embodiment, a motor 23 (see Figure 3) is used as the drive source. The motor 23 is a stepping motor. Alternatively, a solenoid may be used as the drive source. The performance component can be displaced along a predetermined direction by a drive mechanism. Specifically, the performance component can be displaced to multiple positions, including an initial position and a performance position. The performance component is driven (displaced) by a motor 23.

[0033] The position detection sensor 24 is composed of a photosensor or the like. The position detection sensor 24 detects the position of the performance element. Specifically, the position detection sensor 24 comprises a light-emitting unit and a light-receiving unit that receives the light emitted from the light-emitting unit. The position detection sensor 24 outputs a detection signal to the performance control board 300 in response to the light-receiving unit receiving (detecting) the light emitted from the light-emitting unit. On the other hand, when the light-receiving unit is not receiving (detecting) the light emitted from the light-emitting unit, the position detection sensor 24 stops outputting the detection signal to the performance control board 300. Furthermore, a shielding plate is provided at a predetermined position of the performance component. When the performance component is in its initial position, the shielding plate is placed between the light-emitting and light-receiving sections of the position detection sensor 24, blocking the entry of light into the light-receiving section. As a result, when the performance component is in its initial position, the output of a detection signal from the position detection sensor 24 to the performance control board 300 is stopped. On the other hand, when the performance component is not in its initial position, a detection signal is output from the position detection sensor 24 to the performance control board 300. This allows the performance control board 300 to detect whether or not the performance element is positioned in its initial location based on the input status of the detection signal from the position detection sensor 24.

[0034] Furthermore, the pachinko machine 1 is equipped with detection sensors that can detect various abnormal conditions. In this embodiment, detection sensors such as a glass frame opening sensor 107, an inner frame opening sensor 108, a vibration detection sensor 113, a radio wave detection sensor 114, and a magnetic detection sensor 115 are provided. The glass frame release sensor 107 detects the opening of the integrated door unit 4 relative to the inner frame unit 3. In response to the opening of the integrated door unit 4 relative to the inner frame unit 3, the glass frame release sensor 107 transmits a detection signal to the main control board 200 via the dispensing control board 400. The inner frame release sensor 108 detects the release of the inner frame unit 3 relative to the outer frame unit 2. In response to the release of the inner frame unit 3 relative to the outer frame unit 2, the inner frame release sensor 108 transmits a detection signal to the main control board 200 via the dispensing control board 400.

[0035] The vibration detection sensor 113 detects vibrations of the game board 11. In this embodiment, the vibration detection sensor 113 is installed on the game board 11. The vibration detection sensor 113 then transmits a detection signal to the main control board 200 in response to the detection of vibrations of the game board 11. The radio wave detection sensor 114 detects radio waves generated around the game board 11. In this embodiment, two radio wave detection sensors 114 are installed in the game board 11. Each radio wave detection sensor 114 transmits a detection signal to the main control board 200 in response to the detection of radio waves. The magnetic detection sensor 115 detects the magnetic field generated around the game board 11. In this embodiment, three magnetic detection sensors 115 are provided. Specifically, one magnetic detection sensor 115 is provided in the inner frame unit 3 (discharge path). Two magnetic detection sensors 115 are provided on the game board 11. The magnetic detection sensor 115 provided in the inner frame unit 3 transmits a detection signal to the main control board 200 via the payout control board 400 in response to the detection of magnetic field. Each magnetic detection sensor 115 provided on the game board 11 also transmits a detection signal to the main control board 200 in response to the detection of magnetic field.

[0036] (Control system configuration) Next, the configuration of the control system in pachinko machine 1 will be explained. Figure 3 is a block diagram showing the configuration of the control system of a pachinko machine. Figure 6 is the address map of the memory area used by the CPU 210. Pachinko machine 1 is equipped with various control boards. Specifically, as shown in Figure 3, the pachinko machine 1 is equipped with multiple control boards, including a main control board 200, a performance control board 300, a payout control board 400, a power supply board 600 that supplies power to each of the control boards 200, 300, 400, etc., a driver board 330, a sub-connection board 340, etc. The multiple control boards 200, 300, 400, and 600 are independent (separate) circuit boards. Furthermore, each control board 200, 300, 400, and 600 is housed in its own individual board case. The main control board 200 and the performance control board 300 are included in the game board unit 10. Specifically, the main control board 200 and the performance control board 300 are mounted on the back side of the game board 11. The dispensing control board 400 is included in the inner frame unit 3. Specifically, the dispensing control board 400 is mounted on the back side of the inner frame of the inner frame unit 3.

[0037] (Configuration of the main control board 200) First, let's explain the configuration of the main control board 200. The main control board 200 controls the progress of the game. The main control board 200 is composed of a one-chip microcomputer (one-chip microcontroller), a clock generation circuit 202, a random number generation circuit 203, an input port 204, an output port 205, a performance display device 206, a RAM clear switch 207, a setting key switch 208, a sink driver 240, source drivers 250a and 250b, etc. A single-chip microcomputer is an LSI that integrates a CPU core, registers, semiconductor memory, and other components. Specifically, a single-chip microcomputer consists of a CPU 210, ROM 220, RAM 230, and so on.

[0038] The main control board 200 is configured to include a memory area used by the CPU 210. As shown in Figure 6, the memory area used by the CPU 210 is configured to include a memory area allocated to the ROM 220 (0000H to 2FFFH) and a memory area allocated to the RAM 230 (F000H to F3FFH). In Figure 6, the address used to identify the memory region is shown in hexadecimal (the "H" indicates that it is a hexadecimal number).

[0039] ROM220 (the memory area of ​​ROM220) consists of a used area m1 (0000H to 1A7AH) and an unused area m2 (2000H to 2BFFH). The used area m1 consists of a program area, an unused area, and a data area. The program area stores the program (program code) for controlling the progress of the game. The data area stores the data (program data) for controlling the progress of the game. Note that the used area m1 does not necessarily have to include an unused area.

[0040] The unused area m2 consists of a program area and a data area. The program area stores a program (program code) for executing the tests specified in the Gaming Machine Regulations and a program (program code) for controlling the display of the performance display device 206 (specifically, for calculating the base ratio). The data area stores data (program data) for executing the tests specified in the Gaming Machine Regulations and data (program data) for controlling the display of the performance display device 206. In addition to the used area m1 and the unused area m2, the ROM220 also includes unused areas, a ROM comment area, a program management area, and other areas. The ROM comment area stores arbitrary data such as the program title and version. On the other hand, the program management area stores the information necessary for the CPU 210 to execute various programs. Furthermore, the ROM220 has an unused area m3 of a predetermined number of bytes (for example, 16 bytes or more) between the used area m1 and the unused area m2. This clarifies the boundary between the used area m1 and the unused area m2.

[0041] RAM230 (the memory area of ​​RAM230) consists of a used area M1 (F000H to F1FFH) and an unused area M2 (F300H to F3FFH). The usage area M1 consists of a work area and a stack area. The work area is used to temporarily store various data while the program stored in the usage area m1 (the program that controls the progress of the game) is being executed. On the other hand, the stack area is used to temporarily save various data while the program stored in the usage area m1 (the program that controls the progress of the game) is being executed. Note that the usage area M1 does not necessarily have to include any unused area. Specifically, the work area consists of a setting value area, a game machine status flag area, a checksum area, a backup flag area, an error-related area, a normal game-related area 1, and a normal game-related area 2. The setting value area stores the setting value. The game machine status flag area stores the game machine status flag. The checksum area stores the checksum. The backup flag area stores the backup flag. The error-related area stores information related to errors. The normal game-related area 1 stores subcommand pointers, etc. The normal game-related area 2 stores input / output data for the main control board 200, data for calculation processing, various counters (random number counter, timer counter, etc.), flags for managing lottery results and game status, etc. In particular, the normal game-related area 2 includes an area (game information storage area described later) that stores game information acquired in response to the input of detection signals from the special figure 1 start port switch 101, the special figure 2 start port switch 102, and the gate switch 104.

[0042] The unused area M2 consists of a work area and a stack area. The work area is used as a temporary storage area for various data while programs stored in the unused area m2 (programs for executing tests specified in the gaming machine regulations, or programs for controlling the display of the performance display device 206) are being executed. On the other hand, the stack area is used as a temporary storage area for various data while programs stored in the unused area m2 (programs for executing tests specified in the gaming machine regulations, or programs for controlling the display of the performance display device 206) are being executed. Specifically, the work area includes a performance display-related area. The performance display-related area is used as a temporary storage area for various data during the execution of a program for controlling the display of the performance display device 206. Furthermore, the RAM230 has an unused area M3 of a predetermined number of bytes (16 bytes or more) between the used area M1 and the unused area M2. This clarifies the boundary between the used area M1 and the unused area M2.

[0043] In this embodiment, processing based on a program (a program for controlling the progress of the game) stored in the used area m1 is permitted to refer to data stored in the unused area M2. On the other hand, processing based on the program stored in the used area m1 (a program for controlling the progress of the game) is prohibited from overwriting (changing) the data stored in the unused area M2. Furthermore, in processing based on a program stored in the unused area m2 (a program for executing tests specified in the gaming machine regulations, or a program for controlling the display of the performance display device 206), it is permitted to refer to data stored in the used area M1. On the other hand, it is prohibited for data stored in the used area M1 to be rewritten (modified) by processing based on a program stored in the unused area m2 (a program for executing tests specified in the gaming machine regulations, or a program for controlling the display of the performance display device 206). Furthermore, the gameplay in pachinko machine 1 can be completed (progressed) by a program (a program for controlling the progress of the game) stored in the usage area m1.

[0044] The clock generation circuit 202 generates a clock (synchronization signal) at a predetermined clock frequency (12 MHz in this embodiment) and outputs this clock to the CPU 210 and the random number generation circuit 203, respectively. The random number generation circuit 203 includes a first loop counter that generates winning random numbers for the normal symbol lottery, a second loop counter that generates jackpot random numbers for the first special symbol lottery, a third loop counter that generates jackpot random numbers for the second special symbol lottery, and a fourth loop counter that generates reach group random numbers. The first loop counter generates a winning random number for the normal symbol lottery by updating the value of the loop counter by 1 within a predetermined range (in this embodiment, within the range of 0 to 65535) each time one clock signal is input from the clock generation circuit 202. In this embodiment, the value of the first loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz] = 0.083 [μs]). The second loop counter generates a winning random number for the first special symbol lottery by updating its value by 1 within a predetermined range (in this embodiment, within the range of 0 to 65535) each time a clock signal is input from the clock generation circuit 202. In this embodiment, the value of the second loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz] = 0.083 [μs]).

[0045] The third loop counter generates a winning random number for the second special symbol lottery by updating the value of the loop counter by 1 within a predetermined range (in this embodiment, within the range of 0 to 65535) each time one clock signal is input from the clock generation circuit 202. In this embodiment, the value of the third loop counter is updated every 0.083 [μs] (1 [s] / 12 [MHz] = 0.083 [μs]). The fourth loop counter generates a reach group random number by updating the value of the loop counter by 1 within a predetermined range (in this embodiment, within the range of 0 to 10006) every 32 clocks input from the clock generation circuit 202 (once every 32 divisions of the clock frequency). In this embodiment, the value of the fourth loop counter is updated every 2.666 [μs] (32 [s] / 12 [MHz] = 2.666 [μs]).

[0046] The input port 204 is configured to include multiple input ports (in this embodiment, input ports 0 to 3). Input port 0 receives detection signals from the glass frame release sensor 107, the inner frame release sensor 108, the vibration detection sensor 113, the one-way radio wave detection sensor 114, the magnetic detection sensor 115, and the like. Input port 1 receives signals such as the RAM clear signal from the RAM clear switch 207, the detection signal from the setting key switch 208, and the handle detection signal from the firing condition detection unit 422. Input port 2 receives detection signals from the count switch 103, the right prize slot switch 105, the left prize slot switch 106, the output switch 109, and the other radio wave detection sensor 114, among others. Input port 3 receives detection signals from the start switch 101 (Figure 1), the start switch 102 (Figure 2), the gate switch 104, and the like. Each input port (input port 0 to input port 3) is provided with a receiving memory area corresponding to each switch / sensor (detection signal). Each receiving memory area corresponding to a switch / sensor is set with 1 bit of data indicating the reception status of the detection signal from that switch / sensor. Specifically, the receiving memory area corresponding to each switch / sensor is set to "1" when a detection signal from that switch / sensor is input (high level), and to "0" when no detection signal from that switch / sensor is input (low level).

[0047] Output port 205 is configured to include multiple output ports (in this embodiment, output ports 0 to 4). Output port 0 outputs data signals ("SEGDATA0" to "SEGDATA7") for controlling the illumination of the main display device 60. The data signals output from output port 0 are then input to the source driver 250a. Output port 1 outputs common signals ("COM0" to "COM3") for controlling the illumination of the main display device 60 and the performance display device 206, as well as a launch permission signal for detecting the launch conditions described later. The common signals output from output port 1 are input to the sink driver 240. Output port 2 outputs an external signal. In this case, the external signal output from output port 2 is input to the hall computer via the payout control board 400 and the external terminal board 450. Output port 3 outputs control signals for controlling the drive of the standard electric mechanism solenoid 64, control signals for controlling the drive of the special electric mechanism solenoid 65, and the like. Output port 4 outputs data signals ("7SEGDATA0" to "7SEGDATA7") for controlling the illumination of the performance display device 206. The data signals output from output port 4 are then input to the source driver 250b.

[0048] Furthermore, the main control board 200 is configured to include command output port 1 and command output port 2. The CPU 210 transmits control commands (subcommands) from command output port 1 to the performance control board 300, and transmits control commands (payout commands) from command output port 2 to the payout control board 400. Command output port 1 and command output port 2 each have a data register for transmission (not shown), a FIFO (First In First Out) buffer (not shown), and a shift register for transmission (not shown), respectively. The data register for transmission outputs the control command entered based on the subcommand transmission process (step S2-4) described later to the FIFO buffer. The FIFO buffer consists of multiple registers and is capable of storing multiple control commands. The FIFO buffer stores the control commands input from the transmit data register and outputs the stored control commands to the transmit shift register in the order they were input. The transmission shift register performs parallel-to-serial conversion on the control commands input from the FIFO buffer and transmits them as serial data to the performance control board 300 or the payout control board 400.

[0049] The performance display device 206 is composed of multiple lighting elements (segments). Each lighting element is composed of a light-emitting element (LED in this embodiment). The performance display device 206 is located on the back side of the game board 11, making it impossible for the player to see it. As will be described later, in pachinko machine 1, the following states of the game machine (hereinafter referred to as "game machine state") are defined: playable state, setting change state, setting confirmation state, setting abnormal state, RAM abnormal state, and backup abnormal state. The information displayed on the performance display device 206 changes according to the game machine state that is occurring.

[0050] The performance display device 206 is composed of four (four-digit) display units (not shown). Each display unit is composed of eight lighting elements. Specifically, each display unit is composed of a 7-segment LED capable of displaying numbers, symbols, etc., and a dot-segment LED capable of displaying dots such as decimal points. Specifically, the performance display device 206 is composed of 32 lighting elements (LEDs 33 to 64). In the performance display device 206, LEDs 33 to 40 form the first digit display, LEDs 41 to 48 form the second digit display, LEDs 49 to 56 form the third digit display, and LEDs 57 to 64 form the fourth digit display.

[0051] While the game-ready state is active, the game can proceed. During this time, the base ratio is displayed on the performance display device 206. In this embodiment, while the game is playable, the first base ratio and the second base ratio are displayed alternately on the performance display device 206 at predetermined intervals (5.0 seconds in this embodiment). The "first base ratio" is the base ratio for the current section (the base ratio calculated for the period from the start of the current section to the present). The "second base ratio" is the base ratio for the previous interval (the final base ratio calculated for the previous interval). Specifically, in the performance display device 206, the upper two digits of the four-digit display section show information for identifying the type of base ratio (first base ratio or second base ratio), and the lower two digits display section shows a number indicating the base ratio (percentage).

[0052] While the setting change state is active, it becomes possible to change the setting value. Furthermore, while the setting change state is active, the performance display device 206 displays the setting value stored (set) in the setting value area of ​​the RAM 230. Specifically, in the performance display device 206, the top three digits of the four-digit display section show information indicating that a setting change state is occurring (specifically, "r" in the first digit, "n." in the second digit, and "-" in the third digit), and the last digit displays a number indicating the setting value stored in the setting value area. While the setting confirmation state is active, it becomes possible to check the setting values. During this time, the performance display device 206 displays the setting values ​​stored (set) in the setting value area of ​​the RAM 230. Specifically, in the performance display device 206, the top three digits of the four-digit display section show information indicating that the setting confirmation state is in progress (specifically, "r" in the first digit, "n." in the second digit, and no display in the third digit), and the last digit displays a number indicating the setting value stored in the setting value area.

[0053] During a game stoppage state (setting error state, RAM error state, and backup error state), it becomes impossible to continue playing the game. Furthermore, during a game stoppage state, the performance display device 206 displays an error code corresponding to the error that occurred. Specifically, in the performance display device 206, the top three digits of the four-digit display section show information indicating that a game stop state is occurring (specifically, "E" in the first digit, "r." in the second digit, and no display in the third digit), and the last digit displays a number indicating an error code corresponding to the abnormality that occurred (setting abnormality state, RAM abnormality state, or backup abnormality state).

[0054] The RAM clear switch 207 is a tactile switch. That is, the RAM clear switch 207 is configured to include a pressable operating part. When the operating part is pressed, the RAM clear switch 207 outputs a RAM clear signal to input port 1. The setting key switch 208 is a key lock switch. That is, the setting key switch 208 is composed of an operating part with a keyhole. When a special key is inserted into the keyhole, the lock on the operating part is released, and it becomes possible to rotate (switch) it from the OFF state to the ON state. When the operating part of the setting key switch 208 is in the ON state, it outputs a detection signal to input port 1.

[0055] The sink driver 240 controls the output of common signals ("COM0" to "COM3") to each display device 60,206 according to the common signals output from output port 1. The source driver 250a controls the output of data signals to the main display device 60 according to the data signals ("SEGDATA0" to "SEGDATA7") output from output port 0. The source driver 250b controls the output of data signals to the performance display device 206 according to the data signals ("7SEGDATA0" to "7SEGDATA7") output from output port 4. In the pachinko machine 1, a source driver 250a corresponding to the main display device 60 and a source driver 250b corresponding to the performance display device 206 are provided. The application of the power supply voltage Vcc to the data signal lines is controlled individually by the main display device 60 and the performance display device 206. On the other hand, in the pachinko machine 1, a common sink driver 240 is provided for the main display device 60 and the performance display device 206. The grounding of the common signal line is controlled collectively by the main display device 60 and the performance display device 206. This eliminates the need to provide a sink driver 240 corresponding to the main display device 60 and the performance display device 206, and as a result, eliminates the need to provide an output port (an output port for outputting common signals) corresponding to the main display device 60 and the performance display device 206. Therefore, it becomes possible to reduce the number of components required to control the illumination of the main display device 60 and the performance display device 206, and the main control board 200 (CPU 210) no longer needs to generate common signals corresponding to the main display device 60 and the performance display device 206, thereby reducing the control load for controlling the illumination of the main display device 60 and the performance display device 206.

[0056] Furthermore, the main control board 200 is configured to include a test signal output circuit (not shown). In the test signal output processing (step S4-24) described later, the CPU 210 generates test information (test signals) indicating the internal state (jackpot game state, time-saving control execution state, probability state of special symbol lottery, etc.), and stores the generated test signals in the port output request buffer of the RAM 230. As a result, the test signals stored in the port output request buffer are output from a predetermined output port. The test signals output from the predetermined output port are then input to the interface board of a test computer (not shown) via the test signal output circuit. Furthermore, on the main control board 200, detection signals from the start switch 101 (Figure 1), the start switch 102 (Figure 2), the gate switch 104, the count switch 103, the right prize slot switch 105, the left prize slot switch 106, the out switch 109, etc., are input to the input port 204 and also to the interface board of the test computer via the test signal output circuit. Furthermore, on the main control board 200, control signals for controlling the drive of each solenoid (ordinary electric mechanism solenoid 64, special electric mechanism solenoid 65, etc.) output from output port 3 are input to each solenoid 64, 65, and are also input to the interface board of the test computer via the test signal output circuit.

[0057] (Configuration of the dispensing control board 400) Next, the configuration of the dispensing control board 400 will be explained. Figure 4 is a block diagram showing the configuration of the launch condition detection circuit and the launch control circuit. The payout control board 400 controls the launch of game balls into the game area 30 and the payout of game balls. The dispensing control board 400 includes a one-chip microcomputer. A single-chip microcomputer is an LSI (Large-Scale Integrated Circuit) that integrates a CPU core, registers, semiconductor memory, and other components. Specifically, a single-chip microcomputer consists of a CPU, ROM (Remote Memory), RAM (Backup Memory), and other components. The payout control board 400 controls the game ball payout operation (prize ball payout operation) by the game ball payout device 440 based on control commands received from the main control board 200. The payout control board 400 also controls the game ball payout operation (loaned ball payout operation) by the game ball payout device 440 based on ball lending instruction signals received from the CR unit 700. Furthermore, the payout control board 400 controls the game ball launching operation of the game ball launching device 430 (launch solenoid 431) based on the resistance value (voltage value) input from the launch volume 411, the touch signal input from the touch sensor 412, the launch stop signal input from the launch stop switch 413, the launch permission signal input from the main control board 200, and the CR connection signal input from the CR unit 700. The following describes in detail how the payout control board 400 controls the game ball launch operation.

[0058] As shown in Figure 4, the payout control board 400 is configured to include a launch condition detection circuit 420 and a launch control circuit 425 as circuits for controlling the game ball payout operation. The launch condition detection circuit 420 is a circuit that detects when the launch conditions described later are met. The launch condition detection circuit 420 includes an operation detection unit 421, a launch-ready condition detection unit 422, and a launch condition detection unit 423. The operation detection unit 421 is a circuit that detects the rotation operation (amount of rotation) of the handle operation unit. The operation detection unit 421 includes an operational amplifier that controls the output of the operation detection signal (sets the operation detection signal to a high level or a low level) according to the resistance value (voltage value) of the firing volume 411. Specifically, in the firing handle unit 6, the resistance value of the firing volume 411 changes according to the amount of rotation of the handle operating part. The operation detection unit 421 then detects the resistance value (voltage value) of the firing volume 411 and, based on the detected resistance value (voltage value), detects whether or not the handle operating part has been rotated and the amount of rotation of the handle operating part. The operation detection unit 421 generates an operation detection signal when it detects rotational operation of the handle control unit, and outputs the generated operation detection signal to the firing condition detection unit 422 (setting the operation detection signal to a high level). On the other hand, when the operation detection unit 421 does not detect rotational operation of the handle control unit, it stops outputting the operation detection signal to the firing condition detection unit 422 (setting the operation detection signal to a low level). Furthermore, when the operation detection unit 421 detects rotation of the handle operation unit, it generates a firing intensity signal corresponding to the amount of rotation of the handle operation unit (resistance value of the firing volume 411), and outputs the generated firing intensity signal to the firing control circuit 425.

[0059] The launch-ready-to-launch condition detection unit 422 is a circuit that detects when the launch-ready-to-launch conditions are met. The firing condition detection unit 422 includes an AND gate IC (logic IC) that controls the output and stopping of a predetermined signal according to the result of a logical AND operation of the operation detection signal, the touch signal, and the firing stop signal, and a transistor that switches the output and stopping of the handle detection signal according to a predetermined signal output from the AND gate IC. The "fire conditions" are among the multiple conditions that make up the firing conditions, which will be described later, and are conditions related to the player's actions (the player's intentions). The firing conditions include (1) conditions based on the detection status of the firing volume 441 and the operation detection unit 421 (detection status of rotation operation of the handle operation unit), (2) conditions based on the detection status of the touch sensor 412 (detection status of contact of the player with the handle operation unit), and (3) conditions based on the detection status of the firing stop switch 413 (detection status of pressing the firing stop button). In this embodiment, the firing condition is met when all of the following conditions are met: (1) the firing volume 441 and the operation detection unit 421 detect rotation of the handle operation unit; (2) the touch sensor 412 detects contact of the player with the handle operation unit; and (3) the firing stop switch 413 does not detect pressing the firing stop button. On the other hand, the firing condition is not met when at least one of the conditions (1) to (3) is not met. Here, the firing conditions may include (1) conditions based on the detection status of the firing volume 441 and the operation detection unit 421 (detection status of rotation operation of the handle operation unit), and (2) conditions based on the detection status of the touch sensor 412 (detection status of contact of the player with the handle operation unit), but may not include (3) conditions based on the detection status of the firing stop switch 413 (detection status of pressing the firing stop button). In other words, the firing condition is met when both of the following conditions are met: (1) rotation of the handle operating part is detected by the firing volume 441 and the operation detection unit 421, and (2) contact of the player with the handle operating part is detected by the touch sensor 412. The firing condition is not met when at least one of the conditions (1) and (2) is not met.

[0060] Specifically, the launch-ready-to-fire condition detection unit 422 detects whether or not the launch-ready-to-fire conditions are met based on the operation detection signal input from the operation detection unit 421, the touch signal input from the touch sensor 412, and the launch stop signal input from the launch stop switch 413. In this case, the launch readiness condition detection unit 422 detects that the launch readiness condition has been met when all three signals—operation detection signal, touch signal, and launch stop signal—are input. On the other hand, if at least one of the operation detection signal, touch signal, and launch stop signal is not input, the launch readiness condition has not been detected. The launch-ready-to-fire condition detection unit 422 generates a handle detection signal when it detects that the launch-ready-to-fire conditions have been met, and outputs the generated handle detection signal to the main control board 200 and the launch-ready-to-fire condition detection unit 423, respectively (setting the handle detection signal to a high level). On the other hand, when the launch-ready-to-fire condition detection unit 422 does not detect that the launch-ready-to-fire conditions have been met, it stops outputting the handle detection signal to the main control board 200 and the launch-ready-to-fire condition detection unit 423, respectively (setting the handle detection signal to a low level).

[0061] The launch condition detection unit 423 is a circuit that detects when the launch conditions are met. The firing condition detection unit 423 includes an AND gate IC (logic IC) that controls the output and stop of the firing signal according to the result of a logical AND operation of the handle detection signal, the firing permission signal, and the CR connection signal. The "launching conditions" are the conditions under which the game ball launching device 430 (launching solenoid 431) launches game balls into the game area 30 (game ball launching operation). In this embodiment, the firing condition is met when all of the following conditions are satisfied: (1) the firing ready condition is met, (2) a firing permission signal is input from the main control board 200, and (3) a CR connection signal is input from the CR unit 700. On the other hand, the firing condition is not met when at least one of the conditions (1) to (3) is not met. The "launch permission signal" is output from the main control board 200 to the launch condition detection unit 423 when the game-ready state is set, assuming that communication is possible between the main control board 200 and the payout control board 400 (i.e., the main control board 200 and the payout control board 400 are electrically connected). Here, it is also possible to configure the system so that, while the main control board 200 is powered on, a launch permission signal is output from the main control board 200 to the launch condition detection unit 423, regardless of the state of the gaming machine. In other words, it is also possible to configure the system so that a launch permission signal is output from the main control board 200 to the launch condition detection unit 423 when communication is possible between the main control board 200 and the payout control board 400 (when the main control board 200 and the payout control board 400 are electrically connected). The "CR connection signal" is output from the CR unit 700 to the firing condition detection unit 423 when communication is possible between the CR unit 700 and the dispensing control board 400 (when the CR unit 700 and the dispensing control board 400 are electrically connected).

[0062] Specifically, the firing condition detection unit 423 detects whether or not the firing conditions are met based on the handle detection signal input from the firing-ready condition detection unit 422, the firing permission signal input from the main control board 200, and the CR connection signal input from the CR unit 700. In this case, the firing condition detection unit 423 detects that the firing condition has been met when all three signals—the handle detection signal, the firing permission signal, and the CR connection signal—are input. On the other hand, if at least one of the three signals—the handle detection signal, the firing permission signal, and the CR connection signal—is not input, the firing condition has not been detected. The launch condition detection unit 423 generates a launch signal when it detects that the launch conditions have been met, and outputs the generated launch signal to the launch control circuit 425 (setting the launch signal to a high level). On the other hand, when the launch condition detection unit 423 does not detect that the launch conditions have been met, it stops outputting the launch signal to the launch control circuit 425 (setting the launch signal to a low level).

[0063] The launch control circuit 425 is a circuit that controls the launch intensity of the game balls launched by the game ball launcher 430 and the launch timing of the game balls launched by the game ball launcher 430. In other words, the launch control circuit 425 controls the output of the drive signal to the game ball launcher 430 (launch solenoid 431). Specifically, the firing control circuit 425 includes a clock generation unit (not shown), a firing timing control unit (not shown), and a firing solenoid drive unit (not shown). The clock generation unit outputs a clock signal of a predetermined frequency to the firing timing control unit. The launch timing control unit generates a pulse signal to control the launch timing based on the clock signal input from the clock generation unit, and outputs the generated pulse signal to the launch solenoid drive unit. At this time, the launch timing control unit generates the pulse signal so that the number of game balls launched per minute is a predetermined number (for example, 100 balls). The firing solenoid drive unit controls the output of the drive signal to the firing solenoid 431 based on the firing signal input from the firing condition detection unit 423, the pulse signal input from the firing timing control unit, and the firing intensity signal input from the operation detection unit 421. Specifically, when a launch signal is input from the launch condition detection unit 423, and a pulse signal is input from the launch timing control unit, the launch solenoid drive unit outputs a drive signal (drive current) to the launch solenoid 431 corresponding to the launch intensity signal input from the operation detection unit 421. As a result, the game ball is launched with an intensity corresponding to the launch intensity signal input from the operation detection unit 421. On the other hand, the launch solenoid drive unit stops outputting a drive signal to the launch solenoid 431 when no launch signal is input from the launch condition detection unit 423. This stops the launch of the game balls.

[0064] The game ball launching device 430 includes a ball-striking hammer (not shown) and a launching solenoid 431 that drives the ball-striking hammer. The launching solenoid 431 is a rotary solenoid. Alternatively, the ball-striking hammer may be driven by another drive source, such as a motor. The game ball launching device 430 is supplied with game balls from a ball feeding unit (not shown). When a drive signal is input to the launching solenoid 431, the launching solenoid 431 is driven according to the input drive signal, and the game ball is launched by the ball striking hammer. In this way, the game ball is launched into the game area 30.

[0065] Based on the above, in the pachinko machine 1, assuming that the main control board 200 is set to a playable state and that communication is possible between the CR unit 700 and the payout control board 400, if the player does not press the launch stop button and the handle operation part is rotated by contact (displaced from the initial position toward the limit position), the game ball launching operation by the game ball launching device 430 is started. During the execution of the game ball launching operation by the game ball launching device 430, game balls are launched into the game area 30 with a strength corresponding to the amount of rotation of the handle operation part. Furthermore, when the launch stop button is pressed, the game ball launching operation by the game ball launching device 430 is stopped. In other words, even when the handle is being rotated by the player's contact, when the launch stop button is pressed, the game ball launching operation by the game ball launching device 430 is stopped. Furthermore, when the handle is returned to its initial position (i.e., when the handle is not being rotated), the game ball launching operation by the game ball launching device 430 stops. In other words, even if the player is in contact with the handle, when the handle is returned to its initial position, the game ball launching operation by the game ball launching device 430 stops.

[0066] In particular, in the pachinko machine 1, while the conditions for launching are met (hereinafter referred to as the "launchable state"), the output of a handle detection signal from the launchable condition detection unit 422 to the main control board 200 is maintained. In other words, while a state is in which rotation of the handle operating part is detected, contact with the handle operating part is detected, and the firing stop button is not pressed (firing ready state), the firing condition detection circuit 420 maintains output of a handle detection signal to the main control board 200. In this case, as long as the firing-ready state is in effect, the output of a handle detection signal from the firing condition detection circuit 420 to the main control board 200 is maintained, regardless of whether or not a firing permission signal is input from the main control board 200 to the firing condition detection circuit 420 (regardless of the game machine state set in the main control board 200). Furthermore, as long as the launch-ready state is in effect, the output of a handle detection signal from the launch condition detection circuit 420 to the main control board 200 is maintained regardless of whether or not a CR connection signal is input from the CR unit 700 to the launch condition detection circuit 420 (regardless of whether or not communication is possible between the CR unit 700 and the dispensing control board 400). As a result, the main control board 200 can detect (understand) whether or not a firing-ready state is currently in place, and can control the progress of the game, the content of the effects, etc., according to the status of the firing-ready state.

[0067] In other words, when the main control board 200 detects that the handle detection signal has changed from a state where no signal is input to a state where a signal is input (the handle detection signal has changed from a low level to a high level), it sends a game status specification command to the performance control board 300 that specifies the occurrence (start) of a firing-ready state. On the other hand, when the main control board 200 detects that the handle detection signal has changed from being input to not being input (the handle detection signal has changed from a high level to a low level), it sends a game status specification command to the performance control board 300 that specifies the cancellation (end) of the firing-ready state. As a result, the performance control board 300 can detect the occurrence of a launchable state by receiving a game status specification command that specifies the occurrence of a launchable state, and can detect the cancellation of the launchable state by receiving a game status specification command that specifies the cancellation of the launchable state. Furthermore, the performance control board 300 can change the performance content depending on whether or not a firing-ready state is currently in place.

[0068] (Configuration of the performance control board 300) Next, the configuration of the performance control board 300 will be explained. Figure 5 is a block diagram showing the configuration of the performance control board. Figure 51 is a block diagram showing the configuration of the sound circuit. The performance control board 300 controls the performances (display performances, sound performances, lamp performances, movable body performances, etc.) based on control commands received from the main control board 200. As shown in Figure 5, the performance control board 300 is composed of a microcomputer (one-chip microcomputer) 301 and various external devices connected to the microcomputer 301. In this embodiment, various external devices include a control ROM 302, a CGROM (Character Generator Read Only Memory) 303, a DRAM (Dynamic Random Access Memory) 304, a digital amplifier 305, and the like.

[0069] (Control ROM 302) The control ROM 302 stores control programs for controlling the operation of the microcomputer 301, various data necessary for executing the control programs, various command lists set in the control registers of the sound circuit 323, and various operating parameters (frequency correction parameters, etc.) transmitted to the digital amplifier 305. In particular, the control ROM 302 stores (remembers) performance scenario data corresponding to each performance number, animation tables corresponding to each display performance number, command lists corresponding to each sound performance control number, various compression lamp drive data, and various compression motor drive data. "Compressed lamp drive data" is data obtained by compressing (encoding) lamp drive data in a predetermined format. "Lamp drive data" is data for driving various lamps 20 and 21 (data that specifies the brightness values ​​of lamps 20 and 21 belonging to each system). The "compressed motor drive data" is data obtained by compressing (encoding) motor drive data in a predetermined format. The "motor drive data" is data for driving various motors 23 (data that defines the output value of each motor 23). In this embodiment, a NOR-type flash memory (NOR-type ROM) is used as the control ROM 302. However, a configuration in which an EEPROM (Electrically Erasable Programmable Read Only Memory) is used as the control ROM 302 is also acceptable. The control ROM 302 is connected to the HOST interface 313 of the microcomputer 301.

[0070] (CGROM303) CGROM303 stores (remembers) various types of compressed image data, various types of compressed audio data, etc. "Compressed image data" is data obtained by compressing (encoding) image data (source data) in a predetermined format. "Image data (source data)" is image data (moving images and still images) that serves as the source material for drawing processing. "Compressed audio data" is data obtained by compressing (encoding) audio data in a predetermined format. "Audio data" is audio data output from various speakers 22. In this embodiment, NAND flash memory (NAND ROM) is used as CGROM303. Specifically, CGROM303 is composed of an SSD (Solid State Drive) that uses NAND flash memory as its storage unit. The CGROM303 is connected to the CG bus interface 314 of the microcomputer 301. The CG bus interface 314 is a SATA (Serial AT Attachment) standard connection interface. As a result, various data stored in the CGROM303 are read via SATA transfer.

[0071] (DRAM304) The DRAM 304 has a preload area. Various types of data stored in the CGROM 303 (specifically, compressed image data, compressed audio data, etc.) are transferred (preloaded) into the preload area. Furthermore, the DRAM 304 is provided with a drawing command buffer area. In this embodiment, a double buffering method is employed for the drawing command buffer area, and two drawing command buffer areas are provided in the DRAM 304. The two drawing command buffer areas are of the same size. While one of the two drawing command buffer areas is designated as the construction area, the other is designated as the transfer area. Furthermore, for each drawing command buffer area, the designation as the construction area and the designation as the transfer area are switched alternately every frame. Then, for each drawing command buffer area, during the period specified in the construction area, the display list described later is stored (generated / constructed) in that drawing command buffer area, and during the period specified in the transfer area, the display list stored in that drawing command buffer area is transferred to the VDP (specifically, the preloader circuit 319). DRAM 304 is connected to the DRAM interface 315 of the microcomputer 301.

[0072] (Microcomputer 301) The 301 microcomputer is an LSI (Large-Scale Integrated Circuit) that integrates a CPU core, registers, semiconductor memory, and other components. The microcomputer 301 controls the performance operations of various performance devices based on control commands received from the main control board 200. "Various performance means" include various image display devices 31, 32, various speakers 22, various lamps 20, 21, and various motors 23 (various movable parts). Therefore, "performance operations by various performance means" include the display of performance images by the various image display devices 31, 32, the output of sound by the various speakers 22, the driving (lighting) of the various lamps 20, 21, the driving of the various motors 23 (various movable parts), etc. The microcomputer 301 includes internal devices such as a CPU 310, CPU work memory 311, CPU interface 312, host interface 313, CG bus interface 314, DRAM interface 315, VRAM 316, serial communication controller 317, transfer circuit 318, preloader circuit 319, display circuit 320, graphics decoder circuit 321, drawing circuit 322, and sound circuit 323, and these internal devices are connected to a data bus 324.

[0073] (CPU310) The CPU 310 is connected to the HOST interface 313 via the CPU interface 312. The main control board 200 is also connected to the HOST interface 313, and control commands from the main control board 200 are input to it. Furthermore, the data bus 324 is connected to the HOST interface 313. This allows the CPU 310 to receive control commands (subcommands) from the main control board 200 via the HOST interface 313. Furthermore, the CPU 310 can communicate with internal devices such as the serial communication controller 317, preloader circuit 319, display circuit 320, and sound circuit 323 via the HOST interface 313 and the data bus 324. Furthermore, the CPU 310 can read various data (control programs, control data, etc.) stored in the control ROM 302 via the HOST interface 313. Furthermore, the CPU 310 is capable of reading various data (compressed audio data) stored in the CGROM 303 via the HOST interface 313, data bus 324, and CG bus interface 314. Furthermore, the CPU 310 is capable of reading and writing data to the DRAM 304 via the HOST interface 313, the data bus 324, and the DRAM interface 315.

[0074] The CPU 310 performs various calculations necessary to control the performance operations of various performance means, as well as control processing of internal devices in accordance with these calculations. In this case, the CPU 310 uses the CPU work memory (RAM) 311 and DRAM 304 as work areas for various arithmetic processes, buffer areas for various arithmetic processing data, table data areas, buffer areas for various input and output data, etc. In other words, the CPU 310 selects an effect (effect number) to be executed based on the control command received from the main control board 200, and selects and sets the effect scenario data corresponding to the selected effect number. Furthermore, according to the selected and set effect scenario data, it sequentially generates command information (internal commands) to control various internal devices (VDP, sound circuit 323, lamp controller 317a, motor controller 317b, etc.).

[0075] Specifically, CPU310 sets the animation table in the animation table setting area according to the command information. Then, according to the set animation table, it generates a display list in the drawing command buffer area specified in the construction area. A "display list" is a collection of drawing commands for one frame. In other words, the display list contains a set of drawing commands for one frame, written in a predetermined order. Then, in the VDP, the processing based on each drawing command is executed in the order written in the display list, generating the drawing data for one frame. The "drawing command" is information that specifies the content of the drawing process (drawing control) to be executed by the VDP. In particular, the drawing command specifies the address of the memory area where the compressed image data used for drawing is stored (hereinafter referred to as the "image address"), the magnification (magnification / reduction) when drawing the image data, the coordinates (coordinates in the frame buffer area) when drawing the image data, and the transparency (transparency / transparency / transparency) when drawing the image data.

[0076] (Transfer circuit 318) The transfer circuit 318 performs the transfer of various types of data between internal devices. Specifically, the transfer circuit 318 transfers the display list stored in the drawing command buffer area designated as the transfer area to the preloader circuit 319. The transfer circuit 318 then transfers the display list, which has been rewritten by the preloader circuit 319, to the drawing circuit 322.

[0077] (VRAM316) The VRAM 316 is provided with an image unpacking area. Image data (source data) unpacked (restored / decoded) by the graphics decoder circuit 321 is temporarily stored in this image unpacking area. Furthermore, the VRAM316 is provided with a frame buffer area. In this embodiment, a double buffering method is employed for the frame buffer area, and two frame buffer areas are provided in the VRAM316. The two frame buffer areas are of the same size. While one frame buffer area is designated as the drawing area, the other frame buffer area is designated as the output area. Furthermore, for each frame buffer area, the designation alternates between being the drawing area and the output area for each frame. Then, for each frame buffer area, during the period specified as the drawing area, drawing data for one frame is stored (generated and drawn) in that frame buffer area, and during the period specified as the output area, the output of the video signal is performed based on the drawing data for one frame stored in that frame buffer area.

[0078] (VDP) In the microcomputer 301, the preloader circuit 319, display circuit 320, graphics decoder circuit 321, drawing circuit 322, etc., function as a VDP (Video Display Processor). The VDP controls the display of animation images by various image display devices 31 and 32. Specifically, the VDP generates drawing data in response to receiving a display list (drawing command) from the CPU 310, generates a video signal based on the generated drawing data, and outputs the generated video signal to the various image display devices 31 and 32. The preloader circuit 319 can read various data (compressed image data) stored in the CGROM 303 via the CG bus interface 314. In particular, the preloader circuit 319 transfers (preloads) the compressed image data stored in the CGROM 303 to the preload area of ​​the DRAM 304 before the drawing process by the drawing circuit 322 is executed. In other words, NAND flash memory such as CGROM303 is easier to increase in capacity compared to NOR flash memory such as control ROM302, but its data read speed is slow. Therefore, if the compressed image data is read directly from CGROM303 (NAND flash memory) when the drawing process is executed by the drawing circuit 322, there is a risk that the processing performance will be significantly reduced. Therefore, in the pachinko machine 1, before the drawing process is executed, the compressed image data stored in the CGROM 303 is transferred in advance to the DRAM 304, which is a storage means with a faster data read speed compared to the CGROM 303. Then, when the drawing process is executed, the compressed image data is read from the DRAM 304, thereby preventing a decrease in processing performance.

[0079] Specifically, each time the preloader circuit 319 receives a display list, it transfers (preloads) one frame of compressed image data specified in the display list from the compressed image data stored in the CGROM 303 to the preload area of ​​the DRAM 304. At this time, the preloader circuit 319 rewrites the display list. In other words, the display list generated by the CPU 310 contains an address that specifies the memory area of ​​the CGROM 303 as the image address included in each drawing command. The preloader circuit 319 then transfers the compressed image data stored in the memory area (the memory area of ​​the CGROM 303) specified by the image address included in each drawing command included in the display list to a predetermined area of ​​the DRAM 304, and then rewrites the image address included in the drawing command to an address that specifies the memory area after the transfer (the predetermined area of ​​the DRAM 304). This generates a new display list with the image addresses rewritten. In this embodiment, the preloader circuit 319 is configured to transfer (preload) the compressed image data stored in the CGROM 303 to the preload area of ​​the DRAM 304. However, the preloader circuit 319 may also be configured to transfer the compressed image data stored in the CGROM 303 to a predetermined area (preload area) of the VRAM 316. The display list, rewritten by the preloader circuit 319, is transferred to the drawing circuit 320 by the transfer circuit 318.

[0080] The drawing circuit 322 stores (generates and draws) drawing data for one frame in the frame buffer area designated as the drawing area, according to the display list received from the preloader circuit 319. Specifically, each time the drawing circuit 320 receives a display list, it reads compressed image data for one frame specified in the display list from the DRAM 304. The compressed image data for one frame read from the DRAM 304 is restored (decoded) by the graphics decoder circuit 321 and stored (decompressed) in the image decompression area of ​​the VRAM 316. Then, the drawing circuit 320 uses the image data stored in the image decompression area to generate drawing data for one frame in the frame buffer area specified as the drawing area.

[0081] The display circuit 320 generates a video signal based on drawing data for one frame stored (generated and drawn) in the frame buffer area designated as the output area, and outputs the generated video signal to various image display devices 31 and 32. In this embodiment, a digital RGB signal is output as the video signal. However, it is also acceptable to configure the system to output an LVDS (Low Voltage Differential Signaling) signal as the video signal. Specifically, the display circuit 320 is composed of a data acquisition circuit (not shown), a scaler circuit (not shown), a color correction circuit (not shown), a ditherer circuit (not shown), a synchronization signal generation circuit (not shown), and the like. The data acquisition circuit reads the drawing data stored in the frame buffer area designated as the output area. The scaler circuit can perform scaling (enlargement and reduction) on the drawing data read out by the data acquisition circuit. The color correction circuit can apply color correction processing to the drawing data after it has been processed by the scaler circuit. The dithering circuit can apply dithering processing to the drawing data after it has been processed by the color correction circuit. The resulting image data, processed by the dithering circuit, is then output as a video signal (digital RGB signal). The synchronization signal generation circuit generates a horizontal synchronization signal and a vertical synchronization signal (Vsync). The synchronization signal generation circuit then outputs the generated horizontal and vertical synchronization signals to various image display devices 31 and 32. The synchronization signal generation circuit also outputs the generated vertical synchronization signal to the CPU 310. In this embodiment, the display of the animation image on each image display device 31, 32 (the display of the animation image based on drawing data for one frame) is updated every 16.66 ms. Therefore, the synchronization signal generation circuit outputs a vertical synchronization signal to the CPU 310 (at a high level) every 16.66 ms.

[0082] (Serial communication controller 317) The serial communication controller 317 is comprised of a lamp controller 317a and a motor controller 317b. The lamp controller 317a controls the driving (light emission) of the various lamps 20 and 21. Specifically, the CPU 310 sets the LED register according to the command information (message) set in the lamp command buffer area, which will be described later. Then, the lamp controller 317a generates lamp drive data according to the setting of the LED register and outputs the generated lamp drive data along with the clock signal to the lamp drivers 332 and 342. At this time, the lamp drive data is output as serial data. The lamp controller 317a includes a lamp decoder circuit (not shown). The lamp decoder circuit reads the compressed lamp drive data specified in the command information from the control ROM 302. It also restores (decodes) the read compressed lamp drive data. Based on the restored lamp drive data, it generates lamp drive data and outputs the generated lamp drive data to the lamp drivers 332 and 342.

[0083] The motor controller 317b controls the drive of various motors 23 (various movable parts). Specifically, the CPU 310 sets the motor register according to the command information (messages) set in the movable body command buffer area, which will be described later. Then, the motor controller 317b generates motor drive data according to the settings of the motor register and outputs the generated motor drive data along with the clock signal to the motor drivers 333 and 343. At this time, the motor drive data is output as serial data. The motor controller 317b includes a motor sequencer circuit (not shown). The motor sequencer circuit reads the compressed motor drive data specified in the command information from the control ROM 302. It also restores (decodes) the read compressed motor drive data. Based on the restored motor drive data, it generates motor drive data and outputs the generated motor drive data to the motor drivers 333 and 343. Furthermore, the motor controller 317b receives information from the driver board 330 indicating the detection status of various sensors 24, as well as information from the sub-connection board 340 indicating the detection status of each switch 25-29 and the detection status of various sensors 24.

[0084] (Sound circuit 323) The sound circuit 323 (built-in sound source) controls the output (playback) of sound (performance sounds) from the various speakers 22. As shown in Figure 51, the sound circuit 323 is composed of 40 tracks (tracks 1 to 40), 8 audio buses (audio bus 1 to audio bus 8), 8 channels (channels 1 to channel 8), and control registers (not shown). In this embodiment, the various speakers 22 include a left upper speaker, a right upper speaker, a left middle speaker, a right middle speaker, a bottom speaker, and a woofer. Each channel is connected (electrically connected) to one speaker via a digital amplifier 305. Specifically, the top left speaker is connected to channel 1, the top right speaker to channel 2, the middle left speaker to channel 3, the middle right speaker to channel 4, the bottom speaker to channel 5, and the woofer to channel 6. On the other hand, no speakers are connected to channels 7 and 8. Here, the upper left speaker, upper right speaker, left center speaker, and right center speaker are configured as high-frequency / mid-frequency speakers (full-range speakers). On the other hand, the lower speaker and woofer are configured as low-frequency speakers. The woofer has a lower output frequency range (its frequency response lies in the lower frequency range) and a higher output (W) compared to the lower speaker. The sound circuit 323 is equipped with an independent sequencer (not shown) for each track. This makes it possible to independently control playback, stopping, volume, etc., of audio data for each track. Each track is equipped with a compressed audio decoder 351, a track volume control unit 352, a programmable pan 353, and the like. The compressed audio decoder 351 restores (decodes) the compressed audio data. The track volume control unit 352 sets the volume of the track. The programmable pan 353 controls the sound localization by outputting the track's audio data to any audio bus.

[0085] The 8 audio buses are equipped with a switcher 354, a ducking control unit 355, a first channel volume control unit 356, and the like. The switcher 354 assigns audio data from eight audio buses and audio data from eight external serial inputs (not shown) to the eight audio buses. In this embodiment, the eight external serial inputs are not used. The ducking control unit 355 ducks (reduces) the volume of the other audio buses based on the volume of the audio data input from a predetermined audio bus among the eight audio buses. The first channel volume control unit 356 sets the association between each audio bus (audio bus 1 to audio bus 8) and each channel (channel 1 to channel 8).

[0086] In this embodiment, the first channel volume control unit 356 connects the audio bus 1 and channel 1. The audio signal generated by channel 1 is input to the upper left speaker. As a result, audio based on the audio data assigned to the audio bus 1 is output from the upper left speaker. Furthermore, the first channel volume control unit 356 connects the audio bus 2 and channel 2. The audio signal generated by channel 2 is input to the upper right speaker. As a result, audio based on the audio data assigned to the audio bus 2 is output from the upper right speaker. Furthermore, the first channel volume control unit 356 connects the audio bus 3 and channel 3. The audio signal generated by channel 3 is then input to the left-center speaker. As a result, audio based on the audio data assigned to the audio bus 3 is output from the left-center speaker. Furthermore, the first channel volume control unit 356 connects the audio bus 4 to channel 4. The audio signal generated by channel 4 is then input to the right-center speaker. As a result, audio based on the audio data assigned to the audio bus 4 is output from the right-center speaker. Furthermore, the first channel volume control unit 356 connects the audio bus 5 to channel 5. The audio signal generated by channel 5 is then input to the lower speaker. As a result, audio based on the audio data assigned to the audio bus 5 is output by the lower speaker. Furthermore, the first channel volume control unit 356 connects the audio bus 6 to channel 6. The audio signal generated by channel 6 is then input to the woofer. As a result, the woofer outputs audio based on the audio data assigned to the audio bus 6. Furthermore, the first channel volume control unit 356 connects the audio bus 7 and channel 6. As a result, audio based on the audio data assigned to the audio bus 7 is output by the woofer. On the other hand, the audio bus 8 is not connected to any channel by the first channel volume control unit 356. As described above, in this embodiment, channels 7 and 8 are unused, and no audio data is input to them.

[0087] The eight channels are configured to include a second channel volume control unit 357, an equalizer 358, a limiter 359, a post-effects processor 360, an overall volume control unit 361, an audio serial output 362, and the like. The second channel volume control unit 357 sets the volume for each channel. The equalizer 358 sets the emphasis or reduction of a specific frequency band for each channel (corrects the frequency). In this embodiment, the equalizer 358 is not used. The limiter 359 prevents clipping by compressing sounds that exceed the threshold for each channel. The post-effector 360 sets the emphasis or reduction of a specific frequency band, volume, timing delay of sound, etc. for each channel. The overall volume control unit 361 sets the volume for all channels at once. The audio serial output 362 converts the audio data of each channel for serial transmission to the digital amplifier 305.

[0088] The CPU 310 reads the command list from the control ROM 302 according to the command information and sets it in the control register of the sound circuit 323. As a result, the sound circuit 323 operates according to the command list set in the control register. The "command list" contains information that specifies the operation of the sound circuit 323. As described above, a command list corresponding to each sound effect control number is stored. In this embodiment, the command list includes a command list for specifying the start of sound effects, a command list for specifying volume adjustment, a command list for specifying the end of sound effects, and so on. The command list for specifying the start of sound effects includes information such as specifying the compressed audio data to start playback, specifying the track to which the compressed audio data will be assigned, specifying the number of times the compressed audio data will be played, specifying the volume of the compressed audio data, specifying the pan-pot ratio of the compressed audio data, and specifying the preset data to be set for the track (preset number). The "pan-pot ratio" is information that specifies the audio bus (audio bus 1 to audio bus 8) to which audio data is assigned. In other words, the pan-pot ratio is information that specifies the volume of each audio bus when assigning audio data to each audio bus. In this embodiment, the pan-pot ratio is used to specify the volume balance of the eight audio buses (audio bus 1 to audio bus 8). Specifically, the pan-pot ratio specifies the volume ratio of audio bus 1 to audio bus 8. On the other hand, the command list for specifying volume adjustments includes information such as which track's volume to adjust and information specifying the adjustment details. On the other hand, the command list for specifying the end of sound effects includes information such as specifying the track to stop playback. As described above, in this embodiment, playback, stopping, volume adjustment, etc., of audio data are controlled for each track.

[0089] (Sound circuit reset process) Next, we will explain the sound circuit reset process. The sound circuit 323 is provided with a first status information setting register where the first status information is set. Here, the "first status information" is information indicating the state of the sound circuit 323 (whether it is in a minor abnormal state, a severe abnormal state, or a normal state). Furthermore, in the sound circuit 323, if there is an abnormality in the compressed audio data read from the CGROM 303, the playback of the compressed audio data is stopped, resulting in an abnormal state. In particular, the sound circuit 323 is capable of individually detecting (detecting) two types of abnormal states, depending on the degree of abnormality in the read compressed audio data: a minor abnormal state (an abnormal state in which playback is stopped only for the track to which the compressed audio data is assigned) and a severe abnormal state (an abnormal state in which playback is stopped not only for the track to which the compressed audio data is assigned, but for all tracks). When no abnormal state (minor or severe abnormal state) is detected, the first status information setting register is set to a value corresponding to the normal state (specifically, "0"). When a minor abnormal state is detected, the first status information setting register is set to a value corresponding to the minor abnormal state (specifically, "1"). When a severe abnormal state is detected, the first status information setting register is set to a value corresponding to the severe abnormal state (specifically, "2").

[0090] Furthermore, in the first status information acquisition process (step S28-5), the CPU 310 acquires the first status information set in the first status information setting register of the sound circuit 323. If the CPU 310 determines that the acquired first status information corresponds to a value corresponding to a severe abnormal state (specifically, "2"), it executes the sound circuit reset process (step S28-7), which will be described later. In the case of minor abnormal conditions, when a new sound effect is initiated, a different compressed audio data than the one causing the abnormality is assigned to the track, thereby resolving the minor abnormal condition. Upon resolution of the minor abnormal condition, the value corresponding to the normal state (specifically, "0") is set in the first status information setting register. Therefore, in this embodiment, if the acquired first status information is determined to be a value corresponding to a minor abnormal condition (specifically, "1"), the sound circuit reset process is not executed. During the sound circuit reset process, a reset signal is sent to the sound circuit 323 (the signal input to the reset terminal is turned ON). Upon receiving the reset signal, the sound circuit 323 initializes various registers. Then, upon completion of initialization (resolution of a severe abnormal state), the first status information setting register is set to a value corresponding to the normal state (specifically, "0").

[0091] (Configuration of Digital Amplifier 305) Next, I will explain the configuration of the digital amplifier 305. The digital amplifier 305 converts and amplifies the audio data (digital signal) input from the sound circuit 323 into an analog signal and outputs it to the various speakers 22 (upper left speaker, upper right speaker, left center speaker, right center speaker, and woofer). At this time, the digital amplifier 305 performs frequency correction, volume correction, etc. for each channel (channels 1 to 8). In particular, the digital amplifier 305 has a built-in DSP (Digital Signal Processor). The digital amplifier 305 receives frequency correction parameters from the CPU 310, allowing for settings such as a 10-band PEQ (Parametric Equalizer), a 3-band DRC (Dynamic Range Controller), a crossover filter, and a bass boost function for each channel (channels 1 to 8).

[0092] Specifically, the digital amplifier 305 is composed of four CPU cores (Core 1 to Core 4). Core 1 performs frequency correction, volume correction, etc. on the audio data for channels 1 and 2 (upper left speaker and upper right speaker). Core 2 performs frequency correction, volume correction, etc. on the audio data for channels 3 and 4 (middle left speaker and middle right speaker). Core 3 performs frequency correction, volume correction, etc. on the audio data for channel 5 (woofer). Core 4 is unused. Furthermore, the digital amplifier 305 is provided with a frequency correction parameter setting register where frequency correction parameters are set (stored). The digital amplifier 305 then performs frequency correction on the audio data of each channel (channels 1 to 8) according to the frequency correction parameters set in the frequency correction parameter setting register.

[0093] (Digital amplifier initialization process) Next, we will explain the digital amplifier initialization process. The DRAM 304 is provided with an initialization information setting area where initialization information is set. Here, "initialization information" is information indicating the state of the digital amplifier 305 (whether it is in the initialization state or the normal state (non-initialized state)). Here, "initialization state" refers to the state during initialization when the power is turned on. Then, in response to power being turned on to the pachinko machine 1, the CPU 310 sets a value corresponding to the initialization state (specifically, "1") in the initialization information setting area and sends a reset signal to the digital amplifier 305 (turning on the signal input to the reset terminal). When the digital amplifier 305 receives a reset signal, it initializes various registers. Specifically, it initializes (clears) the frequency correction parameter setting register, the volume setting (correction) register, the terminal setting register, the second status information setting register, etc. In particular, when the digital amplifier 305 receives a reset signal, it sets the volume setting register to an initial value that specifies the mute state. As a result, when the digital amplifier 305 receives a reset signal, it enters a mute state (silent state / mute state). The "mute state" is a state in which the output of audio data (analog signals) to the various speakers 22 is restricted. Specifically, the mute state is a state in which it is difficult for the player to recognize (perceive) the sound output from the various speakers 22, regardless of whether sound is actually being output from the various speakers 22 or not. In this embodiment, when the digital amplifier 305 is in the mute state, the output of audio data (analog signals) to the various speakers 22 is stopped, and the sound output from the various speakers 22 is stopped. Then, upon completion of the initialization of the digital amplifier 305, the CPU 310 sets a value corresponding to the normal state (non-initialized state) (specifically, "0") in the initialization information setting area.

[0094] (Digital Amplifier Processing) Next, I will explain digital amp presetting. The digital amplifier 305 is provided with a second status information setting register where the second status information is set. Here, the "second status information" is information indicating the state of the digital amplifier 305 (whether it is in an abnormal state or a normal state). Furthermore, the digital amplifier 305 is capable of detecting the occurrence of various abnormal conditions, such as overcurrent, overvoltage, high temperature, communication errors, and a state where the duty cycle (τ) is maintained at an abnormal level. When no abnormal conditions are detected, the second status information setting register is set to a value corresponding to the normal state (specifically, "0"). In response to the detection of various abnormal conditions, the second status information setting register is set to a value corresponding to the abnormal state (specifically, "1"). Furthermore, in the second status information acquisition process (step S28-8) described later, the CPU 310 acquires the second status information set in the second status information setting register of the digital amplifier 305. If the acquired second status information is determined to be a value corresponding to an abnormal state (specifically, "1"), the CPU 310 executes the digital amp reset process (step S28-10) described later. During the digital amp reset process, a reset signal is sent to the digital amplifier 305 (the signal input to the reset terminal is turned ON). Upon receiving the reset signal, the digital amplifier 305 initializes various registers. Specifically, it initializes (clears) the frequency correction parameter setting register, the volume setting (correction) register, the terminal setting register, the status information setting register, etc. Then, upon completion of initialization (resolution of the abnormal state), it sets the second status information setting register to a value corresponding to the normal state (specifically, "0"). In particular, upon receiving the reset signal, the digital amplifier 305 sets the volume setting register to an initial value that specifies the mute state. As a result, upon receiving the reset signal, the digital amplifier 305 enters a mute state (silent state / mute state).

[0095] (Method for controlling the effects using the effects control board 300) Next, the method for controlling the performance using the performance control board 300 will be explained. The CPU 310 selects an animation (animation number) to execute in response to a control command received from the main control board 200. Then, it sets the animation scenario data corresponding to the selected animation number and the animation scenario timer corresponding to that animation scenario data in the animation scenario setting area of ​​the DRAM 304. "Direction scenario data" is information that defines the progress of the direction. Specifically, direction scenario data contains multiple process data registered in chronological order. In other words, direction scenario data contains multiple process data and information that specifies the start time (start timing) of the processing based on each process data. Each process data contains one or more command information. For example, command information may include command information specifying the start of a sub-effect (display effect, sound effect, lamp effect, or movable body effect), command information specifying the end of a sub-effect (display effect, sound effect, lamp effect, or movable body effect) (hereinafter referred to as "effect end command").

[0096] Furthermore, the CPU 310 controls the progress of the performance based on the performance scenario data set in the performance scenario setting area. Specifically, the CPU 310 updates the performance scenario timer set in the performance scenario setting area at predetermined intervals, and, based on the updated performance scenario timer value, determines whether or not there is any process data registered in the performance scenario data set in the performance scenario setting area whose start time has arrived. If it is determined that there is any process data whose start time has arrived, the CPU 310 stores (saves) each command information contained in that process data in the corresponding buffer area. In this case, command information related to display effects (command information specifying the start of a display effect, command information specifying the end of a display effect, etc.) is stored in the display command buffer area. Meanwhile, command information related to sound effects (command information specifying various sound effect control numbers) is stored in the sound command buffer area. Meanwhile, command information related to lamp effects (command information specifying the start of a lamp effect, command information specifying the end of a lamp effect, etc.) is stored in the lamp command buffer area. Meanwhile, command information related to movable body effects (command information specifying the start of a movable body effect, command information specifying the end of a movable body effect, etc.) is stored in the movable body command buffer area.

[0097] (Method for controlling display effects) Next, the method for controlling the display effects (display) using the performance control board 300 will be explained. The control ROM 302 stores animation tables corresponding to each display effect (each display effect number). Furthermore, each animation table corresponding to a display effect is associated with display priority information corresponding to that display effect (the images that make up that display effect). "Display priority information" is information that specifies the display priority. "Display priority" is information that specifies the priority order for display (rendering). Furthermore, when multiple display effects (displays) are executed at overlapping times, the display on the display screen 31a (the display image shown on the display screen 31a) is constructed based on the multiple display effects (images related to the multiple display effects). In this case, among the multiple display effects (multiple images) that constitute the display (the display image), the display effect (image) with a higher display priority is displayed preferentially over the display effect (image) with a lower display priority. In other words, with respect to the multiple display effects (multiple images) that constitute the display image, the display effect (image) with a higher display priority is displayed preferentially.

[0098] In other words, among the multiple display effects (multiple images) that make up the performance image, the display effects (images) with higher display priority are displayed closer to the player than the display effects (images) with lower display priority. That is, among the multiple display effects (multiple images) that make up the performance image, the display effects (images) with higher display priority are displayed closer to the player. As a result, if there is an overlap between a display effect (image) with a higher display priority and a display effect (image) with a lower display priority among the multiple display effects (multiple images) that make up the said effect image, the display effect (image) with the higher display priority will be displayed preferentially for the overlapping portion.

[0099] The CPU 310 (display control unit) determines at a predetermined period (16.5 [ms]) whether or not command information is stored in the display command buffer area. If it determines that command information is stored in the display command buffer area, it analyzes each command information stored in the display command buffer area and executes processing according to the analysis results. In this case, if the display command buffer area contains command information specifying the start of a display effect, the animation table corresponding to the display effect number specified by the command information is read from the animation tables stored in the control ROM 302. Then, the read animation table is set (stored / registered) in the animation table setting area of ​​the DRAM 304. This copies the animation table stored in the control ROM 302 to the animation table setting area. It is possible to set multiple animation tables in the animation table setting area.

[0100] The "animation table" contains information (various parameters for controlling the display of images) that defines the progress of the display effects (display of effect images) by various image display devices 31 and 32. In other words, the animation table contains information that defines the movement of images. Specifically, the animation table contains a predetermined number of frame information entries arranged chronologically. The display animation progresses by sequentially displaying the images based on each frame information entry in the order they are registered in the animation table. Each frame information consists of various parameters for controlling (executing and configuring) the display of an image for one frame. Specifically, each frame information is composed of information that specifies the image data (compressed image data) to be used for drawing (image address information), information that specifies the display priority of the said image data (the said display effect) (display priority information), information that specifies the magnification (magnification / reduction) when drawing the said image data (hereinafter referred to as "display magnification information"), information that specifies the coordinates (coordinates in the frame buffer area) where the said image data is drawn (hereinafter referred to as "display coordinate information"), and information that specifies the transparency (transparency / transparency / transparency) when drawing the said image data (hereinafter referred to as "transparency information").

[0101] The CPU 310 then controls the display of the animation image corresponding to each frame based on one or more animation tables set in the animation table setting area. Specifically, CPU310 executes the command construction process described later at predetermined intervals. In the command construction process, first, the sub-scenario timers corresponding to each animation data set in the display scenario setting area are updated. Next, based on all the animation tables set in the animation table setting area, a display list is constructed in the drawing command buffer area specified in the construction area.

[0102] Specifically, for all animation tables set in the animation table settings area, the frame information registered in each animation table that has been selected as the target for constructing the display list is retrieved. Then, the display list is constructed based on all the retrieved frame information. As a result, the VDP is controlled according to the display list generated in the drawing command buffer area, and the display effects (display of effect images by the main image display device 31) are controlled. In other words, if an animation data is set in the display scenario setting area, a display list is constructed that specifies the drawing of the image data specified by that animation data. On the other hand, if multiple animation data sets are configured in the display scenario setting area, a display list is constructed that specifies that the rendering of the image data specified by those multiple animation data sets should be executed in a predetermined order. In this case, the order in which the image data corresponding to the display priority information is drawn is set based on the display priority specified in the display scenario setting area.

[0103] (Sound effects control method) Next, we will explain how to control sound effects using the performance control board 300. The CPU 310 (sound control unit) executes the command information analysis process (step S41-7), described later, at a predetermined cycle (33 ms) to determine whether or not command information is stored in the sound command buffer area. If it determines that command information is stored in the sound command buffer area, it analyzes each piece of command information stored in the sound command buffer area and executes processing according to the analysis results. Specifically, the command list (operation parameters) corresponding to the sound effect control number specified by the command information is read from the control ROM 302, and the read command list is set in the control register of the sound circuit 323. As a result, the sound circuit 323 operates according to the command list set in the control register. For example, if the analyzed command information is a command information that specifies the start of a sound effect, the command list corresponding to the sound effect control number specified by the command information (the command list that specifies the start of the sound effect) is read from the control ROM 302, and the read command list is set in the control register of the sound circuit 323. Here, the command list that specifies the start of a sound effect includes information that specifies the compressed audio data to start playback, information that specifies the track to which the compressed audio data is assigned, information that specifies the number of times the compressed audio data is played, information that specifies the volume of the compressed audio data (audio data), information that specifies the pan-pot ratio of the compressed audio data (audio data), and information that specifies the preset data to be set on the track (preset number), etc. As a result, the sound effect is started according to the command list set in the control register. On the other hand, if the analyzed command information is a command information that specifies volume adjustment, a command list (a command list that specifies volume adjustment) corresponding to the sound effect control number specified by the command information is set in the control register of the sound circuit 323. Here, the command list that specifies volume adjustment includes information that specifies the track to adjust the volume, information that specifies the content of the adjustment (volume), etc. As a result, the volume is adjusted according to the command list set in the control register. On the other hand, if the analyzed command information is a command information that specifies the end of the sound effect, a command list corresponding to the sound effect control number specified by the command information (a command list that specifies the end of the sound effect) is set in the control register of the sound circuit 323. Here, the command list that specifies the end of the sound effect includes information such as specifying the track to stop playback. As a result, the sound effect is terminated according to the command list set in the control register.

[0104] In particular, the CPU 310 is configured not to perform command information analysis processing if the sound circuit 323 is in a severely abnormal state. This prevents the sound circuit 323 from remaining in a severely abnormal state. On the other hand, the CPU 310 is configured to select whether or not to execute command information analysis processing depending on the state of the digital amplifier 305, when the sound circuit 323 is in a minor abnormal state or a normal state. In this case, if the digital amplifier 305 is in an initialization state (the state during initialization when the power is turned on), the command information analysis processing is not executed. On the other hand, if the digital amplifier 305 is in a normal state, the command information analysis processing is executed regardless of whether or not it is in an abnormal state. This suppresses the delay between sound effects and display effects. In other words, in this embodiment, the command information analysis process is executed at predetermined intervals (33 ms). This ensures that even if the command information analysis process is not executed during the period when the digital amplifier 305 is in an abnormal state, if the digital amplifier 305 recovers from the abnormal state within the predetermined interval (33 ms), the command information analysis process can be executed as scheduled without delay after the digital amplifier 305 recovers from the abnormal state, making it possible to execute sound effects without delay in response to display effects. However, in this embodiment, if the digital amplifier 305 enters an abnormal state, the recovery time (1.5 s in this embodiment) from the time the abnormal state is detected until the system returns to its initial state is longer than the predetermined time (33 ms). As a result, if the system is configured so that the command information analysis process is not executed while the digital amplifier 305 is in an abnormal state, the digital amplifier 305 may not be able to recover from the abnormal state within the predetermined time (33 ms). After the digital amplifier 305 recovers from the abnormal state, the command information analysis process will be executed with a delay, resulting in a delay between the sound effects and the display effects. Therefore, in this embodiment, as long as the sound circuit 323 is not in a severely abnormal state, and the digital amplifier 305 is not in an initialization state, the command information analysis process is executed even if the digital amplifier 305 is in an abnormal state. As a result, the command information analysis process is executed even during the period when the digital amplifier 305 is in an abnormal state. Consequently, a delay in the execution of the command information analysis process after the digital amplifier 305 recovers from the abnormal state is prevented, and sound effects can be executed without delay in response to display effects.

[0105] Specifically, if the sound circuit 323 is in a minor abnormal state or a normal state, the command information analysis process will be executed (continued) even if the digital amplifier 305 is in an abnormal state, as long as the digital amplifier 305 is not in an initialization state. As a result, if the sound circuit 323 is in a minor abnormal state or a normal state, even if the digital amplifier 305 is in an abnormal state, the sound circuit 323 will continue to play audio data, and the audio data (digital signal) played by the sound circuit 323 will continue to be input to the digital amplifier 305. In this case, as described above, if the digital amplifier 305 is in an abnormal state, a mute state will be set in the digital amplifier 305, so even if audio data (digital signal) is input to the digital amplifier 305, the output of audio data (analog signal) to the various speakers 22 based on the input audio data (digital signal) will be limited (stopped). This makes it possible to reduce the processing load on the CPU 310 while preventing the player from feeling uncomfortable.

[0106] (How to control the lamp effects) Next, the method for controlling the lamp effects using the effect control board 300 will be explained. The CPU 310 periodically determines whether or not command information is stored in the lamp command buffer area. If it determines that command information is stored in the lamp command buffer area, it analyzes each command information stored in the lamp command buffer area and executes processing according to the analysis results. In this case, if command information specifying the start of a lamp effect is stored in the lamp command buffer area, the compressed lamp drive data corresponding to the lamp effect number specified by the command information is read, and the read compressed lamp drive data is set in the lamp register. As a result, the lamp controller 317a controls the lamp effect (driving (lighting) of various lamps 20, 21) according to the compressed lamp drive data set in the lamp register.

[0107] (Control method for movable body effects) Next, the method for controlling the movable body effects using the performance control board 300 will be explained. The CPU 310 determines at predetermined intervals whether or not command information is stored in the movable body command buffer area. If it determines that command information is stored in the movable body command buffer area, it analyzes each piece of command information stored in the movable body command buffer area and executes processing according to the analysis results. In this case, if command information specifying the start of a movable body performance is stored in the movable body command buffer area, the compressed motor drive data specified by the command information is read, and the read compressed motor drive data is set in the motor register. As a result, the motor controller 317b controls the movable body performance (driving various motors 23 (various movable bodies)) according to the compressed motor drive data set in the motor register.

[0108] (Configuration of driver board 330) The driver board 330 includes a parallel-to-serial conversion circuit 331, a lamp driver 332, and a motor driver 333. The lamp driver 332 controls the driving (light emission) of each light-emitting group that makes up the panel lamp 21 in accordance with the lamp drive data input from the lamp controller 317a. In this process, the lamp drive data specifies a brightness value corresponding to each system that makes up the panel lamp 21. Then, an excitation signal (drive current) corresponding to the brightness value specified in the lamp drive data is supplied to each system that makes up the panel lamp 21. This controls the driving (light emission) of the light-emitting group that makes up each system. The motor driver 333 controls the output of excitation signals (drive currents) to the various motors 23 (motors 23 constituting various movable units) installed in the game board unit 10, in accordance with the motor drive data input from the motor controller 317b. In this process, the motor drive data specifies the output value of each motor 23 installed in the game board unit 10. Then, an excitation signal (drive current) corresponding to the output value specified in the motor drive data is supplied to each motor 23. This controls the drive of each motor 23. The parallel-to-serial conversion circuit 331 receives detection signals from various sensors 24. The parallel-to-serial conversion circuit 331 then converts the detection signals from the various sensors 24 into serial data and outputs it to the serial communication controller 317.

[0109] (Configuration of sub-connection board 340) The sub-connection board 340 includes a parallel-to-serial conversion circuit 341, a lamp driver 342, and a motor driver 343. The lamp driver 342 controls the driving (light emission) of each light-emitting element group that constitutes the frame lamp 20 in accordance with the lamp drive data input from the lamp controller 317a. In this process, the lamp drive data specifies a brightness value corresponding to each system that makes up the frame lamp 20. Then, an excitation signal (drive current) corresponding to the brightness value specified in the lamp drive data is supplied to each system that makes up the frame lamp 20. This controls the driving (light emission) of the light-emitting elements that make up each system. The motor driver 343 controls the output of excitation signals (drive currents) to the various motors 23 (motors 23 constituting various movable unit components) installed in the integrated door unit 4, in accordance with the motor drive data input from the motor controller 317b. In this process, the motor drive data specifies the output values ​​of each motor 23 installed in the integrated door unit 4. Then, an excitation signal (drive current) corresponding to the output value specified in the motor drive data is supplied to each motor 23. This controls the drive of each motor 23. The parallel-to-serial conversion circuit 341 receives detection signals from various sensors 24 and detection signals from various switches 25-29. The parallel-to-serial conversion circuit 341 then converts the detection signals from the various sensors 24 and the detection signals from the various switches 25-29 into serial data and outputs it to the serial communication controller 317.

[0110] (Regarding the status of the gaming machine) In Pachinko Machine 1, six game machine states are defined (specifically, playable state, setting change state, setting confirmation state, setting abnormal state, RAM abnormal state, and backup abnormal state). The RAM 230 of the main control board 200 is provided with a game machine state flag area. The game machine state flag area stores (sets) values ​​corresponding to one of six game machine states (specifically, playable state, setting change state, setting confirmation state, setting error state, RAM error state, and backup error state) as game machine state flags. Then, in the pachinko machine 1, a game machine state corresponding to the value stored in the game machine state flag area is generated.

[0111] "Game-ready state" means the game machine is in a state where gameplay can proceed. While the game-playable state is established, the execution of steps S4-9 to S4-18, described later, is permitted. This allows the game (regular game and special game) to proceed. Furthermore, while the game is playable, the base ratio is displayed on the performance display device 206. In addition, information related to the game is displayed on the main display device 60.

[0112] The "settings change state" is a state in the gaming machine where it is possible to change the settings stored in the setting value area of ​​RAM230. The setting change state occurs when the setting change conditions are met. In this embodiment, the setting change conditions are met when, at power-on, a detection signal is input from the inner frame release sensor 108, a detection signal is input from the setting key switch 208, and a detection signal is input from the RAM clear switch 207. That is, when, at power-on, the inner frame unit 3 is open, the key switch 208 is rotated to the ON position, and the RAM clear switch 207 is pressed, the setting change state occurs. While the settings change state is active, the execution of the processes described in steps S4-9 to S4-18 is prohibited. As a result, the game (specifically, normal gameplay and special gameplay) is stopped. Furthermore, while the setting change state is active, the performance display device 206 displays the setting value stored in the setting value area. Also, all the lighting elements constituting the main display device 60 are turned off. In addition, security information (external information) is output to an external device. Furthermore, while the setting change state is active, the setting value stored in the setting value area can be changed by pressing the RAM clear switch 207. Then, while the setting change state is active, if the key switch 208 is rotated to the OFF position, the game-ready state is activated instead of the setting change state. This confirms the setting value stored in the setting value area.

[0113] The "settings confirmation state" is a gaming machine state in which the settings stored in the setting value area of ​​RAM230 can be checked. The setting confirmation state occurs when the setting confirmation conditions are met. In this embodiment, the setting confirmation conditions are met when, at power-on, a detection signal is received from the inner frame release sensor 108, a detection signal is received from the setting key switch 208, and no detection signal is received from the RAM clear switch 207. That is, at power-on, the setting confirmation state occurs when the inner frame unit 3 is open, the key switch 208 is rotated to the ON position, and the RAM clear switch 207 is not pressed. While the settings confirmation state is active, the execution of steps S4-9 to S4-18 described later is prohibited. As a result, gameplay (specifically, normal gameplay and special gameplay) is stopped. Furthermore, while the setting confirmation state is active, the performance display device 206 displays the setting value stored in the setting value area. This makes it possible to confirm the setting value stored in the setting value area. In addition, all the lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. Furthermore, while the settings confirmation state is active, it is not possible to change the settings stored in the settings value area. Then, if the key switch 208 is rotated to the OFF position while the settings confirmation state is active, the game-ready state is activated instead of the settings confirmation state.

[0114] "Setting Abnormal State" indicates that the gaming machine is in a state where a setting abnormality has occurred. The setting error state occurs when, while the game is playable, it is determined that the setting value set in the setting value range is not within the specified range. While an abnormal setting state occurs, the execution of the processes described in steps S4-9 to S4-18 is prohibited. As a result, the game (specifically, normal gameplay and special gameplay) is stopped. Furthermore, while a setting error occurs, the performance display device 206 displays an error code indicating the occurrence of the setting error. In addition, all lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from a configuration error, it is necessary to shut off and then power on the system to create a configuration change state.

[0115] "RAM abnormal state" indicates that the gaming machine is in a state where a RAM abnormality has occurred. A RAM abnormality condition occurs when a read / write abnormality in RAM230 is detected during power-up. While a RAM abnormality occurs, the execution of the processes described in steps S4-9 to S4-18 is prohibited. As a result, gameplay (specifically, normal gameplay and special gameplay) is stopped. Furthermore, while a RAM abnormality occurs, the performance display device 206 displays an error code indicating the occurrence of a RAM abnormality. In addition, all the lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from a RAM abnormal state, it is necessary to perform a power cut-off and power-on operation to induce a configuration change state.

[0116] "Backup Anomaly State" indicates that a gaming machine is in a state where a backup anomaly has occurred. A backup error occurs when a backup error in RAM230 (specifically, an error in the backup flag or an error in the checksum) is detected at power-on. While a backup abnormality occurs, the execution of the processes described in steps S4-9 to S4-18 is prohibited. As a result, gameplay (specifically, normal gameplay and special gameplay) is stopped. Furthermore, while a backup failure occurs, the performance display device 206 displays an error code indicating the occurrence of a backup failure. In addition, all the lighting elements constituting the main display device 60 are turned off. Furthermore, security information (external information) is output to an external device. To recover from a backup failure, it is necessary to perform a power cut-off and power-on operation to induce a configuration change state.

[0117] (Regarding the settings) Next, we will explain the settings (setting information) that are set in pachinko machine 1. The "setting value" is information that specifies the probability of winning the special symbol lottery (first special symbol lottery and second special symbol lottery) (the probability of winning the jackpot game state). In this embodiment, the setting value is defined as a value from "0" to "5". The RAM 230 of the main control board 200 is provided with a set value area. In the set value area, one value from "0" to "5" is stored (set) as a set value. In the pachinko machine 1, the probability of winning the special symbol lottery is set to a probability corresponding to the value set in the set value area. In this embodiment, the winning probabilities for the special symbol lottery corresponding to each setting value are, in descending order of winning probability, as follows: the winning probability for setting value = "5", the winning probability for setting value = "4", the winning probability for setting value = "3", the winning probability for setting value = "2", the winning probability for setting value = "1", and the winning probability for setting value = "0" (high winning probability → low winning probability).

[0118] In particular, in pachinko machine 1, it is possible to change (select) the setting value stored in the setting value area while the setting change state is active. Here, the change of the setting value is performed by the administrator of pachinko machine 1 (such as an employee of the amusement facility where pachinko machine 1 is installed). In other words, as described above, a setting change state occurs when the inner frame unit 3 is open when the power is turned on, the key switch 208 is rotated to the ON position, and the RAM clear switch 207 is pressed. While the setting change state is active, the performance display device 206 displays the setting value stored in the setting value area. Furthermore, each time the RAM clear switch 207 is pressed, the setting value stored in the setting value area is changed. When the setting value in the setting value area is changed, the setting value displayed on the performance display device 206 is also changed accordingly. Then, if the key switch 208 is rotated to the OFF position while the setting change state is active, the game-ready state is activated instead of the setting change state. This confirms the setting value stored in the setting value area.

[0119] (Regarding the base ratio) In the pachinko machine 1, the CPU 210 calculates the base ratio (base value) while a playable state is in effect. In this embodiment, the base ratio is calculated only while a predetermined play state is in effect (specifically, while a low probability state for special symbols is in effect and while the time-saving control is stopped). While the game is playable, the calculated base ratio is displayed on the performance display device 206. The "base ratio" is information calculated based on the number of game balls launched into the game area 30 and the number of prize balls dispensed according to the number of game balls entering the predetermined entry points (in this embodiment, the first starting point 51, the second starting point 52, and other prize entry points 54-57). Specifically, the base ratio is the ratio (percentage) of the number of balls dispensed to the number of balls that go out. In this embodiment, the base ratio is calculated for each predetermined interval (period). A predetermined interval is defined as a period in which a predetermined number of out balls (60,000 balls in this embodiment) are detected (discharged). That is, each interval starts when the previous interval ends and ends when the number of out balls detected during the current interval reaches the predetermined number (60,000 balls). The CPU 210 calculates the base ratio in real time during each interval.

[0120] Furthermore, a predetermined time period may be defined as the predetermined interval. In other words, the CPU 210 may be configured to calculate the base ratio for each predetermined time period. "Number of out balls" refers to the number of out balls. "Out balls" refer to game balls that have been ejected from the game area 30. Specifically, out balls are game balls that have passed through the ejection path (game balls detected by the out switch 109). Furthermore, game balls ejected from the out port 58 may also be considered out balls. Specifically, the out switch 109 may be configured to detect only game balls ejected from the out port 58, and game balls detected by the out switch 109 may also be considered out balls. "Payout amount" refers to the total number of prize balls dispensed in accordance with the number of game balls that enter the first starting port 51, the second starting port 52, and other prize entry ports 54-57.

[0121] (Regarding various lotteries) Next, we will explain the various lottery processes performed in Pachinko Machine 1. In pachinko machine 1, a regular symbol lottery is performed when a game ball passes through the starting gate 41. If the regular symbol lottery is successful, a regular symbol win game state is created. In the regular symbol win game state, the regular electric mechanism 52a is displaced (opened) from a closed state to an open state, allowing game balls to enter the second starting opening 52. In this embodiment, one type of game state called "Normal Symbol Win" is set as the type of normal symbol win game state that occurs when a normal symbol lottery is won.

[0122] If a "regular symbol win" is achieved (winning the regular symbol lottery), the regular symbol display device is controlled to stop and display the regular symbols as "regular symbol win symbols". On the other hand, if the regular symbol lottery is unsuccessful, the regular symbol display device is controlled to stop and display the regular symbol as a "losing symbol". In Pachinko Machine 1, it is possible to implement a time-saving control as an auxiliary control that is advantageous to the player. During the execution of the time shortening control, the time for the variable display of the special symbol (hereinafter referred to as "variable time") is shortened compared to when the time shortening control is stopped. In the present embodiment, during the execution of the time shortening control, the winning probability of the normal symbol lottery is improved and the time for the variable display of the normal symbol is shortened compared to when the time shortening control is stopped. Also, during the execution of the time shortening control, the number of opening times of the normal electric accessory 52a increases and the opening time of the normal electric accessory 52a is extended in the gaming state per normal symbol compared to when the time shortening control is stopped.

[0123] When winning the "per normal symbol", the number of opening times of the normal electric accessory 52a is set to 1 [time] or 3 [times], and the opening time of the normal electric accessory 52a in each time is set to 0.5 [s] or 2.0 [s]. At this time, during the execution of the time shortening control, the number of opening times of the normal electric accessory 52a is set to 3 [times], and the opening time of the normal electric accessory 52a in each time is set to 2.0 [s]. On the other hand, when the time shortening control is stopped, the number of opening times of the normal electric accessory 52a is set to 1 [time], and the opening time of the normal electric accessory 52a in each time is set to 0.5 [s].

[0124] Also, in the pachinko machine 1, the first special symbol lottery is executed triggered by the entry of a game ball into the first start port 51, and the second special symbol lottery is executed triggered by the entry of a game ball into the second start port 52. Then, when winning the first special symbol lottery or the second special symbol lottery, a big win gaming state is generated. In the big win gaming state, a round game in which the special electric accessory 53a is displaced from the closed state to the open state is executed, and a state where the entry of a game ball into the big winning port 53 is possible is achieved. In the present embodiment, as the types of the big win gaming states generated when winning the first special symbol lottery, "big win 1" and "big win 2" are set, and as the types of the big win gaming states generated when winning the second special symbol lottery, "big win 3" to "big win 6" are set.

[0125] If a "Big Win 1" is achieved, the stop symbol (display mode) corresponding to the "Big Win 1 symbol" will be displayed in the Special Feature 1 display device. In addition, the stop symbol (display mode) corresponding to the "Probability Change symbol" will be displayed in the performance symbol display areas a1 to a4. Here, the "probability change symbols" are, for example, the first performance symbols z1 that are stopped and displayed at the lottery result display positions in the three first performance symbol display areas a1 to a3 are all "number symbols" that show the same odd number, such as "7,7,7", and the second performance symbol z2 that are stopped and displayed in the second performance symbol display area a4 shows a predetermined color. If a "Big Win 2" is achieved, the stop symbols (display mode) corresponding to the "Big Win 2 symbols" will be displayed in the Special Feature 1 display device. In addition, the stop symbols (display mode) corresponding to the "Normal symbols" will be displayed in the performance symbol display areas a1 to a4. Here, "normal symbols" refers to a display configuration in which, for example, the first performance symbols z1 stopped and displayed at the lottery result display positions in the three first performance symbol display areas a1 to a3 are all "number symbols" showing the same even number, such as "2,2,2", and the second performance symbol z2 stopped and displayed in the second performance symbol display area a4 shows a predetermined color.

[0126] If you win "Big Win 3," the stop symbols (display mode) corresponding to "Big Win 3" will be displayed on the Special Feature 2 display device. In addition, the stop symbols (display mode) corresponding to "Probability Change Symbols" will be displayed in the performance symbol display areas a1 to a4. If you win "Big Win 4," the stop symbols (display mode) corresponding to "Big Win 4" will be displayed on the Special Feature 2 display device. In addition, the stop symbols (display mode) corresponding to "Probability Change Symbols" will be displayed in the performance symbol display areas a1 to a4. If you win "Big Win 5," the stop symbols (display mode) corresponding to "Big Win 5" will be displayed on the special display device 2. In addition, the stop symbols (display mode) corresponding to "Hidden Symbols" will be displayed in the performance symbol display areas a1 to a4. Here, the "hidden symbols" are, for example, first-stage symbols z1 that are stopped and displayed at the lottery result display positions in the three first-stage symbol display areas a1 to a3, which are combinations with a predetermined regularity such as "1, 2, 3", and second-stage symbols z2 that are stopped and displayed in the second-stage symbol display area a4, which are displayed in a predetermined color. If you win "Big Win 6," the stop symbols (display mode) corresponding to "Big Win 6" will be displayed on the Special Feature 2 display device. In addition, the stop symbols (display mode) corresponding to "Hidden Symbols" will be displayed in the performance symbol display areas a1 to a4.

[0127] On the other hand, if the special symbol lottery is unsuccessful (i.e., a "loser"), the stop symbol (display mode) corresponding to the "loser symbol" will be displayed in the Special Symbol 1 display device or the Special Symbol 2 display device. In addition, the stop symbol (display mode) corresponding to the "loser symbol" will be displayed in the performance symbol display areas a1 to a4. Here, a "losing symbol" is defined as a first-generation symbol z1 that is stopped and displayed in one of the three first-generation symbol display areas a1 to a3, where the number shown by the "number symbol" stopped and displayed in at least one area is a different combination from the number shown by the "number symbol" stopped and displayed in the other areas, and the second-generation symbol z2 that is stopped and displayed in the second-generation symbol display area a4 shows a predetermined color.

[0128] If you win "Big Win 1" through "Big Win 6", a predetermined number of rounds of gameplay will be performed in the big win state. In this embodiment, if you win "Big Win 1," "Big Win 2," "Big Win 5," or "Big Win 6," the number of rounds of gameplay is set to 5. On the other hand, if you win "Big Win 3," the number of rounds of gameplay is set to 15. On the other hand, if you win "Big Win 4," the number of rounds of gameplay is set to 10. If a "Big Win 1" to "Big Win 6" is achieved, the maximum opening time of the special electric mechanism 53a in each round of play is set to a predetermined time (29.0 [s] in this embodiment). Each round of play ends when one of the following conditions is met: the maximum opening time set since the special electric mechanism 53a was opened has elapsed, or the number of game balls that have entered the big prize opening 53 in that round of play has reached a predetermined upper limit (10 [balls] in this embodiment).

[0129] Furthermore, in Pachinko Machine 1, the game states related to the probability of winning the special symbol lottery (first special symbol lottery and second special symbol lottery) are defined as "low special symbol probability state" and "high special symbol probability state". During the "Special Symbol Low Probability State," the probability of winning the special symbol lottery is set to the first probability (hereinafter referred to as "low probability"). During the "Special Symbol High Probability State," the probability of winning the special symbol lottery is set to a second probability (hereinafter referred to as "high probability") which is higher than the first probability. The main control board 200 sets the winning probabilities for each lottery so that the winning probabilities for the first special symbol lottery and the winning probabilities for the second special symbol lottery are synchronized. Here, the winning probability for the special symbol lottery refers to the probability of winning a "win" ("Big Win 1" to "Big Win 6") which results in a jackpot game state. In particular, in Pachinko Machine 1, the probability of winning the special symbol lottery is determined by a combination of the setting value set in the setting value range and the game state (low special symbol probability state or high special symbol probability state).

[0130] Specifically, when the setting value is "0" and the "Special Symbol Low Probability State" is active, the probability of winning the special symbol lottery (jackpot probability) is 1 / 319.69. On the other hand, when the setting value is "0" and the "Special Symbol High Probability State" is active, the probability of winning the special symbol lottery (jackpot probability) is 1 / 32.13. On the other hand, when the setting value is "1" and the "Special Symbol Low Probability State" is active, the probability of winning the special symbol lottery (jackpot probability) is 1 / 312.08. On the other hand, when the setting value is "1" and the "Special Symbol High Probability State" is active, the probability of winning the special symbol lottery (jackpot probability) is 1 / 31.36. On the other hand, when the setting value is "2" and the "Special Symbol Low Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 304.82. On the other hand, when the setting value is "2" and the "Special Symbol High Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 30.62.

[0131] On the other hand, when the setting value is "3" and the "Special Symbol Low Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 297.89. On the other hand, when the setting value is "3" and the "Special Symbol High Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 29.93. On the other hand, when the setting value is "4" and the "Special Symbol Low Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 291.27. On the other hand, when the setting value is "4" and the "Special Symbol High Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 29.26. On the other hand, when the setting value is "5" and the "Special Symbol Low Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 284.94. On the other hand, when the setting value is "5" and the "Special Symbol High Probability State" occurs, the probability of winning the special symbol lottery (jackpot probability) becomes 1 / 28.62.

[0132] If you win "Big Win 2" or "Big Win 6", a "Special Feature Low Probability State" will be entered during the period from the end of the current big win game state until the start of the next big win game state. On the other hand, if you win "Big Win 1" or "Big Win 3" through "Big Win 5", a "Special High Probability State" is triggered in accordance with the end of the big win game state. In this embodiment, the "Special High Probability State" is started in accordance with the end of the big win game state and ends in accordance with the start of the next big win game state (end of the display of the "Big Win Symbols" stopping). Furthermore, the "high probability state for special symbols" may be configured to start in response to the end of the jackpot game state, and to end (the "low probability state for special symbols" is established) when the number of special symbol draws performed during the occurrence of the "high probability state for special symbols" reaches a predetermined number (for example, 10,000 times).

[0133] Furthermore, if you win "Big Win 1" through "Big Win 6," a time-saving control will be implemented after the end of the corresponding big win game state. The time-saving control is initiated when the jackpot game state ends and terminates when one of the following conditions is met: the special symbol lottery is won (the "jackpot symbol" is displayed when stopped), or the special symbol notification display (variation display and stop display) is performed for a predetermined number of time-saving rounds. If you win "Big Win 2" or "Big Win 6," a predetermined number of time-saving rounds of 100 will be set. On the other hand, if you win "Big Win 1" or "Big Win 3" through "Big Win 5", a predetermined number of time-saving rounds of 10,000 will be set.

[0134] (Regarding control commands) Next, we will explain the control commands transmitted from the main control board 200 to the performance control board 300, and the control commands transmitted and received between the main control board 200 and the payout control board 400. The main control board 200 and the performance control board 300 are connected to each other via a serial communication harness. Communication between the main control board 200 and the performance control board 300 is unidirectional, from the main control board 200 to the performance control board 300; no communication occurs from the performance control board 300 to the main control board 200. Each control command transmitted from the main control board 200 to the performance control board 300 consists of a 1-byte upper-order data indicating the type of control command and a 1-byte lower-order data indicating the content of the control command. Then, the main control board 200 transmits, by serial communication, a control command composed of upper-level data and lower-level data to the effect control board 300. When the effect control board 300 receives the control command from the main control board 200, a serial communication reception interrupt occurs, and by this interrupt processing, the data of the control command is stored in a predetermined area of the RAM.

[0135] In the pachinko machine 1, as control commands transmitted from the main control board 200 to the effect control board 300, there are set a symbol type designation command, a variation mode designation command, a variation pattern designation command, a stop designation command, a game state designation command, a hold number designation command, an opening designation command, a round start designation command, a round end designation command, an ending designation command, a first read-ahead designation command, a second read-ahead designation command, a third read-ahead designation command, an error designation command, a demo designation command, a set value designation command, a game situation designation command, etc. The symbol type designation command is a command for designating the type (stop symbol number) of the stop symbol. Specifically, the symbol type designation command designates one type among "losing symbols" and "big win 1 symbol" to "big win 6 symbols". The symbol type designation command is transmitted at the start of the variable display of the special symbol. In the present embodiment, the symbol type designation commands corresponding to the first special symbol lottery and the second special symbol lottery are set.

[0136] The variation mode designation command is a command for designating the type (variation mode number) of the variation mode. The variation mode designation command designates the variation time associated with the variation mode number by designating the variation mode number. The variation mode designation command designates the variation time (the mode of the first half period of the variation effect) of the first half period in the variable display (variation effect) of the special symbol. In the present embodiment, as the types of the variation modes, m (a plurality of) types in which different variation times are associated with each other are set. And the variation mode designation command designates one of the types (variation mode numbers) of the m types of variation modes ("variation mode m").

[0137] The variation pattern specification command is used to specify the type of variation pattern (variation pattern number). By specifying the variation pattern number, the variation pattern specification command specifies the variation time associated with that variation pattern number. The variation pattern specification command specifies the variation time (the manner of the latter half of the variation performance) of the variation display (variation performance) of special symbols. In this embodiment, n (or more) types of variation patterns are set, each with a different variation time associated with it. The variation pattern specification command then specifies one of the n types of variation patterns (variation pattern numbers) ("variation pattern n"). The variable mode specification command and the variable pattern specification command are sent when the variable display of the special symbols begins.

[0138] The stop command is used to specify the stopping display of special symbols (effect symbols z1, z2). The stop command is sent when the stopping display of the special symbols begins. The game state specification command is a command that specifies the game state (game state offset value). Here, the "game state offset value" is information that specifies the game state. In this embodiment, the game state offset value is set to a numerical value corresponding to each combination of the time-saving control flag value, the special symbol high probability state flag value, the previous jackpot symbol flag value, and the post-jackpot spin count counter value. The game state specification command specifies a game state offset value. The game state specification command is sent when the power is turned on, when the special game phase is changed (described later), etc.

[0139] The command to specify the number of reserved items is a command to specify the number of reserved items. In this embodiment, the command to specify the number of reserved items (number of reserved items in Special Figure 1 or number of reserved items in Special Figure 2) has increased by "1", the number of reserved items has decreased by "1", the number of reserved items, etc. Here, "Number of Special Symbol 1 Reserved" refers to the number of times the notification display (variation display and stop display) for the first special symbol is reserved on the Special Symbol 1 display device. Also, "Number of Special Symbol 2 Reserved" refers to the number of times the notification display (variation display and stop display) for the second special symbol is reserved on the Special Symbol 2 display device. The command to specify the number of reserved symbols is transmitted when the power is turned on, when game information is stored, when the display of special symbols changes begins, etc. In this embodiment, the command to specify the number of reserved symbols is set to correspond to the first special symbol lottery and the second special symbol lottery, respectively.

[0140] The opening command is used to specify the start of the opening period (the start of the jackpot game state). The opening command specifies the type of jackpot game state (the type of "jackpot symbol"). Specifically, the opening command specifies one type from "jackpot symbol 1" to "jackpot symbol 6". The opening command is sent at the start of the opening period (the start of the jackpot game state). The round start command is a command that specifies the start of a round game. The round start command is sent when a round game begins. The round end command is used to specify the end of a round of gameplay. This command is sent when a round of gameplay ends. The ending specification command is a command that specifies the start of the ending period. The ending specification command is sent at the start of the ending period.

[0141] The first pre-read specification command is a command that specifies the type of stopping symbol (one of the following: "losing symbol" and "jackpot symbol 1" to "jackpot symbol 6"). In this embodiment, the first pre-read specification command is set to correspond to the first special symbol lottery and the second special symbol lottery, respectively. The second pre-read specification command is a command that specifies the content of the variation mode. Specifically, the second pre-read specification command specifies that the type of variation mode is undefined ("undefined value"), or that it specifies one of the m types of variation modes (variation mode numbers) ("variation mode m"). The second pre-read specification command is sent when game information is stored. The third pre-read specification command is a command that specifies the content of the variation pattern. Specifically, the third pre-read specification command specifies that the type of variation pattern is undefined ("undefined value"), or that it specifies one of n types of variation patterns (variation pattern numbers) ("variation pattern n"). The third pre-read specification command is sent when game information is stored.

[0142] The error specification command is a command that specifies the occurrence of various errors. In this embodiment, the error specification command specifies the occurrence of a vibration error, a magnetic error, a radio wave error, or a right-hand stroke error. The error specification command is transmitted when the occurrence of any of the errors is detected. The demo command is used to specify the start of the customer waiting state. The demo command is sent when the customer waiting state begins. The setting value specification command is used to specify a setting value stored in the setting value area of ​​RAM230. The setting value specification command is sent when RAM is cleared, when power is restored after power-on, when the setting change state ends, when the setting confirmation state ends, etc. The game status specification command is a command that specifies the start (beginning) or end (end) of the ready-to-fire state. The game status specification command is sent when the ready-to-fire state is established (beginning) and when the ready-to-fire state is ended (end).

[0143] The main control board 200 and the dispensing control board 400 are connected to each other via a serial communication harness. Communication between the main control board 200 and the dispensing control board 400 is bidirectional. Each control command transmitted and received between the main control board 200 and the dispensing control board 400 consists of one byte of data. The main control board 200 then transmits control commands to the dispensing control board 400 via serial communication. When the dispensing control board 400 receives a control command from the main control board 200, a serial communication reception interrupt is generated, and this interrupt processing stores the control command data in a predetermined area of ​​RAM. The dispensing control board 400 also transmits control commands to the main control board 200 via serial communication. When the main control board 200 receives a control command from the dispensing control board 400, a serial communication reception interrupt is generated, and this interrupt processing stores the control command data in a predetermined area of ​​RAM 230.

[0144] In pachinko machine 1, control commands such as the prize ball count specification command are set as control commands transmitted from the main control board 200 to the payout control board 400. The prize ball specification command is a command that specifies the number of prize balls to be dispensed. In this embodiment, the prize ball specification command specifies the dispensing of n prize balls (n=1 to 15). The prize ball specification command is transmitted when the payout control board 400 executes the prize ball dispensing operation. Furthermore, in the pachinko machine 1, control commands are set to be transmitted from the payout control board 400 to the main control board 200, specifying the occurrence and cancellation of payout errors, full tank errors, ball jam errors, and so on. Each control command is transmitted when the occurrence or cancellation of various errors is detected.

[0145] (Processing performed on the main control board 200) Next, we will explain the processes executed on the main control board 200. First, I will explain the functions of the hardware configured on the main control board 200. When power is turned on to the pachinko machine 1, the random number generation circuit 203 starts the hardware random number update process. In the hardware random number update process, each time one clock signal is input from the clock generation circuit 202 (in this embodiment, every 0.083 [μs]), the values ​​of the first loop counter to the third loop counter are updated by "1" within a predetermined range (in this embodiment, within the range of 0 to 65535).

[0146] Furthermore, in the hardware random number update process, every 32 clock cycles input from the clock generation circuit 202 (every 2.666 [μs] in this embodiment), the value of the fourth loop counter is updated by "1" within a predetermined range (in this embodiment, within the range of 0 to 10006). Then, the hardware random number update process updates the random numbers for the regular symbol draw, the jackpot random numbers for the first special symbol draw, the jackpot random numbers for the second special symbol draw, and the reach group random numbers, respectively. Note that the hardware random number update process is executed as a function of the random number generation circuit 203 (hardware) and is executed independently of the process that the CPU 210 executes based on software, which will be described later.

[0147] Furthermore, when power is turned on to the pachinko machine 1, the transmission shift registers of command output ports 1 and 2 begin the control command transmission process, which sends the control commands stored in the FIFO buffer to the performance control board 300 or the payout control board 400. Note that the control command transmission process is executed as a function of command output ports 1 and 2 (hardware) and is executed independently of the process that the CPU 210 executes based on software, which will be described later.

[0148] Next, we will explain the game control process that the CPU 210 of the main control board 200 executes based on the program (software) stored in the ROM 220.

[0149] (CPU initialization process) First, let's explain the CPU initialization process performed by CPU210. Figure 7 is a flowchart showing the CPU initialization process. When power is turned on to the pachinko machine 1, the CPU 210 starts the CPU initialization process shown in Figure 7. The CPU initialization process is based on a program that controls the progress of the game. In other words, the CPU initialization process is based on a program stored in the usage area m1 (program area) of the ROM 220. Once the CPU initialization process begins, the system first proceeds to step S1-1. In step S1-1, the initial setup process is performed, and then the process moves to step S1-2. In the initial setup process, the boot program is read from ROM220, and various settings necessary for executing the process, such as register settings, are made.

[0150] Furthermore, the initial setup process reads the RAM clear signal from the RAM clear switch 207, the detection signal from the setting key switch 208, and the detection signal from the inner frame release sensor 108. Specifically, the value set in the receiving memory area corresponding to the RAM clear switch 207 is read twice, and based on the results of the two reads, it is determined whether or not the RAM clear switch 207 is in an ON state. The determination result is then saved as switch information for the RAM clear switch 207. In this case, if it is determined that the ON state is occurring, a value indicating that the ON state is occurring (in this embodiment, "1") is saved as switch information, and if it is determined that the ON state is not occurring, a value indicating that the ON state is not occurring (in this embodiment, "0") is saved as switch information.

[0151] Furthermore, the system reads the value set in the receiving memory area corresponding to the setting key switch 208 twice, and based on the results of these two reads, it determines whether or not the setting key switch 208 is in an ON state. The determination result is then saved as the switch information for the setting key switch 208. If it is determined that the ON state is occurring, a value indicating that the ON state is occurring (in this embodiment, "1") is saved as the switch information, and if it is determined that the ON state is not occurring, a value indicating that the ON state is not occurring (in this embodiment, "0") is saved as the switch information.

[0152] Furthermore, the system reads the value set in the receiving memory area corresponding to the inner frame release sensor 108 twice, and based on the results of these two reads, it is determined whether or not the inner frame release sensor 108 is in an ON state. If it is determined that the ON state is not occurring, the switch information of the setting key switch 208 is rewritten to a value indicating that the ON state is not occurring (in this embodiment, "0"). On the other hand, if it is determined that the ON state is occurring, the switch information of the setting key switch 208 is not rewritten.

[0153] In step S1-2, the wait processing time setting process is executed, and the process proceeds to step S1-3. In the wait processing time setting process, a predetermined wait processing time (3.1 seconds in this embodiment) is set in the timer counter. This starts the timer counter from measuring the set wait processing time. In step S1-3, it is determined whether the wait processing time set in step S1-2 has elapsed. If it is determined that the wait processing time has elapsed (Yes), the process proceeds to step S1-4. If it is determined that the wait processing time has not elapsed (No), the process in step S1-3 is repeated.

[0154] In step S1-4, the RAM access permission process is executed, and the process proceeds to step S1-5. The RAM access permission process executes the necessary steps to grant access to the work area of ​​RAM230. Specifically, in the RAM access permission process, a value corresponding to the access permission is stored as a RAM protection value in the RAM access protection area of ​​RAM230. This allows CPU210 to access RAM230.

[0155] In step S1-5, the process for acquiring the gaming machine status flag is executed, and the process proceeds to step S1-6. In the process for acquiring the gaming machine status flag, the gaming machine status flag is acquired. Specifically, in the process of acquiring the gaming machine status flag, the value (gaming machine status flag) stored in the gaming machine status flag area of ​​RAM230 is saved (loaded) into the D register. In step S1-6, it is determined whether the backup enable flag is normal or not. If it is determined that the backup enable flag is normal (Yes), the process proceeds to step S1-7. If it is determined that the backup enable flag is not normal (No), the process proceeds to step S1-18. Here, if the value stored in the backup enable flag area of ​​RAM230 (backup enable flag) is a predetermined valid value, it is determined that the backup enable flag is normal. If the value stored in the backup enable flag area is not a predetermined valid value, it is determined that the backup enable flag is not normal.

[0156] In step S1-7, the checksum calculation process is performed, and the process proceeds to step S1-8. In the checksum calculation process, the checksum is calculated based on the backup information. Specifically, in the checksum calculation process, the checksum is first calculated based on the information stored in the used area M1 (F000H~F1FFH) of RAM230 from the backup information. Next, a checksum is calculated based on the information stored in the unused area M2 (F300H~F3FFH) of RAM230 from the backup information.

[0157] In step S1-8, it is determined whether the checksum calculated in step S1-7 is valid or not. If the checksum is determined to be valid (Yes), the process proceeds to step S1-9. If the checksum is determined to be invalid (No), the process proceeds to step S1-18. Here, if both of the following conditions are met: "the checksum value of the used area M1 calculated in step S1-7 matches the checksum value of the used area M1 stored in the checksum area of ​​RAM230" and "the checksum value of the unused area M2 calculated in step S1-7 matches the checksum value of the unused area M2 stored in the checksum area," then the checksum is determined to be normal. On the other hand, if at least one of the following conditions is not met, the checksum is determined to be abnormal: "The checksum value of the used area M1 calculated in step S1-7 matches the checksum value of the used area M1 stored in the checksum area of ​​RAM230" and "The checksum value of the unused area M2 calculated in step S1-7 matches the checksum value of the unused area M2 stored in the checksum area."

[0158] In step S1-9, the process for setting the areas to be cleared when the power is turned on is executed, and the process proceeds to step S1-10. In the process for setting the areas to be cleared when the power is turned on, the areas other than the setting value area and the game machine status flag area (specifically, the checksum area, backup enabled flag area, error-related area, normal game-related area 1, normal game-related area 2, and stack area) are set as the range to be cleared (initialized) in the used area M1 of RAM230. In step S1-10, it is determined whether the RAM clear switch 207 is in the ON state or not. If it is determined that the ON state is not occurring (No), the process proceeds to step S1-11. If it is determined that the ON state is occurring (Yes), the process proceeds to step S1-21. Here, based on the switch information of the RAM clear switch 207 saved in step S1-1, it is determined whether or not the RAM clear switch 207 is in an ON state. In this case, if a value indicating that the ON state is present is saved as switch information, it is determined that the ON state is present; if a value indicating that the ON state is not present is saved, it is determined that the ON state is not present.

[0159] In step S1-11, it is determined whether or not a playable state has been created (set). If it is determined that a playable state has been created (Yes), the process proceeds to step S1-12. If it is determined that a playable state has not been created (No), the process proceeds to step S1-14. Here, it is determined whether or not a playable state has been created based on the game machine status flag stored in the D register. In this case, if the game machine status flag stored in the D register is a value corresponding to a playable state, it is determined that a playable state has been created; if it is not a value corresponding to a playable state, it is determined that a playable state has not been created.

[0160] In step S1-12, it is determined whether the setting confirmation condition is met. If it is determined that the setting confirmation condition is met (Yes), the process proceeds to step S1-13. If it is determined that the setting confirmation condition is not met (No), the process proceeds to step S1-14. The "setting confirmation conditions" are met when the game-playable state is established, the RAM clear switch 207 is not in the ON state, the setting key switch 208 is in the ON state, and the inner frame release sensor 108 is in the ON state. In step S1-1, if the inner frame release sensor 108 is not in an ON state, the switch information of the setting key switch 208 is rewritten to a value indicating that the ON state is not occurring. As a result, if the ON state is occurring for both the setting key switch 208 and the inner frame release sensor 108, a value indicating that the ON state is occurring is stored as the switch information of the setting key switch 208. On the other hand, if the ON state is not occurring for at least one of the setting key switch 208 and the inner frame release sensor 108, a value indicating that the ON state is not occurring is stored as the switch information of the setting key switch 208. Therefore, in step 1-12, it is determined whether the setting confirmation condition is met based on the switch information of the setting key switch 208 saved in step S1-1. In this case, if a value indicating that the ON state has occurred is saved as switch information, it is determined that the setting confirmation condition is met, and if a value indicating that the ON state has not occurred is saved, it is determined that the setting confirmation condition is not met.

[0161] In step S1-13, the setting confirmation state setting process is executed, and the process proceeds to step S1-14. In the setting confirmation state setting process, the D register is set to a value corresponding to the setting value confirmation state as the game machine state flag. In step S1-14, the process for setting the areas to be cleared when power is restored is executed, and the process proceeds to step S1-15. In the process for setting the areas to be cleared when power is restored, the areas to be cleared (initialized) in the used area M1 of RAM230 are set to include the setting value area, the game machine status flag area, the normal game-related area 2, and other areas excluding the stack area (specifically, the checksum area, the backup enabled flag area, the error-related area, and the normal game-related area 1).

[0162] In step S1-15, the power-up initialization process is executed, and the process proceeds to step S1-16. In the power-up initialization process, the range of the used area M1 of RAM230 set in step S1-14 is cleared (initialized). In step S1-16, the power restoration subcommand transmission process is executed, and the process proceeds to step S1-17. In the power restoration subcommand transmission process, a subcommand (power restoration specification command) that specifies that power has been restored from a power outage is stored in the subcommand output request buffer of RAM230. In step S1-17, the process of sending a power-up-and-recovery

[0163] In step S1-18, the backup abnormal state setting process is executed, and the process proceeds to step S1-19. In the backup abnormal state setting process, a value corresponding to the backup abnormal state is set in the D register as the game machine status flag. In step S1-19, an unused area read / write check process is executed, and the process proceeds to step S1-20. In the unused area read / write check process, the unused area M2 of RAM230 is cleared (initialized) and a read / write check is performed. In step S1-20, the process for setting the area to be cleared in case of an error is executed, and the process proceeds to step S1-21. In the process for setting the area to be cleared in case of an error, all areas (specifically, the setting value area, the game machine status flag area, the checksum area, the backup enabled flag area, the error-related area, the normal game-related area 1, the normal game-related area 2, and the stack area) are set as the range to be cleared (initialized) in the used area M1 of RAM230. In step S1-21, a read / write check of the used memory area is performed, and the process proceeds to step S1-22. In the read / write check of the used memory area, the range set in step S1-20 of the used memory area M1 of RAM230 is cleared (initialized), and a read / write check is performed.

[0164] In step S1-22, it is determined whether the read / write check performed in steps S1-19 and S1-21 is normal or not. If the read / write check is determined to be abnormal (No), the process proceeds to step S1-23. If the read / write check is determined to be normal (Yes), the process proceeds to step S1-24. In step S1-23, the RAM abnormal state setting process is executed, and the process proceeds to step S1-28. In the RAM abnormal state setting process, a value corresponding to the RAM abnormal state is set in the D register as the game machine state flag. In step S1-24, it is determined whether or not the setting confirmation state has occurred (is set). If it is determined that the setting confirmation state has occurred (Yes), the process proceeds to step S1-25. If it is determined that the setting confirmation state has not occurred (No), the process proceeds to step S1-26. Here, it is determined whether or not the setting confirmation state has occurred based on the game machine status flag stored in the D register. In this case, if the game machine status flag stored in the D register is a value corresponding to the setting confirmation state, it is determined that the setting confirmation state has occurred; if it is not a value corresponding to the setting confirmation state, it is determined that the setting confirmation state has not occurred. In step S1-25, the game-ready state setting process is executed, and the process proceeds to step S1-26. In the game-ready state setting process, a value corresponding to the game-ready state is set in the D register as the game machine state flag.

[0165] In step S1-26, it is determined whether the setting change condition is met. If it is determined that the setting change condition is met (Yes), the process proceeds to step S1-27. If it is determined that the setting change condition is not met (No), the process proceeds to step S1-28. The "setting change condition" is met when the RAM clear switch 207 is ON, the setting key switch 208 is ON, and the inner frame release sensor 108 is ON. Here, as described above, if both the setting key switch 208 and the inner frame release sensor 108 are in an ON state, a value indicating that an ON state is occurring is stored as the switch information for the setting key switch 208. On the other hand, if at least one of the setting key switch 208 and the inner frame release sensor 108 is not in an ON state, a value indicating that an ON state is not occurring is stored as the switch information for the setting key switch 208. Therefore, in step 1-26, it is determined whether or not the setting change condition is met based on the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208 that were saved in step S1-1. In this case, if values ​​indicating that an ON state has occurred are stored for both the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208, it is determined that the setting change condition has been met. On the other hand, if values ​​indicating that an ON state has not occurred are stored for at least one of the switch information of the RAM clear switch 207 and the switch information of the setting key switch 208, it is determined that the setting change condition has not been met.

[0166] In step S1-27, the setting change state setting process is executed, and the process proceeds to step S1-28. In the setting change state setting process, a value corresponding to the setting change state is set in the D register as the game machine state flag. In step S1-28, the game machine status flag saving process is executed, and the process proceeds to step S1-29. In the game machine status flag saving process, the game machine status flag set in the D register is saved to the game machine status flag area of ​​RAM230. In step S1-29, the RAM clear subcommand transmission process is executed, and the process proceeds to step S1-30. In the RAM clear subcommand transmission process, a subcommand (RAM clear specification command) indicating that a RAM clear has been performed is stored in the subcommand output request buffer of RAM230. In step S1-30, the RAM clear initialization process is executed, and the process proceeds to step S1-31. In the RAM clear initialization process, the range of the used area M1 of RAM230 set in step S1-9 or step S1-20 is cleared (initialized). In step S1-31, the RAM clear payout command transmission process is executed, and the process proceeds to step S1-32. In the RAM clear payout command transmission process, a payout command indicating that a RAM clear has been performed is stored in the payout command output request buffer of RAM230.

[0167] In step S1-32, the subcommand setting process is executed, and the process proceeds to step S1-33. In the subcommand setting process, the power-on game machine state specification command, which specifies the current state of the game machine, is stored in the subcommand output request buffer of RAM230. Specifically, in the subcommand setting process, a power-on game machine state specification command, which specifies the game machine state flag (game machine state) stored in the game machine state flag area of ​​RAM230, is stored in the subcommand output request buffer of RAM230. In step S1-33, the subcommand group setting process is executed, and the process proceeds to step S1-34. In the subcommand group setting process, the subcommand group is stored in the subcommand output request buffer of RAM230. The subcommand group includes subcommands for specifying the power recovery phase, subcommands for specifying the game state (game state offset value), subcommands for specifying the launch position, subcommands for specifying the stopping symbol of the first special symbol, subcommands for specifying the stopping symbol of the second special symbol, subcommands for specifying the number of special symbol 1 reserved, subcommands for specifying the number of special symbol 2 reserved, subcommands for specifying the value of the time reduction counter, and setting value specification commands for specifying setting values ​​stored in the setting value area of ​​RAM230.

[0168] In step S1-34, the initial display time setting process is executed, and the process proceeds to step S1-35. In the initial display time setting process, the initial display time of the performance display device 206 is set in the initial display timer. In step S1-35, the interrupt setting process is executed, and the process moves to the main loop (step S2-1). The interrupt setting process initializes the peripheral device, the CTC (counter / timer circuit). Specifically, the interrupt setting process sets the interrupt vector register and sets the interrupt count value (4.0 [ms] in this embodiment) to the CTC.

[0169] (Main loop processing) Next, we will explain the main loop processing executed by CPU210. Figure 8 is a flowchart showing the main loop processing. After the CPU initialization process (step S1-35) shown in Figure 7 is completed, the CPU 210 starts the main loop process shown in Figure 8. The main loop process is based on a program that controls the progress of the game. In other words, the main loop process is based on a program stored in the usage area m1 (program area) of the ROM 220. When the main loop processing starts, the program first proceeds to step S2-1.

[0170] In step S2-1, the interrupt disable process is executed, and the process proceeds to step S2-2. The interrupt disable process sets an interrupt disable state, which prevents interrupts from other processes. As a result, during the period in which the interrupt disable state is set, the execution of processes such as the power outage save process and timer interrupt process, which will be described later, is prohibited. In step S2-2, the initial random number update process is executed, and the process proceeds to step S2-3. In the initial random number update process, the value of the loop counter used to generate the initial random number is updated. Here, "initial random number" refers to a random number used to determine the initial and final values ​​of software random numbers (such as winning symbol random numbers, reach mode random numbers, and variation pattern random numbers) that are generated within the program. In other words, the value of the loop counter that generates software random numbers is updated within a predetermined range from an initial value to an end value. The initial and end values ​​of the loop counter that generates software random numbers are changed each time the loop counter value reaches the end value. At this time, the initial and end values ​​of the loop counter are determined based on the initial random number.

[0171] In step S2-3, the main command analysis process is executed, and the process proceeds to step S2-4. In the main command analysis process, the main command received from the dispensing control board 400 (a control command transmitted from the dispensing control board 400 to the main control board 200) is analyzed, and processing is executed according to the analysis results. In step S2-4, the subcommand transmission process is executed, and the process proceeds to step S2-5. In the subcommand transmission process, the subcommand stored in the subcommand output request buffer of RAM230 is output to the transmission data register of output port 205 (command output port 1). As a result, the subcommands entered into the transmission data register are stored in the FIFO buffer. Then, the subcommands stored in the FIFO buffer are transmitted to the performance control board 300 in a predetermined order by the transmission shift register.

[0172] In step S2-5, the interrupt enable process is executed, and the process proceeds to step S2-6. The interrupt enable process releases the interrupt disable state. As a result, the period from the execution of the interrupt enable process in step S2-5 to the execution of the interrupt disable process in step S2-1 becomes an interrupt enable period during which the execution of power outage save process, timer interrupt process, etc., is permitted. In step S2-6, the other random number update process is executed, and the process proceeds to step S2-1. In the other random number update process, the software random numbers excluding the winning symbol random numbers (specifically, the reach mode random numbers, variation pattern random numbers, etc.) are updated.

[0173] (Evacuation procedure in case of power outage) Next, we will explain the power-off backup process performed by CPU210. Figure 9 is a flowchart showing the evacuation process when the power is cut off. The main control board 200 includes a power cutoff detection circuit (not shown). The power cutoff detection circuit monitors the power supply voltage supplied from the power supply board 600 and outputs a power cutoff warning signal to the input port 204 when the power supply voltage falls below a predetermined reference value. When the CPU 210 receives a power cut-off warning signal, it starts the power cut-off save process shown in Figure 9 during the interrupt-enabled period of the main loop processing. The power cut-off save process is based on a program for controlling the progress of the game. In other words, the power cut-off save process is based on a program stored in the usage area m1 (program area) of the ROM 220.

[0174] When the power outage evacuation process is initiated, the process first proceeds to step S3-1. In step S3-1, the register save process is executed, and the process proceeds to step S3-2. In the register save process, the values ​​of the registers used during the execution of the main loop process are saved to the save area of ​​RAM230. In step S3-2, the power cut-off warning signal reading process is executed, and the process proceeds to step S3-3. In the power cut-off warning signal reading process, the power cut-off warning signal from the power cut-off detection circuit is read. Specifically, the power cut-off warning signal reading process reads the value ("1" or "0") set in the receiving memory area corresponding to the power cut-off warning signal of input port 204. In step S3-3, based on the value read in step S3-2 (the value set in the receiving memory area corresponding to the power cut-off warning signal), it is determined whether or not a power cut-off warning signal has been input from the power cut-off detection circuit. If it is determined that a power cut-off warning signal has been input (Yes), the process proceeds to step S3-4. If it is determined that a power cut-off warning signal has not been input (No), the process proceeds to step S3-13.

[0175] In step S3-4, the output port shutdown process is executed, and the process proceeds to step S3-5. The output port shutdown process stops the output of control signals and control commands from output port 205 (output ports 0 to 4). Specifically, the output port shutdown process initializes the values ​​of all bits in the port registers of output port 205 (output ports 0 to 4). This stops the output of control signals and control commands from output port 205 (output ports 0 to 4). In step S3-5, the backup enable flag setting process is executed, and the process proceeds to step S3-6. In the backup enable flag setting process, a predetermined enable value is saved in the backup enable flag area of ​​RAM230.

[0176] In step S3-6, the checksum saving process is performed, and the process proceeds to step S3-7. In the checksum saving process, the checksum is calculated and saved. Specifically, in the checksum saving process, first, a checksum is calculated based on the information stored in the used area M1 (F000H~F1FFH) of RAM230. Then, the calculated checksum value is saved to the checksum area of ​​RAM230. Next, a checksum is calculated based on the information stored in the unused area M2 (F300H~F3FFH) of RAM230. Then, the calculated checksum value is saved to the checksum area. In step S3-7, the RAM access prohibition process is executed, and the process proceeds to step S3-8. The RAM access prohibition process executes a process to prohibit access to RAM230. Specifically, in the RAM access prohibition process, a value corresponding to the access prohibition is stored as a RAM protect value in the RAM access protect area of ​​RAM230. This prevents CPU210 from accessing RAM230.

[0177] In step S3-8, the loop counter setting process is executed, and the process proceeds to step S3-9. In the loop counter setting process, a predetermined number of power cut-off warning signal reads is set as the value of the loop counter for recovery determination. In step S3-9, the power cut-off warning signal reading process is executed, and the process proceeds to step S3-10. In the power cut-off warning signal reading process, the power cut-off warning signal from the power cut-off detection circuit is read. Specifically, the power cut-off warning signal reading process reads the value ("1" or "0") set in the receiving memory area corresponding to the power cut-off warning signal of input port 204. In step S3-10, based on the value read in step S3-9 (the value set in the receiving memory area corresponding to the power cut-off warning signal), it is determined whether or not a power cut-off warning signal has been input from the power cut-off detection circuit. If it is determined that no power cut-off warning signal has been input (No), the process proceeds to step S3-11. If it is determined that a power cut-off warning signal has been input (Yes), the process proceeds to step S3-8.

[0178] In step S3-11, the loop counter update process is executed, and the process proceeds to step S3-12. In the loop counter update process, "1" is subtracted from the value set for the loop counter used for recovery determination. In step S3-12, it is determined whether the value of the recovery determination loop counter is "0". If it is determined that the value of the recovery determination loop counter is "0" (Yes), the process proceeds to the CPU initialization process (step S1-1). If it is determined that the value of the recovery determination loop counter is not "0" (No), the process proceeds to step S3-9. In step S3-13, the register restore process is executed, ending the series of processes and returning to the original process. The register restore process restores the values ​​of the registers that were saved in step S3-1. After the register restore process is completed, the program returns to the main loop process (the program address indicated by the stack pointer).

[0179] (Timer interrupt handling) Next, we will explain the timer interrupt handling performed by CPU210. Figure 10 is a flowchart showing the timer interrupt processing. The clock generation circuit 202 generates an interrupt request signal at predetermined interrupt intervals (4.0 [ms] in this embodiment). In response to the occurrence of an interrupt request signal, the CPU 210 starts the timer interrupt processing shown in Figure 10 during the interrupt enable period of the main loop processing. The main loop processing is based on a program for controlling the progress of the game. In other words, the main loop processing is based on a program stored in the usage area m1 (program area) of the ROM 220.

[0180] When timer interrupt processing begins, the process first proceeds to step S4-1. In step S4-1, the register save process is executed, and the process proceeds to step S4-2. In the register save process, the values ​​of all registers used during the execution of the main loop process are saved to the save area of ​​RAM230. In step S4-2, the interrupt enable process is executed, and the process proceeds to step S4-3. The interrupt enable process enables the interrupt. In step S4-3, dynamic port output processing is performed, and the process proceeds to step S4-4. Dynamic port output processing will be described later.

[0181] In step S4-4, port input processing is performed, and the process proceeds to step S4-5. During port input processing, the status of each switch sensor (each signal) is acquired. RAM230 is provided with an input information storage area corresponding to each switch / sensor (each signal input to input port 204) connected to input port 204 (input port 0 to input port 3), and an on-state storage area corresponding to each switch / sensor (each signal input to input port 204) connected to input port 204 (input port 0 to input port 3). In port input processing, first, for each switch / sensor connected to input port 204 (input ports 0 to 3), the information set in the receiving memory area corresponding to that switch / sensor is acquired, and the acquired information is saved (stored) in the input information memory area corresponding to that switch / sensor. As a result, for each switch sensor, if a detection signal is input from that switch sensor (high level), "1" is stored in the input information storage area corresponding to that switch sensor, and if no detection signal is input from that switch sensor (low level), "0" is stored in the input storage area corresponding to that switch sensor.

[0182] Next, it is determined whether an ON state has occurred for each switch and sensor connected to input port 204 (input ports 0 to 3). In this process, the ON state is determined for each switch and sensor based on the value stored in the input information storage area during the previous port input processing and the value stored in the input information storage area during the current port input processing. "On state" refers to the state in which the detection signal changes from a state where no detection signal is input (low level) to a state where a detection signal is input (high level). Then, if it is determined that an ON state has occurred for each switch or sensor, the ON state memory area corresponding to that switch or sensor is set to "1". On the other hand, if it is determined that an ON state has not occurred for each switch or sensor, the ON state memory area corresponding to that switch or sensor is set to "0". In the following explanation, the value stored in the ON state memory area corresponding to each switch sensor will be referred to as the "switch bit data" of that switch sensor. In particular, input port 1 is provided with a receiving storage area corresponding to the handle detection signal input from the firing condition detection unit 422. During port input processing, the information set in the receiving storage area corresponding to the handle detection signal of input port 1 is acquired, and the acquired information is stored in the input information storage area corresponding to the handle detection signal.

[0183] In step S4-5, the process of acquiring the gaming machine status flag is executed, and the process proceeds to step S4-6. In the process of acquiring the gaming machine status flag, the gaming machine status flag stored in the gaming machine status flag area of ​​RAM230 is acquired. In step S4-6, it is determined whether or not a playable state has been created (set). If it is determined that a playable state has not been created (No), the process proceeds to step S4-7. If it is determined that a playable state has been created (Yes), the process proceeds to step S4-9. Here, based on the game machine status flag obtained in step S4-5, it is determined whether or not a playable state has been established. In this case, if the obtained game machine status flag is a value corresponding to a playable state, it is determined that a playable state has been established; if it is not a value corresponding to a playable state, it is determined that a playable state has not been established.

[0184] In step S4-7, it is determined whether or not an abnormal condition has occurred (is set). If it is determined that no abnormal condition has occurred (No), the process proceeds to step S4-8. If it is determined that an abnormal condition has occurred (Yes), the process proceeds to step S4-19. Here, based on the game machine status flag obtained in step S4-5, it is determined whether or not an abnormal state has occurred. In this case, if the obtained game machine status flag is a value corresponding to any of the following: setting abnormal state, RAM abnormal state, and backup abnormal state, it is determined that an abnormal state has occurred. If the obtained game machine status flag is not a value corresponding to any of the following: setting abnormal state, RAM abnormal state, and backup abnormal state, it is determined that an abnormal state has not occurred.

[0185] In step S4-8, configuration-related processing is performed, and the process proceeds to step S4-19. The configuration-related processing will be described later. In step S4-9, the timer update process is executed, and the process proceeds to step S4-10. In the timer update process, various timers are updated. Specifically, the timer update process updates the values ​​of various timer counters (special game timer, regular game timer, security timer, etc.). In step S4-10, the initial random number update process is executed, and the process proceeds to step S4-11. The initial random number update process in step S4-10 is the same as the initial random number update process in step S2-2. Specifically, the initial random number update process updates the value of the loop counter used to generate the initial random number. In step S4-11, the winning symbol random number update process is executed, and the process proceeds to step S4-12. In the winning symbol random number update process, the value of the loop counter used to generate the winning symbol random number from the software random numbers is updated. In step S4-12, the switch management process is executed, and the process proceeds to step S4-13. The switch management process executes operations (such as obtaining various random numbers) according to the status of each switch 101, 102, and 104 (whether or not an ON state is detected). The switch management process will be described later.

[0186] In step S4-13, the special game management process is executed, and the process proceeds to step S4-14. The special game management process manages the operation of the special symbol display device and the special electric mechanism 53a. The special game management process will be described later. In step S4-14, the normal game management process is executed, and the process proceeds to step S4-15. The normal game management process manages the operation of the normal display device and the normal electric mechanism 52a. The normal game management process will be described later.

[0187] In step S4-15, the state management process is executed, and the process proceeds to step S4-16. The state management process monitors the occurrence and resolution of various errors (abnormal states). When the occurrence or resolution of various errors is detected, various settings (such as subcommand settings) are executed. Furthermore, in the state management process, it is determined whether the state has changed from one where the handle detection signal is not input to one where it is input, based on the values ​​stored in the input information storage area corresponding to the handle detection signal (the value stored in the previous timer interrupt processing and the value stored in the current timer interrupt processing). If it is determined that the state has changed from one where the handle detection signal is not input to one where it is input, a game status specification command that specifies the occurrence of a ready-to-fire state is stored in the subcommand output request buffer of RAM230. Furthermore, in the state management process, it is determined whether the state has changed from one in which the handle detection signal is present to one in which it is not, based on the values ​​stored in the input information storage area corresponding to the handle detection signal (the values ​​stored in the previous timer interrupt process and the values ​​stored in the current timer interrupt process). If it is determined that the state has changed from one in which the handle detection signal is present to one in which it is not, a game state specification command that specifies the release of the firing-ready state is stored in the subcommand output request buffer of RAM230. In step S4-16, the prize slot switch processing is executed, and the process proceeds to step S4-17. In the prize slot switch processing, processing (such as updating various counters) is performed according to the state of each switch 101-103, 105, and 106 (whether or not an ON state is detected).

[0188] In step S4-17, the payout control management process is executed, and the process proceeds to step S4-18. In the payout control management process, a payout command is generated based on the value of the prize ball control counter set in step S4-16, and the generated payout command is sent. In this embodiment, the following prize ball control counters are set: prize ball control counter 1 which stores the number of balls that entered the large prize slot 53; prize ball control counter 2 which stores the number of balls that entered the right other prize slot 54; prize ball control counter 3 which stores the number of balls that entered the upper left, left center, lower left other prize slots 55-57; prize ball control counter 4 which stores the number of balls that entered the first starting slot 51; and prize ball control counter 5 which stores the number of balls that entered the second starting slot 52. In the payout control management process, first, it is determined whether the value of the prize ball control counter 1 is "1" or greater. If it is determined that the value of the prize ball control counter 1 is "1" or greater, a payout command is generated that specifies the payout of a predetermined number of prize balls (15 balls in this embodiment), and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is sent to the payout control board 400. Subsequently, when the payout control board 400 completes the payout of the prize balls by the game ball payout device 440, it sends a main command to the main control board 200 that specifies the completion of the payout. In response to the receipt of the main command specifying the completion of the payout, "1" is subtracted from the value of the prize ball control counter 1.

[0189] Next, it is determined whether the value of the prize ball control counter 2 is "1" or greater. If it is determined that the value of the prize ball control counter 2 is "1" or greater, a payout command is generated that specifies the payout of a predetermined number of prize balls (10 balls in this embodiment), and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is transmitted to the payout control board 400. Subsequently, in response to the receipt of a main command specifying the completion of the payout, "1" is subtracted from the value of the prize ball control counter 2. Next, it is determined whether the value of the prize ball control counter 3 is "1" or greater. If it is determined that the value of the prize ball control counter 3 is "1" or greater, a payout command is generated that specifies the payout of a predetermined number of prize balls (10 balls in this embodiment), and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is transmitted to the payout control board 400. Subsequently, in response to the receipt of a main command specifying the completion of the payout, "1" is deducted from the value of the prize ball control counter 3.

[0190] Next, it is determined whether the value of the prize ball control counter 4 is "1" or greater. If it is determined that the value of the prize ball control counter 4 is "1" or greater, a payout command is generated that specifies the payout of a predetermined number of prize balls (3 balls in this embodiment), and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is transmitted to the payout control board 400. Subsequently, in response to the receipt of a main command specifying the completion of the payout, "1" is deducted from the value of the prize ball control counter 4. Next, it is determined whether the value of the prize ball control counter 5 is "1" or greater. If it is determined that the value of the prize ball control counter 5 is "1" or greater, a payout command is generated that specifies the payout of a predetermined number of prize balls (in this embodiment, 1 ball), and the generated payout command is stored in the payout command output request buffer of RAM 230. As a result, a payout command specifying the payout of a predetermined number of prize balls is transmitted to the payout control board 400. Subsequently, in response to the receipt of a main command specifying the completion of the payout, "1" is deducted from the value of the prize ball control counter 5.

[0191] In step S4-18, the launch position designation management process is executed, and the process proceeds to step S4-19. The launch position designation management process executes the process related to designating the launch position. Specifically, in the launch position specification management process, when the state changes from specifying the launch of the game ball to the left path to specifying the launch of the game ball to the right path (such as at the start of a jackpot game state), the launch position specification flag area of ​​RAM230 is set to "1", and a subcommand specifying the launch of the game ball to the right path is stored in the subcommand output request buffer of RAM230. As a result, the subcommand specifying the launch of the game ball to the right path is sent to the performance control board 300. On the other hand, when changing from a state that specifies launching the game ball to the right path to a state that specifies launching the game ball to the left path (such as when the time-saving control ends), the launch position specification flag area of ​​RAM230 is set to "0".

[0192] In step S4-19, the external information management process is executed, and the process proceeds to step S4-20. In the external information management process, the external information (external signals) to be output to the hall computer (or data display device) is set. In this embodiment, the external information output from the pachinko machine 1 to external devices (electronic devices such as hall computers and data display devices) is defined to include information on the number of times symbols have been confirmed, information on the starting gate, information on big wins, security information, information on the number of payouts from the output gate, and error occurrence information. The "symbol confirmation count information" is external information regarding the number of times the special symbol lottery (display and stop display of the special symbol) has been performed. The CPU 210 outputs an external signal corresponding to the symbol confirmation count information to the hall computer (or data display device) each time the number of times the special symbol stop display has been performed reaches a predetermined number of times.

[0193] The "start gate information" is external information regarding the entry of game balls into start gates 51 and 52. Whenever the CPU 210 detects that the detection signal input from start gate switches 101 and 102 is ON, it outputs an external signal corresponding to the start gate information to the hall computer (or data display device). "Big win information" is external information related to the occurrence of a big win game state. The main control board 200 outputs an external signal corresponding to the big win information to the hall computer (or data display device) each time a big win game state occurs. The "outlet payout information" is external information relating to the number of game balls discharged from the discharge path (or the number of game balls discharged from the outlet 58). The CPU 210 outputs an external signal corresponding to the outlet payout information to the hall computer each time the value of the external information outlet ball counter reaches a predetermined value. "Security information" is external information indicating that a setting change state is occurring, a setting confirmation state is occurring, or various errors (abnormalities) are occurring. When the security timer value is "1" or greater, the CPU 210 outputs an external signal corresponding to the security information to the hall computer.

[0194] In the external information management process, it is determined whether the value of the external information confirmation count counter has reached a predetermined value (1 in this embodiment). If it is determined that the value of the external information confirmation count counter has reached the predetermined value, the symbol confirmation count information (external signal) is stored in the port output request buffer of RAM230. Then, the predetermined value (1 in this embodiment) is subtracted from the value of the external information confirmation count counter. As a result, the symbol confirmation count information (external signal) is output to the hall computer. Furthermore, the external information management process determines whether the value of the ball entry counter for the external information start slot has reached a predetermined value (1 in this embodiment). If it is determined that the value of the ball entry counter for the external information start slot has reached the predetermined value, the start slot information (external signal) is stored in the port output request buffer of RAM230. Then, the predetermined value (1 in this embodiment) is subtracted from the value of the ball entry counter for the external information start slot. As a result, the start slot information (external signal) is output to the hall computer.

[0195] Furthermore, the external information management process determines whether the value of the external information jackpot count counter has reached a predetermined value (1 in this embodiment). If it is determined that the value of the external information jackpot count counter has reached the predetermined value, the jackpot information (external signal) is stored in the port output request buffer of RAM230. Subsequently, the predetermined value (1 in this embodiment) is subtracted from the value of the external information jackpot count counter. As a result, the jackpot information (external signal) is output to the hall computer. Furthermore, the external information management process determines whether the value of the external information ball count counter has reached a predetermined value (10 balls in this embodiment). If it is determined that the value of the external information ball count counter has reached the predetermined value, the ball payout information (external signal) is stored in the port output request buffer of RAM230. Subsequently, the predetermined value (10 balls in this embodiment) is subtracted from the value of the external information ball count counter. As a result, the ball payout information (external signal) is output to the hall computer.

[0196] Furthermore, the external information management process determines whether the value stored in the gaming machine status flag area of ​​RAM230 (gaming machine status flag) corresponds to the playable state. Then, if it is determined that the value stored in the gaming machine status flag area does not correspond to the playable state (i.e., it is determined to correspond to the setting change state, setting confirmation state, setting abnormal state, RAM abnormal state, or backup abnormal state), security information is stored in the port output request buffer of RAM230. As a result, security information (external signal) is output to the hall computer. Furthermore, the external information management process determines whether the security timer value is "1" or greater. If it is determined that the security timer value is "1" or greater, the security information is stored in the port output request buffer of RAM230. This causes the security information (external signal) to be output to the hall computer.

[0197] In step S4-20, the LED display setting process is executed, and the process proceeds to step S4-21. In the LED display setting process, the display data to be output to the main display device 60 or the performance display device 206 is set. RAM230 is provided with a common 0 output request buffer (8 bits), a common 1 output request buffer (8 bits), a common 2 output request buffer (8 bits), and a common 3 output request buffer (8 bits). In the LED display setting process, the common 2 output request buffer is first cleared (initialized), and the common 3 output request buffer is also cleared (initialized). Specifically, each bit value of the common 2 output request buffer is set to "0", and each bit value of the common 3 output request buffer is set to "0".

[0198] Next, the game machine status flag stored in the game machine status flag area of ​​RAM230 is retrieved. If the acquired gaming machine status flag corresponds to a playable state, the normal display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag corresponds to a setting change state, the setting change display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag corresponds to a setting confirmation state, the setting confirmation display data setting process described later is executed. On the other hand, if the acquired gaming machine status flag corresponds to an abnormal state (setting abnormal state, RAM abnormal state, or backup abnormal state), the abnormal display data setting process described later is executed.

[0199] In the normal display data setting process, first, the value of the Special Feature 1 display symbol counter is obtained, and the display data (8 bits) corresponding to the obtained value of the Special Feature 1 display symbol counter is set in the Common 0 output request buffer. As a result, the first special pattern is displayed by LED1 to LED8, which are light-emitting elements that make up the main display device 60. Next, the value of the Special Feature 2 display symbol counter is obtained, and the display data (8 bits) corresponding to the obtained value of the Special Feature 2 display symbol counter is set in the Common 1 output request buffer. As a result, the second special pattern is displayed by LED9 to LED16, which are light-emitting elements that make up the main display device 60. Next, the value of the regular display pattern counter is obtained, and the display data corresponding to the obtained value of the regular display pattern counter is set as output data a.

[0200] Next, it is determined whether the value set in the special game phase flag area of ​​RAM230 specifies one of the special game phases: "pre-opening state of the big prize slot," "control state of opening the big prize slot," "active state of closing the big prize slot," and "wait state after the big prize slot has opened." Then, if it is determined that the value set in the special game phase flag area is a value that specifies one of the special game phases among "pre-opening state of the big prize slot", "control state of opening the big prize slot", "active state of closing the big prize slot", and "wait state after the big prize slot has opened", the value set in the special symbol determination flag area of ​​RAM230 (a value corresponding to the type of big win symbol) is obtained, and the display data corresponding to the obtained value is set as output data b. On the other hand, if the value set in the special game phase flag area is determined not to be a value that specifies one of the special game phases among "pre-opening state of the big prize slot," "control state for opening the big prize slot," "active state for closing the big prize slot," and "wait state for the end of opening the big prize slot," then output data b will not be set.

[0201] Next, the value set in the launch position specification flag area of ​​RAM230 is retrieved, and the display data corresponding to the retrieved value is set as output data c. Next, the display data (8 bits) obtained by logically ORing output data a to output data c is set in the common 2 output request buffer. As a result, among the light-emitting elements that make up the main display device 60, LEDs 17 and 18 display a normal pattern, LEDs 19 to 23 display the number of rounds played during a jackpot game (type of jackpot game), and LED 24 displays the path through which the game ball should be launched (left path or right path). Next, the value of the reserved count counter in Special Feature 1 is obtained, and the display data corresponding to the obtained value is set as output data d. Next, the value of the reserved count counter in Special Feature 2 is obtained, and the display data corresponding to the obtained value is set as output data e. Next, the value of the regular display count counter is obtained, and the display data corresponding to the obtained value is set as output data f. Next, we determine whether or not the power has been restored. Then, if it is determined that the power has been restored, the value set in the special feature high probability state flag area is obtained, and the display data corresponding to the obtained value is set as output data g. On the other hand, if it is determined that the power has not been restored, output data g will not be set. Next, the value set in the time-saving control flag area of ​​RAM230 is retrieved, and the display data corresponding to the retrieved value is set as output data h. Next, the display data (8 bits) obtained by logically ORing output data d to output data h is set in the common 3 output request buffer. As a result, among the light-emitting elements that make up the main display device 60, LEDs 25 and 26 display the number of reserved special symbols 1, LEDs 27 and 28 display the number of reserved special symbols 2, LEDs 29 and 30 display the number of reserved regular symbols, LED 31 displays the game state when the power is restored (when a high probability special symbol state is occurring or when a low probability special symbol state is occurring), and LED 32 displays the current game state (when time-saving control is being executed or stopped).

[0202] During the setting change display data setting process, information indicating that a setting change state is occurring is set in the Common 0 output request buffer to the Common 2 output request buffer, and information indicating the setting value stored in the setting value area of ​​RAM230 is set in the Common 3 output request buffer. Specifically, the display data for "r" (8 bits) is set in the Common 0 output request buffer, the display data for "n." (8 bits) is set in the Common 1 output request buffer, the display data for "-" (8 bits) is set in the Common 2 output request buffer, and the display data corresponding to the setting value stored in the setting value area of ​​RAM230 is set in the Common 3 output request buffer. As a result, among the light-emitting elements that make up the performance display device 206, LEDs 33 to 40 display the letter "r", LEDs 41 to 48 display the letter "n.", LEDs 49 to 56 display the letter "-", and LEDs 57 to 64 display a number indicating the set value.

[0203] During the setting confirmation display data setting process, information indicating that the setting confirmation state is in progress is set in the Common 0 output request buffer to the Common 2 output request buffer, and information indicating the setting value stored in the setting value area of ​​RAM230 is set in the Common 3 output request buffer. Specifically, the display data for "r" (8 bits) is set in the Common 0 output request buffer, the display data for "n." (8 bits) is set in the Common 1 output request buffer, and the display data corresponding to the setting value stored in the setting value area of ​​RAM230 is set in the Common 3 output request buffer. Note that no display data is set in the Common 2 output request buffer (it remains at a cleared value). As a result, among the light-emitting elements that make up the performance display device 206, LEDs 33 to 40 display the letter "r", LEDs 41 to 48 display the letter "n.", and LEDs 57 to 64 display a number indicating the set value. LEDs 49 to 56 are turned off.

[0204] In the abnormal status display data setting process, information indicating that an abnormal state (setting abnormal state, RAM abnormal state, or backup abnormal state) is occurring is set in the Common 0 output request buffer to the Common 2 output request buffer, and the error code corresponding to the abnormality that occurred is set in the Common 3 output request buffer. Specifically, the display data for "E" (8 bits) is set in the Common 0 output request buffer, the display data for "r." (8 bits) is set in the Common 1 output request buffer, and the display data (error code) corresponding to the abnormal state that occurred (setting abnormal state, RAM abnormal state, or backup abnormal state) is set in the Common 3 output request buffer. Note that no display data is set in the Common 2 output request buffer (it remains at a cleared value). As a result, among the light-emitting elements that make up the performance display device 206, LEDs 33 to 40 display the letter "E", LEDs 41 to 48 display the letter "r.", and LEDs 57 to 64 display a number indicating an error code. LEDs 49 to 56 are turned off.

[0205] In step S4-21, the solenoid data setting process is executed, and the process proceeds to step S4-22. In the solenoid data setting process, the control data (drive data) to be output for each solenoid 64, 65 is stored (set) in the port output request buffer of RAM230. In step S4-22, port output processing is performed, and the process proceeds to step S4-23. During port output processing, various signals are output to the hall computer, solenoids 64, 65, etc. Specifically, in port output processing, various information (external signals, control signals, etc.) set in the port output request buffer is output to output port 205 (output port 2, output port 3). As a result, the external signals set in the port output request buffer are output to the hall computer. In addition, solenoids 64 and 65 are driven and controlled based on the drive signals set in the port output request buffer. In step S4-23, the interrupt disable process is executed, and the process proceeds to step S4-24. The interrupt disable process sets an interrupt disable state, which prevents interrupts from other processes. As a result, during the period when the interrupt disable state is set, the execution of processes such as the power outage save process and timer interrupt process, which will be described later, is prohibited.

[0206] In step S4-24, the test signal output process is executed, and the process proceeds to step S4-25. In the test signal output process, test information (test signals) is set. The test signal output process is based on a program that executes the testing procedures stipulated in the gaming machine regulations. In other words, the test signal output process is based on a program stored in the unused area m2 (program area) of ROM220. The test signal tube is called during the execution of timer interrupt processing. Specifically, in the test signal output processing, test information (test signals) indicating the internal state (jackpot game state, time-saving control execution state, special symbol lottery probability state, etc.) is stored in the port output request buffer of RAM230. In step S4-25, the performance display device control process is executed, and the process proceeds to step S4-26. The performance display device control process will be described later. In step S4-26, the register restore process is executed, ending the series of processes and returning to the original process. The register restore process restores the values ​​of the registers that were saved in step S4-1. After the register restore process is completed, the program returns to the main loop process (the program address indicated by the stack pointer).

[0207] (Dynamic port output processing) Next, we will explain the dynamic port output processing in step S4-3. Figure 11 is a flowchart showing the dynamic port output processing. When the dynamic port output processing is performed in step S4-3, the process first proceeds to step S29-1, as shown in Figure 11. In step S29-1, the output data clearing process is executed, and the process proceeds to step S29-2. In the output data clearing process, the A register is cleared (initialized). Specifically, each bit value of the A register is set to "0". In step S29-2, the main display device data output process is executed, and the process proceeds to step S29-3. In the main display device data output process, the value of register A (the value cleared in step S29-1) is output to output port 0. This clears (initializes) output port 0, and the data signals ("SEGDATA0" to "SEGDATA7") for controlling the illumination of the main display device 60 are set to a low level.

[0208] In step S29-3, the performance display device data output process is executed, and the process proceeds to step S29-4. In the performance display device data output process, the value of register A (the value cleared in step S29-1) is output to output port 4. This clears (initializes) output port 4, and the data signals ("7SEGDATA0" to "7SEGDATA7") for controlling the illumination of the performance display device 206 are set to a low level. In step S29-4, the common selection process is executed, and the process proceeds to step S29-5. In the common selection process, the value of the common counter is updated. Specifically, the common selection process determines whether the value of the common counter has reached its upper limit (in this embodiment, "3"). If it is determined that the value of the common counter has not reached its upper limit, "1" is added to the value of the common counter. On the other hand, if it is determined that the value of the common counter has reached its upper limit, a predetermined initial value (in this embodiment, "0") is set as the value of the common counter.

[0209] In step S29-5, common output processing is performed, and the process proceeds to step S29-6. In common output processing, output data corresponding to the value of the common counter is output to output port 1. In other words, when the common counter value is "0", output data is output to output port 1 with "COM0" set to high level and "COM1", "COM2", and "COM3" set to low level. As a result, "COM0" is selected (output) from "COM0" to "COM3". On the other hand, if the common counter value is "1", output data is output to output port 1, setting "COM1" to high level and "COM0", "COM2", and "COM3" to low level. As a result, "COM1" is selected (output) from "COM0" to "COM3". On the other hand, if the common counter value is "2", output data is output to output port 1 with "COM2" set to high level and "COM0", "COM1", and "COM3" set to low level. As a result, "COM2" is selected (output) from "COM0" to "COM3". On the other hand, if the common counter value is "3", output data is output to output port 1 with "COM3" set to high level and "COM0", "COM1", and "COM2" set to low level. As a result, "COM3" is selected (output) from "COM0" to "COM3".

[0210] In addition, during common output processing, the output data of the launch permission signal is output to output port 1. In other words, first, it is determined whether or not a playable state has been created (set). Then, if it is determined that a playable state has been established, output data that sets the launch permission signal to a high level is output to output port 1. This results in the output of the launch permission signal. On the other hand, if it is determined that a playable state has not occurred, output data that sets the launch permission signal to a low level is output to output port 1. This stops the output of the launch permission signal. Here, it is determined whether or not a playable state has been established based on the value (playable state flag) stored in the RAM230's game machine state flag area. In this case, if the value stored in the game machine state flag area corresponds to a playable state, it is determined that a playable state has been established; if it does not correspond to a playable state, it is determined that a playable state has not been established. In this embodiment, the common output processing is configured to set the output of the launch permission signal only when it is determined that a playable state has occurred. As a result, the launch permission signal is output only while the playable state is occurring (set). However, the common output processing may also be configured to set the output of the launch permission signal regardless of the state of the game machine. With such a configuration, the launch permission signal can be output at all times while the main control board 200 is powered on.

[0211] In step S29-6, it is determined whether or not a playable state has been created (set). If it is determined that a playable state has been created (Yes), the process proceeds to step S29-7. If it is determined that a playable state has not been created (No), the process proceeds to step S29-11. Here, it is determined whether or not a playable state has been established based on the value (playable state flag) stored in the RAM230's game machine state flag area. In this case, if the value stored in the game machine state flag area corresponds to a playable state, it is determined that a playable state has been established; if it does not correspond to a playable state, it is determined that a playable state has not been established.

[0212] In step S29-7, the main display device data acquisition process is executed, and the process proceeds to step S29-8. In the main display device data acquisition process, display data for the main display device 60 is acquired, and the acquired display data is set in the A register. Specifically, in the main display device data acquisition process, the value of the common counter is first checked. Then, the display data set in the output request buffer corresponding to the checked common counter value among the common 0 output request buffer to common 3 output request buffer of RAM230 is acquired, and the acquired display data is set in the A register. In this case, if the value of the common counter is "0", the display data set in the common 0 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "1", the display data set in the common 1 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "2", the display data set in the common 2 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "3", the display data set in the common 3 output request buffer is retrieved, and the retrieved display data is set in the A register. Here, the display data acquired in the main display device data acquisition process is the display data set in the common 0 output request buffer to common 3 output request buffer in the LED display setting process (specifically, the normal display data setting process) in step S4-20 included in the previous timer interrupt process.

[0213] In step S29-8, the main display device data output process is executed, and the process proceeds to step S29-9. In the main display device data output process, the display data set in register A in step S29-7 is output to output port 0. As a result, data signals ("SEGDATA0" to "SEGDATA7") based on the display data set in the output request buffer (one of the output request buffers from Common 0 to Common 3) are output to the source driver 250a. In other words, the display on the main display device 60 is controlled based on the display data set in the output request buffer (one of the output request buffers from Common 0 to Common 3).

[0214] In step S29-9, the interrupt disable process is executed, and the process proceeds to step S29-10. The interrupt disable process sets an interrupt disable state, which prevents interrupts from other processes. As a result, during the period in which the interrupt disable state is set, the execution of processes such as the power outage save process and timer interrupt process, which will be described later, is prohibited. In step S29-10, the performance display device output processing is executed, and the series of processes is completed, moving on to the next process (step S4-4). The performance display device output processing will be described later.

[0215] In step S29-11, the performance display device data acquisition process is executed, and the process proceeds to step S29-12. In the performance display device data acquisition process, display data for the performance display device 206 is acquired, and the acquired display data is set in the A register. Specifically, in the performance display device data acquisition process, the value of the common counter is first checked. Then, the display data set in the output request buffer corresponding to the checked common counter value from the common 0 output request buffer to the common 3 output request buffer of RAM230 is acquired, and the acquired display data is set in the A register. In this case, if the value of the common counter is "0", the display data set in the common 0 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "1", the display data set in the common 1 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "2", the display data set in the common 2 output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the value of the common counter is "3", the display data set in the common 3 output request buffer is retrieved, and the retrieved display data is set in the A register. Here, the display data acquired in the performance display device data acquisition process is the display data set in the common 0 output request buffer to common 3 output request buffer in the LED display setting process in step S4-20 included in the previous timer interrupt process (specifically, the display data setting process when settings are changed, the display data setting process when settings are confirmed, or the display data setting process when an error occurs).

[0216] In step S29-12, the performance display device data output process is executed, and the series of processes is completed, moving on to the next process (step S4-4). In the performance display device data output process, the display data set in the A register in step S29-11 is output to output port 4. As a result, data signals ("7SEGDATA0" to "7SEGDATA7") based on the display data set in the output request buffer (one of the output request buffers from Common 0 to Common 3) are output to the source driver 250b. In other words, the display on the performance display device 206 is controlled based on the display data set in the output request buffer (one of the output request buffers from Common 0 to Common 3).

[0217] (Performance display device output processing) Next, the performance display device output processing in step S29-10 will be explained. Figure 12 is a flowchart showing the output processing of the performance display device. The performance display device output processing is based on a program that controls the display of the performance display device 206. In other words, the performance display device output processing is based on a program stored in the unused area m2 (program area) of the ROM 220. The performance display device output processing is called during the execution of the dynamic port output processing. When the performance display device output processing is called in step S29-10, it first proceeds to step S30-1, as shown in Figure 12. In step S30-1, the register saving process is executed, and the process proceeds to step S30-2. In the register saving process, the values ​​of all registers used during the execution of the program stored in the usage area m1 are saved to the RAM saving area. In addition, the values ​​of all stack pointers used during the execution of the program stored in the usage area m1 are saved to the RAM saving area.

[0218] In step S30-2, the performance display device data acquisition process is executed, and the process proceeds to step S30-3. In the performance display device data acquisition process, display data for the performance display device 206 is acquired, and the acquired display data is set in the A register. Specifically, in the performance display device data acquisition process, the value of the common counter is first checked. Then, the display data set in the area corresponding to the checked common counter value within the identification segment output request buffer and ratio segment output request buffer of RAM230 is acquired, and the acquired display data is set in the A register. In this case, if the value of the common counter is "0", the display data set in the upper 8 bits of the identification segment output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the common counter value is "1", the display data set in the lower 8 bits of the identification segment output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the common counter value is "2", the display data set in the upper 8 bits of the ratio segment output request buffer is retrieved, and the retrieved display data is set in the A register. On the other hand, if the common counter value is "3", the display data set in the lower 8 bits of the ratio segment output request buffer is retrieved, and the retrieved display data is set in the A register. Here, the display data acquired in the performance display device data acquisition process is the display data set in the identification segment output request buffer or the ratio segment output request buffer in the performance display device control process of step S4-25 included in the previous timer interrupt process.

[0219] In step S30-3, the performance display device data output process is executed, and the process proceeds to step S30-4. In the performance display device data output process, the display data set in the A register in step S30-2 is output to output port 4. As a result, data signals ("7SEGDATA0" to "7SEGDATA7") based on the display data set in the output request buffer (identification segment output request buffer or ratio segment output request buffer) are output to the source driver 250b. In other words, the display of the performance display device 206 is controlled based on the display data set in the output request buffer (identification segment output request buffer or ratio segment output request buffer).

[0220] In step S30-4, the register restoration process is executed, and the process proceeds to step S30-5. In the register restoration process, the values ​​of the registers saved in step S30-1 (the values ​​of the registers used during the execution of the program based on the used area m1) and the value of the stack pointer saved in step S30-1 (the value of the stack pointer used during the execution of the program based on the used area m1) are restored. In step S30-5, the interrupt enable process is executed, ending the series of processes and moving on to the next process (step S4-4). The interrupt enable process releases the interrupt disable state. This allows the execution of processes such as power outage save process and timer interrupt process.

[0221] (Configuration-related processing) Next, we will explain the settings-related processes in step S4-8. Figure 13 is a flowchart showing the settings-related processes. Once the configuration-related processing is performed in step S4-8, the process proceeds to step S37-1, as shown in Figure 13. In step S37-1, it is determined whether or not a setting change state has occurred (is set). If it is determined that a setting change state has occurred (Yes), the process proceeds to step S37-2. If it is determined that a setting change state has not occurred (No), the process proceeds to step S37-8. Here, it is determined whether or not a setting change state has occurred based on the value (game machine status flag) stored in the game machine status flag area of ​​RAM230. In this case, if the value stored in the game machine status flag area corresponds to the setting change state, it is determined that a setting change state has occurred; if it does not correspond to the setting change state, it is determined that a setting change state has not occurred.

[0222] In step S37-2, the setting value acquisition process is executed, and the process proceeds to step S30-3. In the setting value acquisition process, the setting value stored in the setting value area of ​​RAM230 is acquired (loaded), and the acquired setting value is stored in a register. In step S37-3, it is determined whether or not the RAM clear switch 207 has been pressed. If it is determined that the RAM clear switch 207 has been pressed (Yes), the process proceeds to step S37-4. If it is determined that the RAM clear switch 207 has not been pressed (No), the process proceeds to step S37-5. Here, regarding the RAM clear switch 207, if the ON state occurs, it is determined that the RAM clear switch 207 has been pressed; if the ON state does not occur, it is determined that the RAM clear switch 207 has not been pressed. In step S37-4, the setting value update process is executed, and the process proceeds to step S37-5. In the setting value update process, "1" is added to the setting value stored in the register.

[0223] In step S37-5, it is determined whether the setting value stored in the register is less than a predetermined setting comparison value (in this embodiment, "6"). If it is determined that the setting value stored in the register is not less than the predetermined setting comparison value (i.e., the setting value is greater than or equal to the predetermined setting comparison value) (No), the process proceeds to step S37-6. If it is determined that the setting value stored in the register is less than the predetermined setting comparison value (Yes), the process proceeds to step S37-7. In step S37-6, the setting value initialization process is executed, and the process proceeds to step S37-7. In the setting value initialization process, a predetermined initial value (in this embodiment, "0") is overwritten as the setting value stored in the register. In step S37-7, the setting value saving process is executed, and the process proceeds to step S37-8. In the setting value saving process, the setting values ​​stored in the registers are saved to the setting value area of ​​RAM230.

[0224] In step S37-8, it is determined whether the setting key switch 208 is in the ON state or not. If it is determined that the setting key switch 208 is not in the ON state (is in the OFF state) (No), the process proceeds to step S37-9. If it is determined that the setting key switch 208 is in the ON state (Yes), the series of processes ends and the process proceeds to the next step (step S4-19). Here, regarding the setting key switch 208, if an ON state occurs, it is determined that the setting key switch 208 is in the ON state; if an ON state does not occur, it is determined that the setting key switch 208 is not in the ON state. In step S37-9, the subcommand setting process is executed, and the process proceeds to step S37-10. In the subcommand setting process, the setting-related termination specification command (subcommand) is stored in the subcommand output request buffer of RAM230.

[0225] In step S37-10, the subcommand group setting process is executed, and the process proceeds to step S37-11. In the subcommand group setting process, the subcommand group is stored in the subcommand output request buffer of RAM230. Here, the subcommand group includes subcommands for specifying the game state (game state offset value), subcommands for specifying the launch position, subcommands for specifying the stopping symbol of the first special symbol, subcommands for specifying the stopping symbol of the second special symbol, subcommands for specifying the number of special symbol 1 reserved, subcommands for specifying the number of special symbol 2 reserved, subcommands for specifying the value of the time-saving counter, and setting value specification commands for specifying setting values ​​stored in the setting value area of ​​RAM230. In step S37-11, the RAMSet process is executed, completing the series of processes and moving on to the next process (step S4-19). In the RAMSet process, the game machine state is set to a playable state. Specifically, the value corresponding to the playable state is stored (saved) as the value in the gaming machine state flag area of ​​RAM230 (gaming machine state flag).

[0226] (Switch management process) Next, we will explain the switch management process in step S4-12. Figure 14 is a flowchart showing the switch management process. When the switch management process is executed in step S4-12, it first proceeds to step S5-1, as shown in Figure 14. In step S5-1, it is determined whether or not the ON state of the gate switch 104 has been detected. If it is determined that the ON state of the gate switch 104 has been detected (Yes), the process proceeds to step S5-2. If it is determined that the ON state of the gate switch 104 has not been detected (No), the process proceeds to step S5-3. In step S5-2, the general-purpose starting ball detection process is executed, and the process proceeds to step S5-3. The general-purpose starting ball detection process will be described later. Furthermore, the regular starting ball detection process determines whether or not it is the right-handed hitting period. If it is determined that it is not the right-handed hitting period (i.e., it is the left-handed hitting period), "1" is added to the value of the right-handed hitting error counter. In this embodiment, the period during which either the jackpot game state or the time-saving control is in effect is the right-hand play period. On the other hand, the period during which the normal game state (a game state in which the jackpot game state is not in effect and the time-saving control is stopped) is the left-hand play period.

[0227] In step S5-3, it is determined whether or not the ON state of the start port switch 101 in Specifications Figure 1 has been detected. If it is determined that the ON state of the start port switch 101 in Specifications Figure 1 has been detected (Yes), the process proceeds to step S5-4. If it is determined that the ON state of the start port switch 101 in Specifications Figure 1 has not been detected (No), the process proceeds to step S5-5. In step S5-4, the starting ball detection process shown in Figure 1 is executed, and the process proceeds to step S5-5. The starting ball detection process shown in Figure 1 will be described later. In step S5-5, it is determined whether or not the ON state of the start port switch 102 in Figure 2 has been detected. If it is determined that the ON state of the start port switch 102 in Figure 2 has been detected (Yes), the process proceeds to step S5-6. If it is determined that the ON state of the start port switch 102 in Figure 2 has not been detected (No), the process ends and the process proceeds to the next step (step S4-13). In steps S5-6, the Special Feature 2 starting ball detection process is executed, and the series of processes is completed, moving on to the next process (step S4-13). The Special Feature 2 starting ball detection process will be described later.

[0228] (Normal starting ball detection process) Next, the process of detecting the starting ball in step S5-2 will be explained. Figure 15 is a flowchart showing the process for detecting the starting ball. When the general starting ball detection process is executed in step S5-2, the process first proceeds to step S6-1, as shown in Figure 15. In step S6-1, the process of acquiring random numbers for the regular symbols is executed, and then the process moves to step S6-2. In the process of acquiring random numbers for the regular symbols, the winning random number (random value) is acquired (loaded) from the loop counter corresponding to the drawing of regular symbols. In step S6-2, it is determined whether the value of the regular display hold counter is at the upper limit (in this embodiment, "4"). If it is determined that the value of the regular display hold counter is not at the upper limit (No), the process proceeds to step S6-3. If it is determined that the value of the regular display hold counter is at the upper limit (Yes), the series of processes ends and the process proceeds to the next process (step S5-3). In step S6-3, the general chart reserve counter update process is executed, and the process proceeds to step S6-4. In the general chart reserve counter update process, the value obtained by adding "1" to the value currently set in the general chart reserve counter is set as the new value in the general chart reserve counter.

[0229] In step S6-4, the general random number saving process is executed, and the series of processes is completed, moving on to the next process (step S5-3). In the general random number saving process, the winning random number obtained in step S6-1 is stored as general game information in the general game information storage area of ​​RAM230. RAM230 is configured to include a memory area 0 where game information for games currently being played is stored, and a game information storage area where game information for games for which the win / loss judgment is pending is stored. The general game information storage area is configured as a storage area capable of storing general game information, and includes storage areas 1 to 4. The priority of each memory area is defined as follows, from highest priority to lowest: Memory Area 1, Memory Area 2, Memory Area 3, and Memory Area 4 (higher priority to lower priority). The general game information stored in the general game information memory area is then used to determine whether the general game win or loss occurs, starting with the memory area with the highest priority. In the general random number saving process, the winning random number obtained in step S6-1 is stored as general game information in the general game information storage area. At this time, the general game information is stored in the storage area with the highest priority among the available storage areas. In other words, if the current value of the regular number of reserved spins counter is "1", the winning random number obtained in step S6-1 is stored in memory area 1. If the current value of the regular number of reserved spins counter is "2", the winning random number obtained in step S6-1 is stored in memory area 2. If the current value of the regular number of reserved spins counter is "3", the winning random number obtained in step S6-1 is stored in memory area 3. If the current value of the regular number of reserved spins counter is "4", the winning random number obtained in step S6-1 is stored in memory area 4.

[0230] (Special Figure 1: Starting Ball Detection Process) Next, the starting ball detection process in step S5-4, as shown in Figure 1, will be explained. Figure 16 is a flowchart showing the starting ball detection process in Special Figure 1. As shown in Figure 16, when the starting ball detection process is executed in step S5-4, the process first proceeds to step S7-1. In step S7-1, the special symbol identification value setting process is executed, and the process proceeds to step S7-2. In the special symbol identification value setting process, the special symbol identification value corresponding to the first special symbol lottery is set in the special symbol identification value setting area of ​​RAM230. In addition, "1" is added to the value of the ball entry counter for external information start slot. Furthermore, the special symbol identification value setting process determines whether or not it is the right-hand play period. If it is determined that it is not the right-hand play period (i.e., it is the left-hand play period), the value of the right-hand play error counter is reset (the value of the right-hand play error counter is set to "0"). In step S7-2, the pending counter address setting process is executed, and the process proceeds to step S7-3. In the pending counter address setting process, the address of the pending counter shown in Figure 1 is set in the pending counter address setting area of ​​RAM 230. In step S7-3, the process for obtaining special symbol random numbers is executed, and the series of processes ends, moving on to the next process (step S5-5). The process for obtaining special symbol random numbers will be described later.

[0231] (Special Figure 2: Starting Ball Detection Process) Next, the starting ball detection process in step S5-6, as shown in Figure 2, will be explained. Figure 17 is a flowchart showing the starting ball detection process in Special Figure 2. As shown in Figure 17, when the starting ball detection process in step S5-6 is executed, the process first proceeds to step S8-1. In step S8-1, the special symbol identification value setting process is executed, and the process proceeds to step S8-2. In the special symbol identification value setting process, the special symbol identification value corresponding to the second special symbol lottery is set in the special symbol identification value setting area of ​​RAM230. In addition, "1" is added to the value of the ball entry counter for external information start slot. Furthermore, the special symbol identification value setting process determines whether or not it is the right-hand play period. If it is determined that it is not the right-hand play period (i.e., it is the left-hand play period), "1" is added to the value of the right-hand play error counter. In step S8-2, the pending counter address setting process is executed, and the process proceeds to step S8-3. In the pending counter address setting process, the address of the pending counter shown in Figure 2 is set in the pending counter address area of ​​RAM 230. In step S8-3, the process for obtaining special symbol random numbers is executed, and the series of processes ends, moving on to the next process (step S4-13). The process for obtaining special symbol random numbers will be described later.

[0232] (Special symbol random number acquisition process) Next, we will explain the process of obtaining special symbol random numbers in steps S7-3 and S8-3. Figure 18 is a flowchart showing the process for obtaining special symbol random numbers. When the special symbol random number acquisition process is executed in steps S7-3 and S8-3, the process first proceeds to step S9-1, as shown in Figure 18. In step S9-1, the special symbol identification value acquisition process is executed, and the process proceeds to step S9-2. In the special symbol identification value acquisition process, the special symbol identification value set in the special symbol identification value setting area of ​​RAM230 is acquired (loaded). In step S9-2, the special symbol hold count acquisition process is executed, and the process proceeds to step S9-3. In the special symbol hold count acquisition process, the value of the special symbol hold count counter (special symbol 1 hold count counter or special symbol 2 hold count counter), which is identified by the address set in the hold count counter address area, is acquired (loaded).

[0233] In step S9-3, the special symbol random number acquisition process is executed, and the process proceeds to step S9-4. In the special symbol random number acquisition process, various random numbers (random values) such as jackpot random numbers, winning symbol random numbers, reach group random numbers, reach mode random numbers, and variation pattern random numbers are acquired (loaded) from the loop counter corresponding to each lottery. At this time, the corresponding loop counter is selected based on the special symbol identification value acquired in step S9-1. In step S9-4, it is determined whether the number of special feature reserves (number of special feature 1 reserves or number of special feature 2 reserves) obtained in step S9-2 is at the upper limit (in this embodiment, "4"). If it is determined that the number of special feature reserves is not at the upper limit (No), the process proceeds to step S9-5. If it is determined that the number of special feature reserves is at the upper limit (Yes), the series of processes ends and the process proceeds to the next process (step S4-13 or S5-5). In step S9-5, the special feature hold count counter update process is executed, and the process proceeds to step S9-6. In the special feature hold count counter update process, the value set in the special feature hold count counter (special feature 1 hold count counter or special feature 2 hold count counter), which is identified by the address set in the hold count counter address area, is increased by "1", and this value is then set in the special feature hold count counter.

[0234] In step S9-6, the special symbol random number saving process is executed, and the process proceeds to step S9-7. In the special symbol random number saving process, the various random numbers obtained in step S9-3 are stored as special symbol game information (special symbol 1 game information or special symbol 2 game information) in the special symbol game information storage area (special symbol 1 game information storage area or special symbol 2 game information storage area) of RAM230. RAM230 is configured to include a memory area 0 where special feature game information is stored during gameplay, a special feature 1 game information storage area where special feature 1 game information for which the start determination is pending is stored, and a special feature 2 game information storage area for which the start determination is pending. The Special Feature 1 game information storage area is configured as a storage area capable of storing Special Feature 1 game information, and includes storage areas 1 to 4. The priority of each memory area is defined as follows, from highest priority to lowest: Memory Area 1, Memory Area 2, Memory Area 3, and Memory Area 4 (higher priority to lower priority). Then, the Special Feature 1 game information stored in the Special Feature 1 game information memory area is checked for activation in order from the memory area with the highest priority. The Special Feature 2 game information storage area is configured as a storage area capable of storing Special Feature 2 game information, and includes storage areas 1 to 4. The priority of each memory area is defined as follows, from highest priority to lowest: Memory Area 1, Memory Area 2, Memory Area 3, and Memory Area 4 (higher priority to lower priority). Then, the Special Feature 2 game information stored in the Special Feature 2 game information memory area is checked for activation in the order of the memory area with the highest priority.

[0235] In the special symbol random number saving process, if the special symbol identification value obtained in step S9-1 corresponds to the value for the first special symbol lottery, the various random numbers obtained in step S9-3 are stored as special symbol 1 game information in the special symbol 1 game information storage area. At this time, the various random numbers obtained in step S9-3 are stored in the storage area with the highest priority among the available storage areas. In other words, if the current value of the Special Feature 1 Reserved Count Counter is "1", the various random numbers obtained in step S9-3 are stored in memory area 1. If the current value of the Special Feature 1 Reserved Count Counter is "2", the various random numbers obtained in step S9-3 are stored in memory area 2. If the current value of the Special Feature 1 Reserved Count Counter is "3", the various random numbers obtained in step S9-3 are stored in memory area 3. If the current value of the Special Feature 1 Reserved Count Counter is "4", the various random numbers obtained in step S9-3 are stored in memory area 4. On the other hand, if the special symbol identification value obtained in step S9-1 corresponds to the value for the second special symbol lottery, the various random numbers obtained in step S9-3 are stored in the special symbol 2 game information storage area as special symbol 2 game information. At this time, the various random numbers obtained in step S9-3 are stored in the storage area with the highest priority among the available storage areas. In other words, if the current value of the Special Feature 2 Reserved Count Counter is "1", the various random numbers obtained in step S9-3 are stored in memory area 1. If the current value of the Special Feature 2 Reserved Count Counter is "2", the various random numbers obtained in step S9-3 are stored in memory area 2. If the current value of the Special Feature 2 Reserved Count Counter is "3", the various random numbers obtained in step S9-3 are stored in memory area 3. If the current value of the Special Feature 2 Reserved Count Counter is "4", the various random numbers obtained in step S9-3 are stored in memory area 4.

[0236] In step S9-7, the process for setting the number of reserved symbols command is executed, and the process proceeds to step S9-8. In the process for setting the number of reserved symbols command, a command specifying that the number of reserved symbols (number of reserved symbols 1 or 2) has increased by "1" is stored in the subcommand output request buffer of RAM230. At this time, if the special symbol identification value obtained in step S9-1 is the value corresponding to the 1st special symbol lottery, a command specifying that the number of reserved symbols 1 has increased by "1" is stored in the subcommand output request buffer of RAM230. If it is the value corresponding to the 2nd special symbol lottery, a command specifying that the number of reserved symbols 2 has increased by "1" is stored in the subcommand output request buffer of RAM230.

[0237] In step S9-8, a pre-determination process is executed, and the series of processes is completed, moving on to the next process (step S4-13 or S5-5). In the pre-determination process, various lottery results are pre-determined based on the game information (special feature 1 game information or special feature 2 game information) (hereinafter referred to as "pre-determination target game information") stored in the special feature game information storage area (special feature 1 game information storage area or special feature 2 game information storage area) in step S9-6. In this embodiment, pre-determination of various lottery results is performed for all game information (special figure 1 game information and special figure 2 game information). Furthermore, for game information acquired (stored) while a jackpot game state is occurring, the system may be configured so that pre-determining of various lottery results is not performed. Also, for special feature 2 game information acquired (stored) while the time-saving control is stopped, the system may be configured so that pre-determining of various lottery results is not performed, and for special feature 1 game information acquired (stored) while the time-saving control is running, the system may be configured so that pre-determining of various lottery results is not performed.

[0238] In the pre-determination process, the pre-special symbol hit determination process is performed first. In the pre-special symbol win determination process, the result of the special symbol lottery ("jackpot" or "miss") is determined (pre-special symbol win determination). ROM220 stores a special symbol win / loss lottery table in which the winning values ​​for special symbol lotteries are registered. In addition, the special symbol win / loss lottery table stores a special symbol win / loss lottery table corresponding to each combination of setting value ("1" to "6") and game state ("low special symbol state" or "high special symbol state"). Specifically, the special symbol win / loss lottery tables stored are: "Special symbol win / loss lottery table for setting value 1 low probability", "Special symbol win / loss lottery table for setting value 1 high probability", "Special symbol win / loss lottery table for setting value 2 low probability", "Special symbol win / loss lottery table for setting value 2 high probability", "Special symbol win / loss lottery table for setting value 3 low probability", "Special symbol win / loss lottery table for setting value 3 high probability", "Special symbol win / loss lottery table for setting value 4 low probability", "Special symbol win / loss lottery table for setting value 4 high probability", "Special symbol win / loss lottery table for setting value 5 low probability", "Special symbol win / loss lottery table for setting value 5 high probability", "Special symbol win / loss lottery table for setting value 6 low probability", and "Special symbol win / loss lottery table for setting value 6 high probability".

[0239] The "Special Symbol Win / Loss Lottery Table for Low Probability (Setting Value 0)" is selected when the setting value is "0" and "0" is set in the Special Symbol High Probability State Flag Area (meaning the "Special Symbol Low Probability State" is occurring). In the "Special Symbol Win / Loss Lottery Table for Low Probability (Setting Value 0)", the winning random numbers "0" to "204" from "0" to "65535" are registered as winning values. The "Special Symbol Win / Loss Lottery Table for High Probability Mode with Setting Value 0" is selected when the setting value is "0" and "1" is set in the Special Symbol High Probability State Flag Area (meaning the "Special Symbol High Probability State" is active). In the "Special Symbol Win / Loss Lottery Table for High Probability Mode with Setting Value 0," the winning random numbers "0" to "2039" from "0" to "65535" are registered as winning values. The "Setting Value 1 Low Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "1" and "0" is set in the special symbol high probability state flag area (meaning the "special symbol low probability state" is occurring). In the "Setting Value 1 Low Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "209" from "0" to "65535" are registered as winning values. The "Special Symbol Win / Loss Lottery Table during High Probability Setting 1" is selected when the setting value is "1" and "1" is set in the special symbol high probability state flag area (meaning the "special symbol high probability state" is active). In the "Special Symbol Win / Loss Lottery Table during High Probability Setting 1," the winning random numbers "0" to "2089" from "0" to "65535" are registered as winning values. The "Setting Value 2 Low Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "2" and "0" is set in the special symbol high probability state flag area (meaning the "special symbol low probability state" is occurring). In the "Setting Value 2 Low Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "214" from "0" to "65535" are registered as winning values. The "Setting Value 2 High Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "2" and "1" is set in the special symbol high probability state flag area (meaning the "special symbol high probability state" is active). In the "Setting Value 2 High Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "2139" from "0" to "65535" are registered as winning values.

[0240] The "Setting Value 3 Low Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "3" and "0" is set in the special symbol high probability state flag area (meaning the "special symbol low probability state" is occurring). In the "Setting Value 3 Low Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "219" from "0" to "65535" are registered as winning values. The "Setting Value 3 High Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "3" and "1" is set in the special symbol high probability state flag area (meaning the "special symbol high probability state" is active). In the "Setting Value 3 High Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "2189" from "0" to "65535" are registered as winning values. The "Setting Value 4 Low Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "4" and "0" is set in the special symbol high probability state flag area (meaning the "special symbol low probability state" is occurring). In the "Setting Value 4 Low Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "224" from "0" to "65535" are registered as winning values. The "Special Symbol Win / Loss Lottery Table during High Probability Setting 4" is selected when the setting value is "4" and "1" is set in the special symbol high probability state flag area (meaning the "special symbol high probability state" is active). In the "Special Symbol Win / Loss Lottery Table during High Probability Setting 4," the winning random numbers "0" to "2239" from "0" to "65535" are registered as winning values. The "Setting Value 5 Low Probability Special Symbol Win / Loss Lottery Table" is selected when the setting value is "5" and "0" is set in the special symbol high probability state flag area (meaning the "special symbol low probability state" is occurring). In the "Setting Value 5 Low Probability Special Symbol Win / Loss Lottery Table," the winning random numbers "0" to "229" from "0" to "65535" are registered as winning values. The "Special Symbol Win / Loss Lottery Table for High Probability Setting 5" is selected when the setting value is "5" and "1" is set in the special symbol high probability state flag area (meaning the "special symbol high probability state" is active). In the "Special Symbol Win / Loss Lottery Table for High Probability Setting 5," the winning random numbers "0" to "2289" from "0" to "65535" are registered as winning values.

[0241] In the pre-special symbol win determination process, the value set in the setting value area (setting value) and the current game state ("special symbol high probability state" or "special symbol low probability state") are checked, and the special symbol win / loss lottery table corresponding to this check result is read. Then, based on the jackpot random number included in the pre-determined game information and the read special symbol win / loss lottery table, the result of the special symbol lottery ("jackpot" or "miss") is determined (pre-special symbol win determination). Specifically, if the value of the jackpot random number included in the pre-determined game information matches the jackpot value registered in the special symbol win / loss lottery table that has been read out, the result of the special symbol lottery will be determined to be a "jackpot" (win). On...

Claims

1. An analysis means that performs analysis of sound control data at predetermined intervals, A playback means that reproduces an audio signal in response to instructions from the analysis means, The system comprises an amplification means for amplifying the sound signal reproduced by the aforementioned playback means, If the playback means is in the first abnormal state, the analysis of sound control data by the analysis means will not be performed. If the playback means is in a normal state or a second abnormal state, even if the amplification means is in an abnormal state, the analysis of sound control data by the analysis means continues. A gaming machine characterized in that the time it takes for the amplification means to recover from an abnormal state is longer than the predetermined time.

2. The gaming machine according to Claim 1, characterized in that it can recover from the second abnormal state upon the commencement of a new sound effect.

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