Back contact battery and method for manufacturing the same

Abstract

To provide a back contact battery relating to the technical field of solar power generation, capable of preventing a first doped semiconductor layer and a second doped semiconductor layer from becoming electrically conductive and shortening the movement distance of a part of carriers.SOLUTION: The back contact battery includes: a silicon substrate; and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed at intervals on a non-light-receiving surface side of the silicon substrate. On the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is a first region, and the region corresponding to the second doped semiconductor layer is a second region. The region located between the first region and the second region adjacent to the first region is a spacing region. The surface of the second region is recessed into the silicon substrate with respect to a surface of the first region. The surface of the spacing region is recessed into the silicon substrate with respect to the surface of the second region. Side surfaces of the first doped semiconductor layer and the second doped semiconductor layer that are close to the spacing region are both substantially wavy.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic power generation, and particularly to a back contact battery and a method for manufacturing the same. It relates to.

Background Art

[0002] A back contact battery is a solar cell in which there are no electrodes on the light-receiving surface of the battery cell, and both the positive electrode and the negative electrode are provided on the non-light-receiving surface side of the battery cell. Thereby, the shielding of the battery cell by the electrodes is reduced, the short-circuit current of the battery cell is increased, and the energy conversion efficiency of the battery cell can be increased. Moreover, by forming a surface passivation layer on the non-light-receiving surface side of the back contact battery, the carrier recombination rate on the non-light-receiving surface side of the back contact battery can be reduced, and the photoelectric conversion efficiency of the back contact battery can be improved. However, in conventional back contact batteries, the carrier collection efficiency is low, which is disadvantageous for improving the operating performance of the back contact battery.

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Summary of the Invention

[0004] An object of the present invention is to provide a back contact battery and a method for manufacturing the same, which are advantageous for improving the operating performance of the back contact battery, by shortening the movement distance of some carriers and increasing the carrier collection efficiency in a state where the first doped semiconductor layer and the second doped semiconductor layer are prevented from conducting.

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[0022] [[A back contact battery is provided, which includes a body layer. Herein, a first doped semiconductor layer and a second doped semiconductor layer are provided. The first doped semiconductor layer has the opposite conductivity type. On the non-photosensitive surface of the silicon substrate, the first doped semiconductor The region corresponding to the layer is the first region, and the region corresponding to the second doped semiconductor layer is the second region. Furthermore, the region located between the first region and the second region adjacent to it is the interval region. The surface of the region is recessed into the silicon substrate relative to the surface of the first region. The surface of the spacing region is second The region is recessed into the silicon substrate relative to the surface of the region, and the surface of the spacing region is the surface of the first region. In contrast, the depth of the indentation into the silicon substrate is less than 3000 nm.

[0006] When the above technical solution is used, the back contact battery provided by the present invention is The first and second doped semiconductor layers, which have opposite conductivity types, are located on the non-photosensitive side of the silicon substrate. They are distributed alternately at intervals. Based on this, the intervals on the non-light-receiving surface of the silicon substrate The separation region isolates the first doped semiconductor layer and the second doped semiconductor layer, and the first doped semiconductor Reducing the carrier recombination rate at the lateral boundary between the body layer and the second doped semiconductor layer is possible. This is advantageous for improving the photoelectric conversion efficiency of back-contact batteries. Next, the first doped semiconductor A layer is formed in the first region of the non-photosensitive surface, and a second doped semiconductor layer is formed in the second region of the non-photosensitive surface. Therefore, the surface of the second region is recessed into the silicon substrate relative to the surface of the first region, and If the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, actual manufacturing In the process, after selectively etching the first doped semiconductor layer that covers the entire non-light-receiving surface, The portions located in the second region and the spacing region of the first doped semiconductor layer are completely removed. Furthermore, it is clear that the silicon substrate is also partially etched to a certain thickness, and the second It is ensured that the first doped semiconductor layer does not remain in the region and the spacing region, thereby preventing short circuits. Furthermore, both are located on the non-light-receiving side of the silicon substrate and have opposite conductivity types. The body layer and the second doped semiconductor layer are offset at least partially in the thickness direction of the silicon substrate. This is also advantageous, as the risk of leakage current on the non-light-receiving side is further reduced, and the power of the back contact battery Aerodynamic reliability is improved. Similarly, the surface of the spacing region is within the silicon substrate relative to the surface of the second region. If it is recessed, in the actual manufacturing process, the first doped semiconductor layer, the second region and the spacing region After selectively etching the second doped semiconductor layer deposited in the region, the second doped semiconductor layer Not only are the portions located in the first doped semiconductor layer and the spacing region completely removed, but the silicon It is clear that the areas corresponding to the spacing regions of the substrate are also etched to a certain thickness. It is ensured that the second doped semiconductor layer does not remain in the first doped semiconductor layer and the spacing region. This prevents short circuits.

[0007] Furthermore, as can be seen from the above, on the non-light-receiving surface of the silicon substrate, the silicon in the spacing region The depth of the indentation into the substrate is greatest, and the spacing region is within the silicon substrate relative to the surface of the first region. The depth of the indentation is less than 3000 nm. Based on this, the spacing region in the conventional technology The case where the recess depth into the silicon substrate is 5 μm is more efficient than the case where the bag provided by the present invention In contact batteries, the depth of the recess in the silicon substrate of the spacing region is small, and in this case, The corresponding conductive carriers do not bypass the deep spacing region, but instead proceed through the first doped semiconductor It can be collected by a body layer or a second doped semiconductor layer, thereby collecting some carriers. The movement distance can be shortened, and the carrier collection efficiency can be improved, which is beneficial to the performance improvement of the back contact battery. It is beneficial to the performance improvement.

[0008] As a possible implementation form, the surface of the interval region is a plane. In this case, the surface of the interval region is relatively flat. Based on this, when the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed in the interval region with a flat surface is larger, the passivation effect of the surface passivation layer on the interval region is enhanced, the carrier recombination rate on the surface of the interval region can be reduced, which is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery. The surface is relatively flat. Based on this, when the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed in the interval region with a flat surface is larger, the passivation effect of the surface passivation layer on the interval region is enhanced, the carrier recombination rate on the surface of the interval region can be reduced, which is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery. If the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed in the interval region with a flat surface is larger, the passivation effect of the surface passivation layer on the interval region is enhanced, the carrier recombination rate on the surface of the interval region can be reduced, which is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery. If the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed in the interval region with a flat surface is larger, the passivation effect of the surface passivation layer on the interval region is enhanced, the carrier recombination rate on the surface of the interval region can be reduced, which is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery. The passivation effect of the surface passivation layer on the interval region can be enhanced, and the carrier recombination rate on the surface of the interval region can be reduced, which is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery. It is beneficial to the improvement of the photoelectric conversion efficiency of the back contact battery.

[0009] As a possible implementation form, the roughness within a range of per 10,000 square micrometers on the surface of the interval region is 30 μm or less. The beneficial effect in this case is similar to the beneficial effect when the surface of the interval region is a plane, and the description here is omitted. The beneficial effect in this case is similar to the beneficial effect when the surface of the interval region is a plane, and the description here is omitted. The beneficial effect in this case is similar to the beneficial effect when the surface of the interval region is a plane, and the description here is omitted.

[0010] As a possible implementation form, in the arrangement direction of the first region and the second region, the length of the interval region is 20 μm or more and 110 μm or less. μm or more and 110 μm or less.

[0011] When the above technical solution is used, the length of the interval region is within the above range. The small interval prevents leakage from occurring between the first doped semiconductor layer and the second doped semiconductor layer, and high electrical reliability of the back contact battery can be ensured. Also, the large interval reduces the formation range on the non-light-receiving surface side of the first doped semiconductor layer and / or the second doped semiconductor layer, and the carriers on the non-light-receiving surface side are less likely to enter the first doped semiconductor layer and / or the second doped semiconductor layer. The small interval prevents leakage from occurring between the first doped semiconductor layer and the second doped semiconductor layer, and high electrical reliability of the back contact battery can be ensured. The small interval prevents leakage from occurring between the first doped semiconductor layer and the second doped semiconductor layer, and high electrical reliability of the back contact battery can be ensured. Also, the large interval reduces the formation range on the non-light-receiving surface side of the first doped semiconductor layer and / or the second doped semiconductor layer. The large interval reduces the formation range on the non-light-receiving surface side of the first doped semiconductor layer and / or the second doped semiconductor layer. The carriers on the non-light-receiving surface side are less likely to enter the first doped semiconductor layer and / or the second doped semiconductor layer. This prevents the inability to collect data in a timely manner due to the layered semiconductor, and prevents the data from being extracted from the corresponding electrode. It is also possible to further reduce the carrier recombination rate on the non-photosensitive side.

[0012] One possible implementation is that the surface of the second region is planar. In this case, the surface of the second region The surface is relatively flat, which is advantageous for improving the formation quality of the second doped semiconductor layer formed in the second region. Furthermore, the surface of the second doped semiconductor layer formed in the second region and the surface of the second region are undulating. Because the degree is similar, if the surface of the second region is planar, the silicon of the second doped semiconductor layer This is also advantageous for improving the surface flatness on the side away from the substrate. Based on this, back contact electric If the pond also contains a surface passivation layer, the surface passivation layer is more effective than the texture. The thickness of the portion of the doped semiconductor layer formed on the second doped semiconductor layer, which has high surface flatness, is greater. Furthermore, the surface passivation layer on the side of the second doped semiconductor layer away from the silicon substrate Enhancing the passivation effect and the carrier recombination speed on the non-photosensitive side of the back contact battery. This can further reduce the value, which is advantageous for improving the photoelectric conversion efficiency of back-contact batteries. .

[0013] As one possible implementation, the recess depth of the surface of the second region into the silicon substrate is 100 It is greater than or equal to 1000 nm and less than or equal to 1000 nm.

[0014] When the above technical solution is used, the depth of the indentation of the surface of the second region into the silicon substrate is Within the specified range, and due to the small depth of the indentation of the surface of the second region into the silicon substrate, A first doped semiconductor layer and a second doped semiconductor layer are located on the non-light-receiving side of the silicon substrate and have opposite conductivity types. - Prevents the degree of displacement of the semiconductor layer in the silicon substrate thickness direction from becoming small, and the non-light-receiving side This can further reduce the risk of electrical leakage. Also, the spacing region is silicate to the second region. Because it is recessed into the silicon substrate, that is, the depth of the recess in the spacing region into the silicon substrate is greater than the second region. Because the size is also large, if the depth of the indentation of the surface of the second region into the silicon substrate is within the above range, Due to the large depth of the indentation of the surface of the second region into the silicon substrate, the silicon in the spacing region This prevents the indentation depth within the substrate from becoming larger and bypasses the spacing region to the first doped semiconductor. Ensure that the travel distance of some carriers transported to the layer or the second doped semiconductor layer is small. Furthermore, the depth of the indentation into the silicon substrate in the second region and the spacing region is large. This also prevents the need to use thicker silicon substrates, and furthermore, This will reduce the manufacturing cost of back contact batteries, and also reduce the manufacturing cost of back contact batteries This is advantageous for realizing sheet-type production.

[0015] As one possible implementation, the height difference between the surface of the second region and the surface of the spacing region is 30 It is greater than or equal to 0 nm and less than 2000 nm.

[0016] When the above technical solution is used, the height difference between the surface of the second region and the surface of the spacing region is Within the above range, and due to the small height difference, the second dope half in the actual manufacturing process After completely removing the portion located in the gap region of the conductor layer, the etching time is strictly controlled. If this is not possible, the etching depth of the etching agent in the gap region of the silicon substrate cannot be reduced. This prevents the problem and reduces the difficulty of etching. This prevents the travel distance of the corresponding conductive carrier from decreasing significantly, and the carrier This also ensures the possibility of improving collection efficiency.

[0017] One possible implementation is the spacing region between the first doped semiconductor layer and the second doped semiconductor layer. The sides that are close to the second doped semiconductor layer are all almost wavy. The corresponding variation range of the surface is greater than the corresponding variation range of the side surface near the spacing region of the first doped semiconductor layer. Larger and / or, the corresponding fluctuation frequency on the side close to the spacing region of the second doped semiconductor layer is The frequency of variation is smaller than that of the corresponding fluctuations on the sides near the spacing region of the single-doped semiconductor layer.

[0018] When the above technical solution is used, the spacing between the first doped semiconductor layer and the second doped semiconductor layer When the sides close to the region are all roughly wavy, the sides close to the spacing region of the second doped semiconductor layer The corresponding variation range is greater than the corresponding variation range on the side closer to the spacing region of the first doped semiconductor layer. In short, the roughness of the local region on the side surface close to the spacing region of the second doped semiconductor layer is greater than that of the first doped semiconductor layer. The roughness of the formed second doped semiconductor layer is smaller than the roughness of the local region on the side near the interlayer spacing region. This reduces the number of defects in the region close to the spacing region of the second doped semiconductor layer, and further reduces the number of defects in the region close to the spacing region of the second doped semiconductor layer. This is advantageous for reducing the partial carrier recombination rate and the operability of back contact batteries. Noh will improve even further.

[0019] As one possible implementation, the side wall of the above-mentioned spacing region crosses at least a portion of the spacing region. At least a portion of the surface is water-resistant so that the area gradually increases from the light-receiving surface to the non-light-receiving surface. It is positioned at an angle to the plane.

[0020] When the above technical solution is used, the cross-sectional area on the light-receiving surface side of the spacing region is the same as the cross-sectional area on the non-light-receiving surface side. The cross-sectional area is smaller than that of the first doped semiconductor layer and the second doped semiconductor layer which has the opposite conductivity type to the first doped semiconductor layer itself. This is advantageous for increasing the gap with the body layer, and reduces leakage current on the non-light-receiving side of the back contact battery. The noise is reduced, and the high electrical reliability of the back contact battery is ensured. The portion of the side wall of the region that is positioned at an angle to the horizontal plane is also advantageous for reflecting light rays. Furthermore, in areas where more rays are positioned at an angle to the horizontal plane on the side walls of the spacing region. Under the reflective effect, it is advantageous for the back contact battery to enter the silicon substrate from the non-light-receiving side. Furthermore, it is advantageous for improving the photoelectric conversion efficiency of back-contact batteries.

[0021] As one possible implementation, the above back contact battery comprises a first doped semiconductor layer, a second doped semiconductor layer, and The system further includes a surface passivation layer covering the rib semiconductor layer and the gap region.

[0022] When the above technical solution is used, the surface passivation layer is a back contact battery Passivating the non-photosensitive side reduces the carrier recombination rate on the non-photosensitive side. This is possible. Also, the spacing region with the greatest recess depth into the silicon substrate is the corresponding recess. Because the depth is less than 3000 nm, the reaction of each region on the non-light-receiving side of the back contact battery This is advantageous in reducing the degree of insufficiency, and the formation thickness on the non-light-receiving side of the surface passivation layer is This increases the passivation effect on the non-light-receiving side of the surface passivation layer. It is advantageous for that.

[0023] As one possible implementation, the above back contact battery has a first region of the silicon substrate It further includes a first passivation layer located between the region and the first doped semiconductor layer.

[0024] When the above technical solution is used, the first passivation layer and the first doped semiconductor layer are selected A selective contact structure is formed to chemically pack a first region of the non-photosensitive surface of the silicon substrate. To achieve sivation and selective collection of corresponding conductive carriers, This can reduce the carrier recombination rate on the light-receiving surface, and the photoelectric transformation of the back contact battery. This is advantageous for improving conversion efficiency.

[0025] As one possible implementation, the above back contact battery has a second region of the silicon substrate It further includes a second passivation layer located between the region and the second doped semiconductor layer.

[0026] When using the above technical solution, the second passivation layer and the second doped semiconductor layer are selected A selective contact structure is formed to chemically pack a second region of the non-photosensitive surface of the silicon substrate. To achieve sivation and selective collection of corresponding conductive carriers, This can reduce the carrier recombination rate on the light-receiving surface, and the photoelectric transformation of the back contact battery. This is advantageous for improving conversion efficiency.

[0027] One possible implementation is that the back contact battery includes a first passivation layer, and If the first passivation layer is a tunnel passivation layer, then the first doped semiconductor The layer is a doped polycrystalline silicon layer.

[0028] One possible implementation is that the back contact battery includes a second passivation layer, and If the second passivation layer is a tunnel passivation layer, the second doped semiconductor The layer is a doped polycrystalline silicon layer.

[0029] In a second aspect, the present invention is a step of preparing a silicon substrate, the silicon substrate The non-light-receiving surface has a first region and a second region distributed alternately at intervals, and the first region and A step having an interval region located between itself and a second region adjacent to it, and a first region having A doped semiconductor layer is formed, and both the surface of the spacing region and the second region are treated with respect to the surface of the first region. The steps are to create a depression in the silicon substrate and to form a second doped semiconductor layer in the second region, and then space The surface of the region is recessed into the silicon substrate relative to the surface of the second region, and the surface of the spacing region is Steps that make the depth of the recess into the silicon substrate less than 3000 nm relative to the surface of one region. The present invention provides a method for manufacturing a back contact battery, including a push mechanism.

[0030] As one possible implementation, after the above step of preparing a silicon substrate, the second region is Before forming the 2-doped semiconductor layer, the manufacturing method of the back contact battery involves the silicon substrate A first doped semiconductor layer provided throughout the entire surface of the non-light-receiving surface, and a first region of the first doped semiconductor layer. The steps include forming a first mask layer located in the corresponding portion and creating a mask of the first mask layer. Under the conditions, portions located in the spacing region and the second region of the first doped semiconductor layer are selectively removed. Then, both the surface of the spacing region and the second region are moved into the silicon substrate relative to the surface of the first region. This includes the step of creating a recess.

[0031] As one possible implementation, the material of the first doped semiconductor layer contains silicon. A first doped semiconductor layer is provided throughout the entire surface of the non-light-receiving surface of the recon substrate, and the first doped semiconductor The above step of forming a first mask layer located in the portion corresponding to the first region of the layer is performed by Silico The steps include forming a first intrinsic semiconductor layer on the non-light-receiving surface of the substrate, and forming a first intrinsic semiconductor layer that is provided in the entire layer. The intrinsic semiconductor layer is doped to form the first intrinsic semiconductor layer as the first doped semiconductor layer, and A first doped silicate glass layer is formed on the first doped semiconductor layer, with the entire layer being provided. Steps and laser etching process to create spacing between the first doped silicate glass layers The regions corresponding to the first and second regions are heat-treated to perform heat treatment on the first doped silicate glass layer. The steps include forming the unprocessed portion as the first mask layer and the first doped silicate glass. The process includes the step of removing the portion of the layer that has undergone heat treatment.

[0032] When the above technical solution is used, if the material of the first doped semiconductor layer contains silicon, The material for the first intrinsic semiconductor layer used to manufacture the 1-doped semiconductor layer also contains silicon. Furthermore, after doping the first intrinsic semiconductor layer, a first doped semiconductor layer can be obtained. Furthermore, the first doped silicate glass layer, which is provided in all layers on the first doped semiconductor layer, It can also be formed. Subsequently, by a laser etching process, the first doped silicate A portion of the doped glass layer is heat-treated. In this case, the laser in the first doped silicate glass layer The treated area becomes less dense and easier to remove. On the other hand, the first doped silicate The untreated areas within the glass layer are highly dense and difficult to remove, As a result, after heat treatment, different parts of the first doped silicate glass layer undergo different etching. A first mask layer is obtained that has a selectivity ratio and is used for patterning the first doped semiconductor layer. To obtain the first mask layer described above, additional mask material is formed, and other mask deposition is performed. It eliminates the need to form a process, reduces the manufacturing cost of back contact batteries, and also reduces back contact This is advantageous for simplifying the manufacturing flow of contactless batteries.

[0033] As one possible implementation, by a wet chemical process, under the masking action of the first mask layer, The portions located in the spacing region and the second region of the first doped semiconductor layer are selectively removed, and the interval Both the surface of the separating region and the surface of the second region are recessed into the silicon substrate relative to the surface of the first region. Here, the process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or, the process time of the wet chemical process is 40 s or more and 200 s or less, and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution. The etching solution, and the volume of the alkaline component in an alkaline wet chemical etching solution. The ratio is 2% or more and 20% or less, and / or is used in wet chemical processes. A chemical etching solution containing an abrasive additive, and a wet chemical etching solution of the abrasive additive. The volume ratio inside is 0.5% or more and 5% or less.

[0034] When the above technical solution is used, the process temperature and process time of the wet chemical process In both cases, the surfaces of the spacing region and the second region are treated by a wet chemical process, and the first region This affects the depth of the indentation created within the silicon substrate relative to the surface. Based on this, wet chemistry If the process temperature is within the above range, the low process temperature will result in a short interval. Both the surface of the first region and the surface of the second region are recessed into the silicon substrate relative to the surface of the first region. This prevents the depth from becoming too small. Also, the high process temperature The surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region. It is also possible to prevent the depth in which it is located from increasing. After this operation, the spacing area and the second The depth to which the surface of the region is recessed into the silicon substrate relative to the surface of the first region is the same for all of them. In the back contact battery, the surface of the second region is silicon relative to the surface of the first region. This is equal to the depth of the recess into the substrate. Here, the surface of the second region is equal to the surface of the first region. To prevent the depth of the indentation within the silicon substrate from increasing or decreasing. For the beneficial effects, please refer to the preceding paragraph. Next, the process time and the volume of alkaline components. The beneficial effect of the ratio being within the above range is that the process temperature is 60°C or higher, and 80°C. The beneficial effects are similar to those described below, and will not be explained here. Also, wet chemical processes When the volume ratio of polishing additives in the polishing solution is within the above range, the spacing region and after the operation The planarity of the two regions is increased, and the surface passivation to the spacing region and the second doped semiconductor layer is improved. This can further enhance the passivation effect of the cushioning layer.

[0035] As one possible implementation, the surfaces of both the spacing region and the second region are positioned relative to the surface of the first region. After the above step of creating a depression in the silicon substrate, the method for manufacturing a back contact battery is A first doped semiconductor layer, a second doped semiconductor layer is deposited in the spacing region and the second region, and then the The steps include forming a second mask layer in the portion corresponding to the second region of the 2-doped semiconductor layer, and the second Under the masking effect of the mask layer, the portion corresponding to the first region and the spacing region of the second doped semiconductor layer This selectively removes the material and creates a recess in the silicon substrate relative to the surface of the second region. This includes the step of getting used to it.

[0036] As one possible implementation, the material of the second doped semiconductor layer contains silicon. A doped semiconductor layer, a second doped semiconductor layer is deposited in the gap region and the second region, and then the second doped The above step of forming a second mask layer in the portion corresponding to the second region of the semiconductor layer is performed in the first step The steps include depositing a second intrinsic semiconductor layer in a first semiconductor layer, a spacing region, and a second intrinsic semiconductor layer in a second region, and depositing a second intrinsic semiconductor layer in a second intrinsic semiconductor layer A semiconductor layer is doped to form a second intrinsic semiconductor layer as a second doped semiconductor layer, and A second doped silicate glass layer is formed on the second doped semiconductor layer, with the second doped silicate glass layer covering the entire layer. The first region of the second doped silicate glass layer is removed by the TEPP and laser etching process. The portion corresponding to the spacing region is heat-treated to form the second region of the second doped silicate glass layer. Steps include forming the corresponding portion as a second mask layer and forming a second doped silicate glass layer. The process includes the step of removing the heat-treated portion.

[0037] When the above technical solution is used, if the material of the second doped semiconductor layer contains silicon, The material for the second intrinsic semiconductor layer used to manufacture the 2-doped semiconductor layer also contains silicon. Furthermore, after doping the second intrinsic semiconductor layer, a second doped semiconductor layer can be obtained. Furthermore, the second doped silicate glass layer, which is provided throughout the entire layer, is placed on the second doped semiconductor layer. It can also be formed. Subsequently, by a laser etching process, the second doped silicate The portion of the glass layer corresponding to the first region and the spacing region is heat-treated. In this case, the second doping The laser-treated areas in the silicate glass layer have lower density and are easier to remove. Yes. On the other hand, the portion of the second region of the second doped silicate glass layer corresponding to the second region is laser-treated. Because it is not made, it has high density and is difficult to remove, and as a result, after heat treatment, the second stage Different parts of the doped silicate glass layer have different etching selectivity ratios, and the second doped semiconductor A second mask layer is obtained for patterning the body layer, and in order to obtain the above second mask layer There is no need to additionally form other mask materials or to perform other mask deposition processes. To reduce the manufacturing cost of back contact batteries and simplify the manufacturing flow of back contact batteries. It is advantageous for abbreviation.

[0038] One possible implementation is by a wet chemical process, under the masking action of the second mask layer. The portion corresponding to the first region and the spacing region of the second doped semiconductor layer is selectively removed, and the interval The surface of the separating region is recessed into the silicon substrate relative to the surface of the second region. Here, wet chemical process The process temperature of the process is 60°C or higher and 80°C or lower, and / or wet chemical process The process time for the process is 50 seconds or more and 300 seconds or less, and / or a wet chemical process. The wet chemical etching solution used in Seth is an alkaline wet chemical etching solution. Furthermore, the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or more, and 2 It is 0% or less, and / or in wet chemical etching solutions used in wet chemical processes. The solution contains polishing additives, and the volume ratio of the polishing additives in the wet chemical etching solution is 0.5%. The above, and less than 5%.

[0039] When the above technical solution is used, the process temperature and process time of the wet chemical process In both cases, the surface of the spacing region is treated with silica by a wet chemical process relative to the surface of the second region. This affects the depth of the indentation within the substrate. Based on this, the process temperature of the wet chemical process is determined. When the degree is within the above range, the process temperature is low, and the second region of the surface of the spacing region This prevents the depth of the recess into the silicon substrate relative to the surface of the region from becoming smaller. It is possible. Also, due to the high process temperature, the surface of the spacing region is compared to the surface of the second region. This also prevents the depth of the indentation in the silicon substrate from increasing. The depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region is small. For the beneficial effects of preventing it from becoming or growing larger, please refer to the preceding paragraph. Next, the beneficial effects of the process time and the volume ratio of alkaline components being within the above range. The effect is similar to the beneficial effect of having a process temperature of 60°C or higher and 80°C or lower. The explanation will be omitted here. Also, the volume ratio of polishing additives in the wet chemical etching solution is If within the specified range, the flatness of the surface of the spacing region after the operation is increased, and the surface packing of the spacing region is improved. This can further enhance the passivation effect of the sivation layer.

[0040] One possible implementation is to prepare a silicon substrate and then apply a first doped semiconductor to the first region. Before forming the layer, the manufacturing method of the back contact battery involves first passivation in the first region The process further includes the step of forming a layer.

[0041] As one possible implementation, the surfaces of both the spacing region and the second region are positioned relative to the surface of the first region. After creating a depression in the silicon substrate, before forming the second doped semiconductor layer in the second region... The manufacturing method for a back contact battery involves forming a second passivation layer in the second region. Includes further steps.

[0042] One possible implementation is to insert the surface of the spacing region into the silicon substrate relative to the surface of the second region. After indentation, the manufacturing method of the back contact battery is: first doped semiconductor layer, second doped semiconductor layer The process further includes the step of forming a surface passivation layer that covers the conductor layer and the spacing region.

[0043] The beneficial effects of the second aspect of the present invention and its various embodiments are described in relation to the first aspect and its embodiments. For an analysis of the beneficial effects in various embodiments, please refer to the provided documentation; a detailed explanation is omitted here. do. [Brief explanation of the drawing]

[0044] The drawings described herein are intended to further illustrate the present invention and to represent a part of the present invention. Therefore, the exemplary embodiments and descriptions of the present invention are for interpretation purposes only, and this invention is interpreted accordingly. There is no intention to inappropriately limit the invention. A description of the drawings is provided below. [Figure 1] This is a longitudinal cross-sectional SEM diagram of the structure of a back-contact battery in related technologies. [Figure 2] This is a schematic longitudinal cross-sectional view of the structure of a back contact battery provided by an embodiment of the present invention. [Figure 3] This is an SEM diagram (part 1) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 4] This is an SEM diagram (part 2) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 5] This is an SEM diagram (part 3) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 6] This is an SEM diagram (part 4) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 7] This is an SEM diagram (part 5) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 8] This is a schematic diagram (part 1) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 9] This is a schematic diagram (part 2) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 10] This is a schematic diagram (part 3) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 11] This is a schematic diagram (part 4) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 12] This is a schematic diagram (5) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 13] This is a schematic diagram (6) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 14] This is a schematic diagram (7) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 15] This is a schematic diagram (part 8) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 16] This is a schematic diagram (9) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 17] This is a schematic diagram (10) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 18] This is a schematic diagram (No. 11) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 19] This is a schematic diagram (No. 12) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 20] This is a schematic diagram (No. 13) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 21]This is a schematic diagram (No. 14) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Modes for carrying out the invention]

[0045] Embodiments of the present disclosure will be described below with reference to the drawings. However, these descriptions are illustrative. It should be understood that this is merely illustrative and does not limit the scope of this disclosure. In the following explanation, to avoid unnecessary confusion with the concepts of this disclosure, we will refer to known structures and technologies. I will omit the explanation for this.

[0046] The drawings show various schematic diagrams of structures according to embodiments of the present disclosure. These diagrams are proportional It is not depicted in this way, but rather, in order to clearly express it here, some details are enlarged. Therefore, some details may be omitted. The shapes of the various regions and layers shown in the diagram. The relative sizes and positional relationships between them are illustrative only and do not reflect actual manufacturing tolerances. There may be variations due to technical limitations, and a person skilled in the art would know the actual requirements. Depending on the requirements, regions / layers with different shapes, sizes, and relative positions can be designed separately. .

[0047] In the context of this disclosure, when describing one layer / element as being located "on top of" another layer / element This layer / element may be located directly on top of this other layer / element, or an intermediate layer may be placed between them. / Elements may exist. Also, in a certain orientation, one layer / element may be positioned "on top" of another layer / element. If placed in a certain position, changing its orientation will cause that layer / element to be positioned "below" another layer / element. This makes it possible. The technical problems, technical solutions, and beneficial effects that this invention aims to solve can be further enhanced. To clarify, the present invention will be described in more detail below, combining drawings and embodiments. The specific examples described herein are for interpretation purposes only and do not necessarily reflect the present invention. It should be understood that this is not intended to limit the scope of the invention.

[0048] Furthermore, the terms "first" and "second" are merely descriptive and indicate relative importance. It should not be understood as implying or suggesting the quantity of the technical features being described. Therefore, it is clear that the features designated as "first" and "second" include one or more such features. It may be indicated or implied. In the description of the present invention, unless explicitly and specifically limited, "Multiple" means two or more. Unless clearly and specifically defined, "a few" means one. It means one or more.

[0049] In describing this invention, unless explicitly defined or limited, the terminology used is " The terms "to attach," "to connect," and "to link" should be understood in a broad sense, for example, fixing They may be connected directly, detachably, or integrally. The connection may be mechanical, electrical, direct, or even through an intermediate medium. They may be connected indirectly via, and the internal communication between the two elements or the interaction between the two elements It may be related. Those skilled in the art will know the specific meaning of the above terms in this invention depending on the specific situation. It allows one to understand the nuanced meaning.

[0050] Currently, solar cells are being used in a wide range of applications as a new alternative energy source. Among these, photovoltaic solar cells are devices that convert the sun's light energy into electrical energy. Specifically, solar cells generate carriers using the principle of photovoltaic energy, and then transfer them to electrodes. This allows for the extraction of more carriers, and thus is advantageous for the efficient use of electrical energy.

[0051] Here, both the positive and negative electrodes in the solar cell are located on the non-light-receiving surface of the solar cell. The solar cell is a back-contact cell. The light-receiving surface of the back-contact cell is metal. Because it is not affected by shielding by electrodes, back contact batteries have a thicker light-receiving surface that is shielded. Compared to solar cells, they have higher short-circuit current and photoelectric conversion efficiency, and are currently used to realize high-efficiency crystalline silicon batteries. This is one of the technological trends. Specifically, as shown in Figure 1, conventional back contact The battery is typically arranged with alternating spacing between the silicon substrate 11 and the non-light-receiving side of the silicon substrate 11. It includes a first doped semiconductor layer 12 and a second doped semiconductor layer 13 that are distributed in a certain manner. The semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types.

[0052] In the actual manufacturing process, typically, a first doped semiconductor layer is provided throughout the entire layer on the non-light-receiving side. This forms a layer, and then selectively etches the first doped semiconductor layer to a portion of the non-photosensitive surface. Only the first doped semiconductor layer located therein is retained. Subsequently, the first doped semiconductor layer and the non-photosensitive layer are retained. A second doped semiconductor layer is formed on the portion of the surface exposed to the first doped semiconductor layer, and then the A first-doped semiconductor layer and a second-doped semiconductor layer are alternately spaced apart on the non-light-receiving surface of the silicon substrate. The second doped semiconductor layer is selectively etched to achieve a distributed pattern.

[0053] However, as shown in Figure 1, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 Because the conductivity types are opposite, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 conduct electricity. In order to prevent short circuits, conventional manufacturing methods use wet chemical etching, etc. A gap region 16 with a certain width is formed between them. However, conventional back contact batteries Next, the spacing region 16 located between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 Because the depth of the indentation into the silicon substrate 11 is large (for example, greater than 5 μm), If the carriers within the substrate 11 do not bypass the deep spacing region, each will be in the first doped half The conductor layer 12 and the second doped semiconductor layer 13 prevent the carriers from being collected, and the carrier migration distance This process is lengthy, further reducing carrier collection efficiency, and increasing the carrier recombination rate. This is detrimental to improving the operating performance of contact lenses.

[0054] To solve the above technical problems, in the first aspect, embodiments of the present invention are back contact A battery is provided. As shown in Figure 2, a back contact provided by an embodiment of the present invention. The battery is divided alternately at intervals on the silicon substrate 11 and the non-light-receiving side of the silicon substrate 11. It includes a first doped semiconductor layer 12 and a second doped semiconductor layer 13. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. On the light-receiving surface, the region corresponding to the first doped semiconductor layer 12 is the first region 14, and the second do The region corresponding to the first semiconductor layer 13 is the second region 15, which is adjacent to the first region 14 itself. The region located between the second region 15 and the first region is the intervening region 16. The surface of the second region 15 is the first region The surface of region 14 is recessed into the silicon substrate 11. The surface of the spacing region 16 is the second region It is recessed into the silicon substrate 11 relative to the surface of region 15, and relative to the surface of the first region 14. The depth of the indentation into the silicon substrate 11 is less than 3000 nm.

[0055] When the above technical solution is used, as shown in Figure 2, the embodiment of the present invention is provided. In a back-contact battery, the first doped semiconductor layer 12 and the second doped semiconductor layer have opposite conductivity types. The body layer 13 is distributed alternately at intervals on the non-light-receiving side of the silicon substrate 11. Furthermore, the gap region 16 of the non-light-receiving surface of the silicon substrate 11 is the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are isolated, and the first doped semiconductor layer 12 and the second doped semiconductor The carrier recombination rate at the lateral boundary of layer 13 can be reduced, and the back contour This is advantageous for improving the photoelectric conversion efficiency of the CT battery. Next, the first doped semiconductor layer 12 is on the non-light-receiving surface A first region 14 is formed, and a second doped semiconductor layer 13 is formed in the second region 15, which is a non-photosensitive surface. Therefore, the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14. Furthermore, the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15. In this case, during the actual manufacturing process, the first doped semiconductor layer 12 covers the entire non-light-receiving surface. After selective etching, the second region 15 and the spacing region 16 of the first doped semiconductor layer 12 Not only is the portion located there completely removed, but the silicon substrate 11 is also partially removed to a certain thickness. It is clear that etching occurs, and the first doped area is applied to the second region 15 and the spacing region 16. It is ensured that the conductive layer 12 does not remain, preventing short circuits, and both are silicon substrates. A first doped semiconductor layer 12 and a second doped semiconductor layer 11 are located on the non-light-receiving side and have opposite conductivity types. It is also advantageous to offset the conductive layer 13 at least partially in the thickness direction of the silicon substrate 11. Yes, the risk of leakage current on the non-light-receiving side is further reduced, and the electrical reliability of the back contact battery is improved. The pressure increases. Similarly, the surface of the spacing region 16 is relative to the surface of the second region 15 on the silicon substrate 11. If it is concave inward, in the actual manufacturing process, the first doped semiconductor layer 12, the second region 15 And after selectively etching the second doped semiconductor layer 13 deposited in the spacing region 16, The portion of the 2-doped semiconductor layer 13 located in the first doped semiconductor layer 12 and the spacing region 16 is complete Not only is it removed, but the portion corresponding to the spacing region 16 of the silicon substrate 11 is also removed to a certain thickness. It is clear that etching occurs, and the first doped semiconductor layer 12 and the spacing region 16 It is ensured that no doped semiconductor layer 13 remains, thereby preventing short circuits. As can be seen, on the non-light-receiving surface of the silicon substrate 11, the silicon substrate of the spacing region 16 The depth of the indentation in 11 is greatest, and the spacing region 16 is silicon relative to the surface of the first region 14. The depth of the indentation into the substrate 11 is less than 3000 nm. Based on this, compared to the conventional technology... In the embodiment of the present invention, the recess depth into the silicon substrate of the spacing region is 5 μm, compared to the case where the recess depth in the silicon substrate of the spacing region is 5 μm. The back contact battery provided by the company has a recess in the silicon substrate 11 of the spacing region 16. When the depth is small, in this case the corresponding conductive carrier bypasses the larger spacing region 16. Collected by the first doped semiconductor layer 12 or the second doped semiconductor layer without rotation. This allows for a reduction in the travel distance for some carriers and an improvement in carrier collection efficiency. This is advantageous for improving the operating performance of back-contact batteries.

[0056] In actual application processes, as shown in Figure 2, the light-receiving surface of the silicon substrate 11 is planar. It may be present, or the light-receiving surface of the silicon substrate may have a texture. Here, Because textures have a light-confining effect, if the light-receiving surface of the silicon substrate is a texture, By reducing the reflectivity of the light surface, more light rays are refracted from the light-receiving surface into the silicon substrate. It is advantageous for being absorbed and utilized by the capacitor substrate, and the photoelectric conversion efficiency of back contact batteries It is advantageous for improvement.

[0057] Furthermore, from the perspective of range, the first region and the second region having on the non-light-receiving side of the silicon substrate and The boundary of the spacing region is a virtual boundary. As shown in Figure 2, the first doped semiconductor layer 12 is the first region Because it is formed in region 14, the formation range of the first doped semiconductor layer 12 in actual application scenarios is required. Depending on the request, the extent of the first region 14 on the non-light-receiving surface side of the silicon substrate 11 is determined. Next, the second doped semiconductor layer 13 is formed in the second region 15, so the actual application Depending on the requirements for the formation range of the second doped semiconductor layer 13 in the scenario, the silicon substrate 11 is not The range of the second region 15 on the optical surface side can be determined. Regarding the spacing region 16, As stated in the preamble, the spacing region 16 consists of a first doped semiconductor layer 12 and a second doped semiconductor layer with opposite conductivity types. By isolating it from layer 13, leakage current can be suppressed. Therefore, in actual application scenarios... In response to the requirements for the leakage prevention spacing between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 This allows us to determine the range of the spacing region 16 on the non-light-receiving surface side.

[0058] For example, in the arrangement direction of the first and second regions, the length of the spacing region is 20 μm or more, and The distance is 110 μm or less. For example, the length of the spacing region is 20 μm, 40 μm, 60 μm, 8 The spacing may be 0 μm, 100 μm, or 110 μm, etc. In this case, the length of the spacing region is as described above. It is within the range, and because the above-mentioned gap is small, the first doped semiconductor layer and the second doped semiconductor layer This prevents electrical leakage from occurring during this process and ensures high electrical reliability of the back contact battery. This is possible. Also, due to the large spacing, the first doped semiconductor layer and / or the second doped semiconductor layer The formation area of ​​the first dome semiconductor layer on the non-photosensitive side becomes smaller, and the carriers on the non-photosensitive side become smaller. The doped semiconductor layer and / or the second doped semiconductor layer prevent timely collection from the corresponding electrode. This prevents the signal from being lost and further reduces the carrier recombination rate on the non-photoreceiving surface. can.

[0059] From the viewpoint of the depth of the recess, the second region and the spacing region of the non-light-receiving surface of the silicon substrate The depth of the recess into the silicon substrate, and the height difference between the surfaces of the second region and the spacing region are actually This may be determined according to the application scenario, where the second region is recessed inward relative to the surface of the first region. Furthermore, the surface of the spacing region is recessed inward relative to the surface of the second region, and the surface of the spacing region The depth to which the surface is recessed into the silicon substrate relative to the surface of the first region is less than 3000 nm. All that's needed is to ensure that it happens.

[0060] For example, the indentation depth of the surface of the second region into the silicon substrate is 100 nm or more, The wavelength may be less than 1000 nm. For example, the indentation of the surface of the second region into the silicon substrate The depth is 100nm, 300nm, 600nm, 800nm, 900nm, or 1000nm. Other options may also be used. In this case, the depth of the indentation of the surface of the second region into the silicon substrate is within the above range. It is inside, and because the recess depth of the surface of the second region into the silicon substrate is small, both silicon The first doped semiconductor layer and the second doped semiconductor layer are located on the non-light-receiving side of the substrate and have opposite conductivity types. This prevents the degree of displacement of the conductive layer in the silicon substrate thickness direction from becoming too small, and prevents leakage on the non-light-receiving side. This can further reduce the risk of electrical damage. Also, the spacing region is silicon relative to the second region. Because it is recessed into the substrate, that is, the depth of the recess in the silicon substrate of the spacing region is greater than that of the second region. Because it is large, if the depth of the indentation of the surface of the second region into the silicon substrate is within the above range, the second Due to the large depth of the recess of the surface of the region into the silicon substrate, the silicon substrate of the spacing region This prevents the inward recess depth from becoming larger and bypasses the spacing region to the first doped semiconductor layer. Alternatively, ensure that the travel distance of some carriers transported to the second doped semiconductor layer is small. Furthermore, the depth of the indentation into the silicon substrate in the second region and the spacing region is large. This also prevents the need to use thicker silicon substrates, and furthermore, This will reduce the manufacturing cost of back contact batteries, and also reduce the manufacturing cost of back contact batteries This is advantageous for realizing sheet-type production.

[0061] For example, the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more. Furthermore, it may be less than 2000 nm. For example, between the surface of the second region and the surface of the spacing region. The height difference is 300nm, 600nm, 900nm, 1200nm, 1500nm, 180 It may be 0 nm or 2000 nm, etc. In this case, the surface of the second region and the surface of the spacing region The height difference between them is within the above range, and because this height difference is small, in the actual manufacturing process After completely removing the portion located in the spacing region of the second doped semiconductor layer, etching time If not strictly controlled, the etching depth of the etching agent in the gap region of the silicon substrate This prevents the inability to reduce the size and lowers the difficulty of etching. The large difference in pressure means that the travel distance of the corresponding conductive carrier is not reduced significantly. This can prevent problems and ensure the potential for improving carrier collection efficiency.

[0062] Regarding the depth of the recess in the silicon substrate of the spacing region, the depth value is the silicon on the surface of the second region. The value may be greater than the depth of the recess into the substrate and less than 3000 nm. For example, if the recess depth of the surface of the second region into the silicon substrate is 500 nm, then The depth to which the separation region is recessed into the silicon substrate relative to the surface of the first region is greater than 500 nm. and any value less than 3000nm (for example, 1000nm, 1500nm, 180nm) It may be 0nm, 2000nm, 2500nm, 2800nm, or 2900nm, etc. stomach.

[0063] From the viewpoint of surface morphology, as shown in Figure 2, on the non-light-receiving surface of the silicon substrate 11, The surface of the first region 14 is planar. The surface of the second region 15 is also planar, but with texture It may be. Here, as shown in Figures 2 to 7, if the surface of the second region 15 is planar In addition, the surface of the second region 15 is relatively flat, and the second doped semiconductor formed in the second region 15 This is advantageous for improving the formation quality of the body layer 13. In addition, the second doped semiconductor formed in the second region 15 Because the degree of relief of the surface of layer 13 and the surface of the second region 15 are similar, the surface of the second region 15 is planar. In this case, the direction of surface flatness of the second doped semiconductor layer 13 on the side away from the silicon substrate 11 It is also advantageous for the upper part. Based on this, the back contact battery has a surface passivation layer 17 If it further includes, the surface flatness of the surface passivation layer 17 compared to the texture The thickness of the portion formed in the highly doped second semiconductor layer 13 becomes larger, and the second doped semiconductor The passive surface passivation layer 17 on the side of the body layer 13 away from the silicon substrate 11 To enhance the vaping effect, the carrier recombination speed on the non-light-receiving side of the back contact battery is further increased. This can reduce the power consumption, which is advantageous for improving the photoelectric conversion efficiency of back-contact batteries.

[0064] As shown in Figures 2 to 7, the surface of the spacing region 16 is planar. Alternatively, it may be a texture. Here, as shown in Figures 2 to 7, the table of the spacing region 16 If the surface is planar, the surface of the spacing region 16 is relatively flat. Based on this, If the contact battery further includes a surface passivation layer 17, compared to the texture, The thickness of the portion of the surface passivation layer 17 whose surface is formed in the planar spacing region 16 is The passivation effect of the surface passivation layer 17 on the spacing region 16 increases. This can increase the carrier recombination rate on the surface of the spacing region 16, and the back contour This is advantageous for improving the photoelectric conversion efficiency of CT batteries. Specifically, the surface roughness of the spacing region 16 is Passivation of surface passivation layer 17 to spacing region 16 in the application scenario The requirements for the effect and the actual manufacturing process may be determined accordingly, and here we will not specifically limit the options. do not.

[0065] For example, the range per 10,000 square micrometers on the surface of the spacing region ( The roughness within a 100 micrometer x 100 micrometer area is 30 μm or less. It is also acceptable. For example, per 10,000 square micrometers on the surface of the spacing region The roughness ranges are 5μm, 10μm, 12μm, 15μm, 18μm, 20μm, and 22μm. The thickness may be 25 μm or 30 μm, etc. The beneficial effect in this case is that the surface of the spacing region is flat. The beneficial effects are similar to those in the case of a surface, so we will omit the explanation here.

[0066] Here, if the surface of the second region or the spacing region is textured, the texture of the surface The size of the structure may be determined according to the depth of the recess of the texture into the silicon substrate. Here, we will not specify any particular limitations. To make it understandable, within a certain range, the texture of the silicon The smaller the depth of the recess into the substrate, the smaller the size of the texture structure on its surface. Also, it should be explained that if the surface of the second region or the spacing region is a texture... The depth of the indentation of the surface of the second region or the spacing region into the silicon substrate is the second region or the spacing region This is equal to the vertical distance from the middle of the texture structure to the surface of the first region.

[0067] Regarding the shape of the side walls of the spacing region, as shown in Figure 2, the side walls of the spacing region 16 are horizontal and They may be installed vertically. Alternatively, as shown in Figure 13, on the side wall of the spacing region 16, The cross-sectional area of ​​at least a portion of the spacing region 16 gradually increases in the direction from the light-receiving surface to the non-light-receiving surface. To that end, at least some of the surfaces are positioned at an angle to the horizontal plane. In this case, The cross-sectional area of ​​the light-receiving side of the separation region 16 is smaller than the cross-sectional area of ​​the non-light-receiving side of itself, and the first do The gap between the doped semiconductor layer 12 and the second doped semiconductor layer 13, which has a conductivity type opposite to that of the first doped semiconductor layer, is increased. This is advantageous, as it reduces the risk of leakage current on the non-light-receiving side of the back contact battery, and the back contact High electrical reliability of the contact battery is ensured. Also, the horizontal of the side wall of the spacing region 16 The parts positioned at an angle to the surface are also advantageous for reflecting light rays, allowing more light rays to be reflected. Under the reflective action of the portion of the side wall of the spacing region 16 that is positioned obliquely to the horizontal plane, This is advantageous for the contact battery to enter the silicon substrate 11 from the non-light-receiving side, and further This is advantageous for improving the photoelectric conversion efficiency of back-contact batteries.

[0068] In the above case, the side wall of the spacing region is provided at an angle to the horizontal plane. The angle between the part and the horizontal plane is determined according to the actual manufacturing process and the reflection requirements for the side wall. However, we will not specify this here.

[0069] For example, a portion of the side wall of the spacing area that is positioned at an angle to the horizontal plane and a horizontal portion. The angle with respect to the surface may be 52° or more and 58° or less. For example, the side of the spacing region The angle between the portion of the wall that is positioned diagonally to the horizontal plane and the horizontal plane is 52°. It may be 53°, 54°, 55°, 56°, 57°, or 58°, etc. In this case, the angle If the degree is within the above range, more light rays will be oblique to the horizontal plane at the side walls of the spacing region. Under the large reflective effect of the portion provided, it enters the silicon substrate and is beneficial to the silicon substrate. This ensures that the battery is used and further increases the light utilization rate of the back contact battery.

[0070] Regarding the first doped semiconductor layer and the second doped semiconductor layer described above, from a material standpoint, The material for the first doped semiconductor layer or the second doped semiconductor layer is silicon, germanium silicon. It may also be a semiconductor material such as germanium or gallium arsenide. From the viewpoint of the arrangement of materials. Therefore, the crystalline phase of the first doped semiconductor layer or the second doped semiconductor layer is amorphous, microcrystalline, nanocrystalline. It may be a crystal, single crystal, or polycrystalline material. From the viewpoint of conductivity type, the first doped semiconductor layer and the second As long as it is ensured that the doped semiconductor layer has the opposite conductivity type, the first doped semiconductor layer or the The conductivity type of the two-doped semiconductor layer may be opposite to or the same as that of the silicon substrate. i. The thickness of the first doped semiconductor layer and the second doped semiconductor layer shall be determined according to the actual requirements. You may set it, and we will not specifically limit it here. For example, the first doped semiconductor layer or the second doped The thickness of the occluding semiconductor layer may be 100 nm or more and 500 nm or less.

[0071] In actual application processes, the first doped semiconductor layer is formed directly on the first region of the silicon substrate. Alternatively, as shown in Figure 2, the back contact battery is located on the silicon substrate 11. A first passivation layer located between the first region 14 and the first doped semiconductor layer 12. 18 further includes. In this case, the first passivation layer 18 and the first doped semiconductor layer 12 are A selective contact structure is configured to contact the first region 14 of the non-light-receiving surface of the silicon substrate 11. To achieve chemical passivation and selective collection of corresponding conductive carriers This can be achieved, reducing the carrier recombination speed on the non-photoreceiving surface side, and back contact electricity This is advantageous for improving the photoelectric conversion efficiency of ponds.

[0072] Specifically, the material of the first passivation layer is the material of the first doped semiconductor layer, and Selection of a first passivation layer and a first doped semiconductor layer in actual application scenarios The type of contact structure may be determined according to the type of contact structure, and is not specifically limited here.

[0073] For example, a selective contact structure consisting of a first passivation layer and a first doped semiconductor layer In the case of a tunnel passivation contact structure, the first doped semiconductor layer is doped polycrystalline silica The tunnel is a concrete layer, and the first passivation layer is a tunnel passivation layer. The material for the passivation layer is silicon dioxide, aluminum oxide, or titanium dioxide. It may be included.

[0074] Furthermore, for example, a selective contact structure consisting of a first passivation layer and a first doped semiconductor layer. If the first doped semiconductor layer is a dissimilar contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped The first passivation layer is a microcrystalline silicon layer and / or This is an intrinsic microcrystalline silicon layer.

[0075] The thickness of the first passivation layer may be set according to the actual needs, here So, we won't limit it specifically. For example, the thickness of the first passivation layer is 0.5 nm or more, and It may also be 3nm or less.

[0076] Regarding the second doped semiconductor layer described above, the second doped semiconductor layer is located on the second region of the silicon substrate. It may be formed directly. Alternatively, as shown in Figure 2, the back contact battery may be silicon-based The second passivation is located between the second region 15 of the plate 11 and the second doped semiconductor layer 13. It further includes a doping layer 19. In this case, it includes a second passivation layer 19 and a second doped semiconductor. Layer 13 constitutes a selective contact structure, and the second region 15 of the non-light-receiving surface of the silicon substrate 11 To achieve chemical passivation and select the corresponding conductive carrier. This enables targeted collection and reduces the carrier recombination rate on the non-photoreceiving surface, and backcon This is advantageous for improving the photoelectric conversion efficiency of tact batteries.

[0077] Specifically, the material and thickness of the second passivation layer described above are the same as those of the first passivation layer described above. The material and thickness of the coating layer can be found in the references provided, and will not be explained here.

[0078] From a morphological standpoint, in the embodiments of the present invention, between the first doped semiconductor layer and the second doped semiconductor layer Without specifically limiting the shape of the side surface close to the partition area, the backco provided by the embodiment of the present invention It would be sufficient if it could be applied to contactless batteries. For example, a first doped semiconductor layer and / or a second doped semiconductor layer. The sides near the spacing region of the semiconductor layer have shapes such as straight lines, bent lines, arcs, or nearly wavy shapes. This may also be the case. Here, the morphology of the side surface near the spacing region of the first doped semiconductor layer is the second doped The morphology of the side surface near the spacing region of the semiconductor layer may be the same as or different from that of the semiconductor layer.

[0079] Here, in the actual application process, as shown in Figures 3 to 7, the first doped half described above The sides of the conductive layer 12 and the second doped semiconductor layer 13 near the spacing region 16 are both approximately wavy. It may be present. Also, the corresponding variation on the side of the second doped semiconductor layer 13 near the spacing region 16. The width is greater than the corresponding variation width of the side surface near the spacing region 16 of the first doped semiconductor layer 12. It is also possible to consider the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer 13 near the spacing region 16. This is smaller than the corresponding variation frequency of the side surface near the spacing region 16 of the first doped semiconductor layer 12. This is also possible. In this case, the corresponding variation of the side surface of the second doped semiconductor layer 13 near the spacing region 16. If the width is greater than the corresponding variation width of the side surface close to the spacing region 16 of the first doped semiconductor layer 12, The roughness of the local region on the side surface close to the spacing region 16 of the second doped semiconductor layer 13 is similar to that of the first doped semiconductor layer. The roughness of the local region on the side of the body layer 12, which is smaller than the roughness of the second dome that was formed. The number of defects in the region close to the spacing region 16 of the doped semiconductor layer 13 is reduced, and further the second doped semiconductor This is advantageous for reducing the carrier recombination rate in the portion of layer 13 close to the spacing region 16, The operating performance of contact lenses will be further improved.

[0080] Here, the corresponding side of the surface near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer. The range of variation refers to the range of undulation of the protruding portion of the side relative to the lowest point of the recessed portion of the side. The corresponding fluctuation frequencies of the sides near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer, and This refers to the frequency at which different protrusions on the side surface appear. Specifically, the first doped semiconductor If the sides near the spacing region of both the first doped semiconductor layer and the second doped semiconductor layer are both approximately wavy, then the first doped semiconductor layer The variation range and variation frequency on the sides near the spacing region of the doped semiconductor layer and the second doped semiconductor layer are actually This may be determined according to the manufacturing process, and is not specifically limited here.

[0081] As one possible implementation, as shown in Figure 2, the back contact battery is the first door Surface passivation covering the doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacing region 16 A layer 17 may be further included. In this case, the surface passivation layer 17 is a back contour Passivating the non-light-receiving side of the CT battery reduces the carrier recombination rate on the non-light-receiving side. It can be made possible. Also, the spacing region 16 in which the depth of the recess into the silicon substrate 11 is the largest is Because the corresponding recess depth is less than 3000 nm, the back contact battery is not light-receiving. This is advantageous in reducing the degree of undulation in each region on the surface side, and the non- The thickness of the formation on the light-receiving surface side is increased, and the surface passivation layer 17 is increased relative to the non-light-receiving surface side. It is advantageous for enhancing the motivational effect.

[0082] Specifically, the material of the above surface passivation layer is silicon dioxide, aluminum oxide, or This may be any insulating material having passivation properties, such as silicon nitride. The thickness of the surface passivation layer may be determined according to the actual application scenario. We will not specify any limitations here.

[0083] In a second aspect, embodiments of the present invention provide a method for manufacturing a back-contact battery. Hereinafter, The manufacturing process will be explained based on the cross-sectional diagrams of the operations shown in Figures 2 to 21. Specifically, The method for manufacturing the back contact battery includes the following steps.

[0084] First, prepare a silicon substrate, and on the non-light-receiving surface of the silicon substrate, divide the surface at alternating intervals. The first and second regions that are covered, and the second region adjacent to the first region itself It has a spacing region.

[0085] Specifically, the ranges of the first region, the second region, and the spacing region on the non-light-receiving surface side are as follows: You can refer to [the relevant source], so I will omit the explanation here.

[0086] Next, as shown in Figures 12 to 14, a first doped semiconductor layer 12 is formed in the first region 14. Furthermore, the surfaces of both the spacing region 16 and the second region 15 are siliconized relative to the surface of the first region 14. The circuit board 11 is recessed.

[0087] In the actual manufacturing process, as shown in Figure 11, after preparing the silicon substrate 11, A first doped semiconductor layer 12 is provided throughout the entire surface of the non-light-receiving surface of the recon substrate 11, and the first doped A first mask layer 20 is formed in the portion of the semiconductor layer 12 that corresponds to the first region 14. This can be done. Next, as shown in Figures 12 and 13, under the masking action of the first mask layer 20 , selectively removes portions located in the spacing region 16 and the second region 15 of the first doped semiconductor layer 12. Then, the surfaces of both the spacing region 16 and the second region 15 are made relative to the surface of the first region 14. This creates a recess in the silicon substrate 11.

[0088] Here, the material and thickness of the first doped semiconductor layer, and the table of the spacing region and the second region after the operation. The depth of the recess into the silicon substrate for each surface can be found in the preceding text. The first mask layer described above. Regarding this, the material of the first mask layer may be any of the materials having a masking effect. Here, we will not specify the details. Next, the specifics of the first doped semiconductor layer and the first mask layer. Depending on the material, the formation process and specific formation of the first doped semiconductor layer and the first mask layer The process can be determined.

[0089] For example, if the material of the first doped semiconductor layer contains silicon, the non- On the light-receiving surface, a first doped semiconductor layer is provided throughout the entire layer, and in a first region of the first doped semiconductor layer The above step of forming a first mask layer located in the corresponding portion includes the following steps: However, this is also acceptable. As shown in Figure 8, the first light is provided in the entire layer on the non-light-receiving surface of the silicon substrate 11. A first intrinsic semiconductor layer 22 is formed. Next, as shown in Figure 9, the first intrinsic semiconductor layer 22 is doped. Therefore, the first intrinsic semiconductor layer 22 is formed as the first doped semiconductor layer 12, and the first doped A first doped silicate glass layer 23 is formed on the semiconductor layer 12, with the entire layer being provided. As shown in Figure 10, the first doped silicate glass is produced by a laser etching process. The portion of the gap region 16 and the second region 15 of the sucrose layer 23 is heat-treated to produce the first doped silica The portion of the glass layer 23 that has not undergone heat treatment is formed as the first mask layer 20. Next, As shown in Figure 11, the heat-treated portion of the first doped silicate glass layer 23 is removed. .

[0090] Specifically, the material of the first doped semiconductor layer contains silicon, This may mean that the material contains only silicon, or that the material of the first doped semiconductor layer is silicon This means that it includes not only silicon but also other semiconductor materials such as germanium silicon. This may also be done. Next, in the actual manufacturing process, a process such as chemical vapor deposition may be used to make it light-resistant. A first intrinsic semiconductor layer can be formed on the surface side, extending across the entire layer. Next, diffusion and other processes can be performed. Seth can dope the first intrinsic semiconductor layer. After the doping process, Not only can a single doped semiconductor layer be obtained, but the entire layer can be provided on the first doped semiconductor layer. A first doped silicate glass layer can also be formed. Then, laser etching The first doped silicate glass layer is heat-treated using a process. In this case, see Figure 1. As shown in 0, the laser-treated portion in the first doped silicate glass layer is dense. The value decreases and becomes easier to remove. On the other hand, the laser in the first doped silicate glass layer The untreated areas are highly dense and difficult to remove, which means that after heat treatment... Different parts of the first doped silicate glass layer have different etching selectivity ratios, and the first do A first mask layer 20 is obtained for patterning the single semiconductor layer 12, and the first mask Additional mask materials are formed to obtain the SC layer 20, and other mask deposition processes do not need to be formed, which is beneficial for reducing the manufacturing cost of the back contact battery and simplifying the manufacturing flow of the back contact battery. Specific conditions of the above laser etching process may be set according to the actual application scenario and are not specifically limited here.

[0091] For example, the laser used in the laser etching process may be a nanosecond laser, picosecond laser or femtosecond laser, etc. The laser etching process may be 10 W or more and 100 W or less, and the diameter of the laser spot may be 50 μm or more and 300 μ m or less.

[0092] Of course, when the material of the first doped semiconductor layer contains silicon or the material of the first doped semiconductor layer does not contain silicon, a first doped semiconductor layer provided on the entire non-light receiving surface side may be formed by processes such as chemical vapor deposition and doping. Then, a first mask layer having a masking effect of other materials such as silicon nitride can be formed by processes such as chemical vapor deposition and etching.

[0093] Also, after forming the first mask layer, by a wet chemical process, under the masking effect of the first mask layer, the portions located in the spaced regions and the second region of the first doped semiconductor layer are selectively removed, and the surfaces of both the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region, which can prevent damage to the silicon substrate by a high temperature laser and is beneficial for improving the yield of the back contact battery. Specifically, the first The process conditions for etching include the etching process used, the material of the first doped semiconductor layer, and And based on the depth of indentation of the surface of the spacing region and the second region into the silicon substrate after the operation, etc. It can be decided, and we will not specify it here.

[0094] For example, by a wet chemical process, under the masking action of the first mask layer, the first doped half The portion located in the gap region and the second region of the conductor layer is selectively removed, and the gap region and When both surfaces of the two regions are recessed into the silicon substrate relative to the surface of the first region, the wet method The process temperature of the chemical process may be 60°C or higher and 80°C or lower, and humidity may also be a factor. The process time of the chemical process may be 40 seconds or more and 200 seconds or less, and Therefore, the wet chemical etching solution used in wet chemical processes is an alkaline wet chemical etching solution. It may be a etching solution, and the alkaline component in an alkaline wet chemical etching solution The volume ratio of (for example, NaOH or KOH) may be 2% or more and 20% or less. For example, the process temperature for a wet chemical process is 60°C, 70°C, 75°C, 78°C, or 80°C. °C may also be used. The process time for the wet chemical process is 40s, 60s, 80s, 10 It may be 0s, 150s or 200s, etc. Wet chemical processes used in wet chemical processes If the etching solution is an alkaline wet chemical etching solution, The volume ratio of alkaline components in the mixing solution is 2%, 3%, 6%, 9%, 12%, 15% or This may be 20%, etc. In this case, the process temperature and process time of the wet chemical process In both cases, the surfaces of the intervening region and the second region are treated by a wet chemical process. This affects the depth of the indentation created within the silicon substrate relative to the surface of the region. Based on this, wet processing If the process temperature of the learning process is within the above range, then the low process temperature will result in Both the surface of the separating region and the surface of the second region are recessed into the silicon substrate relative to the surface of the first region. This prevents the depth from becoming too small. Also, because the process temperature is high... Furthermore, the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region. It is also possible to prevent the depth of the dipping from increasing. After this operation, the spacing area and The depth to which the surfaces of the two regions are recessed into the silicon substrate relative to the surface of the first region is, in both cases, shaped In the resulting back contact battery, the surface of the second region is silicon relative to the surface of the first region. This is equal to the depth of the recess into the substrate. Here, the surface of the second region is equal to the surface of the first region. To prevent the depth of the indentation within the silicon substrate from increasing or decreasing. For the beneficial effects, please refer to the preceding paragraph. Next, the process time and the properties of alkaline components The beneficial effect of the part ratio being within the above range is that the process temperature is 60°C or higher, and 80°C. The beneficial effects of temperatures below a certain temperature are similar and will not be explained here.

[0095] Furthermore, by adding polishing additives to the wet chemical etching solution, the interval after the operation is reduced. The flatness of the region and the second region surface is increased, and the surface properties of the spacing region and the second doped semiconductor layer are improved. The passivation effect of the passivation layer can be further enhanced. Specifically, research The components of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution depend on the actual application. It may be decided according to Rio, and will not be specifically limited here. For example, polishing additives are inexpensive. It may contain sodium benzoate, defoaming agent, surfactant, etc. The volume ratio in the wet chemical etching solution of the polishing additive may be 0.5% or more and 5% or less. It may be 0.5% or more and 5% or less.

[0096] It should be noted that when the manufactured back contact battery further includes a first passivation layer located between the first region and the first doped semiconductor layer, after preparing the silicon substrate, before forming the first doped semiconductor layer in the first region, the manufacturing method of the back contact battery further includes a step of forming the first passivation layer in the first region by deposition and etching processes. Or, as shown in FIG. 8, after preparing the silicon substrate, a first passivation layer 18 provided on the entire layer on the non-light-receiving surface side may be formed by a process such as chemical vapor deposition. Thereafter, as shown in FIGS. 11 to 13, a first mask layer 20 is formed, and after selectively etching the first doped semiconductor layer 12 under the masking action of the first mask layer 20, the first passivation layer 18 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer to form the first passivation layer 18, and the manufacturing process of the back contact battery is simplified. Before forming the first doped semiconductor layer in the first region, The manufacturing method further includes a step of first forming the first passivation layer in the first region by deposition and etching processes. It further includes the step of forming the first passivation layer in the first region first by deposition and etching processes.

[0097] Or, as shown in FIG. 8, after preparing the silicon substrate, a first passivation layer 18 provided on the entire layer on the non-light-receiving surface side may be formed by a process such as chemical vapor deposition. Thereafter, as shown in FIGS. 11 to 13, a first mask layer 20 is formed, and after selectively etching the first doped semiconductor layer 12 under the masking action of the first mask layer 20, the first passivation layer 18 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer to form the first passivation layer 18, and the manufacturing process of the back contact battery is simplified. After the first doped semiconductor layer 12 is selectively etched under the masking action of the first mask layer 20, The first passivation layer 18 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer to form the first passivation layer 18, and the manufacturing process of the back contact battery is simplified. The manufacturing process of the back contact battery is simplified.

[0098] Next, after both the surface of the spacing region and the second region are recessed into the silicon substrate with respect to the surface of the first region, as shown in FIG. 20, a second doped semiconductor layer 13 is formed in the second region 15, and the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15, and the depth at which the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the first region 14 is less than 3000 nm. After both the surface of the spacing region and the second region are recessed into the silicon substrate with respect to the surface of the first region, as shown in FIG. 20, a second doped semiconductor layer 13 is formed in the second region 15. And the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15. And the depth at which the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the first region 14 is less than 3000 nm. The depth is less than 3000 nm.

[0099] In the actual manufacturing process, as shown in Figure 18, the surfaces of the spacing region 16 and the second region 15 After both are indented into the silicon substrate 11 relative to the surface of the first region 14, the first doped half A second doped semiconductor layer 13 is deposited in the conductive layer 12, the spacing region 16, and the second region 15, and A second mask layer 21 is formed in the portion of the second doped semiconductor layer 13 corresponding to the second region 15. This can be done. Next, as shown in Figure 19, under the masking effect of the second mask layer 21, the second do The portions corresponding to the first region 14 and the spacing region 16 of the semiconductor layer 13 are selectively removed, and The surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15.

[0100] Specifically, the material and thickness of the second doped semiconductor layer, and the surface of the spacing region after the operation The depth of the indentation into the silicon substrate can be found in the previous section, and will not be explained here. Section 2 The mask layer may be made of any material that has a masking effect. In the actual manufacturing process, depending on the materials of the second doped semiconductor layer and the second mask layer, the second doped The formation process and specific formation steps for the supramolecular layer and the second mask layer may be determined.

[0101] For example, if the material of the second doped semiconductor layer contains silicon, A second doped semiconductor layer is deposited in the body layer, the spacing region and the second region, and the second doped semiconductor layer The above step of forming a second mask layer in the portion corresponding to the second region is as follows: It may include. As shown in Figure 15, the first doped semiconductor layer 12, the spacing region 16 and the second region A second intrinsic semiconductor layer 24 is deposited in region 15. Next, as shown in Figure 16, the second intrinsic semiconductor Layer 24 is doped to form a second intrinsic semiconductor layer 24 as a second doped semiconductor layer 13. , and a second doped silicate glass layer 25 provided throughout the second doped semiconductor layer 13 Next, as shown in Figure 17, the second doping is formed by a laser etching process. The portions of the silicate glass layer 25 corresponding to the first region 14 and the spacing region 16 are heat-treated. The portion of the second doped silicate glass layer 25 corresponding to the second region 15 is the second mask layer 21 This is how it is formed. Then, as shown in Figure 18, the second doped silicate glass layer 25 is heat-treated Remove the parts that have been rationalized.

[0102] Specifically, the fact that the material of the second doped semiconductor layer contains silicon means that the second doped semiconductor layer This may mean that the material contains only silicon, or that the material of the second doped semiconductor layer is silicon This means that it includes not only silicon but also other semiconductor materials such as germanium silicon. This may also be done. Next, in the actual manufacturing process, a process such as chemical vapor deposition may be used to make it light-resistant. A second intrinsic semiconductor layer can be formed on the surface side, extending across the entire layer. Next, diffusion and other processes can be performed. Seth can dope the second intrinsic semiconductor layer. After the doping process, Not only can a 2-doped semiconductor layer be obtained, but the entire layer can be provided on the second doped semiconductor layer. A second doped silicate glass layer can also be formed. Then, laser etching The process involves the first region and the spacing region of the second doped silicate glass layer. The portion can be heat-treated. In this case, the laser in the second doped silicate glass layer... The treated area becomes less dense and easier to remove. On the other hand, the second dope silicate The portion corresponding to the second region of the glass layer is not laser-treated, so it is highly dense and can be removed. This makes it less likely to occur, and as a result, after heat treatment, different parts of the second doped silicate glass layer The minutes have different etching selectivity ratios and are used for patterning the second doped semiconductor layer. A second mask layer is obtained, and to obtain the second mask layer, other mask materials are additionally formed. , and eliminates the need to form other mask deposition processes, reducing the manufacturing cost of back contact batteries. This is advantageous for reducing and simplifying the manufacturing flow of back-contact batteries. For specific conditions regarding the etching process, please refer to the preceding paragraph; here, we will not go into detail. Not limited to a specific target.

[0103] Naturally, the material of the second doped semiconductor layer contains silicon, or the second doped semiconductor layer If the material does not contain silicon, it can be processed through processes such as chemical vapor deposition and doping. A second doped semiconductor layer may be formed on the optical side, extending across the entire layer. Subsequently, chemical vapor deposition is performed. Furthermore, processes such as etching mask the material, which is otherwise silicon nitride or other materials. A second mask layer having the properties can be formed.

[0104] Furthermore, after forming the second mask layer, the second mask layer is processed by a process such as wet chemistry. Under the action, the spacing region of the second doped semiconductor layer and the portion located in the first doped semiconductor layer are selected. Selectively remove the material, and then recess the surface of the spacing region into the silicon substrate relative to the surface of the second region. This prevents damage to the silicon substrate caused by high-temperature lasers, and back contact electricity This is advantageous for improving the yield of good quality ponds. Specifically, it selectively etches the second doped semiconductor layer. The process conditions include the etching process used, the material of the second doped semiconductor layer, and the intervals between them. It may also be determined based on the depth of the indentation of the surface of the separated region into the silicon substrate, and here specifically... Not limited to a specific target.

[0105] For example, by a wet chemical process, under the masking action of the second mask layer, the second doped layer The portion corresponding to the gap region of the conductor layer is selectively removed, and the surface of the gap region is the second region When creating a recess in the silicon substrate relative to the surface, the process temperature of the wet chemical process is 6 The temperature may be above 0°C and below 80°C, and the process time for the wet chemical process is It may be 50 seconds or longer and 300 seconds or less, and is used in wet chemical processes. The wet chemical etching solution is an alkaline wet chemical etching solution, and is alkaline The volume ratio of alkaline components (e.g., NaOH or KOH, etc.) in a wet chemical etching solution is It may be 2% or more and 20% or less. For example, the process temperature of a wet chemical process. The temperature may be 60°C, 70°C, 75°C, 78°C, or 80°C, etc. The processing time can be 50s, 55s, 60s, 100s, 150s, 200s, or 300s, etc. It may be possible. The wet chemical etching solution used in the wet chemical process is alkaline wet In the case of a chemical etching solution, the alkaline component in the alkaline wet chemical etching solution The volume ratio may be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, etc. In this case, the process temperature and process time of the wet chemical process are both wet chemical process This affects the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region. This gives the following: Based on this, if the process temperature of the wet chemical process is within the above range, Due to the low temperature, the silicon substrate is located on the surface of the second region relative to the surface of the second region. This prevents the depth of the indentation from decreasing. Also, the process temperature is high. By doing so, the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region. This also prevents the depth from becoming too large. Here, the second region of the surface of the spacing region The depth of the recess into the silicon substrate relative to the surface becomes smaller or larger. For the beneficial effects of prevention, please refer to the preceding paragraph. Next, process time and Alka The beneficial effect of the volume ratio of the recyclable component being within the above range is that the process temperature is 60°C or higher. The beneficial effects of being above and below 80°C are similar, so we will omit the explanation here.

[0106] Furthermore, by adding polishing additives to the wet chemical etching solution, the interval after the operation is reduced. To increase the flatness of the region surface and passivate the surface passivation layer relative to the spacing region The effect can be further enhanced. Specifically, the components of the polishing additive and the moisture content of the polishing additive The proportion in the chemical etching solution may be determined according to the actual application scenario, where This is not specifically limited. For example, abrasive additives include sodium benzoate, defoamers, and surfactants. It may contain abrasives, etc. The volume ratio of polishing additives in the wet chemical etching solution is 0.5% or less. It may be above, and also 5% or less.

[0107] What needs to be explained is that the manufactured back contact battery has a second region and a second doped semiconductor If a second passivation layer is further included between the body layers, then the spacing region and the second region After both surfaces are recessed into the silicon substrate relative to the surface of the first region, the second region Before forming the second doped semiconductor layer in minutes, the manufacturing method of the back contact battery involves deposition and The step of forming a second passivation layer on the second region previously by an etching process is further included.

[0108] Alternatively, as shown in FIG. 15, after recessing both the surfaces of the spacing region and the second region into the silicon substrate with respect to the surface of the first region a second doped semiconductor layer is formed on a portion of the second region Prior to that, a second passivation layer 19 may be deposited on the first doped semiconductor layer, the second region and the spacing region by a process such as chemical vapor deposition Thereafter, as shown in FIGS. 18 and 19 , a second mask layer 21 is formed, and after selectively etching the second doped semiconductor layer under the masking action of the second mask layer 21 the second passivation layer 19 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer for forming the second passivation layer 19, and the manufacturing process of the back contact battery is simplified.

[0109] Also, when the manufactured back contact battery further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region, after recessing the surface of the spacing region into the silicon substrate with respect to the surface of the second region a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13 and the spacing region 16 can be formed by a process such as chemical vapor deposition as shown in FIG. 21 The material and thickness of the surface passivation layer 17 may refer to the foregoing text.

[0110] For the beneficial effects of the second aspect and its various embodiments in the examples of the present invention, reference may be made to the analysis of the beneficial effects in the first aspect and its various embodiments, and the description is omitted here.

[0111] ​​ Furthermore, the embodiments of the present invention describe the manufacturing of a back contact battery provided by the embodiments of the present invention. A comparative example and an embodiment are further provided to illustrate the manufacturing process and operating performance. Here, Table 1 shows the test results of the back contact batteries corresponding to Example 1 and Comparative Example 1. . Example 1

[0112] Step 1: Alkaline solution is applied to a single-crystal silicon wafer using a 15% alkaline solution. A potassium polishing treatment is performed to create a smooth and clean silicone surface.

[0113] Step 2: Deposition of a tunnel oxide layer on the surface of a single-crystal silicon wafer, and intrinsic polycrystalline silicon. The silicon layer is deposited sequentially. Here, the thickness of the tunnel oxide layer is 1.8 nm, and intrinsic The thickness of the polycrystalline silicon layer is 350 nm.

[0114] Step 3: The deposited intrinsic polycrystalline silicon layer is subjected to boron doping, A crystalline silicon layer is formed as a P-type doped polycrystalline silicon layer, and then the P-type doped polycrystalline silicon A borosilicate glass layer is formed on the ricon layer. Here, the boron doping concentration is 8 × 10⁻⁶. 19 / cm 3 That is the case.

[0115] Step 4: The borosilicate glass layer is heat-treated by a laser etching process, and identified The mask layer has the following pattern. Here, the laser may be a picosecond laser, and The power may be 40W, and the spot diameter is 200µm.

[0116] Step 5: Under the masking effect of the mask layer, selectively apply a portion of the P-doped polycrystalline silicon layer. The groove structure is removed. Then, surface etching is performed on the single crystal silicon wafer to remove the groove structure. This forms the main components of the etching solution used here are alkali and polishing additives. Contains an agent. The alkali concentration in the etching solution is 5%, and the etching temperature is 82°C. The processing time was 300 s, the volume ratio of the polishing additive was 2%, and the main components of the polishing additive were... It contains sodium benzoate, an antifoaming agent, and a surfactant.

[0117] Step 6. Tunnel oxide layer and N-type doping are sequentially laminated on the bottom of the groove structure. A polycrystalline silicon layer is formed, and then a P-type doped polycrystalline silicon layer is formed on a single-crystal silicon wafer. The portion located between the N-type doped polycrystalline silicon layer is the bottom surface of the groove structure. The substrate is recessed. Here, the thickness of the N-type doped polycrystalline silicon layer is 150 nm or more, and The wavelength is 180 nm or less. The thickness of the tunnel oxide layer is 0.5 nm or more and 3 nm or less. P-type doped polycrystalline silicon layer and N-type doped polycrystalline silicon layer of single-crystal silicon wafer. The recess depth into the silicon substrate in the area between these two points is less than 3000 nm.

[0118] Step 7: Single crystal silicon wafer, P-type doped polycrystalline silicon layer and N-type doped polycrystalline silicon layer A surface passivation layer is formed to cover the crystalline silicon layer. Comparative Example 1

[0119] The manufacturing method corresponding to Comparative Example 1 is the same as the manufacturing flow of Example 1, except for step 6. Here, the manufacturing method provided by Comparative Example 1 involves sequentially stacking materials on the bottom of the grooves of the groove structure. After forming the tunnel oxide layer and the N-type doped polycrystalline silicon layer, single crystal silicon The portion located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer of EHA. The indentation depth into the silicon substrate is made greater than 5 μm, and the P of the single crystal silicon wafer is also made greater The surface of the portion located between the N-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer is It is a texture.

[0120] [Table 1]

[0121] From the data shown in Table 1, the back contour formed by the manufacturing method provided in Example 1 In a compact battery, the depth of the recess in the silicon substrate of the spacing region is small, so the carrier's movement distance The separation can be shortened, and the back contact battery further reduces the surface passivation layer. When included, it enhances the passivation effect of the surface passivation layer on the spacing region. This also allows for the back contact electricity obtained by the corresponding manufacturing method of Comparative Example 1 to be obtained. Compared to a pond, the operating efficiency, open-circuit voltage, short-circuit current, and curve factor are higher, that is, in the embodiment of the present invention Back contact batteries, which are supplied by the manufacturer, have higher operating performance.

[0122] The above explanation does not provide a detailed description of the composition of each layer, etching, or other technical details. No. However, a person skilled in the art can shape layers, regions, etc., of a desired shape by various technical means. It should be understood that this is possible. Furthermore, in order to form the same structure, a person skilled in the art would understand. It is also possible to design methods that are not exactly the same as the methods described above. Although each example has been described, this is because the measures in each example cannot be advantageously combined. It doesn't mean that.

[0123] The above describes embodiments of the present disclosure. However, these embodiments are intended for illustrative purposes only. This is merely a limitation and not intended to limit the scope of this disclosure. The scope of this disclosure is limited to the attached patent. The scope of this disclosure is limited by the claims and their equivalents. Without exceeding the scope of this disclosure, the Company Any person can make various replacements and modifications, and all such replacements and modifications are disclosed herein. It shall fall within the specified range. [Explanation of symbols]

[0124] 11 Silicon substrate 12. First doped semiconductor layer 13. Second doped semiconductor layer 14 First area 15 Second area 16 Interval area 17 Surface passivation layer 18. First Passivation Layer 19. Second Passivation Layer 20. First mask layer 21. Second Mask Layer 22 First intrinsic semiconductor layer 23. First doped silicate glass layer 24 Second intrinsic semiconductor layer 25. Second doped silicate glass layer

Claims

1. The silicon substrate includes a first doped semiconductor layer and a second doped semiconductor layer distributed alternately at intervals on the non-light-receiving side of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, and on the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is the first region, the region corresponding to the second doped semiconductor layer is the second region, the region located between the first region and the second region adjacent to it is the gap region, the surface of the second region is recessed into the silicon substrate relative to the surface of the first region, the surface of the gap region is recessed into the silicon substrate relative to the surface of the second region, and the sides of the first doped semiconductor layer and the second doped semiconductor layer near the gap region are both substantially wavy. A back contact battery characterized in that the corresponding variation width of the side surface of the second doped semiconductor layer near the spacing region is greater than the corresponding variation width of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding variation frequency of the side surface of the second doped semiconductor layer near the spacing region is less than the corresponding variation frequency of the side surface of the first doped semiconductor layer near the spacing region, wherein the corresponding variation width of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer refers to the undulation width of the protruding portion of the side surface with respect to the lowest point of the recessed portion of the side surface, and the corresponding variation frequency of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer refers to the frequency at which different protruding portions of the side surface appear.

2. The roughness within a range of 10,000 square micrometers on the surface of the spacing region is 30 μm or less, and / or The back contact battery according to claim 1, characterized in that the length of the spacing region is 20 μm or more and 110 μm or less in the direction of arrangement of the first region and the second region.

3. The surface of the second region is planar and / or, The recess depth of the surface of the second region into the silicon substrate is 100 nm or more and 1000 nm or less, and / or The back contact battery according to claim 1, characterized in that the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm.

4. The back contact battery according to claim 1, characterized in that at least a portion of the surface of the side wall of the spacing region is provided at an angle with respect to the horizontal plane such that the cross-sectional area of ​​at least a portion of the spacing region gradually increases in the direction from the light-receiving surface to the non-light-receiving surface.

5. The first doped semiconductor layer, the second doped semiconductor layer, and the surface passivation layer covering the gap region further comprises and / or The present invention further includes a first passivation layer located between a first region of the silicon substrate and the first doped semiconductor layer, and / or The back contact battery according to any one of claims 1 to 4, further comprising a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

6. If the back contact battery includes the first passivation layer and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer and / or The back contact battery according to claim 5, characterized in that, if the back contact battery includes the second passivation layer and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer.

7. A step of preparing a silicon substrate, wherein the non-light-receiving surface of the silicon substrate has a first region and a second region distributed alternately at intervals, and an interval region located between the first region and the second region adjacent to it, The steps include forming a first doped semiconductor layer in the first region and recessing both the surface of the spacing region and the second region into the silicon substrate relative to the surface of the first region, The process includes the steps of forming a second doped semiconductor layer in the second region and recessing the surface of the gap region into the silicon substrate relative to the surface of the second region, wherein the sides of the first doped semiconductor layer and the second doped semiconductor layer near the gap region are both substantially wavy. A method for manufacturing a back contact battery, characterized in that the corresponding variation width of the side surface of the second doped semiconductor layer near the spacing region is greater than the corresponding variation width of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding variation frequency of the side surface of the second doped semiconductor layer near the spacing region is smaller than the corresponding variation frequency of the side surface of the first doped semiconductor layer near the spacing region, the corresponding variation width of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer refers to the undulation width of the protruding portion of the side surface with respect to the lowest point of the recessed portion of the side surface, and the corresponding variation frequency of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer refers to the frequency at which different protruding portions of the side surface appear.

8. After the step of preparing the silicon substrate, and before the step of forming the second doped semiconductor layer in the second region, the method for manufacturing the back contact battery is as follows: The steps include forming a first doped semiconductor layer provided throughout the entire layer on the non-light-receiving surface of the silicon substrate, and a first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer, The method for manufacturing the back contact battery then includes the steps of selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under the masking action of the first mask layer, and recessing both the surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region, wherein after the step of recessing both the surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region, A method for manufacturing a back contact battery according to claim 7, comprising the steps of: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region; and then selectively removing the portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking action of the second mask layer; and recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region.

9. By a wet chemical process, under the masking effect of the first mask layer, portions of the first doped semiconductor layer located in the gap region and the second region are selectively removed, and the surfaces of both the gap region and the second region are recessed into the silicon substrate relative to the surface of the first region. A method for manufacturing a back contact battery according to claim 8, characterized in that the process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 40 s or higher and 200 s or lower, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains an abrasive additive, and the volume ratio of the abrasive additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

10. By a wet chemical process, under the masking effect of the second mask layer, portions of the second doped semiconductor layer corresponding to the first region and the gap region are selectively removed, and the surface of the gap region is recessed into the silicon substrate relative to the surface of the second region. The method for manufacturing a back contact battery according to claim 8, characterized in that the process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 50 s or higher and 300 s or lower, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains an abrasive additive, and the volume ratio of the abrasive additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

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