Semiconductor and display devices

Abstract

To provide a semiconductor device common for two different circuits to drive the circuits.SOLUTION: A semiconductor device can sequentially output a plurality of signal potentials to the outside by switching the signal potentials, and can operate all of the rows in one of two different circuits arranged in a matrix and operate all of the rows or a specific row alone in the other circuit. For example, in a case where the semiconductor device is applied as a low driver which operates pixels of a display device with a sensor element built therein, it is possible to switch operations of a display element in the pixels of all the rows and operations of a sensor element in pixels of all the rows or a specific row.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a display device including the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an imaging device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. The semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] For the purpose of miniaturizing an electronic device or improving the degree of freedom in design, it is required to narrow the frame of a display device. For narrowing the frame of a display device, it is effective to provide a pixel portion and part or all of a driving circuit portion on the same substrate in a monolithic manner.

[0004] In addition, since the driving circuit portion can be manufactured in the same process as the pixel portion, mounting of an IC chip or the like becomes unnecessary, and the manufacturing cost can be reduced. For example, Patent Document 1 discloses a technique of configuring a circuit such as a shift register with unipolar transistors.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Display devices can be made more functional by incorporating sensor elements into their pixels. For example, by incorporating a capacitive sensor into a display device, it can function as a touch panel. Furthermore, by incorporating an optical sensor into a display device, imaging capabilities or contactless input functions can be added.

[0007] However, driving the sensor elements requires a drive circuit, just like the display elements, which hinders the narrowing of the bezel.

[0008] Therefore, one aspect of the present invention aims to provide a semiconductor device for driving two different circuits. Alternatively, it aims to provide a semiconductor device for driving a pixel having a first circuit and a second circuit. Alternatively, it aims to provide a display device having the above-mentioned semiconductor device. Alternatively, it aims to provide the above-mentioned semiconductor device, a method for driving the above-mentioned display device, etc. Alternatively, it aims to provide a novel semiconductor device, display device, etc.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention relates to a common semiconductor device for driving two different circuits, or to a display device having said semiconductor device.

[0011] One aspect of the present invention is a semiconductor device comprising a first block, a second block, a third block, and a first switch circuit, wherein each of the first to third blocks has a plurality of flip-flop circuits and a plurality of output circuits, each of the flip-flop circuits is electrically connected to a pair of output circuits, the plurality of flip-flop circuits are cascaded in each of the first to third blocks, the final stage flip-flop circuit of the first block, the first stage flip-flop circuit of the second block, the final stage flip-flop circuit of the second block, and the first stage flip-flop circuit of the third block are electrically connected to the first switch circuit, and the output circuit comprises a second switch circuit, a first circuit, and a second circuit, the second switch circuit is electrically connected to the flip-flop circuit, the first circuit, and the second circuit.

[0012] The first switch circuit may have the function of selecting either outputting signal potentials from the first block, the second block, and the third block, or outputting signal potentials from the first block and the third block.

[0013] The second switch circuit may have the function of selecting either conduction between the flip-flop circuit and the first circuit, or conduction between the flip-flop circuit and the second circuit.

[0014] The flip-flop circuit can output a first signal potential to a second switch circuit, the second switch circuit can output a second signal potential based on the first signal potential to the first circuit, the second switch circuit can output a third signal potential based on the first signal potential to the second circuit, the first circuit can output a fourth signal potential based on the second signal potential, and the second circuit can output a fifth signal potential based on the third signal potential.

[0015] The first and second switch circuits can be input to a sixth signal potential, a seventh signal potential, or an eighth signal potential. When the sixth signal potential is input to the first and second switch circuits, the first circuit of the first to third blocks outputs a signal potential. When the seventh signal potential is input to the first and second switch circuits, the second circuit of the first to third blocks outputs a signal potential. When the eighth signal potential is input to the first and second switch circuits, the second circuit of the first and third blocks outputs a signal potential.

[0016] When the final stage of the flip-flop circuit in the first block is the 4th stage, the final stage of the flip-flop circuit in the second block can be the 4nth stage (where n is an integer greater than or equal to 2), and the final stage of the flip-flop circuit in the third block can be the 4n+4th stage.

[0017] Another aspect of the present invention is a display device comprising the semiconductor device and a pixel, wherein the pixel has a third circuit having a display element and a fourth circuit having a light-receiving element, the first circuit being electrically connected to the third circuit and the second circuit being electrically connected to the fourth circuit.

[0018] The display element is a light-emitting element, and the light-receiving element may have electrodes common to the light-emitting element.

[0019] Furthermore, the third and fourth circuits have transistors with a metal oxide in the channel formation region, and it is preferable that the metal oxide contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). [Effects of the Invention]

[0020] According to one aspect of the present invention, a semiconductor device for driving two different circuits can be provided. Alternatively, a semiconductor device for driving a pixel having a first circuit and a second circuit can be provided. Alternatively, a display device having the above-mentioned semiconductor device can be provided. Alternatively, a method for driving the above-mentioned semiconductor device and the above-mentioned display device can be provided. Alternatively, a novel semiconductor device, display device, etc. can be provided.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0022] [Figure 1] Figure 1 is a diagram illustrating a semiconductor device. [Figure 2] Figures 2A and 2B illustrate a conventional example. Figures 2C and 2D illustrate an application example for a semiconductor device. [Figure 3] Figure 3 is a diagram illustrating a semiconductor device. [Figure 4] Figure 4 is a diagram illustrating a semiconductor device. [Figure 5] Figures 5A and 5B illustrate a flip-flop circuit. [Figure 6] Figures 6A and 6B illustrate the switch circuit of the output circuit. [Figure 7] Figures 7A to 7D illustrate the circuitry of the output circuit. [Figure 8] Figures 8A to 8D illustrate a switch circuit. [Figure 9] Figures 9A and 9B illustrate a switch circuit. [Figure 10] Figures 10A and 10B illustrate a switch circuit. [Figure 11] Figure 11 is a diagram illustrating a semiconductor device. [Figure 12] Figures 12A and 12B illustrate the switch circuit of the output circuit. [Figure 13] Figures 13A and 13B illustrate the circuitry of the output circuit. [Figure 14] Figures 14A and 14B illustrate the circuitry of the output circuit. [Figure 15] Figure 15 is a diagram illustrating a semiconductor device. [Figure 16] Figures 16A and 16B illustrate a flip-flop circuit. [Figure 17] Figures 17A and 17B illustrate the switch circuit of the output circuit. [Figure 18] Figures 18A to 18D illustrate the circuitry of the output circuit. [Figure 19] Figures 19A to 19D illustrate a switch circuit. [Figure 20] Figures 20A and 20B illustrate a switch circuit. [Figure 21] Figures 21A and 21B illustrate a switch circuit. [Figure 22] Figure 22 is a diagram illustrating a semiconductor device. [Figure 23] Figures 23A and 23B illustrate the switch circuit of the output circuit. [Figure 24] Figures 24A and 24B illustrate the circuitry of the output circuit. [Figure 25] Figures 25A and 25B illustrate the circuitry of the output circuit. [Figure 26] Figure 26 is a diagram illustrating a display device. [Figure 27] Figures 27A, 27B, 27D, and 27E illustrate circuits that can be applied to pixels of a display device. Figure 27C is a timing chart illustrating the operation of PIX2. [Figure 28]Figure 28 is a diagram illustrating the connection configuration of the circuits in the display device. [Figure 29] Figures 29A and 29B illustrate the morphology of pixels. [Figure 30] Figures 30A and 30B illustrate the circuitry of the output circuit. [Figure 31] Figure 31 is a timing chart illustrating the operation of the display device. [Figure 32] Figure 32 is a timing chart illustrating the operation of the display device. [Figure 33] Figure 33 is a timing chart illustrating the operation of the display device. [Figure 34] Figure 34 is a timing chart illustrating the operation of the display device. [Figure 35] Figure 35 is a cross-sectional view illustrating a display device. [Figure 36] Figures 36A and 36B are diagrams illustrating electronic devices. [Figure 37] Figures 37A to 37G illustrate electronic devices. [Figure 38] Figures 38A to 38D illustrate electronic devices. [Modes for carrying out the invention]

[0023] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0024] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0025] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0026] (Embodiment 1) In this embodiment, a semiconductor device that is one aspect of the present invention will be described with reference to the drawings.

[0027] One aspect of the present invention is a semiconductor device capable of switching and sequentially outputting multiple signal potentials to the outside. This semiconductor device can, for example, operate all rows of one circuit and operate all rows or only specific rows of the other circuit when two different circuits are arranged in a matrix.

[0028] For example, when the semiconductor device is applied as a low driver to drive the pixels of a display device that incorporates sensor elements, it is possible to switch between the operation of the display elements at pixels in all rows and the operation of the sensor elements at pixels in all rows or specific rows.

[0029] Furthermore, the two different circuits operated by the semiconductor device are not limited to a combination of a circuit having a display element and a circuit having a sensor element, but may also be a combination of a circuit having a first display element and a circuit having a second display element. For example, a light-emitting device such as an organic EL element and a non-light-emitting device such as a liquid crystal element can be operated by the semiconductor device.

[0030] Alternatively, the semiconductor device may consist of a circuit having a first sensor element and a circuit having a second sensor element. For example, an image sensor for image acquisition and an image sensor for distance measurement (such as a TOF (Time Of Flight) sensor) can be operated by the semiconductor device. Alternatively, the semiconductor device may consist of a combination of a display element and a sensor element, along with a memory circuit.

[0031] Figures 2A and 2B show an example of the prior art, illustrating an example where two drive circuits are used to drive the pixels 24 of a pixel array 23. Conventionally, when a pixel 24 has a circuit 25 with a display element and a circuit 26 with a sensor element, different drive circuits (low driver 21 and low driver 22) were required to drive circuit 25 and circuit 26, respectively. This is because the control of the timing of signal output differs between circuit 25 and circuit 26, or, as shown in Figure 2B, the rows driven may differ between circuit 25 and circuit 26, such as when circuit 26 is not arranged in all rows.

[0032] By using a semiconductor device 20 according to one aspect of the present invention as a low driver, it is possible to switch between the operation of the circuit 25 in all rows shown in Figure 2C or the operation of the circuit 26 in all rows, and the operation of the circuit 26 in a specific row shown in Figure 2D.

[0033] In other words, since two different low drivers can be combined into a single low driver, the number of wires and the area occupied by transistors and other components that make up the low driver can be reduced. Therefore, a narrower bezel is possible, and display devices and other components can be made smaller.

[0034] Figure 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. The semiconductor device 20 is a sequential circuit that sequentially outputs signal potentials to the outside, and is also called a shift register. Note that Figure 1 is a schematic diagram, and details such as the signal potentials input to each element, the power supply potential, and the connection configuration between each element are omitted.

[0035] The semiconductor device 20 has blocks 31, 32, and 33. Each of blocks 31, 32, and 33 has a plurality of flip-flop circuits 10 and an output circuit 11. The plurality of flip-flop circuits 10 in each of blocks 31, 32, and 33 are connected in cascading order. In addition, each of the flip-flop circuits 10 is electrically connected to a pair of output circuits 11.

[0036] The final stage flip-flop circuit 10 of block 31, the first stage flip-flop circuit 10 of block 32, the final stage flip-flop circuit 10 of block 32, and the final stage flip-flop circuit 10 of block 32 are electrically connected to the switch circuit 15.

[0037] The switch circuit 15 can switch between a first mode in which the output operation of signal potentials in blocks 31, 32, and 33 is enabled, and a second mode in which the output operation of signal potentials in blocks 31 and 33 is enabled. In the first mode, signal potentials can be sequentially output to the outside from all blocks. In the second mode, since block 32 is inactive, signal potentials can be sequentially output to the outside from blocks 31 and 33.

[0038] As shown in Figure 1, if a start pulse SP is input to the first stage flip-flop circuit 10 of block 31, and the fourth stage flip-flop circuit 10 is the final stage of block 31, then block 32 can have 5 to 4n stages (where n is an integer greater than or equal to 2) of flip-flop circuits 10. Also, block 33 can have 4n+1 to 4n+4 stages of flip-flop circuits 10.

[0039] For example, in the second mode, when n=2, the flip-flop circuits in stages 1 through 4 and 9 through 12 can output a signal potential, while the flip-flop circuits in stages 5 through 8 can not output a signal potential. Also, when n=9, the flip-flop circuits in stages 1 through 4 and 37 through 40 can output a signal potential, while the flip-flop circuits in stages 5 through 36 can not output a signal potential.

[0040] Specifically, when the semiconductor device 20 is applied to a display device having sensor elements and display elements in its pixels, the first mode is used when writing image data and performing sensing functions that require high resolution (such as fingerprint authentication). On the other hand, the second mode is used for functions such as touch or non-touch panel operation, which do not require high resolution. In the second mode, the number of lines of operation can be reduced, allowing for high-speed operation.

[0041] Furthermore, circuits with the same configuration as switch circuit 15, block 32, and block 33 can be repeatedly connected to block 33 and beyond.

[0042] Next, the output circuit 11, which is electrically connected to the flip-flop circuit 10, will be described. The output circuit 11 includes a switch circuit 12, a circuit 13, and a circuit 14. The switch circuit 12 is electrically connected to the flip-flop circuit 10. The switch circuit 12 is also electrically connected to circuits 13 and 14.

[0043] The switch circuit 12 can output a second signal potential to either circuit 13 or circuit 14 based on the first signal potential input from the flip-flop circuit 10. Additionally, a pulse width control signal PWC is input to either circuit 13 or circuit 14 via the switch circuit 12. Circuit 13 or circuit 14 can output a third signal potential externally based on the pulse width control signal PWC and the second signal potential.

[0044] For example, circuit 13 can be electrically connected to a circuit that drives the display elements of the pixels of the display device. Circuit 14 can be electrically connected to a circuit that drives the sensor elements of the pixels of the display device. In Figure 1, the output paths from circuits 13 and 14 are shown as one each, but there may be two or more. By increasing the number of pulse width control signals (PWC) input to switch circuit 12, circuit 13, and circuit 14, signal potentials can be output from two or more paths at different timings.

[0045] Figures 3 and 4 are detailed block diagrams of a semiconductor device 20a that can be applied as a semiconductor device 20 when n=9. The flip-flop circuit 10 and output circuit 11 (switch circuits 12, 13, and 14) shown in Figures 3 and 4 correspond to the block diagram shown in Figure 1. The switch circuit 15 shown in Figure 1 has as its components the switch circuits 16, 17, and 18 shown in Figure 3, and the switch circuit 19 shown in Figure 4, etc.

[0046] As mentioned above, the output circuit 11 can output a signal potential from either circuit 13 or circuit 14. Figures 3 and 4 illustrate a configuration in which the signal potential GLA (GLA[1] to GLA

[40] ) is output from circuit 13 and the signal potential GLB (GLB[1] to GLB

[40] ) is output from circuit 14.

[0047] Furthermore, Figure 3 shows an example in which a switch circuit 18 is provided between the 4th stage flip-flop circuit 10 and the 5th stage flip-flop circuit, and Figure 4 shows an example in which a switch circuit 19 is provided between the 36th stage flip-flop circuit 10 and the 37th stage flip-flop circuit 10.

[0048] Specifically, the first to fourth stage flip-flop circuits 10 and output circuits 11 shown in Figure 3 correspond to block 31 shown in Figure 1. Also, the fifth to 36th stage flip-flop circuits 10 and output circuits 11 shown in Figures 3 and 4 correspond to block 32 shown in Figure 1. Furthermore, the 37th to 40th stage flip-flop circuits 10 and output circuits 11 shown in Figure 4 correspond to block 33 shown in Figure 1.

[0049] The number of stages in each block can be changed within the scope described in Figure 1. In addition, in the configurations shown in Figures 3 and 4, the output signal of the subsequent flip-flop circuit 10 is input to the preceding flip-flop circuit 10, so the final block (not shown) of the semiconductor device 20a is provided with the necessary number of dummy flip-flop circuits 10.

[0050] The input signals for the semiconductor device 20a can include clock signals CLK1 to CLK4, pulse width control signals PWC1 to PWC4, reset signal RES, start pulse signal SP, selection signal SEL_A, selection signal SEL_B1, and selection signal SEL_B2.

[0051] Figure 5A shows a block diagram of the flip-flop circuit 10, and Figure 5B shows an example of a circuit diagram of the flip-flop circuit 10. Refer to Figure 5B for the connection configuration of the transistors and capacitors constituting the flip-flop circuit 10; the explanation is omitted. VDD represents a high-potential power supply, and VSS represents a low-potential power supply. Furthermore, the transistors constituting the semiconductor device 20a are n-channel transistors.

[0052] The input signals are two clock signals, a reset signal RES, a reset signal RIN input from the subsequent flip-flop circuit 10, and a shift signal LIN input from the preceding flip-flop circuit 10. In the first stage flip-flop circuit 10, clock signals CLK1 and CLK2 are used, and a start pulse signal SP is used instead of the shift signal LIN.

[0053] The output signals are signal potential 01, signal potential SROUT, and signal potential FN. Signal potential 01 is used to generate the signal potential to be output externally in circuit 13 or circuit 14, and signal potential FN is used to control the transistor that acts as a pull-down resistor in circuit 13 or circuit 14. Signal potential SROUT is used as the shift signal LIN for the subsequent flip-flop circuit 10 and the reset signal RIN for the preceding flip-flop circuit 10.

[0054] Figure 6A shows an example of a block diagram of the switch circuit 12, and Figure 6B shows an example of a circuit diagram of the switch circuit 12. Refer to Figure 6B for the connection configuration of the transistors and capacitors that make up the switch circuit 12; their explanation is omitted here.

[0055] The input signals are the pulse width control signal PWC, selection signal SEL_A, selection signal SEL_B, and signal potentials 01 and FN input from the flip-flop circuit 10. Selection signals SEL_A and SEL_B are signals that select whether to output the signal potential to the outside from either circuit 13 or circuit 14. Selection signal SEL_B is the signal potential generated by the switch circuit 16, which will be described later.

[0056] The output signals are signal potential 01_A, signal potential 01_B, signal potential FN_A, signal potential FN_B, pulse width control signal A_PWC, and pulse width control signal B_PWC. Inputting the selection signal SEL_A generates signal potential 01_A, signal potential FN_A, and pulse width control signal A_PWC. Inputting the selection signal SEL_B generates signal potential 01_B, signal potential FN_B, and pulse width control signal B_PWC.

[0057] Signal potentials 01_A and 01_B are used to generate the signal potentials output by circuit 13 or circuit 14. Signal potentials FN_A and FN_B are used to control the transistors that act as pull-down resistors in circuit 13 or circuit 14. Pulse width control signals A_PWC and B_PWC are used to control the pulse width of the signal potentials output by circuit 13 or circuit 14.

[0058] In other words, since the switch circuit 12 generates two pulse-width control signals from one pulse-width control signal, the input signal to the semiconductor device 20 can be reduced.

[0059] Figure 7A shows an example of a block diagram of circuit 13, and Figure 7B shows an example of a circuit diagram of circuit 13. Refer to Figure 7B for the connection configuration of the transistors and capacitors that make up circuit 13; their explanation is omitted here.

[0060] The input signals are signal potential 01_A, signal potential FN_A, and pulse width control signal A_PWC, which are input from the switch circuit 12. The signal potential GLA generated by the input of signal potential 01_A and pulse width control signal A_PWC can be output to the wiring to which an external circuit is connected. In addition, the input of signal potential FN_A activates a transistor equivalent to a pull-down resistor, stabilizing the potential of the wiring to VSS.

[0061] Figure 7C shows an example of a block diagram of circuit 14, and Figure 7D shows an example of a circuit diagram of circuit 14. Refer to Figure 7D for the connection configuration of the transistors and capacitors that make up circuit 14; their explanation is omitted here.

[0062] The input signals are signal potential 01_B, signal potential FN_B, and pulse width control signal B_PWC, which are input from the switch circuit 12. The signal potential GLB generated by the input of signal potential 01_B and pulse width control signal B_PWC can be output to the wiring to which an external circuit is connected. In addition, the input of signal potential FN_B activates a transistor equivalent to a pull-down resistor, stabilizing the potential of the wiring to VSS.

[0063] Figure 8A shows an example of a block diagram of the switch circuit 16, and Figure 8B shows an example of a circuit diagram of the switch circuit 16. Refer to Figure 8B for the connection configuration of the transistors constituting the switch circuit 16; the explanation is omitted here.

[0064] The input signals are selection signal SEL_B1 and selection signal SEL_B2. Regardless of which selection signal is input, a signal potential SEL_B is generated. This signal potential SEL_B is input to the switch circuit 12 described above. The input of selection signal SEL_B to the switch circuit 12 enables the output of the signal potential from circuit 14 to the outside.

[0065] Figure 8C shows an example of a block diagram of the switch circuit 17, and Figure 8D shows an example of a circuit diagram of the switch circuit 17. Refer to Figure 8D for the connection configuration of the transistors constituting the switch circuit 17; a detailed explanation is omitted.

[0066] The input signals are selection signal SEL_A and selection signal SEL_B1. Regardless of which selection signal is input, a signal potential SEL_C is generated. The signal potential SEL_C is input to switch circuits 18 and 19, which will be described later.

[0067] Figure 9A shows an example of a block diagram of the switch circuit 18, and Figure 9B shows an example of a circuit diagram of the switch circuit 18. Refer to Figure 9B for the connection configuration of the transistors constituting the switch circuit 18; the explanation is omitted here.

[0068] The input signals are selection signals SEL_C and SEL_B2. The switch circuit 18 has terminals SWIN1, RIN1, LIN1, LIN2, and SWIN2. In Figure 3, terminal SWIN1 is electrically connected to the output terminal of the 4th stage flip-flop circuit 10 (the terminal that outputs the signal potential SROUT). Terminal RIN1 is electrically connected to the input terminal of the 4th stage flip-flop circuit 10 (the terminal to which the reset signal RIN is input). Terminal LIN1 is electrically connected to the input terminal of the 5th stage flip-flop circuit 10 (the terminal to which the shift signal LIN is input). In Figures 3 and 4, terminal LIN2 is electrically connected to the input terminal of the 37th stage flip-flop circuit 10 (the terminal to which the shift signal LIN is input) and the switch circuit 19, which will be described later. Terminal SWIN2 is electrically connected to the output terminal of the 5th stage flip-flop circuit 10 (the terminal that outputs the signal potential SROUT).

[0069] Figure 10A shows an example of a block diagram of the switch circuit 19, and Figure 10B shows an example of a circuit diagram of the switch circuit 19. Refer to Figure 10B for the connection configuration of the transistors constituting the switch circuit 19; the explanation is omitted here.

[0070] The input signals are selection signals SEL_C and SEL_B2. The circuit also has terminals SWIN1, RIN1, RIN2, LIN1, and SWIN2. In Figure 4, terminal SWIN1 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the 36th stage flip-flop circuit 10. Terminal RIN1 is electrically connected to the input terminal (the terminal to which the reset signal RIN is input) of the 36th stage flip-flop circuit 10. In Figures 3 and 4, terminal RIN2 is electrically connected to the input terminal (the terminal to which the reset signal RIN is input) of the 4th stage flip-flop circuit 10. In Figure 4, terminal LIN1 is electrically connected to the input terminal (the terminal to which the shift signal LIN is input) of the 37th stage flip-flop circuit 10. Terminal SWIN2 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the 37th stage flip-flop circuit 10.

[0071] When the selection signal SEL_C is input to switch circuits 18 and 19, in switch circuit 18, terminals SWIN1 and LIN1 become conductive, and terminals RIN1 and SWIN2 become conductive. In switch circuit 19, terminals SWIN1 and LIN1 become conductive, and terminals RIN1 and SWIN2 become conductive.

[0072] Therefore, the signal potential SROUT output by the fourth-stage flip-flop circuit 10 is input to the fifth-stage flip-flop circuit 10 as a shift signal LIN. The signal potential SROUT output by the fifth-stage flip-flop circuit 10 is input to the fourth-stage flip-flop circuit 10 as a reset signal RIN. Therefore, by inputting the selection signal SEL_C, the output operation of the signal potentials in blocks 31 and 32 shown in Figure 1 is selected.

[0073] Furthermore, the signal potential SROUT output by the 36th flip-flop circuit 10 is input to the 37th flip-flop circuit 10 as a shift signal LIN. The signal potential SROUT output by the 37th flip-flop circuit 10 is input to the 36th flip-flop circuit 10 as a reset signal RIN. Therefore, by inputting the selection signal SEL_C, the output operation of the signal potential in block 33 shown in Figure 1 is further selected.

[0074] In other words, by inputting the selection signal SEL_C, the operation of blocks 31, 32, and 33 shown in Figure 1 is selected, and the signal potentials GLA[1] to GLA

[40] or GLB[1] to GLB

[40] can be output.

[0075] On the other hand, when the selection signal SEL_B2 is input to switch circuits 18 and 19, terminals SWIN1 and LIN2 become conductive in switch circuit 18. Also, in switch circuit 19, terminals RIN2 and SWIN2 become conductive.

[0076] Therefore, the signal potential SROUT output by the fourth-stage flip-flop circuit 10 is input to the 37th-stage flip-flop circuit 10 as a shift signal LIN. The signal potential SROUT output by the 37th-stage flip-flop circuit 10 is input to the fourth-stage flip-flop circuit 10 as a reset signal RIN.

[0077] In other words, by inputting the selection signal SEL_B2, the output operation of the signal potentials in blocks 31 and 33 shown in Figure 1 is selected, and the signal potentials GLA[1] to GLA[4] and signal potentials GLA

[37] to GLA

[40] , or signal potentials GLB[1] to GLB[4] and signal potentials GLB

[37] to GLB

[40] can be output.

[0078] Table 1 summarizes the selection signal input to semiconductor device 20a and the circuit that outputs the signal potential, as described above.

[0079] [Table 1]

[0080] Although the above example shows that there is only one path for the signal potential output from circuits 13 and 14, by increasing the number of control signals PWC input to switch circuit 12, circuit 13, and circuit 14, it is possible to output signal potentials from two or more paths at different timings.

[0081] Figure 11 is a block diagram of a semiconductor device 20b showing an example where circuits 13 and 14 each output two signal potentials. Circuit 13 can output signal potentials GLA1 and GLA2 at different timings. Similarly, circuit 14 can output signal potentials GLB1 and GLB2 at different timings.

[0082] The semiconductor device 20b differs from semiconductor device 20a shown in Figures 3 and 4 in that the input signal includes pulse width control signals PWCA (PWCA1 to PWCA4) and PWCB (PWCB1 to PWCB4). Also, the configurations of switch circuits 12, 13, and 14 differ from those of semiconductor device 20a. However, the configurations of the flip-flop circuit 10, switch circuits 16, 17, and switch circuits 18, 19 (not shown) in semiconductor device 20b, as well as the configuration of the connections between these elements, can be the same as those of semiconductor device 20a.

[0083] Figure 12A shows a block diagram of the switch circuit 12 of the semiconductor device 20b, and Figure 12B shows an example of a circuit diagram of the switch circuit 12. Refer to Figure 12B for the connection configuration of the transistors and capacitors constituting the switch circuit 12; their explanation is omitted here.

[0084] The input signals are pulse width control signals PWCA and PWCB, selection signal SEL_A and selection signal SEL_B, and signal potentials 01 and FN input from the flip-flop circuit 10. Selection signals SEL_A and SEL_B are signals that select whether to output the signal potential to the outside from either circuit 13 or circuit 14.

[0085] The output signals are signal potentials 01_A, 01_B, FN_A, FN_B, pulse width control signal A_PWCA, pulse width control signal B_PWCA, pulse width control signal A_PWCB, and pulse width control signal B_PWCB. Inputting the selection signal SEL_A generates signal potentials 01_A, FN_A, pulse width control signal A_PWCA, and pulse width control signal A_PWCB. Inputting the selection signal SEL_B generates signal potentials 01_B, FN_B, pulse width control signal B_PWCA, and pulse width control signal B_PWCB.

[0086] Signal potentials 01_A and 01_B are used to generate the signal potentials output by circuit 13 or circuit 14. Signal potentials FN_A and FN_B are used to control the transistors that act as pull-down resistors in circuit 13 or circuit 14. Pulse width control signals A_PWCA, A_PWCB, and pulse width control signals B_PWCA, B_PWCB are used to control the pulse width and timing of the signal potentials output by circuit 13 or circuit 14.

[0087] Figure 13A shows a block diagram of circuit 13 in the semiconductor device 20b, and Figure 13B shows an example of a circuit diagram of circuit 13. Refer to Figure 13B for the connection configuration of the transistors and capacitors constituting circuit 13; their explanation is omitted here.

[0088] The input signals are signal potential 01_A, signal potential FN_A, and pulse width control signals A_PWCA and A_PWCB, which are input from the switch circuit 12.

[0089] The signal potential GLA1 can be output to a wiring connected to an external circuit by inputting signal potential 01_A and pulse width control signal A_PWCA. Furthermore, the signal potential FN_A and pulse width control signal A_PWCA can activate a transistor equivalent to a pull-down resistor, stabilizing the potential of the wiring to VSS.

[0090] Furthermore, by inputting signal potential 01_A and pulse width control signal A_PWCB, the signal potential GLA2 can be output to wiring connected to an external circuit. Additionally, by inputting signal potential FN_A and pulse width control signal A_PWCB, a transistor equivalent to a pull-down resistor can be activated, stabilizing the potential of the wiring to VSS.

[0091] Therefore, the signal potentials GLA1 and GLA2 can be output externally at different timings.

[0092] Figure 14A shows a block diagram of circuit 14 of the semiconductor device 20b, and Figure 14B shows an example of a circuit diagram of circuit 14. Refer to Figure 14B for the connection configuration of the transistors and capacitors constituting circuit 14; their explanation is omitted here.

[0093] The input signals are signal potentials 01_B and FN_B, and pulse width control signals B_PWCA and B_PWCB, which are input from the switch circuit 12.

[0094] The signal potential GLB1 can be output to a wiring connected to an external circuit by inputting the signal potential 01_B and the pulse width control signal B_PWCA. Furthermore, the signal potential FN_B and the pulse width control signal B_PWCA can activate a transistor equivalent to a pull-down resistor, stabilizing the potential of the wiring to VSS.

[0095] Furthermore, by inputting signal potential 01_B and pulse width control signal B_PWCB, the signal potential GLB2 can be output to wiring connected to an external circuit. Additionally, by inputting signal potential FN_B and pulse width control signal B_PWCB, a transistor equivalent to a pull-down resistor can be activated, stabilizing the potential of the wiring to VSS.

[0096] Therefore, the signal potentials GLB1 and GLB2 can be output externally at different timings.

[0097] The semiconductor devices 20a and 20b described above can use an n-channel transistor as a component. The semiconductor material that can be used in the channel formation region of the n-channel transistor is preferably silicon or a metal oxide.

[0098] In transistors that use silicon for the channel formation region (hereinafter referred to as Si transistors), amorphous silicon, microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon can be used. When the transistor is mounted on an insulating surface such as a glass substrate, amorphous silicon or polycrystalline silicon is preferred.

[0099] Amorphous silicon is preferable for use in large devices because the technology for forming it on large-area glass substrates using plasma CVD (chemical vapor deposition) has been established. Polycrystalline silicon, on the other hand, can form high-mobility transistors, allowing for smaller transistor sizes, and is therefore preferable for use in high-resolution, small to medium-sized devices. Furthermore, transistors using polycrystalline silicon can operate at high speeds, making them suitable for forming drive circuits. Specific examples of such devices include display devices.

[0100] High-quality polycrystalline silicon can be easily obtained by using processes such as laser crystallization. Alternatively, high-quality polycrystalline silicon can also be obtained by solid-phase growth, which involves adding a metal catalyst such as nickel or palladium to amorphous silicon and heating it. Furthermore, the crystallinity of polycrystalline silicon formed by solid-phase growth using a metal catalyst may be further enhanced by laser irradiation. Since the metal catalyst remains in the polycrystalline silicon and degrades the electrical properties of the transistor, it is preferable to create regions outside the channel formation area where phosphorus or a noble gas is added, thereby trapping the metal catalyst in these regions.

[0101] On the other hand, transistors using metal oxides as the channel formation region (hereinafter referred to as OS transistors) have higher mobility than transistors using amorphous silicon as the channel formation region. Furthermore, since they can be formed on insulating surfaces such as glass substrates using sputtering methods, they can be easily adapted for large-area devices. Therefore, OS transistors can be widely applied to devices ranging from small to large.

[0102] Because OS transistors have a large energy gap in their semiconductor layer, they can exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm channel width). Therefore, when OS transistors are used in the pixel circuits of display devices, the data potential can be maintained in the pixel circuit for a long period of time.

[0103] Therefore, proper image display can be achieved even when the frame frequency is reduced. For example, by using a first frame frequency (e.g., 60Hz or higher) for displaying moving images and switching to a second frame frequency lower than the first (e.g., around 1 to 10Hz) for displaying still images, the power consumption of the display device can be reduced.

[0104] A semiconductor device according to one aspect of the present invention can be used in a driving circuit (e.g., a low driver) of a display device. Since the driving circuit is formed using the same process as the pixel circuit, the mounting of IC chips and other components are unnecessary, making it possible to form a display device with a narrow bezel. In other words, forming a semiconductor device according to one aspect of the present invention together with a pixel circuit using OS transistors is effective in narrowing the bezel of a display device.

[0105] Furthermore, the configuration is not limited to forming all transistors in the pixel circuit and drive circuit with Si transistors or OS transistors; one of the pixel circuit and drive circuit may be formed with Si transistors and the other with OS transistors. Alternatively, some of the transistors in the pixel circuit and drive circuit may be formed with either Si transistors or OS transistors, and the other transistors with either Si transistors or OS transistors. The above configuration should be appropriately determined according to the functions required of the display device.

[0106] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0107] OS transistors have characteristics that differ from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short-channel effects, allowing for the formation of highly reliable circuits. Furthermore, OS transistors are less prone to variations in electrical properties caused by crystalline non-uniformity, which is a problem in Si transistors.

[0108] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using the ALD (Atomic Layer Deposition) method.

[0109] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn-based oxide by the sputtering method preferably satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3::2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the formed semiconductor layer includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0110] As the semiconductor layer, an oxide semiconductor with a low carrier concentration is used. For example, the semiconductor layer has a carrier concentration of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 or less, and an oxide semiconductor with a carrier concentration of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0111] However, this is not limited to these, and any composition appropriate to the semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor should be used. Furthermore, in order to obtain the semiconductor characteristics of the transistor, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriately.

[0112] In oxide semiconductors that constitute a semiconductor layer, the presence of silicon or carbon, which are Group 14 elements, increases oxygen vacancies and causes n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0113] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0114] Furthermore, if nitrogen is present in the oxide semiconductor constituting the semiconductor layer, electrons, which act as carriers, are generated, increasing the carrier concentration and making it easier for the transistor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻⁶. 18 atoms / cm 3 The following is preferable:

[0115] Furthermore, if the oxide semiconductor constituting the semiconductor layer contains hydrogen, it can react with oxygen bonded to metal atoms to form water, thus potentially creating oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor may exhibit normally-on characteristics. Moreover, a defect containing hydrogen can function as a donor, generating electrons as carriers. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics.

[0116] Defects where hydrogen fills an oxygen vacancy can function as donors in oxide semiconductors. However, quantitatively evaluating such defects is difficult. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0117] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0118] Furthermore, the semiconductor layer may have a non-single-crystal structure, for example. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, while CAAC-OS has the lowest defect level density.

[0119] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0120] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0121] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS, which is one form of a non-single-crystal semiconductor layer.

[0122] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0123] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0124] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0125] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0126] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is any number).

[0127] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0128] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0129] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0130] Note that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0131] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0132] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable; for example, an oxygen gas flow rate ratio of 0% or more and less than 30%, preferably 0% or more and 10% or less, is preferable.

[0133] CAC-OS is characterized by the absence of a clear peak when measured using the θ / 2θ scan method, an out-of-plane X-ray diffraction (XRD) measurement technique. In other words, X-ray diffraction measurements indicate that no orientation in the ab-plane direction or the c-axis direction of the measurement region is observed.

[0134] Furthermore, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness (ring region) and multiple bright spots are observed within this ring region. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0135] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0136] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0137] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1 In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, In X2 Zn Y2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved when regions with this as the main component are distributed in a cloud-like manner within the oxide semiconductor.

[0138] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InOX1 is a region with high insulation compared to the region where it is the main component. That is, GaO X3 and the like being the main component distributed in the oxide semiconductor can suppress the leakage current and realize good switching operation.

[0139] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 and the like, and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily to realize a high on-current (I on ) and a high field-effect mobility (μ).

[0140] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0141] Also, the semiconductor device 20a and the semiconductor device 20b described above use an n-channel type transistor as a component, but a p-channel type transistor may also be used as a component.

[0142] FIG. 15 is a block diagram of a semiconductor device 20c using a p-channel type transistor as a circuit component. The connection configuration of each element circuit is the same as that of the semiconductor device 20a shown in FIGS. 3 and 4, and only a part is shown in FIG. 15. In the semiconductor device 20c, except that a p-channel type transistor is used as a circuit component, the configurations of the switch circuit 16 and the switch circuit 17 and the signals input thereto are different from those of the semiconductor device 20a.

[0143] Figure 16A shows a block diagram of the flip-flop circuit 10, and Figure 16B shows an example of a circuit diagram of the flip-flop circuit 10 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting the flip-flop circuit 10 is shown in Figure 16B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 5B. Note that the flip-flop circuit 10 shown in Figure 16B is supplied with a power supply potential that is the inverse of the power supply potential (VDD, VSS) shown in Figure 5B.

[0144] Figure 17A shows a block diagram of the switch circuit 12, and Figure 17B shows an example of a circuit diagram of the switch circuit 12 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting the switch circuit 12 is shown in Figure 6B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 6B. Note that the switch circuit 12 shown in Figure 17B is supplied with a power supply potential that is the inverse of the power supply potential (VDD, VSS) shown in Figure 6B.

[0145] Figure 18A shows a block diagram of circuit 13, and Figure 18B shows an example of a circuit diagram of circuit 13 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting circuit 13 is shown in Figure 7B, and its explanation is omitted here. Furthermore, explanations of the input and output signals can be found in the explanation in Figure 7B. Note that the circuit 13 shown in Figure 18B is supplied with a power supply potential that is the inverted version of the power supply potentials (VDD, VSS) shown in Figure 7B.

[0146] Figure 18C shows a block diagram of circuit 14, and Figure 18D shows an example of a circuit diagram of circuit 14 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting circuit 14 is shown in Figure 18D, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 7D. Note that the circuit 14 shown in Figure 18D is supplied with a power supply potential that is the inverse of the power supply potential (VDD, VSS) shown in Figure 7D.

[0147] Figure 19A shows a block diagram of the switch circuit 16, and Figure 19B shows an example of a circuit diagram of the switch circuit 16 composed of p-channel transistors. Refer to Figure 19B for the connection configuration of the transistors constituting the switch circuit 16; the explanation is omitted here.

[0148] The input signals are selection signals SEL_A, SEL_B1, and SEL_B2. When either selection signal SEL_B1 or SEL_B2 is input, a signal potential SEL_B is generated. This signal potential SEL_B is input to the switch circuit 12 described above. When selection signal SEL_B is input to the switch circuit 12, the output of the signal potential from circuit 14 to the outside can be enabled. When selection signal SEL_A is input, no valid signal potential SEL_B is generated.

[0149] Figure 19C shows a block diagram of the switch circuit 17, and Figure 19D shows an example of a circuit diagram of the switch circuit 17 composed of p-channel transistors. Refer to Figure 19D for the connection configuration of the transistors constituting the switch circuit 17; a detailed explanation is omitted.

[0150] The input signals are selection signals SEL_A, SEL_B1, and SEL_B2. When either selection signal SEL_B1 or SEL_B2 is input, a signal potential SEL_C is generated. Signal potential SEL_C is input to switch circuits 18 and 19, which will be described later. When selection signal SEL_A is input, no valid signal potential SEL_B is generated.

[0151] Figure 20A shows a block diagram of the switch circuit 18, and Figure 20B shows an example of a circuit diagram of the switch circuit 18 composed of p-channel transistors. The connection configuration of the transistors constituting the switch circuit 18 is shown in Figure 20B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 9B. Note that the circuit 14 shown in Figure 20B is supplied with a power supply potential that is the inverted version of the power supply potential (VDD, VSS) shown in Figure 9B.

[0152] Figure 21A shows a block diagram of the switch circuit 19, and Figure 21B shows an example of a circuit diagram of the switch circuit 19 composed of p-channel transistors. The connection configuration of the transistors constituting the switch circuit 19 is shown in Figure 21B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 10B. Note that the circuit 14 shown in Figure 21B is supplied with a power supply potential that is the inverted version of the power supply potential (VDD, VSS) shown in Figure 10B.

[0153] Although the above example shows that there is only one path for the signal potential output from circuits 13 and 14, by increasing the number of control signals PWC input to switch circuit 12, circuit 13, and circuit 14, it is possible to output signal potentials from two or more paths at different timings.

[0154] Figure 22 is a block diagram of a semiconductor device 20d showing an example where there are two paths for the signal potentials output from circuits 13 and 14. Circuit 13 can output signal potentials GLA1 and GLA2 at different timings. Similarly, circuit 14 can output signal potentials GLB1 and GLB2 at different timings.

[0155] The semiconductor device 20d differs from semiconductor device 20c shown in Figure 5 in that the input signal includes pulse width control signals PWCA (PWCA1 to PWCA4) and pulse width control signals PWCB (PWCB1 to PWCB4). Also, the configurations of switch circuits 12, 13, and 14 differ from those of semiconductor device 20c. Note that the configurations of the flip-flop circuit 10, switch circuits 16, 17, and switch circuits 18, 19 (not shown) of semiconductor device 20d, and the configuration of the connections between these elements, can be the same as those of semiconductor device 20c.

[0156] Figure 23A shows a block diagram of the switch circuit 12 in the semiconductor device 20d, and Figure 23B shows an example of a circuit diagram of the switch circuit 12 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting the switch circuit 12 is shown in Figure 23B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 12B. Note that the switch circuit 12 shown in Figure 23B is supplied with a power supply potential that is the inverted version of the power supply potentials (VDD, VSS) shown in Figure 12B.

[0157] Figure 24A shows a block diagram of circuit 13 in semiconductor device 20d, and Figure 24B shows an example of a circuit diagram of circuit 13 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting circuit 13 is shown in Figure 24B, and its explanation is omitted. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 13B. Note that the circuit 13 shown in Figure 23B is supplied with a power supply potential that is the inverted version of the power supply potential (VDD, VSS) shown in Figure 13B.

[0158] Figure 25A shows a block diagram of circuit 14 in semiconductor device 20d, and Figure 25B shows an example of a circuit diagram of circuit 14 composed of p-channel transistors. The connection configuration of the transistors and capacitors constituting circuit 14 is shown in Figure 25B, and its explanation is omitted here. Furthermore, the explanation of the input and output signals can be found in the explanation in Figure 14B. Note that the circuit 14 shown in Figure 23B is supplied with a power supply potential that is the inverted version of the power supply potential (VDD, VSS) shown in Figure 14B.

[0159] Furthermore, it is preferable to use Si transistors for p-channel transistors. In particular, it is preferable to use polycrystalline silicon or single-crystal silicon, which can form high-mobility transistors even in the p-channel type.

[0160] Furthermore, the configuration is not limited to forming all transistors in the pixel circuit and drive circuit with Si transistors; the drive circuit may be formed with Si transistors and the pixel circuit with OS transistors. Alternatively, some transistors in the pixel circuit and drive circuit may be formed with either Si transistors or OS transistors, and the other transistors with either Si transistors or OS transistors. The above configuration should be determined as appropriate according to the functions required of the display device.

[0161] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0162] (Embodiment 2) This embodiment describes a display device to which the semiconductor device described in Embodiment 1 can be applied.

[0163] Figure 26 is a diagram illustrating a display device according to one embodiment of the present invention. The display device includes a pixel array 23 having pixels 24 arranged in the column and row directions, and circuits 40, 41, and 42. Note that the wiring connecting each block shown in Figure 26 is simplified and may differ from the actual number of wires.

[0164] Pixel 24 has circuits 25 and 26. Circuit 25 has the function of emitting light for display. Circuit 26 has the function of detecting light. Circuits 25 and 26 can also be called sub-pixels.

[0165] Circuit 25 has a light-emitting device (also called a light-emitting element) that emits visible light. Preferably, an EL element such as an OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) is used as the light-emitting device. Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (Thermally Activated Delayed Fluorescence (TADF) materials). Alternatively, an LED such as a microLED (Light Emitting Diode) can be used as the light-emitting device.

[0166] Circuit 26 has a light-receiving device (also called a light-receiving element). For example, a pn-type or pin-type photodiode can be used as the light-receiving device. A photoelectric conversion element that detects incident light and generates an electric charge can be used as the light-receiving device. In a light-receiving device, the amount of charge generated is determined based on the amount of incident light.

[0167] As the light-receiving device, it is preferable to use an organic photodiode having an organic compound in its photoelectric conversion layer. Organic photodiodes are easy to make thin, light, and large in area. Also, because they offer a high degree of freedom in shape and design, they can be applied to various display devices. Alternatively, photodiodes using amorphous silicon, crystalline silicon (single-crystal silicon, polycrystalline silicon, microcrystalline silicon, etc.), metal oxides, etc., can also be used as the light-receiving device.

[0168] When an organic compound is used in the photoelectric conversion layer of a photodiode, sensitivity from ultraviolet to infrared light can be achieved by appropriately selecting the material. When amorphous silicon is used in the photoelectric conversion layer, sensitivity is mainly to visible light, while when crystalline silicon is used, sensitivity is from visible light to infrared light. Because metal oxides have a large energy gap, when a metal oxide is used in the photoelectric conversion layer, it has high sensitivity mainly to light with higher energy than visible light. As a metal oxide, for example, In-M-Zn based oxides as described in Embodiment 1 can be used.

[0169] In one aspect of the present invention, an organic EL element is used as the light-emitting device and an organic photodiode is used as the light-receiving device. The organic photodiode has many layers that can share the same configuration as the organic EL element. Therefore, the light-receiving device can be incorporated into the display device without significantly increasing the manufacturing process. For example, the photoelectric conversion layer of the light-receiving device and the light-emitting layer of the light-emitting device may be manufactured separately, while the other layers may have the same configuration for both the light-emitting and light-receiving devices.

[0170] Circuit 40 is a low driver (gate driver) for driving circuits 25 and 26. Circuit 40 can be one of the semiconductor devices 20a, 20b, 20c, or 20d described in Embodiment 1.

[0171] Circuit 41 is a column driver (source driver) that supplies image data and other data to circuit 25. For example, a shift register circuit or a decoder circuit can be used for circuit 41.

[0172] Circuit 42 is a data readout circuit for the data output by circuit 26. Circuit 42 may, for example, have an A / D conversion circuit and have the function of converting the analog data output from circuit 26 into digital data. Circuit 42 may also have a CDS circuit that performs correlated double sampling on the output data of circuit 26. It may also have a selection circuit (multiplexer circuit) between the CDS circuit and the A / D conversion circuit. It may also have a column driver that outputs the digital data to the outside.

[0173] Circuit 26 can function as an input interface. Circuit 26 has a light-receiving device and can read positional information of objects near the display device from changes in the amount of light reaching the pixel array 23. Therefore, it can perform operations equivalent to a touch panel without physical contact. Furthermore, it can perform actions such as pointer movements without physical contact.

[0174] Alternatively, the object may be brought into contact with the display device, and imaging data may be acquired by circuit 26. By bringing the object into contact with the display device, imaging data such as fingerprints or palm prints can be acquired at high resolution. In other words, a biometric authentication function can be added to the display device. In one embodiment of the present invention, the imaging data can be obtained by receiving the light emitted by circuit 25 and reflected by the object with circuit 26. In this case, the light emitted by circuit 25 is preferably green light or white light.

[0175] Figure 27A shows an example of a pixel circuit PIX1 applicable to circuit 25. The pixel circuit PIX1 includes a light-emitting device EL, transistors M1, M2, M3, and capacitor C1. Here, an example using a light-emitting diode as the light-emitting device EL is shown. It is preferable to use an organic EL element that emits visible light as the light-emitting device EL.

[0176] Transistor M1 has its gate electrically connected to wiring G1, one of its source or drain electrically connected to wiring S1, and the other of its source or drain electrically connected to one electrode of capacitor C1 and the gate of transistor M2. One of the source or drain of transistor M2 is electrically connected to wiring V2, and the other is electrically connected to the anode of light-emitting device EL and one of the source or drain of transistor M3. Transistor M3 has its gate electrically connected to wiring G2, and the other of its source or drain electrically connected to wiring V0. The cathode of light-emitting device EL is electrically connected to wiring V1.

[0177] A constant potential is supplied to wiring V1 and wiring V2, respectively. Light emission can be achieved by setting the anode side of the light-emitting device EL to a high potential and the cathode side to a low potential. Transistor M1 is controlled by the signal supplied to wiring G1 and functions as a selection transistor to control the selected state of the pixel circuit PIX1. Transistor M2 functions as a drive transistor that controls the current flowing to the light-emitting device EL according to the potential supplied to the gate.

[0178] When transistor M1 is conducting, the potential supplied to wiring S1 is supplied to the gate of transistor M2, and the luminescence brightness of the light-emitting device EL can be controlled according to that potential. Transistor M3 is controlled by a signal supplied to wiring G2. The potential between transistor M3 and the light-emitting device EL can be reset to a constant potential supplied from wiring V0, and the potential can be written to the gate of transistor M2 while the source potential of transistor M2 is stabilized.

[0179] Figure 27B shows an example of a pixel circuit PIX2 that can be applied to circuit 25. The pixel circuit PIX2 has a boost function. The pixel circuit PIX2 includes a light-emitting device EL, transistors M4, M5, M6, M7, capacitors C2 and C3.

[0180] Transistor M4 has its gate electrically connected to wiring G1, one of its source or drain electrically connected to wiring S1, and the other of its source or drain electrically connected to one electrode of capacitor C2, one electrode of capacitor C3, and the gate of transistor M7. Transistor M5 has its gate electrically connected to wiring G2, one of its source or drain electrically connected to wiring VRW, and the other of its source or drain electrically connected to the other electrode of capacitor C2 and one of its source or drain of transistor M6.

[0181] The gate of transistor M6 is electrically connected to wiring G1, and the other of its source or drain is electrically connected to the other electrode of capacitor C3, one of the source or drain of transistor M7, and the anode of light-emitting device EL. The other of the source or drain of transistor M7 is electrically connected to wiring V2.

[0182] Transistors M4 and M6 are controlled by signals supplied to wiring G1, and transistor M5 is controlled by signals supplied to wiring G2. Transistor M7 functions as a drive transistor that controls the current flowing to the light-emitting device EL in accordance with the potential supplied to the gate.

[0183] By making transistors M5 and M6 conduct, the potential between transistor M7 and the light-emitting device EL can be reset to a constant potential (e.g., reset potential VRES) supplied from the wiring VRW. Therefore, the potential of wiring S1 can be written to the gate of transistor M7 while the source potential of transistor M7 is stabilized. In addition, by setting the reset potential VRES to the same potential as wiring V1, or to a potential lower than wiring V1, the light emission of the light-emitting device EL can be suppressed.

[0184] The pixel circuit PIX2 can increase the light emission intensity of the light-emitting device EL. The boost function of the pixel circuit PIX2 is explained using the timing chart shown in Figure 27C. Note that the node to which the gate of transistor M7 is connected is called node ND.

[0185] First, when the potentials of wires G1 and G2 are set to "H" (high potential), transistor M4 conducts, and the potential D1 of wire S1 is supplied to node ND. Also, transistors M5 and M6 conduct, and the reset potential VRES is supplied to the other electrode of capacitor C2.

[0186] Next, when the potential of wiring G1 is set to "L" (low potential), transistors M4 and M6 become non-conductive, and node ND becomes floating. At this time, capacitor C2 maintains a potential of D1-VRES.

[0187] Then, when the potential of wiring VRW is changed from the reset potential VRES to the boost potential VW, the change in the potential of the other electrode of capacitor C2 (VW-VRES) is added to the potential of node ND due to capacitive coupling.

[0188] Note that the actual potential increase at node ND is determined according to the capacitance ratio of node ND to capacitor C2, (C2 / (C ND +C2)) × (VW-VRES). Here, C ND (C2 / (C)) is the capacitance of node ND, and C2 is the capacitance of capacitor C2. If C2 is sufficiently large, then (C2 / (C)) ND +C2)) approximates 1. Also, if the reset potential VRES = 0, the increase in potential at node ND becomes VW. Therefore, node ND is boosted from potential D1 to potential D1 + VW.

[0189] By boosting the potential of the node ND, a larger current can be supplied to the light-emitting device (EL), thereby increasing the luminescence brightness. When the object being imaged is brought into contact with the display device, increasing the luminescence brightness reduces dark areas, allowing for the acquisition of more detailed imaging data. Furthermore, having a voltage boosting function at the pixel level eliminates the need to supply a high voltage from the source driver, thus reducing power consumption. In addition, since a high-output source driver is not required, manufacturing costs can be reduced.

[0190] Figure 27D shows an example of a pixel circuit PIX3 that can be applied to circuit 26. The pixel circuit PIX3 includes a light-receiving device PD, transistors M9, M10, M11, M12, and capacitor C4. Here, an example is shown in which a photodiode is used as the light-receiving device PD.

[0191] The photodetector PD has its cathode electrically connected to wiring V1 and its anode electrically connected to either the source or drain of transistor M9. Transistor M9 has its gate electrically connected to wiring G4 and its other source or drain electrically connected to one electrode of capacitor C4, either the source or drain of transistor M10, and the gate of transistor M11. Transistor M10 has its gate electrically connected to wiring G5 and its other source or drain electrically connected to wiring V4. Transistor M11 has its source or drain electrically connected to wiring V3 and its other source or drain electrically connected to either the source or drain of transistor M12. Transistor M12 has its gate electrically connected to wiring G6 and its other source or drain electrically connected to wiring OUT.

[0192] Constant potentials are supplied to wirings V1, V3, and V4, respectively. When the photodetector PD is driven with reverse bias, a potential lower than that of wiring V1 is supplied to wiring V4. Transistor M10 is controlled by a signal supplied to wiring G5 and has the function of resetting the potential of the node (charge readout section) connected to the gate of transistor M11 to the potential supplied to wiring V4. Transistor M9 is controlled by a signal supplied to wiring G4 and has the function of controlling the timing at which the potential of the above node changes according to the amount of charge accumulated in the photodetector PD. Transistor M11 functions as an amplifying transistor that provides an output according to the potential of the above node. Transistor M12 is controlled by a signal supplied to wiring G6 and functions as a selection transistor for reading the output according to the potential of the above node with an external circuit connected to wiring OUT.

[0193] Here, it is preferable to use OS transistors for the transistors in the pixel circuits PIX1 to PIX3. OS transistors can achieve extremely small off-currents. Due to the small off-current characteristics of OS transistors, it is possible to retain the charge stored in the capacitor connected in series with the transistor for a long period of time.

[0194] In particular, it is preferable to use OS transistors for transistors M1, M4, M5, M6, M9, and M10, which have current paths connected in series with capacitors C1, C2, or C3. By using OS transistors in circuit 26, long-term charge retention becomes possible, allowing the application of a global shutter method that performs charge accumulation operation simultaneously at all pixels without complicating the circuit configuration and operating method. Furthermore, by similarly using OS transistors for the other transistors, manufacturing costs can be reduced.

[0195] Furthermore, Si transistors can be used in the transistors of the pixel circuits PIX1 to PIX3. In particular, using highly crystalline silicon such as single-crystal silicon or polycrystalline silicon is preferable because it can achieve high field-effect mobility, enabling faster operation.

[0196] Alternatively, one or more of the transistors in the pixel circuits PIX1 to PIX3 may be OS transistors, while the others are Si transistors.

[0197] Furthermore, when using OS transistors, a back gate may be provided for each transistor, as shown in Figure 27E. By supplying the same potential to the back gate as to the front gate, the on-current can be increased. Also, by supplying a constant potential to the back gate, the threshold voltage of the transistor can be adjusted. This configuration of providing a back gate to the transistor can also be applied to Figures 27A to 27D. It can also be applied to the semiconductor device that can use the OS transistor shown in Embodiment 1.

[0198] Although Figures 27A to 27E illustrate an example using an n-channel transistor, a p-channel transistor can also be used.

[0199] Next, the configuration of the connection between circuit 40 and pixels 24 (circuits 25 and 26), and their operation will be described. As mentioned above, the semiconductor devices 20a to 20d described in Embodiment 1 can be used for circuit 40. Here, an example using semiconductor device 20b for circuit 40 will be described.

[0200] Figure 28 shows the connection configuration between a part of circuit 40 (a single-stage flip-flop circuit 10 and an output circuit 11 (switch circuits 12, 13, and 14)) and circuits 25 and 26 of the pixel 24. Note that the pixel circuit PIX2 shown in Figure 27B is used as circuit 25, and the pixel circuit PIX3 shown in Figure 27C is used as circuit 26.

[0201] Figure 28 illustrates a configuration in which one circuit 25 and one circuit 26 are provided in each pixel 24. This configuration can be used when the display and imaging data are in grayscale. When displaying in color, at least one circuit 25 emitting each of the three primary colors of light is required. Therefore, as shown in Figure 29A, a configuration can be used in which the pixel 24 is provided with a circuit 25 (R) that emits red light, a circuit 25 (G) that emits green light, and a circuit 25 (B) that emits blue light.

[0202] In the configuration shown in Figure 29A, the circuit 25 can be formed by using a light-emitting device EL that emits red, green, or blue light. Alternatively, the light-emitting device EL in the circuit 25 may be a light-emitting device that emits white light, and a color filter for red, green, or blue light may be provided on the light-emitting device.

[0203] Furthermore, when acquiring color imaging data, as shown in Figure 29B, the pixel 24 can be configured to have a circuit 26(R) for red light imaging, a circuit 26(G) for green light imaging, and a circuit 26(B) for blue light imaging. These can be formed by using a light-emitting device having a photoelectric conversion layer that absorbs one color of light (red, green, or blue) more strongly than the other colors of light as the light-receiving device PD of the circuit 26. Alternatively, a light-emitting device having a photoelectric conversion layer that absorbs in the red, green, and blue wavelength bands may be used as the light-receiving device PD of the circuit 26, and a red, green, or blue color filter may be provided on the light-receiving device.

[0204] As shown in Figure 28, circuit 13 has an electrical output to wiring G1 and wiring G2. Wiring G1 can be supplied with the signal potential GLA1 output by circuit 13. Wiring G2 can be supplied with the signal potential GLA2 output by circuit 13.

[0205] Circuit 14 has an electrical output to wiring G5 and wiring G6. Wiring G5 can be supplied with the signal potential GLB1 output by circuit 14. Wiring G6 can be supplied with the signal potential GLB2 output by circuit 14.

[0206] Wiring G5 is electrically connected to the gate of transistor M10 in circuit 26. Transistor M10 is a reset transistor that resets the gate potential of transistor M11 to the potential of wiring V4. As mentioned above, by using OS transistors for transistors M9 and M10, a global shutter method can be applied that performs charge accumulation operation simultaneously at all pixels.

[0207] In a global shutter system, since a reset operation is performed simultaneously for all pixels, a signal potential must be supplied from circuit 40 to all circuits 26 to simultaneously conduct transistor M10. In such cases, it is preferable to configure circuit 14 as shown in Figures 30A and 30B.

[0208] In this configuration, when the signal potential FN_B is input and the reset power supply potential RSVSS is inverted from a low potential to a high potential, a high potential can be output as the signal potential GLB1. This operation is only effective when the power supply potential RSVSS is inverted from a low potential to a high potential, and it is possible to supply a signal potential from circuit 40 to all circuits 26 simultaneously to conduct transistor M10.

[0209] Furthermore, a selection circuit 50 is electrically connected to the wiring VRW. The selection circuit 50 can supply either the reset potential VRES or the boost potential VW to the wiring VRW.

[0210] Next, the operation of the circuit 40 and pixels 24 shown in Figures 26 and 28 will be explained using the timing charts shown in Figures 31 to 34. The operation will be explained in separate parts: writing image data to all circuits 25 (normal emission, mode A), writing boosted data to all circuits 25 (high-brightness emission, mode B), reading out the captured data from all circuits 26 (mode C), and reading out the captured data from a specific circuit 26 (mode D). The number of rows of pixels 24 is assumed to be 2340, and the circuit 40 is assumed to be able to output a signal potential to drive the pixels 24 of that number of rows.

[0211] First, the writing of image data (normal light emission, mode A) will be explained using the timing chart shown in Figure 31. The input signals listed in the timing chart are the clock signals CLK1 to CLK4, pulse width control signals PWCA1 to PWCA4, pulse width control signals PWCB1 to PWCB4, and start pulse signal SP, all input to circuit 40. In modes A and B, the reset power supply potential RSVSS is always kept at a low potential.

[0212] The output signals shown in the timing chart are the signal potentials GLA1[1] to GLA1

[2340] , signal potentials GLA2[1] to GLA2

[2340] , signal potential GLA1[DUM], and signal potential GLA2[DUM] of the dummy stage, output by circuit 13 of circuit 40.

[0213] Furthermore, the timing chart shows the signal potentials GLB1[1] to GLB1

[2340] , signal potentials GLB2[1] to GLB2

[2340] , signal potentials GLB1[DUM], and signal potentials GLB2[DUM] of the dummy stage output by circuit 14 of circuit 40. However, during the operation timing of modes A and B, no signal potential is output from circuit 14 that causes the transistors in circuit 26 to conduct.

[0214] Mode A operation utilizes the first mode of operation of the semiconductor device 20 as described in Figure 1. First, a start pulse signal is input, followed by clock signals CLK1 to CLK4 being input sequentially. In addition, pulse width control signals PWCA1 to PWCA4 and pulse width control signals PWCB1 to PWCB4 are input sequentially in parallel with the clock signals CLK1 to CLK4.

[0215] In accordance with the input signal, pulses of signal potential GLA1 and signal potential GLA2 are output sequentially from the first stage to the dummy stage with the same pulse width and timing. Signal potential GLA1 is supplied to wiring G1, causing transistors M4 and M6 of circuit 25 to conduct. Signal potential GLA2 is supplied to wiring G2, causing transistor M5 of circuit 25 to conduct. In addition, the selection circuit 50 supplies a reset potential VRES (for example, a low potential such as 0V) to wiring VRW (see Figure 28).

[0216] At this time, the reset potential VRES is supplied to the source of transistor M7 in circuit 25, and the gate (node ​​ND) of transistor M7 becomes the data potential supplied from wiring S1. In other words, the data potential can be written to node ND while the source potential of transistor M7 is stable. The light-emitting device EL emits light according to this data potential.

[0217] The above is an explanation of Mode A.

[0218] Next, we will explain the writing of boost data (high-brightness emission, mode B) using the timing chart shown in Figure 32.

[0219] Mode B operation utilizes the first mode of operation of the semiconductor device 20 as described in Figure 1. First, a start pulse signal is input, followed by clock signals CLK1 to CLK4 being input sequentially. In addition, pulse width control signals PWCA1 to PWCA4 and pulse width control signals PWCB1 to PWCB4 are input sequentially in parallel with the clock signals CLK1 to CLK4. The difference from image data writing (normal light emission) is that the pulse width of the pulse width control signal PWCA is smaller than the pulse width of the pulse width control signal PWCB.

[0220] In accordance with the input signal, pulses at signal potential GLA1 and signal potential GLA2 begin to be output at the same timing, but the pulse at signal potential GLA1 finishes outputting first. This operation can be used to perform the boost operation described in Figure 27C. In this operation, the selection circuit 50 switches the potential supplied to the wiring VRW from the reset potential VRES to the potential VW (see Figure 28).

[0221] The above explains the writing of boosted data (high-brightness emission).

[0222] Next, we will explain the readout of imaging data from all circuits 26 (mode C) using the timing chart shown in Figure 33. In mode C, imaging data is read out from the circuits 26 of pixels 24 in all rows, so high-resolution imaging data can be obtained.

[0223] Mode C operation utilizes the first mode, which is the operation of the semiconductor device 20 as described in Figure 1. Mode C operation performs imaging using the light emission from Mode A or Mode B operation. Therefore, it is performed following Mode A or Mode B operation.

[0224] In Mode C operation, the imaging operation is first performed by circuit 26. In this operation, the reset power supply potential RSVSS, as explained in Figure 30, is inverted to a high potential, and a high potential is output from circuit 14 as the signal potential GLB1. This operation allows the charge readout section to be reset simultaneously for all circuits 26. Subsequently, after the exposure period, the charge accumulated in the photodetector is transferred to the charge readout section, and the potential of the charge readout section is maintained. This completes the imaging operation.

[0225] Next, the readout operation of the charge readout unit, which was held by the imaging operation, is performed. In the readout operation, a start pulse signal is first input, followed by clock signals CLK1 to CLK4 being input sequentially. In addition, pulse width control signals PWCA1 to PWCA4 are input sequentially in parallel with the clock signals CLK1 to CLK4. Furthermore, pulse width control signals PWCB1 to PWCB4, which have waveforms with a pulse width smaller than that of pulse width control signals PWCA, are input with a delay to the pulses of pulse width control signals PWCA1 to PWCA4.

[0226] In accordance with the input signal, the pulse of signal potential GLB2 is output first, followed by the pulse of signal potential GLB1 with a delay, and both pulses finish outputting at the same time. This operation can be used to read the potential of the charge readout unit when data is acquired and when the charge readout unit is reset. Using these two data, the difference can be read out by the CDS circuit in circuit 42 shown in Figure 26. This difference is the potential obtained by subtracting the reset potential from the data potential (including the reset potential), and corresponds to data from which noise components have been removed.

[0227] Next, we will explain the readout of imaging data from a specific circuit 26 (mode D) using the timing chart shown in Figure 34. In mode D, imaging data is read out from a specific row of circuit 26, allowing for high-speed acquisition of imaging data.

[0228] Mode D operation utilizes the second mode, which is the operation of the semiconductor device 20 described in Figure 1. In Mode D operation, first, the imaging operation is performed by circuit 26, similar to Mode C.

[0229] Next, the charge readout unit performs a potential readout operation. The input signal is the same as in mode C, and signal potentials GLB1[1:4] and GLB2[1:4] are output sequentially, but signal potentials GLB1[5:36] and GLB2[5:36] are not output. In addition, signal potentials GLB1[37:40] and GLB2[37:40] are output sequentially.

[0230] Therefore, the circuits 26 in the first row (the circuit 26 to which the signal potentials GLB1[1] and GLB2[1] are input) are read out sequentially from the circuit 26 in the first row to the circuit 26 in the fourth row, the circuits 26 in the fifth to the 36th row are not read out, and the circuits 26 in the 37th to the 40th row are read out.

[0231] Note that the operation of modes A, B, C, and D is performed by switching sequentially without overlap. For example, it is possible to switch from mode A to mode B, from mode A to mode D, from mode B to mode C, and from mode C to mode A. Here, the display operation of mode B involves a boost operation, so it has more operation steps than mode A. Also, since mode C performs a read operation from pixels of all rows, it has more operation steps than mode D's read operation from pixels of a specific row.

[0232] Therefore, each mode (A, B, C, and D) may be operated at a frame frequency appropriate for it. For example, mode A may be operated at 60Hz, and then switched to 30Hz to operate in mode B. Alternatively, mode B may be operated at 30Hz, and then switched to 10Hz to operate in mode C. Or, mode A may be operated at 60Hz, and mode D may be operated without changing the frame frequency.

[0233] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0234] (Embodiment 3) In this embodiment, the pixel configuration of the display device described in Embodiment 2 will be described.

[0235] FIG. 35 shows an example of a cross-section of a region including a part of circuit 40, a part of circuit 25, and a part of circuit 26 in pixel 24 of the display device shown in FIG. 26.

[0236] The display device shown in FIG. 35 has a transistor 201, a transistor 205, a transistor 206, a light-emitting device 190, a light-receiving device 110, etc. between a substrate 151 and a substrate 152.

[0237] The substrate 152 and the insulating layer 214 are adhered via an adhesive layer 142. For the encapsulation of the light-emitting device 190 and the light-receiving device 110, a solid encapsulation structure, a hollow encapsulation structure, etc. can be applied. The space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 is filled with an inert gas (such as nitrogen, argon, etc.), and a hollow encapsulation structure is applied. The adhesive layer 142 may be provided overlapping the light-emitting device 190. Also, the region surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 may be filled with a resin different from the adhesive layer 142.

[0238] The light-emitting device 190 has a stacked structure in which a pixel electrode 191, a common layer 112, a light-emitting layer 193, a common layer 114, and a common electrode 115 are stacked in this order from the insulating layer 214 side. The pixel electrode 191 is connected to a conductive layer 222b included in the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has a function of controlling the driving of the light-emitting device 190. The end portion of the pixel electrode 191 is covered by a partition wall 216.

[0239] The light-receiving device 110 has a stacked structure in which the pixel electrode 111, common layer 112, photoelectric conversion layer 113, common layer 114, and common electrode 115 are stacked in that order from the insulating layer 214 side. The pixel electrode 111 is electrically connected to the conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 214. The ends of the pixel electrode 111 are covered by partition walls 216.

[0240] The light emitted by the light-emitting device 190 is projected toward the substrate 152. Light is also incident upon the light-receiving device 110 through the substrate 152 and the space 143. It is preferable to use a material with high transmittance to visible light for the substrate 152.

[0241] Pixel electrodes 111 and 191 can be manufactured using the same material and process. Common layers 112 and 114, and common electrode 115 are used in both the light-receiving device 110 and the light-emitting device 190. The light-receiving device 110 and the light-emitting device 190 can have the same configuration except for the differences in the configuration of the photoelectric conversion layer 113 and the light-emitting layer 193. This allows the light-receiving device 110 to be incorporated into the display device without significantly increasing the manufacturing process.

[0242] A light-shielding layer 148 is provided on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 148 has openings at positions overlapping with the light-receiving device 110 and at positions overlapping with the light-emitting device 190. An optical filter 149, such as a color filter, is provided at the position overlapping with the light-receiving device 110. However, a configuration without the optical filter 149 is also possible.

[0243] Transistors 201, 205, and 206 are all formed on the substrate 151. These transistors can be manufactured using the same materials and processes.

[0244] On the substrate 151, insulating layers 211, 213, 215, and 214 are provided in this order. A portion of insulating layer 211 functions as a gate insulating layer for each transistor. A portion of insulating layer 213 functions as a gate insulating layer for each transistor. Insulating layer 215 is provided covering the transistors. Insulating layer 214 is provided covering the transistors and functions as a planarization layer. The number of gate insulating layers and insulating layers covering the transistors are not limited and may be a single layer or two or more layers, respectively.

[0245] It is preferable to use a material that does not easily allow impurities such as water and hydrogen to diffuse into at least one layer of the insulating layer covering the transistor. This allows the insulating layer to function as a barrier layer. With such a configuration, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0246] It is preferable to use an inorganic insulating film for insulating layer 211, insulating layer 213, and insulating layer 215. As the inorganic insulating film, for example, silicon nitride film, silicon oxynitride film, silicon oxide film, silicon nitride oxide film, aluminum oxide film, or aluminum nitride film can be used. Note that silicon oxynitride film refers to a film in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide film refers to a film in which the nitrogen content is greater than the oxygen content. Alternatively, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, or neodymium oxide film may be used. Furthermore, two or more of the above insulating films may be laminated and used.

[0247] An organic insulating film is preferred for the insulating layer 214, which functions as a planarizing layer. Examples of materials that can be used as the organic insulating film include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

[0248] Here, organic insulating films often have lower barrier properties against impurities compared to inorganic insulating films. Therefore, it is preferable for the organic insulating film to have an opening near the edge of the display device. This can suppress the diffusion of impurities from the edge of the display device through the organic insulating film. Alternatively, the organic insulating film may be formed such that its edge is located inward from the edge of the display device, so that the organic insulating film is not exposed at the edge of the display device.

[0249] In the region 228 shown in Figure 35, an opening is formed in the insulating layer 214. This prevents impurities from diffusing from the outside into the circuit 25 or circuit 26 through the insulating layer 214, even when an organic insulating film is used for the insulating layer 214. Therefore, the reliability of the display device can be improved.

[0250] Transistors 201, 205, and 206 each have a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as source and drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0251] The transistor structure of the display device of this embodiment is not particularly limited. For example, planar transistors, staggered transistors, inverse staggered transistors, etc., can be used. Furthermore, either a top-gate or bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0252] For transistors 201, 205, and 206, a configuration is applied in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying the same signal thereto. Alternatively, a potential for controlling the threshold voltage of the transistor may be applied to one of the two gates, and a potential for driving may be applied to the other.

[0253] The crystallinity of the semiconductor material used for the transistor is not particularly limited either, and any of amorphous semiconductors, single crystal semiconductors, or semiconductors having crystallinity other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having a crystalline region in part) may be used. Using a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0254] The semiconductor layer of the transistor preferably has a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may have silicon. Examples of silicon include amorphous silicon, crystalline silicon (such as low-temperature polysilicon, single crystal silicon, etc.).

[0255] The transistors included in circuit 40, the transistors included in circuit 25, and the transistors included in circuit 26 may have the same structure or different structures.

[0256] A connection portion 204 is provided in a region on substrate 151 where substrate 152 does not overlap. In connection portion 204, wiring 165 is electrically connected to FPC 172a via conductive layer 166 and connection layer 242. On the upper surface of connection portion 204, conductive layer 166 obtained by processing the same conductive film as pixel electrode 191 is exposed. Thereby, connection portion 204 and FPC 172a can be electrically connected via connection layer 242.

[0257] Various optical components can be placed on the outside of the substrate 152. Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. In addition, an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and an impact-absorbing layer may be placed on the outside of the substrate 152.

[0258] Substrates 151 and 152 can be made of glass, quartz, ceramic, sapphire, resin, or the like.

[0259] Various types of curing adhesives can be used as the adhesive layer, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0260] As the connecting layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), etc., can be used.

[0261] The light-emitting device 190 can be a top-emission type, a bottom-emission type, a dual-emission type, etc. In one aspect of the present invention, a top-emission type is preferred, but other configurations can also be applied by orienting the light-emitting surface of the light-emitting device 190 and the light-incoming surface of the light-receiving device 110 in the same direction.

[0262] The light-emitting device 190 has at least a light-emitting layer 193. The light-emitting device 190 may further have layers other than the light-emitting layer 193, such as a material with high hole injection properties, a material with high hole transport properties, a hole blocking material, a material with high electron transport properties, a material with high electron injection properties, or a bipolar material (a material with high electron transport and hole transport properties). For example, the common layer 112 preferably has one or both of a hole injection layer and a hole transport layer. For example, the common layer 114 preferably has one or both of an electron transport layer and an electron injection layer.

[0263] The common layer 112, the light-emitting layer 193, and the common layer 114 may use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the common layer 112, the light-emitting layer 193, and the common layer 114 can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0264] The light-emitting layer 193 may have an inorganic compound such as quantum dots as a light-emitting material.

[0265] The photoelectric conversion layer 113 of the light-receiving device 110 includes a semiconductor. This semiconductor can be an inorganic semiconductor such as silicon, or an organic semiconductor containing an organic compound. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor in the photoelectric conversion layer 113. Using an organic semiconductor is preferable because it allows the light-emitting layer 193 of the light-emitting device 190 and the photoelectric conversion layer 113 of the light-receiving device 110 to be formed using the same method (e.g., vacuum deposition), thus enabling the use of common manufacturing equipment.

[0266] The n-type semiconductor material of the photoelectric conversion layer 113 is fullerene (for example, C 60 , C 70Examples of electron-accepting organic semiconductor materials include those mentioned above or their derivatives. In addition, examples of electron-donating organic semiconductor materials for the p-type semiconductor material of the photoelectric conversion layer 113 include copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), and zinc phthalocyanine (ZnPc).

[0267] For example, the photoelectric conversion layer 113 can be formed by co-depositing an n-type semiconductor and a p-type semiconductor.

[0268] Materials that can be used for conductive layers such as the gate, source, and drain of transistors, as well as various wirings and electrodes that constitute display devices, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys mainly composed of these metals. Films containing these materials can be used in single-layer or multilayer structures.

[0269] Furthermore, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene can be used as the light-transmitting conductive material. Alternatively, metallic materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, as well as alloy materials containing such metallic materials, can be used. Alternatively, nitrides of such metallic materials (e.g., titanium nitride) may be used. When using metallic materials, alloy materials (or their nitrides), it is preferable to make them thin enough to be light-transmitting. In addition, a laminated film of the above materials can be used as a conductive layer. For example, using a laminated film of a silver-magnesium alloy and indium tin oxide is preferable because it can enhance conductivity. These can also be used for conductive layers of various wirings and electrodes that constitute a display device, and for conductive layers of display elements (conductive layers that function as pixel electrodes or common electrodes).

[0270] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, and aluminum oxide.

[0271] The display device of this embodiment has a light-receiving device and a light-emitting device in the display unit, and the display unit has both the function of displaying an image and the function of detecting light. This makes it possible to miniaturize and lighten the electronic device compared to cases where a sensor is provided outside the display unit or outside the display device. Furthermore, by combining it with a sensor provided outside the display unit or outside the display device, it is possible to realize a more multi-functional electronic device.

[0272] The light-receiving device can have at least one layer other than the photoelectric conversion layer that is common to the light-emitting device (EL element). Furthermore, the light-receiving device may have all layers other than the photoelectric conversion layer that are common to the light-emitting device (EL element). For example, by simply adding a step of depositing a photoelectric conversion layer to the manufacturing process of the light-emitting device, the light-emitting device and the light-receiving device can be formed on the same substrate. In addition, the pixel electrodes and common electrodes of the light-receiving device and the light-emitting device can be formed using the same material and the same process. Moreover, by manufacturing the circuits electrically connected to the light-receiving device and the circuits electrically connected to the light-emitting device using the same material and the same process, the manufacturing process of the display device can be simplified. In this way, a highly convenient display device with a built-in light-receiving device can be manufactured without complex processes.

[0273] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0274] (Embodiment 4) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied.

[0275] The electronic device 6500 shown in Figure 36A is a portable information terminal that can be used as a smartphone.

[0276] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0277] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0278] Figure 36B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0279] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0280] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0281] Furthermore, a portion of the display panel 6511 is folded back in the area outside the display unit 6502. The FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to terminals provided on the printed circuit board 6517.

[0282] A display device according to one embodiment of the present invention can be applied to the display panel 6511. By using a narrow-bezel display device according to one embodiment of the present invention, a small and lightweight electronic device can be realized.

[0283] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0284] (Embodiment 5) This embodiment describes an electronic device equipped with a display device according to one aspect of the present invention.

[0285] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Furthermore, it is possible to create an electronic device that achieves both high resolution and a large screen.

[0286] The display unit of an electronic device according to one aspect of the present invention can display video having a resolution of, for example, Full HD, 4K2K, 8K4K, 16K8K, or higher.

[0287] Examples of electronic devices include those with relatively large screens, such as television sets, notebook computers, monitors, digital signage, pachinko machines, and game consoles, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0288] An electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of the interior or exterior walls of a house or building, or the interior or exterior of an automobile, etc.

[0289] The electronic equipment shown in Figures 37A to 37G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0290] The electronic devices shown in Figures 37A to 37G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0291] Details of the electronic equipment shown in Figures 37A to 37G will be explained below.

[0292] Figure 37A is a perspective view showing the television system 9100. The television system 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0293] Figure 37B is a perspective view showing a personal digital assistant (PDA) 9101. The PDA 9101 can be used, for example, as a smartphone. The PDA 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDA 9101 can also display text and image information on multiple surfaces. Figure 37B shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the subject of an email or SNS message, the sender's name, date and time, time, battery level, and antenna signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0294] Figure 37C is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0295] Figure 37D is a perspective view showing a wristwatch-type personal information terminal 9200. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0296] Figures 37E, 37F, and 37G are perspective views showing a foldable personal information terminal 9201. Figure 37E shows the personal information terminal 9201 in an unfolded state, Figure 37G shows it in a folded state, and Figure 37F shows a state in between the transition from Figure 37E to Figure 37G. The personal information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the personal information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm to 150 mm.

[0297] Figure 38A shows an example of a television system. The television system 7100 has a display unit 7500 incorporated into a housing 7101. Here, the housing 7101 is shown supported by a stand 7103.

[0298] The television device 7100 shown in Figure 38A can be operated using the operation switches on the housing 7101 or a separate remote control unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television device 7100 may be operated by touching it. The remote control unit 7111 may have a display unit in addition to operation buttons.

[0299] The television equipment 7100 may also include a television broadcast receiver or a communication device for network connection.

[0300] Figure 38B shows the notebook personal computer 7200. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated into the casing 7211.

[0301] Figures 38C and 38D show examples of digital signage.

[0302] The digital signage 7300 shown in Figure 38C comprises a housing 7301, a display unit 7500, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switches), connection terminals, various sensors, a microphone, etc.

[0303] Figure 38D also shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is provided along the curved surface of the column 7401.

[0304] The larger the display area 7500, the more information can be provided at once, and because it is more eye-catching, it can have the effect of enhancing the promotional effect of advertisements, for example.

[0305] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows it to be used not only for advertising purposes but also for providing information that the user needs, such as route information, traffic information, and information on commercial facilities.

[0306] Furthermore, as shown in Figures 38C and 38D, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 such as a smartphone owned by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0307] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the information terminal 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0308] A display device according to one embodiment of the present invention can be applied to the display unit 7500 in Figures 38A to 38D.

[0309] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Explanation of Symbols]

[0310] C1: Capacitor, C2: Capacitor, C3: Capacitor, C4: Capacitor, EL: Light-emitting device, G1: Wiring, G2: Wiring, G4: Wiring, G5: Wiring, G6: Wiring, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M5: Transistor, M6: Transistor, M7: Transistor, M9: Transistor, M10: Transistor, M11: Transistor, M12: Transistor, PD: Light-receiving device, PIX1: Pixel circuit, PIX2: Pixel circuit, PIX3: Pixel circuit, S1: Wiring, V0: Wiring, V1: Wiring, V2 :Wiring, V3:Wiring, V4:Wiring, VRW:Wiring, 10:Flip-flop circuit, 11:Output circuit, 12:Switch circuit, 13:Circuit, 14:Circuit, 15:Switch circuit, 16:Switch circuit, 17:Switch circuit, 18:Switch circuit, 19:Switch circuit, 20:Semiconductor device, 20a:Semiconductor device, 20b:Semiconductor device, 20c:Semiconductor device, 20d:Semiconductor device, 21:Low driver, 22:Low driver, 23:Pixel array, 24:Pixel, 25:Circuit, 26:Circuit, 31:Block, 32:Block, 33:Block, 40:Circuit, 41:Circuit, 42: Circuit, 50: Selection circuit, 110: Light-receiving device, 111: Pixel electrode, 112: Common layer, 113: Photoelectric conversion layer, 114: Common layer, 115: Common electrode, 142: Adhesive layer, 143: Space, 148: Light-shielding layer, 149: Optical filter, 151: Substrate, 152: Substrate, 165: Wiring, 166: Conductive layer, 172a: FPC, 190: Light-emitting device, 191: Pixel electrode, 193: Light-emitting layer, 201: Transistor, 204: Connection part, 205: Transistor, 206: Transistor, 211: Insulating layer, 213: Insulating layer, 214: Insulating layer, 215: Insulating layer, 216: Partition wall, 221: conductive layer, 222a: conductive layer, 222b: conductive layer, 223: conductive layer, 228: region, 231: semiconductor layer, 242: connection layer, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7100: television equipment, 7101: housing,7103: Stand, 7111: Remote control unit, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7500: Display unit, 9000: Enclosure ,9001:Display unit, 9003:Speaker, 9005:Operation keys, 9006:Connection terminal, 9007:Sensor, 9008:Microphone, 9050:Icon, 9051:Information, 9052:Information, 9053:Information, 9054:Information, 9055:Hinge, 9100:Television device, 9101:Personal information terminal, 9102:Personal information terminal, 9200:Personal information terminal, 9201:Personal information terminal,

Claims

1. It has a first block, a second block, and a third block, Each of the first to third blocks has the same number of flip-flop circuits and the same number of output circuits. Each of the aforementioned flip-flop circuits is electrically connected to a pair of the aforementioned output circuits. In each of the first to third blocks, the multiple flip-flop circuits are connected in cascading order. The final stage flip-flop circuit of the first block is electrically connected to the first stage flip-flop circuit of the second block via a first switch. The final stage flip-flop circuit of the first block is electrically connected to the first stage flip-flop circuit of the third block via a second switch. A semiconductor device in which the final stage flip-flop circuit of the second block is electrically connected to the first stage flip-flop circuit of the third block via a third switch.

2. A semiconductor device according to claim 1, and a pixel, The pixel has a first circuit having a display element, The output circuit is a display device electrically connected to the first circuit.

Images