Real-time clock module

Abstract

To provide a real-time clock module capable of enhancing the extensibility of an alarm function without greatly increasing a circuit scale.SOLUTION: A real-time clock module includes: an oscillation circuit that generates a first clock signal by oscillating a resonator; an interface circuit to which alarm setting data is input; a memory in which the alarm setting data and a program are stored; and a processor that executes the program to perform comparison processing of comparing clocking data generated on the basis of the first clock signal with the alarm setting data and output an alarm signal according to a result of the comparison processing.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a real-time clock module.

Background Art

[0002] Patent Document 1 discloses a real-time clock device including a carry control unit that generates a carry signal based on a reference clock signal and an external access signal, a timing unit that performs timing processing based on the carry signal to generate timing information, and an interrupt output control unit that generates and outputs an interrupt signal that is not affected by the state of the external access signal based on the reference clock signal, thereby enabling accurate generation of an interrupt signal at a specific time.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the real-time clock device described in Patent Document 1, the alarm unit included in the interrupt output control unit generates an interrupt signal by performing a downcount from an alarm calculation value obtained by calculating the difference between a preset alarm time and the timing information acquired from the timing unit. Since it is generally composed of a hardware logic circuit, the number of alarm channels, the setting of time digits, etc. are fixed, and there is no extensibility of the alarm function. Also, if a logic circuit capable of supporting various alarm functions is provided to enhance the extensibility of the alarm function, the circuit scale of the real-time clock device will increase significantly.

Means for Solving the Problems

[0005] One aspect of the real-time clock module according to the present invention is An oscillator circuit that generates a first clock signal by causing an oscillator to oscillate, An interface circuit into which alarm setting data is input, The memory in which the alarm setting data and program are stored, The system includes a processor that, by executing the program, performs a comparison process to compare timing data generated based on the first clock signal with the alarm setting data, and outputs an alarm signal according to the result of the comparison process. [Brief explanation of the drawing]

[0006] [Figure 1] Functional block diagram of the real-time clock module of this embodiment. [Figure 2] A diagram showing an example of a program, various data, and various registers. [Figure 3] A diagram showing an example of bit allocation for various types of data stored in RAM. [Figure 4] A diagram showing an example of bit allocation for various types of data stored in RAM. [Figure 5] A diagram showing an example of bit allocation for data held in various registers. [Figure 6] A flowchart illustrating an example of the processing procedure using a real-time clock module. [Figure 7] A flowchart illustrating an example of the time setting process in step S2 of Figure 6. [Figure 8] A flowchart illustrating an example of the procedure for the BCD time setting process in step S23 of Figure 7. [Figure 9] A flowchart illustrating an example of the binary time setting process in step S25 of Figure 7. [Figure 10] A flowchart illustrating an example of the time reading process in step S4 of Figure 6. [Figure 11] A flowchart illustrating an example of the procedure for the alarm setting process in step S6 of Figure 6. [Figure 12]A flowchart showing an example of the procedure of the BCD alarm setting process in step S63 of FIG. 11. [Figure 13] A flowchart showing an example of the procedure of the binary alarm setting process in step S65 of FIG. 11. [Figure 14] A flowchart showing an example of the procedure of the time update process in step S8 of FIG. 6. [Figure 15] A flowchart showing an example of the procedure of the BCD time update process in step S82 of FIG. 14. [Figure 16] A flowchart showing an example of the procedure of the binary time update process in step S84 of FIG. 14. [Figure 17] A diagram showing an example of the sequence of the timing process by the processor. [Figure 18] A diagram showing an example of the sequence of the alarm process by the processor.

Mode for Carrying Out the Invention

[0007] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0008] 1. Real-Time Clock Module 1-1. Configuration of the Real-Time Clock Module FIG. 1 is a functional block diagram of the real-time clock module 1 of the present embodiment. As shown in FIG. 1, the real-time clock module 1 includes an oscillator 2 and a real-time clock circuit 3.

[0009] The real-time clock module 1 is supplied with a power supply voltage VDD from the main power supply 4 via the terminal P1 of the real-time clock circuit 3, and a power supply voltage VBAT from the backup power supply 5 via the terminal P2 of the real-time clock circuit 3.

[0010] The oscillator 2 may be a tuning fork type crystal oscillator, an AT cut crystal oscillator, an SC cut crystal oscillator, etc., or may be a piezoelectric oscillator other than a SAW resonator or a crystal oscillator. SAW is an abbreviation for Surface Acoustic Wave. Also, the oscillator 2 may be a MEMS oscillator made of a silicon semiconductor. MEMS is an abbreviation for Micro Electro Mechanical Systems. The oscillator 2 may be excited by the piezoelectric effect or driven by the Coulomb force.

[0011] The real-time clock circuit 3 includes an oscillation circuit 10, a frequency division circuit 20, a first counter 30, a second counter 40, a third counter 50, a processor 60, a write buffer 70, a read buffer 80, an interface circuit 90, a memory 100, a register group 110, an interrupt generation circuit 120, a power supply voltage selection circuit 130, a power supply voltage determination circuit 140, and a regulator 150. However, the real-time clock circuit 3 may have a configuration in which some of these elements are omitted or modified, or other elements are added. In the present embodiment, the real-time clock circuit 3 is a one-chip integrated circuit, but may be composed of a multi-chip integrated circuit or at least a part thereof may be composed of discrete components.

[0012] The power supply voltage determination circuit 140 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is equal to or higher than a predetermined voltage value VT, and outputs a determination signal VDET. In the present embodiment, when the power supply voltage determination circuit 140 determines that the power supply voltage VDD is equal to or higher than the voltage value VT, it outputs a high-level determination signal VDET, and when it determines that the power supply voltage VDD is less than the voltage value VT, it outputs a low-level determination signal VDET.

[0013] The power supply voltage selection circuit 130 selects either the power supply voltage VDD or the power supply voltage VBAT based on the determination signal VDET and outputs it as the power supply voltage VOUT. Specifically, the power supply voltage selection circuit 130 selects the power supply voltage VDD when the determination signal VDET is at a high level, that is, when the power supply voltage determination circuit 140 determines that the power supply voltage VDD is greater than or equal to the voltage value VT. The power supply voltage selection circuit 130 also selects the power supply voltage VBAT when the determination signal VDET is at a low level, that is, when the power supply voltage determination circuit 140 determines that the power supply voltage VDD is less than the voltage value VT.

[0014] Therefore, when the power supply voltage VDD is supplied from the main power supply 4 to the real-time clock module 1, the power supply voltage VOUT is the power supply voltage VDD and is a predetermined voltage value greater than or equal to VT. When the supply of power supply voltage VDD from the main power supply 4 to the real-time clock module 1 is cut off, the power supply voltage VOUT immediately switches to the power supply voltage VBAT and becomes a predetermined voltage value less than or equal to VT. As a result, the real-time clock module 1 can continue its timing operation even when the supply of power supply voltage VDD from the main power supply 4 is cut off. In contrast, the host device 6 that controls the operation of the real-time clock module 1 operates when power supply voltage VDD is supplied from the main power supply 4, and stops operating when the supply of power supply voltage VDD from the main power supply 4 is cut off.

[0015] The regulator 150 generates stabilized power supply voltages VOSC and VLOGIC, which have constant voltage values, based on the power supply voltage VOUT.

[0016] The power supply voltage VOSC is supplied to the oscillator circuit 10. The power supply voltage VLOGIC is supplied to the frequency divider circuit 20, the first counter 30, the second counter 40, the third counter 50, the processor 60, the write buffer 70, the read buffer 80, the interface circuit 90, the memory 100, the register group 110, and the interrupt generation circuit 120.

[0017] The oscillation circuit 10 generates a first clock signal CK1 by causing the resonator 2 to oscillate. Specifically, the oscillation circuit 10 is electrically connected to both ends of the resonator 2 via terminals P3 and P4 of the real-time clock circuit 3, and outputs the first clock signal CK1 by amplifying the output signal of the resonator 2 and feeding it back. In this embodiment, the frequency of the first clock signal CK1 is 32.768 kHz. However, the frequency of the first clock signal CK1 is not particularly limited. In order to ensure that the first clock signal CK1 has an accurate frequency, it is preferable that the oscillation circuit 10 is an oscillation circuit equipped with a temperature compensation function and a frequency control function.

[0018] The frequency divider circuit 20 divides the first clock signal CK1 to generate a second clock signal CK2 having a desired frequency. In this embodiment, the division ratio of the frequency divider circuit 20 is 32, and the frequency of the second clock signal CK2 is 1.024 kHz. However, the division ratio of the frequency divider circuit 20 and the frequency of the second clock signal CK2 are not particularly limited.

[0019] The first counter 30 counts the number of pulses of the second clock signal CK2 based on the first clock signal CK1, and outputs a third clock signal CK3 based on the counted value. Specifically, the first counter 30 divides the second clock signal CK2 by 1024 to generate a 1Hz third clock signal CK3, and performs counting operations in synchronization with the second clock signal CK2. The first counter 30 is a 10-bit binary counter and sequentially generates binary count values ​​representing decimal numbers from 0 to 1023. When the count value of the first counter 30 becomes equal to the value representing decimal number 1023, it resets the count value to 0 in synchronization with the next pulse of the second clock signal CK2. The count value generated by the first counter 30 is used as timing data SUBSEC, which represents time in units of 1 / 1024 seconds.

[0020] The second counter 40 is a seconds counter that generates time data representing time in seconds by performing counting operations in synchronization with the third clock signal CK3. The second counter 40 is a 7-bit sexagesimal BCD counter that sequentially generates BCD count values ​​representing decimal numbers from 0 to 59 in synchronization with the pulses of the third clock signal CK3. BCD stands for Binary Coded Decimal. When the count value of the second counter 40 becomes equal to the value representing decimal number 59, it resets the count value to 0 in synchronization with the next pulse of the third clock signal CK3. The count value generated by the second counter 40 is used as timing data SEC_BCD, which represents time in seconds.

[0021] The third counter 50 is a seconds counter that generates a count value representing time in seconds by performing counting operations in synchronization with the third clock signal CK3. The third counter 50 is an 8-bit binary counter that sequentially generates binary count values ​​representing decimal numbers from 0 to 255 in synchronization with the pulses of the third clock signal CK3. When the count value of the third counter 50 becomes equal to the value representing decimal number 255, it resets the count value to 0 in synchronization with the next pulse of the third clock signal CK3. The count value generated by the third counter 50 is used as timing data SEC_BIN, which represents time in seconds.

[0022] Memory 100 is a circuit that stores programs and various data. In this embodiment, memory 100 includes RAM 101 and non-volatile memory 102. The register group 110 includes various registers. RAM stands for Random Access Memory. Figure 2 shows an example of programs and various data stored in memory 100 and various registers included in the register group 110.

[0023] As shown in Figure 2, RAM 101 stores timing data 200 and alarm setting data 210. The timing data 200 is at least one of BCD timing data T_BCD, which is timing data in BCD format, and binary timing data T_BIN, which is timing data in binary format. The alarm setting data 210 is at least one of BCD alarm setting data 211, which is setting data in BCD format, and binary alarm setting data 212, which is setting data in binary format. The BCD alarm setting data 211 includes multiple setting data corresponding to multiple times. Specifically, the BCD alarm setting data 211 includes two setting data: BCD alarm first setting data A1_BCD and BCD alarm second setting data A2_BCD, which correspond to two times. Similarly, the binary alarm setting data 212 includes multiple setting data corresponding to multiple times. Specifically, the binary alarm setting data 212 includes two setting data: binary alarm first setting data A1_BIN and binary alarm second setting data A2_BIN, which correspond to two different time periods.

[0024] The BCD timing data T_BCD, the BCD alarm first setting data A1_BCD, and the BCD alarm second setting data A2_BCD are each composed of second data representing 0-59, minute data representing 0-59, hour data representing 0-23, day data representing 1-31, day of the week data representing 1-7, month data representing 1-12, and year data representing 0-9999, respectively. The binary timing data T_BIN, the binary alarm first setting data A1_BIN, and the binary alarm second setting data A2_BIN are each composed of second data.

[0025] Figures 3 and 4 show examples of bit allocation for various data stored in RAM 101. In the examples in Figures 3 and 4, one address is allocated to 16-bit data.

[0026] As shown in Figure 3, the BCD timing data T_BCD is stored in memory area A of RAM101, which has a size of 4 words. In the first word of 16-bit data stored in memory area A, bits 15-7 are unused, bits 6-4 correspond to the tens digit of the seconds data, and bits 3-0 correspond to the units digit of the seconds data. In the second word of 16-bit data stored in memory area A, bits 15-13 are unused, bits 12 and 11 correspond to the tens digit of the hour data, bits 10-7 correspond to the units digit of the hour data, bits 6-4 correspond to the tens digit of the minute data, and bits 3-0 correspond to the units digit of the minute data. The third word of 16-bit data stored in memory area A has bits 15 and 14 unused, bits 13-11 correspond to the day of the week data, bit 10 corresponds to the tens digit of the month data, bits 9-6 correspond to the units digit of the month data, bits 5 and 4 correspond to the tens digit of the day data, and bits 3-0 correspond to the units digit of the day data. The fourth word of 16-bit data stored in memory area A has bits 15-12 corresponding to the thousands digit of the year data, bits 11-8 correspond to the hundreds digit of the year data, bits 7-4 correspond to the tens digit of the year data, and bits 3-0 correspond to the units digit of the year data.

[0027] The BCD timing data T_BCD is also stored in memory area B of RAM101, which is 4 words in size. The bit allocation of the BCD timing data T_BCD stored in memory area B is the same as the bit allocation of the BCD timing data T_BCD stored in memory area A, so its explanation is omitted. As described later, there is always a difference of 1 second between the BCD timing data T_BCD stored in memory area A and the BCD timing data T_BCD stored in memory area B. Specifically, if the BCD timing data T_BCD stored in memory area A represents the current time, the BCD timing data T_BCD stored in memory area B represents the time 1 second later. Also, if the BCD timing data T_BCD stored in memory area B represents the current time, the BCD timing data T_BCD stored in memory area A represents the time 1 second later.

[0028] As shown in Figure 3, the binary timing data T_BIN is stored in memory area C of RAM101, which is the size of three words. In the first word of 16-bit data stored in memory area C, bits 15-8 are unused, and bits 7-0 correspond to bits 7-0 of the seconds data. In the second word of 16-bit data stored in memory area C, bits 15-0 correspond to bits 23-8 of the seconds data. In the third word of 16-bit data stored in memory area C, bits 15-9 are unused, and bits 8-0 correspond to bits 32-24 of the seconds data.

[0029] The binary timing data T_BIN is also stored in memory area D of RAM101, which is 3 words in size. The bit allocation of the binary timing data T_BIN stored in memory area D is the same as the bit allocation of the binary timing data T_BIN stored in memory area C, so its explanation is omitted. As will be described later, there is always a difference of 1 second between the binary timing data T_BIN stored in memory area C and the binary timing data T_BIN stored in memory area D. Specifically, if the binary timing data T_BIN stored in memory area C represents the current time, the binary timing data T_BIN stored in memory area D represents the time 1 second later. Also, if the binary timing data T_BIN stored in memory area D represents the current time, the binary timing data T_BIN stored in memory area C represents the time 1 second later.

[0030] As shown in Figure 3, the BCD timing data T_BCD is stored in a 4-word memory area A or B, with 7 bits of second data in the first 16-bit data, 6 bits of hour data and 7 bits of minute data in the second 16-bit data, 3 bits of day of the week data, 5 bits of month data and 6 bits of day data in the third 16-bit data, and 16 bits of year data in the fourth 16-bit data. In other words, the BCD timing data T_BCD is not stored by dividing the second data, minute data, hour data, day data, day of the week data, month data, and year data into 7 separate 16-bit data, but rather by compressing them into 4 16-bit data and storing them in the RAM 101 of memory 100. Therefore, the size of memory areas A and B where the BCD timing data T_BCD is stored is reduced, and the area of ​​RAM 101 can be reduced.

[0031] As shown in Figure 4, the first BCD alarm setting data A1_BCD is stored in a 4-word memory area E of RAM 101. The second BCD alarm setting data A2_BCD is stored in a 4-word memory area F of RAM 101. The bit assignments for the first BCD alarm setting data A1_BCD and the second BCD alarm setting data A2_BCD are the same as the bit assignments for the BCD timing data T_BCD, so their explanation is omitted.

[0032] As shown in Figures 3 and 4, the BCD alarm first setting data A1_BCD, the BCD alarm second setting data A2_BCD, and the BCD timing data T_BCD have the same bit allocation and are compressed in the same format and stored in the RAM 101 of memory 100. Therefore, the size of the storage area E where the BCD alarm first setting data A1_BCD is stored and the storage area F where the BCD alarm second setting data A2_BCD is stored are reduced, and the area of ​​RAM 101 can be reduced.

[0033] As shown in Figure 4, the first binary alarm setting data A1_BIN is stored in a 3-word memory area G of RAM 101. The second binary alarm setting data A2_BIN is stored in a 3-word memory area H of RAM 101. The bit assignments for the first binary alarm setting data A1_BIN and the second binary alarm setting data A2_BIN are the same as the bit assignments for the binary timing data T_BIN, so their explanation is omitted.

[0034] Returning to Figure 2, the register group 110 includes an internal flag register 111, an external flag register 112, a first alarm selection register 113, a second alarm selection register 114, and a control register 115. The internal flag register 111 holds the values ​​of various flags that are not accessible from the host device 6. The external flag register 112 holds the values ​​of various flags that are accessible from the host device 6. The first alarm selection register 113 holds data for selecting the content of alarm processing based on the first BCD alarm setting data A1_BCD. The second alarm selection register 114 holds data for selecting the content of alarm processing based on the second BCD alarm setting data A2_BCD. The control register 115 stores data for controlling the enable / disable of various timing and alarm processing.

[0035] Figure 5 shows an example of bit allocation for data held in various registers included in the register group 110. When the power supply voltage VLOGIC rises from 0V to a predetermined voltage value, each bit in the various registers is initialized to 0.

[0036] As shown in Figure 5, the internal flag register 111 is a 6-bit register, with bit 0 holding the first pre-alarm flag FAlm1, bit 1 holding the second pre-alarm flag FAlm2, bit 2 holding the third pre-alarm flag FAlm3, bit 3 holding the fourth pre-alarm flag FAlm4, bit 4 holding the first current time selection flag FBUF1, and bit 5 holding the second current time selection flag FBUF2.

[0037] If the data selected from the BCD timing data T_BCD, which represents the time one second later, matches the data selected from the BCD alarm first setting data A1_BCD, the first pre-alarm flag FAlm1 is set to 1. If they do not match, the first pre-alarm flag FAlm1 is reset to 0. The data to be compared is selected by the first alarm selection register 113.

[0038] If the data selected from the BCD timing data T_BCD, which represents the time one second later, matches the data selected from the BCD alarm second setting data A2_BCD, the second pre-alarm flag FAlm2 is set to 1. If they do not match, the second pre-alarm flag FAlm2 is reset to 0. The data to be compared is selected by the second alarm selection register 114.

[0039] If the binary timing data T_BIN, which represents the time one second later, matches the binary alarm first setting data A1_BIN, the third pre-alarm flag FAlm3 is set to 1. If they do not match, the third pre-alarm flag FAlm3 is reset to 0.

[0040] If the binary timing data T_BIN, which represents the time one second later, matches the binary alarm second setting data A2_BIN, the fourth pre-alarm flag FAlm4 is set to 1. If they do not match, the fourth pre-alarm flag FAlm4 is reset to 0.

[0041] When the first current time selection flag FBUF1 is 0, it indicates that the BCD timing data T_BCD stored in memory area A of RAM101 represents the current time. When the first current time selection flag FBUF1 is 1, it indicates that the BCD timing data T_BCD stored in memory area B of RAM101 represents the current time.

[0042] When the second current time selection flag FBUF2 is 0, it indicates that the binary timing data T_BIN stored in memory area C of RAM101 represents the current time. When the second current time selection flag FBUF2 is 1, it indicates that the binary timing data T_BIN stored in memory area D of RAM101 represents the current time.

[0043] As shown in Figure 5, the external flag register 112 is a 6-bit register, with bit 0 holding the first alarm flag FA1, bit 1 holding the second alarm flag FA2, bit 2 holding the third alarm flag FA3, bit 3 holding the fourth alarm flag FA4, bit 4 holding the first error flag FE1, and bit 5 holding the second error flag FE2.

[0044] If the first pre-alarm flag FAlm1 is 1 at the time update timing every second, the first alarm flag FA1 is set to 1.

[0045] If the second pre-alarm flag FAlm2 is 1 at the time update timing every second, the second alarm flag FA2 is set to 1.

[0046] If the third pre-alarm flag FAlm3 is 1 at the time update timing every second, the third alarm flag FA3 is set to 1.

[0047] If the fourth pre-alarm flag FAlm4 is 1 at the time update timing every second, the fourth alarm flag FA4 is set to 1.

[0048] If the value of the BCD timing data T_BCD does not fall within a predetermined range corresponding to the range of possible times, the first error flag FE1 is set to 1.

[0049] If the value of the binary timing data T_BIN does not fall within a predetermined range corresponding to the range of possible times, the second error flag FE2 is set to 1.

[0050] The host device 6 has access to the external flag register 112, and each flag set to 1 is automatically reset to 0 when read by the host device 6, or reset to 0 when written by the host device 6.

[0051] As shown in Figure 5, the first alarm selection register 113 is a 7-bit register, with bit 0 holding the second data selection bit XSAE, bit 1 holding the minute data selection bit XMIAE, bit 2 holding the hour data selection bit XHAE, bit 3 holding the day data selection bit XDAE, bit 4 holding the day of the week data selection bit XWAE, bit 5 holding the month data selection bit XMOAE, and bit 6 holding the year data selection bit XYAE.

[0052] When the second data selection bit XSAE is 0, it indicates that the second data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as the comparison target in the comparison process. When the second data selection bit XSAE is 1, it indicates that the second data of both will not be selected as the comparison target in the said comparison process.

[0053] When the minute data selection bit XMIAE is 0, it indicates that the minute data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as the comparison target in the comparison process. When the minute data selection bit XMIAE is 1, it indicates that the minute data of both will not be selected as the comparison target in the said comparison process.

[0054] When the time data selection bit XHAE is 0, it indicates that the time data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as comparison targets in the comparison process. When the time data selection bit XHAE is 1, it indicates that the time data of both will not be selected as comparison targets in the said comparison process.

[0055] When the daily data selection bit XDAE is 0, it indicates that the daily data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as the comparison target in the comparison process. When the daily data selection bit XDAE is 1, it indicates that the daily data of both will not be selected as the comparison target in the said comparison process.

[0056] When the day of the week data selection bit XWAE is 0, it indicates that the day of the week data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as comparison targets in the comparison process. When the day of the week data selection bit XWAE is 1, it indicates that the day of the week data of both will not be selected as comparison targets in the said comparison process.

[0057] When the monthly data selection bit XMOAE is 0, it indicates that the monthly data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as the comparison target in the comparison process. When the monthly data selection bit XMOAE is 1, it indicates that the monthly data of both will not be selected as the comparison target in the said comparison process.

[0058] When the year data selection bit XYAE is 0, it indicates that the year data of both the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD will be selected as the comparison target in the comparison process. When the year data selection bit XYAE is 1, it indicates that the year data of both will not be selected as the comparison target in the said comparison process.

[0059] The host device 6 has access to the first alarm selection register 113 and can read from and write to each bit.

[0060] As shown in Figure 5, the second alarm selection register 114 is a 7-bit register, with bit 0 holding the second data selection bit XSAE, bit 1 holding the minute data selection bit XMIAE, bit 2 holding the hour data selection bit XHAE, bit 3 holding the day data selection bit XDAE, bit 4 holding the day of the week data selection bit XWAE, bit 5 holding the month data selection bit XMOAE, and bit 6 holding the year data selection bit XYAE.

[0061] When the second data selection bit XSAE is 0, it indicates that the second data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as the comparison target in the comparison process. When the second data selection bit XSAE is 1, it indicates that the second data of both will not be selected as the comparison target in the said comparison process.

[0062] When the minute data selection bit XMIAE is 0, it indicates that the minute data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as the comparison target in the comparison process. When the minute data selection bit XMIAE is 1, it indicates that the minute data of both will not be selected as the comparison target in the said comparison process.

[0063] When the time data selection bit XHAE is 0, it indicates that the time data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as comparison targets in the comparison process. When the time data selection bit XHAE is 1, it indicates that the time data of both will not be selected as comparison targets in the said comparison process.

[0064] When the daily data selection bit XDAE is 0, it indicates that the daily data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as the comparison target in the comparison process. When the daily data selection bit XDAE is 1, it indicates that the daily data of both will not be selected as the comparison target in the said comparison process.

[0065] When the day of the week data selection bit XWAE is 0, it indicates that the day of the week data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as comparison targets in the comparison process. When the day of the week data selection bit XWAE is 1, it indicates that the day of the week data of both will not be selected as comparison targets in the said comparison process.

[0066] When the monthly data selection bit XMOAE is 0, it indicates that the monthly data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as the comparison target in the comparison process. When the monthly data selection bit XMOAE is 1, it indicates that the monthly data of both will not be selected as the comparison target in the said comparison process.

[0067] When the year data selection bit XYAE is 0, it indicates that the year data of both the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD will be selected as the comparison target in the comparison process. When the year data selection bit XYAE is 1, it indicates that the year data of both will not be selected as the comparison target in the said comparison process.

[0068] The host device 6 has access to the second alarm selection register 114 and can read from and write to each bit.

[0069] As shown in Figure 5, the control register 115 is a 6-bit register, with bit 0 holding the BCD timing enable bit BCDCE, bit 1 holding the binary timing enable bit BINCE, bit 3 holding the first alarm enable bit AE1, bit 4 holding the second alarm enable bit AE2, bit 5 holding the third alarm enable bit AE3, and bit 6 holding the fourth alarm enable bit AE4.

[0070] When the BCD timing valid bit BCDCE is 0, it indicates that the BCD timing mode, which measures BCD time, is disabled. When the BCD timing valid bit BCDCE is 1, it indicates that the BCD timing mode is enabled.

[0071] When the binary timing valid bit BINCE is 0, it indicates that the binary timing mode, which measures binary time, is disabled. When the binary timing valid bit BINCE is 1, it indicates that the binary timing mode is enabled.

[0072] When the first alarm enable bit AE1 is 0, it indicates that the first alarm mode, which performs alarm processing based on the BCD alarm first setting data A1_BCD, is disabled. When the first alarm enable bit AE1 is 1, it indicates that the first alarm mode is enabled.

[0073] When the second alarm enable bit AE2 is 0, it indicates that the second alarm mode, which performs alarm processing based on the BCD alarm second setting data A2_BCD, is disabled. When the second alarm enable bit AE2 is 1, it indicates that the second alarm mode is enabled.

[0074] When the third alarm enable bit AE3 is 0, it indicates that the third alarm mode, which performs alarm processing based on the binary alarm first setting data A1_BIN, is disabled. When the third alarm enable bit AE3 is 1, it indicates that the third alarm mode is enabled.

[0075] When the fourth alarm enable bit AE4 is 0, it indicates that the fourth alarm mode, which performs alarm processing based on the binary alarm second setting data A2_BIN, is disabled. When the fourth alarm enable bit AE4 is 1, it indicates that the fourth alarm mode is enabled.

[0076] The host device 6 has access to the control register 115 and can read from and write to each bit.

[0077] Returning to Figure 2, the non-volatile memory 102 stores the program PG. When the power supply voltage VLOGIC rises from 0V to a predetermined voltage value, the program PG stored in the non-volatile memory 102 is transferred to the RAM 101 and stored in the RAM 101 as program PGX.

[0078] Returning to Figure 1, in this embodiment, the processor 60 performs timing processing to generate timing data 200 based on the third clock signal CK3 by executing the program PGX stored in RAM 101. Specifically, the processor 60 reads first timing data, which is timing data 200 corresponding to the current time, from RAM 101 based on the third clock signal CK3, and generates second timing data, which is timing data 200 corresponding to the next time, based on the first timing data, and stores it in RAM 101.

[0079] More specifically, when the BCD timing mode is enabled, that is, when the BCD timing enable bit BCDCE in the control register 115 is 1, the processor 60, at the time update timing when the pulse of the third clock signal CK3 occurs, changes the first current time selection flag FBUF1 to 0 if it is 1, reads the BCD timing data T_BCD corresponding to the current time stored in memory area A of RAM 101, and based on the read BCD timing data T_BCD and the timing data SEC_BCD generated by the second counter 40, generates BCD timing data T_BCD corresponding to the time 1 second later and stores it in memory area B of RAM 101. Furthermore, at the time update timing when the pulse of the third clock signal CK3 occurs, if the first current time selection flag FBUF1 is 0, the processor 60 changes the first current time selection flag FBUF1 to 1 and reads the BCD timing data T_BCD corresponding to the current time stored in memory area B of RAM 101. Based on the read BCD timing data T_BCD and the timing data SEC_BCD generated by the second counter 40, it generates BCD timing data T_BCD corresponding to the time 1 second later and stores it in memory area A of RAM 101. In this way, the processor 60 generates the BCD timing data T_BCD using a double buffer method with two memory areas A and B of RAM 101. Note that if the BCD timing mode is disabled, that is, if the BCD timing enable bit BCDCE of the control register 115 is 0, the processor 60 does not perform the process of generating the BCD timing data T_BCD.

[0080] Similarly, when binary timing mode is enabled, that is, when the binary timing enable bit BINCE of the control register 115 is 1, the processor 60, at the time update timing when the pulse of the third clock signal CK3 occurs, changes the second current time selection flag FBUF2 to 0 if it is 1, reads the binary timing data T_BIN corresponding to the current time stored in the memory area C of RAM 101, and based on the read binary timing data T_BIN and the timing data SEC_BIN generated by the third counter 50, generates the binary timing data T_BIN corresponding to the time 1 second later and stores it in the memory area D of RAM 101. Furthermore, at the time update timing when the pulse of the third clock signal CK3 occurs, if the second current time selection flag FBUF2 is 0, the processor 60 changes the second current time selection flag FBUF2 to 1 and reads the binary timing data T_BIN corresponding to the current time stored in the memory area D of RAM 101. Based on the read binary timing data T_BIN and the timing data SEC_BIN generated by the third counter 50, it generates the binary timing data T_BIN corresponding to the time 1 second later and stores it in the memory area C of RAM 101. In this way, the processor 60 generates the binary timing data T_BIN using a double-buffer method with the two memory areas C and D of RAM 101. Note that if the binary timing mode is disabled, that is, if the binary timing valid bit BINCE of the control register 115 is 0, the processor 60 does not perform the process of generating the binary timing data T_BIN.

[0081] Thus, although the timing data 200 is directly generated based on the third clock signal CK3, the third clock signal CK3 is generated based on the first clock signal CK1, so it can be said that the timing data 200 is generated based on the first clock signal CK1.

[0082] In this embodiment, the processor 60 performs a comparison process by executing the program PGX stored in the RAM 101 to compare the timing data 200 with the alarm setting data 210 stored in the RAM 101, and performs an alarm process that outputs an alarm signal SALM according to the result of the comparison process. Specifically, the processor 60 compares the second timing data, which is the timing data 200 corresponding to the next time, with the alarm setting data 210, and if the second timing data and the alarm setting data 210 match, it outputs an alarm signal SALM at the next time update timing.

[0083] More specifically, when the first alarm mode is enabled, that is, when the first alarm enable bit AE1 of the control register 115 is 1, the processor 60 compares the BCD timing data T_BCD corresponding to the time 1 second later with the BCD alarm first setting data A1_BCD at the time update timing when the pulse of the third clock signal CK3 occurs. If the two match, the processor sets the first pre-alarm flag FAlm1 to 1; otherwise, it resets the first pre-alarm flag FAlm1 to 0. The data to be compared between the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD is selected according to the values ​​of each bit in the first alarm selection register 113. Furthermore, if the second alarm mode is enabled, that is, if the second alarm enable bit AE2 of the control register 115 is 1, the processor 60 compares the BCD timing data T_BCD corresponding to the time 1 second later with the BCD alarm second setting data A2_BCD at the time update timing when the pulse of the third clock signal CK3 occurs. If the two match, the processor sets the second pre-alarm flag FAlm2 to 1; otherwise, it resets the second pre-alarm flag FAlm2 to 0. The data to be compared between the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD is selected according to the value of each bit in the second alarm selection register 114. Then, at the next time update timing when the next pulse of the third clock signal CK3 occurs, the processor 60 sets the first alarm flag FA1 to 1 if the first pre-alarm flag FAlm1 is 1, sets the second alarm flag FA2 to 1 if the second pre-alarm flag FAlm2 is 1, and outputs the alarm signal SALM if at least one of the first pre-alarm flag FAlm1 and the second pre-alarm flag FAlm2 is 1.

[0084] Similarly, if the third alarm mode is enabled, that is, if the third alarm enable bit AE3 of the control register 115 is 1, the processor 60 compares the binary timing data T_BIN corresponding to the time 1 second later with the binary alarm first setting data A1_BIN at the time update timing when the pulse of the third clock signal CK3 occurs. If the two match, the processor sets the third pre-alarm flag FAlm3 to 1; otherwise, the processor resets the third pre-alarm flag FAlm3 to 0. Also, if the fourth alarm mode is enabled, that is, if the fourth alarm enable bit AE4 of the control register 115 is 1, the processor 60 compares the binary timing data T_BIN corresponding to the time 1 second later with the binary alarm second setting data A2_BIN at the time update timing when the pulse of the third clock signal CK3 occurs. If the two match, the processor sets the fourth pre-alarm flag FAlm4 to 1; otherwise, the processor resets the fourth pre-alarm flag FAlm4 to 0. Then, at the next time update timing when the next pulse of the third clock signal CK3 occurs, the processor 60 sets the third alarm flag FA3 to 1 if the third pre-alarm flag FAlm3 is 1, sets the fourth alarm flag FA4 to 1 if the fourth pre-alarm flag FAlm4 is 1, and outputs the alarm signal SALM if at least one of the third pre-alarm flag FAlm3 and the fourth pre-alarm flag FAlm4 is 1.

[0085] As shown in Figures 3 and 4, since the BCD alarm first setting data A1_BCD, the BCD alarm second setting data A2_BCD, and the BCD timing data T_BCD have the same bit assignment, the processor 60 can easily perform comparison processing between the BCD timing data T_BCD and the BCD alarm first setting data A1_BCD, and between the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD. Similarly, since the binary alarm first setting data A1_BIN, the binary alarm second setting data A2_BIN, and the binary timing data T_BIN have the same bit assignment, the processor 60 can easily perform comparison processing between the binary timing data T_BIN and the binary alarm first setting data A1_BIN, and between the binary timing data T_BIN and the binary alarm second setting data A2_BIN.

[0086] In this embodiment, if the value of the timing data 200 is not within a predetermined range, the processor 60 performs at least one of the following: outputting an error signal SERR, stopping the update of the timing data 200, and initializing the timing data 200 to a value within the predetermined range. For example, if the value of the BCD timing data T_BCD is not within a predetermined range corresponding to the range of possible times, for example, February 30th, 0:00:00, the processor 60 sets the first error flag FE1 to 1 and outputs an error signal SERR. Also, if the value of the binary timing data T_BIN is not within a predetermined range corresponding to the range of possible times, the processor 60 sets the second error flag FE2 to 1 and outputs an error signal SERR. Furthermore, if the value of the BCD timing data T_BCD is not within a predetermined range, the processor 60 may stop updating the BCD timing data T_BCD, and if the value of the binary timing data T_BIN is not within a predetermined range, the processor 60 may stop updating the binary timing data T_BIN. Furthermore, if the value of the BCD timing data T_BCD is not within a predetermined range, the processor 60 may initialize the BCD timing data T_BCD to a predetermined value within a predetermined range, and if the value of the binary timing data T_BIN is not within a predetermined range, the binary timing data T_BIN may be initialized to a predetermined value within a predetermined range. The predetermined value may be, for example, data in which all bits are 0.

[0087] The write buffer 70 acquires and stores the write data WDAT output from the interface circuit 90. The first counter 30, the second counter 40, the third counter 50, and the processor 60 each receive a portion of the write data WDAT held by the write buffer 70 as input.

[0088] The read buffer 80, in response to a read request signal (not shown) from the interface circuit 90, acquires and stores at least one of the timing data SUBSEC, SEC_BIN, and SEC_BCD generated by the first counter 30, the second counter 40, and the third counter 50, respectively, as well as the BCD timing data T_BCD and binary timing data T_BIN generated by the processor 60, and outputs the stored timing data as read data RDAT to the interface circuit 90.

[0089] The interface circuit 90 is an interface circuit for communication between the real-time clock module 1 and the host device 6. In this embodiment, the interface circuit 90 is I 2 This is a C-bus compatible interface circuit that communicates with the host device 6 based on the serial clock signal SCL input via terminal P6 of the real-time clock circuit 3 and the serial data signal SDA input and output via terminal P7 of the real-time clock circuit 3. 2 C stands for Inter-Integrated Circuit. However, interface circuit 90 may be another serial bus compatible interface circuit such as SPI, or a parallel bus compatible interface circuit. SPI stands for Serial Peripheral Interface.

[0090] The interface circuit 90 receives access signals from the host device 6 via terminals P6 and P7, and performs various processing according to the received access signals.

[0091] Specifically, when the interface circuit 90 receives an access signal from the host device 6 requesting time setting, it transfers the time data included in the access signal to the write buffer 70 as write data WDAT.

[0092] Subsequently, if the timing data SUBSEC is to be written, the interface circuit 90 outputs a write clock signal to the first counter 30, and the first counter 30 updates the timing data SUBSEC with time data representing the time in units of 1 / 1024 seconds included in the data transferred to the write buffer 70, according to the write clock signal.

[0093] Furthermore, if the timing data SEC_BCD is to be written, the interface circuit 90 outputs a write clock signal to the second counter 40 and updates the timing data SEC_BCD with the BCD format seconds data included in the data transferred to the write buffer 70. Furthermore, if the timing data SEC_BIN is to be written, the interface circuit 90 outputs a write clock signal to the third counter 50 and updates the timing data SEC_BIN with the lower 8 bits of the binary format time data included in the data transferred to the write buffer 70.

[0094] Furthermore, if the BCD timing data T_BCD is to be written, the interface circuit 90 outputs a write request signal for the BCD timing data T_BCD to the processor 60, and the processor 60 updates at least a portion of the year data, month data, day of the week data, day data, hour data, minute data, and second data of the BCD timing data T_BCD by writing at least a portion of the data transferred to the write buffer 70 to the storage area A of the RAM 101. Note that if the day of the week data is not to be written, the processor 60 may calculate the day of the week data from the year data, month data, and day data.

[0095] Furthermore, if the binary timing data T_BIN is to be written, the interface circuit 90 outputs a write request signal for the binary timing data T_BIN to the processor 60, and the processor 60 updates the binary timing data T_BIN by writing the data transferred to the write buffer 70 to the memory area C of the RAM 101.

[0096] Furthermore, when the interface circuit 90 receives an access signal from the host device 6 requesting the reading of at least one of the timing data SUBSEC, SEC_BCD, SEC_BIN, T_BCD, or T_BIN, it generates a read request signal (not shown) requesting the reading of the timing data to be read and outputs it to the read buffer 80. The interface circuit 90 then acquires the read data RDAT, which is the timing data to be read that has been acquired and held by the read buffer 80, converts the read data RDAT into a serial data signal SDA, and transmits it to the host device 6 via terminal P7.

[0097] Furthermore, when the interface circuit 90 receives an access signal from the host device 6 requesting alarm setting, it transfers the alarm setting data included in the access signal to the write buffer 70 as write data WDAT, and outputs a write request signal (not shown) to the processor 60 requesting the writing of the alarm setting data to be written.

[0098] Subsequently, if the BCD alarm first setting data A1_BCD is to be written, the interface circuit 90 outputs a write request signal for the BCD alarm first setting data A1_BCD to the processor 60, and the processor 60 updates the BCD alarm first setting data A1_BCD by writing the data transferred to the write buffer 70 to the memory area E of RAM 101. Also, if the BCD alarm second setting data A2_BCD is to be written, the interface circuit 90 outputs a write request signal for the BCD alarm second setting data A2_BCD to the processor 60, and the processor 60 updates the BCD alarm second setting data A2_BCD by writing the data transferred to the write buffer 70 to the memory area F of RAM 101.

[0099] Furthermore, if the binary alarm first setting data A1_BIN is to be written, the interface circuit 90 outputs a write request signal for the binary alarm first setting data A1_BIN to the processor 60, and the processor 60 updates the binary alarm first setting data A1_BIN by writing the data transferred to the write buffer 70 to the memory area G of RAM 101. Furthermore, if the binary alarm second setting data A2_BIN is to be written, the interface circuit 90 outputs a write request signal for the binary alarm second setting data A2_BIN to the processor 60, and the processor 60 updates the binary alarm second setting data A2_BIN by writing the data transferred to the write buffer 70 to the memory area H of RAM 101.

[0100] Furthermore, when the interface circuit 90 receives an access signal from the host device 6 requesting the writing or reading of data to or from the non-volatile memory 102 of the memory 100, it performs the writing or reading of data to or from the non-volatile memory 102. Alternatively, the interface circuit 90 may also receive an access signal requesting the writing or reading of data to or from the RAM 101 of the memory 100 and perform the writing or reading of data to or from the RAM 101. Specifically, writing or reading data targeting BCD timing data T_BCD, binary timing data T_BIN, BCD alarm first setting data A1_BCD, BCD alarm second setting data A2_BCD, binary alarm first setting data A1_BIN, and binary alarm second setting data A2_BIN may be performed by DMA without going through the processor 60. DMA stands for Direct Memory Access.

[0101] Furthermore, when the interface circuit 90 receives an access signal from the host device 6 requesting the writing or reading of data to or from the external flag register 112, the first alarm selection register 113, the second alarm selection register 114, or the control register 115 included in the register group 110, it performs the writing or reading of data to or from the target register.

[0102] The interrupt generation circuit 120 generates an interrupt signal XINT when at least one of the alarm signal SALM and the error signal SERR is output from the processor 60, and outputs the interrupt signal XINT to the host device 6 via terminal P5 of the real-time clock circuit 3. When the host device 6 receives the interrupt signal XINT, it can analyze the cause of the interrupt signal XINT by reading the data held in the external flag register 112 via the interface circuit 90.

[0103] The processor 60 is composed of, for example, a register that sequentially acquires multiple instruction codes constituting the program PGX from RAM 101 in synchronization with the clock signal, a decoder that decodes the instruction codes acquired in the register, an ALU that performs various operations such as addition, subtraction, logical operations, and bit shift operations, two accumulators that each hold two data inputs to the ALU in synchronization with the clock signal, and multiple registers that hold the data resulting from the operations performed by the ALU in synchronization with the clock signal. ALU stands for Arithmetic Logic Unit. For example, the processor 60 performs various data loading and various operations according to each instruction code by pipeline processing in synchronization with the clock signal. Therefore, the timing and alarm processing performed by the processor 60 every second requires a time equivalent to about 10 pulses of the clock signal, and the period of the clock signal that operates the processor 60 must be sufficiently shorter than 1 second. Therefore, as the clock signal, for example, the first clock signal CK1 or the second clock signal CK2 may be used, or an oscillation signal generated by an RC oscillator circuit (not shown) may be used, or the serial clock signal SCL transmitted from the host device 6 may be used.

[0104] Furthermore, a considerable amount of time is required from the time the host device 6 sends a command requesting time setting, alarm setting, or time reading until the processor 60 completes processing the request. Therefore, a busy flag may be provided in the external flag register 112, and the processor 60 may set the busy flag to 1 during the period from the start to the completion of the processing, and when the busy flag is 1, it may be specified that the host device 6 cannot send any new request commands. Alternatively, the processor 60 may output a high-level busy signal to the host device 6 during the period from the start to the completion of the processing, and when the busy flag is high, it may be specified that the host device 6 cannot send any new request commands. Alternatively, when the host device 6 requests time setting, alarm setting, or time reading, it may be specified that there should be a waiting period of a specified amount of time before the host device 6 sends the next request command, or it may be specified that the host device 6 sends a specified number of dummy commands before sending the next request command.

[0105] Furthermore, if a time update timing occurs between the start and completion of processing by the processor 60 for a command requesting time setting, alarm setting, or time reading, special processing such as delaying the time update will be required. To avoid such special processing, the processor 60 may output a dedicated signal to the host device 6 to inform it of the appropriate timing for sending a request command, and the host device 6 may send the next request command within a specified time from the dedicated signal. Alternatively, the processor 60 may notify the host device 6 of the time update timing, and the host device 6 may send the next request command within a specified time after a specified time has elapsed for the timing process to be completed following the notification.

[0106] 1-2. Processing of the Real-Time Clock Module Figure 6 is a flowchart illustrating an example of the processing procedure performed by the real-time clock module 1. It is assumed that each part of the real-time clock module 1 starts operating prior to the processing shown in Figure 6. In addition to the processing shown in Figure 6, the real-time clock module 1 also performs various other processes, such as writing and reading data to and from the various registers included in the register group 110.

[0107] As shown in Figure 6, if the host device 6 requests time setting in step S1, the real-time clock module 1 performs time setting processing in step S2, setting the specified time value to the specified timing data. If the host device 6 does not request time setting in step S1, the real-time clock module 1 does not perform the time setting processing in step S2. Details of the time setting processing procedure will be described later.

[0108] Next, in step S3, if the host device 6 requests time reading, in step S4, the real-time clock module 1 performs time reading processing to output the specified timing data to the host device 6. If there is no time reading request from the host device 6 in step S3, the real-time clock module 1 does not perform the time reading processing in step S4. Details of the time reading processing procedure will be described later.

[0109] Next, in step S5, if the host device 6 requests an alarm setting, in step S6, the real-time clock module 1 performs an alarm setting process, setting the specified time value in the specified alarm setting data. If the host device 6 does not request an alarm setting in step S5, the real-time clock module 1 does not perform the alarm setting process in step S6. Details of the alarm setting process procedure will be described later.

[0110] Next, in step S7, when the time update timing based on the third clock signal CK3 arrives, in step S8, the real-time clock module 1 performs a time update process to update the timing data 200 stored in RAM 101. If the time update timing does not arrive in step S7, the real-time clock module 1 does not perform the time update process in step S8. Details of the time update process will be described later.

[0111] Then, in step S9, the real-time clock module 1 repeats the processes of steps S1 to S8 until timing is terminated by instructions from the host device 6 or the like.

[0112] Figure 7 is a flowchart illustrating an example of the procedure for the time setting process in step S2 of Figure 6.

[0113] As shown in Figure 7, first, in step S21, time data is transferred from the interface circuit 90 to the write buffer 70.

[0114] Next, in step S22, if the request from the host device 6 is for time setting in BCD format, in step S23, the real-time clock module 1 performs BCD time setting processing, setting the BCD time data held in the write buffer 70 to the specified data among the data included in the BCD timing data T_BCD and timing data SEC_BCD. If the request from the host device 6 in step S22 is not for time setting in BCD format, the real-time clock module 1 does not perform the BCD time setting processing in step S23. Details of the BCD time setting processing procedure will be described later.

[0115] Next, in step S24, if the request from the host device 6 is for binary time setting, in step S25, the real-time clock module 1 performs binary time setting processing to set the binary time data held in the write buffer 70 to the binary timing data T_BIN and timing data SEC_BIN. If the request from the host device 6 in step S24 is not for binary time setting, the real-time clock module 1 does not perform the binary time setting processing in step S25. Details of the binary time setting processing procedure will be described later.

[0116] Figure 8 is a flowchart illustrating an example of the procedure for the BCD time setting process in step S23 of Figure 7.

[0117] As shown in Figure 8, first, in step S231, the timing data SEC_BCD held in the second counter 40 is updated with the seconds data included in the time data held in the write buffer 70.

[0118] Next, in step S232, the processor 60 writes the year data, month data, day of the week data, day data, hour data, minute data, and second data contained in the time data held in the write buffer 70 to the storage area A of RAM 101 as the respective data contained in the BCD timing data T_BCD.

[0119] Next, in step S233, the processor 60 sets the first current time selection flag FBUF1=0 and sets the BCD timing data T_BCD stored in memory area A of RAM 101 to the current time.

[0120] Next, in step S234, the processor 60 writes the timing data SEC_BCD held in the second counter 40 and the BCD timing data T_BCD stored in memory area A of RAM 101, excluding the seconds data, to memory area B of RAM 101.

[0121] Next, in step S235, the processor 60 calculates the BCD timing data T_BCD for 1 second later for the data written to memory area B in step S234, and overwrites it in memory area B.

[0122] Next, in step S236, the processor 60 determines whether the value of the BCD timing data T_BCD after 1 second, calculated in step S235, is outside a predetermined range. If, in step S236, the value of the BCD timing data T_BCD after 1 second is outside the predetermined range, the processor 60 performs error processing in step S237. For example, as error processing, the processor 60 performs at least one of the following: outputting an error signal SERR, stopping the update of the BCD timing data T_BCD, and initializing the BCD timing data T_BCD to a value included in the predetermined range. For example, the content of the error processing may be selectable by the host device 6. The processor 60 sets the first error flag FE1 to 1, and the interrupt generation circuit 120 generates an interrupt signal XINT based on the error signal SERR.

[0123] Furthermore, in step S236, if the value of the BCD timing data T_BCD after 1 second is within a predetermined range, and if the first alarm mode is enabled in step S238, then in step S239, the processor 60 determines whether the BCD timing data T_BCD after 1 second matches the BCD alarm first setting data A1_BCD. If the BCD timing data T_BCD after 1 second matches the BCD alarm first setting data A1_BCD in step S239, then in step S240, the processor 60 sets the first pre-alarm flag FAlm1=1.

[0124] Furthermore, if the first alarm mode is disabled in step S238, or if the BCD timing data T_BCD after 1 second and the BCD alarm first setting data A1_BCD do not match in step S239, and the second alarm mode is enabled in step S241, then in step S242, the processor 60 determines whether the BCD timing data T_BCD after 1 second and the BCD alarm second setting data A2_BCD match. If the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD match in step S242, then in step S243, the processor 60 sets the second pre-alarm flag FAlm2=1.

[0125] Figure 9 is a flowchart illustrating an example of the binary time setting process in step S25 of Figure 7.

[0126] As shown in Figure 9, first, in step S251, the timing data SEC_BIN held in the third counter 50 is updated with the lower 8 bits of the time data held in the write buffer 70.

[0127] Next, in step S252, the processor 60 writes the time data held in the write buffer 70 as binary timing data T_BIN to the memory area C of the RAM 101.

[0128] Next, in step S253, the processor 60 sets the second current time selection flag FBUF2=0 and sets the binary timing data T_BIN stored in the memory area C of RAM 101 to the current time.

[0129] Next, in step S254, the processor 60 writes the 8-bit timing data SEC_BIN held in the third counter 50 and the upper 25 bits of the binary timing data T_BIN stored in memory area C of RAM 101 to memory area D of RAM 101.

[0130] Next, in step S255, the processor 60 calculates the binary timing data T_BIN for 1 second later for the data written to the storage area D in step S254, and overwrites it in the storage area D.

[0131] Next, in step S256, the processor 60 determines whether the value of the binary timing data T_BIN calculated in step S255 after 1 second is outside a predetermined range. If, in step S256, the value of the binary timing data T_BIN after 1 second is outside the predetermined range, the processor 60 performs error processing in step S257. For example, as error processing, the processor 60 performs at least one of the following: outputting an error signal SERR, stopping the update of the binary timing data T_BIN, and initializing the binary timing data T_BIN to a value included in the predetermined range. For example, the content of the error processing may be selectable by the host device 6. The processor 60 sets the second error flag FE2 to 1, and the interrupt generation circuit 120 generates an interrupt signal XINT based on the error signal SERR.

[0132] Furthermore, in step S256, if the value of the binary timing data T_BIN after 1 second is within a predetermined range, and if the third alarm mode is enabled in step S258, then in step S259, the processor 60 determines whether the binary timing data T_BIN after 1 second matches the binary alarm first setting data A1_BIN. If the binary timing data T_BIN after 1 second matches the binary alarm first setting data A1_BIN in step S259, then in step S260, the processor 60 sets the third pre-alarm flag FAlm3=1.

[0133] Furthermore, if the third alarm mode is disabled in step S258, or if the binary timing data T_BIN after 1 second and the binary alarm first setting data A1_BIN do not match in step S259, and the fourth alarm mode is enabled in step S261, then in step S262, the processor 60 determines whether the binary timing data T_BIN after 1 second and the binary alarm second setting data A2_BIN match. If the binary timing data T_BIN after 1 second and the binary alarm second setting data A2_BIN match in step S262, then in step S263, the processor 60 sets the fourth pre-alarm flag FAlm4=1.

[0134] Figure 10 is a flowchart illustrating an example of the procedure for the time reading process in step S4 of Figure 6.

[0135] As shown in Figure 10, first, in step S41, if the request from the host device 6 is to read a time in BCD format, and in step S42 the first current time selection flag FBUF1=0, then in step S43 the processor 60 transfers the timing data SEC_BCD held in the second counter 40 and the BCD timing data T_BCD stored in memory area A of RAM 101, excluding the seconds data, to the read buffer 80.

[0136] Furthermore, if the first current time selection flag FBUF1=1 in step S42, in step S44, the processor 60 transfers the timing data SEC_BCD held in the second counter 40 and the BCD timing data T_BCD stored in memory area B of RAM 101, excluding the seconds data, to the read buffer 80.

[0137] If the request from the host device 6 in step S41 is not for reading a time in BCD format, the processor 60 does not perform the processes in steps S42, S43, and S44.

[0138] Next, in step S45, if the request from the host device 6 is to read a time in binary format, and in step S46 the second current time selection flag FBUF2 = 0, then in step S47 the processor 60 transfers the 8-bit timing data SEC_BIN held in the third counter 50 and the upper 25 bits of the binary timing data T_BIN stored in the memory area C of RAM 101 to the read buffer 80.

[0139] Furthermore, if the second current time selection flag FBUF2 = 1 in step S46, in step S48, the processor 60 transfers the 8-bit timing data SEC_BIN held in the third counter 50 and the upper 25 bits of the binary timing data T_BIN stored in the memory area D of RAM 101 to the read buffer 80.

[0140] If the request from the host device 6 in step S45 is not for reading a time in binary format, the processor 60 does not perform the processes in steps S46, S47, and S48.

[0141] Then, in step S49, timing data in BCD format or binary format is transferred from the read buffer 80 to the interface circuit 90.

[0142] Figure 11 is a flowchart illustrating an example of the procedure for the alarm setting process in step S6 of Figure 6.

[0143] As shown in Figure 11, first, in step S61, alarm setting data is transferred from the interface circuit 90 to the write buffer 70.

[0144] Next, in step S62, if the request from the host device 6 is for an alarm setting in BCD format, in step S63, the real-time clock module 1 performs a BCD alarm setting process in which it sets the BCD alarm setting data held in the write buffer 70 to the specified setting data included in the BCD alarm setting data 211. If the request from the host device 6 in step S62 is not for an alarm setting in BCD format, the real-time clock module 1 does not perform the BCD alarm setting process in step S63. Details of the BCD alarm setting process will be described later.

[0145] Next, in step S64, if the request from the host device 6 is for a binary alarm setting, in step S65, the real-time clock module 1 performs a binary alarm setting process, setting the specified setting data in the binary alarm setting data 212 with the binary alarm setting data held in the write buffer 70. If the request from the host device 6 in step S64 is not for a binary alarm setting, the real-time clock module 1 does not perform the binary alarm setting process in step S65. Details of the binary alarm setting process will be described later.

[0146] Figure 12 is a flowchart illustrating an example of the procedure for the BCD alarm setting process in step S63 of Figure 11.

[0147] As shown in Figure 12, first, in step S631, if the request from the host device 6 is for BCD alarm first setting, then in step S632, the processor 60 writes the alarm setting data held in the write buffer 70 as BCD alarm first setting data A1_BCD to the storage area E of RAM 101.

[0148] Next, in step S633, if the request from the host device 6 is for BCD alarm second setting, in step S634, the processor 60 writes the alarm setting data held in the write buffer 70 as BCD alarm second setting data A2_BCD to the storage area F of RAM 101.

[0149] Figure 13 is a flowchart illustrating an example of the procedure for setting a binary alarm in step S65 of Figure 11.

[0150] As shown in Figure 13, first, in step S651, if the request from the host device 6 is for a binary alarm first setting, then in step S652, the processor 60 writes the alarm setting data held in the write buffer 70 as binary alarm first setting data A1_BIN to the storage area G of RAM 101.

[0151] Next, in step S653, if the request from the host device 6 is for binary alarm second setting, in step S654, the processor 60 writes the alarm setting data held in the write buffer 70 as binary alarm second setting data A2_BIN to the storage area H of RAM 101.

[0152] Figure 14 is a flowchart illustrating an example of the time update process in step S8 of Figure 6.

[0153] As shown in Figure 14, first, if the BCD timing mode is enabled in step S81, in step S82, the real-time clock module 1 performs a BCD timing data update process to update the BCD timing data T_BCD stored in RAM 101. If the BCD timing mode is disabled in step S81, the real-time clock module 1 does not perform the BCD timing data update process in step S82. Details of the BCD timing data update process will be described later.

[0154] Next, in step S83, if the binary timing mode is enabled, in step S84, the real-time clock module 1 performs a binary timing data update process to update the binary timing data T_BIN stored in RAM 101. If the binary timing mode is disabled in step S83, the real-time clock module 1 does not perform the binary timing data update process in step S84. Details of the binary timing data update process will be described later.

[0155] Figure 15 is a flowchart illustrating an example of the procedure for the BCD time update process in step S82 of Figure 14.

[0156] As shown in Figure 15, first, if the first pre-alarm flag FAlm1=1 in process S820, then in process S821, the processor 60 sets the first alarm flag FA1=1.

[0157] If the first pre-alarm flag FAlm1=0 in process S820, and the second pre-alarm flag FAlm2=1 in process S822, then in process S823, the processor 60 sets the second alarm flag FA2=1.

[0158] Next, in step S824, the processor 60 outputs an alarm signal SALM, and the interrupt generation circuit 120 generates an interrupt signal XINT.

[0159] If the first pre-alarm flag FAlm1 is 0 in process S820 and the second pre-alarm flag FAlm2 is 0 in process S822, the processor 60 and the interrupt generation circuit 120 do not perform the processing in process S824.

[0160] Next, if the first current time selection flag FBUF1=0 in step S825, then in step S826, the processor 60 sets the first current time selection flag FBUF1=1 and sets the BCD timing data T_BCD stored in memory area B of RAM 101 to the current time.

[0161] Next, in step S827, the processor 60 writes the timing data SEC_BCD held in the second counter 40 and the BCD timing data T_BCD stored in memory area B of RAM 101, excluding the seconds data, to memory area A of RAM 101.

[0162] Next, in step S828, the processor 60 calculates the BCD timing data T_BCD for 1 second later for the data written to memory area A in step S827, and overwrites it in memory area A.

[0163] Furthermore, if the first current time selection flag FBUF1=1 in step S825, then in step S829, the processor 60 sets the first current time selection flag FBUF1=0 and sets the BCD timing data T_BCD stored in memory area A of RAM 101 to the current time.

[0164] Next, in step S830, the processor 60 writes the timing data SEC_BCD held in the second counter 40 and the BCD timing data T_BCD stored in memory area A of RAM 101, excluding the seconds data, to memory area B of RAM 101.

[0165] Next, in step S831, the processor 60 calculates the BCD timing data T_BCD for 1 second later based on the data written to memory area B in step S830, and overwrites it in memory area B.

[0166] Next, in step S832, the processor 60 determines whether the value of the BCD timing data T_BCD after 1 second, calculated in step S828 or step S831, is outside a predetermined range. If, in step S832, the value of the BCD timing data T_BCD after 1 second is outside the predetermined range, the processor 60 performs error processing in step S833. For example, as error processing, the processor 60 performs at least one of the following: outputting an error signal SERR, stopping the update of the BCD timing data T_BCD, and initializing the BCD timing data T_BCD to a value included in the predetermined range. The processor 60 sets the first error flag FE1 to 1, and the interrupt generation circuit 120 generates an interrupt signal XINT based on the error signal SERR.

[0167] Furthermore, in step S832, if the value of the BCD timing data T_BCD after 1 second is within a predetermined range, and if the first alarm mode is enabled in step S834, then in step S835, the processor 60 determines whether the BCD timing data T_BCD after 1 second matches the BCD alarm first setting data A1_BCD. If the BCD timing data T_BCD after 1 second matches the BCD alarm first setting data A1_BCD in step S835, then in step S836, the processor 60 sets the first pre-alarm flag FAlm1=1.

[0168] Furthermore, if the first alarm mode is disabled in step S834, or if the BCD timing data T_BCD after 1 second and the BCD alarm first setting data A1_BCD do not match in step S835, and the second alarm mode is enabled in step S837, then in step S838, the processor 60 determines whether the BCD timing data T_BCD after 1 second and the BCD alarm second setting data A2_BCD match. If the BCD timing data T_BCD and the BCD alarm second setting data A2_BCD match in step S838, then in step S839, the processor 60 sets the second pre-alarm flag FAlm2=1.

[0169] Figure 16 is a flowchart illustrating an example of the binary time update process in step S84 of Figure 14.

[0170] As shown in Figure 16, first, if the third pre-alarm flag FAlm3=1 in process S840, then in process S841, the processor 60 sets the third alarm flag FA3=1.

[0171] If the third pre-alarm flag FAlm3=0 in process S840, and the fourth pre-alarm flag FAlm4=1 in process S842, then in process S843, the processor 60 sets the fourth alarm flag FA4=1.

[0172] Next, in step S844, the processor 60 outputs an alarm signal SALM, and the interrupt generation circuit 120 generates an interrupt signal XINT.

[0173] If the third pre-alarm flag FAlm3 is 0 in process S840 and the fourth pre-alarm flag FAlm4 is 0 in process S842, the processor 60 and the interrupt generation circuit 120 will not perform the processing in process S844.

[0174] Next, if the second current time selection flag FBUF2=0 in step S845, then in step S846, the processor 60 sets the second current time selection flag FBUF2=1 and sets the binary timing data T_BIN stored in the memory area D of RAM 101 to the current time.

[0175] Next, in step S847, the processor 60 writes the 8-bit timing data SEC_BIN held in the third counter 50 and the upper 25 bits of the binary timing data T_BIN stored in the memory area D of RAM 101 to the memory area C of RAM 101.

[0176] Next, in step S848, the processor 60 calculates the binary timing data T_BIN for 1 second later for the data written to the memory area C in step S847, and overwrites it in the memory area C.

[0177] Furthermore, if the second current time selection flag FBUF2=1 in step S845, then in step S849, the processor 60 sets the second current time selection flag FBUF2=0 and sets the binary timing data T_BIN stored in the memory area C of RAM 101 to the current time.

[0178] Next, in step S850, the processor 60 writes the 8-bit timing data SEC_BIN held in the third counter 50 and the upper 25 bits of the binary timing data T_BIN stored in memory area C of RAM 101 to memory area D of RAM 101.

[0179] Next, in step S851, the processor 60 calculates the binary timing data T_BIN for 1 second later for the data written to the storage area D in step S850, and overwrites it in the storage area D.

[0180] Next, in step S852, the processor 60 determines whether the value of the binary timing data T_BIN calculated in step S848 or step S851 after 1 second is outside a predetermined range. If, in step S852, the value of the binary timing data T_BIN after 1 second is outside the predetermined range, the processor 60 performs error processing in step S853. For example, as error processing, the processor 60 performs at least one of the following: outputting an error signal SERR, stopping the update of the binary timing data T_BIN, and initializing the binary timing data T_BIN to a value included in the predetermined range. The processor 60 sets the second error flag FE2 to 1, and the interrupt generation circuit 120 generates an interrupt signal XINT based on the error signal SERR.

[0181] Furthermore, in step S852, if the value of the binary timing data T_BIN after 1 second is within a predetermined range, and if the third alarm mode is enabled in step S854, then in step S855, the processor 60 determines whether the binary timing data T_BIN after 1 second matches the binary alarm first setting data A1_BIN. If the binary timing data T_BIN after 1 second matches the binary alarm first setting data A1_BIN in step S855, then in step S856, the processor 60 sets the third pre-alarm flag FAlm3=1.

[0182] Furthermore, if the third alarm mode is disabled in step S854, or if the binary timing data T_BIN after 1 second and the binary alarm first setting data A1_BIN do not match in step S855, and the fourth alarm mode is enabled in step S857, then in step S858, the processor 60 determines whether the binary timing data T_BIN after 1 second and the binary alarm second setting data A2_BIN match. If the binary timing data T_BIN after 1 second and the binary alarm second setting data A2_BIN match in step S858, then in step S859, the processor 60 sets the fourth pre-alarm flag FAlm4=1.

[0183] 1-3. Example of a processor processing sequence Figure 17 shows an example of a timing processing sequence performed by the processor 60.

[0184] In the example shown in Figure 17, first, as shown in ST1, the first current time selection flag FBUF1=1, and the BCD timing data T_BCD stored in memory area B of RAM101 represents the current time.

[0185] When the next time update timing arrives, the processor 60 sets the first current time selection flag FBUF1=0, as shown in ST2. As a result, the BCD timing data T_BCD stored in memory area A of RAM 101 will represent the current time.

[0186] Next, as shown in ST3, since the first current time selection flag FBUF1=0, the processor 60 writes the timing data SEC_BCD held by the second counter 40 to the memory area B of RAM 101 as seconds data.

[0187] Next, as shown in ST4, since the first current time selection flag FBUF1=0, the processor 60 reads the BCD timing data T_BCD corresponding to the current time stored in memory area A and writes the data other than the seconds data contained in the BCD timing data T_BCD to memory area B of RAM 101.

[0188] Next, as shown in ST5, since the first current time selection flag FBUF1=0, the processor 60 reads the data written to memory area B, calculates the BCD timing data T_BCD for 1 second later, and overwrites it in memory area B.

[0189] When the next time update timing arrives, the processor 60 sets the first current time selection flag FBUF1=1, as shown in ST6. As a result, the BCD timing data T_BCD stored in memory area B of RAM 101 will represent the current time.

[0190] Next, when a time read request occurs, as shown in ST7, the processor 60 reads the BCD timing data T_BCD corresponding to the current time stored in memory area B, since the first current time selection flag FBUF1=1, and transfers the data other than the seconds data contained in the BCD timing data T_BCD to the read buffer 80.

[0191] Next, as shown in ST8, the second counter 40 transfers the timing data SEC_BCD to the read buffer 80. The timing data synthesized in the read buffer 80 is then transmitted to the host device 6 via the interface circuit 90.

[0192] Figure 18 shows an example of the alarm processing sequence by the processor 60. In the example in Figure 18, alarm processing takes place between ST5 and ST6 in Figure 17.

[0193] In the example shown in Figure 18, first, as shown in ST5, the processor 60 reads the data written to memory area B of RAM 101 because the first current time selection flag FBUF1=0, calculates the BCD timing data T_BCD for 1 second later, and overwrites it in memory area B.

[0194] Next, as shown in ST11, the processor 60 reads out the BCD timing data T_BCD stored in memory area B and the BCD alarm first setting data A1_BCD stored in memory area E of RAM 101, since the first current time selection flag FBUF1=0.

[0195] Next, as shown in ST12, if the processor 60 finds that the read BCD timing data T_BCD matches the BCD alarm first setting data A1_BCD, it sets the first pre-alarm flag FAlm1=1.

[0196] When the next time update timing arrives, as shown in ST13, the processor 60 sets the first alarm flag FA1 to 1 because the first pre-alarm flag FAlm1 is 1.

[0197] Next, as shown in ST14, the processor 60 outputs an alarm signal SALM to the interrupt generation circuit 120, and the interrupt generation circuit 120 outputs an interrupt signal XINT to the host device 6.

[0198] Next, as shown in ST6, the processor 60 sets the first current time selection flag FBUF1=1. As a result, the BCD timing data T_BCD stored in memory area B of RAM 101 represents the current time.

[0199] 1-4. Effects As described above, in the real-time clock module 1 of this embodiment, the processor 60 in the real-time clock circuit 3 performs alarm processing by executing a program PGX that is transferred from the non-volatile memory 102 and stored in the RAM 101. Therefore, the content of the alarm processing can be easily changed by changing the program PG stored in the non-volatile memory 102. Furthermore, in the real-time clock module 1 of this embodiment, the processor 60 performs alarm processing based on alarm setting data 210 that is input from the outside via the interface circuit 90 and stored in the RAM 101. Therefore, the content of the alarm processing can be easily changed by changing the content of the alarm setting data 210. Accordingly, with the real-time clock module 1 of this embodiment, various alarm functions can be realized by software processing, so the expandability of the alarm function can be increased without significantly increasing the circuit size.

[0200] Furthermore, in the real-time clock module 1 of this embodiment, the processor 60 in the real-time clock circuit 3 can select to perform alarm processing for BCD format time or for binary format time by executing the program PGX. Therefore, with the real-time clock module 1 of this embodiment, alarm functions for two different time formats can be realized by software processing, thereby increasing the expandability of the alarm function without significantly increasing the circuit size.

[0201] Furthermore, in the real-time clock module 1 of this embodiment, the processor 60 in the real-time clock circuit 3 can perform two-channel alarm processing for BCD format time and two-channel alarm processing for binary format time by executing the program PGX. Therefore, with the real-time clock module 1 of this embodiment, a four-channel alarm function can be realized by software processing, thereby increasing the expandability of the alarm function without significantly increasing the circuit size.

[0202] Furthermore, with the real-time clock module 1 of this embodiment, the timing data 200 and alarm setting data 210 are compressed and stored in the RAM 101, thus suppressing a significant increase in the size of the RAM 101 in order to enhance expandability. In addition, with the real-time clock module 1 of this embodiment, the setting data A1_BCD and A2_BCD of the BCD timing data T_BCD and BCD alarm setting data 211 are in the same compressed format, so the processor 60 can easily perform comparison processing between the BCD timing data T_BCD and the setting data A1_BCD and A2_BCD.

[0203] Furthermore, in the real-time clock module 1 of this embodiment, the processor 60 executes the program PGX in the real-time clock circuit 3, performing timing processing in BCD format or binary format using a double-buffer method with two memory areas A and B or two memory areas C and D of RAM 101. Therefore, with the real-time clock module 1 of this embodiment, the timing function can be realized by software processing, thus increasing the expandability of the timing function without significantly increasing the circuit size. In particular, with the real-time clock module 1 of this embodiment, a BCD format or binary format timing circuit is not required as hardware, so the size of the real-time clock circuit 3 can be reduced. Moreover, with the real-time clock module 1 of this embodiment, the exception of a leap year, which occurs once every 400 years in the timing processing by the processor 60, can also be easily handled by software processing. Therefore, with the real-time clock module 1 of this embodiment, there is no need to provide a circuit that operates only very rarely as hardware, so the size of the real-time clock circuit 3 can be reduced even further.

[0204] Furthermore, according to the real-time clock module 1 of this embodiment, the processor 60 generates timing data 200 corresponding to the next time before the next time update timing arrives, and compares the timing data 200 corresponding to the next time with the alarm setting data 210, so that the alarm signal SALM can be output as soon as the next time update timing arrives.

[0205] Furthermore, according to the real-time clock module 1 of this embodiment, if the value of the timing data 200 is outside a predetermined range, error processing is performed, so that incorrect timing processing is not continued.

[0206] 2. Variations In the above embodiment, the timing data 200 stored in RAM 101 includes two data: BCD timing data T_BCD and binary timing data T_BIN. However, the number of data included in the timing data 200 is not limited to two; it may be one or three or more.

[0207] Furthermore, in the above embodiment, the alarm setting data 210 stored in RAM 101 includes four setting data: BCD alarm first setting data A1_BCD, BCD alarm second setting data A2_BCD, binary alarm first setting data A1_BIN, and binary alarm second setting data A2_BIN. However, the number of setting data included in the alarm setting data 210 is not limited to four; it may be one, two, three, or five or more.

[0208] Furthermore, in the above embodiment, the various flags are held by registers, but they may also be stored in RAM 101.

[0209] Furthermore, in the above embodiment, the processor 60 performs error processing if the value of the timing data 200 is outside a predetermined range, but similar error processing may also be performed if the value of the alarm setting data 210 is not included in a predetermined range corresponding to the range of times in which it may exist. In addition, the processor 60 may perform error processing if the time data held in the write buffer 70 is outside a predetermined range before writing the timing data 200 or alarm setting data 210 to the RAM 101.

[0210] Furthermore, in the above embodiment, the real-time clock circuit 3 includes a second counter 40 and a third counter 50, but it is not necessary to include at least one of the second counter 40 and the third counter 50. If the second counter 40 is not present, the processor 60, if the BCD timing mode is enabled, may add 1 to the BCD timing data T_BCD corresponding to the current time stored in one of the memory areas A and B of the RAM 101 every second to generate BCD timing data T_BCD corresponding to the time one second later, and store it in the other memory area A and B. Also, if the third counter 50 is not present, the processor 60, if the binary timing mode is enabled, may add 1 to the binary timing data T_BIN corresponding to the current time stored in one of the memory areas C and D of the RAM 101 every second to generate binary timing data T_BIN corresponding to the time one second later, and store it in the other memory area C and D.

[0211] Furthermore, in the above embodiment, the processor 60 generates the timing data 200 by executing the program PGX, but instead, the real-time clock circuit 3 may be provided with a hardware timing circuit that generates part or all of the timing data 200. In this case, the processor 60 may execute the program PGX to obtain timing data corresponding to the current time from the timing circuit, calculate the timing data for 1 second later, store the timing data for 1 second later in the RAM 101, and perform alarm processing in software.

[0212] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0213] The embodiments and variations described above are examples only and are not limiting. For example, each embodiment and each variation can be combined as appropriate.

[0214] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0215] The following can be derived from the embodiments and modifications described above.

[0216] One embodiment of a real-time clock module is: An oscillator circuit that generates a first clock signal by causing an oscillator to oscillate, An interface circuit into which alarm setting data is input, The memory in which the alarm setting data and program are stored, The system includes a processor that, by executing the program, performs a comparison process to compare timing data generated based on the first clock signal with the alarm setting data, and outputs an alarm signal according to the result of the comparison process.

[0217] In this real-time clock module, the processor performs a comparison process between timing data and alarm setting data by executing a program, so the content of the comparison process can be easily changed by modifying the program. Furthermore, in this real-time clock module, the processor performs the comparison process based on alarm setting data input from an external source via an interface circuit, so the content of the comparison process can be easily changed by modifying the content of the alarm setting data. Therefore, with this real-time clock module, various alarm functions can be implemented through software processing, thereby increasing the expandability of alarm functions without significantly increasing the circuit size.

[0218] One embodiment of the real-time clock module is: The system includes a counter that counts the number of pulses in a second clock signal based on the first clock signal and outputs a third clock signal based on the counted value. The processor may generate the timing data based on the third clock signal by executing the program.

[0219] In one embodiment of the real-time clock module, The aforementioned timing data is at least one of BCD format timing data and binary format timing data. The alarm setting data may be at least one of BCD format setting data and binary format setting data.

[0220] In this real-time clock module, the processor can perform comparison processing between BCD format timing data and alarm setting data, or between binary format timing data and alarm setting data, by executing a program. Therefore, with this real-time clock module, alarm functions for two different time formats can be implemented through software processing, thereby increasing the scalability of alarm functions without significantly increasing the circuit size.

[0221] In one embodiment of the real-time clock module, The alarm setting data may include multiple setting data corresponding to multiple times.

[0222] In this real-time clock module, the processor can perform a comparison process between each of the multiple setting data included in the alarm setting data and the timing data by executing a program. Therefore, with this real-time clock module, alarm functions for multiple time points can be implemented through software processing, thereby increasing the scalability of the alarm function without significantly increasing the circuit size.

[0223] In one embodiment of the real-time clock module, The alarm setting data and the timing data may be compressed in the same format and stored in the memory.

[0224] With this real-time clock module, alarm setting data and timing data are compressed and stored in memory, thus suppressing a significant increase in memory size to enhance scalability. Furthermore, with this real-time clock module, since the alarm setting data and timing data are in the same compressed format, the processor can easily compare the timing data and alarm setting data.

[0225] In one embodiment of the real-time clock module, The aforementioned timing data is stored in the memory. The aforementioned processor, The first timing data, which is the timing data corresponding to the current time, is read from the memory. Based on the first timing data, a second timing data, which is the timing data corresponding to the next time, is generated and stored in the memory. If the second timing data and the alarm setting data match, the alarm signal may be output at the next time update timing.

[0226] This real-time clock module allows the timing function to be implemented through software processing, thereby increasing the scalability of the timing function without significantly increasing the circuit size. Furthermore, with this real-time clock module, the processor generates a second timing data corresponding to the next time before the next time update timing occurs, and compares this second timing data with the alarm setting data, so that an alarm signal can be output as soon as the next time update timing occurs.

[0227] In one embodiment of the real-time clock module, The aforementioned processor, If the value of the timing data does not fall within a predetermined range, at least one of the following processes may be performed: outputting an error signal, stopping the updating of the timing data, and initializing the timing data to a value that falls within the predetermined range.

[0228] This real-time clock module prevents the continued use of incorrect timing processes. [Explanation of Symbols]

[0229] 1…Real-time clock module, 2…Oscillator, 3…Real-time clock circuit, 4…Main power supply, 5…Backup power supply, 6…Host device, 10…Oscillator circuit, 20…Frequency divider circuit, 30…First counter, 40…Second counter, 50…Third counter, 60…Processor, 70…Write buffer, 80…Read buffer, 90…Interface circuit, 100…Memory, 101…RAM, 102…Non-volatile memory, 110…Register group, 111…Internal flag register, 112…External flag register, 113…First alarm selection register, 114…Second alarm selection register, 115…Control register, 120…Interrupt generation circuit, 130…Power supply voltage selection circuit, 140…Power supply voltage determination circuit, 150…Regulator, 200…Timekeeping data, 210…Alarm setting data, 211…BCD alarm setting data, 212…Binary alarm setting data

Claims

1. An oscillator circuit that generates a first clock signal by causing an oscillator to oscillate, An interface circuit into which alarm setting data is input, The memory in which the alarm setting data and program are stored, The system includes a processor that, by executing the program, performs a comparison process to compare timing data generated based on the first clock signal with alarm setting data, and outputs an alarm signal according to the result of the comparison process, The aforementioned timing data is stored in the memory. The aforementioned processor, The first timing data, which is the timing data corresponding to the current time, is read from the memory. Based on the first timing data, a second timing data, which is the timing data corresponding to the next time, is generated and stored in the memory. A real-time clock module that compares the second timing data with the alarm setting data, and if the second timing data and the alarm setting data match, outputs the alarm signal at the next time update timing.

2. The system includes a counter that counts the number of pulses in a second clock signal based on the first clock signal and outputs a third clock signal based on the counted value. The real-time clock module according to claim 1, wherein the processor generates the timing data based on the third clock signal by executing the program.

3. The aforementioned timing data is at least one of BCD format timing data and binary format timing data. The real-time clock module according to claim 2, wherein the alarm setting data is at least one of setting data in BCD format and setting data in binary format.

4. The real-time clock module according to any one of claims 1 to 3, wherein the alarm setting data includes a plurality of setting data corresponding to a plurality of times.

5. The real-time clock module according to any one of claims 1 to 4, wherein the alarm setting data and the timing data are compressed in the same format and stored in the memory.

6. The aforementioned processor, A real-time clock module according to any one of claims 1 to 5, which performs at least one of the following processes if the value of the timing data does not fall within a predetermined range: outputting an error signal, stopping the updating of the timing data, and initializing the timing data to a value that falls within the predetermined range.

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