Polymer coatings for semiconductor processing chamber components

Abstract

A component within a semiconductor processing chamber is provided. The conductive semiconductor or metal body has a thickness of 10.0×10 -6 / K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxyalkane (PFA) layer is disposed over the intermediate layer to form a component.

Description

[Technical Field]

[0001] Cross-references to related applications This application claims priority under U.S. Patent Application No. 63 / 158,115, filed on 8 March 2021, which is incorporated herein by reference for all purposes.

[0002] This disclosure generally relates to the manufacture of semiconductor devices. More specifically, this disclosure relates to chamber components used in the manufacture of semiconductor devices.

[0003] During semiconductor wafer processing, a plasma processing chamber is used to process semiconductor devices. The plasma processing chamber is exposed to halogen plasma and / or oxygen plasma, and the plasma can degrade the components within the plasma processing chamber.

[0004] The background art provided herein is intended to provide a general overview of the background to this disclosure. The works of the inventors named herein, to the extent described herein, are not considered prior art to this disclosure, either explicitly or implicitly, along with any manner of description that would not ordinarily be considered prior art at the time of filing. [Overview of the project]

[0005] To achieve the above, components within a semiconductor processing chamber are provided in accordance with the purposes of this disclosure. The conductive semiconductor or metal body is 10.0 × 10 -6 It has a CTE of less than / K. An intermediate layer is disposed on at least one surface of the main body, and the intermediate layer contains a fluorine polymer. A perfluoroalkoxyalkane (PFA) layer is disposed on the intermediate layer so as to form a component.

[0006] In another embodiment, an edge ring for use in a plasma processing chamber is provided. An elemental silicon edge ring body is provided. A fluorine polymer is present on at least one surface of the elemental silicon edge ring body. A perfluoroalkoxyalkane (PFA) coating is provided, which is fluorinated ethylene propylene or polyethersulfate. Ho It is on top of the coating.

[0007] In another embodiment, a method is provided for forming components for use in a semiconductor processing chamber. A conductive semiconductor or metal body is provided, the body being 10.0 × 10 -6 It has a CTE of less than / K. An intermediate layer is formed on at least one surface of the main body, and the intermediate layer contains a fluorine polymer. A perfluoroalkoxyalkane (PFA) layer is formed on the intermediate layer so as to form a component.

[0008] The above-mentioned and other features of this disclosure will be described in detail in the detailed description made with reference to the attached drawings. [Brief explanation of the drawing]

[0009] The attached drawings illustrate this disclosure for illustrative purposes only, not for limitation. In these attached drawings, similar components are denoted by the same reference numerals.

[0010] [Figure 1] A schematic flowchart of one embodiment.

[0011] Figures 2A to 2E show one embodiment of a method for processing edge ring components used in a plasma processing chamber. [Figure 2A] A top view showing the component substrate in the form of an edge ring. [Figure 2B] Cross-sectional view of the component substrate in Figure 2A. [Figure 2C] Detailed cross-sectional view of the substrate surface in Figure 2A. [Figure 2D]Detailed cross-sectional view of the intermediate fluoropolymer layer coated on the substrate shown in Figure 2A. [Figure 2E] Detailed cross-sectional view of the structure shown in Figure 2D after a perfluoroalkoxyalkane (PFA) layer has been coated onto a fluoropolymer intermediate layer to form components for a plasma processing chamber.

[0012] [Figure 3] A cross-sectional view showing a portion of the plasma processing chamber.

[0013] [Figure 4] A schematic diagram showing a plasma processing chamber that can be used in one embodiment. [Modes for carrying out the invention]

[0014] The following description provides a detailed explanation of the disclosure with reference to several preferred embodiments illustrated in the accompanying drawings. The following description includes numerous specific details to facilitate a full understanding of the disclosure. However, as will be apparent to those skilled in the art, the disclosure can be implemented without some or all of these specific details. Furthermore, to avoid unnecessarily obscuring the disclosure, detailed descriptions of well-known processes and / or structures have been omitted.

[0015] The various embodiments described herein provide semiconductor processing chamber components that are resistant to damage caused by arc discharge and / or corrosion resulting from processes such as plasma etching, thereby suppressing or minimizing wear on components that may result from plasma processing and etching processes inherent in semiconductor processing systems such as plasma processing chambers.

[0016] To facilitate understanding, Figure 1 is a schematic flowchart illustrating the process of a first embodiment for manufacturing and utilizing components for a semiconductor processing chamber (such as a plasma processing chamber). The component body is provided (step 104). The component body has a low coefficient of thermal expansion (CTE) (e.g., 10.0 × 10⁻⁶). -6 / K~5.0x10 -6 It includes a conductive semiconductor or metal material having a (less than / K). As will be described in more detail later, the conductivity and low CTE of the component body are particularly beneficial attributes for use in components of semiconductor processing chambers (such as plasma processing chambers).

[0017] Referring to FIGS. 2A - 2C, the provided substrate body 204 may be formed in the shape of a component for use in a plasma processing chamber, such as an edge ring having an inner diameter surface or a central hole 208 that at least partially surrounds an electrostatic chuck (ESC). FIG. 2A is a top view of the substrate body, FIG. 2B is a cross - sectional view of the substrate body, and FIG. 2C is an enlarged cross - sectional view of section A - A of the substrate body surface 212. It is understood that the drawings shown in FIGS. 2A - 4 are for illustrative purposes only and may vary with respect to scale, form, and features. The substrate body 204 may be formed by many different processing operations (such as machining, casting, sintering, polishing, chemical etching, etc.).

[0018] According to one embodiment, the substrate body 204 has a low coefficient of thermal expansion (CTE) (e.g., 10.0×10 -6 / K or less, and in a further embodiment, 5.0×10 -6The conductive material has a coefficient of thermal expansion less than 1 / K. In further embodiments, the substrate body 204 comprises a conductive semiconductor, in particular a conductive polycrystalline (multi-crystalline) doped silicon or silicon carbide semiconductor material. In another embodiment, the substrate body 204 comprises elemental silicon. In alternative embodiments, the substrate body may comprise other conductive semiconductors (e.g., germanium) or low CTE metals (e.g., titanium). In various embodiments, the semiconductor may be polycrystalline. Polycrystalline (multi-crystalline) silicon has particles that are on average larger than polycrystalline (polycrystalline) silicon particles. Polycrystalline (multi-crystalline) silicon has an average particle size greater than 1 mm. A low coefficient of thermal expansion generally provides lower stress, wear, and better fit between components. In particular, during chamber processing, edge rings and other adjacent components (especially the ESC base plate) reach different temperatures. Due to heating caused by plasma, the edge ring generally becomes much hotter (in the range of 150°C to 250°C) than the ESC baseplate, whose temperature is actively controlled (in the range of -40°C to 50°C). By selecting an edge ring material with a low coefficient of thermal expansion, variations in the gap size between the edge ring and the adjacent component (ESC) are effectively reduced, resulting in a more consistent capacitance between the two conductors. Consequently, more consistent electrical performance is achieved.

[0019] In one embodiment, the component body is formed by shaping a specific component (for example, by pouring or injecting molten semiconductor into a mold), where the molten semiconductor is cooled in the mold to a hardened state to form a polycrystalline (multicrystalline) structure with large grain size. In another embodiment, the semiconductor is solidified into a cylindrical shape and then machined to a final shape by grinding or other machining techniques.

[0020] Referring to FIGS. 1 and 2D, after the substrate body 204 is provided, an intermediate fluoropolymer layer 216 (FIG. 2D) is formed on one or more surfaces 212 of the substrate body 204 (step 108). The intermediate fluoropolymer layer 216 aids in the adhesion of subsequent layers (e.g., the PFA layer 224 in FIG. 2D) to the substrate body 204. In one embodiment, the intermediate fluoropolymer layer 216 comprises a fluoropolymer (such as fluorinated ethylene propylene (FEP)) having a high curing temperature (e.g., 350° C. to 400° C.) and a composition that aids in the bonding of the subsequent PFA layer 224. In another embodiment, the intermediate fluoropolymer layer 216 comprises a resin (e.g., polyethersulfone Ho (PES)) to aid in bonding to the substrate surface 212. Further, the intermediate fluoropolymer layer 216 has little to no coloring (i.e., is transparent) to minimize contamination within the processing chamber. To aid in vapor deposition (e.g., liquid spray vapor deposition techniques), the intermediate fluoropolymer layer 216 comprises a solvent-based or aqueous composition. In one embodiment, the intermediate fluoropolymer layer 216 is composed of Xylan® 8840 dry film lubricant manufactured by PPG Industries Ohio, Inc. of Cleveland, Ohio. However, it is understood that any resin-bonded or resin-based, FEP-based coating (particularly solvent-based or aqueous) may be used.

[0021] According to several embodiments, the intermediate fluoropolymer layer 216 is deposited using a spray deposition method that provides a substantially uniform layer so as to function as a primer for subsequent layer coatings with proper adhesion to the underlying substrate body 204. To facilitate spray deposition, the intermediate fluoropolymer layer 216 is aqueous or solvent-based. In alternative embodiments, deposition methods (chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), electrodeposition (electrodeposition coating, e.g., also known as Elecoat Nicelon® from Shimizu Corporation (shimizu-corp.co.jp), or similar deposition methods, etc.) may be used. In one embodiment, prior to the application of any coating layer, the substrate body 204 is pre-treated to remove or substantially remove any oxides (e.g., silicon oxide) and surface damage to the substrate surface 212 or loosely adhering microstructures on the substrate surface 212 that may have occurred during processing. For example, when priming a silicon substrate, a deionized (DI) water rinse may be performed on the substrate body 204, and then mixed acid etching may be performed to remove any surface defects and increase the surface roughness to, for example, 20 microns or more.

[0022] The thickness of the intermediate fluoropolymer layer 216 may be varied by one or more factors, such as the type of component, the position of the component, the geometry of the component, the substrate material properties, and the cost. According to one embodiment, the thickness of the intermediate fluoropolymer layer 216 is between approximately 1 micrometer (μm) and 30 μm.

[0023] Referring to Figures 1 and 2E, after the intermediate fluoropolymer layer 216 is formed, a final coating or layer is applied to the surface 220 of the intermediate fluoropolymer layer 216. The final coating layer is also a fluoropolymer (e.g., perfluoroalkoxyalkane (PFA)) that has excellent resistance to high-temperature acids, and is hereafter referred to as the PFA layer 224. Other fluoropolymers may be considered. For example, polytetrafluoroethylene (PTFE) may be used, but it is generally more porous. Figure 2E is a cross-sectional view showing one embodiment of a part of the substrate body 204 after the application of the PFA layer 224. As shown in Figure 2E, the PFA layer 224 is added on the original surface 220 of the intermediate fluoropolymer layer 216, thereby increasing the overall thickness of the component. In some embodiments, the PFA layer 224 is at least 20 μm thick and may be 150 μm or thicker. Since PFA generally has poor adhesion to metals and semiconductors (such as silicon), the intermediate fluoropolymer layer 216 acts as a primer to the substrate body 204. Since the PFA bonds well to the intermediate fluoropolymer layer 216, which has good overall adhesion to the semiconductor substrate body 204, the resulting PFA layer 224 coating is firmly attached to the substrate body 204, minimizing delamination or separation. According to some embodiments, the PFA layer 224 is applied to the intermediate fluoropolymer layer 216 using an electrostatic spray deposition method, which provides a substantially uniform layer across the surface of the substrate body 204.

[0024] As detailed above, the PFA coated substrate body, processed according to steps 104-112 of the process in Figure 1, has minimal contaminants and high corrosion resistance to chemicals and corrosive processes specific to the semiconductor processing chamber.

[0025] The component 200 is placed in a semiconductor processing chamber (such as a plasma processing chamber) after being properly processed in steps 104-112 of Figure 1 (step 116, Figure 1). The processing shown in Figure 1 is particularly useful for manufacturing plasma processing chamber components using substrate materials that are typically consumed very rapidly by common oxygen / halogen reactants in plasma processing chambers.

[0026] In the following embodiments, the components 200 formed from the processes shown in Figures 1 and 2A to 2E are directed to specific applications as edge rings or similar components within an electrostatic chuck (ESC) assembly or system (e.g., the ESC assembly 300 in Figure 3) used in a plasma processing chamber (e.g., the plasma processing chamber 404 shown in Figure 4). However, it is understood that the components 200 formed from the processes shown in Figures 1 and 2A to 2E may be implemented as any number of components (particularly high-flow liners, gas distribution plates, etc., as well as pinnacles® and electrostatic chucks (ESCs)) within the ESC assembly 300 or plasma processing chamber 404, provided that high corrosion resistance, good conductivity, and low thermal expansion properties are desired.

[0027] Figure 3 is a cross-sectional view showing a portion of an ESC assembly 300 having a movable edge ring configuration for use in a plasma processing system (defined by section BB shown in Figure 4). The ESC assembly 300 includes an upper edge ring 324 configured to surround an electrostatic chuck (ESC) 304. The ESC 304 may also be called a substrate support, which functions as a support for the processing wafer 466 during processing. The upper edge ring 324 has an annular lower recess 326 supported by a movable edge ring 308. The movable edge ring 308 is arranged to move vertically articulate within a cavity defined by the ESC 304, heating plate 352, and central inner edge ring 328 radially inward, and the stationary edge ring 316, outer edge ring 312, and cover edge ring 320 radially outward. The cover edge ring 320 has a radially inward projection 322 that partially covers the upper edge ring 324.

[0028] The upper edge ring 324 is constantly worn down because it is exposed to corrosive plasma and etchant during the processing of the wafer 466, so its thickness decreases as the exposure increases. Therefore, the movable edge ring 308 is used to lift the edge ring 324 to restore the height relationship between the upper surface of the upper edge ring 324 and the wafer / substrate 466. To act on such height adjustment, one or more lift pins 340 are actuated vertically (through the opening 348 of the ESC 304 and the opening 318 of the stationary edge ring 316) to push up the movable edge ring 308 and, in turn, adjust the vertical position of the upper edge ring 324. A sleeve 344 is positioned around the outer circumference of the lift pins 340 to seal the opening 348 of the ESC 304.

[0029] According to one embodiment, the component 200 is machined according to the process shown in Figures 1 and 2A-2E to form a stationary edge ring 316 to be attached to the ESC assembly 300. The stationary edge ring 316 benefits greatly from the corrosion resistance of the intermediate fluoropolymer / PFA coating 216 / 224 of the component 200 due to its position in the chamber and its proximity to / exposure to the plasma during processing of the wafer 466 (i.e., having one or more "plasma-facing surfaces"). In one example, plasma can pass through the upper edge ring 324 and the outer edge rings 312 and cover edge ring 320 to the outer surface of the movable edge ring 308 and the inner surface of the stationary edge ring 316 (e.g., the inner diameter surface or central hole 208 in Figure 2B). The amount of plasma that passes through depends on the position of the upper edge ring 324. Furthermore, at the position shown in Figure 3, the upper edge ring 324 can prevent plasma from reaching the inner or outer surface of the movable edge ring 308 by passing between the upper edge ring 324 and the central inner edge ring 328 and / or the outer edge ring 312. When the movable edge ring 308 lifts the upper edge ring 324, a gap is created between the upper edge ring 324 and the central inner edge ring 328 and / or the outer edge ring 312, allowing plasma to reach the surfaces of the movable edge ring 308 and the stationary edge ring 316.

[0030] In one embodiment, the entire outer surface of the stationary edge ring 316 may be treated to have an intermediate fluoropolymer / PFA coating 216 / 224, as provided in component 200. However, it is understood that only a portion of the outer surface of the component may be treated. For example, the outer surface of the stationary edge ring 316, i.e., the outer diameter surface, may be excluded from the PFA layer 224 (e.g., by masking or similar treatment) so that only the plasma-facing surface (e.g., the inner diameter surface 208, see Figure 2B) has the intermediate fluoropolymer / PFA coating 216 / 224. Such partial coating treatment may require uncoated masked portions. The plasma-facing surface is a surface that is exposed to plasma during plasma treatment or to reactive halogen species at high temperature and low pressure. The reactive halogen species may be formed from remote plasma or thermally reactive fluorine. In some embodiments, several points on the movable edge ring 308 may be used to connect to electrodes during electroplating and are therefore not coated.

[0031] Furthermore, the movable edge ring 308, together with the stationary edge ring 316, benefits from the conductivity of the substrate body 204 of the component 200 in order to achieve a more uniform plasma during chamber processing and improve wafer processing uniformity near the edge by providing an RF conduction (AC) path to the ESC 304. Therefore, among the components of the ESC assembly 300 and the plasma processing chamber system 400, the movable edge ring 308 and the upper edge ring 324 in particular may be formed to have an intermediate fluoropolymer / PFA coating 216 / 224 of the component 200 using the processing shown in Figures 1 and 2A to 2E.

[0032] Returning to the process disclosed in Figure 1, the component 200 is utilized in a plasma processing chamber to facilitate semiconductor processing on the processing wafer 466 (step 120). The plasma processing may be one or more processes from etching, deposition, passivation, or other plasma processing. The plasma processing may be performed in combination with non-plasma processing.

[0033] To facilitate understanding, Figure 4 shows a schematic diagram of an example of a plasma processing chamber system 400 available in one embodiment. The plasma processing chamber system 400 comprises a plasma reactor 402 having a plasma processing chamber 404 inside. A plasma power supply 406, regulated by a power matching network 408, powers a transformer-coupled plasma (TCP) coil 410 located near a dielectric inductive power window 412 to generate plasma 414 within the plasma processing chamber 404 by supplying inductively coupled power. A pinnacle 472 extends from the chamber wall 476 of the plasma processing chamber 404 to the dielectric inductive power window 412, forming a pinnacle ring. The pinnacle 472 is angled with respect to the chamber wall 476 and the dielectric inductive power window 412. For example, the internal angle between the pinnacle 472 and the chamber wall 476, and the internal angle between the pinnacle 472 and the dielectric inductive power window 412, may each be greater than 90° and less than 180°. The pinnacle 472 provides a slanted ring near the top of the plasma processing chamber 404, as shown in the figure. The TCP coil (upper power source) 410 may be configured to produce a uniform diffusion profile within the plasma processing chamber 404. For example, the TCP coil 410 may be configured to generate a toroidal power distribution within the plasma 414. A dielectric inductive power window 412 is provided to isolate the TCP coil 410 from the plasma processing chamber 404 while allowing energy to pass from the TCP coil 410 to the plasma processing chamber 404. A wafer bias voltage power supply 416, tuned by a bias matching network 418, powers the ESC assembly 300 to set the bias voltage when the processing wafer 466 is placed on the ESC assembly 300. A controller 424 controls the plasma power supply 406 and the wafer bias voltage power supply 416.

[0034] The plasma power supply 406 and the wafer bias voltage power supply 416 may be configured to operate at specific high frequencies (e.g., 13.56 megahertz (MHz), 27 MHz, 1 MHz, 2 MHz, 60 MHz, 400 kilohertz (kHz), 2.54 gigahertz (GHz), or a combination thereof). The plasma power supply 406 and the wafer bias voltage power supply 416 may be appropriately sized to supply a range of power to achieve desired processing performance. For example, in one embodiment, the plasma power supply 406 may supply power in the range of 50 to 5000 watts, and the wafer bias voltage power supply 416 may supply a bias voltage of 20 to 3000 volts (V). Furthermore, the TCP coil 410 and / or ESC assembly 300 may consist of two or more subcoils or subelectrodes. The subcoils and subelectrodes may be powered by a single power supply or by multiple power supplies.

[0035] As shown in Figure 4, the plasma processing chamber system 400 further comprises a gas source / gas supply mechanism 430. The gas source 430 is in fluid communication with the plasma processing chamber 404 through a gas inlet (such as a gas injector 440). The gas injector 440 has at least one borehole 441 to allow gas to enter the plasma processing chamber 404 through the gas injector 440. The gas injector 440 may be located at any advantageous position within the plasma processing chamber 404 and may take any form for injecting gas. However, preferably, the gas inlet may be configured to produce an "adjustable" gas injection profile. The adjustable gas injection profile allows for independent adjustment of the flow rate to each of several compartments within the plasma processing chamber 404. More preferably, the gas injector is mounted on a dielectric induction power window 412. The gas injector may be mounted above the power window, mounted inside the power window, or form part of the power window. The processing gas and by-products are removed from the plasma processing chamber 404 via a pressure control valve 442 and a pump 444. The pressure control valve 442 and pump 444 also function to maintain a specific pressure within the plasma processing chamber 404. The pressure control valve 442 can maintain a pressure of less than 1 Torr during processing. One or more edge rings may be positioned around the top of the ESC assembly 300. The gas source / gas supply mechanism 430 is controlled by a controller 424. Kiyo®, Strata®, or Vector® from Lam Research, Inc., Fremont, California may be used to carry out one embodiment.

[0036] The wafer to be processed 466 is placed in the plasma processing chamber 404, specifically on or inside the ESC assembly 300, as shown in Figure 3. Plasma processing is performed on the wafer to be processed 466 (e.g., step 120 in Figure 1). In this example, the plasma processing of the wafer to be processed 466 is used to provide etching of a portion of the stack on the wafer to be processed 466, such as etching a tungsten-containing layer in the stack. In this embodiment, the plasma processing is heated to a temperature higher than 550°C. Furthermore, the plasma processing deposits residue inside the plasma processing chamber 404. After the plasma processing of the wafer to be processed 466, the wafer to be processed 466 is removed from the plasma processing chamber 404. The plasma processing chamber 404 is cleaned to remove the deposited residue. In this embodiment, reactive fluorine from a remote fluorine plasma is used to clean the inside of the plasma processing chamber 404. A pressure in the range of 1 mm Torr (mTorr) to 10 Torr is provided. The ESC assembly 300 is not sufficiently cooled and remains at a temperature above 500°C. After cleaning is complete, a new processing wafer 466 may be placed in the plasma processing chamber 404 to start a new cycle. In another example, plasma processing is used to provide etching including a carbon layer, a polysilicon layer, or an oxide / nitride layer. In such an example, the wafer temperature is controlled in the range of 0°C to 150°C, and the chamber is cleaned after wafer processing with in-situ oxygen (O2) and nitrogen trifluoride (NF3) plasma.

[0037] In various embodiments, the intermediate fluoropolymer / PFA coating 216 / 224 and features of component 200 may be mounted on various parts of the plasma processing chamber 404, such as the confinement ring, edge ring, electrostatic chuck, grounding ring, chamber liner, door liner, pinnacle, showerhead, dielectric power window, gas injector, edge ring, ceramic transfer arm, or other components. For example, the intermediate fluoropolymer / PFA coating 216 / 224 may be formed on the upper edge ring 324. While the component 200 and ESC assembly 300 are shown in an embodiment of Figure 4 with respect to their use in an inductively coupled plasma (ICP) reactor for the plasma processing chamber system 400, it is understood that other components and / or types of plasma processing chambers may be used. Examples of other types of plasma processing chambers in which component 200 may be used include capacitively coupled plasma processing chambers (CCPs), bevel plasma processing chambers, and similar processing chambers. In another example, the plasma processing chamber may be a dielectric processing chamber or a conductive processing chamber. An example of such a plasma processing chamber is the Exelan Flex® etching system manufactured by Lam Research® in Fremont, California.

[0038] While the present disclosure has been described above with reference to several preferred embodiments, there are substitutes, replacements, modifications, and various alternative equivalents within the scope of this disclosure. It should also be noted that there are numerous other ways of carrying out the methods and apparatus of this disclosure. Therefore, the appended claims shall be interpreted as encompassing all such substitutes, replacements, and various alternative equivalents that fall within the true intent and scope of this disclosure. This disclosure may be implemented in the following forms: [Form 1] A component within a semiconductor processing chamber, A conductive semiconductor or metal body, The main body is 10.0 × 10 -6 The main body has a CTE of less than / K, An intermediate layer disposed on at least one surface of the main body, wherein the intermediate layer includes a fluoropolymer, A perfluoroalkoxyalkane (PFA) layer is disposed on the intermediate layer to form the aforementioned components, A component comprising: [Form 2] A component described in Form 1, The aforementioned body is a semiconductor body containing silicon or silicon carbide, which is a component. [Form 3] A component described in Form 2, The aforementioned semiconductor body is a component containing elemental silicon. [Form 4] A component described in Form 1, The aforementioned main body is 5.0 × 10 -6 Components having a CTE less than / K. [Form 5] A component described in Form 1, The intermediate layer is a component that is polyethersulfone (PES) resin-based to facilitate bonding of the main body to the at least one surface. [Form 6] A component described in Form 1, The intermediate layer is a component that is aqueous or solvent-based, in order to allow coating of the intermediate layer to the at least one surface of the main body by spray deposition or to enable the intermediate layer to be applied. [Form 7] A component described in Form 1, The PFA layer is a component that is coated onto the intermediate layer by spray deposition for bonding to the intermediate layer. [Form 8] A component described in Form 1, The aforementioned components are configured to be installed in a semiconductor processing chamber. The aforementioned components form a ring around an electrostatic chuck within the semiconductor processing chamber, and the electrostatic chuck supports the wafer for processing. [Form 9] A component described in Form 1, The semiconductor processing chamber includes a plasma processing chamber. The component is exposed to a corrosive treatment within the plasma treatment chamber, and the PFA layer is resistant to damage or corrosion caused by the corrosive treatment. [Form 10] A component described in Form 1, The intermediate layer is a component that is fluoroethylene propylene resin-based to facilitate bonding of the main body to the at least one surface. [Form 11] A component described in Form 1, The fluorine polymer is a component that is at least one of fluorinated ethylene propylene (FEP) and polyethersulfone (PES). [Form 12] A method for forming components to be used in a semiconductor processing chamber, A process for providing a conductive semiconductor or metal body, The main body is 10.0 × 10 -6 A process having a CTE of less than / K, A step of forming an intermediate layer on at least one surface of the main body, wherein the intermediate layer includes a fluoropolymer, The steps include forming a perfluoroalkoxyalkane (PFA) layer on the intermediate layer to form the aforementioned components, A method that includes [a certain feature]. [Form 13] The method described in Embodiment 12, The method wherein the body is a semiconductor body containing silicon or silicon carbide. [Form 14] The method described in Embodiment 13, The semiconductor body comprises elemental silicon, and the method is as described above. [Form 15] The method described in Embodiment 12, The aforementioned main body is 5.0 × 10 -6 A method having a CTE less than / K. [Form 16] The method described in Embodiment 12, The intermediate layer is resin-based to facilitate bonding of the main body to the at least one surface, in a method. [Form 17] The method described in Embodiment 16, The method comprising the resin being polyethersulfone (PES). [Form 18] The method described in Embodiment 12, The intermediate layer is aqueous or solvent-based, and the step of forming the intermediate layer includes the step of applying the intermediate layer to the at least one surface of the main body by spray deposition. [Form 19] The method described in Embodiment 12, A method wherein the PFA layer is coated onto the intermediate layer by spray deposition for bonding to the intermediate layer. [Form 20] The method described in Embodiment 12, further, The process includes installing the aforementioned components inside a semiconductor processing chamber. The aforementioned components form a ring around an electrostatic chuck in the semiconductor processing chamber, and the electrostatic chuck supports a wafer for processing. [Form 21] A method described in form 20, The semiconductor processing chamber includes a plasma processing chamber. A method wherein the components are exposed to a corrosive treatment in the plasma treatment chamber, and the PFA layer is resistant to damage or corrosion caused by the corrosive treatment. [Form 22] The method described in Embodiment 12, The method wherein the intermediate layer comprises at least one of fluoroethylene propylene and polyethersulfone (PES). [Form 23] An edge ring used in a plasma processing chamber, The elemental silicon edge ring body, A fluorine polymer coating on at least one surface of the elemental silicon edge ring body, The perfluoroalkoxyalkane (PFA) coating on the aforementioned fluoropolymer coating, An edge ring equipped with this feature.

Claims

1. A component in a semiconductor processing chamber exposed to plasma, A conductive semiconductor or metal body, The main body is 10.0 x 10 －６ The main body has a CTE of less than / K, An intermediate layer disposed on at least one surface of the main body, wherein the intermediate layer includes a fluoropolymer, A perfluoroalkoxyalkane (PFA) layer is disposed on the intermediate layer to form the aforementioned components, Equipped with, The surface of the PFA layer opposite to the surface in contact with the intermediate layer is an exposed component.

2. A component according to claim 1, The aforementioned body is a semiconductor body containing silicon or silicon carbide, which is a component.

3. The component according to claim 2, The aforementioned semiconductor body is a component containing elemental silicon.

4. A component according to claim 1, The main body is 5.0 x 10 －６ A component having a CTE of less than / K.

5. A component according to claim 1, The intermediate layer is a component that is polyethersulfone (PES) resin-based to facilitate bonding of the main body to the at least one surface.

6. A component according to claim 1, The intermediate layer is a component that is aqueous or solvent-based, in order to enable coating of the intermediate layer onto the at least one surface of the main body by spray deposition or to allow the intermediate layer to be applied.

7. A component according to claim 1, The PFA layer is a component that is applied to the intermediate layer by spray deposition for bonding to the intermediate layer.

8. A component according to claim 1, The aforementioned components are configured to be installed in a semiconductor processing chamber. The aforementioned components form a ring around an electrostatic chuck within the semiconductor processing chamber, and the electrostatic chuck supports the wafer for processing.

9. A component according to claim 1, The semiconductor processing chamber includes a plasma processing chamber. The component is exposed to a corrosive treatment within the plasma treatment chamber, and the PFA layer is resistant to damage or corrosion caused by the corrosive treatment.

10. A component according to claim 1, The intermediate layer is a component that is fluoroethylene propylene resin-based to facilitate bonding of the main body to the at least one surface.

11. A component according to claim 1, The fluorine polymer is a component that is at least one of fluorinated ethylene propylene (FEP) and polyethersulfone (PES).

12. A method for forming a component for use in a semiconductor processing chamber exposed to plasma, A process for providing a conductive semiconductor or metal body, The main body is 10.0 x 10 －６ A process having a CTE of less than / K, A step of forming an intermediate layer on at least one surface of the main body, wherein the intermediate layer includes a fluoropolymer, The steps include forming a perfluoroalkoxyalkane (PFA) layer on the intermediate layer to form the aforementioned components, Equipped with, The method wherein the surface of the PFA layer opposite to the surface in contact with the intermediate layer is exposed.

13. A method according to claim 12, The method wherein the body is a semiconductor body containing silicon or silicon carbide.

14. The method according to claim 13, The semiconductor body comprises elemental silicon, and the method is as described above.

15. The method according to claim 12, The main body is 5.0 x 10 －６ A method having a CTE of less than / K.

16. The method according to claim 12, The intermediate layer is resin-based to facilitate bonding of the main body to the at least one surface, in a method.

17. The method according to claim 16, The method comprising the resin being polyethersulfone (PES).

18. The method according to claim 12, The intermediate layer is aqueous or solvent-based, and the step of forming the intermediate layer includes the step of applying the intermediate layer to the at least one surface of the main body by spray deposition.

19. The method according to claim 12, A method wherein the PFA layer is coated onto the intermediate layer by spray deposition for bonding to the intermediate layer.

20. The method according to claim 12, further, The process includes installing the aforementioned components inside a semiconductor processing chamber. The aforementioned components form a ring around an electrostatic chuck in the semiconductor processing chamber, and the electrostatic chuck supports a wafer for processing.

21. The method according to claim 20, The semiconductor processing chamber includes a plasma processing chamber. A method wherein the components are exposed to a corrosive treatment in the plasma treatment chamber, and the PFA layer is resistant to damage or corrosion caused by the corrosive treatment.

22. A method according to claim 12, The method wherein the intermediate layer comprises at least one of fluoroethylene propylene and polyethersulfone (PES).

23. An edge ring used in a plasma processing chamber, The elemental silicon edge ring body, A fluorine polymer coating on at least one surface of the elemental silicon edge ring body, The perfluoroalkoxyalkane (PFA) coating on the aforementioned fluoropolymer coating, An edge ring equipped with this feature.

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