Gaming machine

Abstract

To provide a game machine which can execute more improved image performance control.SOLUTION: A game machine is provided with a CPU circuit 51 which produces display list DL information for identifying an image performance, and sound command list VC information for identifying a sound performance, and a data transfer circuit 70 which forwards the DL information and the VC information by a predetermined forward size as one unit to a drawing circuit 74 and a sound processing part SND. The DL information and the VC information are constituted by listing instruction commands integer N times (N≥1) larger than a standard size, and a transfer size is made to be M times (M≥1) larger than the standard size, and the number of the instruction commands is thus any number.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a gaming machine that performs a lottery process caused by a gaming operation and executes an image effect corresponding to the lottery result, and particularly to a gaming machine that can stably execute a powerful image effect.

Background Art

[0002] A ball shooting gaming machine such as a pachinko machine includes a symbol start port provided on a game board, a symbol display unit that displays a series of symbol variation patterns by a plurality of display symbols, a big winning port where an opening / closing plate is opened / closed, and the like. When a detection switch provided at the symbol start port detects the passage of a game ball, it enters a winning state. After the game ball is paid out as a bonus ball, the display symbols on the symbol display unit are varied for a predetermined time. Then, when the symbols stop in a predetermined pattern such as 7·7·7, it enters a jackpot state, and the big winning port is repeatedly opened, generating a gaming state advantageous to the player.

[0003] Whether to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start port, and the above symbol variation operation is based on this lottery result. For example, when the lottery result is a winning state, an effect operation called a reach reaction is executed for about 20 seconds, and then special symbols are aligned. On the other hand, in the case of a losing state, a similar reach reaction may also be executed. In this case, the player will closely watch the transition of the effect operation while strongly hoping for a jackpot state. And when a predetermined symbol is aligned on the stop line at the end of the symbol variation operation, it is guaranteed to the player that it is a jackpot state.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

[0005] In this type of gaming machine, there is a desire to make various effects more complex and abundant, and there is a particularly high demand for image effects. Therefore, the applicant has made various proposals (References 1 to 3), but further sophistication of image effects and improvement of image effect control are desired.

[0006] This invention has been made in view of the above problems, and aims to provide a gaming machine capable of performing improved image presentation control. [Means for solving the problem]

[0007] To achieve the above objective, the gaming machine according to the present invention is a gaming machine equipped with a CPU means for generating first information that identifies an image presentation by a display device and second information that identifies an audio presentation, and a transfer means for transferring the first information to a first circuit and the second information to a second circuit, with a predetermined transfer size as one unit, wherein the first information and / or the second information are composed of a list of instruction commands that are an integer N times (N≧1) of a reference size, and the transfer size is an integer M times (M≧1) of the reference size, so that the number of instruction commands in the first information and / or the second information can be any number, and the CPU means The constituent data of the first information and The configuration data for the second piece of information is configured to be written to a predetermined write port at predetermined write sizes. [Effects of the Invention]

[0008] According to the present invention described above, the degree of freedom in configuring instruction commands for the first information and / or the second information is increased, so that even with advanced image effects, smooth and appropriate image control operations can be performed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view showing the pachinko machine of this embodiment. [Figure 2] Figure 1 is a front view showing the game area of ​​the gaming machine. [Figure 3] This is a block diagram showing the overall circuit configuration of the gaming machine in Figure 1. [Figure 4] This diagram illustrates the internal configuration of the performance interface board, the performance control board, and the liquid crystal interface board. [Figure 5] This is a circuit block diagram illustrating a composite chip, including its related circuit elements. [Figure 6] This is a diagram illustrating the index space and the virtual drawing space. [Figure 7] This is a diagram illustrating the display circuit. [Figure 8] This is a diagram illustrating the internal configuration of a data transfer circuit. [Figure 9] This diagram illustrates the transfer operation of display lists and voice command lists. [Figure 10] This is a diagram illustrating filtering based on a display list. [Figure 11] This is a diagram illustrating the playback procedure for IPB streamed video. [Figure 12] This diagram illustrates the internal configuration and control procedure of the audio processing unit. [Figure 13] This is a diagram illustrating the drawing pipeline process of a drawing circuit. [Figure 14] This is a process diagram illustrating various drawing modes that utilize all or part of the drawing pipeline process. [Figure 15] This flowchart explains the control operation of the performance control CPU, excluding preload operations. [Figure 16] This is a flowchart that explains a part of Figure 15. [Figure 17] This is a flowchart explaining the control operations of the performance control CPU, including the preload operation. [Modes for carrying out the invention]

[0010] Hereinafter, the present invention will be described in detail based on embodiments. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached via a hinge 2 fixed to the outer frame 1 so as to be openable and closable. A game board 5 is detachably attached to this inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side thereof so as to be openable and closable, respectively. In this specification, the glass door 6 and the front panel 7 are collectively referred to as a front door member. And the inner frame 3 in a state where the front door member (glass door 6 or front panel 7) is pivotally attached may be referred to as a game frame.

[0011] On the outer periphery of the glass door 6, decorative lamps such as LED lamps are arranged in a substantially C shape. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged at the upper part output the sound of the left and right channels R and L, respectively, and the lower speaker is configured to output bass.

[0012] An upper tray 8 for storing game balls for launching is attached to the front panel 7, and a lower tray 9 for storing game balls that have overflowed or been taken out from the upper tray 8 and a launch handle 10 are provided at the lower part of the inner frame 3. The launch handle 10 is interlocked with a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0013] <00 provin="000099">A chance button 11 is provided on the outer peripheral surface of the upper tray 8. This chance button 11 is provided at a position that can be operated with the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the launch handle 10. This chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is lit and it becomes operable. The button chance state is a game state provided as needed.

[0014] Furthermore, a rotary switch-type volume switch VLSW is located below the chance button 11, allowing the player to adjust the speaker volume in eight steps, from silent (=0) to maximum (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial volume is maintained unless the player operates the volume switch VLSW. In addition, an abnormal alert sound, which notifies the player of an abnormal situation, is emitted at the maximum volume regardless of the initial volume set by the attendant or the player's setting.

[0015] On the right side of the upper tray 8, there is an operation panel 12 for dispensing balls to a card-type ball dispenser, which includes a frequency display that shows the remaining balance on the card as a three-digit number, a ball dispensing switch that instructs the dispenser to dispense a predetermined amount of game balls, and a return switch that instructs the card to be returned when the game ends.

[0016] As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided approximately in the center. Below the central opening HO, a movable performance element (not shown) is concealed, and when a movable pre-announcement performance is performed, the movable performance element rises and becomes exposed, thereby realizing a pre-announcement performance with a predetermined reliability. Here, a pre-announcement performance is a performance that uncertainly notifies the player that a jackpot state advantageous to them is about to be brought about, and the reliability of the pre-announcement performance means the probability that the jackpot state will be brought about.

[0017] A display device DS, consisting of a large (for example, 1280 pixels wide x 1024 pixels high) liquid crystal color display, is positioned in the central opening HO. The display device DS consists of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that displays specific symbols related to the jackpot state in a variable manner, as well as displaying background images and various characters in an animated manner. This display device DS has special symbol display units Da to Dc in the center and a regular symbol display unit 19 in the upper right. In the special symbol display units Da to Dc, reach effects that suggest the arrival of a jackpot state may be executed, and appropriate pre-announcement effects are executed in and around the special symbol display units Da to Dc.

[0018] Incidentally, the game area in which the game balls fall and move is equipped with a first symbol start opening 15a, a second symbol start opening 15b, a first major prize opening 16a, a second major prize opening 16b, a regular prize opening 17, and a gate 18. Each of these prize openings 15 to 18 has a detection switch inside that can detect the passage of the game balls.

[0019] Above the first symbol start opening 15a, there is a performance stage 14 configured to allow game balls that enter from the entry opening IN to move in a seesaw-like or roulette-like manner before entering the first symbol start opening 15. When a game ball enters the first symbol start opening 15, the special symbol display sections Da to Dc begin to change.

[0020] The second symbol start opening 15b is configured to be opened and closed by an electrically operated tulip with a pair of opening and closing claws on the left and right. When the stopping symbol after the change in the normal symbol display unit 19 displays a winning symbol, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0021] The regular symbol display unit 19 displays regular symbols. When a game ball that has passed through the gate 18 is detected, the regular symbols change for a predetermined time, and then stop displaying a stopping symbol determined by a random value for the lottery extracted at the time the game ball passes through the gate 18.

[0022] The first large prize opening 16a is configured with a sliding plate that moves back and forth in the front-rear direction, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is pivotally supported and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a corresponds to the first symbol start opening 15a, and the second large prize opening 16b corresponds to the first symbol start opening 15b.

[0023] In other words, when a game ball enters the first symbol starting opening 15a, the special symbol display section Da to Dc starts moving, and then when the predetermined jackpot symbols are aligned in the special symbol display section Da to Dc, the special game for the first jackpot begins, and the sliding disc of the first jackpot opening 16a opens forward, making it easier for game balls to enter.

[0024] On the other hand, as a result of the fluctuation operation initiated by a game ball entering the second symbol starting opening 15b, when the predetermined jackpot symbols align in the special symbol display section Da~Dc, a special game, which is the second jackpot, begins, and the opening and closing plate of the second jackpot entry opening 16b is opened, making it easier for game balls to enter. The game value of the special game (jackpot state) varies depending on the aligning jackpot symbols, but which game value is assigned is predetermined based on the lottery result corresponding to the timing of the game ball's entry.

[0025] In a typical jackpot state, the opening and closing plate of the large prize winning slot 16 opens, and then closes after a predetermined time has elapsed or a predetermined number of game balls (for example, 10) have entered. This operation can continue for up to, for example, 15 times, and is controlled to be advantageous to the player. Furthermore, if the stopping symbols after the special symbol display section Da~Dc changes are specific symbols among the special symbols, the game after the special game ends will be in a high-probability state (probability change state), which is a special bonus.

[0026] Figure 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the operations described above. Figure 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT located on the payout control board 25. As shown in Figure 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) along with AC24V, a main control board 21 that is primarily responsible for game control operations, an effects interface board 22 equipped with a digital amplifier 29 for sound effects, etc., an effects control board 23 that uniformly executes lamp effects, sound effects, and image effects based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the effects control board 23 and the display device DS, a payout control board 25 that controls the payout motor M to dispense game balls based on control commands CMD' received from the main control board 21, and a launch control board 26 that launches game balls in response to the player's operation.

[0027] Figure 4 is a slightly more detailed illustration of a part of Figure 3(a), and schematically shows the internal configuration of the performance interface board 22, the performance control board 23, and the liquid crystal interface board 24. As shown in Figures 4 and 3(a), the performance interface board 22, the performance control board 23, and the liquid crystal interface board 24 are directly connected by male and female connectors without the need for wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made more complex and sophisticated, the overall space required for the board can be minimized, and noise immunity can be improved by minimizing the connection lines.

[0028] As shown in Figure 3(a), the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, both control commands CMD and CMD' are 16 bits long, but they are transmitted in parallel in two separate 8-bit segments.

[0029] The main control board 21 and the payout control board 25 are equipped with computer circuits, including a one-chip microcontroller. The performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as an integrated performance circuit 52 and an internal CPU circuit 51. In this specification, these control boards 21, 25, and 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are functionally referred to collectively as the main control unit 21, the performance control unit 23, and the payout control unit 25. The performance control unit 23 and the payout control unit 25 are sub-control units with respect to the main control unit 21.

[0030] Furthermore, this pachinko machine GM is broadly divided into the frame-side member GM1, enclosed by the dashed line in Figure 3(a), and the board-side member GM2, which is fixed to the back of the game board 5. The frame-side member GM1 includes the inner frame 3 to which the glass door 6 and front panel 7 are pivotally attached, and the outer wooden frame 1 outside of it, and is permanently installed in the gaming hall for a long period of time regardless of changes in the machine model. On the other hand, the board-side member GM2 is replaced in response to changes in the machine model, and the new board-side member GM2 is attached to the frame-side member GM1 in place of the original board-side member. Note that everything except the frame-side member GM1 is the board-side member GM2.

[0031] As shown in the dashed box in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to the appropriate locations on the inner frame 3. On the other hand, the main control board 21 and the performance control board 23 are fixed to the back of the game board 5 together with the display device DS and other circuit boards. The frame-side member GM1 and the game board-side member GM2 are electrically connected by centralized connection connectors C1 to C3 which are located in one place.

[0032] The power supply board 20 generates three types of DC voltages (35V, 12V, and 5V) based on the AC voltage (AC24V) distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the central connection connector C2. The three types of DC voltages (35V, 12V, and 5V), along with the AC voltage (AC24V), are also distributed to the payout control board 25. The DC voltages (35V, 12V, and 5V) distributed to the payout control board 25, along with the backup power supply BAK, are then distributed to the main control board 21 via the central connection connector C1.

[0033] 35V DC is used as the power supply for the ball feeding solenoid and launch solenoid in relation to the launching operation of the game balls, and as the power supply for the electromagnetic solenoid that drives the opening and closing of the electric tulip (variable prize device) and the large prize opening 16. 12V DC is used as the power supply for the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier. Meanwhile, 5V DC is used as the power supply voltage for the one-chip microcontroller on the payout control board 25 and the main control board 21, and as the power supply voltage for the logic elements mounted on each control board. Furthermore, after the 5V DC voltage is reduced in level by the DC / DC converters on the performance interface board 22 and the performance control board 23, the reduced voltages are used as the power supply voltage for various computer circuits (such as the composite chip 50).

[0034] The backup power supply BAK is a DC 5V DC power supply used to retain data in the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25 after the power supply is cut off, and is implemented, for example, by an electric double-layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double-layer capacitor placed on the backup power supply board 33 is configured to be charged during game operation by the DC voltage of 5V received from the payout control board 25.

[0035] On the other hand, after the power is cut off, the backup power supply BAK retains the data from the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the game operation that was in place before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with electric double-layer capacitors that can retain the contents of the built-in RAM of each one-chip microcontroller for at least several days.

[0036] In this embodiment, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC voltage AC24V, is generated not by the power supply board 20, but by the power supply monitor unit MNT of the payout control board 25. As shown in Figure 3(b), the power supply monitor unit MNT is configured to include a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light when energized, a phototransistor TR that uses the DC voltage 5V received from the power supply board 20 as its power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs a high-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

[0037] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power abnormality signal ABN to reach a normal level (H). However, if the AC power then drops abnormally for any reason (normally a power outage), the photocoupler PH changes to the OFF state, causing the power abnormality signal ABN to change to an abnormal level (L). This power abnormality signal ABN is transmitted to the one-chip microcontroller on the payout control board 25, and is also transmitted to the one-chip microcontroller on the main control board 21 via the central connection connector C1. Therefore, each one-chip microcontroller that receives an abnormal level power abnormality signal ABN will perform a backup process to store the necessary information in its built-in RAM. As explained earlier, the information in the built-in RAM is maintained by the backup power supply BAK, so the game operation before the power outage can be resumed after power is turned on.

[0038] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as an integrated performance circuit 52 and an internal CPU circuit 51, and the liquid crystal interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) for storing performance data, and a power supply control circuit SPY.

[0039] In this embodiment, the integrated performance circuit 52 built into the composite chip 50 includes a video display processor (VDP), an audio processor (SND), a motor control unit (MT_CTL), and a lamp control unit (L_CTL). Based on control from the built-in CPU circuit 51, the integrated performance circuit 52 operates intermittently with an operating cycle δ (= 1 / 30 second) to execute image effects using the display device DS, sound effects driving speakers via the digital amplifier 29, motor effects moving props by rotating the performance motors M1 to Mn, and lamp effects flashing LED lamps, etc. In the following description, the built-in CPU circuit 51 may be abbreviated as CPU circuit 51.

[0040] The reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20 when the power is turned on, thereby resetting the internal circuits of the composite chip 50 and other electronic components. As explained earlier, the internal circuits of the composite chip 50 include the video processing unit VDP (Video Display Processor) and the audio processing unit SND (Audio Processor), but the power reset signal is none other than the system reset signal SYS of the composite chip 50, which synchronously resets the CPU circuit 51 and the integrated production circuit 52.

[0041] In this embodiment, during the L assertion period of the system reset signal SYS, all internal circuits are uniformly initialized, and the performance control register RGij of the composite chip 50 is set to a default value. Subsequently, when the system reset signal SYS transitions to the H level, the boot program is started, and the necessary initial setup operations are performed on the performance control register RGij. On the other hand, if the DC voltage of 5V drops (usually when the power is cut off), the system reset signal SYS drops to the L level, and the CPU circuit 51 and the integrated performance circuit 52 of the performance control board 23 enter a stopped state.

[0042] As will be described later, in this embodiment, the system reset signal SYS does not change even when the WDT (Watch Dog Timer) circuit 58 is activated, and even in the abnormal situation where the WDT 58 is activated, not all internal circuits are uniformly initialized. In other words, in this embodiment, a predetermined internal circuit that is arbitrarily selected is configured to be initialized.

[0043] Next, the clock circuit 38 and the performance data memory 39 mounted on the LCD interface board 24 are powered by a secondary battery (not shown), which is appropriately charged by the power supply voltage from the power supply board 20 during gameplay. Therefore, even after the power is cut off, the clock circuit 38 continues to keep time, and the game performance information stored in the performance data memory 39 is permanently retained (non-volatile).

[0044] The clock circuit 38 is configured to output an interrupt signal to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the day, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, the alarm interrupt IRQ_RTC is used to update the daily game performance information at the end of each business day.

[0045] As shown in Figure 3(a), the payout control board 25 and the main control unit 21 are equipped with reset circuits RST1 and RST2, respectively, and are configured to generate a power reset signal when the power is turned on, thereby resetting each computer circuit. Thus, in this embodiment, reset circuits RST1 to RST3 are arranged on the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, so that, for example, the system reset signal generated by the power supply board 20 is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal, the risk of the computer circuit being abnormally reset due to noise superimposed on the wiring cable is eliminated.

[0046] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21 or 25, each CPU is forcibly reset. In addition, the main control unit 21 is equipped with an initialization switch SW that can be operated by an operator, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW was turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcontrollers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcontrollers of each control unit 21 or 25.

[0047] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply depletion signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0048] Furthermore, the main control unit 21 receives switch signals from detection switches built into each of the prize entry slots 16-18 on the game board, while also driving solenoids such as the electric tulips. The solenoids and detection switches are configured to operate with the power supply voltage VB (12V) distributed from the main control unit 21. In addition, the switch signals indicating the entry status into the symbol entry slot 15, etc., are converted into TTL level or CMOS level switch signals by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0049] As explained earlier, the performance interface board 22 receives DC voltages (5V, 12V, 35V) at various levels from the power supply board 20 via the central connection connector C2 (see Figures 3(a) and 4). The DC voltage of 12V is used as the power supply voltage for the digital amplifier 29 and as the driving voltage for LED lamps and the like. The DC voltage of 35V is distributed to the appropriate locations on the game frame and used as the driving voltage for solenoids that move movable parts back and forth.

[0050] Meanwhile, the 5V DC voltage is supplied as the power supply voltage to the circuit elements at various locations on the performance interface board 22, and is also supplied to the DC / DC converter DC to generate 3.3V (see Figure 4). The generated 3.3V DC voltage then becomes the base voltage for the power reset signal (system reset signal) SYS generated by the reset circuit RST3. The 5V DC voltage distributed to the performance interface board 22, along with the 3.3V generated by the DC / DC converter DC, is then distributed to the performance control board 23. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as the power supply voltage to the composite chip 50 and the external ROM 55.

[0051] As shown in Figure 4, the performance control board 23 is equipped with two DC / DC converters, DC1 and DC2, which generate 1.5V and 1.05V respectively based on the 5V DC voltage supplied to them. Here, the 1.05V DC voltage is the power supply voltage for the chip core of the composite chip 50, and the 1.5V DC voltage is the power supply voltage for I / O (input / output) with the VRAM 53 and expansion RAM 54. Therefore, the 1.5V DC voltage is also supplied to the VRAM 53 and expansion RAM 54 as a power supply voltage.

[0052] As shown in Figure 3(a), the performance interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and forwards them to the performance control board 23. More specifically, as shown in Figure 4, the control command CMD and the strobe signal STB are forwarded via the input buffer 40 to the composite chip 50 (CPU circuit 51) of the performance control board 23. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the performance control CPU 57 obtains the control command CMD based on the interrupt processing program (interrupt handler) that is activated upon receiving the received interrupt signal IRQ_CMD.

[0053] As shown in Figure 4, the input buffer 44 of the performance interface board 22 receives switch signals from the frame relay board 36 for the chance button 11 and the volume switch VLSW, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits a 3-bit length of encoder output indicating the contact position (0-7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11 to the CPU circuit 51.

[0054] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. In Figure 4, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives the output SN0~SNn of the origin sensor, which determines the current position of the movable performance object (the rotational position of the performance motors M1~Mn), and transmits this to the motor control unit MT_CTL of the performance control board 23.

[0055] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 forwards the serial signals received from the lamp control unit L_CTL and motor control unit MT_CTL of the performance control board 23 to each driver IC. Specifically, the serial signals are the lamp (motor) drive signal SDATA and the clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock-synchronous manner, executing lamp effects using numerous LED lamps and illuminated lamps, as well as mechanical effects using performance motors M1 to Mn.

[0056] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2. The driver IC on the lamp drive board 37 receives the lamp drive signal SDATA0 for CH0, output by the lamp control unit L_CTL, via the frame relay board 36, synchronized with the clock signal CK0. The series of lamp drive signals SDATA0, transmitted as serial signals, are output from the driver IC to the lamp group CH0 when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO62) changes to an active level, thereby simultaneously updating the lighting state of the lamp group CH0.

[0057] The same applies to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 output by the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually PIO62) changes to the active level, the lighting status of the lamp group CH1 is updated simultaneously.

[0058] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted clock-synchronously from the motor control unit MT_CTL to drive the lamp group CH2, and also receives a motor drive signal transmitted clock-synchronously to drive the performance motor group M1 to Mn, which consists of multiple stepping motors. Since the lamp drive signal and the motor drive signal are serial signals of the same type, a series of composite serial signals SDATA2 are output from the motor control unit MT_CTL in synchronization with the clock signal CK2. The driver IC receives this signal and updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0059] Thus, in this embodiment, for convenience, the motor control unit MT_CTL is responsible for both the motor and lamp effects on the motor lamp drive board 31, and therefore the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Alternatively, the lamp drive signals SDATA0 and SDATA1 for the lamp drive boards 37 and 30 may also be output from the motor control unit MT_CTL.

[0060] As shown in Figure 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 also extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51. When the clock circuit 38 is selected by the chip select signal, the CPU circuit 51 is configured to be able to arbitrarily access the internal register (which has a 4-bit address value).

[0061] Furthermore, the performance data memory 39 is a high-speed accessible memory element, SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus and the lower 16 bits of the data bus of the CPU circuit 51. When the chip is selected, game performance information and other data stored in the SRAM (performance data memory) 39 are accessed by the CPU circuit 51 as appropriate via read / write.

[0062] Furthermore, the liquid crystal interface board 24 is equipped with a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL. Specifically, the power supply control circuit SPY controls the start timing of supplying power voltages of 12V and 5V to the display device DS and the backlight board BL using the control signal STBY, and controls the brightness and start timing of the backlight light using the control signal PWM.

[0063] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 that incorporates a CPU circuit 51 and an integrated performance circuit 52, a VRAM 53 that is accessed at high speed by R / W from the CPU circuit 51 and the integrated performance circuit 52, an expanded RAM 54 that can store a large amount of data, and an external ROM 55 that stores CG data and other data nonvolatilously.

[0064] VRAM 53 is capable of high-speed access with a theoretical transfer speed of approximately 102 GB / second and has a storage capacity of approximately 48 MB. VRAM 53 is primarily used for (1) storing reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see Figure 5(a)). It can also be used for (2) storing copies of data from the external ROM 55, and (3) as a work area for the CPU circuit 51.

[0065] The extended RAM 54 can operate at a theoretical transfer speed of approximately 17.0 GB / second and has a storage capacity of approximately 1 GB, allowing it to be used in the same way as the VRAM 53. Specifically, the extended RAM 54 can be used to (1) store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) store copies of data from the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0066] The external ROM 55 in this embodiment is a non-volatile storage device that stores a boot program that starts when the power is turned on, control data including a control program and lamp drive data for the CPU circuit 51 that realizes the control of the effects, CG compressed data for image effects, and audio compressed data for sound effects. The storage capacity of the external ROM 55 is up to about 256 GB, but high-speed access is not possible, so in this embodiment, when the power is turned on, a portion of the data in the external ROM 55 is transferred to the expansion RAM 54. Specifically, the control program and control data that make the CPU circuit 51 function are transferred and copied from the external ROM 55 to the expansion RAM 54 by the boot program stored in the external ROM 55 when the power is turned on.

[0067] Figure 5(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of this embodiment incorporates a CPU circuit 51 that issues a display list DL and an audio command list VC, and an integrated performance circuit 52 that executes image performances based on the display list DL, audio performances based on the audio command list VC, as well as lamp performances and motor performances. The CPU circuit 51 and the integrated performance circuit 52 are connected through a CPU bus section 56 that relays data between them.

[0068] First, let's describe the CPU bus section 56, which is located between the CPU circuit 51 and the integrated production circuit 52. As shown in Figure 5(a), the CPU bus section 56 is connected to the VRAM 53, the expanded RAM 54, and the external ROM 55 via the VRAMIF section 53a, the expanded RAMIF section 54a, and the CG bus IF section 55a. Therefore, in this embodiment, the VRAM 53, the expanded RAM 54, and the external ROM 55 can be accessed not only from the integrated production circuit 52 but also from the CPU circuit 51.

[0069] The VRAMIF unit 53a, the extended RAMIF unit 54a, and the CG bus IF unit 55a are connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via an arbitration circuit ICM (Inter Connect Module) (not shown). The arbitration circuit ICM is located between each functional block of the integrated production circuit 52 and the VRAMIF unit 53a, the extended RAMIF unit 54a, and the CG bus I / F unit 55a, arbitrating the data requests issued by each functional block as appropriate to establish the necessary connection relationships.

[0070] In any case, the CPU circuit 51 in this embodiment can access the VRAM 53, the expanded RAM 54, and the external ROM 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external ROM 55 to the expanded RAM 54 when the power is turned on, it does not access the external ROM 55 again. That is, after the copy operation, the CPU circuit 51 executes control operations based on the control program and control data copied to the expanded RAM 54.

[0071] The CPU circuit 51 can access various performance control registers RGij via read / write to control the internal operation of the integrated performance circuit 52. The data transfer circuit 70 can also transmit and receive data between the CPU circuit 51 and the integrated performance circuit 52 via the CPU bus 56. Data transmission from the CPU circuit 51 to the integrated performance circuit 52 includes issuing display list DLs and voice command list VCs.

[0072] As shown on the right side of Figure 5(a), the integrated production circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphic Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND. The production control register RGij is used by the CPU circuit 51 to appropriately control the internal circuits of this integrated production circuit 52.

[0073] Therefore, the performance control register RGij is broadly divided into (1) data transfer register, (2) display register, (3) preload register, (4) GDEC register, (5) drawing register, (6) image filter register, (7) index table register, (8) MT_CTL register, (9) L_CTL register, and (10) sound register, corresponding to each of the circuits (1) to (10) mentioned above, and a system control register is provided for overall system control (see Figure 5(b)). Note that the system control register and each of the individual circuit registers (1) to (10) are actually composed of multiple subdivided register groups.

[0074] Based on the above, the CPU circuit 51 will now be described. The CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcontroller, and as shown on the left side of Figure 5(a), it consists of a performance control CPU 57 that comprehensively controls image / sound / lamp / motor effects based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU if the program goes into a runaway state, an internal RAM 59 with a memory capacity of about 2 MB used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that enables data transfer without going through the performance control CPU 57, a serial input / output port (SIO) 61 with multiple input ports Si and output port So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output port Po, and an operation control register REG in which setting values ​​are set to control the internal configuration of the CPU circuit 51.

[0075] For convenience, this specification uses the term "input / output port," but in the performance control unit 23, the input / output port includes an input port and an output port that operate independently. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0076] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) via the input / output circuit 64p. The performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port 62 via the input / output circuit 64p.

[0077] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby activating the receive interrupt process. Therefore, based on the receive interrupt process, the performance control CPU 57, having grasped the control command CMD, will then uniformly control the corresponding sound effects, lamp effects, motor effects, and image effects through processes such as performance lottery. The parallel input / output port 62 outputs the operation control signals ENABLE0 to ENABLE1 for the lamp effects via the input / output circuit 64p.

[0078] Furthermore, the serial input / output port (SIO) 61 is configured to send and receive serial signals via the input / output circuit 63s. Therefore, as shown by the dashed line in Figure 5(a), it is also possible to output a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA via the input / output circuit 63s which is internally connected to the serial input / output port SIO 61. However, in this embodiment, the lamp / motor effects are realized using the lamp control unit L_CTL and motor control unit MT_CTL of the integrated effect circuit 52 without using the serial input / output port 61.

[0079] Incidentally, the built-in RAM 59 of the CPU circuit 51 is equipped with a DL buffer BUF that sequentially updates and stores a display list DL, which is a list of instruction commands that identify a frame of the display device DS. Furthermore, this DL buffer BUF is configured by partitioning the area, and a voice command list VC that identifies the content of the sound effects is also sequentially updated and stored there.

[0080] In this embodiment, the instruction commands of the display list DL that define one frame of the display screen include: (1) index table control system commands related to the index table IDXTBL that manages the index space; (2) texture loading system commands such as the LOADTX command for reading image materials (textures) from the external ROM 55 and decoding (decompressing / unpacking); (3) filter execution system commands that specify the filtering process for the decompressed image data; (4) drawing system commands such as the SPRITE command for placing the decoded (unpacked) image materials at a predetermined position in the virtual drawing space; (5) pipeline system commands related to the drawing pipeline operation; and (6) overall control system commands that define the overall operation of the integrated production circuit 52. All of these are composed of integer multiples of 32 bits (>0). The display list DL is configured to list an appropriate number of instruction commands and then terminate with a predetermined termination command EODL (32-bit length).

[0081] Furthermore, the audio command list VC, which defines the operation of the audio processing unit SND that executes the audio effects, lists an appropriate number of audio commands and then concludes with a predetermined termination command EOSC (32-bit length). Here, the audio commands are broadly classified into track-related commands that define the operation of the pre-processing unit FT shown in Figure 12(a), master effect-related commands that define the operation of the post-processing unit BK shown in Figure 12(a), and other system-related commands, but all audio commands are composed of integer multiples of 32 bits (>0).

[0082] As will be described later, the drawing pipeline operation of this embodiment is performed using the vertex buffer VB built into the drawing circuit 74, the frame buffer FB and depth / stencil buffer reserved as index space, and consists of an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The (5) pipeline command described above functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0083] Incidentally, while "texture" generally refers to the feel or texture of an object's surface, in this specification, the term "texture" is used as a general term for image data before and after decoding. For example, sprite image data that makes up a still image, frame image data that makes up a single frame of a video, and pasted image data that is applied to drawing primitives such as triangular polygons and quadrilateral polygons are all referred to as textures.

[0084] Then, (2) the LOADTX command of the texture loading system reads the texture from the external ROM 55 and decodes it. (5) The SETTXINDEX command, which is a texture sampler process TX command included in the pipeline system commands, sets the source image data to be a texture, and (4) the SPRITE command of the drawing system commands virtually draws it in the virtual drawing space shown in Figure 6(c). The contents drawn in the virtual drawing space are output to the display device DS via the frame buffer FB, which will be described later.

[0085] To explain in more detail, the SETTXINDEX command sets the index space (space type and index number) to be used as a texture using embedded parameters. Here, the space type can be any of the following: an arbitrary area of ​​VRAM53, a page area of ​​VRAM53, an AAC area of ​​VRAM53, an arbitrary area of ​​extended RAM54, or a page area of ​​extended RAM54. However, in this embodiment, the shared area of ​​VRAM53 is used as the ACC area, so there is no page area in VRAM53 (see Figure 6(a)).

[0086] Furthermore, when the LOADTX command is executed after setting the index space with the SETTXINDEX command, the decoded result is stored in the set index space. The LOADTX command specifies the horizontal and vertical pixel sizes of the decoded texture, as well as the type of memory where the underlying data to be decoded is stored and the address of the underlying data. By specifying the horizontal / vertical pixel sizes with the LOADTX command, the internal circuitry of the video processing unit VDP can easily manage the correspondence between the horizontal and vertical positions of each texture pixel (RGBA color information) and the data positions in the index space.

[0087] Note that while there is usually only one type of pixel size information and basic data address information, when decoding IPB streams, as described later, a single LOADTX command may specify two types of information for the main frame and subframe. The memory type is usually external ROM 55, but extended RAM 54 or VRAM 53 can also be specified. For example, in Figure 11, the reference buffer accessed by the LOADTX command is an index space allocated in an arbitrary area of ​​VRAM 53 or extended RAM 54.

[0088] The SPRITE command is used to apply a rectangular texture to a rectangular area of ​​window coordinates. In this example, a single SPRITE command can access up to four textures, and the embedded parameters of the SPRITE command specify the top-left and bottom-right coordinates of the texture (only if necessary), and the top-left and bottom-right coordinates of the window where the texture will be applied. Note that if the entire texture is used, specifying the top-left and bottom-right coordinates of the texture is unnecessary; only the window coordinates of the application destination are required.

[0089] Furthermore, the index space managed by the index table control system command (1) mentioned above refers to a one-dimensional or two-dimensional memory work area (logical address space) used by the integrated performance circuit 52 during drawing operations, etc. This index space is identified as a one-dimensional or two-dimensional logical address space by the index number specified in the instruction command of the display list DL.

[0090] In other words, in this embodiment, an index space is allocated in an appropriate location within the memory accessible as a memory work area (VRAM 53 and extended RAM 54), and this space is identified by an index number. Furthermore, VRAM 53 and extended RAM 54 are divided into virtual work areas (AAC area, page area, and arbitrary area), and an index space is allocated for each (see Figures 6(a) and 6(b)). As a result, the index number is a unique value for each virtual work area, simplifying texture loading commands, filter execution commands, drawing commands, pipeline commands, etc.

[0091] Furthermore, it enables unique operation for each virtual work area (AAC area, page area, and arbitrary area). For example, in the AAC area, the index space is automatically allocated and released as the area for expanding decoded data. Therefore, the index number is not required in the AAC area.

[0092] In terms of specific control operations, virtual work areas (AAC area, page area, arbitrary area) are defined during the initial processing after power-on, and the necessary index space is allocated to the required virtual work area at the required timing thereafter. The allocated index space is then managed by the index table IDXTBL, linked to the index number, thereby enabling subsequent operations based on the index number.

[0093] The following explains the relationship between the virtual work area and the actual work area, which consists of VRAM 53 and extended RAM 54. First, VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other arbitrary areas. Specifically, in the initial processing after power-on, the shared area of ​​VRAM 53 is secured by setting an appropriate starting address and area data size to the corresponding performance control register RGij. Then, the area of ​​VRAM 53 other than the shared area secured automatically becomes an arbitrary area of ​​VRAM 53 (Figure 6(a)).

[0094] The shared area allocated in VRAM53 can be used as an ACC area, which does not require index number management, or as a page area, which requires index space management using index numbers. Therefore, when using the shared area, by specifying that the index space should be allocated in the AAC area with the SETTXINDEX command, and then specifying the pixel size and storage address of the texture (image material) with the LOADTX command, the expanded data of the loaded texture can be automatically expanded into the index space allocated in the ACC area.

[0095] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, the decoded data for still images and I-stream videos (S-stream videos consisting only of I-pictures, as described later) is expanded into the AAC area of ​​VRAM 53. In other words, in this embodiment, the shared area of ​​VRAM 53 is used exclusively as the AAC area.

[0096] Next, in the initial processing after power-on, the page area of ​​the extended RAM 54 is reserved by setting the starting address and area data size on the extended RAM 54 using the corresponding performance control register RGij, and the remaining area becomes an arbitrary area of ​​the extended RAM 54 (Figure 6(b)). Here, an arbitrary area means an area in the extended RAM 54 and VRAM 53 that is allowed to be used arbitrarily, and not only can an index space be reserved, but other uses are also possible. In this embodiment, a preload area for pre-transferring (preloading) CG data acquired from the external ROM 55 is reserved in the arbitrary area of ​​the extended RAM 54 (see Figure 6(b)), and a preload buffer that stores the rewritten list DL' obtained by the preloader 72 rewriting the display list DL is reserved in the arbitrary area of ​​VRAM 53 (see Figure 6(a)).

[0097] Furthermore, in this embodiment, the control program and control data stored in the external ROM 55 are transferred and copied to an arbitrary area of ​​the extended RAM 54 when the power is turned on (see Figure 6(b)). Of course, instead of the extended RAM 54, all or part of the control program and control data may be transferred and copied to the VRAM 53. Moreover, not limited to the control program and control data, a configuration may be adopted in which all or part of the CG compressed data and audio compressed data are also transferred and copied to RAM 53 and 54.

[0098] In any case, the index space can be appropriately allocated in the (1) ACC area, (2) VRAM page area, (3) VRAM arbitrary area, (4) extended RAM page area, and (5) extended RAM arbitrary area with respect to the extended RAM 54 and VRAM 53. However, in this embodiment, the shared area of ​​VRAM 53 is used exclusively as the AAC area. However, the area allocated as a shared area in VRAM 53 can be used as both a page area and an AAC area, so the explanation below will continue with this in mind.

[0099] When allocating an index space in the page area of ​​VRAM 53, it is necessary to set the index number and space size in the predetermined performance control register RGij for VRAM. Similarly, the index space in the page area of ​​extended RAM 54 is allocated by setting the index number and space size in the predetermined performance control register RGij for extended RAM. In this embodiment, the page area of ​​extended RAM 54 is used for expanding video frames. In the page area, the starting address of the index space is determined appropriately based on internal processing, which eliminates the need to manage the starting address. In other words, in the page area, there is no need to worry about overlap with existing index spaces when allocating an index space.

[0100] On the other hand, when allocating a two-dimensional index space in an arbitrary area of ​​VRAM 53 or an arbitrary area of ​​extended RAM 54, it is necessary to set the index number, the starting address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. Note that in the case of a one-dimensional index space, the horizontal and vertical sizes are not necessary, and only the space size needs to be set.

[0101] Thus, when allocating an index space in an arbitrary region, the starting address and size can be precisely set, which has the advantage of allowing for efficient use of memory. Therefore, in this embodiment, the image data for one frame of the display device DS is completed and the frame buffer FB is allocated as a two-dimensional index space in an arbitrary region of VRAM 53 (see Figure 6(a)). Of course, the frame buffer FB may also be allocated in an arbitrary region of the extended RAM 54.

[0102] The frame buffer FB allocated in an arbitrary area of ​​VRAM53 corresponds to the drawing area of ​​the virtual drawing space that drawing commands such as the SPRITE command target. Figure 6(c) illustrates the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be arbitrarily set within the virtual drawing space, and the frame buffer FB that stores the image data to be output to the display device DS.

[0103] The frame buffer FB receives image data for one display screen by the drawing circuit 74, while the display circuit 71 reads out image data for one display screen. This frame buffer FB has a double buffer structure composed of a pair of index spaces, consisting of a first buffer with index number N1 and a second buffer with index number N2.

[0104] For the display circuit 71, the first buffer and the second buffer are image data reading areas, and by toggling the index numbers N1 / N2 based on the information embedded in a predetermined display register RGij, the image data from the first buffer and the second buffer is read sequentially at each operation cycle δ.

[0105] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are areas for writing image data, and based on instruction commands on the display list DL, the index numbers N1 / N2 are toggled at each operation cycle δ, thereby alternately writing image data to the first buffer and the second buffer.

[0106] The writing operation of the drawing circuit 74 and the reading operation of the display circuit 71 correspond to each other. Image data written to the first buffer in one operation cycle is read out by the display circuit 71 in the next operation cycle. In the operation cycle in which the image data from the first buffer is read out, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, with the first and second buffers being used alternately as either a "writing area" or a "reading area".

[0107] In this embodiment, as a general workspace other than the frame buffer FB and the space for decompressing compressed data, an index space allocated in an arbitrary area of ​​VRAM 53 or extended RAM 54 is used. These various index spaces can be allocated when needed and released when not needed. When an index space is allocated or released, the contents of the index table IDXTBL, which stores the index space and index number in association, are updated, enabling consistent operation thereafter.

[0108] Having explained the index space and the CPU circuit 51, next we will explain the integrated production circuit 52.

[0109] The integrated production circuit 52 includes: (1) various production control registers RGij, in which setting values ​​defining internal operations are set by the production control CPU 57; (2) a data transfer circuit 70 that performs data transmission and reception between internal and external chip circuits; (3) an index table IDXTBL that manages the index space, which is a work area reserved in VRAM 53 and extended RAM 54; (4) a preloader 72 that can perform a preload operation that reads the external ROM 55 prior to drawing operations; (5) a GDEC circuit (Graphic Decoder) 73 that decodes compressed data for image production read from the external ROM 55; (6) a drawing circuit 74 that appropriately combines the decoded still image data and video data to generate image data for one frame of the display device DS in the frame buffer FB; (7) multiple display circuits 71 that read the image data from the frame buffer FB generated by the drawing circuit 74, perform appropriate image processing, and output it; and (8) The system comprises (9) an output selection unit 76 that appropriately selects and outputs the outputs of multiple display circuits 71, an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs it, (10) an audio processing unit SND that executes audio effects based on an audio command list VC, (11) a motor control unit MT_CTL that executes motor effects, and (12) a lamp control unit L_CTL that executes lamp effects (see Figure 5(a)). The audio processing unit SND includes an audio decoder that decodes compressed data for audio effects read from an external ROM 55.

[0110] Motor effects are executed based on the control operations of the effect control CPU 57, specifically based on the setting value of a predetermined effect control register RGij for motor effects and the control data (motor drive data) copied to the extended RAM 54. Lamp effects are executed similarly, based on the control operations of the effect control CPU 57, specifically based on the setting value of a predetermined effect control register RGij for lamp effects and the control data (lamp drive data) copied to the extended RAM 54.

[0111] Figure 5(b) illustrates the relationship between the CPU bus section 56, the CG bus IF section 55a, the extended RAM IF section 54a, and the VRAM IF section 53a, and the performance control register RGij, the external ROM 55, the extended RAM 54, and the VRAM 53. As shown in the figure, the CG compressed data acquired from the external ROM 55 is supplied to the GDEC circuit 73 via the CG bus IF section 55a and the data transfer circuit 70, and the decompressed (decoded) data is expanded into a predetermined index space reserved in the extended RAM 54 or VRAM 53.

[0112] As explained earlier, in this embodiment, an ACC area for decompressing still images is reserved in VRAM 53, and a page area for decompressing video frames is reserved in extended RAM 54. Then, the decoded data of still images and videos is decompressed in a predetermined index space in the ACC area / page area. In addition, the decompressed data of compressed CG data acquired from the external ROM 55 may be transferred to the preload area of ​​extended RAM 54 as preload data.

[0113] Next, the display circuit 71 will be described based on Figure 7. The display circuit 71 is a circuit that reads the image data of the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and then outputs it. The final image processing includes, for example, scaling processing of the scaler to enlarge / reduce the image to a similar shape, subtle color correction processing, and dithering processing to minimize the quantization error of the entire image. These image processing processes are performed uniformly based on the setting value in the performance control register RGij (display register). The digital RGB signal that has undergone uniform image processing is then output along with the horizontal synchronization signal and the vertical synchronization signal.

[0114] As shown in Figure 7, three display circuits A / B / C are provided to perform the above operations in parallel. However, in this embodiment, since there is only one display device, only the frame buffer FB (=FBa) for display circuit A is reserved. However, if frame buffers FBa to FBc are reserved, it is also possible to drive the other two display devices that can perform independent image effects.

[0115] Next, we will return to Figure 5(a) and explain the data transfer circuit 70. The data transfer circuit 70 is a circuit that performs DMA (Direct Memory Access) data transfer operations between the internal resources of the integrated production circuit 52 and the external storage medium, with the internal resources and external storage medium being the source and destination of the transfer. Figure 8 is a block diagram showing the internal configuration of this data transfer circuit 70 along with the related circuit configurations.

[0116] In this embodiment, the data transfer source for the data transfer circuit 70 includes the CPU address space via the CPU bus 56, the external ROM 55, the extended RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the data transfer destination for the data transfer circuit 70 includes the CPU register port PORT, the CPU address space, the extended RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0117] Here, the CPU address space refers to the memory area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus 56, and the performance control CPU 57 can access it arbitrarily as a read / write.

[0118] Furthermore, virtual work areas such as page areas and arbitrary areas are defined in the extended RAM 54 and VRAM 53. Within these virtual work areas, an index space identified by an index number is allocated / deallocated. Therefore, the operation of the data transfer circuit 70 is performed by referring to the index table IDXTBL, which stores the relationship between the index space and the actual address space. The index space allocated in the extended RAM 54 or VRAM 53 can also be set as the data source or data destination of the data transfer circuit 70. Consequently, data from the frame buffer FB allocated in an arbitrary area of ​​VRAM 53 can also be transferred to the extended RAM 54.

[0119] Incidentally, in the circuit configuration shown in Figure 8, the transfer size that the data transfer circuit 70 can transfer is 32 bits × (01h to 4000_0000 h) when passing through data relay units CH0 to CH1, and 32 bits × (01h to 100_0000 h) when passing through data relay units CH2 to CH4. In other words, the data transfer circuit 70 in this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h means a hexadecimal number, and the upper limit of the transfer size is specifically 32 × 1,073,741,824 bits when passing through data relay units CH0 to CH1, and 32 × 16,777,216 bits when passing through data relay units CH2 to CH4.

[0120] As shown in Figure 8, the data transfer circuit 70 is configured to receive necessary data from the external ROM 55 via the arbitration circuit ICM, which has router functionality and arbitrates access paths, and to send and receive necessary data with the VRAM 53 and the extended RAM 54. The external ROM 55, VRAM 53, and extended RAM 54 are accessed via the CG bus IF unit 55a, the VRAM IF unit 53a, and the extended RAM IF unit 54a.

[0121] This data transfer circuit 70 consists of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five data relay sections CH0 to CH4. As explained earlier, the CPU register port PORT is configured to be read-only accessible from the performance control CPU 57.

[0122] The data relay section CH0 consists of a 1024-bit x 18-stage CH0 data FIFO circuit and a checksum circuit. The data relay sections CH1 to CH4 each consist of a 1024-bit x 18-stage CH0 data FIFO circuit. The data relay sections CH2 to CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0123] On the other hand, the CPU data FIFO circuit and the data relay units CH0 to CH1 are configured to communicate bidirectionally. Therefore, a predetermined amount of data set in the data transfer register is transmitted and received from a predetermined source set in the data transfer register to a predetermined destination set in the data transfer register, via the CPU data FIFO circuit or the data relay units CH0 to CH1.

[0124] Regardless of which path (CH0-CH4) is used for data relay, the amount of data to be transferred (data size) must be set in 32-bit units, as described above, and there are also predetermined restrictions on the starting addresses of the source and destination. Specifically, the starting addresses of the source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in VRAM 53 and extended RAM 54. The source starting address in external ROM 55 is also set in 32-bit units.

[0125] When data is transmitted via the data relay section CH0~CH1, the source and / or destination are the external ROM 55, VRAM 53, or extended RAM 54. When data is transmitted via the CPU data FIFO circuit connected to the CPU register port PORT, the source or destination is the CPU address space. The CPU address space naturally includes the built-in RAM 59.

[0126] The above describes the bidirectional data relay units CH0 to CH1, but the data relay units CH2 to CH4 form a unidirectional communication path. The performance control CPU 57 can transmit the display list DL and the voice command list VC of the DL buffer BUF of the built-in RAM 59 to the data relay units CH2 to CH4 in one direction by writing to the CPU register port PORT in 32-bit units via the CPU bus unit 56.

[0127] Furthermore, the built-in RAM 59 can be selected as the data transfer source, so data can also be transferred via the data relay section CH2~CH4 (without going through the CPU register port PORT) using the DL buffer BUF as the data transfer source and the drawing circuit 74, preloader 72, or audio processing unit SND as the data transfer destination.

[0128] In this case, the starting address of the built-in RAM 59, the source of the data transfer, is defined in 8-bit units, so the lower 7 bits of the starting address of the DL buffer BUF must be zero. Also, regardless of whether or not the data is transferred via the CPU register port PORT, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0129] In any case, data relay units CH2, CH3, and CH4 are each unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via data relay unit CH2, and to the preloader 72 via data relay unit CH3. Similarly, an audio command list VC of a predetermined data transfer size is transferred to the audio processing unit SND via data relay unit CH4.

[0130] As described above, in this embodiment, the transfer paths for the display list DL and the voice command list VC are provided as follows: (1) a first path via the CPU register port PORT, and (2) a second path that does not go through the CPU register port PORT. Either of these can be used. This also applies to other data besides the display list DL and voice command list VC, where there is a first path via the CPU register port PORT and data relay units CH0~CH4, and a second path via only the data relay units CH0~CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, while the second path is used for data transfers (DMA operation) in which the performance control CPU 57 is not directly involved.

[0131] Incidentally, as shown in Figure 8, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 are configured to receive data in 1024-bit units. Therefore, when the first path is utilized, once 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data will be transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as the channel data FIFO).

[0132] In other words, if less than 32 stages of data are written to the CPU data FIFO circuit, no data transfer to the channel data FIFO occurs. Only when the 32nd stage of data is written is the 32 stages of accumulated data transferred to the channel data FIFO, and then the data is transferred to the next destination.

[0133] On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, it is possible that the data in the CPU data FIFO circuit may end up with less than 32 stages. However, when the cumulative size of the written data reaches the transfer size set in the data transfer register beforehand, the accumulated data of less than 32 stages will be transferred to the channel data FIFO and the destination beyond it.

[0134] Thus, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value that is an integer multiple of 32 bits, regardless of whether it passes through the first path or the second path. Corresponding to this configuration, the instruction commands that make up the display list DL and the voice commands that make up the voice command list VC are all composed of integer multiples of 32 bits. Therefore, in this embodiment, there are no restrictions on the number of commands in the display list DL or the voice command list VC, allowing for a free list configuration, and there is no need to adjust the total data size by adding dummy commands or the like.

[0135] Figure 9 shows the transfer operation of the display list DL to the drawing circuit 74 via the CPU register port PORT and data relay unit CH2 (Figure 9(a)), the transfer operation of the display list DL from the built-in RAM 59 to the drawing circuit 74 via the data relay unit CH2 (Figure 9(b)), and the transfer operation of the rewritten list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (Figure 9(c)).

[0136] Figures 9(d) and 9(e) show the operation of transferring the display list DL to the preloader 72 via the CPU register port PORT and data relay unit CH3, and the operation of transferring the display list DL from the built-in RAM 59 to the preloader 72 via data relay unit CH3.

[0137] Furthermore, Figures 9(f) and 9(g) show the transfer operation of the voice command list VC to the voice processing unit SND via the CPU register port PORT and data relay unit CH4, and the transfer operation of the voice command list VC from the built-in RAM 59 to the voice processing unit SND via data relay unit CH4.

[0138] The CPU circuit 51 starts the operation of the drawing circuit 74, preloader 72, and audio processing unit SND prior to the start of operation of the data transfer circuit 70. The drawing circuit 74 then starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 performs the necessary preload operations based on the transferred display list DL. The transferred display list DL is determined by the display list analyzer built into the drawing circuit 74 and preloader 72, and processing is performed according to the type of instruction command. The audio processing unit SND then starts or proceeds with audio effects based on the transferred audio command list VC.

[0139] Furthermore, data in the CPU address space other than the display list DL and voice command list VC can be transmitted via the CPU bus 56, then via the CPU register port PORT, or directly to the data relay units CH0~CH4. The data relay units CH0~CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or extended RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar; the data relay units CH0~CH1, having received data via the arbitration circuit ICM, transfer it either via the CPU register port PORT or directly to a predetermined destination in the CPU address space.

[0140] Next, the preloader 72 will be explained, but whether or not to utilize the preloader 72 is optional. When the display list analyzer interprets the display list DL transferred from the data relay section CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data on the external ROM 55 that the LOADTX command refers to to the preload area of ​​the extended RAM 54 (see Figure 6(b)).

[0141] Furthermore, the preloader 72 stores a rewrite list DL' in the DL buffer BUF' of VRAM 53 (see Figure 6(a)) in which the reference destination of the CG data for the LOADTX command described above has been rewritten to the address after the transfer. Note that the DL buffer BUF' and the preload area are allocated in advance during the initial processing after the CPU reset.

[0142] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM of the data transfer circuit 70 and the data relay unit CH2 when the drawing operation of the drawing circuit 74 begins (see Figure 9(c)). The drawing circuit 74 then performs the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external ROM 55 based on commands such as LOADTX is quickly obtained from the preload area of ​​the extended RAM 54 as preloaded data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is activated in a typical equipment configuration.

[0143] In this embodiment, since the preload area is set in the external expansion RAM 54 which has sufficient memory capacity, it is possible to perform multiple preloads, for example, by preloading CG data for multiple frames at once. That is, regarding the operation period of the preloader 72, multiple preloads are realized by appropriately setting the operation period of a series of preload operations, including the pre-reading operation of CG data, within the range of an integer multiple of the operation period δ during the intermittent operation of the integrated production circuit 52.

[0144] However, for convenience, the following description will explain an embodiment without multiple preloads, so the preloader 72 in this embodiment will complete the preload operation for one frame during one operation cycle δ. In this embodiment, the operation cycle δ of the integrated production circuit 52 during intermittent operation is 1 / 30 of a second, which is twice the period of the vertical synchronization signal of the display device DS.

[0145] Next, the drawing circuit 74 sequentially analyzes the instruction command sequences of the display list DL and rewrite list DL' transferred via the data transfer circuit 70, and, in cooperation with the GDEC circuit 73 and the geometry engine, draws an image of one frame of the display device DS onto the frame buffer FB reserved in the VRAM 53.

[0146] As described above, when the preloader 72 is in operation, the CG data referenced in the rewrite list DL' is not the external ROM 55, but the preload area set in the extended RAM 54. Therefore, sequential access to the CG data that occurs during drawing by the drawing circuit 74 can be performed quickly, and even high-resolution videos with rapid movement can be drawn without problems.

[0147] Incidentally, regardless of whether the preloader 72 is activated or not, even if data bit corruption occurs during the transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect it. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the start of operation of the drawing circuit 74.

[0148] In order to detect malfunctions in the drawing circuit 74, this embodiment provides a time setting register TO that allows the user to arbitrarily set a timeout period. The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to start based on the setting value of a predetermined drawing register (drawing operation permission / denial register).

[0149] When a predetermined timeout period is set in the time setting register TO, and start information is set in the drawing operation permission register, the drawing circuit 74 starts operating. In response, the timeout monitoring circuit monitors the memory access cycle. If no memory access occurs even after the timeout period has elapsed, the abnormal flag in a predetermined drawing register is set to ON, and an abnormal interrupt is triggered.

[0150] While it is possible to respond to this abnormal interrupt by activating an interrupt handling program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag at each operation cycle δ of the integrated display circuit 52. Specifically, if the abnormal flag is ON, the screen update is skipped for that operation cycle, even if the operation of the drawing circuit 74 has been completed.

[0151] Here, if measures such as activating the WDT58 or resetting the drawing circuit 74 are taken, as in the configurations of Patent Documents 1 and 2, there is a risk that an unnatural screen display may appear. However, in this embodiment, the appearance of abnormal screens is easily prevented with minimal intervention. Furthermore, the monitoring timeout period can be arbitrarily set considering the arrangement of commands such as the LOADTX command in the display list DL and the access time of the external ROM 55, so optimal monitoring operation can be achieved.

[0152] Incidentally, in the above configuration, the memory access cycle was monitored from the start to the end of operation of the drawing circuit 74. However, it is also preferable to adopt a configuration in which the operation time of the GDEC circuit 73 from the start to the end of operation is monitored, instead of this configuration, or in addition to this configuration. In this case as well, an optimal value considering the data capacity of the texture can be set in the time setting register TO', so optimal monitoring operation can be achieved.

[0153] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding the CG compressed data, and ends the monitoring operation for that cycle when decoding is complete. In the case of a timeout, the abnormal flag in a predetermined drawing register is set to ON, triggering an abnormal interrupt, and when an abnormality is detected, the screen update for that operation cycle is skipped, just as in the former configuration. In this embodiment, a flag polling method is used to check the ON / OFF state of the abnormal flag at each operation cycle δ of the integrated presentation circuit 52, but a configuration may also be adopted in which an abnormal interrupt processing program is activated to skip the screen update for the operation cycle in which the problem occurred.

[0154] Next, the image filter circuit 75 functions based on instruction commands (filter execution commands) described in the display list DL, and performs appropriate filtering on textures temporarily stored in VRAM 53 or extended RAM 54. In other words, the image filter circuit 75 in this embodiment does not perform uniform filtering based on the setting value of the performance control register RGij, but rather allows for flexible filtering of necessary image data by arbitrarily describing appropriate instruction commands in the display list DL.

[0155] The content of the filtering process is determined by the selection of the filtering execution command and the setting parameters of the selected command, but the executable filtering processes include (1) FIR (Finite Impulse Response) filtering, (2) downsampling, and (3) linear interpolation. Here, downsampling is a different process from the uniform scaling process in the display circuit 71 that operates based on the setting value in the performance control register RGij (display register).

[0156] In other words, downsampling involves reducing the image only in the vertical direction or only in the horizontal direction, rather than reducing it to a similar shape like scaling. While not particularly limited, downsampling reduces the texture by calculating the average value of the image information of pixels within a predetermined range surrounding the target pixel and applying a decimation process such as moving average processing.

[0157] Figure 10(a) is a diagram illustrating an example of operation in which FIR filtering is performed twice consecutively by a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be filtered should be saved (command processing L20). Subsequently, the LOADTX command retrieves the reference texture from the external ROM 55 indicated by the setting parameters of that command, and saves the decoded image data to the destination index space (command processing L21).

[0158] Then, the SETFTINDEX command sets the index space where the result texture will be saved (command processing L22), and the SETFTSAMP and SETFTCOEF commands set the filter coefficients and other information (command processing L23), and the FTEXECFIR command executes the FIR filter (command processing L24). Note that the SETFTINDEX command distinguishes whether to specify the index space for the reference texture or the index space for the result texture depending on the parameters set in the command.

[0159] As shown in Figure 10(b), the image data expanded into the index space for the reference texture specified by instruction command L20 is then stored in the index space for the result texture specified by instruction command L22 after undergoing the FIR filtering process specified by instruction command L23.

[0160] Next, the SETFTINDEX command is used to set the index space for the reference texture (command processing L25), and the SETTXINDEX command is used to set the index space where the result texture will be saved (command processing L26). Since the filtered image data is designated as the reference texture in instruction command L25, the result texture specified in instruction command L22 will be changed to the reference texture by instruction command L25.

[0161] After that, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command processing L27), and then the necessary FIR filtering is performed using the FTEXECFIR command (command processing L28). The filtered image data is then stored in the index space specified by the instruction command L26, so after activating the SETTXMODE command, the SPRITE command is executed (command processing L29), and the image data that has undergone FIR filtering is drawn into the appropriate rectangular section of the virtual drawing space.

[0162] Figure 10(c) is a diagram illustrating an example of how scaling is performed by a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be scaled should be saved (command processing L30), and then the LOADTX command retrieves the reference texture from the external ROM 55 indicated by the command's setting parameters (command processing L31).

[0163] Next, the SETTXINDEX command is used to set up an index space for storing the auxiliary data necessary for scaling (command processing L32). Here, the auxiliary data is plane information extracted from the reference texture, which is information that characterizes the reference texture. The reason for considering such auxiliary data is that the scaling process in this example includes deformation of dissimilar shapes that are not similar in shape, and appropriate interpolation processing is performed to eliminate the unnaturalness of the deformed image.

[0164] Therefore, in the scaling process of this embodiment, the FTEXECGRD command is written following command L32 to generate auxiliary information (plane information) in the index space defined by command L32 (command processing L33). With the necessary preparations completed with the commands up to this point, the next step is to set the index space to be used as a texture with the SETTXINDEX command (command processing L34), set the necessary information with the SETTXSAMP command, and then execute the scaling process with the SETTXMODE command (command processing L35).

[0165] As a result of the above, the image data after scaling is stored in the index space specified by the instruction command L34. Therefore, after executing the SETTXMODE command, the SPRITE command is executed (command processing L36), and the image data after scaling is drawn into the appropriate rectangular section of the virtual drawing space.

[0166] The image filter circuit 75 has been described above, but the GDEC circuit 73 performs decoding processing on compressed data such as stream video, still images, and alpha values ​​using software processing corresponding to each compression algorithm. In this embodiment, the stream video is divided into S-stream, IP-stream, and IPB-stream, and the frames constituting the stream video are composed of I-pictures, S-pictures, P-pictures, or B-pictures in appropriate combinations.

[0167] An I (Intra-coded) picture refers to an intra-coded screen, meaning image data that is compressed as is, independently of other screens. On the other hand, an S picture is image data that performs predictive coding by referring to the most recent I pictures, and has the advantage of a higher compression ratio than an I picture. The S-stream video in this embodiment is a video that combines these I pictures and S pictures, and by arranging the I pictures according to a certain period, random access and reverse playback starting from the I pictures can be performed, enabling effective image effects. Note that S-stream videos without S pictures are also possible, and S-stream videos without S pictures are substantially the same as I-stream videos.

[0168] Next, P-pictures (Predictive coded) are image data that perform forward predictive coding, predicting the current frame from a frame that has been in the past in time. Predictive coding is performed from an I-picture or P-picture located in the past in time. On the other hand, B-pictures (Bidirectional coded) are image data that perform bidirectional predictive coding, performing both forward prediction and backward prediction, predicting the current frame from a future frame. Predictive coding is performed from an I-picture or P-picture located in the past and future in time.

[0169] Generally, interframe prediction techniques include forward prediction (predicting the current frame from frames in the past), backward prediction (predicting the current frame from future frames), and bidirectional prediction (performing both forward and backward prediction). B-picture performs bidirectional prediction, which can improve prediction accuracy.

[0170] Therefore, in this embodiment, in addition to S-stream videos which combine I-pictures and S-pictures, the system is configured to also play IP-stream videos and IPB-stream videos which appropriately combine I-pictures, P-pictures, and B-pictures. IP-stream videos are composed of a combination of I-pictures and P-pictures, while IPB-stream videos are composed of a combination of I-pictures, P-pictures, and S-pictures.

[0171] As is clear from the above relationship, in S-stream videos containing S-pictures and IPB-stream videos, due to the need for backward predictive coding, it becomes necessary to acquire and decode I-pictures and P-pictures that should be played later in time, prior to acquiring S-pictures and B-pictures.

[0172] Therefore, in this embodiment, a single LOADTX command is configured to identify multiple textures, namely the main frame's CG data and the subframe's CG data. Here, the main frame refers to the CG frame data that should be played back at the current time, and the subframe refers to the CG frame data that should be played back at a different time.

[0173] For example, in S-pictures, predictive coding is performed by referencing the most recent (previous or next) I-picture. Therefore, in S-stream videos where I-pictures and S-pictures are consecutive, the CG data of both the S-picture as the main frame and the I-picture as a subframe may be acquired and decoded with a single LOADTX command.

[0174] Furthermore, since B-picture (Bidirectional coded) performs bidirectional predictive coding, it is necessary that the CG data of past frames and the CG data of future frames be allocated in a decoded state prior to the decoding process of the B-picture. Therefore, in this embodiment, when playing back an IPB stream video, it is necessary to allocate a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space with sufficient capacity to store the reference image, allocated in an arbitrary area of ​​VRAM 53 or extended RAM 54, and identified by a unique index number.

[0175] Figure 11 is a diagram illustrating the playback procedure for IPB stream video, with the playback operation progressing from the top to the bottom of the page. Figure 11 is divided into six sections horizontally, and from left to right, they show: (1) the LOADTX command on the display list DL, (2) the pictures that make up the IPB stream video, (3) the decoding process of the main frame and subframes, (4) the decoding process of the reference image, (5) the reference buffer where the reference image is stored, and (6) the index space (expansion space) where the decoded image displayed on the screen is stored.

[0176] The downward arrow in the first column indicates the progression of the operating cycle of the intermittently operating integrated production circuit 52 (GDEC circuit 73), and the downward arrow in the sixth column indicates the display order of the images displayed on the display device DS. For convenience, in the following explanation, a group of video frames played back at timings T1 to T7 is referred to as a GOP (Group Of Picture), but the GOP can be changed as appropriate based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0177] First, the LOADTX command at timing T1, when the I-picture should be played back, identifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the subframe through its embedded parameters. The index number of the expansion space where the decoded data should be stored is also identified.

[0178] Therefore, the I-picture (I1) acquired based on the LOADTX command at timing T1 is decoded and stored in the first reference buffer, which stores past frames, along with its original expansion space. Also, the P-picture (P1) is acquired based on the LOADTX command at timing T1, and its decoded data is stored as a reference image in the second reference buffer, which stores future frames. The reference image is stored in a compressed state using a special method, although this is not particularly limited.

[0179] Next, the LOADTX command at timing T2 instructs only the B picture (B1) as the main frame. Then, as a bidirectional predictive operation, the image data B1 of the current frame is reconstructed and saved in the unfolded space based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B1). The same applies to the subsequent LOADTX command at timing T3, where the image data B2 of the current frame is reconstructed and saved in the unfolded space based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B2).

[0180] Next, in the LOADTX command at timing T4, when the P-picture should be played back, the embedded parameters of the command instruct that the main frame P-picture (P1) should be retrieved from the second reference buffer. The address of the subframe P-picture (P2) is also identified.

[0181] Therefore, at timing T4, the P-picture (P1) in the second reference buffer, which is compressed using a special method, is decompressed and saved in the decompression space. At the same time, the P-picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. In addition, a future P-picture (P2) is acquired by the LOADTX command at timing T4, and its decoded data is saved in the second reference buffer as a reference image for the future frame.

[0182] The subsequent operations at timings T5 and T6 are substantially the same as those at timings T2 and T3. That is, at timing T5, based on bidirectional prediction, the B3 picture image, which is based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B3), is unfolded into the unfolding space. At timing T6, the B4 picture image, which is based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B4), is unfolded into the unfolding space.

[0183] Next, the LOAD command at timing T7 instructs that the main frame, P picture (P2), be retrieved from the second reference buffer. The address of the subframe, I picture (I2), is also identified. Therefore, at timing T7, P picture (P2) in the second reference buffer is decompressed and saved in the decompression space. Simultaneously, the I picture (I2) is retrieved according to the instructions of the LOADTX command at timing T7, and its decoded data is saved in the second reference buffer as a reference image for future frames.

[0184] At the next timing T9, the system is instructed to retrieve the main frame, I-picture (I2), from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the decompression space, and at the same time, the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. In addition, the LOAD command at timing T9 specifies the address of the subframe, P-picture (P3), so P-picture (P3) is retrieved, and its decoded data is saved in the second reference buffer as a reference image for future frames.

[0185] Figure 12(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT, in which 64 processing blocks are arranged to operate in parallel; a post-processing unit BK, which consists of a master effect unit, a master volume unit, an output protection unit, and a serializer; and a mixer MX, which transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0186] As shown in the diagram, the pre-processing unit FT is equipped with 64 decoders that receive compressed audio data (compressed phrase data) from the external memory 55. On the other hand, the post-processing unit BK is configured to output the audio signals SDOUTA to SDOUTD of the four paths A / B / C / D as serial data, along with the clock signal SBCLK and the control signal SLRCLK, via a serializer. The serial data SDOUTA to SDOUTD of the four paths A / B / C / D each contain right data R and left data L on one data line, and depending on whether the control signal SLRCLK is in a high-level period or a low-level period, it is determined whether the serial data SDOUTA at that timing is left data L or right data R.

[0187] Next, regarding the internal operation of the pre-processing unit FT, the phrase data decompressed by the decoder has its volume adjusted appropriately by the primary volume, secondary volume, and pan pot section. Here, the primary and secondary volume controls two levels of volume adjustment, while the pan pot section adjusts the volume ratio between the left and right speakers. The specific operations of the primary volume, secondary volume, and pan pot section are defined by the voice commands listed in the voice command list VC.

[0188] By the way, phrase data is audio data that realizes a single unit of audio production, and includes a whole song of background sound, or a single unit of audio production such as sound effects or shouts. Then, one phrase data is output from the pan pot section of the pre-processing unit FT to 8 paths. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing unit FT) are arranged to operate in parallel, and at most 64 phrase data can be output to the mixer MX, and the audio data, which is grouped into 8 paths (4 paths A / B / C / D for left and right audio R / L), is transmitted to the post-processing unit BK.

[0189] The pan pot allows you to adjust the volume ratio between the left and right speakers. For example, you can set the pan pot of the first track to output only to the first line of the Mixer MX with the left-to-right volume ratio set to maximum:zero, while setting the pan pot of the second track to output only to the second line of the Mixer MX with the left-to-right volume ratio set to zero:maximum. As a result, for example, the first phrase data, which is the left audio, will be output only to the first line, and the second phrase data, which is the right audio, will be output only to the second line, enabling stereo playback using the left and right speakers of system A.

[0190] Next, regarding the internal operation of the post-processing unit BK, the master effect performs audio filtering, and the master volume makes the final volume determination. The specific details of these operations are defined by the audio commands listed in the audio command list VC. The master volume is used, for example, for silent warnings that instantly silence the volume effect, while the master effect is used, for example, for sound change warnings that drastically alter the sound quality.

[0191] Figure 12(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands listed in the voice command list VC. Here, the START command, which instructs the start of playback of a specific phrase data, the PAUSE command, which instructs the stop of playback of a specific phrase data, the RESUME command, which instructs the resume of playback of a specific phrase data, and the STOP command, which instructs the end of playback of a specific phrase data are shown as examples. The voice command list VC is composed of one or more voice commands, but it must be terminated with a predetermined termination command EOSC.

[0192] First, the voice command list VC1 is instructed to start playback of 64 types of phrase data by voice commands START1 to START64. Therefore, once the decoding process of the 64 types of compressed phrase data is complete, playback of the 64 types of phrase data will begin.

[0193] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC2 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0194] Furthermore, the voice command list VC can be output not only at the start and end of phrase data playback, but also at any necessary timing within the operation cycle δ (= 1 / 30 second) of the integrated production circuit 52. In other words, the display list DL is output every operation cycle δ of the integrated production circuit 52, but the voice command list VC is generally output irregularly.

[0195] Next, the drawing pipeline processing that can be executed in the drawing circuit 74 will be described. Figure 13(a) shows a detailed illustration of the part of the drawing circuit 74 related to the drawing pipeline processing. The display list analyzer sequentially analyzes the instruction commands listed in the display list DL and transfers the instruction commands to the appropriate internal circuits according to their type. In Figure 13(a), instruction commands are specifically referred to as drawing commands, and in the following explanation, instruction commands may also be referred to as drawing commands.

[0196] The internal circuits that receive drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands listed in the display list DL in the order they are written and forwards them one after another to the corresponding internal circuits (see Figure 13(a)).

[0197] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with respect to the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that sequentially transfers the configuration data of the display list DL. Generally, the operating speed of the internal circuitry of the drawing circuit 74 is significantly slower than the transfer speed of the configuration data of the display list DL.

[0198] Therefore, the internal circuitry that receives drawing commands is equipped with a waiting queue that stores drawing commands before processing begins. The display list analyzer places a drawing command into the waiting queue only if there is an empty slot in the queue. In other words, the display list analyzer stalls (pauses) the placement operation until the waiting queue becomes free, so there is no risk of losing a drawing command. The numbers indicated in the waiting queue are illustrative examples of the queue's stages.

[0199] As explained earlier, the instruction commands listed in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture loading commands such as the LOADTX command for reading image materials (textures) from the external ROM 55 and decoding (decompressing / unpacking); (3) filter execution commands that specify the filtering process for the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (unpacked) image materials in a predetermined position in the virtual rendering space; and (5) pipeline commands related to the operation of the rendering pipeline.

[0200] As shown in Figure 13(a), the index table control command (1) is transferred to the control circuit of the index table IDXTBL, the texture load command (2) is transferred to the GDEC circuit 73, and the filter execution command (3) is transferred to the image filter circuit 75, where each is processed appropriately. Specifically, the GDEC circuit 73 operates based on the transferred drawing commands (texture load commands) to obtain the necessary textures and expand the decompressed data into the decode space.

[0201] Furthermore, the index table IDXTBL is updated as needed by the operation of the control circuit for the index table IDXTBL. The image filter circuit 75 applies a specified filter to a predetermined reference texture and saves the filter result to a predetermined index space (see Figure 10). In addition, when a predetermined drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS operates, enabling high-speed data transmission and reception between VRAM 53 and extended RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74 and is a separate circuit from the data transfer circuit 70.

[0202] When using the data transfer circuit 70, the CPU circuit 51 needs to set the type of source medium and the transfer start address, the type of destination medium and the receiving start address, and the transfer size in a predetermined performance control register RGij (data transfer register). However, the high-speed transfer circuit TRNS has the advantage of being able to be activated by an instruction command (transfer execution command) in the display list DL when needed, and moreover, it has the advantage of being able to transfer two-dimensional data at high speed using the index space as the unit. It should be noted that, in a control program that is functioning on a regular basis without adopting the configuration of this embodiment, it is not easy from a program configuration standpoint to use the data transfer circuit 70 only when needed.

[0203] As explained earlier, the drawing pipeline operation is performed using the vertex buffer VB built into the drawing circuit 74, the frame buffer FB reserved as an index space, and the depth stencil buffer which manages the front-to-back relationships of polygons and whether or not pixels are displayed. The input assembler process IA, the geometry engine process TL, the rasterizer process RS, the texture sampler process TX, the texture process PS, the pixel drawing process PX, and the render process RO are configured to be executed as needed.

[0204] In other words, the drawing pipeline process is executed from upstream to downstream, either by going through all processes or some of them, in the order of process IA → process TL (process VB) → process RS → process TX → process PS → process PX → process RO. Each process operates in parallel, but since the completion of drawing commands becomes slower as you move downstream, the number of stages in the waiting queue that accumulates drawing commands for each process is configured so that it does not fall below the number of stages in the waiting queue on the upstream side.

[0205] As illustrated in Figure 13(a), the number of stages in the standby queue corresponds to process IA → process TL → process RS → process TX → process PS → process PX → process RO, with 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages. The number of stages in each process is the same as or greater than the number of stages in the upstream standby queue.

[0206] By the way, the pipeline commands explained earlier are setting commands that define the operation of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the necessary operating parameters for the required internal circuits, such as the geometry engine.

[0207] In this embodiment, as shown in Figure 13(b), the drawing pipeline consists of processes IA, TL, RS, TX, PS, PX, and RO. First, the input assembler process IA typically obtains the vertex stream of a three-dimensional 3D drawing object defined in local coordinates, stores the information necessary for subsequent processing, and outputs vertex data having predetermined vertex information.

[0208] In this IA process, in addition to the setting commands for IA (pipeline commands), drawing commands such as the DRAW command and DRAWD command are used. The DRAW command specifies the starting address of the memory (external ROM 55 in this embodiment) where a series of vertex streams are stored, and the number of vertices.

[0209] On the other hand, the DRAWD command has a series of vertex streams embedded in it. The specific operation of the DRAW and DRAWD commands is defined by the embedded information of each command and the setting commands for process IA. In the vertex stream, a vertex color (RGBA color information) can be defined for each vertex, but if a vertex color is not defined, a default value is set as the vertex information in the input assembler process IA. Here, RGB means color information of R=Red, B=Blue, G=Green, and A is the alpha value α which indicates opacity and is used in the alpha blending process when compositing overlapping images.

[0210] In the subsequent geometry engine process TL, matrix operations are performed on the vertex data output from the input assembler process IA to transform the vertex coordinates of 3D rendering objects, as well as lighting processing related to light sources. The coordinate transformation process includes view matrix operations to convert local coordinates to view coordinates, and matrix operations for projection transformation (perspective projection).

[0211] Here, the view coordinate system is one in which the viewpoint is the origin and the point at infinity (0,0,-∞) is the point of line of sight. In projection transformation, to achieve perspective corresponding to the placement of the 3D rendering object, the transformation from the view coordinate system to the clip coordinate system is achieved by scaling the shape of the 3D rendering object.

[0212] The specific details of the matrix operations are defined by the setting commands for the TL process (pipeline commands), and the execution of the predetermined geometry matrix operations is instructed by the DRAW command or DRAWD command. Therefore, processes IA and TL can be executed together with a single drawing command (DRAW / DRAWD). However, in either case, the results of the geometry matrix operations performed by the drawing command (DRAW / DRAWD) are saved in the vertex buffer VB.

[0213] Note that the geometry engine process TL is not mandatory. If a vertex stream defined by clip coordinates is obtained from the external ROM 55, that information is stored directly in the vertex buffer VB via the input assembler process IA. Furthermore, the input assembler process IA and geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to store a maximum of 256 vertices.

[0214] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB. After eliminating unnecessary polygons through transformation from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc., pixel data for the 3D drawing object is generated. In other words, the three-dimensional 3D image object is fixed in a predetermined position and orientation in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0215] To generate primitives, you can appropriately select and use triangle drawing methods such as triangle lists, triangle strips, or triangle fans, as well as line drawing methods such as line lists, line strips, and line fans.

[0216] Furthermore, in this rasterizer process (RS), in addition to setting commands for the RS process (pipeline commands) that specifically define the processing content, drawing commands such as DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate.

[0217] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB. On the other hand, the DRAW command generates and draws primitives based on a vertex stream obtained from the external ROM 55, while the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0218] Therefore, it is possible to perform the rasterizer process RS without going through the geometry engine process TL. For example, in the case of a two-dimensional 2D drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color of each vertex.

[0219] Next, in the texture sampler process TX, the index space to be used as the texture is identified, and the texture coordinates for each pixel are also identified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are calculated as appropriate.

[0220] In these processes TX and PS, and in the following process PX, in addition to the setting commands (pipeline commands) for each process, the drawing commands DRAW, DRAWD, DRAWI, or SPRITE are used as appropriate. The DRAW, DRAWD, or DRAWI commands apply a texture to the area enclosed by the specified vertices, while the SPRITE command applies a texture to the specified rectangular area.

[0221] Next, in the pixel rendering process PX, the rendering color and background color are combined, tone mapping is performed to adjust the contrast, and inverse tone mapping is performed. In this PX process, pixel data containing predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the rendering position of the pixel is input for each pixel from the frame buffer FB.

[0222] In the final rendering stage (RO), the depth and stencil buffers are referenced, and pixel tests are performed to determine whether or not to display a pixel based on its depth and stencil information. After alpha blending processing for overlapping rendering objects, the completed rendering object is written to the frame buffer FB. Writing to the frame buffer FB is equivalent to drawing into the virtual rendering space shown in Figure 6, and the SPRITE command is usually used for this purpose.

[0223] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the RO rendering process also allows the use of the CLEAR command, which fills the frame buffer (FB) with a single color, and the CLEARZ command, which fills the depth and stencil buffers with a single color. The CLEAR command is used to clear the frame buffer (FB) before the start of the rendering operation, while the CLEARZ command is used when depth information and stencil information are not needed.

[0224] In this invention, all or part of the series of drawing pipeline processes function, and two-dimensional or three-dimensional drawing objects are successively written to the frame buffer FB, ultimately completing the image data for one frame of the display device. In this embodiment, two-dimensional and three-dimensional drawing objects are distinguished by whether or not they undergo coordinate transformation processing to three-dimensional coordinates.

[0225] Figure 14 is a process diagram showing various rendering modes that utilize all or part of the rendering pipeline process. First, the rendering mode in Figure 14(a) is an operation mode that uses the CLEAR command and CLEARZ command described above, and only the render process RO is functional.

[0226] The sprite drawing mode in Figure 14(b) involves the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the window vertices, and this offset value is related to the paste rectangle area of ​​the SPRITE command.

[0227] In practice, the SETTXINDEX command sets the target index space for the sprite rendering, the LOADTX command retrieves the specified texture and renders it into the index space, and the SPRITE command reserves this rendered texture in the designated location. Then, the information of the rendered texture is referenced and finally written to the frame buffer FB. Video playback and playback of simple still images are, in principle, achieved using this sprite rendering mode, but preferably, all still images and / or all videos are played using sprite rendering mode.

[0228] The drawing mode shown in Figure 14(c) is an example of operation that uses the entire drawing pipeline to draw triangles and lines. The only difference between triangle drawing and line drawing is the method of primitive generation; in both cases, primitives are identified and drawn based on the vertex stream of the 3D drawing object supplied to the input assembler process IA.

[0229] Figure 14(d) shows a drawing operation using commands such as DRAW and DRAWD, in which pixel data of the drawing object is generated in the rasterizer process RS without performing coordinate transformation. This operation is typically used when displaying a two-dimensional 2D drawing object on a display screen, where the contour lines can be identified by the vertex stream.

[0230] Figures 14(e) and (f) show the operation modes when accumulating vertex data in the vertex buffer VB, and are divided into (e) when coordinate transformation processing is performed and (f) when coordinate transformation processing is not performed. These operations are performed by the DRAW command and the DRAWD command. Next, Figure 14(g) shows the operation mode that uses the vertex data accumulated in the vertex buffer VB, and is performed by the DRAWI command.

[0231] As described above, the drawing pipeline of this embodiment can be used in various ways, but for example, playback of 2D still images and streaming videos (S-stream, IPB-stream, IP-stream) can be achieved simply by drawing sprites, and as mentioned above, the playback operation is realized in the operating mode shown in Figure 14(b).

[0232] As explained above, the display analyzer determines the drawing commands in the display list DL and forwards each to the processing block of the pipeline process corresponding to the drawing command. The forwarded drawing commands are then first placed into the waiting queue of each pipeline process, and the processing corresponding to the drawing commands is executed in the order they were placed.

[0233] However, since the operation of the data transfer circuit 70 that transfers the display list DL is significantly faster than the progress of this rendering pipeline, if, for example, you want to display multiple 3D rendering objects on the screen, and also display other 2D rendering objects, the execution of the SPRITE command in the render process RO will be delayed for a long time.

[0234] In other words, processing the coordinate transformation matrix for 3D drawing objects takes a considerable amount of time, so a large number of SPRITE commands accumulate in the waiting queue, such as in the RO process. However, in this embodiment, as explained earlier, drawing commands are waited to be submitted until the waiting queue is empty (stall state), and furthermore, the number of stages in the waiting queue of the downstream process is the same as or greater than the number of stages in the waiting queue of the upstream process, so the operation of the commands listed in the display list DL is smoothly realized.

[0235] Furthermore, drawing commands that have been migrated from the waiting queue will also be held in a stall state until the necessary start conditions are met, so inconsistent drawing operations such as rewriting the index space will not occur.

[0236] Having explained the circuit configuration, we will now describe the control operation by the CPU circuit 51. As explained earlier, when the power is turned on, a reset period occurs in which the system reset signal SYS maintains an L level for a predetermined time, prior to the start of the control operation.

[0237] During this reset period, first, one or two oscillator circuits that control the operation of the integrated performance circuit 52 and the built-in CPU circuit 51 begin oscillating and wait for the oscillation frequency of each system clock to stabilize. Next, the internal circuits of the composite chip 50 are initialized in synchronization with each system clock, and predetermined default values ​​are set in the performance control register RGij and the operation control register REG. Hereinafter, in this specification, this operation will be referred to as a hardware reset to distinguish it from the software reset described later.

[0238] Once this hardware reset period ends, the built-in CPU circuit 51's performance control CPU 57 executes the boot program stored in the external ROM 55 and transfers the control program and control data from the external ROM 55 to the extended RAM 54. The performance control CPU 57 then continues its control operations based on the control program transferred to the extended RAM 54.

[0239] The control operations performed by the performance control CPU 57 are as shown in Figure 15 and consist of a main process (a) consisting of initial processing and subsequent steady-state processing, a timer interrupt process (b) that is activated every 1 ms, a VBLANK interrupt process (c) that is activated when a VBLANK signal is output from the integrated performance circuit 52 at the start of the vertical retrace period of the display device DS, and a receive interrupt process (not shown) for receiving the control command CMD. The VBLANK signal is generated every 1 / 60 second.

[0240] As shown in Figure 15(b), the timer interrupt processing acquires sensor signals to determine the motor position, etc. (ST20), and starts or progresses the lamp effect or motor effect when necessary (ST21). In this embodiment, the lamp effect is realized by the operation of the effect control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor effect is realized by the operation of the effect control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. Furthermore, in the VBLANK interrupt processing, which is activated by receiving the VBLANK signal, the interrupt counter VCNT is incremented and the processing ends, as shown in Figure 15(c) (ST25).

[0241] First, let's explain the main process when the preloader 72 is not used. As shown in Figure 15(a), the initial setup process (ST1) is executed first, and appropriate setting values ​​are set in the performance control register RGij of the integrated performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0242] The setting process for the performance control register RGij includes allocating appropriate virtual work areas (AAC area, page area, arbitrary area) in VRAM 53 and extended RAM 54 (see Figures 6(a) and 6(b)), and allocating index space essential for game control operations, such as the frame buffer FB. As explained earlier, the frame buffer FB consists of a first buffer with index number N1 and a second buffer with index number N2.

[0243] The starting address of the shared area allocated in VRAM 53 (used as the AAC area in this embodiment) is set in units of 4k bytes (the lower 15 bits are zero), and the area size is allocated in integer multiples of 4k bytes. The page area allocated in extended RAM 54 is set in units of 32k bytes (the lower 18 bits are zero), and the area size is allocated in integer multiples of 32k bytes.

[0244] Furthermore, the setting value in the operation control register REG includes operation parameters related to the watchdog timer WDT58, which include an operation start instruction and a counter value. In this embodiment, the WDT58 is configured to downcount from an initial value (counter value), and the WDT58 is prevented from starting by reloading the counter value before an underflow occurs where the count value becomes zero.

[0245] On the other hand, if the count value underflows, a WDT reset request is generated, and the WDT58 starts up, resulting in a software reset state. In standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG, except for a predetermined register, return to their initial values ​​(default values), and the WDT58 stops operating. The only register whose value is exceptionally maintained is the register indicating the operating status of the WDT.

[0246] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether or not to initialize the internal circuit, and (2) whether or not to initialize the system clock circuit if initialization is performed, can be arbitrarily selected by setting a corresponding value in a predetermined operation control register REG during the initial setup process after a hardware reset.Therefore, in this embodiment, based on the setting value in the predetermined operation control register REG, when a software reset occurs, the game operation is resumed from the process of step ST1 without initializing the internal circuit.

[0247] Thus, unlike the configurations in prior art documents 1 and 2, this embodiment has the advantage that even if the WDT58 underflows, it does not enter a hardware reset state, allowing for a quick resumption of gameplay. Furthermore, since the WDT stops operating after a software reset, there is no risk of the software reset operation being repeatedly triggered.

[0248] Once the initial setup process (ST1), which includes the above processes, is completed, the intermittently executed steady-state processes (ST2~ST10) begin. As shown in step ST2 in Figure 15(a), the steady-state process starts when the interrupt counter VCNT becomes VCNT≧2, so the operating period (operating cycle) δ of the steady-state process is 1 / 30 seconds, corresponding to the operating period of the VBLANK signal (1 / 60 seconds).

[0249] Then, in step ST3, after resetting the interrupt counter VCNT, it is determined whether the conditions for starting steady-state operation are met. Specifically, a predetermined display control register RGij, which indicates the operating state of the drawing circuit 74, is accessed via READ, and it is determined at this timing whether the drawing circuit 74 has finished the drawing operation based on the display list DL of the previous operation cycle. In addition, it is determined whether the memory access period of the drawing circuit 74 in the drawing operation of the previous operation cycle has exceeded the timeout period set in the time setting register TO, by checking the ON / OFF state of a predetermined abnormal flag.

[0250] Then, because the memory access of the drawing circuit 74 took an abnormally long time, if the abnormal flag is ON, even if the drawing circuit 74 has finished its drawing operation, it is determined that the conditions for starting operation have not been met, and the process proceeds to the performance command analysis process in step ST9.

[0251] Steps ST4 to ST8 are skipped because, given the unusually long memory access of the drawing circuit 74, there is a possibility that normal image data is not being generated, including bit corruption in the instruction commands, and this is to avoid an unreasonable screen display.

[0252] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21. If a control command CMD has been received, the control command CMD is analyzed and the necessary processing is executed. The necessary processing includes the preparation process for starting a new variation performance based on a control command CMD that instructs the start of a variation performance, and the start of error notification based on a control command CMD that indicates an error has occurred.

[0253] Next, the watchdog timer WDT58 is prevented from starting by reloading the counter value (ST10). As explained earlier, even in the event of an abnormality where the watchdog timer 58 starts, the composite chip 50 in this embodiment enters a software reset state, which is different from a hardware reset. With this, the operation of this cycle is complete, and the process moves to step ST2, waiting for the next VBLANK interrupt.

[0254] The above describes the case when the conditions for starting operation are not met. Normally, after the determination process in step ST3, the display circuit 71 identifies the image data to be read based on the setting value of a predetermined display register RGij and starts the operation of the display circuit (ST4). As explained earlier, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the setting value of a predetermined display register RGij so that they switch in a toggle manner.

[0255] Specifically, the index numbers N1 / N2 of the first or second buffer, which were identified as the "write area" by the display list DL of the previous operation cycle, are set. When this step ST4 is executed, the "write area" of the previous operation cycle becomes the "read area" of the current operation cycle, so the display circuit 71 outputs the image data completed by the drawing circuit 74 in the previous operation cycle to the display device DS. In other words, the processing of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0256] Once the processing of step ST4, which has the significance described above, is completed, the performance control CPU 57 then completes the display list DL, which identifies the image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see Figure 8).

[0257] The display list DL is, in principle, created each time with its contents changed for each operation cycle, but the beginning area of ​​the display list DL contains a command that defines the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double buffer structure where the index numbers are N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternately specifies the frame buffer FB with index number N1 and the frame buffer FB with index number N2, thereby cycling the "write area".

[0258] The performance control CPU 57 then issues the completed display list DL to the integrated performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN, which centrally manages image performance, sound performance, lamp performance, and motor performance (ST7), and if it is the appropriate performance timing, issues the sound command list VC to the sound processing unit SND to start or advance the sound performance (ST8).

[0259] Regarding motor and lamp effects, when the start time for the effect managed by the effect scenario EN is reached, the timer interrupt processing (Figure 15(b)) executes the motor or lamp effect based on the corresponding motor drive data or lamp drive data. The processing of steps ST9 to ST10 following step ST8 is as described above.

[0260] Figures 16(a) and 16(b) are flowcharts showing the specific details of the display list DL issuance process (ST6), and Figure 16(c) is a schematic diagram showing the operation of the DL issuance process (ST6). As explained with respect to Figure 9, the display list DL issuance process has two cases: one where the CPU register port PORT is accessed in 32-bit units (Figure 9(a)) and one where it is not accessed via the CPU register port PORT (Figure 9(b)). The operation details of each case are shown in Figure 16.

[0261] First, to explain Figure 16(a), the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and also sets the total size of the data to be transferred to a predetermined transfer register RGij (ST30).

[0262] Here, the display list DL differs in content for each operation cycle, but is issued after being terminated by a predetermined termination command EODL. In this embodiment, the instruction command used for the display list DL, including the termination command EODL, is one word or multiple words (=N*32 bits), so no data size adjustment processing is required. Therefore, the total size of the transfer data (display list DL) set in the transfer register RGij will be any value that is an integer multiple of 32 bits.

[0263] Next, the performance control CPU 57 sets the number of writes corresponding to the total size of the data to be transferred to the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the instructions to start the operation of the drawing circuit 74 and the data transfer circuit 70 are realized by setting predetermined drawing registers RGij and transfer registers RGij, respectively.

[0264] Next, the performance control CPU 57, while confirming that the 130-stage CPU data FIFO circuit is not full, writes the configuration data for the display list DL to the CPU register port PORT in 32-bit units (ST35). Then, it continues the writing operation while decrementing the management counter CN (ST36, ST37).

[0265] As explained earlier, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 are configured to receive data in 1024-bit units. Therefore, in principle, when 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data is transferred to the data relay unit CH2. However, when the value set in the transfer register RGij (the total size of the display list DL, which is the data to be transferred) is reached, the accumulated data in the CPU data FIFO circuit at that point is transferred to the data relay unit CH2.

[0266] The above process completes the DL issuance process (ST6) via the CPU register port PORT. Next, Figure 16(b) shows an embodiment in which the data transfer circuit 70 reads the display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and sets the total size of the data to be transferred and the starting address of the list buffer BUF in a predetermined transfer register RGij (ST41).

[0267] Here, regarding the list buffer BUF set in the built-in RAM 59, its starting address must be set in 8-bit units, so as explained earlier, the starting address of the DL buffer BUF has zeros in the lower 7 bits. Note that this address condition applies not only to the starting address of the list buffer BUF that stores the display list DL, but also to the starting address of the list buffer BUF that stores the voice command list VC.

[0268] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). These operation instructions are also realized by setting predetermined drawing registers RGij and transfer registers RGij, respectively. Then, the data transfer process starts with these operation instructions, and the data transfer circuit 70 finishes its operation upon completion of the transfer of a predetermined size of data. Therefore, after the processing in step ST43, the performance control CPU 57 can immediately proceed to another process, which is the display list issuance process (ST6).

[0269] In this case as well, when the amount of data to be transferred reaches the value set in the transfer register RGij (the total size of the display list DL which is the data to be transferred), the data accumulated in the CPU data FIFO circuit at that point is transferred to the data relay unit CH2.

[0270] The process of issuing a display list DL has been explained above based on Figures 16(a) and 16(b). However, when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as in Figures 16(a) and 16(b) (see Figures 9(f) and 9(g)).

[0271] In other words, the voice command list VC, which lists the voice commands, is issued after being terminated with a predetermined termination command EOSC. Since each voice command, including the termination command EOSC, is one or more words (=N*32 bits), no data size adjustment processing is required.

[0272] The above describes the case where the preloader 72 is not used. The main processing when the preloader 72 is used is shown in Figure 17(a). The processing content shown in Figure 17(a) is similar to the processing content shown in Figure 15(a).

[0273] However, as shown in Figure 17(a), this differs from the process in Figure 15(a) in that (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 instead of the drawing circuit 74 (ST60), and (b) although this display list DL is rewritten by the preloader 72 to become a rewritten list DL', the rewritten list DL' from the previous operation cycle is made to be acquired by the drawing circuit 74 prior to the processing in step ST5 (ST41).

[0274] In the process shown in Figure 17(a), the issuance process (ST60) that issues the display list DL to the preloader 72 is almost the same as in Figures 16(a) and 16(b), except that the destination is the preloader 72. The general operation is as shown in Figures 9(d) and 9(e), where the data relay unit CH2 changes to the data relay unit CH3 (data transfer channel CH3) in response to the change in the destination to the preloader 72, but otherwise it is the same as the operation in Figures 16(a) and 16(b), and the corresponding operations are shown in Figures 17(b) and 17(c).

[0275] On the other hand, the process of causing the drawing circuit 74 to acquire the rewrite list DL' (ST41 in Figure 17) is shown in Figure 17(d). As shown in Figure 9(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see Figure 6(a)).

[0276] In step ST41 of Figure 17, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Figure 17(d)). Next, it sets the total size of the rewrite list DL', which is the transfer data, and the starting address of the preload buffer in which the rewrite list DL' is stored to a predetermined transfer register RGij (ST51).

[0277] Since the starting address in VRAM53 needs to be set in 32-bit units, the starting address of the preload buffer for storing the rewrite list DL’ must have its lower 31 bits set to zero. In this embodiment, a preload buffer is secured at a position that meets this condition.

[0278] Next, the production control CPU57 starts the operation of the drawing circuit 74 (ST52) and starts the operation of the data transfer circuit 70 (ST53). These operation instructions are each realized by setting processes to predetermined drawing registers RGij and transfer registers RGij. Then, a data transfer process is started by this operation instruction, and when the data transfer is completed, the data transfer circuit 70 ends its operation.

[0279] Although one embodiment of the present invention has been described above, the specific description content does not particularly limit the present invention and can be changed as appropriate. For example, in the above embodiment, when the memory access cycle of the drawing circuit 74 or the decode processing time is prolonged, a configuration for detecting such an abnormality by flag polling processing has been described, but it is of course possible to utilize an exception interrupt processing.

[0280] FIG. 15(d) shows a configuration example in such a case. When there is a drawing abnormality interrupt, only the drawing circuit 74 is individually reset (ST23), and after resetting the operation parameters necessary for the operation of the drawing circuit 74, the stack area is appropriately released (ST24), and the process proceeds to the process of step ST9.

[0281] Although the embodiments have been described in detail above, the specific description content does not limit the present invention in any way. For the sake of convenience, a pachinko machine has been described, but the present invention can also be suitably applied to other gaming machines such as a spinning reel gaming machine.

Description of Reference Numerals

Claims

[Claim 1] A CPU means that generates first information that identifies image effects by a display device, and second information that identifies sound effects, A gaming machine equipped with a transfer means that transfers first information to a first circuit and second information to a second circuit, with a predetermined transfer size as one unit, The first information and / or the second information is composed of a list of instruction commands that are an integer N times (N ≥ 1) of the base size, and the transfer size is an integer M times (M ≥ 1) of the base size, so that the number of instruction commands in the first information and / or the second information can be any number. The gaming machine is characterized in that the CPU means is configured to write the configuration data of the first information and the configuration data of the second information to a predetermined write port at predetermined write sizes.

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