Doherty amplifier

Abstract

To provide a Doherty amplifier capable of suppressing a decrease in a saturation output power due to manufacturing variations.SOLUTION: A Doherty amplifier according to the present disclosure includes: an input terminal; an output terminal; a first main transistor provided in a first signal path connecting the input terminal and the output terminal; a first peak transistor provided in a second signal path connecting the input terminal and the output terminal; a first matching circuit provided in the first signal path; and a second matching circuit provided in the second signal path. The first main transistor and the first peak transistor are formed in a first semiconductor chip, and the first matching circuit and the second matching circuit are formed in a second semiconductor chip.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a Doherty amplifier.

Background Art

[0002] Patent Document 1 discloses a Doherty amplifier in which two-stage main transistors are integrated on one semiconductor chip, two-stage peak transistors are integrated on one semiconductor chip, and these semiconductor chips are mounted on a resin substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an amplifier, it is important to sufficiently reduce the characteristic variations due to manufacturing variations in order to improve the yield. Generally, manufacturing variations occur for each lot, each wafer, or each semiconductor chip. In a transistor, manufacturing variations are caused, for example, by the parasitic capacitance Cds between the source and drain. In a matching circuit, manufacturing variations are caused, for example, by a MIM (Metal-Insulator-Metal) capacitance.

[0005] ​

[0006] Patent Document 1 describes a case where, due to variations in semiconductor manufacturing, for example, the Cds and MIM capacitance in the main transistor may vary towards higher values, while the Cds and MIM capacitance in the peak transistor may vary towards lower values. When capacitance increases, the passphase lags, and when capacitance decreases, the passphase advances. As a result, in the above case, the difference between θmain and θpeak becomes very large, which may lead to a decrease in saturated output power.

[0007] This disclosure aims to provide a Doherty amplifier that can suppress the decrease in saturation output power due to manufacturing variations. [Means for solving the problem]

[0008] The Doherty amplifier according to this disclosure includes an input terminal, an output terminal, a first main transistor provided in a first signal path connecting the input terminal and the output terminal, and a first peak transistor provided in a second signal path connecting the input terminal and the output terminal. A second main transistor is provided in the first signal path on the output terminal side of the first main transistor, and a second peak transistor is provided in the second signal path on the output terminal side of the first peak transistor, The device comprises a first matching circuit provided in the first signal path and a second matching circuit provided in the second signal path, and includes the first main transistor and the first peak transistor. and the preceding second main transistor and the preceding second peak transistor The first matching circuit and the second matching circuit are formed on the second semiconductor chip. The first matching circuit is provided between the first main transistor and the second main transistor in the first signal path, and the second matching circuit is provided between the first peak transistor and the second peak transistor in the second signal path. ru. [Effects of the Invention]

[0009] In the Doherty amplifier according to this disclosure, the first main transistor and the first peak transistor are formed on a first semiconductor chip, and the first matching circuit and the second matching circuit are formed on a second semiconductor chip. This allows for similar variations in the first main transistor and the first peak transistor. Furthermore, similar variations can be introduced in the first matching circuit and the second matching circuit. Consequently, the phase difference between the first signal path and the second signal path can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] It is a plan view of the Doherty amplifier according to Embodiment 1. [Figure 2] It is a circuit diagram of the Doherty amplifier according to Embodiment 1. [Figure 3] It is a diagram for explaining the passing phase of the Doherty amplifier. [Figure 4] It is a plan view of the Doherty amplifier according to the first comparative example. [Figure 5] It is a plan view of the Doherty amplifier according to the second comparative example. [Figure 6] It is a circuit diagram of the Doherty amplifier according to the second comparative example. [Figure 7] It is a diagram showing the calculation result of the saturation output power of the Doherty amplifier according to the comparative example. [Figure 8] It is a diagram showing the calculation result of the saturation output power of the Doherty amplifier according to Embodiment 1. [Figure 9] It is a diagram showing the inter-stage matching circuit according to the first modification example of Embodiment 1. [Figure 10] It is a diagram showing the inter-stage matching circuit according to the second modification example of Embodiment 1. [Figure 11] It is a diagram showing the inter-stage matching circuit according to the third modification example of Embodiment 1. [Figure 12] It is a diagram showing the inter-stage matching circuit according to the fourth modification example of Embodiment 1. [Figure 13] It is a plan view of the Doherty amplifier according to Embodiment 2. [Figure 14] It is a plan view of the Doherty amplifier according to the modification example of Embodiment 2. [Figure 15] It is a plan view of the Doherty amplifier according to Embodiment 3. [Figure 16] It is a plan view of the Doherty amplifier according to Embodiment 4. [Figure 17] It is a plan view of the Doherty amplifier according to the modification example of Embodiment 4. [Figure 18] It is a plan view of the Doherty amplifier according to Embodiment 5. [Figure 19] It is a diagram for explaining the structure of the transistor.

Best Mode for Carrying Out the Invention

[0011] The Doherty amplifier according to each embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0012] Embodiment 1. FIG. 1 is a plan view of a Doherty amplifier 100 according to Embodiment 1. FIG. 2 is a circuit diagram of the Doherty amplifier 100 according to Embodiment 1. The Doherty amplifier 100 is used, for example, in wireless communication. The Doherty amplifier 100 includes an input terminal 1 and an output terminal 2. A first main transistor 40 is provided in a first signal path P1 connecting the input terminal 1 and the output terminal 2. In the first signal path P1, a second main transistor 42 is provided on the output terminal 2 side of the first main transistor 40. A first peak transistor 41 is provided in a second signal path P2 connecting the input terminal 1 and the output terminal 2. In the second signal path P2, a second peak transistor 43 is provided on the output terminal 2 side of the first peak transistor 41.

[0013] The first peak transistor 41 and the first main transistor 40 are formed on a semiconductor chip 20. The second peak transistor 43 and the second main transistor 42 are formed on a semiconductor chip 22. That is, the first peak transistor 41 and the first main transistor 40 are formed on the same semiconductor substrate. Also, the second peak transistor 43 and the second main transistor 42 are formed on the same semiconductor substrate.

[0014] In the first signal path P1, a first stage matching circuit 50 is provided between the first main transistor 40 and the second main transistor 42. In the second signal path P2, a second stage matching circuit 51 is provided between the first peak transistor 41 and the second peak transistor 43. The first stage matching circuit 50 and the second stage matching circuit 51 are formed on the semiconductor chip 21. In other words, the first stage matching circuit 50 and the second stage matching circuit 51 are formed on the same semiconductor substrate.

[0015] The Doherty amplifier 100 is integrated on a resin substrate 10. The input terminal 1 is connected to a circuit 30 formed on the resin substrate 10. The circuit 30 consists of a distribution circuit 70, an input delay line 80, an input matching circuit 90 for the main transistor, and an input matching circuit 91 for the peak transistor. The circuit 30 is connected to the gate terminal of the first main transistor 40 and the gate terminal of the first peak transistor 41 via bonding wires 60 and 64, respectively.

[0016] Semiconductor chips 20, 21, and 22 are die-bonded to the die pad 11. Semiconductor chips 20 and 21 are connected by bonding wires 61 and 65. Semiconductor chips 21 and 22 are connected by bonding wires 62 and 66. The drain terminals of the second main transistor 42 and the second peak transistor 43 are connected to a circuit 31 formed on the resin substrate 10 by bonding wires 63 and 67, respectively. Circuit 31 consists of a combining circuit 71, an output delay line 81, an output matching circuit 92 for the main transistors, and an output matching circuit 93 for the peak transistors. Circuit 31 is connected to output terminal 2.

[0017] The semiconductor chips 20 and 22 are formed from, for example, a SiC substrate. The first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 are, for example, GaN-HEMT (High Electron Mobility Transistors). The first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 have parasitic capacitance Cds between the source and drain.

[0018] The semiconductor chip 21 is formed from an inexpensive substrate such as GaAs or Si. For example, a MIM capacitor is integrated into the semiconductor chip 21. The first interstage matching circuit 50 and the second interstage matching circuit 51 consist of, for example, two parallel capacitors, one series capacitor, and one series inductor. The first interstage matching circuit 50 and the second interstage matching circuit 51 may be designed to take into account the parasitic inductance of the bonding wires 61, 62, 65, and 66.

[0019] The resin substrate 10 is formed from a material such as FR4. The thickness of the resin substrate 10 is 200 to 500 μm. By making the resin substrate 10 thinner, the thermal resistance of the transistor can be reduced. On the other hand, by making the resin substrate 10 thicker, multilayer wiring becomes possible. This increases the integration density of the circuit, enabling miniaturization and cost reduction. Note that the drain bias circuit and gate bias circuit are omitted in Figures 1 and 2.

[0020] High-efficiency, low-distortion Doherty amplifiers are used, for example, as transmit power amplifiers in communication base stations. In the Doherty amplifier 100, a main transistor biased to Class AB or Class B and a peak transistor biased to Class C are combined in parallel using a λ / 4 transmission line. The λ / 4 transmission line is placed at the output of one amplifier and the input of the other amplifier. The λ / 4 transmission line corresponds to the input delay line 80 and the output delay line 81.

[0021] Under high signal input conditions, the main transistor and peak transistor operate similarly and are combined in phase. This results in characteristics similar to a two-component amplifier, enabling high saturated output power. On the other hand, under low signal input conditions, only the main transistor operates, and the λ / 4 line connected to the output side of the main transistor functions as an impedance inverter. This allows for high efficiency due to the high load impedance. Therefore, the Doherty amplifier 100 achieves high efficiency over a wide output power range.

[0022] Figure 3 illustrates the pass phase of a Doherty amplifier. Figure 3 shows the pass phase at each end face of a two-stage Doherty circuit. Let θmain be the pass phase of the entire first signal path P1 on the main transistor side. θMI is the pass phase from the input signal terminal to the input terminal of the first-stage transistor chip. θM1 is the pass phase of the first-stage transistor chip. θM2 is the pass phase of the interstage matching circuit. θM3 is the pass phase of the final-stage transistor chip. θMO is the pass phase from the output terminal of the final-stage transistor to the combination point. θmain is the sum of θMI, θM1, θM2, θM3, and θMO.

[0023] Similarly, let θpeak be the pass-through phase of the entire second signal path P2 on the peak transistor side. θPI is the pass-through phase from the input signal terminal to the input terminal of the first stage transistor chip. θP1 is the pass-through phase of the first stage transistor chip. θP2 is the pass-through phase of the interstage matching circuit. θP3 is the pass-through phase of the final stage transistor chip. θPO is the pass-through phase from the output terminal of the final stage transistor to the combination point. θmain is the sum of θPI, θP1, θP2, θP3, and θPO.

[0024] In a Doherty amplifier, for the signals amplified in the first signal path P1 and the signals amplified in the second signal path P2 to be combined without loss, θmain and θpeak must be the same. If there is a phase difference between the two, a combination loss occurs, and the saturation output power of the Doherty amplifier decreases.

[0025] Next, a comparative example of this embodiment will be described. As a Doherty amplifier, for example, there is an MMIC (Monolithic Microwave Integrated Circuit) that integrates most of a two-stage Doherty amplifier circuit onto a single semiconductor chip. In the millimeter-wave band, the circuit size is generally not negligible compared to the wavelength. For this reason, it is necessary to construct the Doherty amplifier as a distributed-parameter circuit. With an MMIC, it is possible to manufacture with precise dimensional accuracy. It is also possible to miniaturize the Doherty amplifier. On the other hand, when using high-performance semiconductor substrates such as GaN on SiC, the chip area of ​​an MMIC is large, which may increase manufacturing costs.

[0026] Figure 4 is a plan view of the Doherty amplifier 800 according to the first comparative example. In the Doherty amplifier 800, the first main transistor 40, the first interstage matching circuit 50, and the second main transistor 42 are each integrated on separate semiconductor chips 20a to 22a. In addition, the first peak transistor 41, the second interstage matching circuit 51, and the second peak transistor 43 are each integrated on separate semiconductor chips 20b to 22b. In this case, the matching circuit can be integrated on an inexpensive GaAs or Si substrate, and only the transistors can be integrated on a high-performance semiconductor substrate. This makes it possible to reduce costs while maintaining performance in low-frequency bands such as the L band and S band.

[0027] Figure 5 is a plan view of the Doherty amplifier 900 according to the second comparative example. Figure 6 is a circuit diagram of the Doherty amplifier 900 according to the second comparative example. In the Doherty amplifier 900, the first main transistor 40, the interstage matching circuit 50a, and the second main transistor 42 are integrated on a single semiconductor chip 23. In addition, the first peak transistor 41, the interstage matching circuit 51a, and the second peak transistor 43 are integrated on a single semiconductor chip 24. This configuration also allows for miniaturization of the Doherty amplifier 900.

[0028] In Doherty amplifiers 800 and 900, due to semiconductor manufacturing variations, the Cds of the transistor and the MIM capacitance of the matching circuit may increase simultaneously in the first signal path P1, and decrease simultaneously in the second signal path P2. When capacitance increases, the pass phase lags, and when capacitance decreases, the pass phase leads. In other words, θM1, θM2, and θM3 all become larger, and θP1, θP2, and θP3 all become smaller, potentially resulting in a very large pass phase difference Δ between θmain and θpeak. In this case, the saturation output power decreases.

[0029] In contrast, in this embodiment, the final stage transistors, interstage matching circuits, and first stage transistors are each integrated onto a single semiconductor chip. Generally, variations within the same chip are similar. Therefore, θM1-θP1, θM2-θP2, and θM3-θP3 will be close to zero even if there are variations in Cds or MIM capacitance. Consequently, the pass-through phase difference Δ due to manufacturing variations can be suppressed, and the decrease in saturated output power can be suppressed. Furthermore, in this embodiment, since the Doherty amplifier 100 is composed of multiple semiconductor chips, manufacturing costs can be reduced compared to an MMIC.

[0030] Next, we will explain the calculation results of the variation in the RF characteristics of the Doherty amplifier. Figure 7 shows the calculation results of the saturated output power of the Doherty amplifier 900 according to the comparative example. Figure 8 shows the calculation results of the saturated output power of the Doherty amplifier 100 according to Embodiment 1. In the Doherty amplifier 900 according to the comparative example, it was assumed that the inductance of the bonding wires connecting the semiconductor chips is integrated on the semiconductor chips. The variation elements are the Cds of the first main transistor 40, the second main transistor 42, the first peak transistor 41, and the second peak transistor 43, and the MIM capacitance of the interstage matching circuit. Calculations were performed for the case where each variation element fluctuates by ±15% from the design center.

[0031] In Figures 7 and 8, a positive sign indicates a variation in Cds and MIM capacitance within the chip to a larger value, a negative sign indicates a variation to a smaller value, and the symbol "typ" indicates the center value. In the Doherty amplifier 900, which is a comparative example, the pass phase difference is 0 degrees and the saturated output power is 47.5 dBm at the design center. When both the Cds and MIM capacitance of semiconductor chips 23 and 24 fluctuate to positive or negative values, the pass phase difference is 20 degrees and the fluctuation in saturated output power is limited to a decrease of 0.2 dB. However, when the variations in semiconductor chips 23 and 24 are in opposite directions, the pass phase difference becomes 102 degrees or more, and the saturated output power decreases by 0.9 dB or more.

[0032] On the other hand, in the Doherty amplifier 100 according to this embodiment, even when considering all combinations of variations, the maximum pass phase difference is 22 degrees, and the maximum decrease in saturated output power is 0.3 dB. Thus, it can be seen that in this embodiment, fluctuations in the pass phase difference Δ are suppressed, and the decrease in saturated output power can be suppressed.

[0033] As a variation of this embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be formed on separate semiconductor chips. In this case as well, by integrating the first-stage transistors and the final-stage transistors onto separate semiconductor chips, fluctuations in the pass-through phase difference Δ can be suppressed compared to the Doherty amplifier 900.

[0034] Alternatively, the second main transistor 42 and the second peak transistor 43 may be formed on separate semiconductor chips. In this case as well, the first main transistor 40 and the first peak transistor 41 are formed on one semiconductor chip 20, and the first interstage matching circuit 50 and the second interstage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the pass-through phase difference Δ.

[0035] Similarly, the first main transistor 40 and the first peak transistor 41 may be formed on separate semiconductor chips. In this case as well, the second main transistor 42 and the second peak transistor 43 are formed on one semiconductor chip 22, and the first interstage matching circuit 50 and the second interstage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the pass-through phase difference Δ. Thus, depending on the allowable pass-through phase difference Δ, some of the circuits in Figure 1 may be formed on separate chips.

[0036] Furthermore, in this embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 are formed on a single semiconductor chip 21. However, this is not limited to this configuration; the input matching circuits for the main transistor and the peak transistor may also be formed on a single semiconductor chip. Similarly, the output matching circuits for the main transistor and the peak transistor may also be formed on a single semiconductor chip.

[0037] The configurations of the first interstage matching circuit 50 and the second interstage matching circuit 51 are not limited, and other configurations are acceptable as long as they have similar functions to the circuit shown in Figure 2. Figure 9 shows an interstage matching circuit according to the first modified example of Embodiment 1. Figure 10 shows an interstage matching circuit according to the second modified example of Embodiment 1. Figure 11 shows an interstage matching circuit according to the third modified example of Embodiment 1. Figure 12 shows an interstage matching circuit according to the fourth modified example of Embodiment 1. As shown in Figures 9 to 12, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be, for example, a π-type circuit, a T-type circuit, or a combination thereof. Furthermore, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be different circuits. For example, the first interstage matching circuit 50 may be the circuit shown in Figure 9, and the second interstage matching circuit 51 may be the circuit shown in Figure 10.

[0038] The configuration of circuit 30 is not limited and only needs to have the same function as the circuit shown in Figure 2. The same applies to circuit 31. Furthermore, the Doherty amplifier 100 may be a symmetrical Doherty amplifier or an asymmetrical Doherty amplifier in which the total gate width differs between the main transistor and the peak transistor. The die pad 11 is not limited to being on the resin substrate 10, but may be formed on the resin substrate 10 and provided in an opening where the heat sink is exposed.

[0039] The modifications described above can be appropriately applied to the Doherty amplifier according to the following embodiment. Since the Doherty amplifier according to the following embodiment has many similarities with Embodiment 1, the explanation will focus on the differences from Embodiment 1.

[0040] Embodiment 2. Figure 13 is a plan view of the Doherty amplifier 200 according to Embodiment 2. In this embodiment, the first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 are formed on a semiconductor chip 220. In addition, the input matching circuit 52 for the main transistors and the input matching circuit 53 for the peak transistors are formed on the same semiconductor chip 221 as the first interstage matching circuit 50 and the second interstage matching circuit 51. The input matching circuits 52 and 53 are parts of the input matching circuits 90 and 91, respectively. The input matching circuits 52 and 53 are connected to the circuit 30 via bonding wires 68 and 69. The other configurations are the same as those of Embodiment 1.

[0041] The first main transistor 40 and the first peak transistor 41 of the first stage are positioned outside the second main transistor 42 and the second peak transistor 43 of the final stage. In addition, the input matching circuits 52 and 53 are positioned outside the first stage matching circuit 50 and the second stage matching circuit 51.

[0042] In this embodiment as well, the pass-through phase difference Δ due to manufacturing variations can be suppressed, and the decrease in saturated output power can be suppressed. Furthermore, in this embodiment, the number of chips can be reduced compared to Embodiment 1, so the Doherty amplifier 200 can be further miniaturized.

[0043] Figure 14 is a plan view of a modified Doherty amplifier 300 according to Embodiment 2. The first main transistor 40 and the first peak transistor 41 of the first stage may be placed inside the second main transistor 42 and the second peak transistor 43 of the final stage. In this case, the input matching circuits 52 and 53 are placed inside the first interstage matching circuit 50 and the second interstage matching circuit 51. In this modified configuration, the final stage transistors, which tend to become hot during operation, can be placed far apart. This suppresses the rise in channel temperature of the final stage transistors, enabling operation at high ambient temperatures.

[0044] Embodiment 3. Figure 15 is a plan view of the Doherty amplifier 400 according to Embodiment 3. In this embodiment, the second peak transistor 43 and the first main transistor 40 are formed on semiconductor chip 420, and the first peak transistor 41 and the second main transistor 42 are formed on semiconductor chip 422. In this embodiment, the signal paths of the main transistors and peak transistors are in opposite directions on the semiconductor chip.

[0045] Furthermore, the gate widths of the first main transistor 40 and the first peak transistor 41 may be the same, and the gate widths of the second main transistor 42 and the second peak transistor 43 may also be the same.

[0046] The signal from input terminal 1 is input to the first peak transistor 41 via the distribution circuit 101 and the input matching delay circuit 102. The input matching delay circuit 102 has the functions of both an input matching circuit and a delay circuit. The signal from input terminal 1 is also input to the first main transistor 40 via the distribution circuit 101 and the input matching circuit 103. The functions of the distribution circuit 101, the input matching delay circuit 102, and the input matching circuit 103 are the same as those of circuit 30.

[0047] The signal from the second main transistor 42 is output from output terminal 2 via the output matching delay circuit 104 and the combining circuit 106. The output matching delay circuit 104 has the functions of both an output matching circuit and a delay circuit. The signal from the second peak transistor 43 is output from output terminal 2 via the output matching circuit 105 and the combining circuit 106. The functions of the output matching delay circuit 104, the output matching circuit 105, and the combining circuit 106 are the same as those of circuit 31.

[0048] In this embodiment, even if there are variations in Cds or MIM capacitance, θM3-θP1, θM2-θP2, and θM1-θP3 can be suppressed. Therefore, the pass-through phase difference Δ due to manufacturing variations can be suppressed, and the decrease in saturated output power can be suppressed.

[0049] Furthermore, the transistor sizes of the first main transistor 40 and the first peak transistor 41 are the same, and the transistor sizes of the second main transistor 42 and the second peak transistor 43 are the same. Therefore, semiconductor chips of the same type or specifications can be used as semiconductor chip 420 and semiconductor chip 422. In other words, semiconductor chip 420 and semiconductor chip 422 can be obtained from the same wafer.

[0050] By using adjacent semiconductor chips on the wafer, for example, as semiconductor chip 420 and semiconductor chip 422, variations in semiconductor manufacturing between chips can be further suppressed. Furthermore, while two types of semiconductor chips 20 and 22 were required in Embodiment 1, only one type of semiconductor chip 420 and 422 is needed in this embodiment. Therefore, productivity can be increased.

[0051] As a variation of this embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be formed on separate semiconductor chips. In this case as well, by integrating the first main transistor 40 and the second peak transistor 43, and the second main transistor 42 and the first peak transistor 41, onto a single semiconductor chip, fluctuations in the pass phase difference Δ can be suppressed compared to the Doherty amplifier 900.

[0052] Alternatively, the second main transistor 42 and the first peak transistor 41 may be formed on separate semiconductor chips. In this case as well, the first main transistor 40 and the second peak transistor 43 are formed on one semiconductor chip 420, and the first interstage matching circuit 50 and the second interstage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the pass-through phase difference Δ.

[0053] Similarly, the first main transistor 40 and the second peak transistor 43 may be formed on separate semiconductor chips. In this case as well, the second main transistor 42 and the first peak transistor 41 are formed on one semiconductor chip 422, and the first interstage matching circuit 50 and the second interstage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the pass-through phase difference Δ. Thus, depending on the allowable pass-through phase difference Δ, some of the circuits in Figure 15 may be formed on separate chips.

[0054] Embodiment 4. Figure 16 is a plan view of the Doherty amplifier 500 according to Embodiment 4. This embodiment differs from Embodiment 1 in that the bonding wires connecting the semiconductor chips in the first signal path P1 and the bonding wires connecting the semiconductor chips in the second signal path P2 are non-parallel. The other configurations are the same as in Embodiment 1. In this embodiment, bonding wires 60 and 64, 61 and 65, 62 and 66, and 63 and 67 are non-parallel.

[0055] The spacing between bonding wires narrows on the semiconductor chips 20 and 22 where transistors are integrated. In other words, the bonding wires 61 and 65 connecting semiconductor chip 20 to semiconductor chip 21 adjacent to semiconductor chip 20 are spaced further apart as they approach semiconductor chip 21. Similarly, the bonding wires 62 and 66 connecting semiconductor chip 22 to semiconductor chip 21 adjacent to semiconductor chip 22 are spaced further apart as they approach semiconductor chip 21.

[0056] When two transistors are integrated onto a single semiconductor chip, the transistors are adjacent to each other. Consequently, the bonding wires connected to the transistors are also adjacent. The electromagnetic fields of adjacent bonding wires can couple, potentially degrading the RF characteristics. In this embodiment, by arranging adjacent bonding wires non-parallel, electromagnetic field coupling between wires can be suppressed while keeping the chip size down.

[0057] Furthermore, by narrowing the spacing of the bonding wires on the semiconductor chips 20 and 22, the semiconductor chips 20 and 22 can be made smaller. This allows the Doherty amplifier 500 to be manufactured at a low cost.

[0058] Figure 17 is a plan view of a Doherty amplifier 600 according to a modified example of Embodiment 4. The spacing between bonding wires may be wider on the semiconductor chips 20 and 22 where the transistors are integrated. Furthermore, the non-parallel bonding wires of this embodiment may be applied to Embodiments 2 and 3.

[0059] Embodiment 5. Figure 18 is a plan view of the Doherty amplifier 700 according to Embodiment 5. In this embodiment, the second peak transistor 743 is longer than the second main transistor 42 in the signal propagation direction. The signal propagation direction in Figure 18 is from input terminal 1 to output terminal 2. The drain pad 122 of the second main transistor 42 is provided on the signal propagation direction side of the second main transistor 42. The drain pad 121 of the second peak transistor 743 is provided adjacent to the second peak transistor 743 in a direction perpendicular to the signal propagation direction.

[0060] The output of the second peak transistor 743 is connected via a lead line 120 to a drain pad 121 positioned perpendicular to the gate pad. A bonding wire 67 connected to the drain pad 121 is connected to the circuit 31 via pad 123. The bonding wire 67 connected to the drain pad 121 of the second peak transistor 743 is inclined at an angle of 90 degrees or more relative to the bonding wire 63 connected to the drain pad of the second main transistor 42. The other configurations are the same as those of the fourth embodiment.

[0061] The Doherty amplifier 700 in this embodiment is an asymmetric Doherty amplifier in which the total gate width of the second peak transistor 743 is greater than the total gate width of the second main transistor 42. Compared to a symmetric Doherty amplifier, an asymmetric Doherty amplifier can achieve high efficiency at lower output power.

[0062] Figure 19 is a diagram illustrating the structure of a transistor. In Figure 19, D represents the drain, S represents the source, G represents the gate, and W1 represents the unit gate width. The total gate width is the product of the unit gate width W1 and the number of gates. The longer the unit gate width W1, the longer the transistor becomes in the signal propagation direction. Increasing the number of gates makes the transistor longer in the direction perpendicular to the signal propagation direction. In this embodiment, the second main transistor 42 and the second peak transistor 743 have the same number of gates, but their unit gate widths W1 are different.

[0063] When integrating transistors with different unit gate widths W1 onto a single semiconductor chip, there is a problem of a gap being created due to the difference in unit gate width W1. In this embodiment, the output signal of the second peak transistor 743 is routed to the center of the semiconductor chip 22 using a thin lead line 120. This allows a drain pad 121 to be provided between the second main transistor 42 and the second peak transistor 743. Therefore, the length of the semiconductor chip 22 in the signal propagation direction can be suppressed, and the gap caused by the difference in unit gate width can be suppressed. In addition, the spacing between bonding wires 62 and 66 can be widened, and electromagnetic field coupling can be suppressed. Furthermore, electromagnetic field coupling between bonding wires 63 and 68 can also be suppressed.

[0064] The technical features described in each embodiment may be used in combination as appropriate. [Explanation of symbols]

[0065] 1 Input terminal, 2 Output terminals, 10 Resin substrate, 11 Die pad, 20, 20a, 21, 22, 22a, 23, 24 Semiconductor chip, 30, 31 Circuit, 40 First main transistor, 41 First peak transistor, 42 Second main transistor, 43 Second peak transistor, 50 First interstage matching circuit, 50a Interstage matching circuit, 51 Second interstage matching circuit, 51a Interstage matching circuit, 52, 53 Input matching circuit, 60~68 Bonding wire, 70 Distribution circuit, 71 Combining circuit, 80 Input delay line, 81 Output delay line, 90, 91 Input matching circuit, 92, 93 Output matching circuit, 100 Doherty amplifier, 101 Distribution circuit, 102 Input matching delay circuit, 103 Input matching circuit, 104 Output matching delay circuit, 105 Output matching circuit, 106 Combining circuit, 120 Line, 121, 122 Drain pad, 123 Pad, 200 Doherty amplifier, 220, 221 Semiconductor chip, 300, 400 Doherty amplifier, 420, 422 Semiconductor chip, 500, 600, 700 Doherty amplifier, 743 Second peak transistor, 800, 900 Doherty amplifier, Cds Parasitic capacitance, P1 First signal path, P2 Second signal path, W1 Unit gate width, Δ Pass-through phase difference

Claims

1. Input terminals, Output terminals, A first main transistor is provided in the first signal path connecting the input terminal and the output terminal, A first peak transistor is provided in the second signal path connecting the input terminal and the output terminal, Of the first signal path, a second main transistor is provided on the output terminal side of the first main transistor, Of the second signal path, a second peak transistor is provided on the output terminal side of the first peak transistor, A first matching circuit provided in the first signal path, The second matching circuit provided in the second signal path, Equipped with, The first main transistor, the first peak transistor, the second main transistor, and the second peak transistor are formed on a first semiconductor chip. The first matching circuit and the second matching circuit are formed on the second semiconductor chip. The first matching circuit is provided between the first main transistor and the second main transistor in the first signal path. The Doherty amplifier is characterized in that the second matching circuit is provided between the first peak transistor and the second peak transistor in the second signal path.

2. The Doherty amplifier according to claim 1, characterized in that the first main transistor and the first peak transistor are provided inside the second main transistor and the second peak transistor.

3. The Doherty amplifier according to claim 1 or 2, characterized in that the first bonding wire connecting the semiconductor chips in the first signal path and the second bonding wire connecting the semiconductor chips in the second signal path are non-parallel.

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