Three-phase boost converter with PFC

Abstract

A network circuit (N) is described for providing an intermediate circuit DC voltage (UZK) and a load-dependent intermediate circuit current (IZK) at an output (OUT) from a three-phase supply network (VN). The network circuit includes a capacitor (CS) in a neutral network (MPN), which acts as an adjustable voltage source for setting a voltage difference across an inductor at an input (IN).

Description

Technical Field

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[0001] Cross - reference to related applications This application claims the priority of German Patent Application No. 102020116889.6, filed on June 26, 2020. The entire content of German Patent Application No. 102020116889.6 is hereby incorporated by reference in its entirety into this specification.

[0002] The present invention relates to a network circuit for supplying direct current from a three - phase supply network to an electrical load and to a method for modulating the string voltage from a three - phase supply network. The network circuit thereby ensures that the phase current at the input of the rectifier is substantially sinusoidal, independently of the load.

Background Art

[0003] Network circuits are known from the prior art. EP3068024A1 discloses a three - phase pulse rectifier system with low network feedback, in addition to relatively low reverse - voltage stress and high power density for power semiconductors that can be switched off. Such a three - phase three - point pulse rectifier, also referred to as a so - called Vienna rectifier, is known to be characterized by a substantially low harmonic content on the AC side, in contrast to the conventional six - pulse bridge circuit (B6) used for rectifying three - phase currents.

[0004] The Vienna rectifier is a circuit that requires a large number of components, is very expensive, and also requires very complex control.

[0005] <0*********9>From Austrian Patent Document AT512752B1, a rectifier circuit for a three - phase rectifier arrangement of semiconductor valves, preferably a bridge rectifier circuit of diodes, is known. The rectifier arrangement has a three - phase network - side input and a DC - side output, and at least one of the three phases at the network - side input is connected to the first pole terminal of a three - phase circuit for discharging the injection current into the three - phase circuit.

[0006] U.S. document US2013 / 0194838A1 discloses a low-input-current and harmonic three-phase step-up rectifier comprising an input stage for receiving three-phase input voltages relative to a neutral point and an output stage suitable for coupling to at least one load.

[0007] U.S. Patent document US5933336A discloses a boost converter having first, second, and third phase inputs and outputs. The boost converter further comprises a first switch and a second switch connected between the respective output leads. The boost converter also includes first, second, and third capacitors forming first, second, and third LC series paths with a first inductor, respectively. The first, second, and third LC series paths are coupled between the nodes of the first, second, and third phase inputs and the first and second switches, respectively. The first and second switches work progressively together to discharge current through the first inductor using the voltage across the leads excluding the voltage across the first, second, and third capacitors, thereby reducing the total harmonic distortion (THD) of the input current at all three phase inputs.

[0008] European document EP0973245A2 discloses a circuit in which an inductor is coupled to three phase inputs. Two switches are coupled between the output terminals. Three capacitors are connected to the three phase inputs in a star configuration, with the star point connected to the node between the switches. A diode rectifier is inserted between the inductor and the switches. The output is coupled to the switches through the output capacitor. The phase inputs are passed through an electromagnetic noise filter. The inductor operates in a discontinuous state. A control loop controls the switches. The switches operate progressively together using a voltage across the output that is smaller than that across the capacitors, discharging current through the inductor and reducing the total input current distortion at all phase inputs.

[0009] From international patent application WO93 / 12576A1, a circuit network is known that generates a current having amplitude and phase selected to reduce the total harmonic distortion of a system that converts AC to DC or vice versa, and which is a harmonic of the frequency of the supply system. The DC signal is sampled and, through the control of a switch, generates a sinusoidal current with the desired harmonics, which is supplied to an impedance network that injects this current into the multiphase AC system of a power supplier. The impedance network includes a single inductor and a capacitor connected in series through each of the phases of the power supplier, and the current signal has an amplitude selected to substantially remove harmonics that cause high distortion in the supply signal.

[0010] Chinese document CN102130572A discloses a three-phase rectifier bridge DC-side parallel-connected active power filter. The active power filter includes a coupling element on the AC side of a three-phase rectifier bridge, which is a low-frequency bidirectional power switch, and the coupling element is an impedance. The active power filter improves upon prior art in which two capacitors and four high-frequency power switching tubes are used in two boost bidirectional power converters connected in series, by requiring only one capacitor and three high-frequency power switching tubes. Therefore, compared to prior art, the active power filter does not require voltage balancing between the two original capacitors and thus exhibits better harmonic rejection.

[0011] Many loads connected to public supply networks draw pulsed line currents through simple bridge rectifiers, which are known to be associated with high-harmonic currents. These impulse currents necessitate large public supply networks. In addition, short-term voltage dips and spikes occur, causing increasing problems for sensitive consumers. For this reason, there are corresponding standards that require the use of so-called power factor correction (PFC) above a certain power level. As components in passive systems require larger installation space and emit currents with shapes that deviate from sinusoidal waveforms, the use of active circuit solutions becomes necessary as a result. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] European Patent Application Publication No. 3068024 [Patent Document 2] Austrian Patent No. 512752 [Patent Document 3] U.S. Patent Application Publication No. 2013 / 0194838 [Patent Document 4] U.S. Patent No. 5933336 [Patent Document 5] European Patent Application Publication No. 0973245 [Patent Document 6] International Publication No. 93 / 12576 [Patent Document 7] Chinese Patent Application Publication No. 102130572 Specification [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] The object of the present invention is to provide a low-cost, simple-control circuit for drawing mostly sinusoidal phase currents from a three-phase supply network, while thus maintaining the harmonic current limitations of the PFC standard. [Means for solving the problem]

[0014] This objective is solved by a network circuit for providing intermediate circuit DC voltage and load-dependent intermediate circuit current at the output from a three-phase supply network. The network circuit ensures that the phase currents from the supply network are mostly sinusoidal at the input of a rectifier. The network circuit thereby comprises an input connected to the three-phase supply network via phases, and an output connected to an intermediate circuit. The network circuit also includes a rectifier located between the input and output. Network detection detects network parameters of string voltage and current phase at the input, as well as output parameters at the output. A control unit is connected to the network detection and controls a first switching transistor and a second switching transistor. A midpoint network is connected to the output and input phases via the first and second switching transistors, the first switching transistor being connected to the control unit via a first control terminal, and the second switching transistor being connected to the control unit via a second control terminal. The midpoint network includes a capacitor, which is precharged via a clock signal from the first switching transistor and thus acts as a tunable voltage source for adjusting the voltage difference via one or more inductors.

[0015] Through this network circuit, the network current from the public supply network is mostly corrected to a sinusoidal waveform, and harmonics generated, for example, by pulsed recharging of a capacitor via a rectifier diode due to the load are reduced.

[0016] According to the first embodiment, the network circuit further comprises a coupling circuit connected between the phase at the input and the midpoint network. The coupling circuit, as part of the network circuit, is adapted to draw sinusoidal phase currents from all phases.

[0017] In one embodiment, the supply network may also include a neutral conductor.

[0018] According to another aspect, the capacitor of the midpoint network is in series between the phase at the input and the connection point of the first switching transistor and the second switching transistor.

[0019] According to a further aspect, the midpoint network further comprises an inductor connected in series between the phase at the input and the first switching transistor and the second switching transistor.

[0020] According to another aspect, the midpoint network comprises a series-connected capacitor having a first inductor with a diode and a second inductor with a diode, disposed between the phase at the input and the first switching transistor and the second switching transistor.

[0021] The above object is a method for modulating the phase voltage and current from a three-phase supply network to provide an intermediate circuit DC voltage and a load-dependent intermediate circuit current with a sinusoidal phase current at the output, comprising the steps of sending a phase current from the three-phase supply network to a network circuit via a phase, detecting network parameters of the phase by network detection, rectifying the phase current at the phase to generate a rectified current, and distributing the rectified current into a first rectified current and a second rectified current according to a clock state, supplying the first rectified current to at least one output, passing the second rectified current through the first switching transistor and the second switching transistor, driving the control inputs of the first switching transistor and the second switching transistor by a control unit so as to pass a part of the rectified current as a clock signal through the midpoint network to the phase, precharging the capacitor of the midpoint network with the clock signal, modulating the phase current at the phase via one or more inductors with the transferred clock signal, providing an intermediate circuit DC voltage and a load-dependent intermediate circuit current at the output, and drawing a sinusoidal current from the supply network.

[0022] In one aspect, the modulating step includes a controllable voltage drop across an inductor through a pre-charged capacitor.

[0023] According to another aspect, the step of modulating the phase current in a phase with the transferred clock signal is performed via a coupling circuit.

[0024] According to a further aspect, the step of detecting network parameters includes the step of detecting at least one of the alignment or phase position, the string voltage, and the phase current.

[0025] According to a further aspect, the step of driving the control inputs of the first switching transistor and the second switching transistor controls or affects the magnitude of the clock signal transferred and the intermediate circuit voltage using a duty factor.

[0026] According to a further aspect, the step of driving the control inputs of the first switching transistor and the second switching transistor by a control unit is performed such that, in the case of positive driving, first the first switching transistor is at low impedance from time t1 to time t3 during the switching-on period, the second switching transistor is at low impedance from time t2 to time t4 during the switching-on period, and the first and second switching transistors are at low impedance from time t2 to time t3 during the short-circuit period.

[0027] According to a further aspect, the step of driving the control inputs of the first and second switching transistors by a control unit is performed such that, during negative driving, first the second switching transistor is at low impedance from time t1 to time t3 during the switching-on period, the first switching transistor is at low impedance from time t2 to time t4 during the switching-on period, and the first and second switching transistors are at low impedance from time t2 to time t3 during the short-circuit period.

[0028] In a further embodiment, the step of modulating the transferred clock signal occurs such that the sinusoidal phase current at the input conforms to the limits of harmonic currents according to the PFC standard during operation.

[0029] In a further embodiment, the step of driving the control inputs of the first and second switching transistors is clocked at a clock frequency higher than the network frequency.

[0030] The present invention will be described in more detail here with reference to the drawings. [Brief explanation of the drawing]

[0031] [Figure 1] This is a schematic diagram of the first embodiment of the network circuit. [Figure 2] This is an example of a rectifier. [Figure 3] This is a combination of a rectifier and the first example of a control element. [Figure 4] This is the first example of a midpoint network. [Figure 5] This is a second example of a midpoint network. [Figure 6] This is a third example of a midpoint network. [Figure 7] This is the first example of a coupling circuit. [Figure 8] This is a second example of a coupled circuit. [Figure 9] This is a third example of a coupled circuit. [Figure 10] This is the first example of a four-wire, three-phase system. [Figure 11] This is the second example of a four-wire, three-phase system. [Figure 12] This is a schematic diagram of a second embodiment of the network circuit. [Figure 13] This is a network circuit according to the first embodiment. [Figure 14] It is a positive drive of at least one control element. [Figure 15]It is a negative drive of at least one control element. [Figure 16] This is the switching criterion for the supply network as a three-phase system. [Figure 17] Figure 13 shows a network circuit with illustrative selected components and parts. [Figure 18A] Figure 17 shows the simulation results of the network circuit. [Figure 18B] Figure 17 shows the simulation results of the network circuit. [Figure 18C] Figure 17 shows the simulation results of the network circuit. [Modes for carrying out the invention]

[0032] Referring to Figure 1, the general structure of a network circuit N according to a first embodiment for providing an intermediate circuit DC voltage UZK at output OUT from a three-phase supply network VN is described here.

[0033] The network circuit N comprises multiple interconnected components. The network circuit N includes an input IN, an EMI filter or electromagnetic interference filter, a network detection NE, a control unit SE with optionally an output detection AE, a rectifier GR, at least one control element ST, a midpoint network MPN, and an output OUT.

[0034] At input IN, network circuit N is connected to supply network VN via phases L1, L2, and L3. Phases L1, L2, and L3 have network parameters NG. Network parameters NG include at least one of phase alignment or phase position PL, string voltages UN (string voltages u1, u2, u3), and phase currents INL1, INL2, and INL3.

[0035] EMI filters are used to filter electromagnetic interference in known ways. For this reason and for brevity, EMI filters are not described in detail herein.

[0036] The network parameters NG for phases L1, L2, and L3 are detected by the network detection unit NE and passed to the control unit SE.

[0037] In addition, the location of the symmetric neutral point NN is shown in Figure 1, and it occurs at the indicated location when the supply network VN is a four-wire three-phase system with a neutral line.

[0038] The control unit SE may optionally be extended with an output detection AE to detect the magnitude of voltage and current at different locations, particularly at the output OUT of the network circuit N. Thus, the output detection detects at least one of the intermediate circuit voltage UZK and intermediate circuit current IZK at the output OUT.

[0039] As illustrated in Figure 2, in one embodiment, the rectifier GR may be constructed with rectifier diodes D and inductors LL1, LL2, and LL3 as energy storage. However, the rectifier GR is not limited to this illustrated embodiment. The rectifier GR may be constructed with passive components, active components, and / or combinations thereof. Thus, the rectifier GR can be a rectifier and inverter that enables regeneration capability to the supply network VN. The functions of the rectifier GR correspond to known functions and are therefore not detailed for the sake of brevity.

[0040] The energy required for the intermediate circuit can be provided by known energy storage techniques. A non-limiting example of such techniques is known from German Patent Application No. 102020106698.

[0041] As illustrated in Figure 3, the rectifier GR rectifies the phase currents INL1, INL2, and INL3 in phases L1, L2, and L3, thereby generating a rectified current IG. The rectified current IG is distributed to a first rectified current IG1 and a second rectified current IG2 depending on the clock state of at least one control element ST. The second rectified current IG2 is passed through at least one control element ST. The first rectified current IG1 supplies the output OUT of the network circuit N.

[0042] At least one control element ST comprises a first switching transistor T+ and a second switching transistor T- in the first embodiment of the network circuit N shown in Figure 1. The first switching transistor T+ is provided with a control input AN. The second switching transistor T- is provided with a control input AN. However, at least one control element ST is not limited to the first and second switching transistors T+ and T-.

[0043] Figure 3 shows that the combination of the first and second switching transistors T+ and T- of the network circuit N and the rectifier GR exemplifies a boost converter. A boost converter is a form of DC converter. The magnitude of the output voltage at the output of the boost converter is always higher than the magnitude of the input voltage of the boost converter. The magnitude of the intermediate circuit voltage UZK at output OUT is therefore higher than the rectified value of the network voltage UN (see Figure 1) at input IN.

[0044] At least one control element ST's control input AN is driven by the control unit SE. In the network circuit N shown in Figure 1, the control inputs AN of the first switching transistor T+ and the second switching transistor T- are driven by the control unit SE. By driving the control input AN with the control unit SE, the second rectified current IG2 is converted into a clock signal GS.

[0045] As can be seen in Figure 1, the clock signal GS is transferred to phases L1, L2, and L3 via the midpoint network MPN by at least one control element ST.

[0046] By transferring the clock signal GS to phases L1, L2, and L3, the phase currents INL1, INL2, INL3 and the rectified current IG in phases L1, L2, and L3 are modulated by the transferred clock signal GS. Due to the modulation, the phase currents INL1, INL2, and INL3 become mostly sinusoidal currents.

[0047] Figure 4 illustrates a first example of a midpoint network MPN. The midpoint network MPN in this first example includes a capacitor CS connected in series. Capacitor CS thus corresponds to a voltage source and thus generates a voltage difference through inductors LL1, LL2, and LL3.

[0048] Figure 5 illustrates a second example of a midpoint network MPN. The midpoint network MPN in the second example extends the midpoint network MPN in the first example by adding an inductor LM connected in series. The midpoint network MPN in the second example therefore comprises an inductor LM and a capacitor CS connected in series. Figure 5 illustrates that the combination of inductor LM and capacitor CS in the first example illustrates a series resonant circuit or an LC series resonant circuit.

[0049] Figure 6 illustrates a third example of a midpoint network MPN. The midpoint network MPN in the third example comprises a capacitor CS connected in series, a first inductor LM1 with a diode DL+, and a second inductor LM2 with a diode DL-. As can be seen from Figure 6, the combination of inductors LM1, LM2 and capacitor CS in the third example illustrates another type of series resonant circuit or LC series resonant circuit, as seen in Figure 5.

[0050] The three examples illustrated in Figures 4 to 6 illustrate three different examples of implementing a midpoint network MPN, without the intention of limiting midpoint network MPNs to these three examples.

[0051] The network circuit N shown in Figure 1 further comprises a coupling circuit KS. The coupling circuit KS is adapted to extract sinusoidal phase currents from all phases L1, L2, and L3. In other words, the coupling circuit KS ensures that high-frequency currents caused by the clocking of at least one control element ST are not visible to the phase currents INL1, INL2, and INL3.

[0052] Figure 7 illustrates a first example of the coupling circuit KS. The coupling circuit KS is a capacitor star circuit comprising capacitors CYL1, CYL2, CYL3 and a star point SP. The midpoint network MPN is connected to the star point SP of the capacitor star circuit in this example. The modulation of the phase currents INL1, INL2, and INL3 is performed in phases L1, L2, and L3 by the clock signal GS transferred through the capacitor star circuit KS in this example. The transferred clock signal GS is therefore fed back to the star point of the coupling circuit KS.

[0053] Figure 8 illustrates a second example of the coupling circuit KS. The coupling circuit KS in this second example is a capacitor delta circuit comprising capacitors CDL12, CDL23, and CDL31. In this example, the midpoint network MPN is directly connected to the three phases L1, L2, and L3. The transferred clock signal GS is therefore directly fed back to phases L1, L2, and L3.

[0054] Figure 9 illustrates a third example of the coupling circuit KS. The coupling circuit KS in the third example is a combination of the coupling circuits in the first and second examples.

[0055] The three illustrated examples illustrate three different ways of implementing the coupling circuit KS, without the intention of limiting the coupling circuit KS to these three examples.

[0056] Referring to Figure 10, a portion of a first example of a network circuit N having a four-wire three-phase system with a neutral wire is illustrated. Unlike the three-wire three-phase system described above, the midpoint network MPN may be directly connected to the symmetrical neutral point NN of the neutral wire.

[0057] Referring to Figure 11, a portion of a second example of a network circuit N comprising a four-wire three-phase system with a neutral wire is illustrated. In this second example, the neutral wire may be made up of at least one of an autotransformer, an isolation transformer, or another type of transformer upstream or downstream of the EMI filter EMI. In this example, the midpoint network MPN may be directly connected to the symmetrical neutral point NN of the neutral wire.

[0058] Figure 12 illustrates a second embodiment of the network circuit N as a multi-channel system. In a multi-channel system, a certain number of channels are connected in parallel and then recombined at the output. This system is clocked either synchronously or according to the interleaved principle, where the channels clock alternately. For example, in a two-channel system using the interleaved principle, the two channels are typically clocked with a difference of half a period. In an n-channel system, for example, the n channels are clocked with a difference of n divided periods. In a multi-channel system using the interleaved principle, the star point of the coupling circuit KS, designed as a capacitor star circuit, acts as the common reference point of the midpoint network MPN. In a four-wire three-phase system, the neutral point NN of the neutral wire can alternatively act as the common reference point of the midpoint network.

[0059] To ensure the operation of the network circuit illustrated in Figure 12, two interconnected filters F and two diodes D+ and D- are further exemplified. Optionally, an output detection AE can be provided to detect the voltage and current magnitudes at different positions in each channel.

[0060] Figure 13 illustrates the network circuit N corresponding to Figure 1 in the above-mentioned example of component selection. The input IN of network circuit N connects the three-phase supply network VN to the EMI filter via phases L1, L2, and L3. The network detection NE detects the network parameters NG of phases L1, L2, and L3 and passes them to the control unit SE. The control unit SE also includes an output detection AE, which detects the intermediate circuit voltage UZK and intermediate circuit current IZK at the output OUT. The coupling circuit KS is a capacitor star circuit as described with reference to Figure 7. The rectifier GR is a rectifier GR as described with reference to Figure 2. At least one control element ST is a control element ST as described with reference to Figure 3. A first diode D+ and a second diode D- are placed at the output OUT of network circuit N such that the intermediate circuit voltage UZK at the output OUT remains independent of the clocking of at least one control element ST. For clock independence, either the first diode D+ alone, the second diode D- alone, or both diodes D+ and D- can be provided. Furthermore, an output capacitor CA is provided between the output leads of the network circuit N. An intermediate circuit voltage UZK and a load-dependent intermediate circuit current IZK are provided at the output OUT.

[0061] The output capacitor CA is implemented as a capacitor in Figure 13. In the second example, the output capacitor CA may be implemented as a series connection of two or more capacitors, the midpoint of which is wired to a midpoint network MPN, and appropriate means (e.g., a filter) may be considered.

[0062] Figures 14 and 15 illustrate the control of at least one control element ST. Figure 14 illustrates the positive control of at least one control element ST. In the network circuit N according to Figure 1, the control unit SE drives the control input AN of the first and second switching transistors T+ and T- such that, in the case of positive drive, the first switching transistor T+ is low impedance from time t1 to time t3 during the switch-on period TE+, then the second switching transistor T- is low impedance at time t3 during the switch-on period TE+, the second switching transistor T- is low resistance from time t2 to time t4 during the switch-on period TE-, and during the short-circuit period TK, the first and second switching transistors T+ and T- are low impedance from time t2 to time t3.

[0063] Figure 15 illustrates the negative drive of at least one control element ST. In the network circuit N according to Figure 1, the control unit SE drives the control input AN of the first and second switching transistors T+ and T- such that, in the case of negative drive, the second switching transistor T- is low impedance from time t1 to time t3 during the switch-on period TE-, the first switching transistor T+ is low impedance from time t2 to time t4 during the switch-on period TE+, and the first and second switching transistors T+ and T- are low impedance from time t2 to time t3 during the short-circuit period TK.

[0064] For network circuit N to function as the desired sinusoidal phase currents INL1, INL2, and INL3 to be drawn from the supply network VN, neither positive nor negative driving is performed; both occur periodically alternately during operation. This depends on the network parameters NG of phases L1, L2, and L3, which are valid at the current time and are detected by network detection NE and evaluated by control unit SE.

[0065] Network detection NE can include various possibilities for detecting network parameters NG. For example, network parameters NG may be detected by network detection NE using one or more sensors. However, as an example, network parameters NG may be detected by network detection NE using a predetermined detection method based on actual / target adjustments.

[0066] The control unit SE includes a microprocessor or microcontroller or functionally equivalent component for evaluating the network parameters NG detected by the network detection unit NE.

[0067] Figure 16 illustrates the switching criteria for the supply network VN as a three-phase system. Considering the phase voltages u1, u2, and u3 of the three-phase system, there are times when two voltages are greater than zero and one voltage is less than zero, and times when one voltage is greater than zero and two voltages are less than zero.

[0068] If both voltages are greater than zero, positive control (see Figure 14) is used for this time or control block AB; if both voltages are less than zero, negative control (see Figure 15) is used for this time or control block AB. This switching criterion leads to a nearly triangular voltage curve in the sinusoidal interval SK, always traversing around the zero line.

[0069] In either case, during the voltage period TU, which is the time during which the control is effective, the string voltages u1, u2, and u3 are always in the same state, meaning they are either greater than zero or less than zero. Consequently, for a voltage period TU, the symmetric three-phase system can define TU = T(u1-u3) = T(u3-u2) = T(u2-u1).

[0070] At each zero point of the nearly triangular voltage curve of the sinusoidal interval SK, there is a change from positive to negative drive or negative to positive drive. If the nearly triangular voltage curve of the sinusoidal interval SK runs from a negative control block AB with a value less than zero to a positive control block AB with a value greater than zero, the drive changes from negative drive to positive drive. The transition from one control block AB to the next can be abrupt, as shown in the figure. The transition from one control block AB to the next can be even smoother (not illustrated).

[0071] In a European supply network with a network frequency of fN = 50 Hz, zero occurs every 3.33 milliseconds in a three-phase system. Therefore, there is a change between positive and negative drive every 3.33 milliseconds. However, the network circuit N is not limited to the European supply network. In fact, the network circuit N can be implemented for all international network voltages and network frequencies.

[0072] Figure 17 illustrates the network circuit N relating to Figure 13, with illustrative selected sizes of components and parts simulated in a simulation program for simulation purposes. The midpoint network MPN corresponds to the first example described with reference to Figure 4. For clarity, the network detection NE, control unit SE, and EMI filter EMI are not illustrated in this figure. The indicated size selection of individual components serves to illustrate the first experimental preparation. Thereafter, the size selection illustrates one of many options without intending to limit the size of the components.

[0073] Figure 18A illustrates the first simulation result of the network circuit N shown in Figure 17. The output voltage V(A, DCGND) is shown as an example, having a constant value of 700V and corresponding to the intermediate circuit DC voltage UZK.

[0074] Figure 18B illustrates the second simulation result of the network circuit N shown in Figure 17. The passages of the phase currents I(L1), I(L2), and I(L3), which are mostly sinusoidal in phases L1, L2, and L3, are illustrated, corresponding to the phase currents INL1, INL2, and INL3.

[0075] Figure 18C illustrates the third simulation result of the network circuit N shown in Figure 17. The progression of the network voltages V(L1), V(L2), and V(L3) in phases L1, L2, and L3 is illustrated, corresponding to the phase voltages u1, u2, and u3. [Explanation of Symbols]

[0076] AB control block AE output detection AN control input CA output capacitor CDL12, CDL23, CDL31 Capacitors CS Capacitor CYL1, CYL2, CYL3 Capacitors D Rectifier diode D+ First diode D - Second diode DL+ diode DL- Diode EMI (Electromagnetic Interference) Filter F filter GR rectifier GS clock signal IG rectified current IG1 First rectified current IG2 Second rectified current IN Input INL1, INL2, INL3 phase current IZK intermediate circuit current KS coupling circuit L1, L2, L3 phase LL1, LL2, LL3 Inductors LM Inductor LM1 First inductor LM2 Second inductor MPN Midpoint Network N Network Circuit NE Network Detection NG Network Parameters NN symmetrical neutral point OUT output PL phase position SE Control Unit SP Starpoint ST control element T+ First switching transistor T - Second switching transistor UN(u1, u2, u3) String Voltage UZK Intermediate Circuit DC Voltage VN Three-Phase Supply Network

Claims

1. A network circuit (N) for providing an intermediate circuit DC voltage (UZK) and a load-dependent intermediate circuit current (IZK) at the output (OUT) from a three-phase supply network (VN), wherein the network circuit (N) ensures that the phase currents (INL1, INL2, INL3) are substantially sinusoidal. An input (IN) connected to the three-phase supply network (VN) via phases (L1, L2, L3), The output (OUT) connected to the intermediate circuit (ZK), A rectifier (GR) is positioned between the input (IN) and the output (OUT), Network detection (NE) for detecting the network parameters (NG) of the phases (L1, L2, L3) at the input (IN) and for detecting the output parameters (UZK, IZK) at the output (OUT), A control unit (SE) for driving the first switching transistor (T+) and the second switching transistor (T-), A midpoint network (MPN) connected to the output (OUT) and the phases (L1, L2, L3) of the input (IN) via the first switching transistor (T+) and the second switching transistor (T-), wherein the first switching transistor (T+) is connected to the control unit (SE) via a control input (AN) and the second switching transistor (T-) is connected to the control unit (SE) via a control input (AN), The rectifier (GR) is provided with inductors (LL1, LL2, LL3) positioned between the coupling circuit (KS) and the rectifier (GR) at its input. The aforementioned midpoint network (MPN) A capacitor (CS) that can be precharged via the clock signal (GS) of the first switching transistor (T+) and the second switching transistor (T-), and which acts as a tunable voltage source for adjusting the voltage difference via the inductors (LL1, LL2, LL3), and which reliably adjusts the voltage via the inductors (LL1, LL2, LL3) when the short-circuit period (TK) during which the first switching transistor (T+) and the second switching transistor (T-) are low impedance is adjusted. A network circuit (N) equipped with the following.

2. The coupling circuit (KS) connected between the phases (L1, L2, L3) at the input (IN) and the midpoint network (MPN) is adapted to extract sinusoidal phase currents (INL1, INL2, INL3) from all phases (L1, L2, L3). The network circuit (N) according to claim 1.

3. A network circuit (N) for providing an intermediate circuit DC voltage and a load-dependent intermediate circuit current at the output (OUT) of a four-wire three-phase system with a neutral wire, wherein the network circuit (N) ensures that the phase currents (INL1, INL2, INL3) are substantially sinusoidal. The input (IN) is connected to the aforementioned 4-wire three-phase system via phases (L1, L2, L3), The output (OUT) connected to the intermediate circuit (ZK), A rectifier (GR) is positioned between the input (IN) and the output (OUT), Network detection (NE) for detecting the network parameters (NG) of the phases (L1, L2, L3) at the input (IN) and the output parameters (UZK, IZK) at the output (OUT), A control unit (SE) for driving the first switching transistor (T+) and the second switching transistor (T-), A midpoint network (MPN) is provided, wherein the output (OUT) and the phases (L1, L2, L3) of the input (IN) are connected via the first switching transistor (T+) and the second switching transistor (T-), the first switching transistor (T+) is connected to the control unit (SE) via the control input (AN), and the second switching transistor (T-) is connected to the control unit (SE) via the control input (AN), At the input of the rectifier (GR), inductors (LL1, LL2, LL3) are arranged between the coupling circuit (KS) and the rectifier (GR). Equipped with, The aforementioned midpoint network (MPN) A capacitor (CS) that can be precharged via the clock signal (GS) of the first switching transistor (T+) and the second switching transistor (T-), and which acts as a taut voltage source for setting a voltage difference via the inductors (LL1, LL2, LL3), and which reliably adjusts the voltage via the inductors (LL1, LL2, LL3) when the short-circuit period (TK) during which the first switching transistor (T+) and the second switching transistor (T-) are low impedance is adjusted. A network circuit (N) equipped with the following.

4. The capacitor (CS) of the midpoint network (MPN) is arranged in series between the phases (L1, L2, L3) at the input (IN) and the connection point of the first switching transistor (T+) and the second switching transistor (T-). The network circuit according to claim 1.

5. The midpoint network (MPN) further comprises an inductor (LM) connected in series between the phases (L1, L2, L3) at the input (IN) and the first switching transistor (T+) and the second switching transistor (T-). The network circuit according to claim 1.

6. The midpoint network (MPN) comprises a capacitor (CS) with a first inductor (LM1) with a diode (DL-) and a second inductor (LM2) with a diode (DL+), wherein the capacitor (CS) is connected in series between the phases (L1, L2, L3) at the input (IN) and the first switching transistor (T+) and the second switching transistor (T-). The network circuit according to claim 1.

7. A method for modulating current from a three-phase supply network (VN) to provide an intermediate circuit DC voltage (UZK) and a load-dependent intermediate circuit current (IZK) at an output (OUT) with sinusoidal phase currents (INL1, INL2, INL3), The steps include sending phase currents (INL1, INL2, INL3) from a three-phase supply network (VN) to a network circuit (N) via phases (L1, L2, L3), The steps include detecting network parameters (NG) of the phases (L1, L2, L3) by network detection (NE), A step of generating a rectified current (IG) by rectifying the phase currents (INL1, INL2, INL3) in the aforementioned phases (L1, L2, L3), wherein the rectified current (IG) is distributed to a first rectified current (IG1) and a second rectified current (IG2) according to the clock state, The steps include supplying the first rectified current (IG1) to at least one output (OUT), The steps include passing the second rectified current (IG2) through the first switching transistor (T+) and the second switching transistor (T-), The steps include: driving the control inputs (AN) of the first switching transistor (T+) and the second switching transistor (T-) by a control unit (SE) so that a portion of the second rectified current (IG2) passes through the phases (L1, L2, L3) as a clock signal (GS) via a midpoint network (MPN); The steps include: precharging the capacitor (CS) of the midpoint network (MPN) with the clock signal (GS), The steps include modulating the phase currents (INL1, INL2, INL3) in the phases (L1, L2, L3) via inductors (LL1, LL2, LL3) with the transferred clock signal (GS), The steps include providing the intermediate circuit DC voltage (UZK) and the load-dependent intermediate circuit current (IZK) at the output (OUT), The steps include drawing a sinusoidal current from the three-phase supply network (VN), A method wherein, when the short-circuit period (TK) during which the first switching transistor (T+) and the second switching transistor (T-) are / are at low impedance is adjusted, the capacitor (CS) reliably adjusts the modulation based on the drive.

8. The modulation of the phase currents (INL1, INL2, and INL3) in the phases (L1, L2, L3) in the transferred clock signal (GS) is performed via a coupling circuit (KS). The method according to claim 7.

9. The step of driving the control input (AN) of the first switching transistor (T+) and the second switching transistor (T-) adjusts the level of the transferred clock signal (GS) and the intermediate circuit DC voltage (UZK) via a duty factor (TV), or affects the level of the transferred clock signal (GS) and the intermediate circuit DC voltage (UZK). The method according to claim 7.

10. When the drive of the control input (AN) of the first switching transistor (T+) and the second switching transistor (T-) by the control unit (SE) is a positive drive, First, the first switching transistor (T+) has a low impedance from time t1 to time t3 during the switch-on period (TE+), and The second switching transistor (T-) has a low impedance from time t2 to time t4 during the switch-on period (TE-). The first switching transistor (T+) and the second switching transistor (T-) are low impedance during the short-circuit period (TK) from time t2 to time t3. It is done in this way, The method according to claim 7.

11. When the drive of the control input (AN) of the first switching transistor (T+) and the second switching transistor (T-) by the control unit (SE) is a negative drive, First, the second switching transistor (T-) has a low impedance during the switch-on period (TE-) from time t1 to time t3. The first switching transistor (T+) has a low impedance from time t2 to time t4 during the switch-on period (TE+). The first switching transistor (T+) and the second switching transistor (T-) are low impedance during the short-circuit period (TK) from time t2 to time t3. It is done in this way, The method according to claim 7.

12. The modulation of the transferred clock signal (GS) is performed such that the sinusoidal phase currents (INL1, INL2, and INL3) at the input (IN) of the three-phase supply network (VN) conform to the limits of the harmonic current (OSS) according to the PFC standard during operation. The method according to claim 7.

13. The drive of the control input (AN) of the first switching transistor (T+) and the second switching transistor (T-) is clocked at a clock frequency (fS) higher than the network frequency (fN). The method according to claim 7.

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