Semiconductor equipment

Abstract

To reduce power consumption of a shift register or a display device including the shift register.SOLUTION: A clock signal is not supplied to a shift register through one wiring but is supplied through a plurality of wiring. Further, any one of the plurality of wiring does not supplies the clock signal during the whole operation period of the shift register but supplies the clock signal in only part of the operation period. Therefore, a capacity load driven with supply of the clock signal can be reduced. As the result, power consumption of the shift register can be reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a shift register. It also relates to a display device having the shift register.

Background Art

[0002] As represented by a liquid crystal display device, thin film transistors (hereinafter also referred to as TFT: Thin Film Transistor) formed on a flat plate such as a glass substrate are mainly manufactured using a semiconductor material such as amorphous silicon or polycrystalline silicon. A TFT using amorphous silicon has a low field effect mobility but can cope with the enlargement of the area of the glass substrate. On the other hand, a TFT using polycrystalline silicon has a high field effect mobility but requires a crystallization process such as laser annealing and is not always suitable for the enlargement of the area of the glass substrate.

[0003]

[0004]

[0005] TFTs fabricated using such oxide semiconductors are used in liquid crystal displays and electronic displays. The pixel section and driving circuit of a display device such as a luminescent display or electronic paper. It is expected to be applied to switching elements. For example, using the above oxide semiconductor... A technology that uses TFTs fabricated in this way to construct the pixel section and driving circuit of a display device is not patented. This is disclosed in Submission 1.

[0006] However, all TFTs fabricated using the above oxide semiconductors are n-channel type transients. It is a standard. Therefore, the drive circuit is constructed using TFTs fabricated with oxide semiconductors. In this case, the drive circuit is constructed using only n-channel TFTs (hereinafter also referred to as unipolar). It will be accomplished. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Non-patent literature]

[0008] [Non-Patent Document 1] T.Osada, and 8 others, SID 09 DIGEST, pp.184-187(2009) [Overview of the project] [Problems that the invention aims to solve]

[0009] The drive circuit consists of a shift register and a buffer, etc. If the signal is composed of unipolar TFTs, the signal will be reduced by the threshold voltage of the TFTs. Problems such as an increase occur. Therefore, at the location where such a problem occurs, a bootstrap trap is often used. Specifically, it is often used when driving an analog switch or the like that drives a signal line or a scanning line of a display device.

[0010] Furthermore, when the load of a drive circuit using a bootstrap becomes large, it is necessary to increase the gate width of the TFT constituting the drive circuit. Along with this, the parasitic capacitance generated in the TFT also increases. In particular, in a TFT (so-called, reverse staggered type TFT, etc.) that needs to overlap a conductive layer functioning as a gate terminal and a conductive layer functioning as a source terminal or a drain terminal via a gate insulating layer, the parasitic capacitance increases. As a result, there is a problem that the power consumption of the clock signal input to the drive circuit increases due to the parasitic capacitance.

[0011] In view of the above problems, one aspect of the present invention aims to reduce the power consumption of a shift register or a display device having the shift register.

Means for Solving the Problems

[0012] The above problems can be solved by dividing the clock signal line included in the shift register into a plurality of pulse signal lines. That is, instead of a plurality of flip-flops included in the shift register being electrically connected to one clock signal line, a plurality of pulse signal lines are provided and a part of the plurality of flip-flops is electrically connected to any one of the plurality of pulse signal lines. Furthermore, the pulse signal line does not supply a clock signal throughout the operation period of the shift register, but supplies a clock signal during a part of the operation period included in the operation period. ​ It supplies a signal. This drives the shift register in conjunction with the supply of the clock signal. This reduces the capacitive load. As a result, it reduces the power consumption of the shift register. It is possible.

[0013] In other words, one aspect of the present invention is that the operating period overlaps with the first period, the second period, and the first period. It has a third period including the period of fold-over, and a fourth period including the period of overlapping with the second period. A shift register that periodically cycles between a low power supply potential and a high power supply potential throughout a first period. A first pulse signal line functions as wiring that supplies a repeating clock signal, and a second period Through this, a second pulse signal line functions as wiring that supplies the clock signal, and a third period Through this, it functions as wiring that supplies an inverted clock signal, which is the inverted signal of the clock signal. The third pulse signal line and the wiring that supplies the inverting clock signal throughout the fourth period are used. A functioning fourth pulse signal line and a first period electrically connected to the first pulse signal line In this configuration, a first flip-flop outputs a high power supply potential, and an electrical signal is supplied to the second pulse signal line. A second flip-flop connected to the second flip-flop outputs a high power supply potential during the second period, and A flip-flop 1 and a third pulse signal line are electrically connected, during the third period A third flip-flop that outputs a high power supply potential, and a second flip-flop and a fourth A fourth fuse electrically connected to the pulse signal line, which outputs a high power supply potential during the fourth period. It is a shift register having a lip-flop.

[0014] Furthermore, in one aspect of the present invention, in the above configuration, the first pulse signal line is outside the first period. Throughout this period, it functions as wiring that supplies a low power potential, and the second pulse signal line is the second Throughout the period other than that, it functions as wiring that supplies a low power potential and a third pulse signal The wire functions as wiring that supplies a low power potential throughout the period other than the third period, and the fourth The pulse signal line functions as wiring that supplies a low power potential throughout the period other than the fourth period. It is a shift register.

[0015] Furthermore, in the above configuration, the flip-flop channel formation region is made of an oxide semiconductor. A shift register having transistors configured in this way is also one aspect of the present invention.

[0016] Furthermore, in the above configuration, the pulse signal line is a clock signal or an inverted clock signal. The reference clock signal line is transmitted via a transistor that is turned on during the period when the lock signal is supplied. Alternatively, a shift register electrically connected to a reference inverted clock signal line is also one aspect of the present invention. ru.

[0017] Furthermore, in the above configuration, the pulse signal line is a clock signal or an inverted clock signal. A low power supply potential is supplied via a transistor that turns on during periods when no lock signal is being supplied. A shift register electrically connected to the wiring is also one aspect of the present invention.

[0018] Furthermore, a display device having a shift register with the above configuration is also one aspect of the present invention. [Effects of the Invention]

[0019] A shift register according to one aspect of the present invention is supplied with a clock signal via a single wire. Instead, it is supplied by multiple wires. Furthermore, one of these multiple wires is shift Instead of supplying the clock signal throughout the entire operating period of the resistor, it is supplied only for a portion of the period. It supplies a clock signal. Therefore, the capacitive load driven in conjunction with the supply of the clock signal This can be reduced. As a result, the power consumption of the shift register can be reduced. [Brief explanation of the drawing]

[0020] [Figure 1] (A) A diagram showing an example configuration of the shift register described in Embodiment 1, and (B) a timing chart. [Figure 2] (A) A diagram showing an example configuration of the flip-flop described in Embodiment 1, and (B) a timing chart. [Figure 3] (A) A diagram showing an example configuration of the pulse signal line described in Embodiment 1, and (B) a timing chart. [Figure 4] (A) A diagram showing an example configuration of the pulse signal line described in Embodiment 1, and (B) a timing chart. [Figure 5] (A) to (C) Figures showing modified versions of the shift register described in Embodiment 1. [Figure 6] Figures (A) and (B) showing modified versions of the shift register described in Embodiment 1, and a timing chart (C) showing a modified version. [Figure 7] (A) A diagram showing a modified version of the flip-flop described in Embodiment 1, and (B) A timing chart showing the modified version. [Figure 8] (A) Top view, (B), and (C) Cross-sectional view of the transistor described in Embodiment 2. [Figure 9] (A) Top view and (B) Cross-sectional view of the transistor described in Embodiment 2. [Figure 10] (A) Top view and (B) Cross-sectional view of the multiple transistors described in Embodiment 2. [Figure 11] (A) to (D) Cross-sectional views showing the transistor fabrication process described in Embodiment 2. [Figure 12](A) Top view and (B) Cross-sectional view of the multiple transistors described in Embodiment 3. [Figure 13] (A) Top view and (B) Cross-sectional view of the multiple transistors described in Embodiment 4. [Figure 14] (A) Block diagram of the display device described in Embodiment 5, (B) Block diagram of the scan line drive circuit, and (C) Block diagram of the signal line drive circuit. [Figure 15] (A) Circuit diagram of a pixel, (B) Top view of the pixel, and (C) Cross-sectional view of the liquid crystal display device described in Embodiment 6. [Figure 16] (A) Circuit diagram of a pixel, (B) to (D) Cross-sectional views of the light-emitting display device described in Embodiment 7. [Figure 17] (A) Top view and (B) Cross-sectional view of the light-emitting display device described in Embodiment 7. [Figure 18] (A) Circuit diagram, (B) Top view, and (C) Cross-sectional view of the pixel of the electronic paper described in Embodiment 7. [Figure 19] A diagram showing an example of an e-book described in Embodiment 8. [Figure 20] (A) and (B) are diagrams showing examples of electronic devices described in Embodiment 9. [Figure 21] (A) and (B) are diagrams showing examples of electronic devices described in Embodiment 9. [Figure 22] (A) and (B) are diagrams showing examples of electronic devices described in Embodiment 9. [Modes for carrying out the invention]

[0021] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form may not depart from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, The present invention is not limited to the embodiments described below.

[0022] Note that the source and drain terminals of a transistor are related to the transistor's structure and operating conditions. Because it varies depending on the factors, it is difficult to determine which is the source terminal and which is the drain terminal. It is difficult. Therefore, in this document, one of the source terminal and drain terminal is referred to as the first terminal. The other terminal, besides the source terminal and the drain terminal, will be referred to as the second terminal to distinguish them.

[0023] Furthermore, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment is as follows: The figures may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. It is not defined. Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification are not defined. This is added to avoid confusion regarding the constituent elements and does not mean that the number is limited. do.

[0024] (Embodiment 1) In this embodiment, an example of the configuration and operation of a shift register is shown in Figures 1 to 7. I will explain while referring to it. Specifically, during a certain period included in the operating time of the shift register It functions as wiring that supplies the clock signal during that period, and during periods other than that period, low power supply A pulse signal line that functions as wiring to supply pulses, and electrically connected to the pulse signal line This section describes a shift register that has a flip-flop.

[0025] <Example of a shift register configuration> The shift register of this embodiment includes a first pulse signal line to a sixth pulse signal line, and a third It has 1 to 10 flip-flops.

[0026] The first pulse signal line (PS1) is connected to the first flip-flop (FF1) and the third The flip-flop (FF3) is electrically connected, and the second pulse signal line (PS2) is, The fifth flip-flop (FF5) and the seventh flip-flop (FF7) are electrically connected. Next, the third pulse signal line (PS3) is electrically connected to the ninth flip-flop (FF9). The fourth pulse signal line (PS4) is connected to the second flip-flop (FF2) and Electrically connected to the fourth flip-flop (FF4) and the fifth pulse signal line (PS5) This provides electrical signals to the sixth flip-flop (FF6) and the eighth flip-flop (FF8). The sixth pulse signal line (PS6) is connected to the tenth flip-flop (FF10). It is electrically connected to (see Figure 1(A)).

[0027] Furthermore, the output terminal of each flip-flop supplies electricity to the input terminal of the next flip-flop. They are connected. Note that the input terminal of the first flip-flop (FF1) is the start It is electrically connected to the wiring that supplies pulses (SP).

[0028] Furthermore, the first pulse signal line (PS1) is at a high power supply potential and low power supply potential during the first period (t1). It functions as wiring that supplies a clock signal that periodically repeats the power supply potential, and a second pulse signal Line (PS2) functions as a wiring that supplies the clock signal during the second period (t2). The third pulse signal line (PS3) supplies the clock signal during the third period (t3). It functions as a wiring, and the fourth pulse signal line (PS4) in the fourth period (t4) It functions as wiring that supplies an inverted clock signal, which is the inverted signal of the clock signal, and the fifth The ruth signal line (PS5) is the wiring that supplies the inverted clock signal during the fifth period (t5). It functions as such, and the sixth pulse signal line (PS6) is inverted during the sixth period (t6). It functions as wiring that supplies the buck signal (see Figure 1(B)).

[0029] <Example of shift register operation> The operation of the shift register in this embodiment will be described below.

[0030] First, a start pulse (SP) is sent to the input terminal of the first flip-flop (FF1) as A signal with a high power supply potential is input. The first flip-flop (FF1) receives the input signal. It operates using this, and after half a clock cycle, a high-power supply signal is output to the first flip-flop. Output as a signal (FF1out).

[0031] The output signal (FF1out) is input to the input terminal of the second flip-flop (FF2). The second flip-flop (FF2) is the same as the first flip-flop (FF1). Similarly, it operates using the input signal, and after half a clock cycle, it outputs a high-power supply signal to the second phase. The output signal is generated as the output signal of the lip-flop (FF2out).

[0032] Similarly, when a signal with a high power supply potential is input to the input terminal of the next stage flip-flop, half-clock After the lock cycle, a signal with a high power supply potential is output from the flip-flop.

[0033] <Specific examples of flip-flops> A specific circuit configuration example of the flip-flop in this embodiment is shown in Figure 2(A). In 2(A), for convenience, the first flip-flop (FF1) and the second flip-flop This shows only the configuration of the FF2.

[0034] The first flip-flop (FF1) uses transistors 101 through 106. It has. Note that, in this case, transistors 101 to 106 are n-channel type. Let's assume it's a transistor.

[0035] Transistor 101 has its gate terminal connected to the output terminal of the second flip-flop (FF2). A wire that is electrically connected and whose first terminal supplies a high power potential (VDD) (hereinafter referred to as high power potential) It is electrically connected to a wire (also called a cable).

[0036] Transistor 102 has a gate terminal that supplies the start pulse (SP) (hereinafter, It is electrically connected to the (also called the start pulse line), and the first terminal is the second terminal of transistor 101. A wire electrically connected to the terminal, with the second terminal supplying the low power supply potential (VSS) (hereinafter referred to as low power supply It is electrically connected to the source potential line (also called the source potential line).

[0037] Transistor 103 has its gate terminal electrically connected to the start pulse line, and terminal 1 It is electrically connected to the high-power potential line.

[0038] Transistor 104 has a gate terminal that is the second terminal of transistor 101 and transistor 104. It is electrically connected to the first terminal of 102, and the first terminal is electrically connected to the second terminal of transistor 103. They are connected, and the second terminal is electrically connected to the low power potential line.

[0039] Transistor 105 has a gate terminal that is the second terminal of transistor 103 and transistor It is electrically connected to the first terminal of 104, and the first terminal is electrically connected to the first pulse signal line (PS1). It connects to the target.

[0040] Transistor 106 has its gate terminal at the second terminal of transistor 101, and transistor 1 It is electrically connected to the first terminal of 02 and the gate terminal of transistor 104, and the first terminal is It is electrically connected to the second terminal of the transistor 105, and the second terminal is electrically connected to the low power potential line. It will continue.

[0041] For convenience, in the following, we will refer to the second terminal of transistor 101 and transistor 102 The first terminal, the gate terminal of transistor 104, and the gate terminal of transistor 106 are The points of electrical connection are node A, the second terminal of transistor 103, and transistor 104. The point where the first terminal and the gate terminal of transistor 105 are electrically connected is called node B. Let's do it this way.

[0042] In addition to the above configuration, a capacitance is added between the gate terminal and source terminal of transistor 105. A configuration in which an element is provided is also possible. By providing the capacitive element, as will be explained below. This ensures that the bootstrap operation can be performed reliably.

[0043] <Example of flip-flop operation> The following describes the behavior of the flip-flop as described above, using the first flip-flop (FF1) as an example. The process will be explained with reference to Figure 2(B).

[0044] First, the start pulse line electrically connected to the first flip-flop (FF1) The level increases to a high level (hereinafter referred to as H level). As a result, the H level signal It is input to the gate terminal of transistor 102 and the gate terminal of transistor 103. Therefore, transistors 102 and 103 are turned on. As a result, node A The potential of node B drops to a low level (hereinafter referred to as L level), and the potential of node B drops to a high level. And it increases. Consequently, transistor 105 also turns on. As a result, during that period The potential of the first pulse signal line (PS1), which is at an L level, is the potential of the first flip-flop. It is output as an output signal (FF1out).

[0045] During the following period, the potential of the start pulse line drops to the L level. Therefore, Transistor 102 and transistor 103 turn off. As a result, nodes A and B It enters a floating state. At this time, there is an L level between the source terminal and gate terminal of transistor 105. A potential difference of level H exists from the node, and because node B is in a floating state, The potential difference is maintained. In other words, transistor 105 does not depend on the potential state of the source terminal. It remains on. Also, the potential of the first pulse signal line (PS1) increases to the H level. This results in a floating state that is electrically connected to the gate terminal of transistor 105. The potential of node B is determined by the high-level potential of the first pulse signal line (PS1) during that period. It increases further. In this way, the transistors electrically connected to node B, which is in a floating state The capacitive coupling between the gate terminal and source terminal of TA105 increases the potential of node B. This method is called bootstrap. As a result, the potential of the first pulse signal line (PS1) A certain high-level potential is output as the output signal (FF1out) of the first flip-flop. It can be done.

[0046] Note that in this case, transistor 105 is an n-channel transistor. During the period in which the potential of pulse signal line 1 (PS1) becomes high, transistor 1 In 05, the terminal electrically connected to the output terminal of the first flip-flop (FF1) is so The drain terminal is the terminal that is electrically connected to the first pulse signal line (PS1). Yes. Also, the on / off state of a transistor is determined by the potential difference between the source terminal and the gate terminal. This is determined by the n-channel transistor that does not perform bootstrapping. Then, the high level potential of the first pulse signal line (PS1) is the output signal of the first flip-flop. When output as (FF1out), the output potential is from the H level potential. The threshold voltage (Vth) of the n-channel transistor will decrease by the same amount. However, because transistor 105 is performing bootstrap, the first pulse signal line Without lowering the potential of (PS1), the output signal of the first flip-flop (FF1o It can be written as ut).

[0047] Furthermore, the H-level signal which is the output signal of the first flip-flop (FF1) is the second The input is passed to the flip-flop (FF2). Here, the second flip-flop (FF2) ) is the first pulse signal line (PS) that is electrically connected to the first flip-flop (FF1). Except for replacing 1) with the fourth pulse signal line (PS4), the first flip-flop ( This has the same configuration as FF1). Therefore, for detailed circuit operation, please refer to the explanation above. During the said period, the second flip-flop (FF2) will be used during that period. It outputs an L-level potential, which is the potential of the fourth pulse signal line (PS4).

[0048] During the following period, as the potential of the first pulse signal line (PS1) decreases to the L level... Then the potential of the fourth pulse signal line (PS4) increases to the H level. As a result, the first free The output signal of the pop-flop (FF1out) drops to a low level. Also, the fourth pulse... The potential of the signal line (PS4), which is at an H level, is the output signal (F) of the second flip-flop. Output as F2out)

[0049] The output signal of the second flip-flop (FF2out) is used by the third flip-flop The signal is input to the (not shown) and the transistors of the first flip-flop (FF1) It is also input to the gate terminal of ZISTA 101. Therefore, the first flip-flop (FF1 The transistor 101 in ) turns on. As a result, the potential of node A becomes high. Transistors 104 and 106 also turn on as a result. When 104 is turned on, the potential at node B drops to the L level. In other words, The potential at the gate terminal of transistor 105 drops to an L level. Therefore, transistor 10 5 turns off. In addition, transistor 106 turns on, and the first flip-flop The output signal of the pp (FF1out) is transmitted through transistor 105 during the period of first From the L level of the pulse signal (PS1), the low power supply potential (VS) is transmitted through transistor 106. The signal changes to the L level of S). In other words, the output signal of the first flip-flop (FF1ou There is no substantial change in t), but its origin changes.

[0050] During the following period, the potential of the fourth pulse signal line (PS4) drops to an L level. Consequently, the output signal of the second flip-flop (FF2out) drops to a low level. Therefore, transistor 101 of the first flip-flop (FF1) turns off. As a result, the node and transistor electrically connected to the gate terminal of transistor 104 A node electrically connected to the gate terminal of 106 remains floating while holding an H-level signal. This is the state in which transistors 104 and 106 remain on, and the first phase The output signal of the lip-flop (FF1out) remains at a low level. Note that this state is: Until a high level potential is again input to the input terminal of the first flip-flop (FF1) It will be maintained.

[0051] The first flip-flop (FF1) shown in Figure 2(A) operates as described above, and The transmitted signal can be output with a delay of half a clock cycle.

[0052] <Example of a pulse signal line> The shift register of this embodiment has a first pulse signal line (PS1) to a sixth pulse signal line. The signal line (PS6) supplies the clock signal for a portion of the operating period. It functions as wiring, and during periods other than that period, it functions as wiring that supplies a low power potential. An example of wiring with this function will be described below with reference to Figures 3 and 4.

[0053] The first pulse signal line (PS1) to the sixth pulse signal line (PS6) shown in Figure 3(A) These are the clock signal selection transistors 111, 112, and 113, and the inverting clock, respectively. Source terminal and drain of one of the signal selection transistors 114, 115, or 116 The terminal connects to the reference clock signal line (CK) or the reference inverted clock signal line (CKB) and the power They are electrically connected. Note that here, the clock signal selection transistors 111 and 112 are used. Transistors 113 and 114, 115, and 116 for selecting the inverting clock signal are n-channel Let's assume it's a type transistor.

[0054] Specifically, the clock signal selection transistor 111 has a gate terminal that is connected to control terminal a. The first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal The child is electrically connected to the reference clock signal line (CK). Clock signal selection transistor In terminal 112, the gate terminal is electrically connected to control terminal b, and the first terminal is connected to the second pulse signal. The second terminal is electrically connected to the PS2 line, and the second terminal is electrically connected to the reference clock signal line (CK). The clock signal selection transistor 113 has its gate terminal electrically connected to the control terminal c. It is connected, the first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is It is electrically connected to the reference clock signal line (CK).

[0055] The inverting clock signal selection transistor 114 has its gate terminal electrically connected to the control terminal d. The first terminal is electrically connected to the fourth pulse signal line (PS4), and the second terminal is the reference. Electrically connected to the inverting clock signal line (CKB). Transistor for inverting clock signal selection. In the 115, the gate terminal is electrically connected to the control terminal e, and the first terminal is connected to the fifth pulse signal It is electrically connected to line (PS5), and the second terminal is electrically connected to the reference inverting clock signal line (CKB). They are electrically connected. The inverting clock signal selection transistor 116 has its gate terminal at the control terminal. It is electrically connected to child f, and the first terminal is electrically connected to the sixth pulse signal line (PS6). The second terminal is electrically connected to the reference inverting clock signal line (CKB).

[0056] Furthermore, as shown in Figure 3(B), the reference clock signal line operates at high power supply potential and low power supply potential regardless of the period. This is a wiring that supplies a clock signal that periodically repeats the power supply potential, and the inverting clock signal line is This wiring supplies an inverted clock signal, which is an inverted signal of the clock signal, regardless of the time period.

[0057] Furthermore, the potential of control terminal a becomes H level during the first period (t1), and otherwise During this period, it becomes L level. As a result, the first pulse signal line (PS1) becomes L level during the first period It can function as wiring to supply a clock signal in the interval (t1). In other words, the first period is the period during which the potential of control terminal a is at the H level.

[0058] Similarly, the potentials of control terminals b to f are as follows: 2nd period (t2) to 6th period (t6), respectively. It will be at level H during one of the periods and at level L during the other period. The second pulse signal line is used during the second period, and the third pulse signal line is used during the third period. It functions as a wiring that supplies the clock signal, and the fourth pulse signal line is used in the fourth period. Then, the fifth pulse signal line is used during the fifth period, and the sixth pulse signal line is used during the sixth period. This allows it to function as wiring that supplies an inverted clock signal. In other words, During the second period (t2) to the sixth period (t6), the potentials of control terminals b to f are at the H level. This is the period during which it occurs.

[0059] Also, the first pulse signal line (PS1) to the sixth pulse signal line (PS) shown in Figure 4(A) 6) Each of these is a source of one of the low power supply potential selector transistors 121 to 126. The terminals and drain terminals are electrically connected to the wiring that supplies the low power supply potential (VSS). Here, the low power supply potential selection transistors 121-126 are n-channel type. Let's assume it's a transistor.

[0060] The low power supply potential selection transistor 121 has its gate terminal electrically connected to the control terminal g. The first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal is at a low power supply potential. Electrically connected to the wiring that supplies (VSS). Low power supply potential selector transistor 122 The gate terminal is electrically connected to the control terminal h, and the first terminal is connected to the second pulse signal line (PS 2) is electrically connected, and the second terminal is electrically connected to the wiring that supplies the low power supply potential (VSS). The low power supply potential selection transistor 123 has its gate terminal electrically connected to the control terminal i. The first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is low Electrically connected to the wiring that supplies the power supply potential (VSS). Low power supply potential selection transistor. In terminal 124, the gate terminal is electrically connected to the control terminal j, and the first terminal is connected to the fourth pulse signal. The wire (PS4) is electrically connected, and the second terminal is connected to the wiring that supplies the Low Power Supply (VSS). They are electrically connected. The low power supply potential selection transistor 125 has its gate terminal connected to the control terminal k. Electrically connected, with the first terminal electrically connected to the fifth pulse signal line (PS5), and the second The terminal is electrically connected to the wiring that supplies the low power supply potential (VSS). Low power supply potential selection terminal The transistor 126 has its gate terminal electrically connected to the control terminal l, and the first terminal is connected to the sixth terminal It is electrically connected to the LS signal line (PS6), and the second terminal supplies the low power supply potential (VSS). It is electrically connected to the wiring.

[0061] Furthermore, the potential of the control terminal g becomes L level during the first period (t1), and otherwise... During this period, it becomes H level. As a result, the first pulse signal line (PS1) becomes H level during the first period To function as wiring that supplies a low power supply potential (VSS) during periods other than interval (t1). It is possible.

[0062] Similarly, the potentials of the control terminals h to l are from the second period (t2) to the sixth period (t6), respectively. It becomes L level during that period and H level during the rest of the period. This leads to the second phase The pulse signal line is used during periods other than the second period, and the third pulse signal line is used during periods other than the third period. In between, the fourth pulse signal line is used, and in periods other than the fourth period, the fifth pulse signal line is used. During periods other than the fifth period, the sixth pulse signal line during periods other than the sixth period. It can function as wiring that supplies a low power supply potential (VSS).

[0063] In this embodiment, the shift register is supplied with a clock signal via a single wire. It is not supplied by a single wire, but by multiple wires. Furthermore, one of these multiple wires is used for shifting. Instead of supplying the clock signal throughout the register's operating period, it only supplies it for a portion of the time. It supplies the clock signal. Therefore, the capacitive load driven in conjunction with the supply of the clock signal is reduced. This can be reduced. As a result, the power consumption of the shift register can be reduced.

[0064] <Variation> The shift register described above is just one example of an embodiment, and may differ from the description above. A fast register is also included in this embodiment.

[0065] For example, in the shift register described above, two flip-flops are used for each pulse signal line. The diagram shows an electrically connected shift register (see Figure 1(A)), but each pulse A configuration in which more flip-flops are electrically connected to the signal line is also possible. Specifically, as shown in Figure 5(A), for each pulse signal line, x (where x is 3 or greater) This can be configured with several flip-flops electrically connected.

[0066] Furthermore, the shift register described above has six pulse signal lines. As shown (see Figure 1(A)), a configuration with more pulse signal lines is also possible. Specifically, as shown in Figure 5(B), during a portion of the operating period, the clock... The first pulse signal line (PS1) to the y (where y is a natural number greater than or equal to 4) that supplies the signal. The sludge signal line (PSy) and the inverted clock signal are supplied for a portion of the operating period. The pulse signal lines supplied are the y+1th pulse signal line (PSy+1) to the 2nd y pulse signal line (PS2y) and The configuration includes having two flip-flops electrically connected to each pulse signal line. It is possible.

[0067] Furthermore, the shift register described above uses two flip-flops for each pulse signal line. This describes a shift register that is electrically connected and has six pulse signal lines. (See Figure 1(A)) More flip-flops are electrically connected to each pulse signal line. A configuration with more pulse signal lines may also be used. Specifically, see Figure 5( As shown in C), the first supply of a clock signal during a portion of the operating period. The pulse signal line (PS1) to the pulse signal line (PSy) of the yth (where y is a natural number greater than or equal to 4) And the y+1th pulse that supplies the inverted clock signal for a portion of the operating period. It has a pulse signal line (PSy+1) to a second pulse signal line (PS2y), and each pulse signal This configuration can involve electrically connecting x flip-flops to a single line.

[0068] Furthermore, in the shift register described above, each pulse signal line is electrically connected to a flip-flop. This is shown for shift registers with the same number of rops (Figure 1(A), Figure 5(A)). (See (C)) However, the number of electrically connected flip-flops differs for each pulse signal line. This configuration is also possible. Specifically, as shown in Figure 6(A), the first pulse signal line (P x flip-flops are electrically connected to S1) and the fourth pulse signal line (PS4). Furthermore, the second pulse signal line (PS2) and the fifth pulse signal line (PS5) have z (where z is x This configuration involves electrically connecting two or more (or more) different natural flip-flops. It is possible.

[0069] Furthermore, in the shift register described above, the first pulse signal line (PS1) and the fourth pulse signal line The number of flip-flops electrically connected to each line (PS4) is equal in each shift loop. The zistor is shown (see Figures 1(A), 5(A), and 6(A)), but the first pulse The flip-flop is electrically connected to the signal line (PS1) and the fourth pulse signal line (PS4). The number of lops may be different. Specifically, as shown in Figure 6(B), the first pal x flip-flops are electrically connected to the signal line (PS1), and the fourth pulse signal The wire (PS4) will have a configuration in which x+z flip-flops are electrically connected. It is possible.

[0070] Furthermore, in the shift register described above, there is a first period (t1) and a second period (t2) The case of a non-superimposing shift register is shown (see Figure 1(B)), but the first period (t1) and The configuration may also include a period in which the second period (t2) and the first period overlap. Specifically, see Figure 6. As shown in (C), the period in which the first period (t1) and the second period (t2) overlap is (T The configuration can include ) and so on. To put it simply, as shown in Figures 1(B) and 6(C). To that end, at least one of the multiple pulse signal lines of the shift register is a clock signal It functions as a supply wire and at least one of the multiple pulse signal lines is an inverted clock signal. Each period should be set in such a way that it functions as wiring to supply power.

[0071] Furthermore, the flip-flop circuit configuration shown in Figure 2(A) is just one example, and the input signal... Any circuit configuration is acceptable as long as it delays and outputs the signal. Specifically, see Figure 7( Circuits such as those shown in A) can be applied to the flip-flops of this embodiment. ru.

[0072] The first flip-flop (FF1) shown in Figure 7(A) is connected to transistor 131 to transistor 131. It has transistor 134. Note that here, transistors 131 to 134 Assume that it is an n-channel transistor.

[0073] Transistor 131 has its gate terminal and first terminal electrically connected to the start pulse line. It can be done.

[0074] Transistor 132 has its gate terminal connected to the output terminal of the second flip-flop (FF2). Electrically connected, the first terminal is electrically connected to the second terminal of transistor 131, and Two terminals are electrically connected to the low power supply potential line.

[0075] Transistor 133 has a gate terminal that is the second terminal of transistor 131 and transistor It is electrically connected to the first terminal of 132, and the first terminal is electrically connected to the first pulse signal line (PS1). It connects to the target.

[0076] Transistor 134 has its gate terminal connected to the output terminal of the second flip-flop (FF2). Electrically connected, the first terminal is electrically connected to the second terminal of transistor 133, and the second The terminals are electrically connected to the low power supply potential line.

[0077] For convenience, in the following, we will refer to the second terminal of transistor 131 and transistor 132 The point where the first terminal and the gate terminal of transistor 133 are electrically connected is called node C. Let's do it.

[0078] The operation of the first flip-flop (FF1) shown in Figure 7(A) is described below. This will be explained while referring to B).

[0079] First, the start pulse line electrically connected to the first flip-flop (FF1) The level increases to H level. As a result, the H level signal is passed through the gate of transistor 131. The transistor 131, which is connected to the terminal and the first terminal and is diode-connected, turns on. As a result, the potential of node C increases to the H level. Consequently, transistor 133 also Turn it on. As a result, the potential of the first pulse signal line (PS1) during that period is L. The potential of the bell is output as the output signal (FF1out) of the first flip-flop.

[0080] During the following period, the potential of the start pulse line drops to the L level. Therefore, ZISTA 131 turns off. As a result, node C enters a floating state. At this time, the transistor There is a potential difference between the source terminal and gate terminal of the TA131 ranging from L level to H level. Therefore, because node C is in a floating state, the potential difference is maintained. ZISTA 131 remains on regardless of the potential state of the source terminal. Also, the first pulse The potential of the signal line (PS1) increases to the H level. This causes the floating and traction to... The potential of node C, which is electrically connected to the gate terminal of inverter 133, is the first of the following during the period It is further increased by the H level potential of the pulse signal line (PS1). Therefore, the first The potential of the pulse signal line (PS1), which is at a high level, is the output signal of the first flip-flop. It will be output as code (FF1out).

[0081] Furthermore, the H-level signal which is the output signal of the first flip-flop (FF1) is the second The input is passed to the flip-flop (FF2). Here, the second flip-flop (FF2) ) is the first pulse signal line (P) electrically connected to the first flip-flop (FF1). The first flip-flop is the same except that S1) is replaced with the fourth pulse signal line (PS4). This has the same configuration as (FF1). Therefore, for detailed circuit operation, please refer to the explanation above. It shall be done as follows: During the said period, the second flip-flop (FF2) shall It outputs an L-level potential, which is the potential of the fourth pulse signal line (PS4) in the system.

[0082] During the following period, as the potential of the first pulse signal line (PS1) decreases to the L level... Then the potential of the fourth pulse signal line (PS4) increases to the H level. As a result, the first free The output signal of the pop-flop (FF1out) drops to a low level. Also, the fourth pulse... The potential of the signal line (PS4), which is at an H level, is the output signal (F) of the second flip-flop. Output as F2out)

[0083] The output signal of the second flip-flop (FF2out) is used by the third flip-flop The signal is input to the (not shown) and the transistors of the first flip-flop (FF1) It is also input to the gate terminals of transistor 132 and transistor 134. Therefore, the first When transistors 132 and 134 of the lip-flop (FF1) are turned on This causes the potential of the gate terminal (node ​​C) of transistor 132 to reach an L level. Furthermore, the output signal of the first flip-flop (FF1out) during the said period Transistor 133 receives the first pulse signal (PS1) from the L level, The voltage changes to the low power supply potential (VSS) L level via 4.

[0084] During the following period, the potential of the fourth pulse signal line (PS4) drops to an L level. Consequently, the output signal of the second flip-flop (FF2out) drops to a low level. Therefore, the transistor 132 and transistors of the first flip-flop (FF1) TA134 turns off. Note that this state corresponds to the input terminal of the first flip-flop (FF1). This state is maintained until a high-level potential is input again.

[0085] The first flip-flop (FF1) shown in Figure 7(A) receives input through the operation described above. The signal can be output with a delay of half a clock cycle. Therefore, in this implementation, It can be applied to state flip-flops.

[0086] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be freely combined with other parts.

[0087] (Embodiment 2) In this embodiment, the transistors constituting the shift register shown in Embodiment 1 are suitable An example of a usable transistor is described below.

[0088] An example of the transistor structure in this embodiment will be explained using Figure 8. Figure 8 shows This figure shows an example of the structure of a transistor in this embodiment, and Figure 8(A) shows the transistor This is a top view of the inverter, and Figure 8(B) is a cross-sectional view of the line segment Z1-Z2 in Figure 8(A). ru.

[0089] The transistors shown in Figures 8(A) and 8(B) have a conductive layer 211 on the substrate 201 and An insulating layer 202 on the electrode layer 211, an oxide semiconductor layer 213 on the insulating layer 202, and an oxide semiconductor It has conductive layers 215a and conductive layers 215b on the body layer 213.

[0090] In this transistor, the conductive layer 211 functions as the gate terminal, and the insulating layer 2 02 functions as a gate insulating layer, and one of the conductive layers 215a and 215b is at the source edge. One side functions as a child terminal, and the other functions as a drain terminal. Also, the oxide semiconductor layer 213 is It has a channel formation region. The oxide semiconductor layer 213 is dehydrated or dehydrated during formation. It has undergone a processing treatment.

[0091] Furthermore, the transistors shown in Figures 8(A) and 8(B) have a detachable oxide semiconductor layer 213. In addition to being subjected to aqueous treatment or dehydrogenation treatment, a portion of the oxide semiconductor layer 213 is in contact with An oxide insulating layer 207 is provided. After dehydration or dehydrogenation treatment, the oxide insulating layer Transition using an oxide semiconductor layer 213 on which a border layer 207 is formed as a channel formation region The sta is less prone to threshold voltage (Vth) shifts due to long-term use or high load. Therefore, it is highly reliable.

[0092] Furthermore, a nitride insulating layer may be provided on top of the oxide insulating layer 207. The nitride insulating layer is an oxide insulating layer. The insulating layer 207 is provided below the insulating layer 207 and is in contact with the insulating layer that serves as the base. Preferably, moisture, hydrogen ions, and OH from near the side surface of the substrate are removed. - Impurities such as Blocks entry. In particular, the insulating layer 202 or substrate in contact with the oxide insulating layer 207 It is effective to use a silicon nitride layer as the insulating layer. That is, the lower surface of the oxide semiconductor layer 213, the upper Providing a silicon nitride layer to surround the surface and sides improves the reliability of the transistor.

[0093] Furthermore, on top of the oxide insulating layer 207 (or on top of the nitride insulating layer if a nitride insulating layer is present) A planar insulating layer can also be provided.

[0094] Furthermore, as shown in Figure 8(C), the transistor of this embodiment has an oxide semiconductor layer 21 A portion of 3 is provided with oxide conductive layers 214a and 214b, and oxide conductive A conductive layer 215a is provided so as to be in contact with layer 214a, and is in contact with the oxide conductive layer 214b. A structure in which a conductive layer 215b is provided is also possible.

[0095] The oxide conductive layer 214a and the oxide conductive layer 214b have higher conductivity than the oxide semiconductor layer 213. It has a power ratio, and the source region (also called the low-resistance source region) of transistor 251 and It functions as a drain region (also called a low-resistance drain region).

[0096] Oxide conductive Examples of the film include conductive materials that are transparent to visible light, such as In-Sn-Zn. -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, I n-Sn-O, In-O, Sn-O, and Zn-O metal oxides can be applied. The film thickness is appropriately selected within the range of 1 nm to 300 nm. Furthermore, the sputtering method is used. In this case, film deposition is performed using a target containing 2% to 10% by weight of SiO2, and The photosensitive conductive film is made to contain SiOx (X>0) which inhibits crystallization, and the subsequent de-icing process The oxide semiconductor layer 213 crystallizes during heat treatment for hydration or dehydrogenation. It can be suppressed.

[0097] Furthermore, for example, when using an In-Ga-Zn-O system film as an oxide semiconductor layer, channel formation Oxide semiconductor layer 213 that functions as a region, oxide conductive layer 214a and oxide conductive layer 2 14b and 14b can be produced separately using different film deposition conditions.

[0098] For example, when forming a film using the sputtering method, the oxide semiconductor film is formed in an argon gas atmosphere. The oxide conductive layer 214a and oxide conductive layer 214b have an N-type conductivity, and activated The energy (ΔE) is between 0.01 eV and 0.1 eV.

[0099] In this embodiment, the oxide conductive layer 214a and the oxide conductive layer 214b are I The film is an n-Ga-Zn-O system film and contains at least an amorphous component. Furthermore, crystal grains (nanocrystals) are contained within the oxide conductive layer 214a and the oxide conductive layer 214b. This may include crystal grains (na) in the oxide conductive layer 214a and oxide conductive layer 214b. Nocrystals have a diameter of 1 nm to 10 nm, typically around 2 nm to 4 nm.

[0100] The oxide conductive layer 214a and the oxide conductive layer 214b are not necessarily required, but The oxide semiconductor layer 213, which functions as a channel formation region, and the source terminal and drain terminal Between conductive layer 215a and conductive layer 215b, which function as an oxide conductive layer 214a and an oxide conductive layer 215b By providing the conductive layer 214b, a good electrical junction is obtained, and transistor 251 It can operate stably. Furthermore, it maintains good mobility even at high drain voltages. It can also be done this way.

[0101] Furthermore, the transistors shown in Figures 8(A) and 8(B) are shown in Figures 9(A) and 9(B). As shown, the oxide insulating layer 207 (and the oxide insulating layer 207 if a nitride insulating layer is present) The structure has a conductive layer 217 on top of an oxide semiconductor layer 213 with a nitride insulating layer in between. It is also possible. Figures 9(A) and 9(B) show an example of the transistor structure of this embodiment. This is a diagram showing the top view of the transistor, where Figure 9(A) is a top view of the transistor, and Figure 9(B) is a top view of Figure 9(A). This is a cross-sectional view along the line segment Z1-Z2. The conductive layer 217 is a second gate terminal. It has the ability to apply a second gate voltage to the conductive layer 217 via the second gate terminal. This allows for control of the threshold voltage of transistor 251. Furthermore, the planar insulating layer... If a conductive layer 217 is provided, it is also possible to provide a conductive layer 217 on top of the planar insulating layer.

[0102] For example, if the potential of the second gate terminal is made higher than the potential of the source terminal, The threshold voltage of the transistor is shifted in the negative direction, so that it becomes lower than the potential of the source terminal. As a result, the transistor's threshold voltage shifts in the positive direction.

[0103] As shown in Figures 8 and 9 as an example, the transistor of this embodiment is channel forming This transistor uses an oxide semiconductor in its channel formation region. It has higher mobility compared to conventional transistors using amorphous silicon. Therefore, the shift register composed of these transistors can operate at high speed. .

[0104] Furthermore, regarding one configuration in which multiple transistors are used as shown in Figures 8(A) and 8(C) This will be explained using Figure 10. Figure 10 is applicable to a shift register, which is one embodiment of the present invention. This diagram shows an example of the structure of multiple transistors, and Figure 10(A) shows two transistors. This is a top view, and Figure 10(B) is a cross-sectional view of the line segment X1-X2 in Figure 10(A). .

[0105] Figure 10(A) shows transistors 251 and 252. Here, as an example, we have an oxide semiconductor layer and a conductive material that functions as a source terminal or drain terminal. A structure having an oxide conductive layer between layers is shown.

[0106] Transistor 251 is the transistor shown in Figures 8(A) and 8(C). Therefore, we will refer to the explanation mentioned above here.

[0107] Transistor 252 has a conductive layer 211 on the substrate 201 and an insulating layer 20 on the conductive layer 211. 2, an oxide semiconductor layer 213 on the insulating layer 202, and an oxide conductive layer on the oxide semiconductor layer 213. It comprises layer 214a and oxide conductive layer 214b, and conductive layer 215a and conductive layer 215b. ru.

[0108] In transistor 252, the conductive layer 211 functions as the gate terminal, and the insulating layer Layer 202 functions as a gate insulating layer and has higher conductivity than the oxide semiconductor layer 213. The electrode layer 214a and the oxide conductive layer 214b are source regions (also called low-resistance source regions) or It functions as a drain region (also called a low-resistance drain region), and conductive layer 215a, conductive layer 2 15b functions as a source terminal or drain terminal. Also, the oxide semiconductor layer 213 is It has a channel formation region. The oxide semiconductor layer 213 is dehydrated or dehydrated during formation. It has undergone a processing treatment.

[0109] Furthermore, transistors 251 and 2 shown in Figures 10(A) and 10(B) 52 is a material in which the oxide semiconductor layer is subjected to dehydration or dehydrogenation treatment, as well as the oxide semiconductor layer An oxide insulating layer 207 is provided in contact with a portion of the conductive layer 213 and the oxide semiconductor layer 2132. ru.

[0110] Furthermore, the conductive layer 211 of the transistor 251 is connected through an opening provided in the insulating layer 202. This brings it into contact with the conductive layer 215b. This allows for good contact and reduces contact resistance. This can reduce the number of openings, and thus reduce the occupied area. This can be achieved. Therefore, for example, using two transistors with this structure, a logic circuit It is also possible to configure (for example, an inverter) and so on.

[0111] As shown in Figure 10 as an example, in the shift register shown in Embodiment 1, a certain tra A conductive layer that functions as the gate terminal of the inverter is provided on an insulating layer that functions as the gate insulating layer. Through the opening, the lead acts as the source or drain terminal of another transistor. It can also be structured to be electrically connected to the electrochemical layer.

[0112] Next, an example of a transistor fabrication method shown in Figure 8(B) is illustrated in Figures 11(A) to (D). This will be explained using the following. Figures 11(A) to (D) show the method for fabricating the transistor shown in Figure 8(B). This is a cross-sectional view showing an example.

[0113] In the following, "film" refers to a film formed on the entire surface of the substrate, and later photolithography Items that are processed into a desired shape through processes such as photography are in their pre-processing state. And, a "layer" is a "film" that has been processed into a desired shape through processes such as photolithography. This refers to a formed product, or a product intended to be formed on the entire surface of a substrate.

[0114] First, prepare the substrate 201, form a conductive film on the substrate 201, and then perform the first photolithography. A conductive layer 211 is formed by a graphing process (see Figure 11(A)). The conductive layer 211 is preferably tapered. This allows for improved adhesion with the film in contact with the upper surface.

[0115] As the substrate 201, it is necessary to have an insulating surface and at least heat resistance enough to withstand subsequent heat treatment. As the substrate 201, for example, a glass substrate or the like can be used.

[0116] Also, when the temperature of the subsequent heat treatment is high for the glass substrate, it is preferable to use one with a strain point of 730 °C or higher. Further, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Generally, by including more barium oxide (BaO) compared to boric acid (B2O3), a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0117] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 201. Alternatively, crystallized glass or the like can be used.

[0118] Also, an insulating layer serving as an underlayer may be provided between the substrate 201 and the conductive layer 211. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 201 and can be formed by a layer composed of silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide, or a laminated structure formed by these layers.

[0119] As the material of the conductive film for forming the conductive layer 211, for example, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these can be used, and for forming the conductive layer 211 The conductive film can be formed by a single-layer film or a laminated film of a film containing any one or more of these materials. It can be formed.

[0120] Also, the conductive film for forming the conductive layer 211 has a three-layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminated structure in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer. It is preferable. Of course, it may be a single layer, a two-layer structure, or a laminated structure of four or more layers as the conductive film. In the case of using a laminated conductive film of a titanium film, an aluminum film, and a titanium film as the conductive film, it can be etched by a dry etching method using chlorine gas. It is preferable. Of course, it may be a single layer, a two-layer structure, or a laminated structure of four or more layers. Also, in the case of using a laminated conductive film of a titanium film, an aluminum film, and a titanium film as the conductive film, it can be etched by a dry etching method using chlorine gas. <000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​In this embodiment, as an example, silicon nitride with a film thickness of 200 nm is formed by plasma CVD. An insulating layer 202 is formed by applying a film.

[0124] Next, an oxide semiconductor film is formed on the insulating layer 202. The thickness of the oxide semiconductor film is 2n It is preferable that the film thickness be between m and 200 nm. For example, the film thickness is thinned to 50 nm or less. Therefore, even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the acid It is possible to make oxide semiconductor films amorphous. Furthermore, it is possible to reduce the thickness of oxide semiconductor films. This suppresses crystallization that occurs when the oxide semiconductor film is heat-treated after formation. It is possible.

[0125] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate sputter, and debris adhering to the surface of the insulating layer 202 is removed. This is also acceptable. Reverse sputtering is a method in which voltage is not applied to the target side, but rather to the substrate side in an argon atmosphere. This method involves applying a voltage using an RF power supply to form plasma on the substrate and modify its surface. Nitrogen, helium, oxygen, etc., may be used instead of argon.

[0126] Oxide semiconductor films include In-Ga-Zn-O films, In-Sn-Zn-O films, and In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-Sn-O In this embodiment, oxide semiconductor films of the following types are used: In-O, Sn-O, and Zn-O. The film is deposited by sputtering using an In-Ga-Zn-O metal oxide target. The oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 can be used for film formation, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation in subsequent processes. Here, a metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [at]) is used, and film formation is performed at a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O film by sputtering as the oxide semiconductor film. In addition to the target with the above composition, as the metal oxide target, a composition ratio of In2O3:Ga2O3:ZnO = 1:1:0.5 [mol], In:Ga:Zn = 1 :1:0.25 [at] or In2O3:Ga2O3:ZnO = 1:1:2 [mol], In:Ga:Zn = 1:1:1 [at], etc. can also be used.

[0127] That is, the oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, film formation is carried out using a target containing 2% to 10% by weight of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation in subsequent processes. O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5 [at]) is used, and the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and film formation is performed in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O film by sputtering as the oxide semiconductor film. Here, a metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [at]) is used, and film formation is carried out at a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O film by sputtering as the oxide semiconductor film. Moreover, as the metal oxide target, in addition to the target with the above composition, a composition ratio of In2O3:Ga2O3:ZnO = 1:1:0.5 [mol], In:Ga:Zn = 1 :1:0.25 [at] or In2O3:Ga2O3:ZnO = 1:1:2 [mol], In:Ga:Zn = 1:1:1 [at], etc. can also be used.

[0128] That is, the oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, film formation is carried out using a target containing 2% to 10% by weight of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation in subsequent processes. 、In2O3:Ga2O3:ZnO=1:1:0.5[mol], In:Ga:Zn=1 :1:0.25[at] or In2O3:Ga2O3:ZnO=1:1:2[mol], In:Ga:Zn=1:1:1[at], etc. can also be used.

[0129] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering. There are methods, and there is also the pulsed DC sputtering method, which applies a pulsed bias. RF sputtering The sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal conductive films. It is used in such cases.

[0130] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple layers of different material films in the same chamber. It is also possible to deposit films by simultaneously discharging different materials.

[0131] Furthermore, a sputtering system using a magnetron sputtering method equipped with a magnetic mechanism inside the chamber. ECR spalls, which use microwaves to generate plasma without using glow discharges, are also available. There are sputtering machines that use the T method.

[0132] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas are formed during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the substrate as well.

[0133] Furthermore, a cryopump is preferred as the exhaust method for the deposition chamber where sputtering is performed. It is difficult. By using a cryopump to evacuate the air, impurities such as moisture in the deposition chamber are removed. It is possible to leave.

[0134] Next, the oxide semiconductor film is processed into island shapes by a second photolithography process, A conductive layer 213 is formed (see Figure 11(B)). Note that the second photolithography process Next, the oxide semiconductor layer 213 is placed in an inert gas atmosphere (nitrogen, or helium, neon, or algonium). Heat treatment (400°C or higher but less than 750°C) is performed under conditions such as [unclear], and the contents within the layer are Impurities such as hydrogen and water may be removed.

[0135] Next, the oxide semiconductor layer 213 is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C or higher but less than 750°C, preferably 425°C. That concludes the explanation. Note that if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but if the temperature is 425°C or higher... If the following conditions are met, the heat treatment time should be longer than 1 hour. Here, the heat treatment equipment The substrate is introduced into an electric furnace, one of the furnaces, and the oxide semiconductor layer 213 is subjected to a nitrogen atmosphere. After heat treatment, water and hydrogen are removed from the oxide semiconductor layer 213 without exposure to the atmosphere. To prevent contamination. In this embodiment, the oxide semiconductor layer 213 is dehydrated or dehydrogenated. From the hot temperature, it is slowly cooled using the same furnace until it reaches a temperature sufficient to prevent water from entering again. The mixture is then slowly cooled under a nitrogen atmosphere until the temperature drops by more than 100°C below the heating temperature. The atmosphere is not limited to a nitrogen atmosphere, but can also include inert gas atmospheres such as helium, neon, and argon. In that case, any atmosphere is fine.

[0136] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction from heat sources such as resistance heating elements or The device may include an apparatus that heats the object to be processed by thermal radiation. For example, GRTA(Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal) RTA (Rapid Thermal A A nneal) device can be used. The LRTA device uses halogen lamps, metal halide lamps. Id lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high A device that heats the object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as pressurized mercury lamps. It is a device that performs heat treatment using high-temperature gas. For example, a noble gas such as argon, or nitrogen, reacts with the material being treated through heat treatment. An inert gas is used.

[0137] By heat-treating the oxide semiconductor layer 213 at a temperature of 400°C or higher and less than 750°C, the oxide Dehydration and dehydrogenation of the semiconductor layer are achieved, preventing subsequent re-impregnation with water (H2O). ru.

[0138] Furthermore, in the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the sucrose does not contain water, hydrogen, etc. Also, nitrogen introduced into the heat treatment apparatus Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0139] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 213, the oxide semiconductor When the conductive layer 213 is composed of microcrystalline grains and amorphous regions, or when it is composed of only crystalline grains This can sometimes be the case. For example, microcrystals with a crystallinity of 90% or more, or 80% or more. In some cases, it may become an oxide semiconductor film. Also, the conditions of the first heat treatment or the oxide semiconductor layer Depending on the material of 213, the oxide semiconductor layer 213 may consist only of amorphous regions that do not contain crystal grains. It can also be structured that way.

[0140] The oxide semiconductor layer 213 becomes oxygen-deficient after the first heat treatment, resulting in reduced resistance. The oxide semiconductor film after heat treatment has a higher carrier concentration than the oxide semiconductor film immediately after deposition. Preferably 1 × 10 18 / cm 3 This results in an oxide semiconductor layer having the above carrier concentrations. .

[0141] Furthermore, depending on the conditions of the first heat treatment or the material, the conductive layer 211 may be a microcrystalline layer. Alternatively, it may be a polycrystalline layer. For example, the conductive layer 211 may be indium oxide When using a Z alloy film, it is crystallized by heat treatment at 450°C for 1 hour, and as the conductive layer 211, oxidation Crystallization does not occur when using an indium tin oxide alloy film containing silicon.

[0142] Furthermore, the first heat treatment of the oxide semiconductor layer 213 is performed before processing it into an island-shaped oxide semiconductor layer. This can also be done on oxide semiconductor films. In that case, after the first heat treatment, a heating device or Then the substrate is removed and the photolithography process is performed.

[0143] Next, a conductive film is formed on the insulating layer 202 and the oxide semiconductor layer 213.

[0144] The conductive film may be titanium (Ti), molybdenum (Mo), tungsten (W), aluminum Elements selected from aluminum (Al), chromium (Cr), copper (Cu), and tantalum (Ta) The material, or an alloy containing the aforementioned elements, or a compound combining the aforementioned elements, etc. The conductive film is not limited to a single layer containing the aforementioned elements, but can also be constructed using a laminate of two or more layers. Yes, it is possible. In this embodiment, a titanium film (thickness 100 nm) and an aluminum film (thickness 200 nm) are used. A conductive film is formed with a three-layer structure consisting of a titanium film (thickness 100 nm) and a titanium film (thickness 100 nm). Alternatively, a titanium nitride film may be used.

[0145] Furthermore, if heat treatment at 200°C to 600°C is performed later, the material must have sufficient heat resistance to withstand this heat treatment. It is preferable to have it in a conductive film. For example, an aluminum alloy with added hillock-preventing elements. It is preferable to use gold or a conductive film laminated with a heat-resistant conductive film. This includes sputtering, vacuum deposition (such as electron beam deposition), and arc discharge ion plating. The spraying method is used. In addition, conductive nanopastes such as silver, gold, and copper are used. They may also be formed by extrusion and firing using methods such as clean printing or inkjet printing.

[0146] Next, the resist mask 233a and resist mass are produced by a third photolithography process. Forming 233b, selectively etching the conductive film to form conductive layer 215a and conductive layer 2 Forms 15b (see Figure 11(C)).

[0147] Furthermore, in the third photolithography process, a conductive material is placed on the oxide semiconductor layer 213. It selectively removes only the electrical film. For example, in contact with an In-Ga-Zn-O oxide semiconductor layer. Ammonia peroxide is used as an alkaline etchant to selectively remove only the metal conductive film. If you use water (with a weight ratio of hydrogen peroxide:ammonia:water = 5:2:2), The conductive film is selectively removed, leaving behind an oxide semiconductor layer made of an oxide semiconductor. can.

[0148] Furthermore, depending on the etching conditions, the oxide semiconductor in the third photolithography step... In some cases, the exposed area of ​​layer 213 may be etched. In that case, conductive layer 215a and conductive layer The oxide semiconductor layer in the region sandwiched between 215b is conductive on the conductive layer 211 and conductive layer 215a and conductive The film thickness is thinner compared to the oxide semiconductor layer in the region where layer 215b overlaps.

[0149] Next, an oxide insulating layer 207 is formed on the insulating layer 202 and the oxide semiconductor layer 213. At this stage, a portion of the oxide semiconductor layer 213 comes into contact with the oxide insulating layer 207. The region of the oxide semiconductor layer that overlaps with the conductive layer 211, with 202 in between, becomes the channel formation region.

[0150] The oxide insulating layer 207 has a thickness of at least 1 nm, and is made using methods such as sputtering. This can be formed by using appropriate methods to prevent the introduction of impurities such as water and hydrogen into the marginal layer. In this application method, a silicon oxide film is deposited as an oxide insulating layer using the sputtering method. The substrate temperature should be between room temperature and 300°C, and in this embodiment, it is set to 100°C. The deposition of silicon oxide films by sputtering is performed under a rare gas (typically argon) atmosphere, or under an oxygen atmosphere. This process should be carried out under ambient air, or in a mixed atmosphere of a noble gas (typically argon) and oxygen. This can be done. Furthermore, silicon oxide targets or silicon targets can be used as targets. This can be done. For example, using a silicon target, sputtering can be performed in an oxygen and noble gas atmosphere. Silicon oxide can be formed by this process. It is formed in contact with a low-resistance oxide semiconductor layer. The oxide insulating layer is susceptible to moisture, hydrogen ions, and OH - It does not contain impurities such as these, and these are external Inorganic insulating films are used to block penetration, typically silicon oxide films and silicon nitride films. A film, aluminum oxide film, or aluminum oxide-nitride film is used. The oxide insulating layer formed by this method is particularly dense, suppressing the diffusion of impurities into the adjacent layer. It can be used as a protective film even in a single layer. Furthermore, phosphorus (P) and boron (B) can be added. Using a doped target, phosphorus (P) or boron (B) can also be added to the oxide insulating layer. can.

[0151] In this embodiment, the purity is 6N, and the silicon target is a columnar polycrystalline B-doped material (resistivity value Using a 0.01Ωcm resistor, the distance between the substrate and the target (TS distance) was set to 89mm. Under pressure of 0.4 Pa, DC power supply of 6 kW, and an oxygen atmosphere (oxygen flow rate ratio of 100%), The film will be deposited using the RUSS DC sputtering method. The film thickness will be 300 nm.

[0152] Furthermore, the oxide insulating layer 207 is located on the region that will become the channel formation region of the oxide semiconductor layer 213. It is installed in contact with the channel and also functions as a channel protection layer.

[0153] Next, a second heat treatment (preferably 200°C to 400°C, for example 250°C or higher) The process may be carried out at temperatures below 350°C under an inert gas atmosphere or a nitrogen gas atmosphere. For example A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, A portion of the oxide semiconductor layer 213 is heated while in contact with the oxide insulating layer 207, and oxidation The remaining portion of the semiconductor layer 213 is heated while in contact with the conductive layer 215a and the conductive layer 215b. It can be done.

[0154] The oxide semiconductor layer 213, whose resistance was reduced by the first heat treatment, came into contact with the oxide insulating layer 207. When the second heat treatment is applied in this state, the region in contact with the oxide insulating layer 207 becomes oxygen-rich. As a result, from the region of the oxide semiconductor layer 213 that is in contact with the oxide insulating layer 207, The oxide semiconductor layer 213 is made to have high resistance (type I) in the depth direction (see Figure 11(D)). ).

[0155] The timing of the second heat treatment is immediately after the completion of the third photolithography process. It is not limited to the third photolithography step, and is not particularly limited to any step that is later than the third photolithography step. .

[0156] Based on the above, the transistor shown in Figure 8(B) can be fabricated.

[0157] Furthermore, the contents of this embodiment or a part thereof may differ from the contents of other embodiments or a part thereof. It is possible to combine them freely.

[0158] (Embodiment 3) In this embodiment, the transistors constituting the shift register shown in Embodiment 1 are suitable An example of a transistor different from the transistor shown in Embodiment 2 that can be used is described below. I will reveal it.

[0159] An example of the transistor structure in this embodiment will be explained using Figure 12. Figure 12 is a diagram showing an example of the transistor structure in this embodiment, and Figure 12(A) This is a top view of the transistor, and Figure 12(B) shows the line segment Z1-Z2 in Figure 12(A). This is a cross-sectional view.

[0160] The transistors shown in Figures 12(A) and 12(B) are connected to a conductive layer 211 on the substrate 201. , insulating layer 202 on conductive layer 211, conductive layer 215a and conductive layer 215 on insulating layer 202 b, and the oxide semiconductor layer 213 on the insulating layer 202 and the conductive layer 215a and conductive layer 215b It has the following characteristics.

[0161] In this transistor, the conductive layer 211 functions as the gate terminal, and the insulating layer 2 02 functions as a gate insulating layer, and one of the conductive layers 215a and 215b is at the source edge. One side functions as a child terminal, and the other functions as a drain terminal. Also, the oxide semiconductor layer 213 is It has a channel formation region. The oxide semiconductor layer 213 is dehydrated or dehydrated during formation. It has undergone a processing treatment.

[0162] Furthermore, the transistors shown in Figures 12(A) and 12(B) have an oxide semiconductor layer 213 In addition to being subjected to dehydration or dehydrogenation treatment, a portion of the oxide semiconductor layer 213 is in contact with Then an oxide insulating layer 207 is provided. After dehydration or dehydrogenation treatment, oxidation A tracer was used in which an oxide semiconductor layer 213 on which a material insulating layer 207 was formed was used as a channel formation region. The inverter is less prone to threshold voltage (Vth) shifts due to prolonged use or high load. Therefore, it is highly reliable.

[0163] Furthermore, a nitride insulating layer may be provided on top of the oxide insulating layer 207. The nitride insulating layer is an oxide insulating layer. The insulating layer 207 is provided below the insulating layer 207 and is in contact with the insulating layer that serves as the base. Preferably, moisture, hydrogen ions, and OH from near the side surface of the substrate are removed. - Impurities such as Blocks entry. In particular, the insulating layer 202 or substrate in contact with the oxide insulating layer 207 It is effective to use a silicon nitride layer as the insulating layer. That is, the lower surface of the oxide semiconductor layer 213, the upper Providing a silicon nitride layer to surround the surface and sides improves the reliability of the transistor.

[0164] Furthermore, on top of the oxide insulating layer 207 (or on top of the nitride insulating layer if the above nitride insulating layer is provided) A planar insulating layer can also be provided in the )

[0165] Furthermore, similar to Figures 9(A) and 9(B), the transistor shown in Figure 12 is made of an oxide semiconductor. On the oxide insulating layer 207 in the region overlapping with layer 213 (if the planar insulating layer is provided, then... The structure may also have a conductive layer on top of the flattened insulating layer. The conductive layer is the second gate It functions as a terminal. By applying a second gate voltage to the conductive layer, the terminal The threshold voltage of the inverter can be controlled.

[0166] Note that a planar insulating layer is not always necessary. If a planar insulating layer is not provided, A second gel is placed on the oxide insulating layer 207 (or on the nitride insulating layer if a nitride insulating layer is present). It can also be a structure that has a conductive layer that functions as a terminal.

[0167] For example, if the potential of the second gate terminal is higher than the potential of the source terminal, The threshold voltage of the transistor is shifted in the negative direction, so that it becomes lower than the potential of the source terminal. As a result, the transistor's threshold voltage shifts in the positive direction.

[0168] As shown in Figure 12, the transistor of this embodiment has a source terminal or a drain terminal and A so-called bottom-contact type transistor having an oxide semiconductor layer on a conductive layer that functions as such. This is a transistor. This transistor uses amorphous silicon in the channel formation region. It has higher mobility compared to conventional transistors. Therefore, it is constructed using this transistor. The shift register used can perform high-speed operation. Also, a bottom-contact type shift register... By applying an inverter, the oxide semiconductor layer and the source terminal or drain terminal are configured as follows: This increases the contact area with the conductive layer, preventing peeling and other issues. .

[0169] Furthermore, the contents of this embodiment or a part thereof may differ from the contents of other embodiments or a part thereof. It is possible to combine them freely.

[0170] (Embodiment 4) In this embodiment, the transistors constituting the shift register shown in Embodiment 1 are suitable Transistors other than those shown in Embodiments 2 and 3 are available for use. Let me explain an example.

[0171] An example of the transistor structure in this embodiment will be explained using Figure 13. Figure 13(A) is a diagram showing an example of the transistor structure in this embodiment. This is a top view of the transistor, and Figure 13(B) shows the line segment Z1-Z2 in Figure 13(A). This is a cross-sectional view.

[0172] The transistors shown in Figures 13(A) and 13(B) are similar to the transistors shown in Figure 8. on the substrate 201, there is a conductive layer 211, an insulating layer 202 on the conductive layer 211, and on the insulating layer 202 The oxide semiconductor layer 213 and the conductive layer 215a and conductive layer 215 on the oxide semiconductor layer 213 It has b and

[0173] In this transistor, the conductive layer 211 functions as the gate terminal, and the insulating layer 2 02 functions as a gate insulating layer, and one of the conductive layers 215a and 215b is at the source edge. One side functions as a child terminal, and the other functions as a drain terminal. Also, the oxide semiconductor layer 213 is It has a channel formation region. The oxide semiconductor layer 213 is dehydrated or dehydrated during formation. It has undergone a processing treatment.

[0174] Furthermore, the transistors shown in Figures 13(A) and 13(B) have an oxide semiconductor layer 213 In addition to being subjected to dehydration or dehydrogenation treatment, a portion of the oxide semiconductor layer 213 is in contact with The oxide insulating layer 207 is provided beneath the conductive layer 215a and the conductive layer 215b. Figure 1 The oxide insulating layer 207 shown in 3(A) and Figure 13(B) functions as a channel protection layer. To possess.

[0175] Furthermore, nitride insulating layers are placed on the oxide insulating layer 207 and the conductive layers 215a and 215b. A layer may be provided. The nitride insulating layer extends to the insulating layer 202 provided below the oxide insulating layer 207. Alternatively, it is preferable to have a configuration that is in contact with the underlying insulating layer, and moisture from near the sides of the substrate and , hydrogen ions, OH - It blocks the intrusion of impurities such as oxides. It is effective to use a silicon nitride layer as the insulating layer 202 in contact with layer 207 or as the underlying insulating layer. That is, a silicon nitride layer is provided so as to surround the bottom, top, and side surfaces of the oxide semiconductor layer 213. This improves the reliability of the transistor.

[0176] Furthermore, on the oxide insulating layer 207 and the conductive layer 215a and conductive layer 215b (the above nitride If an insulating layer is to be provided, a planar insulating layer can also be provided on top of the nitride insulating layer.

[0177] Furthermore, on top of the oxide insulating layer 207 (or on top of the planar insulating layer if the planar insulating layer is provided) The structure has a conductive layer on top of the oxide semiconductor layer 213, with an oxide insulating layer 207 sandwiched between them. It is also possible. The conductive layer functions as a second gate terminal. Second gate voltage By applying this to the conductive layer, the threshold voltage of transistor 251 can be controlled. Cut.

[0178] Note that a planar insulating layer is not always necessary. If a planar insulating layer is not provided, On the oxide insulating layer 207 (or on the nitride insulating layer if a nitride insulating layer is present), the conductive It can also be a layered structure.

[0179] For example, if the potential of the second gate terminal is higher than the potential of the source terminal, The threshold voltage of the transistor is shifted in the negative direction, so that it becomes lower than the potential of the source terminal. As a result, the transistor's threshold voltage shifts in the positive direction.

[0180] Furthermore, the transistor of this embodiment, like the transistor shown in Figure 8(C), is oxidized. A pair of oxide conductive layers, which function as a pair of buffer layers, are provided on a portion of the material semiconductor layer 213. The conductive layers 215a and 215a, which are electrodes, are brought into contact with each other, the pair of oxide conductive layers. A structure in which a conductive layer 215b is provided is also possible.

[0181] As described above, the transistor in this embodiment has a chip on a part of the oxide semiconductor layer. This is a so-called channel-protected transistor having an insulating layer that serves as a channel protection layer. The transistor is a conventional transistor that uses amorphous silicon in the channel formation region. It has higher mobility compared to [another transistor]. Therefore, a shift register composed of this transistor... The system can perform high-speed operations.

[0182] Furthermore, the contents of this embodiment or a part thereof may differ from the contents of other embodiments or a part thereof. It is possible to combine them freely.

[0183] (Embodiment 5) In this embodiment, an example of a display device having a shift register as shown in Embodiment 1 is described below. Let's explain using Figure 14.

[0184] The display device having a shift register as shown in Embodiment 1 is a liquid crystal display device or an e Various display devices can be mentioned, such as lectroluminescent (EL) display devices. The configuration of the display device in this embodiment will be explained using Figure 14(A). Figure 1 4(A) is a block diagram showing the configuration of the display device in this embodiment.

[0185] The display device shown in Figure 14(A) comprises a pixel unit 701, a scan line driving circuit 702, and a signal line driving circuit. It has a dynamic circuit 703.

[0186] Furthermore, the pixel section 701 has a dot matrix structure with multiple pixels 704. Physically, multiple pixels 704 are arranged in the matrix direction. Each pixel 704 is a scan line Electrically connected to the scan line drive circuit 702 via 705, and signal line via signal line 706 It is electrically connected to the drive circuit 703.

[0187] The scan line driving circuit 702 is a circuit that selects the pixel 704 that receives the data signal, and A selection signal is output to pixel 704 via the probe line 705.

[0188] The signal line driving circuit 703 is a circuit that outputs data to be written to the pixel 704 as a signal. Then, via the signal line 706, the selected pixel 704 is transmitted to the scan line drive circuit 702. Output "Ta" as a signal.

[0189] Pixel 704 has at least a display element and a switching element. For example, light-emitting elements such as liquid crystal elements or EL elements can be applied, and switching elements For example, transistors can be used as the child component.

[0190] Next, Figure 14(B) shows an example configuration of the scan line drive circuit 702 and the signal line drive circuit 703. We will explain using (C). Figures 14(B) and (C) are block diagrams showing the configuration of the drive circuit. Yes, Figure 14(B) is a block diagram showing the configuration of the scan line drive circuit 702, and Figure 14(C) This is a block diagram showing the configuration of the signal line drive circuit 703.

[0191] As shown in Figure 14(B), the scan line drive circuit 702 has a shift register 900 and a level It has a lucifta 901 and a buffer 902.

[0192] The shift register 900 is used for the start pulse (GSP) for the scan line drive circuit and the scan line drive cycle. A signal such as a road reference clock signal (GCK) is input, and each sequential logic circuit selects sequentially A selection signal is output. The shift register 900 in this embodiment is as shown in Embodiment 1. The reference clock signal (GCK) for the scan line drive circuit is used during a portion of the operating period. It has multiple wires that supply a reference clock signal for the scan line drive circuit.

[0193] The signal line drive circuit 703, as shown in Figure 14(C), is a shift register 903, first A latch circuit 904, a second latch circuit 905, a level shifter 906, a buffer 907, and It has.

[0194] The shift register 903 contains a start pulse (SSP) for the signal line drive circuit and signal line drive A signal such as a circuit reference clock signal (SCK) is input, and each sequential logic circuit processes sequentially A selection signal is output. The shift register 903 in this embodiment is the same as shown in Embodiment 1. For example, the reference clock signal (SCK) for the signal line drive circuit is included in a portion of the operating period. It has multiple wires that supply a reference clock signal for the signal line drive circuit.

[0195] Note that only one of either shift register 900 or shift register 903 will be implemented. The shift register shown in State 1 may also be used.

[0196] The first latch circuit 904 receives a data signal (DATA). The 904 can be constructed using logic circuits.

[0197] Buffer 907 has the function of amplifying the signal and contains an operational amplifier, etc. The 907 can be constructed using logic circuits.

[0198] The second latch circuit 905 can temporarily hold the latch (LAT) signal. The latch signals are simultaneously output to the pixel unit 701 in Figure 14(A). This is called driving. Therefore, if a pixel performs point-sequential driving rather than line-sequential driving, the second ra The latch circuit 905 can be omitted. Also, the second latch circuit 905 is a logic circuit It can be constructed using this method.

[0199] Next, the operation of the display device of this embodiment will be described.

[0200] First, the scan line 705 is selected by the scan line drive circuit 702. The electrically connected pixel 704 receives data from the signal line drive circuit 703 via the signal line 706. A signal is input. As a result, data is written to the pixel 704 and the display status The scan line 705 is selected by the scan line drive circuit 702, and all pixels 704 are... Data writing then takes place. The above describes the operation of the display device in this embodiment.

[0201] All the circuits of the display device shown in Figure 14 can be mounted on the same circuit board. It can be constructed using a single conductive transistor. By placing it on the same substrate... It can be miniaturized, and the process can be simplified by using transistors of the same conductivity type. It is possible.

[0202] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be freely combined with other parts.

[0203] (Embodiment 6) In this embodiment, as an example of a display device shown in Embodiment 5, a liquid crystal display device is described. This will be explained using Figure 15.

[0204] Figure 15(A) shows the circuit diagram of the pixels in the liquid crystal display device of this embodiment. The pixel shown in the diagram comprises a transistor 821, a liquid crystal element 822, and a capacitive element 823. ru.

[0205] Transistor 821 has its gate terminal electrically connected to scan line 804, and its first terminal is a signal It is electrically connected to line 805. Transistor 821 controls the liquid crystal of the pixel. It functions as a select transistor that controls the voltage applied to element 822.

[0206] One terminal of the liquid crystal element 822 is electrically connected to the second terminal of the transistor 821. The other terminal supplies electricity to the wiring (hereinafter also referred to as the common potential line) that provides a common potential (Vcom). They are connected. The liquid crystal element 822 is a first electric element that is part or all of one of the terminals. A pole, a second electrode which is part or all of the other terminal, and between the first electrode and the second electrode A layer having liquid crystal molecules whose orientation changes when a voltage is applied (called a liquid crystal layer) It is composed of [various components].

[0207] Capacitive element 823 has one terminal electrically connected to the second terminal of transistor 821. The other terminal is electrically connected to a common potential line. The capacitive element 823 is connected to one of the terminals A first electrode that is part or all of the other terminal, and a second electrode that is part or all of the other terminal, It is composed of a dielectric layer provided between the first electrode and the second electrode. 823 functions as a pixel retention capacitance. Note that the capacitive element 823 is not necessarily provided. Although it is not necessary, by providing the capacitive element 823, the leakage current of transistor 821 The effects of this can be mitigated.

[0208] In this embodiment, the driving method for the liquid crystal of the liquid crystal display device is TN(Twis (Ted Nematic) mode, IPS (In-Plane-Switching) mode Code, FFS (Fringe Field Switching) mode, MVA (Mu lti-domain Vertical Alignment) mode, PVA(Pa (Vertical Alignment) mode, ASM (Axial (Symmetric aligned Micro-cell) mode, OCB ( Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFL Examples include C (AntiFerroelectric Liquid Crystal). It is possible.

[0209] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Therefore, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears immediately before. The blue phase only appears within a narrow temperature range, so the temperature range needs to be modified. To improve performance, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 100 μs. Its short duration of μs and optical isotropy mean that orientation processing is unnecessary, and it exhibits low dependence on the viewing angle.

[0210] When a signal is input to a pixel, first, the pixel on which the data will be written is selected. When a pixel is detected, the signal input from scan line 804 turns on transistor 821. ru.

[0211] At this time, the data signal from signal line 805 is input to the pixel via transistor 821. The potential of one terminal of the liquid crystal element 822 becomes the potential of the data signal. As a result, the liquid crystal element 822 is set to an orientation state corresponding to the voltage applied between one terminal and the other terminal. After data is written, the signal input from scan line 804 causes transistor 821 to turn on. In the display state, the liquid crystal element 822 maintains the set orientation state for the duration of the display period, and the display state The above operation is performed sequentially for each scan line 804, and for all pixels of the liquid crystal display device The above operation is performed.

[0212] In the display of motion on liquid crystal displays, afterimages occur because the response of the liquid crystal molecules themselves is slow. Alternatively, there is a problem of blurring in the video. In order to improve the video characteristics of liquid crystal display devices, There is a driving technique called black insertion, which involves displaying a black screen every other frame.

[0213] Furthermore, by increasing the normal vertical synchronization frequency by 1.5 times, preferably 2 times or more, the response speed can be increased. There are also drive technologies that improve performance, such as what is called "double-speed drive."

[0214] Furthermore, in order to improve the video characteristics of the liquid crystal display device, multiple LEDs (emitting diodes) are used as the backlight. A surface light source is constructed using a photodiode light source or multiple EL light sources. There is also a driving technology that drives each light source independently and intermittently within a single frame period. Furthermore, you may use three or more types of LEDs, or you may use white-emitting LEDs. Because it can control multiple LEDs, it can synchronize with the switching timing of the optical modulation of the liquid crystal layer. It is also possible to synchronize the timing of the LED illumination. This driving technology partially turns off the LEDs. Because it can be illuminated, this is especially useful for video displays where a large proportion of the screen is black. This can lead to a reduction in power consumption.

[0215] By combining these driving technologies, the display characteristics such as the motion characteristics of liquid crystal displays can be enhanced. It can improve performance compared to conventional methods.

[0216] Next, Figure 15(B) shows the structure of the liquid crystal display device in this embodiment, including the above-mentioned pixels. This will be explained using (C). Figures 15(B) and (C) show the display device in this embodiment. This is a diagram showing the basic structure; Figure 15(B) is a top view of the pixel, and Figure 15(C) is a diagram showing the basic structure. This is a cross-sectional view of A1-A2 and B1-B2 in 5(B).

[0217] The liquid crystal display devices shown in Figures 15(B) and 15(C) have a base in the cross section A1-A2. A conductive layer 2001 on the plate 2000, an insulating layer 2002 on the conductive layer 2001, and an insulating layer 200 2. Oxide semiconductor layer 2003, and conductive layer 2005a and conductive layer on oxide semiconductor layer 2003. The electrode layer 2005b, the conductive layer 2005a, the conductive layer 2005b, and the oxide semiconductor layer 2003 The upper oxide insulating layer 2007 and the conductive layer via an opening provided in the oxide insulating layer 2007 It has a transparent conductive layer 2020 in contact with 2005b.

[0218] The conductive layer 2001 functions as a gate terminal, and the insulating layer 2002 functions as a gate insulating layer. The conductive layer 2005a and conductive layer 2005b function as the first terminal, and the other This functions as a second terminal. Also, here the transistor described in Embodiment 2 Although the transistor (see Figure 8(B)) was applied, the transistor used was as described in Embodiment 3 or the embodiment. It is also possible to apply the transistor shown in Embodiment 4.

[0219] Furthermore, the liquid crystal display devices shown in Figures 15(B) and 15(C) have a cross-section of B1-B2. And, a conductive layer 2008 on the substrate 2000, an insulating layer 2002 on the conductive layer 2008, and an insulating layer An oxide insulating layer 2007 on 2002, and a transparent conductive layer 2020 on the oxide insulating layer 2007. , has.

[0220] Furthermore, the liquid crystal display device of this embodiment is FPC (Flexible Printed) Conductive layer 2022, which functions as an electrode or wiring for connecting to circuits. and transparent conductive layer 2029, conductive layer 2023, conductive layer 2024, and transparent conductive layer 2028 It has the following characteristics.

[0221] Transparent conductive layer 2020, transparent conductive layer 2029, and transparent conductive layer 2028 are made of indioxide. Indium oxide (In2O3) and indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO) The material is formed by sputtering or vacuum deposition using methods such as ( ). The etching process is carried out using a hydrochloric acid-based solution. However, etching ITO in particular generates residue. Because it is easy to etch, indium oxide zinc oxide (In2 O3-ZnO may also be used.

[0222] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be freely combined with other parts.

[0223] (Embodiment 7) In this embodiment, as an example of the display device shown in Embodiment 5, an electroluminescent device is used. A light-emitting display device having a light-emitting element that utilizes a sense will be explained using Figures 16 and 17. do.

[0224] Light-emitting devices that utilize electroluminescence either use organic compounds as the light-emitting material or They are distinguished by whether they are organic or organic compounds; generally, the former are organic EL elements, and the latter are inorganic EL elements. He is called "child."

[0225] Organic EL elements emit electrons and positive voltages from a pair of electrodes when a voltage is applied to the light-emitting element. Each pore is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Light is emitted when the carrier (electrons and holes) recombine. Such light-emitting devices are called current-excited light-emitting devices.

[0226] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements depending on their element configuration. It is classified as follows: Dispersed inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. It possesses a donor-acceptor level, and the luminescence mechanism utilizes donor-acceptor levels. This is acceptor-recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism involves the inner-shell electron transition of metal ions. The localized light emission method used is localized light emission. For this explanation, an organic EL element is used as the light-emitting element. do.

[0227] Figure 16(A) is a circuit diagram showing the circuit configuration of the pixels of the light-emitting display device in this embodiment. be.

[0228] As shown in Figure 16(A), the pixels of the display device in this embodiment are transistors 85 1, a capacitive element 852 that functions as a pixel retention capacitance, and a transistor 853, It has a light-emitting element 854.

[0229] Transistor 851 has its gate terminal electrically connected to scan line 855, and its first terminal is a signal It will be electrically connected to Line 856.

[0230] Capacitive element 852 has one terminal electrically connected to the second terminal of transistor 851. The other terminal is electrically connected to a low power potential line.

[0231] Transistor 853 has its gate terminal connected to the second terminal of transistor 851 and the capacitive element 85 One terminal of 2 is electrically connected, and the first terminal is electrically connected to the low power potential line.

[0232] The light-emitting element 854 has its first terminal electrically connected to the second terminal of the transistor 853, and the Two terminals are electrically connected to the high-power potential line.

[0233] When a signal is input to a pixel, the pixel on which to write data is selected first. The scanned pixels are turned on by the scanning signal input from scan line 855, which turns on transistor 851. In this state, a video signal (also called a data signal) with a predetermined voltage value is sent from signal line 856. This is input to the gate terminal of transistor 853.

[0234] Transistor 853 turns ON based on the potential corresponding to the data signal input to its gate terminal. Alternatively, it turns off. At this time, a mark is made between one terminal and the other terminal of the light-emitting element 854. Current flows according to the applied voltage, and the light-emitting element 854 emits light with a brightness corresponding to the amount of current flowing. Furthermore, the gate voltage of transistor 853 is held for a certain period of time by the capacitive element 852. Therefore, the light-emitting element 854 maintains its light-emitting state for a certain period of time.

[0235] Furthermore, if the data signal input to the pixel from signal line 856 is in digital format, the pixel is The emission state is controlled by switching the lamp on and off. Therefore, area gradation Tones can be displayed using either the area method or the time-based gradation method. Note that the area-based gradation method uses a single area. The element is divided into multiple subpixels, and each subpixel is independently processed using the circuit configuration shown in Figure 16(A). This is a driving method that performs grayscale display by driving based on a signal. This method is a driving technique that performs grayscale display by controlling the duration for which pixels emit light.

[0236] Because light-emitting elements have a higher response speed compared to liquid crystal elements, they are more suitable for time-gradation than liquid crystal elements. Suitable. When displaying using time gradation, one frame period can be divided into multiple subframe periods. The video signal is divided, and the light-emitting elements of the pixels emit light during each subframe period. Control the state. By dividing one frame period into multiple subframe periods, The total length of time during which a pixel actually emits light during a frame is controlled by the video signal. It can display gradations.

[0237] Next, the configuration of the light-emitting element will be explained using Figures 16(B) to 16(D). Now, let's take the case where the transistor 853 is an n-channel type as an example and discuss the cross-sectional structure of the pixels. Let me explain. Note that transistor 853 is used in the light-emitting display device shown in Figures 16(B) to (D). This is a drive transistor.

[0238] The light-emitting element 854 has at least one of its electrodes, either the anode or the cathode, that is transparent in order to extract light. Then, form the transistor and light-emitting element on the substrate, and from the side opposite to the substrate... Top emission to extract light, bottom emission to extract light from the substrate side, and the substrate side and the substrate The present invention has a double-sided emission light-emitting element that extracts light from the opposite side, and the pixel configuration of the present invention is It can be applied to any light-emitting element with an injection structure.

[0239] The light-emitting element with an upper surface injection structure will be explained using Figure 16(B).

[0240] Figure 16(B) shows that the drive transistor, transistor 853, is an n-channel type, and This shows a cross-sectional view of the pixel when the light emitted from the optical element 854 passes through to the anode 7005. Figure 16(B) shows the cathode 7003 of the light-emitting element 854 and the drive transistor. The sta 853 is electrically connected, with the light-emitting layer 7004 on the cathode 7003 and the anode 7005 These are stacked in order. The cathode 7003 is a conductive layer with a small work function and that reflects light. If so, various materials can be used. For example, Ca, Al, CaF, MgAg, A LiLi is preferable. And even if the light-emitting layer 7004 is composed of a single layer, multiple It doesn't matter whether the layers are stacked or not. On cathode 7003, in the order of electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole injection layer It is stacked on top of each other. Note that it is not necessary to provide all of these layers. The anode 7005 is a light-transmitting transparent Formed using a photosensitive conductive material, for example, indium acid containing tungsten oxide Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide containing titanium oxide, also known as ITO (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide with added silicon oxide, etc., which are translucent. A conductive material can be used.

[0241] The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 is the light-emitting element 854. Corresponds to the pixel shown in Figure 16(B), where the light emitted from the light-emitting element 854 is indicated by the arrow. As shown, it is injected towards the anode 7005 side.

[0242] Next, a light-emitting element with a bottom-extrusion structure will be explained using Figure 16(C). Transistor 853 is an n-channel type, and the light emitted from the light-emitting element 854 is emitted towards the cathode 7013. A cross-sectional view of the pixel in this case is shown. In Figure 16(C), the transistor 853 is electrically connected. A cathode 7013 of a light-emitting element 854 is formed on a light-transmitting conductive layer 7017. The light-emitting layer 7014 and the anode 7015 are stacked in order on the cathode 7013. If 015 is translucent, a shielding material to reflect or block light should be used to cover the anode. Layer 7016 may be formed. The cathode 7013 is as in the case of Figure 16(B). Various materials can be used as long as the conductivity function is small. However, the film thickness The wavelength should be such that it transmits light (preferably around 5 nm to 30 nm). For example, 20 nm An aluminum layer having a thickness of [a certain amount] can be used as the cathode 7013. The optical layer 7014, as in Figure 16(B), may consist of a single layer, or multiple layers may be stacked. It doesn't matter whether it's configured that way or not. The anode 7015 does not need to transmit light. However, as shown in Figure 16(B), it can be formed using a light-transmitting conductive material. The shielding layer 7016 can be made of, for example, a metal that reflects light, but if it is made of metal... It is not limited to this. For example, resin with black pigment added can also be used.

[0243] The region between the cathode 7013 and anode 7015, sandwiching the light-emitting layer 7014, is the light-emitting element 854. This corresponds to the pixel shown in Figure 16(C), where the light emitted from the light-emitting element 854 is the arrow. As indicated by the mark, the injection is directed towards the cathode 7013 side.

[0244] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 16(D). Figure 16(D In this case, on the light-transmitting conductive layer 7027 that is electrically connected to the transistor 853, The cathode 7023 of the optical element 854 is formed by depositing a film, and the light-emitting layer 7024 and anode are on the cathode 7023. The 7025s are stacked in order. The cathode 7023 is work-related, as in the case of Figure 16(B). For conductive materials with a small number of particles, various materials can be used. However, the film thickness is... The material should be transparent to light. For example, an aluminum layer with a thickness of 20 nm is used as cathode 702. It can be used as 3. And the light-emitting layer 7024 is single, as in Figure 16(B). It can be composed of a single layer or multiple layers stacked on top of each other; either is fine. The anode 7025 uses a conductive material that is translucent and transmits light, similar to Figure 16(B). It can be formed by doing so.

[0245] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap is the light-emitting element 8 This corresponds to 54. In the case of the pixel shown in Figure 16(D), the light emitted from the light-emitting element 854 is As indicated by the arrows, the material is injected into both the anode 7025 side and the cathode 7023 side.

[0246] Here, we have discussed organic EL elements as light-emitting elements, but inorganic elements can also be used as light-emitting elements. It is also possible to incorporate EL elements.

[0247] In this embodiment, the transistor that controls the driving of the light-emitting element (driving transistor) An example was shown where a light-emitting element (also called a transistor) is electrically connected to a driving transistor. Alternatively, a current control transistor may be connected between the light-emitting element and the light-emitting element.

[0248] Next, regarding the appearance and cross-section of the light-emitting display device (also called a light-emitting panel) in this embodiment... Next, we will explain using Figure 17. Figure 17(A) shows the transistor formed on the first substrate Top view of a light-emitting device in which a light-emitting element and a second substrate are sealed together with a sealing material. Therefore, Figure 17(B) corresponds to the cross-sectional view at HI in Figure 17(A).

[0249] Pixel section 4502, signal line driving circuit 4503a, 45 provided on the first substrate 4501 03b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 450 5 is provided. Also, pixel section 4502, signal line driving circuits 4503a, 4503b, A second substrate 4506 is provided on top of the scan line drive circuits 4504a and 4504b. In other words, the pixel unit 4502, the signal line drive circuits 4503a and 4503b, and the scan line drive circuit Lines 4504a and 4504b connect the first substrate 4501, the sealing material 4505, and the second substrate. It is sealed together with the filler 4507 by 4506. In this way it is not exposed to the outside air. A protective film with high airtightness and minimal degassing (laminated film, UV curing) is used to prevent this. It is preferable to package (enclose) the product with a cover material such as a resin film.

[0250] Furthermore, the first substrate 4501 is provided with a pixel section 4502 and a signal line driving circuit 4503a. , 4503b, and the scan line driving circuits 4504a and 4504b have multiple transistors. In Figure 17(B), the transistor 4510 included in the pixel section 4502 and the signal line The transistors 4509 and 4555 included in the drive circuit 4503a are shown as examples. It is.

[0251] Transistors 4509, 4510, and 4555 include an oxide semiconductor layer as the semiconductor layer. By applying any of the transistors shown in the highly reliable embodiments 2 to 4... This can be done. In this embodiment, transistors 4509, 4510, and 4555 are n-type It is a channel type. Also, an insulating layer 45 is placed on top of transistors 4509, 4510, and 4555. 42 is formed, and an insulating layer 4544 is formed on top of the insulating layer 4542, and the insulating layer 4542 and A conductive layer 4540 is located on top of the transistor 4509, with an insulating layer 4544 in between. 4540 functions as a second gate terminal.

[0252] Furthermore, in the pixel section 4502, a planar insulating layer 4545 is provided on the insulating layer 4542. Furthermore, an insulating layer 4543 is provided on the flattened insulating layer 4545.

[0253] Furthermore, 4511 corresponds to a light-emitting element, and the first pixel electrode of the light-emitting element 4511 Electrode 4517 is electrically connected to the second terminal of transistor 4510. The configuration of the optical element 4511 is a first electrode 4517, a light-emitting layer 4512, and a second electrode 4513. Although it is a laminated structure, it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed to match the direction of the emitted light.

[0254] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0255] Even if the light-emitting layer 4512 consists of a single layer, it is configured so that multiple layers are stacked. Either way is fine.

[0256] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electric A protective layer may be formed on the pole 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer. This forms a silicon nitride oxide layer, a DLC layer (Diamond-like Carbon), etc. It is possible.

[0257] Also, signal line drive circuits 4503a, 4503b, scan line drive circuits 4504a, 4504 b, or the various signals and voltages applied to the pixel unit 4502 are FPC4518a, 451 It is supplied from 8b.

[0258] In the light-emitting display device shown in Figure 17, the connection terminal electrode 4515 is located on the light-emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the first electrode 4517, The source electrode and drain electrode of transistors 4509, 4510, and 4555 are as follows: It is formed from the same conductive film as the conductive film on which the functional conductive layer is formed.

[0259] The connecting terminal electrode 4515 has terminals on FPC 4518a and an anisotropic conductive layer 4519 They are electrically connected via [a certain means].

[0260] The substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. In that case, the substrate may be glass, plastic, polyester film or A light-transmitting material, such as acrylic film, is used.

[0261] Furthermore, in addition to inert gases such as nitrogen and argon, filler material 4507 also contains UV-curable gases. Resins or thermosetting resins can be used, such as PVC (polyvinyl chloride) and acrylic. Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. This embodiment uses filler 450 Nitrogen is used as the element 7.

[0262] Additionally, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plates) may be placed on the emission surface of the light-emitting element. ), phase difference plates (λ / 4 plate, λ / 2 plate), color filters, and other optical films are appropriately provided. Alternatively, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, surface irregularities This allows for an anti-glare treatment that diffuses reflected light and reduces glare.

[0263] Signal line drive circuits 4503a, 4503b, and scan line drive circuits 4504a, 4504b It is formed on a separately prepared substrate using a single-crystal semiconductor layer or a polycrystalline semiconductor layer. A drive circuit may be implemented. Also, if only the signal line drive circuits 4503a and 4503b are implemented, or only part of the scan line drive circuits 4504a and 4504b, or only a part of them, can be separately configured This embodiment may be implemented in any way, and is not limited to the configuration shown in Figure 17.

[0264] By following the above steps, a light-emitting display device (display panel) can be manufactured.

[0265] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be freely combined with other parts.

[0266] (Embodiment 8) In this embodiment, as an example of the display device shown in Embodiment 5, an external connection such as an FPC is used. Electronic paper that can display information without requiring additional wiring will be explained using Figures 18 and 19. ru.

[0267] In this embodiment, the electronic paper has a period during which the image is retained (image retention period) and an image It has a period during which it can be rewritten (image rewriting period). Furthermore, during the said image retention period Therefore, it does not require power to maintain image display. It is a power-efficient display device.

[0268] The electronic paper in question is a display element whose display can be controlled by the application of voltage, and the voltage can also be used to mark It has an element that holds the display when no power is applied. For example, the element is an electric Devices that use pneumophoresis (electrophoretic devices), particle rotation devices that use twisted balls, charged toners - Particle movement elements using electronic powder fluid (registered trademark), and magnetic electrophoresis that expresses gradation using magnetism. Examples include moving elements, liquid moving elements, light scattering elements, and phase change elements. As an example of electronic paper, we will describe electronic paper having an electrophoretic element.

[0269] As an electrophoretic element, a first particle is positively charged, and another particle exhibits a different color from the first particle. Furthermore, a microcapsule containing a second particle that is negatively charged and a liquid solvent is formed. Examples include elements that possess such elements. When a voltage is applied to the electrophoretic element, The label is made by assembling the first or second particles on one side of the Kurocapsule. This is possible. Furthermore, when no voltage is applied to the electrophoretic display element, the first particle The first and second particles do not move. In other words, the display of the electrophoretic element remains unchanged. As a gas electrophoresis element, it consists of particles that are positively or negatively charged, and a substance that exhibits a different color from the particles and dissolves. Elements having microcapsules containing a liquid medium can also be used.

[0270] Furthermore, the positively or negatively charged particles enclosed within the microcapsules are conductive. Body materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials A type of material selected from necessitate materials, electrochromic materials, and magnetophoretic materials, These composite materials can be used.

[0271] Next, an example of the structure of electronic paper in this embodiment will be described using Figure 18. Oh, Figure 18(A) is a circuit diagram of an electronic paper pixel, and Figure 18(B) is above the pixel. This is a top view, and Figure 18(C) is a cross-sectional view corresponding to line AB in Figure 18(B).

[0272] In this embodiment, the pixels of the electronic paper have gate terminals electrically connected to scan lines 630. The first terminal of transistor 601 is electrically connected to signal line 631, and the other terminal is connected to transistor 601. The second terminal of the converter 601 is electrically connected, and the other terminal is electrically connected to the common potential line. Capacitive element 602, and one terminal of the capacitor element 601 is connected to the second terminal of transistor 601. An electric wire is electrically connected to one terminal of 2, and the other terminal is electrically connected to a common potential line. It has an electrophoretic element 603 (see Figure 18(A)). In this embodiment, the common electric Place (V com Examples of ground potential include 0V.

[0273] Structurally, the pixel consists of a substrate 600 and a transistor 6 provided on the substrate 600. 01 and the capacitive element 602, and the electric provided on the transistor 601 and the capacitive element 602 It has an electrophoretic element 603 and a substrate 604 provided on the electrophoretic element 603 (Figure 18( See B) and (C). Note that the electrophoretic element 603 is omitted in Figure 18(B).

[0274] Transistor 601 has a conductive layer 610 electrically connected to the scan line 630, and a conductive layer 6 10 is an insulating layer 611, a semiconductor layer 612 is on the insulating layer 611, and a signal is on the semiconductor layer 612. It is composed of conductive layers 613 and 614 electrically connected to wire 631. Oh, the conductive layer 610 functions as a gate terminal, and the insulating layer 611 functions as a gate insulating layer. The conductive layer 613 functions as the first terminal, and the conductive layer 614 functions as the second terminal. The conductive layer 610 is part of the scan line 630, and the conductive layer 613 is part of the signal line 631. It can also be expressed as "there is / are."

[0275] The capacitive element 602 is electrically connected to the conductive layer 614, the insulating layer 611, and the common potential line 632. It is composed of a conductive layer 615 that is connected to it. The conductive layer 614 is used as one of the terminals. The insulating layer 611 functions as a dielectric, and the conductive layer 615 functions as the other terminal. Furthermore, the conductive layer 615 can also be described as part of the common potential line 632.

[0276] The electrophoretic element 603 emits electricity to the conductive layer 614 at an opening in the insulating layer 620. A pixel electrode 616 is precisely connected to a counter electrode 617 that is given the same potential as the conductive layer 615. And, in the layer 618 containing charged particles provided between the pixel electrode 616 and the counter electrode 617 Thus it is constructed. Note that the pixel electrode 616 functions as one terminal, and the opposing electrode 617 is It functions as the other terminal.

[0277] The electronic paper of this embodiment controls the voltage applied to the layer 618 containing charged particles. By doing so, the movement of charged particles dispersed in the layer 618 containing charged particles can be controlled. This is possible. Furthermore, in this embodiment, the electronic paper has a light-transmitting counter electrode 617 and substrate 604. It has. In other words, the display device of this embodiment is a reflective display with the substrate 604 side as the display surface. It is a display device.

[0278] The following lists the materials applicable to each component of the electronic paper of this embodiment.

[0279] The substrate 600 can be a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), or an SOI substrate. Glass substrate, quartz substrate, conductive substrate with an insulating layer on its surface, or plastic substrate Flexible substrates such as laminated films, paper containing fibrous materials, or base films. Examples include barium borosilicate glass and aluminobosilicate glass. Examples include acidic glass or soda-lime glass. An example of a flexible substrate is polyethylene. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfate Plastics such as PES, or flexible synthetic resins such as acrylic. These are some examples.

[0280] The conductive layer 610, conductive layer 615, scanning line 630, and common potential line 632 are made of aluminum. Um (Al), Copper (Cu), Titanium (Ti), Tantalum (Ta), Tungsten (W), Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The element that was exposed, an alloy containing the above-mentioned element, or a nitride containing the above-mentioned element It can be applied. Furthermore, a laminated structure of these materials can also be applied.

[0281] The insulating layer 611 can be silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride Insulators such as nitrile, aluminum oxide, and tantalum oxide can be used. These materials can also be applied in a layered structure. Note that silicon oxidnitride is a compound of these materials. As a component, it has a higher oxygen content than nitrogen, with an oxygen concentration range of 55-65%. Atomic percent, nitrogen 1-20 atomic percent, silicon 25-35 atomic percent, hydrogen 0.1-10 atomic percent This refers to a substance that contains each element at any concentration such that the total amount of each element is 100 atomic percent within a given percentage range. Furthermore, silicon nitride is a material whose composition contains more nitrogen than oxygen. Yes, the concentration range is 15-30 atomic percent for oxygen, 20-35 atomic percent for nitrogen, and 25- Each component is formulated to have a total of 100 atomic percent, with 35 atomic percent of hydrogen and 15-25 atomic percent of hydrogen. This refers to substances that contain elements at any given concentration.

[0282] The semiconductor layer 612 is made of periodic materials such as silicon (Si) or germanium (Ge). Materials whose main constituent elements are the elements of Group 14 of the Table, silicon germanium (SiGe), or Compounds such as lium arsenide (GaAs), zinc oxide (ZnO), or indium (In) and oxides such as zinc oxide containing gallium (Ga), or organic compounds exhibiting semiconductor properties. Any semiconductor material can be applied. Also, a stacked structure of layers made of these semiconductor materials. It is also possible to apply construction techniques.

[0283] The conductive layer 613, conductive layer 614 and signal line 631 are made of aluminum (Al), copper ( Cu, Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo) , an element selected from chromium (Cr), neodymium (Nd), scandium (Sc), or Applying an alloy containing the aforementioned elements, or a nitride containing the aforementioned elements. This is possible. Furthermore, a layered structure of these materials can also be applied.

[0284] The insulating layer 620 may be silicon oxide, silicon oxide nitride, silicon nitride, or silicon nitride. Insulators such as silicon dioxide, aluminum oxide, and tantalum oxide can be used. Polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic Alternatively, organic materials such as epoxy, siloxane materials such as siloxane resin, or oxazole resin Lipids and other substances can also be applied. Note that siloxane materials contain Si-O-Si bonds. It corresponds to a material. Siloxanes have a skeletal structure formed by the bonding of silicon (Si) and oxygen (O). This is achieved. Substituents include organic groups (e.g., alkyl groups, aromatic hydrocarbons) and fluoro groups. It may be used. The organic group may have a fluoro group.

[0285] The pixel electrode 616 can be made of aluminum (Al), copper (Cu), titanium (Ti), or tan. Talc (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium ( Elements selected from Nd (Nd) and scandium (Sc), or alloys containing the above elements. Alternatively, nitrides containing the aforementioned elements can be applied. A layered structure can also be applied. Furthermore, indium oxide containing tungsten oxide can also be used. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide, indium zinc oxide, acid By applying transparent conductive materials such as indium tin oxide with added silicon dioxide, It can also be done this way.

[0286] The charged particles contained in the layer 618 containing charged particles include positively charged particles such as acid Titanium oxide and carbon black can be applied as negatively charged particles. Electroelectric materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electro A type of material selected from mineescent materials, electrochromic materials, and magnetophoretic materials, Alternatively, these composite materials can also be applied.

[0287] The counter electrode 617 is an indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide, titanium oxide containing Indium tin oxide, indium tin oxide, indium zinc oxide, and silicon oxide are added. A transparent conductive material such as indium tin oxide can be applied.

[0288] Substrate 604 may be barium borosilicate glass, aluminobrosilicate glass, or The substrate is a glass substrate such as soda-lime glass, or polyethylene terephthalate (PET). A translucent substrate, such as any flexible substrate, can be used.

[0289] Furthermore, the electronic paper of this embodiment can be used in any field as long as it displays information. It can be used in devices. For example, it can be used to create ebooks (e-books) using electronic paper. , posters, in-vehicle advertisements such as trains, and various cards such as credit cards It can be applied to displays, etc. An example of an electronic device is shown in Figure 19. Figure 19 is an e-book. An example of 2700 is shown.

[0290] As shown in Figure 19, the e-book 2700 consists of two casings, casing 2701 and casing 2703. It is composed of a housing. Housings 2701 and 2703 are integrated by a shaft portion 2711. The shaft portion 2711 is configured to allow opening and closing operations to be performed using the shaft as an axis. This will allow it to behave more like a physical book.

[0291] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 19), and the left-hand display... An image can be displayed on the unit (display unit 2707 in Figure 19).

[0292] Furthermore, Figure 19 shows an example in which the housing 2701 is equipped with an operating section, etc. In 2701, the power switch 2721, operation keys 2723, speaker 2725, etc. It is equipped with this feature. Pages can be turned using operation key 2723. Note that the display unit of the casing is the same as the display unit. The configuration may include a keyboard and pointing device on one side. External connection terminals (earphone jack, USB terminal, or AC adapter terminal) are located on the back or sides of the body. (and terminals that can connect to various cables such as USB cables), recording media insertion slots, etc. It may also be configured to include these features. Furthermore, the eBook 2700 may be equipped with the functionality of an electronic dictionary. This configuration is also acceptable.

[0293] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. The system will be configured to purchase and download desired book data from an e-book server. It is also possible.

[0294] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be combined with other parts.

[0295] (Embodiment 9) The display devices shown in Embodiments 5 to 8 above are used in various electronic devices (gaming machines) It can be applied to (including) electronic devices. For example, television equipment (tele TVs (also called television receivers), monitors for computers, digital cameras Digital video cameras, digital photo frames, mobile phones (mobile phones, cell phones) Large devices (also called machines), portable game consoles, personal information terminals, sound playback devices, pachinko machines, etc. Game consoles are one example.

[0296] Figure 20(A) shows an example of a television system. The television system 9600 is The display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays images. It is possible to demonstrate this. Furthermore, here, the stand 9605 supports the housing 9601. This shows the configuration.

[0297] The television unit 9600 is operated using the control switches on the housing 9601, as well as a separate unit. This can be done using the remote control unit 9610. The remote control unit 9610 has an operating key -9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can control the remote control. A display unit 9607 may be provided to display information output from the unit 9610.

[0298] The television system 9600 will consist of a receiver, modem, and other components. This allows for the reception of regular television broadcasts, and furthermore, wired or wireless connections are available via the modem. By connecting to a communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to perform two-way information communication (between a sender and receiver, or between receivers, etc.). .

[0299] Figure 20(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 incorporated into the housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function just like a regular picture frame.

[0300] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, U It includes terminals that can connect to various cables such as SB cables, and a recording medium insertion section. These components may be integrated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include this feature as it improves the design. For example, the recording of a digital photo frame. Insert a memory device containing image data taken with a digital camera into the media insertion slot. Data can be captured, and the captured image data can be displayed on the display unit 9703.

[0301] Furthermore, the 9700 digital photo frame can also be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0302] Figure 21(A) shows a portable gaming machine, consisting of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display The unit 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. Also, The portable gaming machine shown in Figure 21(A) also includes a speaker 9884 and a recording medium insertion section 988. 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration (Including devices that measure motion, odor, or infrared radiation), microphones (9889), etc. It is equipped with. Of course, the configuration of portable gaming machines is not limited to those described above, and at least displays Any configuration that includes the device is acceptable, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in Figure 21(A) has a program or data recorded on the recording medium. It has functions to read data and display it on the display unit, and to communicate wirelessly with other portable gaming machines to exchange information. It has a sharing function. However, the functions of the portable gaming machine shown in Figure 21(A) are not limited to this. It is not fixed and can have various functions.

[0303] Figure 21(B) shows an example of a slot machine, which is a large-scale gaming machine. The 9900 has a display unit 9903 integrated into the casing 9901. Also, a slot machine... The 9900 also features other operating mechanisms such as a start lever and stop switch, and a coin slot. It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is as described above. The configuration is not limited to, and may include at least the display device shown in the above embodiment. In addition, the configuration may include other auxiliary equipment as appropriate.

[0304] Figure 22(A) shows an example of a mobile phone. The mobile phone 9000 has a casing 900 In addition to the display unit 9002 incorporated into 1, there are also operation buttons 9003, an external connection port 9004, It is equipped with speaker 9005, microphone 9006, etc.

[0305] The mobile phone 9000 shown in Figure 22(A) allows the user to touch the display unit 9002 with their finger or the like. Information can be entered. Furthermore, operations such as making phone calls or sending emails are displayed. This can be done by touching part 9002 with a finger or the like.

[0306] The display unit 9002 has three main modes. The first mode is for displaying images. The primary display mode is the second mode, which is primarily an input mode for entering information such as characters. It is. The third mode is a mix of two modes: display mode and input mode. It's in power mode.

[0307] For example, when making a phone call or composing an email, the display unit 9002 is primarily used for text input. In this text input mode, you can simply input the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 9002. It's nice.

[0308] Furthermore, the 9000 mobile phone has internal sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device with a s-type sensor, the orientation (vertical or horizontal) of the mobile phone 9000 can be determined. The display unit 9002 can be configured to automatically switch screen displays.

[0309] Furthermore, the screen mode can be switched by touching the display unit 9002 or by operating the housing 9001. This is done by operating the action button 9003. Also, the type of image displayed on the display unit 9002 It can also be configured to switch between modes. For example, the image displayed on the display unit 9002 If the number is video data, switch to display mode; if it's text data, switch to input mode. .

[0310] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 9002 is detected, and the display If there is no input via touch operation on the display unit 9002 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from the "Do" display mode to the "Display Mode".

[0311] The display unit 9002 can also function as an image sensor. For example, the display unit 9 By touching the palm or fingers to device 002 and capturing images of palm prints, fingerprints, etc., personal authentication can be performed. Furthermore, the display unit may have a backlight that emits near-infrared light or a sensing device that emits near-infrared light. Using a suitable light source, it is also possible to image finger veins, palmar veins, and other veins.

[0312] Figure 22(B) is also an example of a mobile phone. The mobile phone in Figure 22(B) has a casing 9411 The display device 9410 includes a display unit 9412 and an operation button 9413, and a housing 9401 Control buttons 9402, external input terminal 9403, microphone 9404, speaker 94 The device includes 05, and a communication device 9400 which includes a light-emitting unit 9406 that emits light when an incoming call is received. The display device 9410, which has a display function, is connected to the communication device 9400, which has a telephone function, in two directions indicated by the arrows. It is detachable. Therefore, the short axes of the display device 9410 and the communication device 9400 are connected. It is also possible to mount the long axes of the display device 9410 and the communication device 9400 together. Furthermore, if only the display function is required, the display device 9410 can be removed from the communication device 9400. The display device 9410 can also be used independently. (Communication device 9400 and display device 9410) This means that images or input information can be exchanged via wireless or wired communication, and each It has a rechargeable battery.

[0313] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or a part thereof. It can be combined with other parts. [Explanation of symbols]

[0314] 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 111 Transistor for selecting clock signal 112 Transistors for selecting clock signals 113 Transistor for selecting clock signal 114 Transistor for clock signal selection 115 Transistor for selecting clock signal 116 Transistors for selecting clock signals 121 Transistor for selecting low power supply potential 122 Transistor for Low Power Supply Potential Selection 123 Transistor for selecting low power supply potential 124 Transistor for selecting low power supply potential 125 Transistor for selecting low power supply potential 126 Transistor for selecting low power supply potential 131 transistors 132 transistors 133 transistors 134 transistors 201 circuit board 202 Insulating layer 207 Oxide insulating layer 211 Conductive layer 213 Oxide semiconductor layer 214a Oxide conductive layer 214b Oxide conductive layer 215a conductive layer 215b Conductive layer 215c conductive layer 217 Conductive layer 233a Resist Mask 233b Resist Mask 251 transistors 252 transistors 600 circuit boards 601 Transistors 602 Capacitive element 603 Electrophoresis element 604 circuit board 610 Conductive layer 611 Insulating layer 612 Semiconductor layer 613 Conductive layer 614 Conductive layer 615 Conductive layer 616 pixel electrodes 617 Counter electrode 618 Layer containing charged particles 620 Insulating layer 630 scan lines 631 signal line 632 Common potential line 701 pixel section 702 Scan Line Drive Circuit 703 Signal Line Drive Circuit 704 pixels 705 scan lines 706 signal line 804 scan lines 805 signal line 821 Transistors 822 liquid crystal elements 823 Capacitive element 851 Transistors 852 Capacitive elements 853 Transistors 854 Light-emitting element 855 scan lines 856 Signal Line 900 Shift Registers 901 Level Shifter 902 buffer 903 Shift Register 904 Latch Circuit 905 Latch Circuit 906 Level Shifter 907 buffer 2000 circuit boards 2001 Conductive layer 2002 Insulating layer 2003 Oxide semiconductor layer 2005a conductive layer 2005b conductive layer 2007 Oxide insulating layer 2008 Conductive layer 2020 Transparent conductive layer 2022 Conductive layer 2023 Conductive layer 2024 Conductive layer 2028 Transparent conductive layer 2029 Transparent conductive layer 2112 conductive layer 2132 Oxide semiconductor layer 2142a Oxide conductive layer 2142b Oxide conductive layer 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power switch 2723 Operation Keys 2725 Speaker 4501 circuit board 4502 pixel section 4503a Signal Line Drive Circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4505 Sealant 4506 circuit board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light-emitting element 4512 Emitting layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4542 Insulating layer 4543 Insulating layer 4544 Insulating layer 4545 Planarized insulating layer 4555 transistor 7003 Cathode 7004 Emitting layer 7005 Anode 7013 Cathode 7014 Emitting layer 7015 Anode 7016 Shielding layer 7017 Conductive layer 7023 Cathode 7024 Emitting layer 7025 Anode 7027 Conductive layer 9000 mobile phones 9001 enclosure 9002 Display section 9003 Operation Buttons 9004 External connection port 9005 Speaker 9006 Microphone 9400 Communication equipment 9401 enclosure 9402 Operation Buttons 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 cabinet 9412 Display section 9413 Operation Buttons 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section

Claims

1. It has a first transistor and a second transistor, One of the source electrode or drain electrode of the first transistor is electrically connected to the other of the source electrode or drain electrode of the second transistor. One of the source electrode or drain electrode of the first transistor is electrically connected to the gate of the first transistor. One of the source electrode or drain electrode of the first transistor is a semiconductor device electrically connected to the first wiring, A first conductive film having a region disposed on an insulating surface and functioning as the gate electrode of the first transistor, A second conductive film having a region disposed on the insulating surface and functioning as the gate electrode of the second transistor, A first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film, A first oxide semiconductor film having a region positioned above the first conductive film via the first silicon nitride film, and having a channel formation region for the first transistor, A second oxide semiconductor film having a region positioned above the second conductive film via the first silicon nitride film, and having a channel formation region for the second transistor, A third conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, and regions in contact with the upper and side surfaces of the second oxide semiconductor film, A fourth conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, An oxide insulating film having a region located above the first oxide semiconductor film, a region located above the second oxide semiconductor film, a region located above the third conductive film, and a region located above the fourth conductive film, A second silicon nitride film having a region positioned above the oxide insulating film, The third conductive film has the function of either the source electrode or the drain electrode of the first transistor, and the function of either the source electrode or the drain electrode of the second transistor. The fourth conductive film functions as the other of the source electrode or drain electrode of the first transistor. The third conductive film has a region in contact with the first conductive film at an opening in the first silicon nitride film. The oxide insulating film has a region in contact with the channel-forming region of the first oxide semiconductor film, In a plan view, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. In a plan view, the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. The first conductive film and the second conductive film are separated from each other. The first oxide semiconductor film and the second oxide semiconductor film are separated from each other. The system comprises a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level. Semiconductor equipment.

2. It has a first transistor and a second transistor, One of the source electrode or drain electrode of the first transistor is electrically connected to the other of the source electrode or drain electrode of the second transistor. One of the source electrode or drain electrode of the first transistor is electrically connected to the gate of the first transistor. One of the source electrode or drain electrode of the first transistor is a semiconductor device electrically connected to the first wiring, A first conductive film having a region disposed on an insulating surface and functioning as the gate electrode of the first transistor, A second conductive film having a region disposed on the insulating surface and functioning as the gate electrode of the second transistor, A first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film, A first oxide semiconductor film having a region positioned above the first conductive film via the first silicon nitride film, and having a channel formation region for the first transistor, A second oxide semiconductor film having a region positioned above the second conductive film via the first silicon nitride film, and having a channel formation region for the second transistor, A third conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, and regions in contact with the upper and side surfaces of the second oxide semiconductor film, A fourth conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, An oxide insulating film having a region located above the first oxide semiconductor film, a region located above the second oxide semiconductor film, a region located above the third conductive film, and a region located above the fourth conductive film, A second silicon nitride film having a region positioned above the oxide insulating film, The first oxide semiconductor film comprises an In-O-based metal oxide. The second oxide semiconductor film comprises an In-O-based metal oxide. The third conductive film has the function of either the source electrode or the drain electrode of the first transistor, and the function of either the source electrode or the drain electrode of the second transistor. The fourth conductive film functions as the other of the source electrode or drain electrode of the first transistor. The third conductive film has a region in contact with the first conductive film at an opening in the first silicon nitride film. The oxide insulating film has a region in contact with the channel-forming region of the first oxide semiconductor film, In a plan view, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. In a plan view, the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. The first conductive film and the second conductive film are separated from each other. The first oxide semiconductor film and the second oxide semiconductor film are separated from each other. The system comprises a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level. Semiconductor equipment.

3. It has a first transistor and a second transistor, One of the source electrode or drain electrode of the first transistor is electrically connected to the other of the source electrode or drain electrode of the second transistor. One of the source electrode or drain electrode of the first transistor is electrically connected to the gate of the first transistor. One of the source electrode or drain electrode of the first transistor is a semiconductor device electrically connected to the first wiring, A first conductive film having a region disposed on an insulating surface and functioning as the gate electrode of the first transistor, A second conductive film having a region disposed on the insulating surface and functioning as the gate electrode of the second transistor, A first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film, A first oxide semiconductor film having a region positioned above the first conductive film via the first silicon nitride film, and having a channel formation region for the first transistor, A second oxide semiconductor film having a region positioned above the second conductive film via the first silicon nitride film, and having a channel formation region for the second transistor, A third conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, and regions in contact with the upper and side surfaces of the second oxide semiconductor film, A fourth conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, An oxide insulating film having a region located above the first oxide semiconductor film, a region located above the second oxide semiconductor film, a region located above the third conductive film, and a region located above the fourth conductive film, A second silicon nitride film having a region positioned above the oxide insulating film, The third conductive film has the function of either the source electrode or the drain electrode of the first transistor, and the function of either the source electrode or the drain electrode of the second transistor. The fourth conductive film functions as the other of the source electrode or drain electrode of the first transistor. The third conductive film has a region in contact with the first conductive film at an opening in the first silicon nitride film. The oxide insulating film has a region in contact with the channel-forming region of the first oxide semiconductor film, In a plan view, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. In a plan view, the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. The first conductive film and the second conductive film are separated from each other. The first oxide semiconductor film and the second oxide semiconductor film are separated from each other. In a plan view, the third conductive film has a region that overlaps the first conductive film via the first oxide semiconductor film, and a region that overlaps the second conductive film via the second oxide semiconductor film. The system comprises a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level. Semiconductor equipment.

4. It has a first transistor and a second transistor, One of the source electrode or drain electrode of the first transistor is electrically connected to the other of the source electrode or drain electrode of the second transistor. One of the source electrode or drain electrode of the first transistor is electrically connected to the gate of the first transistor. One of the source electrode or drain electrode of the first transistor is a semiconductor device electrically connected to the first wiring, A first conductive film having a region disposed on an insulating surface and functioning as the gate electrode of the first transistor, A second conductive film having a region disposed on the insulating surface and functioning as the gate electrode of the second transistor, A first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film, A first oxide semiconductor film having a region positioned above the first conductive film via the first silicon nitride film, and having a channel formation region for the first transistor, A second oxide semiconductor film having a region positioned above the second conductive film via the first silicon nitride film, and having a channel formation region for the second transistor, A third conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, and regions in contact with the upper and side surfaces of the second oxide semiconductor film, A fourth conductive film having regions in contact with the upper and side surfaces of the first oxide semiconductor film, An oxide insulating film having a region located above the first oxide semiconductor film, a region located above the second oxide semiconductor film, a region located above the third conductive film, and a region located above the fourth conductive film, A second silicon nitride film having a region positioned above the oxide insulating film, The third conductive film has the function of either the source electrode or the drain electrode of the first transistor, and the function of either the source electrode or the drain electrode of the second transistor. The fourth conductive film functions as the other of the source electrode or drain electrode of the first transistor. The third conductive film has a region in contact with the first conductive film at an opening in the first silicon nitride film. The oxide insulating film has a region in contact with the channel-forming region of the first oxide semiconductor film, In a plan view, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. In a plan view, the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap. The first conductive film and the second conductive film are separated from each other. The first oxide semiconductor film and the second oxide semiconductor film are separated from each other. In a plan view, the third conductive film has a region that overlaps the first conductive film via the first oxide semiconductor film, and a region that overlaps the second conductive film via the second oxide semiconductor film. In a plan view, the fourth conductive film has a region that overlaps with the first conductive film via the first oxide semiconductor film. The system comprises a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level. Semiconductor equipment.

Images