Filters and multiplexers

Abstract

To provide a filter capable of suppressing a spurious.SOLUTION: A filter comprises: a lamination body in which a dielectric layer and a conductive layer are alternately laminated; an input terminal Tin that is provided onto a front surface of the lamination body; an output terminal Tout that is provided to a front surface of the lamination body; a first conductive pattern M1 that forms at least one part of a close pattern surrounding an open 18 by a plan surface, and is formed by a first conductive layer 12f; a second conductive pattern that is formed by a second conductive layer, is connected to an input terminal, and of which at least one part is overlapped with at least one part of the first conductive pattern, and in which an end part is extended to an outside of the closing pattern from in the open while being positioned into the open; and a third conductive pattern that is formed by a third conductive layer, is connected to an output terminal, of which at least one part is overlapped with at least one part of the first conductive pattern, is not overlapped with the second conductive pattern, and of which the end part is extended to the outside of the closing pattern from the inside of the open while being positioned in the open.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This invention relates to filters and multiplexers. [Background technology]

[0002] Notebook personal computers, smartphones, tablet devices, and mobile phones use filters that allow only high-frequency signals within a specific frequency band to pass through. as Multilayer filters with stacked dielectric layers are known (for example, Patent Documents 1 and 2). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-219469 [Patent Document 2] Japanese Patent Publication No. 2018-19316 [Overview of the project] [Problems that the invention aims to solve]

[0004] Filters that filter out high-frequency signals are required to suppress spurious emissions.

[0005] This invention has been made in view of the above problems and aims to suppress spurious emissions. [Means for solving the problem]

[0006] The present invention relates to a laminate in which a plurality of dielectric layers and a plurality of conductive layers are alternately stacked in the stacking direction, an input terminal provided on the surface of the laminate, an output terminal provided on the surface of the laminate, a first conductive pattern formed from a first conductive layer among the plurality of conductive layers, the planar shape as viewed from the stacking direction forming at least a part of a closed pattern surrounding an opening, and a second conductive layer formed from a second conductive layer different from the first conductive layer among the plurality of conductive layers, connected to the input terminal, and at least a part of which, as viewed from the stacking direction, is at least a part of the first conductive pattern The filter comprises: a second conductive pattern that overlaps with the first conductive pattern, and whose end is located within the opening when viewed from the stacking direction, extending from within the opening to the outside of the closed pattern; and a third conductive pattern formed from a third conductive layer different from the first conductive layer among the plurality of conductive layers, connected to the output terminal, and whose at least part overlaps with at least a part of the first conductive pattern when viewed from the stacking direction, does not overlap with the second conductive pattern when viewed from the stacking direction, whose end is located within the opening, extending from within the opening to the outside of the closed pattern.

[0007] In the above configuration, the closed pattern can be a pattern in which the path through which the current flows is closed.

[0008] In the above configuration, the second conductive pattern and the third conductive pattern can be arranged so as to sandwich the opening when viewed from the stacking direction.

[0009] In the above configuration, when viewed from the stacking direction, the planar shape of the region where the first conductive pattern and the second conductive pattern overlap is approximately a parallelogram, and the planar shape of the region where the first conductive pattern and the third conductive pattern overlap is also approximately a parallelogram.

[0010] In the above configuration, the first conductive pattern and the second conductive pattern can form a first capacitor, and the first conductive pattern and the third conductive pattern can form a second capacitor.

[0011] In the above configuration, the system may include a first inductor connected in parallel to the first capacitor between the input terminal and the output terminal, and a second inductor connected in parallel to the second capacitor between the input terminal and the output terminal.

[0012] In the above configuration, the first parallel resonant circuit comprising the first capacitor and the first inductor can form an attenuation pole on the high-frequency side of the passband, and the second parallel resonant circuit comprising the second capacitor and the second inductor can form an attenuation pole on the high-frequency side of the passband.

[0013] In the above configuration, the laminate can be provided with a ground terminal on its surface and a third capacitor, one end of which is connected to the first conductive pattern and the other end of which is connected to the ground terminal.

[0014] In the above configuration, the first width along the opening in the region where the second conductive pattern overlaps the first conductive pattern when viewed from the stacking direction is smaller than the width in the width direction of the first width in the opening, and the second width along the opening in the region where the third conductive pattern overlaps the first conductive pattern when viewed from the stacking direction is smaller than the width in the width direction of the second width in the opening.

[0015] In the above configuration, when the maximum width of the closed pattern is X (m), the frequency of the high-frequency end of the passband is fc (Hz), and the relative permittivity of the plurality of dielectric layers is εr, then X ≤ 1.875 × 10 7 It can be constructed as / (fc × √εr).

[0016] In the above configuration, the closed pattern can be formed from the first conductive layer.

[0017] In the above configuration, the closed pattern can be configured to include the first conductor pattern, a fourth conductor pattern formed from a fourth conductor layer different from the first conductor layer among the plurality of conductor layers, and via wirings that penetrate through some of the plurality of dielectric layers and connect the first conductor pattern and the fourth conductor pattern.

[0018] In the above configuration, the filter can be configured as a low-pass filter or a band-pass filter.

[0019] The present invention is a multiplexer including the above filter.

Advantages of the Invention

[0020] According to the present invention, spurious can be suppressed.

Brief Description of the Drawings

[0021] [Figure 1] FIG. 1 is a circuit diagram of the filter according to Embodiment 1. [Figure 2] FIGS. 2(a) and 2(b) are a perspective view and a cross-sectional view of the filter according to Embodiment 1. [Figure 3] FIGS. 3(a) to 3(d) are plan views of the dielectric layer in Embodiment 1. [Figure 4] FIGS. 4(a) to 4(d) are plan views of the dielectric layer in Embodiment 1. [Figure 5] FIGS. 5(a) and 5(b) are plan views of the dielectric layer in Comparative Examples 1 and 2, respectively. [Figure 6] FIG. 6 is a diagram showing the passing characteristics and reflection characteristics of Embodiment 1 in the simulation. <I [Figure 7] FIG. 7 is a diagram showing the passing characteristics and reflection characteristics of Comparative Example 1 in the simulation. [Figure 8] FIG. 8 is a diagram showing the passing characteristics and reflection characteristics of Comparative Example 2 in the simulation. ' [Figure 9]Figures 9(a) and 9(b) are plan views of the dielectric layer 11f in Comparative Example 1 and Example 1, respectively. [Figure 10] Figures 10(a) and 10(b) are plan views of the conductive patterns M1 to M3 in Example 1, and Figures 10(c) and 10(d) are plan views of the conductive patterns M1 to M3 in Comparative Example 2. [Figure 11] Figures 11(a) to 11(c) are plan views of the dielectric layer in Modification 1 of Example 1. [Figure 12] Figure 12 is a circuit diagram of the diplexer according to Example 2. [Modes for carrying out the invention]

[0022] The embodiments of the present invention will be described below with reference to the drawings. [Examples]

[0023] As Example 1, we will explain using a low-pass filter (LPF) used in a 5G (5th Generation Mobile Communication System) communication system as an example. In 5G, millimeter waves such as the 28GHz band are used, and even filters with a passband of 6GHz or less are required to improve attenuation characteristics from the passband up to around 30GHz.

[0024] Figure 1 is a circuit diagram of the filter according to Embodiment 1. As shown in Figure 1, the filter 100 of Embodiment 1 has an input terminal Tin, an output terminal Tout, a ground terminal Tg, capacitors C1 to C7, and inductors L1 to L4. Parallel resonant circuits R1 to R4 are connected in series between the input terminal Tin and the output terminal Tout. Node N1 is between parallel resonant circuits R1 and R2, node N2 is between parallel resonant circuits R2 and R3, and node N3 is between parallel resonant circuits R3 and R4. In parallel resonant circuits R1 to R4, capacitors C1 to C4 and inductors L1 to L4 are connected in parallel. Capacitors C5 to C7 are connected between nodes N1 to N3 and the ground terminal Tg.

[0025] Figures 2(a) and 2(b) are perspective and cross-sectional views of the filter according to Embodiment 1. The stacking direction of the dielectric layers 11a to 11h is the Z direction, the arrangement direction of the terminals 14 in the planar direction of the dielectric layers 11a to 11h is the X direction, and the direction perpendicular to the X direction is the Y direction. As shown in Figures 2(a) and 2(b), the filter 100 has a laminate 10. The laminate 10 comprises a plurality of stacked dielectric layers 11a to 11h. Terminals 14 are provided on the lower surface of the laminate 10. The terminals 14 are, for example, an input terminal Tin, an output terminal Tout, and a ground terminal Tg. Directional identification marks are provided on the upper surface of the laminate 10 by a conductive layer 12a.

[0026] Figures 3(a) to 4(d) are plan views of the dielectric layers in Example 1. Figures 3(a) to 4(c) show the conductive layer on the upper surface of dielectric layers 11b to 11h and the via wirings 13b to 13h that penetrate the dielectric layers 11b to 11h, respectively. Figure 4(d) shows the terminal 14 and via wiring 13h on the lower surface of dielectric layer 11h, seen through from above. The electrode C1a in the conductive pattern M2 in Figure 3(d) and the electrode C1b in the input terminal Tin in Figure 4(d) form a capacitor C1 sandwiching the dielectric layers 11e to 11h. The same applies to C2a to C7a and C2b to C7b in Figures 3(d) to 4(b) and Figure 4(d). The same also applies to the following similar figures.

[0027] As shown in Figure 3(a), a conductive layer 12b forming the line patterns L1a to L4a is provided on the upper surface of the dielectric layer 11b. As shown in Figure 3(b), the line patterns L1b to L4b and Conductive pattern A conductive layer 12c forming N2a is provided. Via wiring 13c penetrating the dielectric layer 11c is provided.

[0028] As shown in Figure 3(c), no conductive layer is formed on the upper surface of the dielectric layer 11d. Via wiring 13d is provided penetrating the dielectric layer 11d. As shown in Figure 3(d), a conductive layer 12e forming conductive patterns M2 and M3 is provided on the upper surface of the dielectric layer 11e. Via wiring 13e is provided penetrating the dielectric layer 11e. Conductive pattern M2 includes electrodes C1a, C2a and C5a and corresponds to node N1. Conductive pattern M3 includes electrodes C3a, C4a and C7a and corresponds to node N3.

[0029] As shown in Figure 4(a), a conductive layer 12f is provided on the upper surface of the dielectric layer 11f, forming a conductive pattern M1 and electrodes C5b and C7b. Via wiring 13f is provided penetrating the dielectric layer 11f. Conductive pattern M1 includes electrodes C2b, C3b and C6a. Conductive pattern M1 and N2a are electrically connected via via wiring 13c to 13e, corresponding to node N2.

[0030] As shown in Figure 4(b), a conductive layer 12g is provided on the upper surface of the dielectric layer 11g to form a conductive pattern G. Via wiring 13g is provided penetrating the dielectric layer 11g. The conductive pattern G is a ground pattern electrically connected to the ground terminal Tg via via wirings 13g and 13h, and includes electrode C6b. The conductive pattern G is electrically connected to electrodes C5b and C7b in Figure 4(a) via via wiring 13f.

[0031] As shown in Figure 4(c), no conductive pattern is formed on the upper surface of the dielectric layer 11h. Via wiring 13h is provided penetrating the dielectric layer 11h. As shown in Figure 4(d), terminals 14 are formed on the lower surface of the dielectric layer 11h. Terminals 14 include an input terminal Tin, an output terminal Tout, and a ground terminal Tg. The input terminal Tin includes electrode C1b, and the output terminal Tout includes electrode C4b.

[0032] Inductor L1 is formed by line patterns L1a, L1b and via wirings 13b to 13h, and is connected between input terminal Tin and conductor pattern M2 corresponding to node N1. Inductor L2 is formed by line patterns L2a, L2b and via wirings 13b to 13d, and is connected between conductor pattern M2 corresponding to node N1 and conductor pattern N2a corresponding to node N2. Inductor L3 is formed by line patterns L3a, L3b and via wirings 13b to 13d, and is connected between conductor pattern N2a corresponding to node N2 and conductor pattern M3 corresponding to node N3. Inductor L4 is formed by line patterns L4a, L4b and via wirings 13b to 13h, and is connected between conductor pattern M3 corresponding to node N3 and output terminal Tout.

[0033] Capacitor C1 is formed by electrodes C1a and C1b sandwiching dielectric layers 11e to 11h, and is connected between the input terminal Tin and the conductive pattern M2 corresponding to node N1. Capacitor C2 is formed by electrodes C2a and C2b sandwiching dielectric layer 11e, and is connected between the conductive pattern M2 corresponding to node N1 and the conductive pattern M1 corresponding to node N2. Capacitor C3 is formed by electrodes C3a and C3b sandwiching dielectric layer 11e, and is connected between the conductive pattern M1 corresponding to node N2 and the conductive pattern M3 corresponding to node N3. Capacitor C4 is formed by electrodes C4a and C4b sandwiching dielectric layers 11e to 11h, and is connected between the conductive pattern M3 corresponding to node N3 and the output terminal Tout.

[0034] Capacitor C5 is formed by electrodes C5a and C5b sandwiching the dielectric layer 11e and is connected between the conductive pattern M2 corresponding to node N1 and the ground terminal Tg. Capacitor C6 is formed by electrodes C6a and C6b sandwiching the dielectric layer 11f and is connected between the conductive pattern M1 corresponding to node N2 and the ground terminal Tg. Capacitor C7 is formed by electrodes C7a and C7b sandwiching the dielectric layer 11e and is connected between the conductive pattern M3 corresponding to node N3 and the ground terminal Tg.

[0035] The dielectric layers 11a to 11h are made of a ceramic material and mainly contain oxides of Si, Ca, and Mg (for example, diopside crystals such as CaMgSi2O6). The main components of dielectric layers 11a to 11h may also be oxides other than Si, Ca, and / or Mg. Furthermore, dielectric layers 11a to 11h may also contain at least one oxide of Ti, Zr, and Al as an insulating material.

[0036] The conductive layers 12a-12c and 12e-12g, the via wirings 13b-13h, and the upper part of terminal 14 are metal layers mainly composed of, for example, Ag, Pd, Pt, Cu, Ni, Au, Au-Pd alloy, or Ag-Pt alloy. The upper part of terminal 14 may also contain nonconductive materials such as TiO2, ZrO2, or Al2O3 in addition to the above metal materials. The lower part of terminal 14 is a Ni film and a Sn film.

[0037] In Example 1, as shown in Figure 4(a), the conductive pattern M1 has a rectangular planar shape and a rectangular opening 18. As a result, the conductive pattern M1 is a closed pattern in which the path for current flow is closed.

[0038] [Comparative Example] Figures 5(a) and 5(b) are plan views of the dielectric layers in Comparative Examples 1 and 2, respectively. As shown in Figure 5(a), in Comparative Example 1, the planar shape of the conductive pattern M1 on the upper surface of the dielectric layer 11f is a U-shape with one side removed from a rectangle, and is not a closed pattern. As shown in Figure 5(b), in Comparative Example 2, the planar shape of the conductive pattern M1 on the dielectric layer 11f is a solid rectangle without openings. The upper surfaces of the other dielectric layers 11b to 11e, 11g and 11h, and the lower surface of the dielectric layer 11h in Comparative Examples 1 and 2 have the same configuration as in Figures 3(a) to 3(d) and Figures 4(b) to 4(d), respectively.

[0039] [simulation] For Example 1, Comparative Examples 1 and 2, a three-dimensional electromagnetic field simulation was performed using the finite element method to simulate the transmission and reflection characteristics of the filter.

[0040] Each dielectric layer 11a to 11h is mainly composed of CaMgSi2O6, and its relative permittivity is approximately 10. Because the filter 100 handles high frequencies from 1 GHz to 40 GHz, the filter 100 functions as a distributed-parameter circuit. For this reason, the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L4 are not fixed, but Table 1 shows the approximate values ​​of the capacitances of capacitors C1 to C7 and the inductances of inductors L1 to L4 for Example 1, Comparative Examples 1 and 2. [Table 1]

[0041] Figures 6 to 8 show the transmission and reflection characteristics of Example 1, Comparative Examples 1 and 2 in the simulation. The absolute value of the S parameter S21 represents the transmission characteristics, and the absolute value of S11 represents the reflection characteristics.

[0042] As shown in Figure 6, if the frequency at which S21 becomes -3dB is defined as the cutoff frequency fc (i.e., the high-frequency end of the passband), then the cutoff frequency fc is approximately 7GHz. At frequencies lower than the cutoff frequency fc, S21 is almost 0dB and S11 is below -20dB. At frequencies higher than the cutoff frequency fc, S21 is below -20dB and S11 is almost 0dB. The passband is the band below the cutoff frequency fc, and the attenuation band extends from the cutoff frequency fc to about 40GHz. The attenuation poles A1 to A4 in the attenuation band are mainly formed by parallel resonant circuits R1 to R4. Good attenuation characteristics are obtained around 30GHz.

[0043] As shown in Figure 7, in Comparative Example 1, the cutoff frequency fc is approximately 7 GHz, the same as in Example 1. As shown by the dashed circle 38, spurious signals are observed around 31 GHz where S11 becomes smaller and S21 becomes larger. Thus, the attenuation characteristics deteriorate around 30 GHz.

[0044] As shown in Figure 8, in Comparative Example 2, no spurious signals around 31 GHz were observed, unlike in Comparative Example 1. The cutoff frequency fc is approximately 7 GHz, the same as in Example 1. Good attenuation characteristics were obtained around 30 GHz. As described above, in Comparative Example 1, where the planar shape of the conductor pattern M1 is U-shaped, spurious signals around 31 GHz were generated. It is thought that the spurious signals are related to the planar shape of the conductor pattern M1.

[0045] In Comparative Example 1, we will consider the cause of spurious signals occurring around 31 GHz. Figures 9(a) and 9(b) are plan views of the dielectric layer 11f in Comparative Example 1 and Example 1, respectively. As shown in Figure 9(a), in Comparative Example 1, the conductive pattern M1 is U-shaped. Therefore, the conductive pattern M1 becomes a line of length D0. Length D0 is the length of the center of the line of the conductive pattern M1. Length D0 is given by D0 = D1 + D2 + D1. D1 = 375 μm and D2 = 275 μm, so D0 = 1025 μm. When length D0 is 1 / 4 of the wavelength λ of the high-frequency signal, resonance occurs due to the conductive pattern M1. Therefore, we calculate the frequency at which length D0 is λ / 4. If the relative permittivity of the laminate 10 is εr, then the wavelength λ at which D0 = λ / 4 is λ = 4 × D0 × √εr = 4 × 1.025 × 10 -3 m × √10 ≈ 1.3 × 10 -2 m = 13 mm. The speed of light c is c ≈ 3 × 10⁻¹⁰. 8 Assuming the frequency is m / s, the frequency fs at which the wavelength is λ is fs = c / λ ≈ 23 GHz. Thus, the frequency at which the conductive pattern M1 resonates as a λ / 4 line is close to the 31 GHz at which spurious signals occur in Comparative Example 1.

[0046] As shown in Figure 9(b), in Example 1, the conductive pattern M1 has an opening 18 and is a closed pattern with a closed current path 19. Therefore, a long line like that in Comparative Example 1 in Figure 9(a) is not formed. The length D3 of the long side of the conductive pattern M1 is 475 μm. The wavelength λ for which D3 = λ / 4 is λ = 4 × D3 × √εr = 4 × 0.475 × 10 -3 ×√10 ≈ 6 × 10 -3m = 6 mm, and the frequency fs is fs = c / λ ≈ 50 GHz. Thus, the frequency at which the length of the conductive pattern M1 is λ / 4 is 50 GHz. Also, the length D4 of the diagonal of the conductive pattern M1 is 605 μm. The wavelength λ at which D4 = λ / 4 is λ = 4 × D4 × √εr = 4 × 0.605 × 10 -3 ×√10 ≈ 7.7 × 10 -3 Since m = 7.7 mm, the frequency fs is fs = c / λ ≈ 40 GHz. Thus, the frequency at which the length of the conductive pattern M1 is λ / 4 is 40 to 50 GHz.

[0047] In Comparative Example 1, the conductor pattern M1 resonates at a frequency of approximately 30 GHz at a length of λ / 4, so it is thought that spurious signals are generated around 30 GHz, as shown in Figure 7. On the other hand, in Example 1 and Comparative Example 2, the conductor pattern M1 resonates at a frequency of 40 GHz or higher, so it is thought that no spurious signals are generated in Figures 6 and 8.

[0048] Figures 10(a) and 10(b) are plan views of the conductive patterns M1 to M3 in Example 1, and Figures 10(c) and 10(d) are plan views of the conductive patterns M1 to M3 in Comparative Example 2.

[0049] As shown in Figure 10(a), in Example 1, when viewed from the Z direction, the end of the conductive pattern M2 is located within the opening 18 of the conductive pattern M1, and the conductive pattern M2 extends from within the opening 18 to the outside of the conductive pattern M1. The end of the conductive pattern M3 is located within the opening 18 of the conductive pattern M1, and the conductive pattern M3 extends from within the opening 18 to the outside of the conductive pattern M1. A capacitor C2 is formed in the overlapping region 40a of conductive patterns M1 and M2. A capacitor C3 is formed in the overlapping region 42a of conductive patterns M1 and M3.

[0050] As shown in Figure 10(b), if the alignment of conductive pattern M1 with conductive patterns M2 and M3 is misaligned, for example, if conductive patterns M2 and M3 are misaligned in the +X direction from conductive pattern M1, the area of ​​the overlapping region 40b between conductive patterns M1 and M2, and the area of ​​the overlapping region 42b between conductive patterns M1 and M3, are almost the same as the areas of region 40a and region 42a in Figure 10(a), respectively. Therefore, even if there is a misalignment between conductive patterns M2 and M3 and conductive pattern M1, the capacitances of capacitors C2 and C3 remain almost the same as in Figure 10(a).

[0051] As shown in Figure 10(c), in Comparative Example 2, the conductive pattern M1 is a solid pattern without an opening 18. Capacitor C2 is formed in the overlapping region 40c of conductive patterns M1 and M2. Capacitor C3 is formed in the overlapping region 42c of conductive patterns M1 and M3.

[0052] As shown in Figure 10(d), for example, if conductive patterns M2 and M3 are shifted in the +X direction from conductive pattern M1, the area of ​​the overlapping region 40d between conductive patterns M1 and M2 becomes larger than the area of ​​region 40c in Figure 10(c), and the area of ​​the overlapping region 42d between conductive patterns M1 and M3 becomes smaller than the area of ​​region 42c in Figure 10(c). As a result, the capacitance of capacitor C2 becomes larger than that in Figure 10(c), and the capacitance of capacitor C3 becomes smaller than that in Figure 10(c). If a filter is designed using the capacitances of capacitors C2 and C3 in Figure 10(c), then in Figure 10(d), the capacitances of capacitors C2 and C3 deviate from the design values.

[0053] Thus, in Example 1, by arranging the conductive patterns M2 and M3 so as to cross the ring-shaped closed pattern of conductive pattern M1 when viewed from the Z direction, changes in the capacitance of capacitor C2 and capacitor C3 can be suppressed even if there is a misalignment between conductive patterns M1 and M2 and M3.

[0054] [Example 1 Modification 1] Figures 11(a) to 11(c) are plan views of the dielectric layer in Modification 1 of Example 1. In Figure 11(c), the conductive pattern M4 viewed from the Z direction is shown with a dashed line.

[0055] As shown in Figure 11(a), a conductive layer 12d is provided on the upper surface of the dielectric layer 11d to form a conductive pattern M4. As shown in Figure 11(b), the dielectric layer 11e is provided with via wiring 13e connected to the conductive pattern M4, compared to Figure 3(d). As shown in Figure 11(c), the conductive pattern M1 is U-shaped. As shown in Figures 11(a) and 11(c), the planar shape of the conductive patterns M1 and M4 viewed from the Z direction is a closed pattern. One end of conductive pattern M1 and one end of conductive pattern M4 are electrically connected via via wirings 13d and 13e, and the other end of conductive pattern M1 and the other end of conductive pattern M4 are electrically connected via via wirings 13d and 13e. As a result, a closed loop-shaped current path 19 is formed in the closed pattern.

[0056] As in the modified example 1 of Example 1, even if the conductive pattern M1 forming the electrodes C2b and C3b of capacitors C2 and C3 is U-shaped, it is sufficient if it forms a closed pattern with other conductive patterns M4.

[0057] According to Example 1 and its modifications, the conductive pattern M1 (first conductive pattern) within the laminate 10, which forms at least a portion of a closed pattern surrounding the opening 18 when viewed from the Z direction, is formed from the conductive layer 12f (first conductive layer). The closed pattern is a pattern in which the current flow path 19 is closed. As a result, the resonant frequency is increased at a length of λ / 4, and spurious emissions are less likely to occur in the attenuation band.

[0058] The conductive pattern M2 (second conductive pattern) is formed from a conductive layer 12e (second conductive layer) different from the conductive layer 12f and is connected to the input terminal Tin. When viewed from the Z direction, at least a portion of conductive pattern M2 overlaps with at least a portion of conductive pattern M1 to form capacitor C2 (first capacitor). The conductive pattern M3 (third conductive pattern) is formed from a conductive layer 12e (third conductive layer) different from the conductive layer 12f and is connected to the output terminal Tout. At least a portion of conductive pattern M3 overlaps with at least a portion of conductive pattern M1 to form capacitor C3 (second capacitor). When viewed from the Z direction, the end of conductive pattern M2 is located within the opening 18 and extends from within the opening 18 to the outside of the closed pattern. When viewed from the Z direction, conductive pattern M3 does not overlap with conductive pattern M2, its end is located within the opening 18 and extends from within the opening 18 to the outside of the closed pattern. As a result, as shown in Figures 10(a) and 10(b), even if there is a misalignment between the conductive patterns M1 and M2 and M3, it is possible to suppress the deviation of the capacitances of capacitors C2 and C3 from the design value.

[0059] As shown in Figures 10(a) and 10(b), when viewed from the Z direction, the conductive patterns M2 and M3 are arranged with the opening 18 in between. This further suppresses deviations of the capacitances of capacitors C2 and C3 from the design value even if there is a misalignment between conductive patterns M1 and M2 and M3.

[0060] In Example 1 and Modification 1, a rectangular shape was used as an example for the planar shape of the closed pattern, but the planar shape of the closed pattern may also be an O-shape such as a circle or an ellipse. However, when viewed from the Z direction, it is preferable that the planar shapes of regions 40a and 40b where the conductive patterns M1 and M2 overlap are approximately parallelograms to the extent of manufacturing tolerances, and the planar shapes of regions 42a and 42b where the conductive patterns M1 and M3 overlap are approximately parallelograms to the extent of manufacturing tolerances. As a result, even if there is a misalignment between the conductive patterns M1 and M2 and M3, the area of ​​region 40a and the area of ​​region 40b remain almost unchanged, and the area of ​​region 42a and the area of ​​region 42b remain almost unchanged. Therefore, deviations from the design value of the capacitances C2 and C3 can be further suppressed.

[0061] Conductive pattern viewed from the Z direction M2 The first width W2 along the opening 18 in the region 40a that overlaps with the conductive pattern M1 is smaller than the width W1 in the width direction of the width W2 in the opening 18. Z When viewed from a particular direction, the second width W3 along the opening 18 in region 42a where the conductive pattern M3 overlaps with conductive pattern M1 is smaller than the width W1 in the width direction of the width W3 in the opening 18. As a result, even if there is a misalignment in the Y direction between conductive patterns M1 and M2 and M3, the area of ​​region 40a and region 40b remain almost unchanged, and the area of ​​region 42a and region 42b remain almost unchanged. Therefore, deviations from the design value in the capacitances of capacitors C2 and C3 can be further suppressed. The widths W2 and W3 are preferably 0.9 times or less of the width W1, and more preferably 0.8 times or less.

[0062] As shown in Figure 1, inductor L2 (first inductor) is connected in parallel to capacitor C2 between input terminal Tin and output terminal Tout, and inductor L3 (second inductor) is connected in parallel to capacitor C3. In such a configuration, resonance caused by λ / 4 becomes a problem. Therefore, it is preferable to make electrodes C2b and C3b into a closed pattern.

[0063] In addition, a parallel resonance circuit R2 (first parallel resonance circuit) including a capacitor C2 and an inductor L2 forms an attenuation pole on the high-frequency side of the passband, and a parallel resonance circuit R3 (second parallel resonance circuit) including a capacitor C3 and an inductor L3 forms an attenuation pole on the high-frequency side of the passband. In such a configuration, resonance caused by λ / 4 becomes a problem. Therefore, it is preferable that the electrodes C2b and C3b be closed patterns.

[0064] One end of a capacitor C6 (third capacitor) is connected to a conductor pattern M1, and the other end is connected to a ground terminal Tg. In such a configuration, resonance caused by λ / 4 becomes a problem. Therefore, it is preferable that the electrodes C2b and C3b be closed patterns.

[0065] In the first embodiment and its first modification, the parallel resonance circuits R1 to R4 may include only two of the parallel resonance circuits R2 and R3, or three or five or more may be provided. In the filter 100, the capacitance of the capacitors is symmetric with respect to the input terminal Tin and the output terminal Tout, that is, with respect to the node N2 and the capacitor C6, and the inductance of the inductors is symmetric. The input terminal Tin and the output terminal Tout may be asymmetric.

[0066] In a 5G communication system, signals of 6 GHz or less and 28 GHz are used. Therefore, when the high-frequency end of the passband (cutoff frequency fc at which S21 becomes -3 dB) is 7 GHz, it is preferable that the spurious be 28 GHz or more. Therefore, it is preferable that the frequency of the spurious accompanying the λ / 4 resonance of the closed pattern be 4 times or more the cutoff frequency fc. Therefore, when the maximum width of the closed pattern is X (m), the cutoff frequency is fc (Hz), and the relative permittivity of the plurality of dielectric layers 11a to 11h is εr, the frequency fr of the spurious accompanying the λ / 4 resonance is fr = 4 × fc ≧ c / (4 × X × √εr). Therefore, X ≦ c / (4 × 4 × fc × √εr) = 1.875 × 10 7 / (fc × √εr) [m] is preferable. When the frequency of the spurious is 5 times or more the cutoff frequency fc, X ≦ c / (5 × 4 × fc × √εr) = 1.5 × 10 7 / (fc×√εr)[m] is more preferable. For filters that allow high-frequency signals below 6GHz to pass through in 5G communication systems, X≦2.68×10 -3 / √εr[m] is preferred, and X≦2.14×10 -3 / √εr[m] is more preferable.

[0067] As in Example 1, the closed pattern may be a single conductive pattern M1 formed from a conductive layer 12f provided between adjacent dielectric layers 11e and 11f.

[0068] As shown in Modification 1 of Example 1, the closed pattern may include conductive patterns M1 and M4, and via wiring connecting the end of conductive pattern M1 and the end of conductive pattern M2. Conductive pattern M4 (fourth conductive pattern) is a conductive layer 12f It is formed from a different conductive layer 12d (fourth conductive layer). The closed pattern may be formed from three or more different conductive patterns.

[0069] The conductive layer 12e on which conductive pattern M2 is provided and the conductive layer 12e on which conductive pattern M3 is provided may be different conductive layers or the same conductive layer. The conductive layer 12d on which conductive pattern M4 is provided may be a different conductive layer from the conductive layers 12e on which conductive patterns M2 and M3 are provided, or it may be the same conductive layer.

[0070] I used a low-pass filter as an example to explain the filter, but a band-pass filter would also work. [Examples]

[0071] Figure 12 is a circuit diagram of a diplexer according to Embodiment 2. As shown in Figure 12, the diplexer 20 includes filters 22 and 24. Filters 22 and 24 are connected between the common terminal Ant and terminals T1 and T2, respectively. Antenna 28 is connected to the common terminal Ant. Filter 22 is, for example, a low-pass filter (LPF), which allows low-band high-frequency signals to pass through and suppresses signals of other frequencies. Filter 24 is, for example, a high-pass filter (HPF), which allows high-band high-frequency signals with frequencies higher than the low-band to pass through and suppresses signals of other frequencies.

[0072] Filter 22 can be the filter of Example 1 and its modified form. Although a diplexer was described as an example of a multiplexer, the multiplexer may also be a triplexer or a quadplexer.

[0073] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of Symbols]

[0074] 10 Laminate 11a-11h dielectric layer 12a-12h Conductor layer 13b-13h via wiring 14 terminals 18 Aperture 19 routes

Claims

1. A laminate in which multiple dielectric layers and multiple conductive layers are alternately stacked in the stacking direction, An input terminal provided on the surface of the laminate, Output terminals provided on the surface of the laminate, The planar shape viewed from the stacking direction forms at least a part of a closed pattern surrounding the opening, and a first conductive pattern formed from the first conductive layer among the plurality of conductive layers, A second conductive pattern is formed from a second conductive layer, which is different from the first conductive layer among the plurality of conductive layers, is connected to the input terminal, and at least a portion of it overlaps with at least a portion of the first conductive pattern when viewed from the stacking direction, and when viewed from the stacking direction, its end is located within the opening and extends from within the opening to the outside of the closed pattern, A third conductive pattern is formed from a third conductive layer different from the first conductive layer among the plurality of conductive layers, connected to the output terminal, overlapping at least a portion of the first conductive pattern when viewed from the stacking direction, not overlapping with the second conductive pattern when viewed from the stacking direction, with its end located within the opening and extending from within the opening to the outside of the closed pattern, A first parallel resonant circuit comprising a first capacitor and a first inductor connected in parallel between the input terminal and the output terminal, wherein each of the first capacitor and the first inductor has one end connected to the input terminal and the other end connected to the output terminal, and the first conductive pattern and the second conductive pattern form the first capacitor, A second parallel resonant circuit is connected in series with the first parallel resonant circuit, comprising a second capacitor and a second inductor connected in parallel between the input terminal and the output terminal, wherein each of the second capacitor and the second inductor has one end connected to the input terminal and the other end connected to the output terminal, and the first conductive pattern and the third conductive pattern form the second capacitor. A filter equipped with the following features.

2. The filter according to claim 1, wherein the closed pattern is a pattern in which the path through which current flows is closed.

3. The filter according to claim 1 or 2, wherein, when viewed from the stacking direction, the second conductive pattern and the third conductive pattern are provided sandwiching the opening.

4. The filter according to any one of claims 1 to 3, wherein, when viewed from the stacking direction, the planar shape of the region where the first conductive pattern and the second conductive pattern overlap is substantially parallelogram, and the planar shape of the region where the first conductive pattern and the third conductive pattern overlap is substantially parallelogram.

5. The first parallel resonant circuit, comprising the first capacitor and the first inductor, forms an attenuation pole on the high-frequency side of the passband. The filter according to claim 1, wherein the second parallel resonant circuit comprising the second capacitor and the second inductor forms an attenuation pole on the high-frequency side of the passband.

6. A ground terminal provided on the surface of the laminate, The filter according to claim 1, comprising a third capacitor having one end connected to the first conductive pattern and the other end connected to the ground terminal.

7. The first width along the opening in the region where the second conductive pattern overlaps the first conductive pattern when viewed from the stacking direction is smaller than the width in the width direction of the first width in the opening. The filter according to any one of claims 1 to 6, wherein the second width along the opening in the region where the third conductive pattern overlaps the first conductive pattern when viewed from the stacking direction is smaller than the width in the width direction of the second width in the opening.

8. The filter according to any one of claims 1 to 7, wherein X ≤ 1.875 × 10⁷ / (fc × √εr), where X is the maximum width of the closed pattern (m), fc is the frequency of the high-frequency end of the passband (Hz), and εr is the relative permittivity of the plurality of dielectric layers.

9. The filter according to any one of claims 1 to 8, wherein the closing pattern is formed from the first conductive layer.

10. The filter according to any one of claims 1 to 8, wherein the closed pattern comprises the first conductive pattern, a fourth conductive pattern formed from a fourth conductive layer different from the first conductive layer among the plurality of conductive layers, and via wiring that penetrates some of the dielectric layers among the plurality of dielectric layers and connects the first conductive pattern and the fourth conductive pattern.

11. The filter according to any one of claims 1 to 10, wherein the filter is a low-pass filter or a band-pass filter.

12. A multiplexer comprising the filter according to any one of claims 1 to 11.

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