Positive and negative voltage charge pump circuits, chips, and communication terminals

Abstract

A positive and negative voltage charge pump circuit, a chip, and a communication terminal are provided. [Solution] The positive and negative voltage charge pump circuit includes a clock generation module, a positive voltage charge pump module, a transient boost module, and a negative voltage charge pump module. The positive voltage charge pump module generates a positive voltage based on a clock signal output from the clock generation module, and the transient boost module samples the positive voltage and a power supply voltage, converts them into currents, and compares them. Based on the comparison result, it provides a switchable input voltage to the negative voltage charge pump module. The negative voltage charge pump module quickly and reliably establishes a negative voltage based on the clock signal output from the clock generation module, not only improving the speed and efficiency of the negative voltage charge pump module in generating the negative voltage, but also flexibly realizing different negative voltage requirements.

Description

Technical Field

[0001] The present invention relates to a positive and negative voltage charge pump circuit, and also to an integrated circuit chip including the positive and negative voltage charge pump circuit and a corresponding communication terminal, belonging to the technical field of analog integrated circuits.

Background Art

[0002] With the high integration of integrated circuits, the evolution of process nodes towards deep submicron limits, and the diversification of the application environment of chips, charge pump circuits have been widely applied as basic module circuits for various integrated circuit products. The main function of the charge pump circuit is to supply a positive voltage source higher than the positive rail of the input power supply voltage of the system and a negative voltage source lower than the negative rail of the input power supply voltage, so as to better meet the specifications of system design. High-voltage charge pump circuits for positive power supplies already exist in many application scenarios, but as the specification requirements of the system continue to increase, it is necessary to simultaneously generate a positive high voltage and a negative high voltage inside more electronic systems for stable and highly reliable operation. Therefore, there is an increasing need for the design of a charge pump circuit that provides stable reliability and simultaneously generates voltages higher than the positive rail of the input power supply and lower than the negative rail of the input power supply.

[0003] A Chinese patent with the patent number ZL200810142157.2 discloses a positive and negative high-voltage charge pump circuit that operates to output a positive high voltage or a negative high voltage by a selector based on an asymmetric cross-coupling single-sided cascade connection charge pump structure. However, this circuit cannot output a positive power supply voltage and a negative power supply voltage simultaneously. Also, a patent with the patent number ZL201610004368.4 discloses a charge pump circuit that generates a positive and negative voltage source by controlling the charging and discharging of capacitors by three clock signals that realize a fixed pulse train using a three-phase frequency divider to realize the output of the positive and negative voltage sources. This circuit can realize the output of positive and negative voltage sources, but since the absolute values of its output voltage sources are all lower than the input voltage source, its practical applications are very limited. [Overview of the project]

[0004] The first technical problem that this invention aims to solve is to provide a positive and negative voltage charge pump circuit.

[0005] Another technical problem that the present invention aims to solve is to provide a chip that includes a positive and negative voltage charge pump circuit and a corresponding communication terminal. [Means for solving the problem]

[0006] To achieve the above objectives, the present invention employs the following technical solutions. In a first embodiment of the present invention, a positive and negative voltage charge pump circuit is provided, which includes a clock generation module, a positive voltage charge pump module, a transient enhancement module, and a negative voltage charge pump module. The output terminal of the clock generation module is connected to the input terminals of the positive voltage charge pump module and the negative voltage charge pump module, and the output terminal of the positive voltage charge pump module is connected to the input terminal of the transient enhancement module. The output terminal of the transient enhancement module is connected to the input power supply terminal of the negative voltage charge pump module, and the power supply terminals of the clock generation module, the positive voltage charge pump module, and the transient enhancement module are all connected to the power supply voltage.

[0007] The positive voltage charge pump module generates a positive voltage based on the clock signal output from the clock generation module, and the positive voltage and the power supply voltage are sampled as input voltage sources by the transient enhancement module, converted into current, and then compared. Based on the comparison result, the negative voltage charge pump module is supplied with a switchable input voltage to generate a negative voltage based on the clock signal output from the clock generation module.

[0008] Preferably, the positive voltage charge pump module includes a first clock conversion unit and at least one positive voltage charge pump unit. The input terminal of the first clock conversion unit is connected to the output terminal of the clock generation module, and the output terminal of the first clock conversion unit is connected to the input terminal of each positive voltage charge pump unit.

[0009] Preferably, the first clock conversion unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, and a second NAND gate. The input terminal of the first inverter is connected to the output terminal of the clock generation module and one input terminal of the second NAND gate, and the output terminal of the first inverter is connected to one input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the first output terminal and the input terminal of the third inverter. The output terminal of the third inverter is connected to the other input terminal of the second NAND gate and the second output terminal, and the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the fourth output terminal and the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the other input terminal of the first NAND gate and the third output terminal.

[0010] Preferably, when using multiple positive voltage charge pump units, the process starts with the second positive voltage charge pump unit, and the input voltage of each positive voltage charge pump unit is connected to the positive voltage output terminal of the preceding positive voltage charge pump unit.

[0011] Preferably, the positive voltage charge pump unit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first capacitor, a second capacitor, and a third capacitor. The gate of the first NMOS transistor is connected to the fourth output terminal of the first clock conversion unit, and the sources of the first NMOS transistor and the second NMOS transistor are grounded, respectively. The drain of the first NMOS transistor is connected to one end of the second capacitor and the drain of the first PMOS transistor, respectively, and the gate of the first PMOS transistor is connected to the second output terminal of the first clock conversion unit. The gate of the second NMOS transistor is connected to the first output terminal of the first clock conversion unit, and the drain of the second NMOS transistor is connected to one end of the first capacitor and the drain of the second PMOS transistor, respectively. The gate of the second PMOS transistor is connected to the third output terminal of the first clock conversion unit, and the sources of the second PMOS transistor, the first PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all connected to the input voltage. The gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the other terminal of the first capacitor, the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor, respectively, and the gate of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the other terminal of the second capacitor, the gate of the third PMOS transistor, and the drain of the fourth PMOS transistor, respectively. The sources of the third PMOS transistor and the fourth PMOS transistor are both connected to one terminal of the third capacitor and its positive voltage output terminal, and the other terminal of the third capacitor is grounded.

[0012] Preferably, the transient reinforcement module includes a voltage sampling comparison unit and a voltage switching unit. The input terminal of the voltage sampling comparison unit is connected to the positive voltage output terminal and power supply voltage of the positive voltage charge pump unit, and the output terminal of the voltage sampling comparison unit is connected to the input terminal of the voltage switching unit.

[0013] Preferably, the voltage sampling comparison unit includes a first resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second resistor, a third resistor, and a fourth capacitor. One end of the first resistor and the sources of the fifth and sixth PMOS transistors are connected to the power supply voltage, respectively. The other end of the first resistor is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor, respectively. The drain of the sixth NMOS transistor is connected to the drain and gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor, respectively. The drain of the sixth PMOS transistor is connected to one end of the fourth capacitor, one end of the third resistor, the drain of the seventh NMOS transistor, and the voltage switching unit, respectively. The gate of the seventh NMOS transistor is connected to the gate and drain of the eighth NMOS transistor and to one end of the second resistor, respectively, and the other end of the second resistor is connected to the positive voltage output terminal of the positive voltage charge pump unit. The sources of the eighth NMOS transistor and the seventh NMOS transistor, the other end of the third resistor and the fourth capacitor, and the sources of the sixth NMOS transistor and the fifth NMOS transistor are all grounded.

[0014] Preferably, the voltage switching unit includes a hysteresis inverter, a logic level conversion subunit, and a switch subunit. The input terminal of the hysteresis inverter is connected to the output terminal of the voltage sampling comparison unit, the output terminal of the hysteresis inverter is connected to the input terminal of the logic level conversion subunit, and the output terminal of the logic level conversion subunit is connected to the input terminal of the switch subunit.

[0015] Preferably, the logic level conversion subunit includes a sixth inverter, a seventh inverter, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a fifth capacitor, a sixth capacitor, a third NAND gate, a fourth NAND gate, an XOR gate, and a plurality of digital delay units. The input terminal of the sixth inverter is connected to the output terminal of the hysteresis inverter, and the output terminal of the sixth inverter is connected to the input terminal of the seventh inverter and the gate of the thirteenth NMOS transistor. The output terminal of the seventh inverter is connected to one input terminal of the switch subunit and to the gate of the 14th NMOS transistor, and the X node is connected to the output terminal of the hysteresis inverter, the input terminal of the first digital delay unit, and to one input terminal of the XOR gate, respectively. A plurality of digital delay units are connected in series from the output terminal of the first digital delay unit to the input terminal of the last digital delay unit, and the output terminal of the last digital delay unit is connected to the other input terminal of the XOR gate. The output terminal of the XOR gate is connected to the gates of the 18th NMOS transistor and the 17th NMOS transistor, and to the gates of the 14th PMOS transistor and the 15th PMOS transistor, respectively, and the drain of the 15th PMOS transistor is connected to one end of the sixth capacitor and to the drain of the 18th NMOS transistor. The source of the 18th NMOS transistor is connected to the drain of the 14th NMOS transistor, and the other end of the 6th capacitor is connected to the source of the 15th NMOS transistor, one input terminal of the 3rd NAND gate, and the drain of the 10th PMOS transistor.The drain of the 15th NMOS transistor is connected to the drain of the 16th NMOS transistor, and the source of the 16th NMOS transistor is connected to the drain of the 11th PMOS transistor, one end of the 5th capacitor, and one input terminal of the 4th NAND gate. The other end of the 5th capacitor is connected to the drain of the 14th PMOS transistor and the drain of the 17th NMOS transistor, respectively, and the source of the 17th NMOS transistor is connected to the drain of the 13th NMOS transistor. The gate of the 12th NMOS transistor. is the The drain of the 5 NMOS transistor is connected, and the drain of the 12th NMOS transistor is connected to the drain and gate of the 13th PMOS transistor, and to the gates of the 16th NMOS transistor and the 15th NMOS transistor, respectively. The source of the 13th PMOS transistor is connected to the drain and gate of the 12th PMOS transistor, and to the gates of the 11th PMOS transistor and the 10th PMOS transistor, respectively. The sources of the 12th PMOS transistor, the 11th PMOS transistor, and the 10th PMOS transistor, and the drains of the 15th NMOS transistor and the 16th NMOS transistor are all connected to the positive voltage output terminal of the positive voltage charge pump unit. The sources of the 14th NMOS transistor, the 13th NMOS transistor and the 12th NMOS transistor are each grounded, and the sources of the 14th PMOS transistor and the 15th PMOS transistor are each connected to the negative rail voltage of the location voltage domain. The other input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate and the other input of the switch subunit. At the edge The output terminal of the third NAND gate is connected to the other input terminal of the fourth NAND gate.

[0016] Preferably, the switch subunit includes a 16th PMOS transistor and a 17th PMOS transistor. The gate of the 16th PMOS transistor is connected to the output terminal of the 4th NAND gate, and the source of the 16th PMOS transistor is connected to the positive voltage output terminal of the positive voltage charge pump unit. The gate of the 17th PMOS transistor is connected to the output terminal of the 7th inverter, and the source of the 17th PMOS transistor is connected to the power supply voltage. The drains of the 17th PMOS transistor and the 16th PMOS transistor are the output terminals of the switch subunit.

[0017] Preferably, the negative voltage charge pump module includes a second clock conversion unit and a negative voltage charge pump unit. The input terminal of the second clock conversion unit is connected to the output terminal of the clock generation module, the output terminal of the second clock conversion unit is connected to the input terminal of the negative voltage charge pump unit, and the input terminal of the negative voltage charge pump unit is connected to the output terminal of the voltage switching unit.

[0018] Preferably, the second clock conversion unit includes an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a fifth NAND gate, and a sixth NAND gate. The input terminal of the eighth inverter is connected to the output terminal of the clock generation module and one input terminal of the sixth NAND gate, and the output terminal of the eighth inverter is connected to one input terminal of the fifth NAND gate. The output terminal of the fifth NAND gate is connected to the input terminal of the ninth inverter, and the output terminal of the ninth inverter is connected to the fifth output terminal and the input terminal of the tenth inverter. The output terminal of the tenth inverter is connected to the other input terminal of the sixth NAND gate and the sixth output terminal, and the output terminal of the sixth NAND gate is connected to the input terminal of the eleventh inverter. The output terminal of the eleventh inverter is connected to the eighth output terminal and the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is connected to the other input terminal of the fifth NAND gate and the seventh output terminal.

[0019] Preferably, the negative voltage charge pump unit includes an 18th PMOS transistor, a 19th PMOS transistor, a 19th NMOS transistor, a 20th NMOS transistor, a 20th PMOS transistor, a 21st PMOS transistor, a 21st NMOS transistor, a 22nd NMOS transistor, a 7th capacitor, an 8th capacitor, and a 9th capacitor. The gate of the 18th PMOS transistor is connected to the 8th output terminal of the second clock conversion unit, the drains of the 18th PMOS transistor and the 19th PMOS transistor are connected to the output voltage of the voltage switching unit, the source of the 18th PMOS transistor is connected to one end of the 8th capacitor and the source of the 19th NMOS transistor, and the gate of the 19th NMOS transistor is connected to the 6th output terminal of the second clock conversion unit. The gate of the 19th PMOS transistor is connected to the fifth output terminal of the second clock conversion unit, and the source of the 19th PMOS transistor is connected to one end of the 7th capacitor and the source of the 20th NMOS transistor, respectively. The gate of the 20th NMOS transistor is connected to the seventh output terminal of the second clock conversion unit, and the drains of the 19th NMOS transistor, the 20th NMOS transistor, the 20th PMOS transistor, and the 21st PMOS transistor are grounded, respectively. The gate of the 21st PMOS transistor is connected to the source of the 20th PMOS transistor, the other end of the 7th capacitor, the gate of the 22nd NMOS transistor, and the source of the 21st NMOS transistor, respectively, and the gate of the 20th PMOS transistor is connected to the source of the 21st PMOS transistor, the other end of the 8th capacitor, the gate of the 21st NMOS transistor, and the source of the 22nd NMOS transistor, respectively. The drains of the 21st NMOS transistor and the 22nd NMOS transistor are connected to one end and the negative voltage output terminal of the 9th capacitor, respectively, and the other end of the 9th capacitor is grounded.

[0020] In a second aspect according to an embodiment of the present invention, an integrated circuit chip including the positive and negative voltage charge pump circuit is provided. In a third aspect according to an embodiment of the present invention, a communication terminal including the positive and negative voltage charge pump circuit is provided.

Advantages of the Invention

[0021] The positive and negative voltage charge pump circuit provided by an embodiment of the present invention generates a positive voltage based on a clock signal output from a clock generation module by a positive voltage charge pump module, samples the positive voltage and a power supply voltage by a transient enhancement module, converts them into currents and then compares them, and supplies an input voltage that can be switched to a negative voltage charge pump module based on the comparison result. The negative voltage charge pump module can quickly and surely establish a negative voltage based on the clock signal output from the clock generation module, not only improve the speed and efficiency of the negative voltage charge pump module for generating a negative voltage, but also can flexibly realize different negative voltage requirements.

Brief Description of the Drawings

[0022] [Figure 1] It is a schematic block diagram of a positive and negative voltage charge pump circuit provided by an embodiment of the present invention. [Figure 2] It is a schematic diagram of a circuit of a positive voltage charge pump module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention. [Figure 3] It is a schematic diagram of a circuit of a transient enhancement module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention. [Figure 4] It is a schematic diagram of a circuit of a negative voltage charge pump module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0023] The technical details of the present invention will be described in more detail below with reference to the drawings and specific embodiments.

[0024] To stably and reliably achieve both a positive voltage higher than the positive rail of the input power supply voltage and a negative voltage lower than the negative rail of the input power supply voltage simultaneously, and to flexibly and quickly establish the output negative voltage, the positive and negative voltage charge pump circuit provided by an embodiment of the present invention, as shown in Figure 1, includes a clock generation module 100, a positive voltage charge pump module 101, a transient augmentation module 102, and a negative voltage charge pump module 103. The output terminal of the clock generation module 100 is connected to the input terminals of the positive voltage charge pump module 101 and the negative voltage charge pump module 103, and the output terminal of the positive voltage charge pump module 101 is connected to the input terminal of the transient augmentation module 102. The output terminal of the transient augmentation module 102 is connected to the input power terminal of the negative voltage charge pump module 103, and the power terminals of the clock generation module 100, the positive voltage charge pump module 101, and the transient augmentation module 102 are all connected to the power supply voltage VDD.

[0025] The positive voltage charge pump module 101 generates a positive voltage based on the clock output from the clock generation module 100. This positive voltage and the power supply voltage are sampled as input voltage sources by the transient augmentation module 102, converted to current, and then compared. Based on the comparison result, a switchable input voltage is supplied to the negative voltage charge pump module 103 so that the negative voltage charge pump module 103 generates a negative voltage output based on the clock signal output from the clock generation module 100.

[0026] The clock generation module 100 is used to generate a clock signal. The clock generation module 100 can be implemented using an oscillator of any structure. Its primary purpose is to supply a clock signal of a constant frequency to the positive voltage charge pump module 101 and the negative voltage charge pump module 103.

[0027] As shown in Figure 2, the positive voltage charge pump module 101 includes a first clock conversion unit 201 and at least one positive voltage charge pump unit 202. The input terminal of the first clock conversion unit 201 is connected to the output terminal of the clock generation module 100, and the output terminal of the first clock conversion unit 201 is connected to the input terminal of each positive voltage charge pump unit 202.

[0028] The first clock conversion unit 201 is used to convert the clock signal output from the clock generation module 100 to generate two complementary non-overlapping clock signals. As shown in Figure 2, the first clock conversion unit 201 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first NAND gate NAND1, and a second NAND gate NAND2. The input terminal of the first inverter INV1 is connected to the output terminal of the clock generation module 100 and one input terminal of the second NAND gate NAND2, and the output terminal of the first inverter INV1 is connected to one input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the output terminal of the first inverter and the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 is connected to the other input terminal and the second output terminal of the second NAND gate NAND2, and the output terminal of the second NAND gate NAND2 is connected to the input terminal of the fourth inverter INV4. The output terminal of the fourth inverter INV4 is connected to the fourth output terminal and the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 is connected to the other input terminal and the third output terminal of the first NAND gate NAND1.

[0029] The first clock conversion unit 201 receives the clock signal CLK output from the clock generation module 100 and converts the clock signal CLK into two non-overlapping clock signals, namely, the first non-overlapping clock signals CLK_i and CLK_b, and the second non-overlapping clock signals CLK_if and CLK_bf, using inverters INV1 to INV5 and two input NAND gates NAND1 and NAND2. The conversion of the clock signal CLK into two non-overlapping clock signals by the first clock conversion unit 201 is a prior art technique and will not be described in detail here.

[0030] Furthermore, if the voltage domain of the first clock conversion unit 201 differs from the voltage domain of the received clock signal CLK, the first clock conversion unit 201 needs to complete its level conversion function. For example, if the voltage domain of the clock signal CLK is the power supply voltage VDD and the ground voltage VSS, then, since the power supply voltage VDD is the positive rail of the input signal voltage and VSS is the negative rail of the input signal voltage, the first clock conversion unit 201 needs to convert the amplitude of the clock signal CLK to the voltage domains of the positive rail value VDDi and the ground voltage VSS of the desired conversion target voltage.

[0031] As shown in Figure 2, the positive voltage charge pump unit 202 includes a first NMOS transistor MN0, a second NMOS transistor MN1, a first PMOS transistor MP0, a second PMOS transistor MP1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a first capacitor CF1, a second capacitor CF2, and a third capacitor Chold. The gate of the first NMOS transistor MN0 is connected to the fourth output terminal of the first clock conversion unit 201, and the sources of both the first NMOS transistor MN0 and the second NMOS transistor MN1 are grounded. The drain of the first NMOS transistor MN0 is connected to one end of the second capacitor CF2 and the drain of the first PMOS transistor MP0, respectively, and the gate of the first PMOS transistor MP0 is connected to the second output terminal of the first clock conversion unit 201. The gate of the second NMOS transistor MN1 is connected to the first output terminal of the first clock conversion unit 201, and the drain of the second NMOS transistor MN1 is connected to one end of the first capacitor CF1 and the drain of the second PMOS transistor MP1, respectively. The gate of the second PMOS transistor MP1 is connected to the third output terminal of the first clock conversion unit 201, and the sources of the second PMOS transistor MP1, the first PMOS transistor MP0, the third NMOS transistor MN2, and the fourth NMOS transistor MN3 are all connected to the input voltage Vin. The gate of the fourth NMOS transistor MN3 is connected to the drain of the third NMOS transistor MN2, the other end of the first capacitor CF1, the gate of the fourth PMOS transistor MP3, and the drain of the third PMOS transistor MP2, respectively. The gate of the third NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN3, the other end of the second capacitor CF2, the gate of the third PMOS transistor MP2, and the drain of the fourth PMOS transistor MP3, respectively.The sources of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are connected to one end of the third capacitor Chold and the positive voltage output terminal VDDH, respectively, while the other end of the third capacitor Chold is grounded.

[0032] Here, the first NMOS transistor MN0, the second NMOS transistor MN1, the first PMOS transistor MP0, and the second PMOS transistor MP1 are switch transistors, while the third NMOS transistor MN2, the fourth NMOS transistor MN3, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 are transmission transistors. The first capacitor CF1 and the second capacitor CF2 are sequentially charged and discharged by controlling the on / off states of the first NMOS transistor MN0, the second NMOS transistor MN1, the first PMOS transistor MP0, and the second PMOS transistor MP1 using two complementary non-overlapping clock signals output from the first clock conversion unit 201. Furthermore, by switching the third NMOS transistor MN2, the fourth NMOS transistor MN3, the third PMOS transistor MP2, and the fourth PMOS transistor MP3 on and off, the charge from the first capacitor CF1 and the second capacitor CF2 is transmitted to the third capacitor Chold, thereby achieving a positive voltage output. Here, the capacitance values ​​of the first capacitor CF1 and the second capacitor CF2 are equal, and the input voltage Vin is at most equal to the power supply voltage VDD.

[0033] Specifically, taking the case where the input voltage Vin is at most equal to the power supply voltage VDD, when the non-overlap clock signal CLK_i is at a high level, that is, when the power supply voltage VDD is supplied to the first clock conversion unit 201, the non-overlap clock signal CLK_b is at a low level. That is, when the ground voltage VSS is supplied to the first clock conversion unit 201, the levels of the non-overlap clock signals CLK_if and CLK_bf are the power supply voltage VDD and the ground voltage VSS, respectively. At this time, the first NMOS transistor MN0 and the second PMOS transistor MP1 are turned on, and the first PMOS transistor MP0 and the second NMOS transistor MN1 are turned off, thereby connecting both ends of the first capacitor CF1 to the power supply voltage VDD, and supplying the fourth NMOS transistor MN3 with a power supply voltage VDD that is twice the gate voltage. The source voltage of the fourth NMOS transistor MN3 is VDD, which turns on the fourth NMOS transistor MN3. The gate voltage of the third PMOS transistor MP2 is the supply voltage VDD, which turns on the third PMOS transistor MP2. All the charge in the first capacitor CF1 is transmitted to the third capacitor Chold by the third PMOS transistor MP2, i.e., the third capacitor Chold is charged, thereby achieving a positive voltage output. On the other hand, the gate voltage and source voltage of the third NMOS transistor MN2 are both the supply voltage VDD, which turns off the third NMOS transistor MN2, and the fourth PMOS transistor MP3 is also turned off in the same way. In addition, one end of the second capacitor CF2 is connected to the supply voltage VDD, and the other end is connected to the ground voltage VSS, thereby enabling charging of the second capacitor CF2.

[0034] Similarly, when the non-overlap clock signal CLK_i is at a low level, i.e., when the ground voltage VSS is supplied to the first clock conversion unit 201, the non-overlap clock signal CLK_b is at a high level. That is, when the power supply voltage VDD is supplied to the first clock conversion unit 201, the levels of the non-overlap clock signals CLK_if and CLK_bf are the ground voltage VSS and the power supply voltage VDD, respectively. At this time, the second NMOS transistor MN1 and the first PMOS transistor MP0 are turned on, and the first NMOS transistor MN0 and the second PMOS transistor MP1 are turned off, so that both ends of the second capacitor CF2 are connected to the power supply voltage VDD, thereby supplying the third NMOS transistor MN2 with a power supply voltage VDD that is twice the gate voltage. The source voltage of the third NMOS transistor MN2 is VDD, which turns on the third NMOS transistor MN2. The gate voltage of the fourth PMOS transistor MP3 is the feed voltage VDD, which turns on the fourth PMOS transistor MP3. All the charge in the second capacitor CF2 is transferred by the fourth PMOS transistor MP3 to the third capacitor Chold, i.e., the third capacitor Chold is charged, thereby realizing a positive voltage output. On the other hand, both the gate voltage and source voltage of the fourth NMOS transistor MN3 are the feed voltage VDD, which turns off the fourth NMOS transistor MN3, and similarly turns off the third PMOS transistor MP2. In addition, one end of the first capacitor CF1 is connected to the feed voltage VDD and the other end is connected to the ground voltage VSS, thereby charging the first capacitor CF1. After several cycles, by shifting the charge in the first capacitor CF1 and the second capacitor CF2, the positive voltage output terminal VDDH ultimately outputs twice the feed voltage VDD.

[0035] The non-overlap clock signals CLK_if and CLK_bf correspond to non-overlap clock signals CLK_i and CLK_b, respectively, with their phases advanced. Furthermore, non-overlap clock signals CLK_if and CLK_i are in-phase non-overlap clock signals, and non-overlap clock signals CLK_bf and CLK_b are in-phase non-overlap clock signals. The non-overlap clock signals CLK_if and CLK_bf help to avoid the problem of the PMOS transistor and NMOS transistor in the positive voltage charge pump unit 202 turning on simultaneously.

[0036] Furthermore, if the positive voltage output terminal VDDH of a positive voltage charge pump unit 202 needs to output a higher positive voltage, multiple positive voltage charge pump units 202 can be cascaded. That is, with the exception of the second positive voltage charge pump unit 202, the input voltage Vin of each positive voltage charge pump unit 202 can be connected to the positive voltage output terminal VDDH of the preceding positive voltage charge pump unit 202.

[0037] As shown in Figure 3, the transient enhancement module 102 includes a voltage sampling comparison unit 301 and a voltage switching unit 302. The input terminal of the voltage sampling comparison unit 301 is connected to the positive voltage output terminal VDDH and the power supply voltage VDD of the positive voltage charge pump unit 202, and the output terminal of the voltage sampling comparison unit 301 is connected to the input terminal of the voltage switching unit 302. The voltage sampling comparison unit 301 samples the positive voltage and power supply voltage VDD output from the positive voltage charge pump unit 202, converts the positive voltage and power supply voltage VDD into corresponding currents, and then compares them so that node VDET outputs the state of the detection signal. The voltage switching unit 302 performs the necessary level conversion processing on the state of the detection signal and then controls a switch to switch the voltage, thereby supplying a switchable input voltage to the negative voltage charge pump module 103, and further improving the speed and efficiency of the negative voltage charge pump module 103 in generating negative voltage.

[0038] As shown in Figure 3, the voltage sampling comparison unit 301 includes a first resistor R1, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a second resistor R2, a third resistor R3, and a fourth capacitor C1. One end of the first resistor R1 and the sources of the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5 are connected to the power supply voltage VDD, respectively. The other end of the first resistor R1 is connected to the drain and gate of the fifth NMOS transistor MN4 and the gate of the sixth NMOS transistor MN5, respectively. The drain of the sixth NMOS transistor MN5 is connected to the drain and gate of the fifth PMOS transistor MP4 and the gate of the sixth PMOS transistor MP5, respectively. The drain of the sixth PMOS transistor MP5 is connected to one end of the fourth capacitor C1 and one end of the third resistor R3, and to the drain of the seventh NMOS transistor MN6 and the voltage switching unit 302, respectively. The gate of the seventh NMOS transistor MN6 is connected to the gate and drain of the eighth NMOS transistor MN7 and to one end of the second resistor R2, respectively. The other end of the second resistor R2 is connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. The sources of the eighth NMOS transistor MN7 and the seventh NMOS transistor MN6, the other end of the third resistor R3 and the fourth capacitor C1, and the sources of the sixth NMOS transistor MN5 and the fifth NMOS transistor MN4 are all grounded.

[0039] The operating principle of the voltage sampling comparison unit 301 is explained below. The output voltage VDDH at the positive voltage output terminal of the positive voltage charge pump unit 202 is sampled by the second resistor R2 and the eighth NMOS transistor MN7, and the positive voltage is converted into a corresponding current, which is then duplicated at a preset ratio via the seventh NMOS transistor MN6. The power supply voltage VDD is sampled by the first resistor R1 and the fifth NMOS transistor MN4, and the power supply voltage VDD is converted into a corresponding current. This current is then duplicated at a preset ratio via the sixth NMOS transistor MN5, the fifth PMOS transistor MP4, and the sixth PMOS transistor MP5 in sequence. Here, the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and the power supply voltage VDD are sampled and converted into a corresponding current. This current is duplicated at a preset ratio corresponding to the drain of the eighth NMOS transistor MN7 and the drain of the sixth PMOS transistor MP5. Each is shown below.

number

number

[0040] In the above equation, R1 is the first resistor, R2 is the second resistor, β0 = μnCoxW0 / L0, β3 = μnCoxW3 / L3, and μn is the electron mobility. Cox is the gate oxide layer capacitance, W0 / L0 is the ratio of the width to the length of the fifth NMOS transistor MN4, and W3 / L3 is the ratio of the width to the length of the eighth NMOS tube MN7. VDDH is the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit, VDD is the feed voltage, and V T This is the threshold voltage for circuit design.

[0041] When the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 is equal to the power supply voltage VDD, the current in the sixth PMOS transistor MP5 is greater than the current in the seventh NMOS transistor MN6. Therefore, the state of the detection signal output from node VDET approaches a high level of the power supply voltage VDD, and as the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 gradually increases, I D7 The current also increases. When the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 exceeds the threshold voltage of the circuit design or reaches the target stable state (e.g., twice the supply voltage VDD), the current in the seventh NMOS transistor MN6 is much larger than the current in the sixth PMOS transistor MP5. The state of the detection signal output from node VDET transitions from a high level supply voltage VDD to a low level ground voltage VSS before being output. Thus, the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 is dynamically detected. When the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 rises or falls to a predetermined value, the state of the detection signal output from the voltage sampling comparison unit 301 reverses once.

[0042] As shown in Figure 3, the voltage switching unit 302 includes a hysteresis inverter 3020, a logic level conversion subunit 3021, and a switch subunit 3022. The input terminal of the hysteresis inverter 3020 is connected to the output terminal of the voltage sampling comparison unit 301, the output terminal of the hysteresis inverter 3020 is connected to the input terminal of the logic level conversion subunit 3021, and the output terminal of the logic level conversion subunit 3021 is connected to the input terminal of the switch subunit 3022.

[0043] As shown in Figure 3, the hysteresis inverter 3020 includes a ninth NMOS transistor MN8, a tenth NMOS transistor MN9, an eleventh NMOS transistor MN10, a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, and a ninth PMOS transistor MP8. The gates of the ninth NMOS transistor MN8, the tenth NMOS transistor MN9, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are connected together as the input terminals of the hysteresis inverter 3020, and are connected to node VDET of the sampling comparison unit 301 to receive the state of the detection signal output from the voltage sampling comparison unit 301. The drain of the 9th NMOS transistor MN8 and the source of the 10th NMOS transistor MN9 are connected to the drain of the 9th PMOS transistor MP8, respectively. The drains of the 10th NMOS transistor MN9 and the 8th PMOS transistor MP7, and the gates of the 9th PMOS transistor MP8 and the 11th NMOS transistor MN10 are interconnected as the output terminals of the hysteresis inverter 3020. The source of the 8th PMOS transistor MP7 and the drain of the 7th PMOS transistor MP6 are connected to the drain of the 11th NMOS transistor MN10, respectively. The sources of the 7th PMOS transistor MP6 and the 9th PMOS transistor MP8 are connected to the power supply voltage VDD, respectively. The sources of the 9th NMOS transistor MN8 and the 11th NMOS transistor MN10 are grounded.

[0044] The operating voltage domains of the hysteresis inverter 3020 are the power supply voltage VDD and the ground voltage VSS. The main function of the hysteresis inverter 3020 is to shape the state of the detection signal output from the voltage sampling comparison unit 301, obtain a logic level by inverting the state of the detection signal, and realize a constant hysteresis function, thereby preventing glitch levels from occurring in the state of the power supply voltage VDD and the detection signal, and ensuring that the circuit operates more safely and reliably.

[0045] As shown in Figure 3, the logic level conversion subunit 3021 includes a sixth inverter INV6, a seventh inverter INV7, a twelfth NMOS transistor MN11, a thirteenth NMOS transistor MN12, a fourteenth NMOS transistor MN13, a fifteenth NMOS transistor MN14, a sixteenth NMOS transistor MN15, a seventeenth NMOS transistor MN16, an eighteenth NMOS transistor MN17, a tenth PMOS transistor MP9, an eleventh PMOS transistor MP10, a twelfth PMOS transistor MP11, a thirteenth PMOS transistor MP12, a fourteenth PMOS transistor MP13, a fifteenth PMOS transistor MP14, a fifth capacitor C2, a sixth capacitor C3, a third NAND gate NAND3, a fourth NAND gate NAND4, digital delay units D1 to D4, and an XOR gate XOR1. The connections between the parts of the logic level conversion subunit 3021 are as follows: The input terminal of the sixth inverter INV6 is connected to the output terminal of the hysteresis inverter 3020, and the output terminal of the sixth inverter INV6 is connected to the input terminal of the seventh inverter INV7 and to the gate of the thirteenth NMOS transistor MN12. The output terminal of the seventh inverter INV7 is connected to one input terminal of the switch subunit 3022 and to the gate of the fourteenth NMOS transistor MN13. The X node is connected to the output terminal of the hysteresis inverter 3020, the input terminal of the first digital delay unit D1 and to one input terminal of the XOR gate XOR1, and the second digital delay unit D2 and the third digital delay unit D3 are connected in series between the output terminal of the first digital delay unit D1 and the input terminal of the fourth digital delay unit D4, and the output terminal of the fourth digital delay unit D4 is connected to the other input terminal of the XOR gate XOR1.The output terminal of the XOR gate XOR1 is connected to the gates of the 18th NMOS transistor MN17 and the 17th NMOS transistor MN16, and to the gates of the 14th PMOS transistor MP13 and the 15th PMOS transistor MP14, respectively. The drain of the 15th PMOS transistor MP14 is connected to one end of the 6th capacitor C3 and to the drain of the 18th NMOS transistor MN17, respectively. The source of the 18th NMOS transistor MN17 is connected to the drain of the 14th NMOS transistor MN13. The other end of the 6th capacitor C3 is connected to the source of the 15th NMOS transistor MN14, to one input terminal of the 3rd NAND gate NAND3, and to the drain of the 10th PMOS transistor MP9, respectively. The drain of the 15th NMOS transistor MN14 is connected to the drain of the 16th NMOS transistor MN15. The source of the 16th NMOS transistor MN15 is connected to the drain of the 11th PMOS transistor MP10, one end of the 5th capacitor C2, and one input terminal of the 4th NAND gate NAND4, respectively. The other end of the 5th capacitor C2 is connected to the drain of the 14th PMOS transistor MP13 and the drain of the 17th NMOS transistor MN16, respectively. The source of the 17th NMOS transistor MN16 is connected to the drain of the 13th NMOS transistor MN12, and the gate of the 12th NMOS transistor MN11 is connected to the drain of the 5th NMOS transistor MN4. The drain of the 12th NMOS transistor MN11 is connected to the drain and gate of the 13th PMOS transistor MP12, and to the gates of the 16th NMOS transistor MN15 and the 15th NMOS transistor MN14, respectively. The source of the 13th PMOS transistor MP12 is connected to the drain and gate of the 12th PMOS transistor MP11, and to the gates of the 11th PMOS transistor MP10 and the 10th PMOS transistor MP9, respectively.The sources of the 12th PMOS transistor MP11, the 11th PMOS transistor MP10, and the 10th PMOS transistor MP9, and the drains of the 15th NMOS transistor MN14 and the 16th NMOS transistor MN15 are all connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. The sources of the 14th NMOS transistor MN13, the 13th NMOS transistor MN12, and the 12th NMOS transistor MN11 are each grounded, and the sources of the 14th PMOS transistor MP13 and the 15th PMOS transistor MP14 are each connected to the negative rail voltage VDDL of the location voltage domain. The other input terminal of the third NAND gate NAND3 is connected to the output terminal of the fourth NAND gate NAND4 and the other input terminal of the switch subunit 3022, respectively, and the output terminal of the third NAND gate NAND3 is connected to the other input terminal of the fourth NAND gate NAND4.

[0046] As shown in Figure 3, the switch subunit 3022 includes a 16th PMOS transistor MP15 and a 17th PMOS transistor MP16. The gate of the 16th PMOS transistor MP15 is used as the other input terminal of the switch subunit 3022 to connect to the output terminal of the 4th NAND gate NAND4. The source of the 16th PMOS transistor MP15 is connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, and the gate of the 17th PMOS transistor MP16 is used as one input terminal of the switch subunit 3022 to connect to the output terminal of the 7th inverter INV7. The source of the 17th PMOS transistor MP16 is connected to the power supply voltage VDD, and the drains of the 17th PMOS transistor MP16 and the 16th PMOS transistor MP15 are used as output terminals of the switch subunit 3022 to output a voltage VDD_neg that supplies a switchable input voltage to the negative voltage charge pump module 103.

[0047] The voltage domains in which the third NAND gate NAND3 and the fourth NAND gate NAND4 operate are the positive voltage (positive rail voltage value of the location voltage domain) output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and the negative rail voltage VDDL of the location voltage domain. In this embodiment of the present invention, the negative rail voltage VDDL of the location voltage domain is set to the power supply voltage VDD. The state of the detection signal output from the voltage sampling comparison unit 301 is converted from a voltage domain of high-level power supply voltage VDD and low-level ground voltage VSS to a voltage domain of high-level positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and low-level power supply voltage VDD, and then the output voltage VDD_neg of the transient enhancement module 102 is selected by controlling the gate voltages of the switch transistors, the 16th PMOS transistor MP15 and the 17th PMOS transistor MP16. Furthermore, the 12th NMOS transistor MN11 replicates the current of the 5th NMOS transistor MN4 in the voltage sampling comparison unit 301 at a preset ratio, thereby connecting the 12th PMOS transistor MP11 to the 13th PMOS transistor MP12. The 13th PMOS transistor MP12 is connected in a diode configuration, and the 10th PMOS transistor MP9, the 11th PMOS transistor MP10, and the 12th PMOS transistor MP11 are proportional mirror current sources. The 13th PMOS transistor MP12 supplies static gate voltages to the 16th NMOS transistor MN15 and the 15th NMOS transistor MN14, and precharges the 5th capacitor C2 and the 6th capacitor C3 by controlling the gate voltages of the 14th PMOS transistor MP13, the 15th PMOS transistor MP14, the 17th NMOS transistor MN16, and the 18th NMOS transistor MN17 with a narrow pulse signal RST.The capacitance values ​​of the fifth capacitor C2 and the sixth capacitor C3 are equal. The charges of the two capacitors are initialized, and after the signals output from the X node are logically synthesized by the digital delay units D1-D4 and the XOR gate XOR1, a single narrow pulse signal RST is generated. This signal RST is then used to convert the level of the detection signal output from node VDET.

[0048] To understand the operating principle of the voltage switching unit 302, the operating principle of the voltage switching unit 302, together with the voltage sampling comparison unit 301, will be explained in detail below. Here, the operation of the transient enhancement module 102 begins when the circuit is energized and the positive voltage charge pump module 101 starts operating. The positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 gradually increases from the supply voltage VDD, but in the process before reaching the target voltage, the state of the detection signal output from node VDET is at a high level close to the supply voltage VDD. After passing through the sixth inverter INV6 and the seventh inverter INV7, the gate voltages of the thirteenth NMOS transistor MN12 and the fourteenth NMOS transistor MN13 are the supply voltage VDD and the ground voltage VSS, respectively, the thirteenth NMOS transistor MN12 is in the ON state, and the fourteenth NMOS transistor MN13 is in the OFF state. At this time, the gate voltage XL supplied to the 17th PMOS transistor MP16, which is a switch transistor, is the ground voltage VSS, and therefore the 17th PMOS transistor MP16 is turned ON.

[0049] If the state of the detection signal output from node VDET jumps, the state of the signal output from node X also jumps after being reshaped via the hysteresis inverter 3020. This output signal then passes through the combinational logic of digital time delay units D1 to D4 and the XOR gate XOR1 to generate a narrow pulse signal RST, where the high level is the power supply voltage VDD, and the level of the detection signal output from node VDET is converted by the signal RST.

[0050] After the power supply voltage is properly supplied, the detection signal output from node VDET jumps from the ground voltage VSS to the power supply voltage VDD, and the X node voltage jumps from the power supply voltage VDD to the ground voltage VSS. After passing through a combinational logic subunit consisting of digital time delay units D1 to D4 and XOR gate XOR1, a narrow pulse signal RST is generated with a high level being the power supply voltage VDD. When the level of the narrow pulse signal RST is the ground voltage VSS, the 14th PMOS transistor MP13 and the 15th PMOS transistor MP14 are turned on, and the 17th NMOS transistor MN16 and the 18th NMOS transistor MN17 are turned off. In this case, plates A and B of the 5th capacitor C2 and the 6th capacitor C3 are pre-charged to the power supply voltage VDD. Simultaneously, the plates C and D of the fifth capacitor C2 and the sixth capacitor C3 are charged by the tenth PMOS transistor MP9 and the eleventh PMOS transistor MP10 until they become equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202.

[0051] When the narrow pulse signal RST is the power supply voltage VDD, the 14th PMOS transistor MP13 and the 15th PMOS transistor MP14 are switched off, and the 17th NMOS transistor MN16 and the 18th NMOS transistor MN17 are switched on. The 13th NMOS transistor MN12 is switched on, and the 14th NMOS transistor MN13 is switched off, so the voltage across plate A of the 5th capacitor C2 is rapidly reduced to the ground voltage VSS, and the voltage across plate C of the 5th capacitor C2 also drops rapidly. When the voltage across plate C of the 5th capacitor C2 drops to a certain value, the 16th NMOS transistor MN15 is switched on, and the voltage across plate C of the 5th capacitor C2 is raised. After the 16th NMOS transistor MN15 is switched off, the 14th NMOS transistor MN13 charges the 5th capacitor C2 until the voltage across its plate C becomes equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. During this process, the voltage across the 6th capacitor remains unchanged because the 14th NMOS transistor MN13 is switched off.

[0052] When the narrow pulse signal RST becomes the ground voltage VSS again, the 14th PMOS transistor MP13 and the 15th PMOS transistor MP14 turn on again, the 17th NMOS transistor MN16 and the 18th NMOS transistor MN17 are shut off, and the 5th capacitor C2 and the 6th capacitor C3 return to the pre-charged state, waiting for the trigger of the next narrow pulse of the narrow pulse signal RST.

[0053] In the process described above, the voltage across plate D of the sixth capacitor C3 remains unchanged throughout the process and is still equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. The voltage across plate C of the fifth capacitor C2 initially decreases, then rises until it is equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. As the voltage across plate C of the fifth capacitor C2 approaches the voltage of the power supply voltage VDD, the voltage XH output from the fourth NAND gate NAND4 is raised until it is equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, and the 16th PMOS transistor MP15 of the switch transistor turns off. The 17th PMOS transistor MP16 turns on and the 16th PMOS transistor MP15 turns off, so in that state the output voltage VDD_neg of the voltage switching unit 302 is equal to the power supply voltage VDD.

[0054] After the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 is established or reaches the target voltage, if the detection signal output from node VDET jumps from the high-level supply voltage VDD to the low-level ground voltage VSS, the gate voltages of the 13th NMOS transistor MN12 and the 14th NMOS transistor MN13 are the ground voltage VSS and the supply voltage VDD, respectively. Therefore, the 14th NMOS transistor MN13 turns ON, and the 13th NMOS transistor MN12 turns OFF. Consequently, the 17th PMOS transistor MP16 is OFF. Simultaneously, the X node voltage jumps from the ground voltage VSS to the supply voltage VDD, and after passing through a combinational logic subunit consisting of digital delay units D1-D4 and an XOR gate XOR1, generates a narrow pulse signal RST where the high level is the supply voltage VDD. That is, a valid detection pulse causes the voltage at plate D of the 6th capacitor C3 to drop first, and then rise. On the other hand, the voltages of the two plates of the fifth capacitor C2 remain unchanged, and therefore the voltage output from the third NAND gate NAND3 is equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, which has been established or reached the target voltage. The voltage output from the fourth NAND gate NAND4 is the low-level power supply voltage VDD, and therefore the voltage XH output from the fourth NAND gate NAND4 is the power supply voltage VDD. At this time, the 16th PMOS transistor MP15 is in the ON state. The 17th PMOS transistor MP16 is shut off and the 16th PMOS transistor MP15 is turned ON, so in this state the output voltage VDD_neg of the voltage switching unit 302 is equal to the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, which has been established or reached the target voltage.

[0055] The negative voltage charge pump module 103 generates a negative voltage output based on the clock signal generated by the clock generation module 100 and the clock amplitude voltage VDD_neg supplied by the transient augmentation module 102. As shown in Figure 4, the negative voltage charge pump module 103 includes a second clock conversion unit 401 and a negative voltage charge pump unit 402. The input terminal of the second clock conversion unit 401 is connected to the output terminal of the clock generation module 100, the output terminal of the second clock conversion unit 401 is connected to the input terminal of the negative voltage charge pump unit 402, and the input terminal of the negative voltage charge pump unit 402 is connected to the output terminal of the voltage switching unit 302.

[0056] The second clock conversion unit 401 is used to convert the clock signal output from the clock generation module 100 to generate two complementary non-overlapping clock signals. As shown in Figure 4, the second clock conversion unit 401 includes an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a fifth NAND gate NAND5, and a sixth NAND gate NAND6. The input terminal of the eighth inverter INV8 is connected to the output terminal of the clock generation module 100 and one input terminal of the sixth NAND gate NAND6, and the output terminal of the eighth inverter INV8 is connected to one input terminal of the fifth NAND gate NAND5. The output terminal of the fifth NAND gate NAND5 is connected to the input terminal of the ninth inverter INV9, and the output terminal of the ninth inverter INV9 is connected to the output terminal of the fifth and the input terminal of the tenth inverter INV10. The output terminal of the 10th inverter INV10 is connected to the other input terminal and the 6th output terminal of the 6th NAND gate NAND6, and the output terminal of the 6th NAND gate NAND6 is connected to the input terminal of the 11th inverter INV11. The output terminal of the 11th inverter INV11 is connected to the 8th output terminal and the input terminal of the 12th inverter INV12, and the output terminal of the 12th inverter INV12 is connected to the other input terminal and the 7th output terminal of the 5th NAND gate NAND5.

[0057] The second clock conversion unit 401 receives the clock signal CLK output from the clock generation module 100 and converts the clock signal CLK into two non-overlapping clock signals using inverters INV8 to INV12 and two input NAND gates NAND5 and NAND6. Here, the first non-overlapping clock signals are CLK_i' and CLK_b', and the second non-overlapping clock signals are CLK_if' and CLK_bf'. Here, the operating voltage domains of the two input NAND gates NAND5 and NAND6 are the output voltage VDD_neg and ground voltage VSS of the voltage switching unit 302. The conversion of the clock signal CLK into two non-overlapping clock signals by the second clock conversion unit 401 is prior art and will not be described in detail here.

[0058] As shown in Figure 4, the negative voltage charge pump unit 402 includes an 18th PMOS transistor MP17, a 19th PMOS transistor MP18, a 19th NMOS transistor MN18, a 20th NMOS transistor MN19, a 20th PMOS transistor MP19, a 21st PMOS transistor MP20, a 21st NMOS transistor MN20, a 22nd NMOS transistor MN21, a 7th capacitor CF3, an 8th capacitor CF4, and a 9th capacitor Chold1. The gate of the 18th PMOS transistor MP17 is connected to the 8th output terminal of the second clock conversion unit 401, and the drains of the 18th PMOS transistor MP17 and the 19th PMOS transistor MP18 are connected to the output voltage VDD_neg of the voltage switching unit 302, respectively. The source of the 18th PMOS transistor MP17 is connected to one end of the 8th capacitor CF4 and to the source of the 19th NMOS transistor MN18, respectively, and the gate of the 19th NMOS transistor MN18 is connected to the 6th output terminal of the second clock conversion unit 401. The gate of the 19th PMOS transistor MP18 is connected to the 5th output terminal of the second clock conversion unit 401, and the source of the 19th PMOS transistor MP18 is connected to one end of the 7th capacitor CF3 and to the source of the 20th NMOS transistor MN19, respectively, and the gate of the 20th NMOS transistor MN19 is connected to the 7th output terminal of the second clock conversion unit 401. The drains of the 19th NMOS transistor MN18, the 20th NMOS transistor MN19, the 20th PMOS transistor MP19, and the 21st PMOS transistor MP20 are all grounded.The gate of the 21st PMOS transistor MP20 is connected to the source of the 20th PMOS transistor MP19, the other end of the 7th capacitor CF3, the gate of the 22nd NMOS transistor MN21, and the source of the 21st NMOS transistor MN20, respectively. The gate of the 20th PMOS transistor MP19 is connected to the source of the 21st PMOS transistor MP20, the other end of the 8th capacitor CF4, the gate of the 21st NMOS transistor MN20, and the source of the 22nd NMOS transistor MN21, respectively. The drains of the 21st NMOS transistor MN20 and the 22nd NMOS transistor MN21 are both connected to the 9th capacitor Chold1 and the negative voltage output terminal VSSH, and the other end of the 9th capacitor Chold1 is grounded.

[0059] When the positive and negative voltage charge pump circuit starts operating, the positive voltage charge pump unit 202 and the negative voltage charge pump unit 402 operate simultaneously. If the positive rail voltage of the voltage domain of the positive and negative voltage charge pump circuit is the feed voltage VDD and the negative rail voltage is the ground voltage VSS, the voltage generated by the positive voltage charge pump unit 202 is quickly established at the target voltage. In this process, the transient enhancement module 102 samples the feed voltage VDD and the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202. If the sampled positive voltage of the positive voltage charge pump unit 202 does not reach the target value, the feed voltage VDD acts as the input voltage for the negative voltage charge pump unit 402, and if the non-overlap clock signal CLK_i' is at a high level, the non-overlap clock signal CLK_b' is at a low level, and simultaneously, the levels of the non-overlap clock signals CLK_if' and CLK_bf' are the feed voltage VDD and the ground voltage VSS, respectively. At this time, the 18th PMOS transistor MP17 and the 20th NMOS transistor MN19 are in the ON state, while the 19th NMOS transistor MN18 and the 19th NMOS transistor MN18 are in the OFF state. Therefore, the terminals of the 7th capacitor CF3 are connected to the power supply voltage VDD, supplying a gate voltage of ground voltage VSS minus power supply voltage VDD to the 21st PMOS transistor MP20. The source voltage of the 21st PMOS transistor MP20 is VDD, so the 21st PMOS transistor MP20 is in the ON state, the gate voltage of the 21st NMOS transistor MN20 is the power supply voltage VDD, so the 21st NMOS transistor MN20 is in the ON state, and all the charge in the 7th capacitor CF3 is transmitted to the 9th capacitor Chold1 by the 21st NMOS transistor MN20. In other words, by charging the ninth capacitor Chold1, a negative voltage is output, and this negative voltage is VSSH = VSS - VDD_neg, that is, if the positive voltage of the positive voltage charge pump unit 202 sampled by the transient augmentation module 102 does not reach the target value, the voltage VDD_neg that the transient augmentation module 102 supplies to the negative voltage charge pump unit 402 is the power supply voltage VDD.At this time, the negative voltage VSSH generated from the negative voltage charge pump unit 402 is equal to the ground voltage VSS minus the power supply voltage VDD. Meanwhile, the 20th PMOS transistor MP19 and the 22nd NMOS transistor MN21 are in an interrupted state, and one end of the 8th capacitor CF4 is connected to the power supply voltage VDD, and the other end is connected to the ground voltage VSS, charging the 8th capacitor CF4.

[0060] After the positive voltage of the positive voltage charge pump unit 202 reaches the target value, the positive voltage of the positive voltage charge pump unit 202 acts as the input voltage of the negative voltage charge pump unit 402. At this time, a non-overlap clock signal controls the following: the 19th PMOS transistor MP18 and the 19th NMOS transistor MN18 are turned on, the 18th PMOS transistor MP17 and the 20th NMOS transistor MN19 are turned off, the 20th PMOS transistor MP19 and the 22nd NMOS transistor MN21 are turned on, and the 21st PMOS transistor MP20 and the 21st NMOS transistor MN20 are turned off. In this way, all the charge in the 8th capacitor CF4 is transmitted to the 9th capacitor Chold1 by the 22nd NMOS transistor MN21. That is, the 9th capacitor Chold1 is charged, and a negative voltage output is realized. The negative voltage is VSSH = VSS - VDD_neg, that is, when the positive voltage of the positive voltage charge pump unit 202 sampled by the transient augmentation module 102 reaches the target value, the voltage VDD_neg supplied by the transient augmentation module 102 to the negative voltage charge pump unit 402 is the positive voltage of the positive voltage charge pump unit 202. At this time, the negative voltage VSSH generated by the negative voltage charge pump unit 402 is the ground voltage VSS minus the positive voltage of the positive voltage charge pump unit 202.

[0061] Therefore, after the output voltage of the positive voltage charge pump unit 202 is established, the negative voltage charge pump unit 402 extracts current from the positive voltage charge pump unit 202 and completes its own negative voltage establishment. As a result, the establishment time of the voltage output from the positive voltage charge pump unit 202 is not affected by the operation of the negative voltage charge pump unit 402. At the same time, in the process of establishing the positive voltage, the negative voltage charge pump unit 402 is established early at the voltage of ground voltage VSS - power supply voltage VDD, and after the voltage output from the positive voltage charge pump unit 202 reaches a stable state, it uses that voltage to complete the generation of the negative voltage, thereby accelerating the negative voltage establishment time of the negative voltage charge pump unit 402.

[0062] The non-overlap clock signals CLK_if' and CLK_bf' correspond to clock signals that are phase-advancing versions of the non-overlap clock signals CLK_i' and CLK_b', respectively. Furthermore, clock signals CLK_if' and CLK_i' are in phase, and clock signals CLK_bf' and CLK_b' are in phase. The non-overlap clock signals CLK_if' and CLK_bf' help to avoid the problem of the PMOS transistor and NMOS transistor in the negative voltage charge pump unit 402 turning on simultaneously.

[0063] The positive and negative voltage charge pump circuit provided by the embodiment of the present invention may be used in an integrated circuit chip. The specific structure of the positive and negative voltage charge pump circuit in the integrated circuit chip will not be described in detail here.

[0064] The positive and negative voltage charge pump circuit described above can also be used in communication terminals as an important component of analog integrated circuits. The communication terminals referred to here are computer devices that can be used in mobile environments and support various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE, including mobile phones, laptop computers, tablet computers, and in-car computers. Furthermore, the technical solutions provided in this invention are applicable to other analog integrated circuit applications, such as communication base stations.

[0065] The positive and negative voltage charge pump circuit provided by the embodiment of the present invention generates a positive voltage using a positive voltage charge pump module, samples the positive voltage and the supply voltage using a transient enhancement module, converts them into currents, compares them, and supplies a switchable input voltage to the negative voltage charge pump module based on the comparison result. The negative voltage charge pump module quickly and reliably establishes a negative voltage based on a clock signal output from a clock generation module, and can improve the speed and efficiency of negative voltage generation by the negative voltage charge pump module, as well as flexibly accommodate different negative voltage requirements.

[0066] The positive and negative voltage charge pump circuit, chip, and communication terminal provided by the present invention have been described in detail above. Those skilled in the art will know that any obvious modifications made thereto without departing from the substantial content of the present invention will all fall within the scope of the patent protection of the present invention.

Claims

1. In a positive / negative voltage charge pump circuit, It includes a clock generation module, a positive voltage charge pump module, a transient enhancement module, and a negative voltage charge pump module. The output terminal of the clock generation module is connected to the input terminals of the positive voltage charge pump module and the negative voltage charge pump module; the output terminal of the positive voltage charge pump module is connected to the input terminal of the transient reinforcement module; the output terminal of the transient reinforcement module is connected to the input power supply terminal of the negative voltage charge pump module; and the power supply terminals of the clock generation module, the positive voltage charge pump module and the transient reinforcement module are all connected to the power supply voltage. A positive and negative voltage charge pump circuit characterized in that the positive voltage charge pump module generates a positive voltage based on a clock signal output from the clock generation module, the positive voltage and the power supply voltage are sampled by the transient enhancement module as an input voltage source, converted into current, and then compared, and based on the comparison result, a switchable input voltage is supplied to the negative voltage charge pump module so that the negative voltage charge pump module generates a negative voltage based on a clock signal output from the clock generation module.

2. The positive voltage charge pump module includes a first clock conversion unit and at least one positive voltage charge pump unit. The positive and negative voltage charge pump circuit according to claim 1, characterized in that the input terminal of the first clock conversion unit is connected to the output terminal of the clock generation module, and the output terminal of the first clock conversion unit is connected to the input terminal of each of the positive voltage charge pump units.

3. The first clock conversion unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, and a second NAND gate. The positive and negative voltage charge pump circuit according to claim 2, characterized in that the input terminal of the first inverter is connected to the output terminal of the clock generation module and one input terminal of the second NAND gate, the output terminal of the first inverter is connected to one input terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first output terminal and the input terminal of the third inverter, the output terminal of the third inverter is connected to the other input terminal of the second NAND gate and the second output terminal, the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the fourth output terminal and the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the other input terminal of the first NAND gate and the third output terminal.

4. The positive / negative voltage charge pump circuit according to claim 2, characterized in that, when using multiple positive voltage charge pump units, the circuit starts with the second positive voltage charge pump unit, and the input voltage of each positive voltage charge pump unit is connected to the positive voltage output terminal of the preceding positive voltage charge pump unit.

5. The positive voltage charge pump unit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first capacitor, a second capacitor, and a third capacitor. The gate of the first NMOS transistor is connected to the fourth output terminal of the first clock conversion unit, the sources of the first NMOS transistor and the second NMOS transistor are grounded, the drain of the first NMOS transistor is connected to one end of the second capacitor and the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the second output terminal of the first clock conversion unit, the gate of the second NMOS transistor is connected to the first output terminal of the first clock conversion unit, the drain of the second NMOS transistor is connected to one end of the first capacitor and the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the third output terminal of the first clock conversion unit, and the second PMOS transistor and the first PMO The positive and negative voltage charge pump circuit according to claim 4, characterized in that the sources of the S transistor, the third NMOS transistor and the fourth NMOS transistor are all connected to the input voltage, the gate of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the other end of the first capacitor, the gate of the fourth PMOS transistor and the drain of the third PMOS transistor, respectively, the gate of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the other end of the second capacitor, the gate of the third PMOS transistor and the drain of the fourth PMOS transistor, respectively, the sources of the third PMOS transistor and the fourth PMOS transistor are both connected to one end of the third capacitor and the positive voltage output terminal, and the other end of the third capacitor is grounded.

6. The transient enhancement module includes a voltage sampling comparison unit and a voltage switching unit. The positive / negative voltage charge pump circuit according to claim 5, characterized in that the input terminal of the voltage sampling comparison unit is connected to the positive voltage output terminal and power supply voltage of the positive voltage charge pump unit, and the output terminal of the voltage sampling comparison unit is connected to the input terminal of the voltage switching unit.

7. The voltage sampling comparison unit includes a first resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second resistor, a third resistor, and a fourth capacitor. One end of the first resistor and the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the power supply voltage, the other end of the first resistor is connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the drain and gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor is connected to one end of the fourth capacitor and one end of the third resistor and the seventh NMOS transistor The positive and negative voltage charge pump circuit according to claim 6, characterized in that the drain of the transistor and the voltage switching unit are connected, the gate of the seventh NMOS transistor is connected to the gate and drain of the eighth NMOS transistor and one end of the second resistor, the other end of the second resistor is connected to the positive voltage output terminal of the positive voltage charge pump unit, and the sources of the eighth NMOS transistor and the seventh NMOS transistor, the other end of the third resistor and the fourth capacitor, and the sources of the sixth NMOS transistor and the fifth NMOS transistor are all grounded.

8. The voltage switching unit includes a hysteresis inverter, a logic level conversion subunit, and a switch subunit. The positive and negative voltage charge pump circuit according to claim 6, characterized in that the input terminal of the hysteresis inverter is connected to the output terminal of the voltage sampling comparison unit, the output terminal of the hysteresis inverter is connected to the input terminal of the logic level conversion subunit, and the output terminal of the logic level conversion subunit is connected to the input terminal of the switch subunit.

9. The logic level conversion subunit includes a sixth inverter, a seventh inverter, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a fifth capacitor, a sixth capacitor, a third NAND gate, a fourth NAND gate, an XOR gate, and a plurality of digital delay units. The input terminal of the sixth inverter is connected to the output terminal of the hysteresis inverter, the output terminal of the sixth inverter is connected to the input terminal of the seventh inverter and the gate of the thirteenth NMOS transistor, the output terminal of the seventh inverter is connected to one input terminal of the switch subunit and the gate of the fourteenth NMOS transistor, the X node is connected to the output terminal of the hysteresis inverter, the input terminal of the first digital delay unit and one input terminal of the XOR gate, a plurality of digital delay units are connected in series from the output terminal of the first digital delay unit to the input terminal of the last digital delay unit, the output terminal of the last digital delay unit is connected to the other input terminal of the XOR gate, the output terminal of the XOR gate is connected to the gates of the eighteenth NMOS transistor and the seventeenth NMOS transistor and the fourteenth PMOS transistor and the fifteenth PMOS transistor, respectively, the drain of the fifteenth PMOS transistor is connected to one end of the sixth capacitor and the drain of the eighteenth NMOS transistor The source of the 18th NMOS transistor is connected to the drain of the 14th NMOS transistor, the other end of the 6th capacitor is connected to the source of the 15th NMOS transistor, one input terminal of the 3rd NAND gate, and the drain of the 10th PMOS transistor, the drain of the 15th NMOS transistor is connected to the drain of the 16th NMOS transistor, the source of the 16th NMOS transistor is connected to the drain of the 11th PMOS transistor, one end of the 5th capacitor, and one input terminal of the 4th NAND gate, the other end of the 5th capacitor is connected to the drain of the 14th PMOS transistor and the drain of the 17th NMOS transistor, the source of the 17th NMOS transistor is connected to the drain of the 13th NMOS transistor, the gate of the 12th NMOS transistor is connected to the drain of the 5th NMOS transistor, and the drain of the 12th NMOS transistor is connected to the drain and gate of the 13th PMOS transistor,The gates of the 16th NMOS transistor and the 15th NMOS transistor are connected, respectively. The source of the 13th PMOS transistor is connected to the drain and gate of the 12th PMOS transistor, and to the gates of the 11th PMOS transistor and the 10th PMOS transistor, respectively. The sources of the 12th PMOS transistor, the 11th PMOS transistor, and the 10th PMOS transistor, and the drain of the 15th NMOS transistor and the drain of the 16th NMOS transistor are all connected to the positive voltage output of the positive voltage charge pump unit. The positive and negative voltage charge pump circuit according to claim 8, characterized in that the terminals are connected, the sources of the 14th NMOS transistor, the 13th NMOS transistor and the 12th NMOS transistor are each grounded, the sources of the 14th PMOS transistor and the 15th PMOS transistor are each connected to the negative rail voltage of the location voltage domain, the other input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate and the other input terminal of the switch subunit, and the output terminal of the third NAND gate is connected to the other input terminal of the fourth NAND gate.

10. The switch subunit includes a 16th PMOS transistor and a 17th PMOS transistor, The positive and negative voltage charge pump circuit according to claim 9, characterized in that the gate of the 16th PMOS transistor is connected to the output terminal of the 4th NAND gate, the source of the 16th PMOS transistor is connected to the positive voltage output terminal of the positive voltage charge pump unit, the gate of the 17th PMOS transistor is connected to the output terminal of the 7th inverter, the source of the 17th PMOS transistor is connected to the power supply voltage, and the drains of the 17th PMOS transistor and the 16th PMOS transistor are the output terminals of the switch subunit.

11. The negative voltage charge pump module includes a second clock conversion unit and a negative voltage charge pump unit. The positive and negative voltage charge pump circuit according to claim 10, characterized in that the input terminal of the second clock conversion unit is connected to the output terminal of the clock generation module, the output terminal of the second clock conversion unit is connected to the input terminal of the negative voltage charge pump unit, and the input terminal of the negative voltage charge pump unit is connected to the output terminal of the voltage switching unit.

12. The second clock conversion unit includes an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a fifth NAND gate, and a sixth NAND gate. The positive and negative voltage charge pump circuit according to claim 11, characterized in that the input terminal of the eighth inverter is connected to the output terminal of the clock generation module and one input terminal of the sixth NAND gate, the output terminal of the eighth inverter is connected to one input terminal of the fifth NAND gate, the output terminal of the fifth NAND gate is connected to the input terminal of the ninth inverter, the output terminal of the ninth inverter is connected to the fifth output terminal and the input terminal of the tenth inverter, the output terminal of the tenth inverter is connected to the other input terminal and the sixth output terminal of the sixth NAND gate, the output terminal of the sixth NAND gate is connected to the input terminal of the eleventh inverter, the output terminal of the eleventh inverter is connected to the eighth output terminal and the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is connected to the other input terminal and the seventh output terminal of the fifth NAND gate.

13. The negative voltage charge pump unit includes an 18th PMOS transistor, a 19th PMOS transistor, a 19th NMOS transistor, a 20th NMOS transistor, a 20th PMOS transistor, a 21st PMOS transistor, a 21st NMOS transistor, a 22nd NMOS transistor, a 7th capacitor, an 8th capacitor, and a 9th capacitor. The gate of the 18th PMOS transistor is connected to the 8th output terminal of the second clock conversion unit, the drains of the 18th PMOS transistor and the 19th PMOS transistor are each connected to the output voltage of the voltage switching unit, the source of the 18th PMOS transistor is connected to one end of the 8th capacitor and the source of the 19th NMOS transistor, the gate of the 19th NMOS transistor is connected to the 6th output terminal of the second clock conversion unit, the gate of the 19th PMOS transistor is connected to the 5th output terminal of the second clock conversion unit, the source of the 19th PMOS transistor is connected to one end of the 7th capacitor and the source of the 20th NMOS transistor, the gate of the 20th NMOS transistor is connected to the 7th output terminal of the second clock conversion unit, and the 19th NMOS transistor The positive and negative voltage charge pump circuit according to 12, characterized in that the drains of the 20th NMOS transistor, the 20th PMOS transistor and the 21st PMOS transistor are each grounded, the gate of the 21st PMOS transistor is connected to the source of the 20th PMOS transistor, the other end of the 7th capacitor, the gate of the 22nd NMOS transistor and the source of the 21st NMOS transistor, the gate of the 20th PMOS transistor is connected to the source of the 21st PMOS transistor, the other end of the 8th capacitor, the gate of the 21st NMOS transistor and the source of the 22nd NMOS transistor, the drains of the 21st NMOS transistor and the 22nd NMOS transistor are each connected to one end of the 9th capacitor and the negative voltage output terminal, and the other end of the 9th capacitor is grounded.

14. An integrated circuit chip characterized by including a positive and negative voltage charge pump circuit as described in any one of claims 1 to 13.

15. A communication terminal characterized by including a positive and negative voltage charge pump circuit as described in any one of claims 1 to 13.

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