Clamp circuits and electronic circuits

Abstract

To provide a clamp circuit and an electronic circuit capable of restricting a voltage exerted to a capacitance.SOLUTION: A clamp circuit includes: a current clamp circuit connected between a prescribed terminal contained in the circuit and a capacitance; and a voltage clamp circuit connected between the connection point of the current clamp circuit and the capacitance and the ground.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a clamp circuit and an electronic circuit.

Background Art

[0002] There is known a voltage regulator that can prevent a decrease in output voltage and an increase in output noise without suppressing overshoot in a steady state (see, for example, Patent Document 1). FIG. 1 is a circuit diagram showing an example of a voltage regulator. The voltage regulator includes an error amplifier circuit 3, PMOS transistors 21, 32, 6, NMOS transistors 41, 33, a reference voltage circuit 7, constant current circuits 23, 31, a constant voltage circuit 13, resistors 4, 5, 12, a capacitor 11, an inverter 22, a ground terminal 0, an output terminal 2, and a power supply terminal 1. The capacitor 11, the resistor 12, and the constant voltage circuit 13 constitute an overshoot detection circuit 10. The PMOS transistor 21, the constant current circuit 23, and the inverter 22 constitute a driver state determination circuit 20. The constant current circuit 31, the PMOS transistor 32, and the NMOS transistor 33 constitute an overshoot suppression circuit 30.

[0003] When a power supply voltage VDD is input to the power supply terminal 1, the voltage regulator outputs an output voltage Vout from the output terminal 2. The resistors 4 and 5 divide the output voltage Vout and output a feedback voltage Vfb. The error amplifier circuit 3 compares the reference voltage Vref of the reference voltage circuit 7 input to the inverting input terminal with the feedback voltage Vfb input to the non-inverting input terminal, and controls the gate voltage of the PMOS transistor 6 that operates as an output transistor so that the output voltage Vout becomes constant.

[0004] A process for suppressing fluctuations in the output voltage Vout will be described. As an example, the NMOS transistor 41 is turned off. (1) When an overshoot occurs in the output voltage Vout, in the overshoot detection circuit 10, the capacitor 11 passes an AC current through the resistor 12. (2) The gate voltage of the NMOS transistor 33 rises, and the NMOS transistor 33 turns on. The NMOS transistor 33 flows a drain current that is larger than that of the constant current circuit 31. (3) The gate voltage of the PMOS transistor 32 decreases, and the PMOS transistor 32 turns on. The PMOS transistor 32 flows drain current. (4) The gate voltage of PMOS transistor 6 rises, and PMOS transistor 6 turns off. As the output current decreases, the overshoot of the output voltage Vout is suppressed. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-141463 [Overview of the project] [Problems that the invention aims to solve]

[0006] If the output voltage Vout experiences a DC short circuit (a high voltage short-circuit with low resistance), a high voltage is applied to capacitor 11. For example, if Vout = 12V and constant voltage 13 = 1V, then 12V - 1V = 11V is applied to capacitor 11. Therefore, a high-voltage capacitor with a small capacitance value per unit area is used for capacitor 11. However, using a high-voltage capacitor with a small capacitance value per unit area increases the area of ​​the capacitor element. This increase in the area of ​​the capacitor element leads to increased costs. The object of the present invention is to provide a clamp circuit and an electronic circuit that can limit the voltage applied to a capacitance. [Means for solving the problem]

[0007] One aspect of the present invention is a clamp circuit comprising a current clamp circuit connected between a predetermined terminal included in the circuit and a capacitor, and a voltage clamp circuit connected between the connection point between the current clamp circuit and the capacitor and ground.

[0008] One aspect of the present invention is an electronic circuit comprising: a reference voltage circuit for generating a reference voltage; an output transistor for outputting an output voltage; an error amplification circuit for amplifying and outputting the difference between the voltage based on the output voltage output by the output transistor and the reference voltage, and for controlling the gate of the output transistor; an overshoot detection circuit for which the voltage based on the output voltage is input to an input terminal; and an overshoot suppression circuit for which the output of the overshoot detection circuit is input to an input terminal and whose output terminal is connected to the output terminal of the error amplification circuit, wherein the electronic circuit further comprises a clamp circuit connected to a capacitor included in the overshoot detection circuit and for limiting the voltage applied to the capacitor.

[0009] One aspect of the present invention is an electronic circuit comprising: a differential amplifier circuit having a pair of differential input terminals; an output amplifier circuit having an output terminal and including an amplifying element and a constant current source for amplifying the output of the differential amplifier circuit; and a phase compensation circuit connected between the differential amplifier circuit and the output amplifier circuit, wherein the phase compensation circuit includes an inverting amplifier circuit through which a current proportional to the current flowing to the amplifying element of the output amplifier circuit flows, a first capacitor, a second capacitor, and a clamp circuit, the first capacitor being connected between the output terminal of the differential amplifier circuit and the output terminal of the output amplifier circuit, the second capacitor and the clamp circuit being connected between the output terminal of the inverting amplifier circuit and the output terminal of the output amplifier circuit, the input terminal of the inverting amplifier circuit being connected to the output terminal of the differential amplifier circuit, and the clamp circuit limiting the voltage applied to the second capacitor. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a clamp circuit and an electronic circuit that can limit the voltage applied to a capacitance. [Brief explanation of the drawing]

[0011] [Figure 1] This is a circuit diagram showing an example of a voltage regulator. [Figure 2] This figure shows an example of a clamp circuit according to this embodiment. [Figure 3] This is a diagram showing an example of a voltage clamp circuit of the clamp circuit according to this embodiment. [Figure 4] This is a diagram showing an example of the operation of a voltage clamp circuit of the clamp circuit according to this embodiment. [Figure 5] This is a circuit diagram showing an example of a voltage regulator. [Figure 6] This is a circuit diagram showing an example of an operational amplifier. [Figure 7] This is a diagram showing an example of a current clamp circuit included in the clamp circuit according to Modification 1 of the embodiment. [Figure 8] This is a diagram showing an example of a current clamp circuit included in the clamp circuit according to Modification 2 of the embodiment. [Figure 9] This is a diagram showing an example of a voltage clamp circuit included in the clamp circuit according to Modification 3 of the embodiment. [Figure 10] This is a diagram showing an example of a voltage clamp circuit included in the clamp circuit according to Modification 4 of the embodiment. [Figure 11] This is a diagram showing an example of a voltage clamp circuit included in the clamp circuit according to Modification 5 of the embodiment.

Mode for Carrying Out the Invention

[0012] Next, the clamp circuit and the electronic circuit of this embodiment will be described while referring to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments. In all the drawings for explaining the embodiments, those having the same function are denoted by the same reference numerals, and repeated explanations are omitted. Also, as used in this application, "based on XX" means "at least based on XX", and includes cases where it is based on another element in addition to XX. Also, "based on XX" is not limited to the case where XX is directly used, and includes cases where it is based on something obtained by performing operations or processing on XX. "XX" is an arbitrary element (for example, arbitrary information).

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment) FIG. 2 is a diagram showing an example of a clamp circuit according to the present embodiment. The clamp circuit 200 of the present embodiment includes a current clamp circuit 202 and a voltage clamp circuit 204. An example of the clamp circuit 200 is connected to a predetermined terminal of the internal circuit 50, for example, an output terminal, via a capacitor 206. Hereinafter, as an example, the case where the clamp circuit 200 is connected to the output terminal of the internal circuit 50 via the capacitor 206 will be continued to be described. Specifically, in the capacitor 206, the first terminal is connected to the output terminal of the internal circuit 50, and the second terminal is connected to the current clamp circuit 202 and the voltage clamp circuit 204.

[0014] An example of the current clamp circuit 202 is a depletion-type NMOS transistor. The depletion-type NMOS transistor functions as a current source. In the current clamp circuit 202, the gate, source, and back gate of the depletion-type NMOS transistor are connected. In the depletion-type NMOS transistor, the node to which the gate, source, and back gate are connected is connected to the capacitor 206 and the voltage clamp circuit 204, and the drain is connected to the output terminal. The depletion-type NMOS transistor clamps the current flowing through the voltage clamp circuit 204 to a low current (hereinafter referred to as "current Iclamp") that can be supplied by the current source. In the current clamp circuit 202, the depletion-type NMOS transistor is designed such that the current Iclamp is higher than the AC current flowing through the capacitor 206 supplied to the internal circuit 50 and lower than the current that can be supplied by the voltage clamp circuit 204.

[0015] An example of the voltage clamp circuit will be described. FIG. 3 is a diagram showing an example of the voltage clamp circuit of the clamp circuit according to the present embodiment. The voltage clamp circuit 204 comprises a voltage circuit 212 and a PMOS transistor 214. In the voltage circuit 212, the positive terminal is connected to the gate of the PMOS transistor 214, and the negative terminal is connected to the ground terminal 216. In the PMOS transistor 214, the source is connected to the back gate and is connected to the output terminal of the internal circuit 50 via a capacitor 206. The drain of the PMOS transistor 214 is connected to the ground terminal 218.

[0016] Current flows through the PMOS transistor 214 when a clamp voltage is applied between its gate and source. The clamp voltage is the voltage at which the PMOS transistor turns on. In the voltage clamp circuit 204, the voltage circuit 212 applies a voltage V2 to the gate of the PMOS transistor 214. When a voltage V2 is applied to the gate of the PMOS transistor 214 by the voltage circuit 212, a voltage VGSP is applied between the gate and the source. When the sum of voltage V2 and voltage VGSP exceeds the voltage threshold VTH, current flows through the PMOS transistor 214.

[0017] Figure 4 shows an example of the operation of the voltage clamp circuit of the clamp circuit according to this embodiment. In Figure 4, the horizontal axis is the voltage V1, and the vertical axis is the drain current of the PMOS transistor 214. In the PMOS transistor 214, the drain current of the PMOS transistor 214 increases as the voltage VGSP increases. When the voltage VGSP increases further and the sum of voltage V2 and voltage VGSP exceeds the clamp voltage, the drain current of the PMOS transistor is limited to the current Iclamp. Return to Figure 2 and continue the explanation.

[0018] An example of the internal circuit 50 is an electronic circuit such as a voltage regulator and a phase compensation circuit. The voltage regulator and the phase compensation circuit will be explained below. Voltage regulators will be explained. Figure 5 is a circuit diagram showing an example of a voltage regulator. The voltage regulator includes an error amplification circuit 103, PMOS transistors 121, 132, and 106, NMOS transistors 141 and 133, a reference voltage circuit 107, constant current circuits 123 and 131, a constant voltage circuit 113, resistors 104, 105, and 112, a capacitor 111, an inverter 122, a ground terminal 100, an output terminal 102, and a power supply terminal 101. The overshoot detection circuit 110 is composed of a capacitor 111, a resistor 112, and a constant voltage circuit 113. The driver state determination circuit 120 is composed of a PMOS transistor 121, a constant current circuit 123, and an inverter 122. The constant current circuit 131, the PMOS transistor 132, and the NMOS transistor 133 constitute the overshoot suppression circuit 130.

[0019] Next, we will explain how to connect the voltage regulator. The error amplification circuit 103 has an inverting input terminal connected to the positive terminal of the reference voltage circuit 107, a non-inverting input terminal connected to the connection point of resistors 104 and 105, and an output terminal connected to the gate of the PMOS transistor 106. The negative terminal of the reference voltage circuit 107 is connected to the ground terminal 100, the other terminal of resistor 105 is connected to the ground terminal 100, and the other terminal of resistor 104 is connected to the output terminal 102.

[0020] Capacitor 111 has one terminal connected to the clamp circuit 200 and the other terminal connected to the gate of the NMOS transistor 133. One terminal of resistor 112 is connected to the gate of NMOS transistor 133, and the other terminal is connected to the positive terminal of the constant voltage circuit 113 via resistor 112. The negative terminal of the constant voltage circuit 113 is connected to the ground terminal 100.

[0021] The gate of the PMOS transistor 121 is connected to the output terminal of the error amplifier circuit 103, the drain is connected to the input of the inverter 122, and the source is connected to the power supply terminal 101. One terminal of the constant current circuit 123 is connected to the input of the inverter 122, and the other terminal is connected to the ground terminal 100. The gate of the NMOS transistor 141 is connected to the output of the inverter 122, the drain is connected to the gate of the NMOS transistor 133, and the source is connected to the ground terminal 100. The drain of the NMOS transistor 133 is connected to the gate of the PMOS transistor 132, and the source is connected to the ground terminal 100.

[0022] The constant current circuit 131 has one terminal connected to the power supply terminal 101 and the other terminal connected to the gate of the PMOS transistor 132. The drain of PMOS transistor 132 is connected to the gate of PMOS transistor 106, and the source is connected to the power supply terminal 101. The drain of the PMOS transistor 106 is connected to the output terminal 102, and the source is connected to the power supply terminal 101.

[0023] Next, we will explain the operation of the voltage regulator. When the power supply voltage VDD is input to the power supply terminal 101, the voltage regulator outputs an output voltage Vout from the output terminal 102. Resistors 104 and 105 divide the output voltage Vout and output a feedback voltage Vfb. The error amplification circuit 103 compares the reference voltage Vref of the reference voltage circuit 107, which is input to the inverting input terminal, with the feedback voltage Vfb, which is input to the non-inverting input terminal, and controls the gate voltage of the PMOS transistor 106, which operates as an output transistor, so that the output voltage Vout remains constant. If the output voltage Vout experiences a DC short circuit (a high voltage short-circuit with low resistance), the PMOS transistor 106 will turn off. In the current clamp circuit 202 of the clamp circuit 200, the depletion-type NMOS transistor will clamp to the current Iclamp that the current source can supply.

[0024] Phase compensation circuits will be explained. As an example, an operational amplifier including a phase compensation circuit will be described. Figure 6 is a circuit diagram showing an example of an operational amplifier. The operational amplifier includes a differential amplifier circuit 326 having a pair of differential input terminals 301 and 302 for receiving differential input signals Vin- and Vin+, and an output terminal 303 for outputting an output signal, a phase compensation circuit 327, and an output amplifier circuit 328 having an output terminal 308 for outputting an output signal Vout.

[0025] The differential amplifier circuit 326 consists of input MOS transistors 310 and 311, load MOS transistors 313 and 314, and a MOS transistor 312 that operates as a current source. The output signal of the differential amplifier circuit 326 is supplied from the output terminal 303 to the inverting amplifier circuit 319 of the phase compensation circuit 327 and to the gate terminal of the MOS transistor 321 of the output amplifier circuit 328. Load MOS transistor 313 has its source terminal connected to the power supply voltage, and its gate terminal and drain terminal connected. Load MOS transistor 314 has its source terminal connected to the power supply voltage, its gate terminal connected to the drain terminal of load MOS transistor 313, and its drain terminal connected to output terminal 303.

[0026] The input MOS transistor 310 has its drain terminal connected to the drain terminal of the load MOS transistor 313, and its gate terminal connected to the differential input terminal 301. The input MOS transistor 311 has its drain terminal connected to the output terminal 303, and its gate terminal connected to the differential input terminal 302. The MOS transistor 312 has its drain terminal connected to the source terminals of the input MOS transistors 310 and 311, its gate terminal connected to the input terminal 307 which controls the amount of current, and its source terminal is grounded.

[0027] The phase compensation circuit 327 consists of an inverting amplifier circuit 319, capacitors 322 and 324, and a clamp circuit 200. One terminal of capacitor 322 is connected to the output terminal 306 of the inverting amplifier circuit 319, and the other terminal is connected to the output terminal 308 of the output amplifier circuit 328 via the clamp circuit 200. Furthermore, one terminal of capacitor 324 is connected to the output terminal 303 of differential amplifier circuit 326, and the other terminal is connected to the output terminal 308 of output amplifier circuit 328. The input terminal of inverting amplifier circuit 319 is connected to the output terminal 303 of differential amplifier circuit 326.

[0028] The output amplifier circuit 328 consists of a MOS transistor 321, which acts as an amplifying element to amplify the output signal of the differential amplifier circuit 326, and a MOS transistor 320, which acts as a constant current source. Its output signal Vout is supplied to the outside from the output terminal 308. Output terminal 308 is connected to capacitors 322 and 324 of the phase compensation circuit 327. The source terminal of the MOS transistor 321 is connected to the power supply voltage, the gate terminal is connected to the output terminal 303 of the differential amplifier circuit 326, and the drain terminal is connected to output terminal 308.

[0029] MOS transistor 320 has its drain terminal connected to output terminal 308, its gate terminal connected to input terminal 307, and its source terminal grounded. Capacitor 323 (capacitance value C2) is connected between output terminal 308 and ground. Capacitor 323 includes the drain capacitance of MOS transistors 320 and 321, the parasitic capacitance of elements connected to the output terminals, and the wiring capacitance of the output terminals. Figure 6 illustrates the case where load MOS transistors 313 and 314 and MOS transistor 321 are P-type, and input MOS transistors 310 and 311 and MOS transistors 312 and 320 are N-type.

[0030] Next, we will explain the operation of the operational amplifier shown in Figure 6. The output signal of the differential amplifier circuit 326 is input to the gate terminal of the MOS transistor 321 of the output amplifier circuit 328, and the current signal amplified by the MOS transistor 321 is output from the output terminal 308. In this case, if the voltage at the output terminal 303 of the differential amplifier circuit 326 is V3 and the transformer (trans)conductance value of the MOS transistor 321 is gm2, then the output current Iout output to the output terminal 308 is Iout = (-gm2·V3).

[0031] On the other hand, the signal input from output terminal 303 to the input terminal of the inverting amplifier circuit 319 with amplification factor (-A) is output from output terminal 306 as a voltage signal with output voltage (-A·V3). The voltage signal from output terminal 306 is passed through capacitor 322 (capacitance value C1) with impedance (1 / sC1) and clamp circuit 200, and a current signal with output current Iout = (-A·sC1·V3) is output to output terminal 308. Similarly, a current signal with output current Iout = (sC5·V3) is output to output terminal 308 via capacitor 324 (capacitance value C5) with impedance (1 / sC5). Here, the sum of the output currents Iout flowing through the three signal paths from output terminal 303 to output terminal 308 is B(s) = (-gm2·V3) + (-A·sC1·V3) + sC5·V3. To find the sum of the output currents Iout, the transfer function must be calculated precisely, but the zero point Z1 of the transfer function can be found as the value of the point where B(s) is zero.

[0032] If the signal in the 322 capacitance path is small and negligible compared to other signals, then Z1 = -gm2 / (A·sC1). This zero point Z1 has a negative sign, which has the effect of increasing the phase margin. Furthermore, since the zero point Z1 is proportional to gm2 and also proportional to the second pole (-gm2 / C2), by appropriately selecting the amplification factor A of the inverting amplifier circuit 319 and the capacitance value C1 of the capacitor 322, the second pole can be canceled and disabled regardless of the magnitude of the output current Iout output from the operational amplifier. Therefore, the stability of the operational amplifier can be maintained regardless of the magnitude of the output current Iout. If the voltage signal from output terminal 306 experiences a DC short circuit (high voltage with low resistance), the depletion-type NMOS transistor in the current clamp circuit 202 of clamp circuit 200 will clamp the current to Iclamp, which is the current that the current source can supply.

[0033] In the embodiments described above, a configuration in which a clamp circuit 200 is included in a voltage regulator was described as an example, but the invention is not limited to this example. For example, the clamp circuit 200 may be included in an electronic circuit such as a voltage tracker that includes a voltage follower configuration without a voltage divider resistor.

[0034] According to the clamp circuit 200 of this embodiment, the current can be limited by the current clamp circuit 202 connected in series with the capacitance, and then the voltage of the capacitance can be clamped by the voltage clamp circuit 204. Therefore, the voltage related to the capacitance can be limited to below the withstand voltage. For this reason, capacitive elements with a small area per unit capacitance can be used.

[0035] (Modification of Embodiment 1) Figure 7 shows an example of a current clamp circuit included in the clamp circuit according to the modified embodiment 1. The current clamp circuit 202a according to the first modified embodiment is configured to include a depletion-type PMOS transistor. A depletion-type PMOS transistor functions as a current source. In a depletion-type PMOS transistor, the gate, back gate, and source are connected. The node where the gate, back gate, and source are connected is connected to the output terminal. In the current clamp circuit 202a, the depletion-type PMOS transistor clamps the current flowing through the voltage clamp circuit 204 to a low current Iclamp that the current source can supply. In the current clamp circuit 202a, the depletion-type PMOS transistor is designed so that the current Iclamp is higher than the AC current flowing through the capacitor 206 to the internal circuit 50, and lower than the current that the voltage clamp circuit 204 can supply.

[0036] (Modified embodiment 2) Figure 8 shows an example of a current clamp circuit included in a clamp circuit according to a modified example 2 of the embodiment. The current clamp circuit 202b according to the modified embodiment 2 is configured to include a current mirror circuit of a PMOS transistor. The current clamp circuit 202b comprises a PMOS transistor 212b-1, a PMOS transistor 212b-2, and a constant current circuit 212b-3. The second terminal of the capacitor 206 is connected to the drain of the PMOS transistor 212b-2. In the PMOS transistor 212b-2, the source and back gate are connected. The constant current circuit 212b-3 has one terminal connected to the gate and drain of PMOS transistor 212b-1 and the gate of PMOS transistor 212b-2, and the other terminal connected to the ground terminal 218. In PMOS transistor 212b-1, the source and back gate are connected. The node in PMOS transistor 212b-1 where the source and back gate are connected, and the node in PMOS transistor 212b-2 where the source and back gate are connected, are connected to the output terminal. In the current clamp circuit 202b, the current mirror circuit of the PMOS transistor clamps the current flowing through the voltage clamp circuit 204 to the current Iclamp that the current source can supply.

[0037] (Modification of Embodiment 3) Figure 9 shows an example of a voltage clamp circuit included in the clamp circuit according to the modified embodiment 3. The voltage clamp circuit 204a according to the third modified embodiment is composed of multiple PMOS transistors. Figure 9 shows, as an example, a case in which the voltage clamp circuit 204a is composed of two PMOS transistors.

[0038] The voltage clamp circuit 204a comprises a voltage circuit 212, a PMOS transistor 214a-1, and a PMOS transistor 214a-2. In the voltage circuit 212, the positive terminal is connected to the gate of the PMOS transistor 214a-2, and the negative terminal is connected to the ground terminal 216. In PMOS transistor 214a-2, the drain is connected to the ground terminal 218, and the source is connected to the gate and drain of PMOS transistor 214a-1. In PMOS transistor 214a-1, the source is connected to the back gate and the back gate of PMOS transistor 214a-1. In PMOS transistor 214a-1, the node where the source, back gate, and the back gate of PMOS transistor 214a-1 are connected is connected to the output terminal of internal circuit 50 via capacitor 206.

[0039] PMOS transistors 214a-1 and 214a-2 allow current to flow when a clamp voltage is applied between their gate and source. The clamp voltage is the voltage at which the PMOS transistor turns on. In the voltage clamp circuit 204a, the voltage circuit 212 applies a voltage V2 to the gate of the PMOS transistor 214a-2. When the voltage V2 is applied to the gate of the PMOS transistor 214a-2 by the voltage circuit 212, a voltage VGSP is applied between the gate and the source of the PMOS transistor 214a-2. When a voltage VGSP is applied to the gate of PMOS transistor 214a-1 by PMOS transistor 214a-2, a voltage VGSP is applied between the gate and source of PMOS transistor 214a-1. When the sum of voltage V2 and voltage VGSP exceeds the voltage threshold VTH, current flows through PMOS transistors 214a-1 and 214a-2. Here, if a voltage clamp circuit is constructed including n (where n is an integer n>0) PMOS transistors, then when n × VGSP + V2 exceeds the voltage threshold VTH, current flows through the n PMOS transistors.

[0040] (Modification of Embodiment 4) Figure 10 shows an example of a voltage clamp circuit included in a clamp circuit according to a modified example of the embodiment 4. The voltage clamp circuit 204b according to the fourth modified embodiment is composed of multiple NMOS transistors. Figure 10 shows, as an example, a case in which the voltage clamp circuit 204b is composed of three NMOS transistors. The voltage clamp circuit 204b comprises NMOS transistors 214b-1, 214b-2, and 214b-3. The source of NMOS transistor 214b-3 is connected to the back gates of NMOS transistor 214b-1, 214b-2, and 214b-3. The source of NMOS transistor 214b-3, the back gate of NMOS transistor 214b-1, the back gate of NMOS transistor 214b-2, and the node connected to the back gate of NMOS transistor 214b-3 are connected to the ground terminal 218. The gate and drain of NMOS transistor 214b-3 are connected to the source of NMOS transistor 214b-2. The gate and drain of NMOS transistor 214b-2 are connected to the source of NMOS transistor 214b-1. The gate and drain of NMOS transistor 214b-1 are connected to the output terminal of internal circuit 50 via capacitor 206. In Figure 10, the clamp voltage is represented as 3 × VGSN.

[0041] (Modification of Embodiment 5) Figure 11 shows an example of a voltage clamp circuit included in a clamp circuit according to modified embodiment 5. The voltage clamp circuit 204c according to the modified embodiment 5 is configured to include a Zener diode 214c. In the Zener diode 214c, the anode is grounded and the cathode is connected to the output terminal of the internal circuit 50 via a capacitor 206. The clamp voltage is represented by the Zener voltage Vz.

[0042] Although embodiments and modified embodiments 1 to 5 of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to the embodiments and modified embodiments 1 to 5, and includes design changes and the like that do not depart from the gist of the present invention. For example, the embodiments and modified embodiments 1 to 5 described above may be combined in any way. [Explanation of symbols]

[0043] 50…Internal circuit 103…Error amplification circuit 121, 132, 106… PMOS transistors 141, 133…NMOS transistors 107...Reference voltage circuit 123, 131... Constant current circuit 113... Constant voltage circuit 104, 105, 112… Resistors 111...Capacity 122... Inverter 100...Ground terminal 102…Output terminal 101…Power terminal 200... Clamp circuit 202...Current clamp circuit 204...Voltage clamp circuit 206…Capacity 212...Voltage Circuit 214…PMOS transistor 218...Ground terminal 301, 302… Differential input terminals 303, 308… Output terminals 310, 311… Input MOS transistors 312, 321…MOS transistors 313, 314… Load MOS transistors 319... Inverting amplifier circuit 326…Differential amplifier circuit 327…Phase compensation circuit 328…Output Amplifier Circuit

Claims

1. A clamp circuit comprising a current clamp circuit and a voltage clamp circuit, A clamp circuit in which one end of the current clamp circuit and one end of the voltage clamp circuit are commonly connected to a connection point that is connected to a second terminal of a capacitor whose first terminal is connected to a predetermined terminal included in an electronic circuit, the other end of the current clamp circuit is connected to an output terminal, and the other end of the voltage clamp circuit is connected to ground.

2. The clamp circuit according to claim 1, wherein the current clamp circuit includes a depletion transistor or a current mirror circuit.

3. The clamp circuit according to claim 1 or claim 2, wherein the voltage clamp circuit includes one or more transistors.

4. A reference voltage circuit that generates a reference voltage, An output transistor that outputs an output voltage, An error amplification circuit that amplifies and outputs the difference between the voltage based on the output voltage output by the output transistor and the reference voltage, and controls the gate of the output transistor, An overshoot detection circuit is input to an input terminal, where a voltage based on the output voltage is input. An electronic circuit comprising: an overshoot suppression circuit whose input terminal receives the output of the overshoot detection circuit and whose output terminal is connected to the output terminal of the error amplification circuit, An electronic circuit comprising a clamp circuit according to any one of claims 1 to 3, which is connected to a capacitor included in the overshoot detection circuit and limits the voltage applied to the capacitor.

5. An electronic circuit comprising: a differential amplifier circuit having a pair of differential input terminals; an output amplifier circuit having an output terminal and including an amplifying element and a constant current source for amplifying the output of the differential amplifier circuit; and a phase compensation circuit connected between the differential amplifier circuit and the output amplifier circuit, The phase compensation circuit includes an inverting amplifier circuit through which a current proportional to the current flowing through the amplifying element of the output amplifier circuit flows, a first capacitor, a second capacitor, and a clamping circuit. The first capacitance is connected between the output terminal of the differential amplifier circuit and the output terminal of the output amplifier circuit. The second capacitor and the clamp circuit are connected between the output terminal of the inverting amplifier circuit and the output terminal of the output amplifier circuit. The input terminal of the inverting amplifier circuit is connected to the output terminal of the differential amplifier circuit. The clamp circuit comprises the clamp circuit according to any one of claims 1 to 3, which limits the voltage applied to the second capacitance.

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