Display device and method for manufacturing the same

Abstract

To provide a display device capable of improving reliability, and a method for manufacturing the display device.SOLUTION: A display device according to an embodiment, comprises: a first display element that contains a first lower electrode, a first upper electrode, and a first organic layer emitting a light in accordance with a voltage between the first lower electrode and the first upper electrode; a second display element that contains a second lower electrode and a second upper electrode, and a second organic layer emitting a light in accordance with a voltage between the second lower electrode and the second upper electrode; and a barrier wall that is arranged between the first display element and the second display element. The barrier wall comprises: a lower part having a first side surface on the first display element and a second side surface on the second display element; and an upper part that includes a first end part projected from the first side surface and a second end part projected from the second side surface. The first end part has a light blocking property, and the second end part has translucency.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] In manufacturing the above-described display device, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device and a method for manufacturing the same that can improve reliability.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a first display element comprising a first lower electrode, a first upper electrode, and a first organic layer that emits light in response to a voltage between the first lower electrode and the first upper electrode; a second display element comprising a second lower electrode, a second upper electrode, and a second organic layer that emits light in response to a voltage between the second lower electrode and the second upper electrode; and a partition wall disposed between the first display element and the second display element. The partition wall comprises a lower portion having a first side surface on the first display element side and a second side surface on the second display element side, and an upper portion having a first end protruding from the first side surface and a second end protruding from the second side surface. The first end is light-shielding, and the second end is light-transmitting.

[0007] In a method for manufacturing a display device according to one embodiment, a first lower electrode and a second lower electrode are formed, and a partition wall is formed having a lower part having a first side surface on the first lower electrode side and a second side surface on the second lower electrode side, and an upper part having a light-shielding first end protruding from the first side surface and a light-transmitting second end protruding from the second side surface. A first organic layer including a light-emitting layer, a first upper electrode covering the first organic layer, a first sealing layer made of an inorganic material, and a first resist covering the first sealing layer are formed in order on the first lower electrode, the second lower electrode, and the partition wall. The portion of the first resist that overlaps with the second lower electrode and the second end is exposed, and the exposed portion of the first resist is removed by exposing the first resist to a developer solution. The portion of the first organic layer, the first upper electrode, and the first sealing layer exposed from the first resist is removed by first etching to form a first display element including the first lower electrode, the first organic layer, and the first upper electrode. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3]FIG. 3 is a schematic cross-sectional view of the display device along line III-III in FIG. 2. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged view of a partition wall disposed between the first sub-pixel and the second sub-pixel and its vicinity. [Figure 5] FIG. 5 is a schematic cross-sectional view showing another example of a structure applicable to the partition wall. [Figure 6] FIG. 6 is a schematic plan view of the partition wall. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing the display device. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing process of the display device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process following FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the manufacturing process following FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the manufacturing process following FIG. 16. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the manufacturing process following FIG. 19. [Figure 21] Figure 21 is a schematic cross-sectional view showing the manufacturing process following FIG. 20. [Figure 22] Figure 22 is a schematic cross-sectional view showing the manufacturing process following FIG. 21. [Figure 23] Figure 23 is a schematic cross-sectional view showing the manufacturing process following FIG. 22. [Figure 24] Figure 24 is a schematic cross-sectional view showing the manufacturing process following FIG. 23. [Figure 25] Figure 25 is a schematic cross-sectional view showing the manufacturing process following FIG. 24. [Figure 26] Figure 26 is a schematic cross-sectional view showing the manufacturing process following FIG. 25.

Mode for Carrying Out the Invention

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and those that can be easily conceived by those skilled in the art for appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each drawing, components that exhibit the same or similar functions as those previously described with respect to the already presented drawings may be given the same reference numerals, and detailed descriptions that are repeated may be omitted as appropriate.

[0010] In the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Looking at various elements parallel to the third direction Z is referred to as a plan view. [[ID=三十二]]

[0011] [[ID=三十三]] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a first sub-pixel SP1 that is blue, a second sub-pixel SP2 that is green, and a third sub-pixel SP3 that is red. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. Display element DE is an organic light-emitting diode (OLED) as a light-emitting element.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, the second sub-pixel SP2 and the first sub-pixel SP1 are aligned in the first direction X. The third sub-pixel SP3 and the first sub-pixel SP1 are also aligned in the first direction X. Furthermore, the third sub-pixel SP3 and the second sub-pixel SP2 are aligned in the second direction Y.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which multiple first sub-pixels SP1 are repeatedly arranged in the second direction Y, and columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have a first pixel aperture AP1 in the first sub-pixel SP1, a second pixel aperture AP2 in the second sub-pixel SP2, and a third pixel aperture AP3 in the third sub-pixel SP3. In the example in Figure 2, the second pixel aperture AP2 is larger than the third pixel aperture AP3, and the first pixel aperture AP1 is larger than the second pixel aperture AP2.

[0022] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between two adjacent first pixel apertures AP1 in the second direction Y, and between adjacent pixel apertures AP2 and AP3 in the second direction Y. The second partition wall 6y is positioned between adjacent pixel apertures AP1 and AP2 in the first direction X, and between adjacent pixel apertures AP1 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0024] The first sub-pixel SP1 comprises a first lower electrode LE1, a first upper electrode UE1, and a first organic layer OR1, which overlap with the first pixel aperture AP1. The second sub-pixel SP2 comprises a second lower electrode LE2, a second upper electrode UE2, and a second organic layer OR2, which overlap with the second pixel aperture AP2. The third sub-pixel SP3 comprises a third lower electrode LE3, a third upper electrode UE3, and a third organic layer OR3, which overlap with the third pixel aperture AP3. In the example in Figure 2, the outlines of the first upper electrode UE1 and the first organic layer OR1 are identical, the outlines of the second upper electrode UE2 and the second organic layer OR2 are identical, and the outlines of the third upper electrode UE3 and the third organic layer OR3 are identical.

[0025] The first lower electrode LE1, the first upper electrode UE1, and the first organic layer OR1 constitute the first display element DE1 of the first sub-pixel SP1. The second lower electrode LE2, the second upper electrode UE2, and the second organic layer OR2 constitute the second display element DE2 of the second sub-pixel SP2. The third lower electrode LE3, the third upper electrode UE3, and the third organic layer OR3 constitute the third display element DE3 of the third sub-pixel SP3.

[0026] For example, the first display element DE1 emits light in the blue wavelength range, the second display element DE2 emits light in the green wavelength range, and the third display element DE3 emits light in the red wavelength range.

[0027] The first lower electrode LE1 is connected to the pixel circuit 1 of the first sub-pixel SP1 (see Figure 1) through the first contact hole CH1. The second lower electrode LE2 is connected to the pixel circuit 1 of the second sub-pixel SP2 through the second contact hole CH2. The third lower electrode LE3 is connected to the pixel circuit 1 of the third sub-pixel SP3 through the third contact hole CH3.

[0028] In the example in Figure 2, the first contact hole CH1 completely overlaps with the first partition 6x between two adjacent first pixel apertures AP1 in the second direction Y. The contact holes CH2 and CH3 completely overlap with the first partition 6x between adjacent pixel apertures AP2 and AP3 in the second direction Y. In another example, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the first partition 6x.

[0029] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the organic insulating layer 12.

[0030] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0031] The partition wall 6 includes a conductive lower section 61 positioned on the rib 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 can also be described as overhanging.

[0032] The upper section 62 includes a light-transmitting transparent layer TP and a light-shielding light-blocking layer LS. In the example shown in Figure 3, the transparent layer TP is positioned on top of the lower section 61, and the light-shielding layer LS is positioned on top of the transparent layer TP.

[0033] In the partition 6 between sub-pixels SP1 and SP2, the light-shielding layer LS covers a portion of the transparent layer TP closer to the first sub-pixel SP1. In the partition 6 between sub-pixels SP1 and SP3, the light-shielding layer LS covers a portion of the transparent layer TP closer to the first sub-pixel SP1.

[0034] The first organic layer OR1 covers the first lower electrode LE1 through the first pixel aperture AP1. The first upper electrode UE1 covers the first organic layer OR1 and faces the first lower electrode LE1. The second organic layer OR2 covers the second lower electrode LE2 through the second pixel aperture AP2. The second upper electrode UE2 covers the second organic layer OR2 and faces the second lower electrode LE2. The third organic layer OR3 covers the third lower electrode LE3 through the third pixel aperture AP3. The third upper electrode UE3 covers the third organic layer OR3 and faces the third lower electrode LE3.

[0035] In the example shown in Figure 3, the first cap layer CP1 is placed on the first upper electrode UE1, the second cap layer CP2 is placed on the second upper electrode UE2, and the third cap layer CP3 is placed on the third upper electrode UE3. The cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0036] A portion of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1 is located above the upper section 62. This portion is separated from the other portions of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1. Similarly, a portion of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2 is located above the upper section 62, and this portion is separated from the other portions of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2. Furthermore, a portion of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 is located above the upper section 62, and this portion is separated from the other portions of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3.

[0037] The first sub-pixel SP1 is covered with the first sealing layer SE1, the second sub-pixel SP2 is covered with the second sealing layer SE2, and the third sub-pixel SP3 is covered with the third sealing layer SE3. The first sealing layer SE1 continuously covers the first cap layer CP1 and the partition wall 6. The second sealing layer SE2 continuously covers the second cap layer CP2 and the partition wall 6. The third sealing layer SE3 continuously covers the third cap layer CP3 and the partition wall 6.

[0038] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0039] The organic insulating layer 12 and the resin layers 13 and 15 are formed from organic materials. The ribs 5 and the sealing layers 14, SE1, SE2, SE3 are formed from inorganic materials such as silicon nitride (SiNx). The ribs 5 and the sealing layers 14, SE1, SE2, SE3 may be formed as single layers of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, the ribs 5 and the sealing layers 14, SE1, SE2, SE3 may be formed as laminates of at least two combinations of silicon nitride layers, silicon oxide layers, silicon oxynitride layers, and aluminum oxide layers.

[0040] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0041] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0042] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0043] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0044] When a potential difference is formed between the first lower electrode LE1 and the first upper electrode UE1, the light-emitting layer of the first organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the second lower electrode LE2 and the second upper electrode UE2, the light-emitting layer of the second organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the third lower electrode LE3 and the third upper electrode UE3, the light-emitting layer of the third organic layer OR3 emits light in the red wavelength range.

[0045] Figure 4 is a schematic, enlarged cross-sectional view of the partition wall 6 located between sub-pixels SP1 and SP2 and its vicinity. In this figure, the substrate 10, circuit layer 11, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0046] The lower part 61 of the partition wall 6 has a first side surface F1 on the side of the first sub-pixel SP1 (side of the first display element DE1) and a second side surface F2 on the side of the second sub-pixel SP2 (side of the second display element DE2). The upper part 62 of the partition wall 6 has a first end portion E1 protruding from the first side surface F1 and a second end portion E2 protruding from the second side surface F2. The first upper electrode UE1 is in contact with the first side surface F1, and the second upper electrode UE2 is in contact with the second side surface F2.

[0047] In the example shown in Figure 4, the lower section 61 has a first metal layer 611 positioned on the rib 5 and a second metal layer 612 positioned on the first metal layer 611. The second metal layer 612 is formed to be thicker than the first metal layer 611.

[0048] The upper transparent layer TP of 62 is formed extending from the first end E1 to the second end E2. In the example in Figure 4, the transparent layer TP has a first transparent layer 621 placed on the first metal layer 611 and a second transparent layer 622 placed on the first transparent layer 621.

[0049] The light-shielding layer LS of the upper 62 is positioned on the second transparent layer 622 at least at the first end E1, but not at the second end E2. That is, the first end E1 includes the transparent layer TP and the light-shielding layer LS. On the other hand, the second end E2 includes the transparent layer TP but does not include the light-shielding layer LS. In the example in Figure 4, the light-shielding layer LS also extends to the region between the first end E1 and the second end E2.

[0050] The light-shielding layer LS does not necessarily have to be placed on top of the transparent layer TP. As another example, the light-shielding layer LS may be placed below the transparent layer TP. Alternatively, the light-shielding layer LS may be placed between the first transparent layer 621 and the second transparent layer 622.

[0051] The first metal layer 611 is formed of, for example, molybdenum (Mo). The second metal layer 612 is formed of, for example, aluminum (Al). The second metal layer 612 may be formed of an aluminum alloy, or it may have a laminated structure of aluminum and an aluminum alloy.

[0052] The first transparent layer 621 is formed of, for example, silicon oxide. The second transparent layer 622 is formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), and IGZO (IndiumGalliumZinc Oxide).

[0053] The light-shielding layer LS is formed of, for example, titanium (Ti). Preferably, the light-shielding layer LS has a transmittance of 10% or less for at least one, preferably both, of light with a wavelength of 436 nm (g-line) and light with a wavelength of 405 nm (h-line).

[0054] In the examples shown in Figures 3 and 4, the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1 on the upper part 62 are spaced apart from the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2 on the upper part 62.

[0055] The first sealing layer SE1 continuously covers the first display element DE1, the first side surface F1, and the first end surface E1. The second sealing layer SE2 continuously covers the second display element DE2, the second side surface F2, and the second end surface E2. The ends of the first sealing layer SE1 and the ends of the second sealing layer SE2 are located above the upper part 62 and are spaced apart from each other.

[0056] Below the first end E1, a void V is formed that is not filled by the first sealing layer SE1. Below the second end E2, a void V is also formed that is not filled by the second sealing layer SE2.

[0057] The first organic layer OR1, the first upper electrode UE1, the first cap layer CP1, and a portion of the first sealing layer SE1 are located on top of the light-shielding layer LS. In the example in Figure 4, these portions are not in contact with the second transparent layer 622. In other examples, these portions may be in contact with the second transparent layer 622.

[0058] Figure 5 is a schematic cross-sectional view showing another example of a structure that can be applied to the partition wall 6. In this example, the lower part 61 has a single-layer structure. The transparent layer TP also has a single-layer structure.

[0059] The lower part 61 of the single-layer structure can be formed from, for example, aluminum or an aluminum alloy. The transparent layer TP of the single-layer structure can be formed from, for example, silicon oxide.

[0060] The structure of the partition wall 6 is not limited to the examples shown in Figures 4 and 5. For example, the lower section 61 may have a laminated structure and the transparent layer TP may have a single-layer structure. Alternatively, the lower section 61 may have a single-layer structure and the transparent layer TP may have a laminated structure.

[0061] The configuration of the partition 6 between subpixels SP1 and SP3 and its vicinity is the same as the configuration of the partition 6 between subpixels SP1 and SP2 and its vicinity shown in Figure 4 or Figure 5.

[0062] Figure 6 is a schematic plan view of partition wall 6. The area with the dot pattern corresponds to the transparent layer TP, and the area with the diagonal pattern corresponds to the light-shielding layer LS. The light-shielding layer LS overlaps with the transparent layer TP overall.

[0063] The transparent layer TP is a grid surrounding the sub-pixels SP1, SP2, SP3 (display elements DE1, DE2, DE3). The light-shielding layer LS surrounds the first sub-pixel SP1 (first display element DE1).

[0064] Specifically, the light-shielding layer LS is provided over the entire first partition wall 6x between adjacent first sub-pixels SP1 in the second direction Y. Furthermore, the light-shielding layer LS is provided over a portion of the second partition wall 6y between sub-pixels SP1 and SP2 that is closer to the first sub-pixel SP1, and over a portion of the second partition wall 6y between sub-pixels SP1 and SP3 that is closer to the first sub-pixel SP1.

[0065] The shape of the light-shielding layer LS is not limited to the example in Figure 6. For example, the light-shielding layer LS may be frame-shaped, surrounding each individual first subpixel SP1, and the light-shielding layers LS surrounding adjacent first subpixel SP1s may be spaced apart.

[0066] Next, we will explain the manufacturing method of the DSP display device. Figure 7 is a flowchart showing an example of a method for manufacturing a DSP display device. Figures 8 to 26 are schematic cross-sectional views showing part of the manufacturing process of a DSP display device.

[0067] In the manufacturing of a display device DSP, a circuit layer 11 and an organic insulating layer 12 are first formed on a substrate 10 (step P1 in Figure 7).

[0068] After step P1, as shown in Figure 8, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step P2 in Figure 7).

[0069] After step P2, an insulating layer 5a, which will form the base of the rib 5, is formed as shown in Figure 9 (step P3 in Figure 7). The insulating layer 5a is made of an inorganic material such as silicon nitride and covers the lower electrodes LE1, LE2, and LE3.

[0070] After step P3, the partition wall 6 is formed (step P4 in Figure 7). Specifically, as shown in Figure 10, first a metal layer 61a, which will be the base for the lower layer 61, is formed on the insulating layer 5a, a transparent layer TPa, which will be the base for the transparent layer TP, is formed on the metal layer 61a, a light-shielding layer LSa, which will be the base for the light-shielding layer LS, is formed on the transparent layer TPa, and a resist R11 is formed on the light-shielding layer LSa. The resist R11 is patterned to the shape of the light-shielding layer LS shown in Figure 6, for example.

[0071] If the lower part 61 includes a first metal layer 611 and a second metal layer 612 as shown in Figure 4, then the metal layer 61a includes two layers formed from the materials of these metal layers 611 and 612. If the transparent layer TP includes a first transparent layer 621 and a second transparent layer 622 as shown in Figure 4, then the transparent layer TPa includes two layers formed from the materials of these transparent layers 621 and 622.

[0072] Next, as shown in Figure 11, the portion of the light-shielding layer LSa exposed from resist R11 is removed by etching using resist R11 as a mask. This forms the light-shielding layer LS, as shown in Figure 11. After the formation of the light-shielding layer LS, resist R11 is removed.

[0073] Next, as shown in Figure 12, a resist R12 corresponding to the shape of the partition wall 6 is formed on the transparent layer TPa and the light-shielding layer LS. Furthermore, by etching using the resist R12 as a mask, the portions of the transparent layer TPa and the metal layer 61a exposed from the resist R12 are removed. As a result, the upper part 62 including the transparent layer TP and the light-shielding layer LS is formed, as shown in Figure 13. In the example in Figure 13, a portion of the metal layer 61a exposed from the resist R12 remains. For example, the etching of the transparent layer TPa is wet etching, and the etching of the metal layer 61a is anisotropic dry etching.

[0074] Next, isotropic wet etching is performed on the metal layer 61a. For example, an etching solution containing phosphoric acid, nitric acid, and acetic acid is used for this wet etching. This wet etching removes the portion of the metal layer 61a exposed from the resist R12, forming the lower part 61 as shown in Figure 14. In this wet etching, the sides of the lower part 61 are also eroded. As a result, the width of the lower part 61 becomes smaller than the width of the upper part 62, and an overhanging partition wall 6 is obtained. After wet etching, the resist R12 is removed.

[0075] After the formation of the partition wall 6, the insulating layer 5a is patterned as shown in Figure 15 to form the pixel apertures AP1, AP2, and AP3 (step P5 in Figure 7). By forming the pixel apertures AP1, AP2, and AP3 after the formation of the partition wall 6, the lower electrodes LE1, LE2, and LE3 can be protected from etching during the formation of the partition wall 6.

[0076] After step P5, as shown in Figure 16, a first organic layer OR1 that contacts the first lower electrode LE1 through the first pixel aperture AP1, a first upper electrode UE1 covering the first organic layer OR1, a first cap layer CP1 covering the first upper electrode UE1, and a first sealing layer SE1 covering the first cap layer CP1 are sequentially formed by vapor deposition (step P6 in Figure 7). These first organic layer OR1, first upper electrode UE1, first cap layer CP1, and first sealing layer SE1 are formed over at least the entire display area DA and are located not only on the first sub-pixel SP1 but also on the second sub-pixel SP2 and the third sub-pixel SP3.

[0077] After step P6, the first display element DE1 is formed by patterning the first organic layer OR1, the first upper electrode UE1, the first cap layer CP1, and the first sealing layer SE1 (step P7 in Figure 7).

[0078] Specifically, as shown in Figure 17, first a positive-type first resist R21 is formed (applied) that completely covers the first sealing layer SE1. The first resist R21 fills the voids V that form below the first end E1 and second end E2 of each partition wall 6.

[0079] Next, the region of the first resist R21 that overlaps with the lower electrodes LE2 and LE3 in the third direction Z, and the region that overlaps with the second end E2 of each partition wall 6 in the third direction Z, is exposed, excluding the first subpixel SP1 and the first end E1 of the partition wall 6 surrounding it. The light EX1 used for this exposure includes, for example, at least one of light with a wavelength of 436 nm (g-line) and light with a wavelength of 405 nm (h-line).

[0080] The transparent layer TP has good light transmission for these g- and h-rays. Therefore, the first resist R21 that has entered the void V below the second end E2 is also irradiated with light EX1.

[0081] After exposure of the first resist R21, the first resist R21 is developed. That is, by exposing the first resist R21 to the developer, the portion of the first resist R21 that was irradiated with light EX1 is removed, as shown in Figure 18. The first resist R21 that had entered the void V below the second end E2 is also removed in this process.

[0082] After developing the first resist R21, a first etching process using the first resist R21 as a mask removes the portions of the first organic layer OR1, the first upper electrode UE1, the first cap layer CP1, and the first sealing layer SE1 that are exposed from the first resist R21, as shown in Figure 19. For example, the first etching process includes dry etching of the first sealing layer SE1, wet etching or ashing of the first cap layer CP1, wet etching of the first upper electrode UE1, and ashing of the first organic layer OR1. In the dry etching of the first sealing layer SE1, the first cap layer CP1 and the first organic layer OR1 function as etching stoppers.

[0083] Subsequently, as shown in Figure 20, the first display element DE1, which includes the first organic layer OR1, the first upper electrode UE1, the first cap layer CP1, and the first sealing layer SE1, is completed by removing the first resist R21.

[0084] After step P7, as shown in Figure 21, a second organic layer OR2 that contacts the second lower electrode LE2 through the second pixel aperture AP2, a second upper electrode UE2 covering the second organic layer OR2, a second cap layer CP2 covering the second upper electrode UE2, and a second sealing layer SE2 covering the second cap layer CP2 are sequentially formed by vapor deposition (step P8 in Figure 7). These second organic layer OR2, second upper electrode UE2, second cap layer CP2, and second sealing layer SE2 are formed over at least the entire display area DA and are located not only on the second sub-pixel SP2 but also on the first sub-pixel SP1 and the third sub-pixel SP3.

[0085] In the example shown in Figure 21, voids V not filled with sealing layers SE1, SE2, etc. are formed below the first end E1 and below the second end E2 of each partition wall 6.

[0086] After step P8, the second display element DE2 is formed by patterning the second organic layer OR2, the second upper electrode UE2, the second cap layer CP2, and the second sealing layer SE2 (step P9 in Figure 7).

[0087] Specifically, as shown in Figure 22, first a positive-type second resist R22 is formed (applied) that completely covers the second sealing layer SE2, etc. The second resist R22 fills the voids V below the first end E1 and second end E2 of each partition wall 6.

[0088] Next, the region of the second resist R22 is exposed, excluding the second sub-pixel SP2 and the second end E2 of the partition 6 surrounding it, such as the portion overlapping the first display element DE1 in the third direction Z, the portion overlapping the third lower electrode LE3 in the third direction Z, the portion overlapping the partition wall 6 between sub-pixels SP1 and SP3 in the third direction Z, and the portion overlapping the first end E1 of the partition wall 6 between sub-pixels SP1 and SP2 in the third direction Z. The light EX2 used for this exposure includes, for example, at least one of the g-line and the h-line, just like the light EX1 described above.

[0089] Light EX2 also irradiates the second resist R22, which has entered the void V located below the second end E2 of the partition wall 6 surrounding the third subpixel SP3. On the other hand, light EX2 is blocked by the light-shielding layer LS. Therefore, the second resist R22, which has entered the void V located below the first end E1 having the light-shielding layer LS, is hardly irradiated by light EX2.

[0090] After exposure of the second resist R22, the second resist R22 is developed. That is, by exposing the second resist R22 to the developer, the portion of the second resist R22 that was irradiated with light EX2 is removed, as shown in Figure 23. The second resist R22 that had entered the void V located below the second end E2 of the partition wall 6 surrounding the third subpixel SP3 is also removed in this process. On the other hand, the second resist R22 that had entered the void V located below the first end E1 of each partition wall 6 remains without being removed by the developer. Hereinafter, the second resist R22 remaining in the void V will be referred to as the residual portion R22a.

[0091] After developing the second resist R22, a second etching process using the second resist R22 as a mask removes the portions of the second organic layer OR2, second upper electrode UE2, second cap layer CP2, and second sealing layer SE2 that are exposed from the second resist R22, as shown in Figure 24. The remaining portion 22a remains even after the second etching is performed. For example, the second etching process includes dry etching of the second sealing layer SE2, wet etching or ashing of the second cap layer CP2, wet etching of the second upper electrode UE2, and ashing of the second organic layer OR2. In the dry etching of the second sealing layer SE2, the second cap layer CP2 and the second organic layer OR2 function as etching stoppers.

[0092] Subsequently, as shown in Figure 25, the second display element DE2, which includes the second organic layer OR2, the second upper electrode UE2, the second cap layer CP2, and the second sealing layer SE2, is completed by removing the second resist R22 and the remaining portion R22a.

[0093] The third display element DE is formed using the same procedure as the first display element DE1 and the second display element DE2. Specifically, the third organic layer OR3, which contacts the third lower electrode LE3 through the third pixel aperture AP3, the third upper electrode UE3 covering the third organic layer OR3, the third cap layer CP3 covering the third upper electrode UE3, and the third sealing layer SE3 covering the third cap layer CP3 are formed sequentially by vapor deposition (step P10 in Figure 7).

[0094] Furthermore, through patterning similar to that in steps P7 and P9, a third display element DE3, including a third organic layer OR3, a third upper electrode UE3, a third cap layer CP3, and a third sealing layer SE3, is formed on the third sub-pixel SP3 as shown in Figure 26 (step P11 in Figure 7). This patterning process includes the formation of a positive-type third resist that completely covers the third sealing layer SE3, exposure and development of the third resist, and third etching using the third resist as a mask. For example, light including g-line and h-line light, similar to light EX1 and EX2, is used for exposure of the third resist. After development of the third resist, a residual portion of the third resist may form below the first end E1, similar to the residual portion R22a described above.

[0095] After the display elements DE1, DE2, and DE3 are formed, the resin layer 13, sealing layer 14, and resin layer 15 shown in Figure 3 are formed in sequence, completing the display device DSP (step P12 in Figure 7).

[0096] In this embodiment, the upper part 62 of the partition wall 6 adjacent to the first sub-pixel SP1 has a light-shielding first end E1 and a light-transmitting second end E2. With this configuration, the reliability of the display device DSP can be improved when manufacturing the display device DSP using the manufacturing method illustrated in Figures 7 to 26.

[0097] In other words, if, during exposure of the first resist R21 shown in Figure 17, the light EX1 does not sufficiently irradiate the first resist R21 that has entered the void V below the second end E2, a residual portion of the first resist R21 will remain in the void V even after development of the first resist R21. If such a residual portion remains, in the subsequent first etching, the portion of the first sealing layer SE1, the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1 that is covered by this residual portion will not be removed, and the formation of the display elements DE2 and DE3 may be hindered. For example, if the remaining first sealing layer SE1, etc., creates a region where the upper electrodes UE2 and UE3 do not contact the lower part 61 of the partition wall 6, good conductivity between the upper electrodes UE2 and UE3 and the lower part 61 cannot be ensured.

[0098] In contrast, if the second end portion E2 has good light transmittance to light EX1, as in this embodiment, light EX1 is also irradiated onto the first resist R21 that has entered the void V below the second end portion E2. Therefore, the formation of residual portions of the first resist R21 in the void V can be suppressed. As a result, a highly reliable display device DSP equipped with a second display element DE2 and a third display element DE3 with good shape can be manufactured.

[0099] On the other hand, if the upper part 62 is translucent overall, when the second resist R22 shown in Figure 22 is exposed, the light EX2 will also irradiate the second resist R22 that has entered the void V below the first end E1. In this case, the residual portion R22a shown in Figure 23 will not be formed. Near the void V below the first end E1, the first sealing layer SE1 and the second sealing layer SE2 are thin, and the second cap layer CP2 and the second organic layer OR2, which act as etching stoppers for dry etching of the second sealing layer SE2, are not sufficiently formed. Therefore, in the second and third etching processes, the first sealing layer SE1 and the first display element DE1 below the first end E1 may be damaged.

[0100] In contrast, when the first end portion E1 has light-shielding properties, as in this embodiment, a residual portion R22a is formed in the void V below the first end portion E1. This residual portion R22a protects the first sealing layer SE1 and the first display element DE1 below the first end portion E1 from second and third etching. As a result, a highly reliable display device DSP with a first display element DE1 in good shape can be manufactured.

[0101] All display devices and manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the display device and manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0102] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0103] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0104] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP...Sub-pixel, LE...Lower electrode, OR...Organic layer, UE...Upper electrode, SE...Sealing layer, DE...Display element, 5...Rib, 6...Partition wall, 61...Lower part of partition wall, F1...First side of the lower part, F2...Second side of the lower part, 62...Upper part of partition wall, E1...First end of the upper part, E2...Second end of the upper part.

Claims

1. A first display element comprising a first lower electrode, a first upper electrode, and a first organic layer that emits light in response to the voltage between the first lower electrode and the first upper electrode, A second display element comprising a second lower electrode, a second upper electrode, and a second organic layer that emits light in response to the voltage between the second lower electrode and the second upper electrode, A partition wall is disposed between the first display element and the second display element, Equipped with, The aforementioned partition wall is A lower part having a first side surface on the first display element side and a second side surface on the second display element side, An upper part having a first end protruding from the first side surface and a second end protruding from the second side surface, Equipped with, The first end has light-shielding properties, and the second end has light-transmitting properties. Display device.

2. The aforementioned upper part is, A transparent layer extending from the first end to the second end, The light-shielding layer disposed at the first end, Equipped with, The display device according to claim 1.

3. The light-shielding layer is disposed on top of the transparent layer. The display device according to claim 2.

4. The light-shielding layer is made of titanium. The display device according to claim 2 or 3.

5. The transmittance of the light-shielding layer to light with a wavelength of 436 nm or light with a wavelength of 405 nm is 10% or less. The display device according to any one of claims 2 to 4.

6. The partition wall surrounds the first display element and the second display element, The light-shielding layer surrounds the first display element. The display device according to any one of claims 2 to 5.

7. The aforementioned transparent layer is A first transparent layer formed of silicon oxide, A second transparent layer formed of a conductive oxide, including, The display device according to any one of claims 2 to 6.

8. The transparent layer has a single-layer structure of silicon oxide. The display device according to any one of claims 2 to 6.

9. The aforementioned lower part is conductive, The first upper electrode is in contact with the first side surface, The second upper electrode is in contact with the second side surface. The display device according to any one of claims 1 to 8.

10. The first display element, the first side surface and the first end are covered by a first sealing layer made of an inorganic material, The second display element, the second side surface and the second end are covered by a second sealing layer made of an inorganic material, Furthermore, The ends of the first sealing layer and the second sealing layer are located above the upper part and are spaced apart from each other. The display device according to any one of claims 1 to 9.

11. A first lower electrode and a second lower electrode are formed. A partition wall is formed comprising a lower part having a first side surface on the first lower electrode side and a second side surface on the second lower electrode side, and an upper part having a light-shielding first end protruding from the first side surface and a light-transmitting second end protruding from the second side surface. A first organic layer including a light-emitting layer, a first upper electrode covering the first organic layer, a first sealing layer made of an inorganic material, and a first resist covering the first sealing layer are formed in order on the first lower electrode, the second lower electrode, and the partition wall. The portion of the first resist that overlaps with the second lower electrode and the second end is exposed. By exposing the first resist to a developer, the exposed portion of the first resist is removed. By removing the portion of the first organic layer, the first upper electrode, and the first sealing layer that is exposed from the first resist by first etching, a first display element including the first lower electrode, the first organic layer, and the first upper electrode is formed. A method for manufacturing a display device.

12. After forming the first display element, a second organic layer including a light-emitting layer, a second upper electrode covering the second organic layer, a second sealing layer made of an inorganic material, and a second resist covering the second sealing layer are formed sequentially on the first display element, the second lower electrode, and the partition wall. The portion of the second resist that overlaps with the first display element and the first end is exposed. By exposing the second resist to a developer, the exposed portion of the second resist is removed. By removing the portion of the second organic layer, the second upper electrode, and the second sealing layer that is exposed from the second resist by second etching, a second display element is formed, including the second lower electrode, the second organic layer, and the second upper electrode. A method for manufacturing a display device according to claim 11.

13. A portion of the second resist is located below the first end, The light that exposes the second resist is blocked by the first end. When the second etching is performed after the second resist has been exposed to the developer, the portion of the second resist located below the first end remains. A method for manufacturing a display device according to claim 12.

14. The aforementioned upper part is, A transparent layer extending from the first end to the second end, The light-shielding layer disposed at the first end, Equipped with, A method for manufacturing a display device according to claim 12 or 13.

15. The transmittance of the light-shielding layer to the light used for exposure of the second resist is 10% or less. A method for manufacturing a display device according to claim 14.

16. For exposure of the second resist, light with a wavelength of 436 nm or light with a wavelength of 405 nm is used. A method for manufacturing a display device according to claim 15.

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