Array substrate and display device

Abstract

To realize an efficient layout for a circuit that is disposed in a peripheral region of an array substrate.SOLUTION: An array substrate includes: a plurality of signal lines disposed in an active region; and a switch circuit connected to the signal lines. The signal lines include first and second signal lines. The switch circuit includes: a circuit unit including first and second transistors; a first input line connected to the first and second transistors; a first selection line that supplies a first selection signal that turns on the first transistor; a second selection line that supplies a second selection signal that turns on the second transistor; a first output line that connects the first transistor and the first signal to each other and intersects with the first selection line; and a second output line that connects the second transistor and the second signal to each other and intersects with the first selection line. A first intersection part of the first output line that intersects with the first selection line and a second intersection part of the second output line that intersects with the first selection line are formed in different layers.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to an array substrate and a display device.

Background Art

[0002] Generally, a display device includes pixel electrodes arranged in each of a plurality of pixels, pixel transistors connected to the pixel electrodes, and signal lines for supplying video signals to pixel circuits. Also, a switch circuit for selectively supplying video signals to the signal lines is arranged in a peripheral area around the display area.

[0003] In recent years, pixel high definition has been advancing. As a result, there is a demand for improving the efficiency of the layout of circuits arranged in the peripheral area. [[ID=!17]]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One object of the present disclosure is to provide an array substrate and a display device capable of realizing an efficient layout of circuits arranged in a peripheral area.

Means for Solving the Problems

[0006] An array substrate according to one embodiment includes a plurality of signal lines arranged in an active area, and a switch circuit arranged in a peripheral area around the active area and connected to the plurality of signal lines. The plurality of signal lines include a first signal line and a second signal line. The switch circuit is The plurality of signal lines are aligned in the direction of extension.The device includes a circuit unit comprising a first transistor and a second transistor; a first input line connected to the first transistor and the second transistor; a first selection line positioned between the circuit unit and the active region and supplying a first selection signal to turn on the first transistor; a second selection line supplying a second selection signal to turn on the second transistor; a first output line connecting the first transistor and the first signal line and intersecting the first selection line; and a second output line connecting the second transistor and the second signal line and intersecting the first selection line. Furthermore, a first intersection portion of the first output line that intersects the first selection line and a second intersection portion of the second output line that intersects the first selection line are formed on different layers.

[0007] A display device according to one embodiment includes the array substrate. Furthermore, the active region includes a plurality of pixel transistors connected to the plurality of signal lines and a plurality of pixel electrodes connected to each of the plurality of pixel transistors. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of an equivalent circuit that can be applied to a subpixel. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device in the active area. [Figure 4] Figure 4 is a schematic plan view of the array substrate in the active region. [Figure 5] Figure 5 shows an example of the configuration of a circuit unit included in a switch circuit. [Figure 6] Figure 6 is a schematic plan view showing an example of a configuration that can be applied to the circuit unit. [Figure 7] Figure 7 is a plan view showing the elements related to the first and second transistors extracted from the circuit unit shown in Figure 6. [Figure 8]Figure 8 is a plan view showing the elements related to the third and fourth transistors extracted from the circuit unit shown in Figure 6. [Figure 9] Figure 9 is a schematic cross-sectional view showing the connection structure between the first transistor and the first signal line. [Figure 10] Figure 10 is a schematic cross-sectional view showing the connection structure between the second transistor and the second signal line. [Figure 11] Figure 11 is a schematic cross-sectional view showing the connection structure between the third transistor and the third signal line. [Figure 12] Figure 12 is a schematic plan view, enlarged, of the area around the first selection line in Figure 6. [Modes for carrying out the invention]

[0009] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, while the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of this invention. In addition, in this specification and each drawing, components that perform the same or similar functions as those described above with respect to previously shown drawings are denoted by the same reference numerals, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis is called the first direction X, the direction along the Y axis is called the second direction Y, and the direction along the Z axis is called the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] In this embodiment, as an example of a display device and an array substrate, a liquid crystal display device and an array substrate included in the liquid crystal display device are disclosed. However, the configuration disclosed in this embodiment, particularly the circuit configuration for supplying signals to the signal lines in the active region, is applicable to other types of display devices and electronic devices other than display devices. Examples of electronic devices other than display devices include, for example, sensors in which a plurality of detection elements are arranged in the active region.

[0012] FIG. 1 is a diagram showing a configuration example of a liquid crystal display device DSP (hereinafter referred to as a display device DSP) according to this embodiment. The display device DSP includes an array substrate AR. In the example of FIG. 1, the array substrate AR is rectangular, but it is not limited to this example.

[0013] The array substrate AR has an active region AA (display region) including a plurality of pixels PX and a peripheral region SA around the active region AA. For example, the pixel PX includes a red sub-pixel SPR, a green sub-pixel SPG, and a blue sub-pixel SPB. It is not limited to this example, and the pixel PX may include sub-pixels of other colors such as white.

[0014] The array substrate AR further includes a plurality of scanning lines G and a plurality of signal lines S. The plurality of scanning lines G extend in the first direction X in the active region AA and are arranged in the second direction Y. The plurality of signal lines S extend in the second direction Y in the active region AA and are arranged in the first direction X.

[0015] A terminal portion T is provided in the peripheral region SA. A flexible circuit board F is connected to the terminal portion T via, for example, a conductive adhesive. The voltage and signals necessary for driving the array substrate AR are input via the flexible circuit board F and the terminal portion T.

[0016] The array substrate AR includes a driving element DD, a scanning line driving circuit GD, a signal line driving circuit SD, a switch circuit ASW (selector), and a common voltage driving circuit CD. All of these elements are arranged in the peripheral region SA. However, for example, the driving element DD and the common voltage driving circuit CD may be mounted on the flexible circuit board F.

[0017] The driving element DD is, for example, an IC, and controls the scanning line driving circuit GD, the signal line driving circuit SD, the switch circuit ASW, and the common voltage driving circuit CD based on control signals such as a clock signal and a timing signal input to the terminal portion T.

[0018] The common voltage driving circuit CD supplies a common voltage to the common voltage line CML. The common voltage line CML is arranged, for example, in the peripheral region SA and surrounds the active region AA. The scanning line driving circuit GD supplies a scanning signal to each scanning line G in a time-division manner.

[0019] The driving element DD and the switch circuit ASW are connected by a first selection line SLT1 and a second selection line SLT2. The driving element DD supplies a selection signal to the first selection line SLT1 and the second selection line SLT2 in a time-division manner.

[0020] The switch circuit ASW includes a plurality of circuit units CU arranged in the first direction X. In the present embodiment, each circuit unit CU is connected to the signal line driving circuit SD via a first input line Sin1 and a second input line Sin2. Each circuit unit CU is also connected to four signal lines S.

[0021] The signal line driving circuit SD outputs video signals to the input lines Sin1, Sin2. Each circuit unit CU switches the signal lines S, which are the output destinations of these video signals, according to the selection signals supplied to the selection lines SLT1, SLT2.

[0022] Figure 2 shows an example of an equivalent circuit that can be applied to a sub-pixel SP (SPR, SPG, SPB). The sub-pixel SP comprises a pixel transistor PTR and a pixel electrode PE. The source electrode of the pixel transistor PTR is connected to the signal line S, the gate electrode is connected to the scan line G, and the drain electrode is connected to the pixel electrode PE. The common voltage of the common voltage line CML is supplied to the common electrode CE. A retaining capacitance CS is formed between the pixel electrode PE and the common electrode CE.

[0023] When a scanning signal is supplied to the scanning line G, a voltage corresponding to the video signal on the signal line S is applied to the pixel electrode PE. This creates a potential difference between the common electrode CE and the pixel electrode PE. The electric field corresponding to this potential difference acts on the liquid crystal layer LC of the display device DSP.

[0024] Figure 3 is a schematic cross-sectional view of the display device DSP in the active region AA. The display device DSP includes the array substrate AR and liquid crystal layer LC described above, as well as a counter substrate CT. The counter substrate CT faces the array substrate AR. The liquid crystal layer LC is sealed between the array substrate AR and the counter substrate CT.

[0025] In the example shown in Figure 3, the array substrate AR comprises the aforementioned signal lines S, pixel transistors PTR, pixel electrodes PE, and common electrodes CE. Furthermore, the array substrate AR comprises an insulating substrate 10, insulating layers 11-18, an alignment film 19, and a light-shielding layer LS.

[0026] A pixel transistor (PTR) includes a semiconductor layer SC, gate electrodes GEa and GEb, a source electrode SE, and a drain electrode DE. The gate electrodes GEa and GEb are, for example, part of a scan line G. The source electrode SE is, for example, part of a signal line S.

[0027] For example, a transparent glass substrate or a resin substrate can be used as the insulating substrate 10. The insulating layers 11-16, 18 are formed of an inorganic insulating material. The insulating layer 17 is formed of an organic insulating material. The signal line S (source electrode SE), scan line G (gate electrode GEa, GEb), and light shielding layer LS are formed of a conductive metallic material. The alignment film 19 is formed of an alignment film material such as polyimide. The pixel electrode PE, common electrode CE, and drain electrode DE are formed of a transparent conductive oxide such as ITO (Indium Tin Oxide).

[0028] The insulating layer 11 covers the insulating substrate 10. The insulating layer 12 covers the insulating layer 11. The gate electrode GEa is located on the insulating layer 12. The insulating layer 13 covers the gate electrode GEa and the insulating layer 12. The semiconductor layer SC is located on the insulating layer 13. The insulating layer 14 covers the semiconductor layer SC and the insulating layer 13. The gate electrode GEb is located on the insulating layer 14. Both gate electrode GEa and GEb face the semiconductor layer SC.

[0029] The insulating layer 15 covers the gate electrode GEb and the insulating layer 14. The signal line S and the source electrode SE are located on the insulating layer 15. The source electrode SE is in contact with the semiconductor layer SC through contact holes that penetrate the insulating layers 14 and 15. The drain electrode DE is located on the insulating layer 16. The drain electrode DE is in contact with the semiconductor layer SC through contact holes that penetrate the insulating layers 14 to 16.

[0030] The insulating layer 17 covers the drain electrode DE and the insulating layer 16. The insulating layer 17, which is made of an organic insulating material, is sufficiently thicker than the other insulating layers 11-16, 18, and flattens the irregularities caused by the pixel transistor PTR.

[0031] The pixel electrode PE is placed on the insulating layer 17. The pixel electrode PE is in contact with the drain electrode DE through a contact hole that penetrates the insulating layer 17. The insulating layer 18 covers the pixel electrode PE and the insulating layer 17. The light-shielding layer LS is placed on the insulating layer 18. The common electrode CE covers the light-shielding layer LS. The alignment film 19 covers the common electrode CE. In the example in Figure 3, the common electrode CE has a slit ST.

[0032] The opposing substrate CT comprises an insulating substrate 20, a color filter layer 21, an overcoat layer 22, and an alignment film 23. For the insulating substrate 20, a transparent glass substrate or a resin substrate can be used. The color filter layer 21 includes a red color filter placed at sub-pixel SPR, a green color filter placed at sub-pixel SPG, and a blue color filter placed at sub-pixel SPB. The overcoat layer 22 is formed of, for example, a transparent resin material and covers the color filter layer 21. The alignment film 23 is formed of an alignment film material such as polyimide and covers the overcoat layer 22. The color filter layer 21 may also be a COA (Color Filter On Array) provided on the array substrate AR. In the case of a COA, the color filter layer 21 can be provided, for example, between the insulating layer 16 and the insulating layer 17.

[0033] In the following explanation, the metal layer between insulating layers 12 and 13 (the layer of the gate electrode GEa) will be called metal layer M1, the metal layer between insulating layers 14 and 15 (the layer of the gate electrode GEb) will be called metal layer M2, the metal layer between insulating layers 15 and 16 (the layer of the signal line S) will be called metal layer M3, and the metal layer above insulating layer 18 (the layer of the light-shielding layer LS) will be called metal layer M4.

[0034] Figure 4 is a schematic plan view of the array substrate AR in the active region AA. In this figure, some of the conductive elements constituting the subpixels SPR, SPG, and SPB are shown, while the pixel transistor PTR is omitted.

[0035] As described above, the scan line G extends in the first direction X, and the signal line S extends in the second direction Y. In the example in Figure 4, both the scan line G and the signal line S are straight, but this is not the only example. For example, the signal line S may extend in the second direction Y while bending.

[0036] The light-shielding layer LS overlaps with the scan line G and the signal line S. As a result, in the example in Figure 4, the light-shielding layer LS is a grid with openings at the sub-pixels SPR, SPG, and SPB. If the signal line S is bent as described above, the light-shielding layer LS may also be bent in a similar manner.

[0037] The light-shielding layer LS has a lower reflectivity than the scan line G and signal line S. This suppresses light reflection from the scan line G and signal line S. Furthermore, the light-shielding layer LS is connected to the common voltage line CML mentioned above. As a result, the light-shielding layer LS also serves as wiring to supply a common voltage to the common electrode CE.

[0038] The common electrode CE has a slit ST in each of the sub-pixels SPR, SPG, and SPB. These slits ST overlap with the pixel electrodes PE of the sub-pixels SPR, SPG, and SPB, respectively. The electric field formed between the pixel electrode PE and the common electrode CE acts on the liquid crystal layer LC through the slits ST.

[0039] In the example shown in Figure 4, the slit ST extends in a direction intersecting the first direction X and the second direction Y. The shape of the slit ST is not limited to this, and it may extend parallel to the second direction Y. Furthermore, multiple slit STs may be formed for each of the subpixels SPR, SPG, and SPB.

[0040] Next, we will explain the configuration of the ASW switch circuit. Figure 5 shows an example of the configuration of the circuit unit CU included in the switch circuit ASW. In this figure, the parts composed of metal layers M1 to M4 are represented by different types of line segments as shown in the legend within the rectangular frame. The active region AA is located at the top of the figure. The coordinate systems of the first direction X and the second direction Y are included to show the approximate positional relationship of each element. Each wire is shown as a line segment extending in the first direction X or the second direction Y for the sake of simplification of the illustration, but these line segments do not necessarily define the precise extension direction of each wire.

[0041] The first selection line SLT1, the second selection line SLT2, and the common voltage line CML, as shown in Figure 1, extend in the first direction X. The common voltage line CML is located between the first selection line SLT1 and the active region AA in the second direction Y. The first selection line SLT1 is located between the second selection line SLT2 and the common voltage line CML in the second direction Y.

[0042] The circuit unit CU includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4. These transistors TR1 to TR4 are arranged in the second direction Y (the direction in which the signal line S extends) between the first selection line SLT1 and the second selection line SLT2. More specifically, they are arranged in the order of first transistor TR1, third transistor TR3, second transistor TR2, and fourth transistor TR4, from the first selection line SLT1 side toward the second selection line SLT2 side.

[0043] The first selection wire SLT1 is connected to the gate electrode GE1 of the first transistor TR1 and the gate electrode GE3 of the third transistor TR3. The second selection wire SLT2 is connected to the gate electrode GE2 of the second transistor TR2 and the gate electrode GE4 of the fourth transistor TR4.

[0044] The first input line Sin1 and the second input line Sin2, shown at the bottom of the figure, are connected to the signal line drive circuit SD, as also shown in Figure 1. The first input line Sin1 is connected to the source electrode SE1 of the first transistor TR1 and the source electrode SE2 of the second transistor TR2. The second input line Sin2 is connected to the source electrode SE3 of the third transistor TR3 and the source electrode SE4 of the fourth transistor TR4.

[0045] The drain electrode DE1 of the first transistor TR1 is connected to the first output line Sout1. The drain electrode DE2 of the second transistor TR2 is connected to the second output line Sout2. The drain electrode DE3 of the third transistor TR3 is connected to the third output line Sout3. The drain electrode DE4 of the fourth transistor TR4 is connected to the fourth output line Sout4. These output lines Sout1 to Sout4 intersect with the first selection line SLT1 and the common voltage line CML.

[0046] The multiple signal lines S shown in Figure 1 include a first signal line S1, a second signal line S2, a third signal line S3, and a fourth signal line S4. The first output line Sout1 is connected to the first signal line S1. The second output line Sout2 is connected to the second signal line S2. The third output line Sout3 is connected to the third signal line S3. The fourth output line Sout4 is connected to the fourth signal line S4.

[0047] The selection lines SLT1 and SLT2 are alternately supplied with selection signals. When the first selection signal is supplied to the first selection line SLT1, transistors TR1 and TR3 are turned on. At this time, the video signal from the first input line Sin1 is output to the first signal line S1 via the first output line Sout1. Also, the video signal from the second input line Sin2 is output to the third signal line S3 via the third output line Sout3.

[0048] On the other hand, when the second selection signal is supplied to the second selection line SLT2, transistors TR2 and TR4 are turned on. At this time, the video signal from the first input line Sin1 is output to the second signal line S2 via the second output line Sout2. Also, the video signal from the second input line Sin2 is output to the fourth signal line S4 via the fourth output line Sout4.

[0049] Figure 6 is a schematic plan view showing an example of a configuration that can be applied to a circuit unit CU. Here, three circuit units CU adjacent to each other in the first direction X are shown. In this figure, the parts composed of metal layers M1 to M4 are represented by different types of diagonal lines as shown in the legend within the rectangular frame.

[0050] Each circuit unit CU has a similar configuration. That is, in the switch circuit ASW, multiple first transistors TR1 are arranged in the first direction X, multiple second transistors TR2 are arranged in the first direction X, multiple third transistors TR3 are arranged in the first direction X, and multiple fourth transistors TR4 are arranged in the first direction X.

[0051] Figure 7 is a plan view showing elements related to the first transistor TR1 and the second transistor TR2 extracted from the circuit unit CU shown in Figure 6. The selection lines SLT1 and SLT2 have, for example, a laminated structure of metal layers M2 and M3 (see Figure 9). The first input line Sin1 is formed, for example, from metal layer M3 and connected to relay line RL1 at contact portion C1. The first input line Sin1 may also be formed from metal layer M2.

[0052] The relay line RL1 is connected to the source line SL1 at the contact section C2. The relay line RL1 is formed of a metal layer M1, and the source line SL1 is formed of a metal layer M2. The relay line RL1 intersects with the second select line SLT2 between the contact sections C1 and C2.

[0053] The first transistor TR1 comprises a semiconductor layer SC1. The second transistor TR2 comprises a semiconductor layer SC2. The semiconductor layers SC1 and SC2 are aligned in the second direction Y between the selection lines SLT1 and SLT2.

[0054] Source wire SL1 overlaps with semiconductor layers SC1 and SC2. The portion of source wire SL1 that overlaps with semiconductor layer SC1 corresponds to source electrode SE1. The portion of source wire SL1 that overlaps with semiconductor layer SC2 corresponds to source electrode SE2. Source electrodes SE1 and SE2 are in contact with semiconductor layers SC1 and SC2, respectively.

[0055] Between the selection lines SLT1 and SLT2, gate lines GL1 and GL2, formed from metal layer M1, are positioned. Gate line GL1 is connected to the first selection line SLT1 at contact C3 and intersects with semiconductor layer SC1. The portion of gate line GL1 that overlaps with semiconductor layer SC1 corresponds to the gate electrode GE1. Gate line GL2 is connected to the second selection line SLT2 at contact C4 and intersects with semiconductor layer SC2. The portion of gate line GL2 that overlaps with semiconductor layer SC2 corresponds to the gate electrode GE2.

[0056] The drain electrode DE1 is formed of a metal layer M2 and is in contact with the semiconductor layer SC1. The first output line Sout1 is formed of a metal layer M1 and intersects with the first select line SLT1. The drain electrode DE1 and the first output line Sout1 are connected at the contact portion C5.

[0057] The drain electrode DE2 is formed of a metal layer M2 and is in contact with the semiconductor layer SC2. The second output line Sout2 has a first portion P21 formed of a metal layer M4 and a second portion P22 formed of a metal layer M1. The drain electrode DE2 and the first portion P21 are connected at a contact portion C6. The first portion P21 and the second portion P22 are connected at a contact portion C7. The first portion P21 intersects with the first selection line SLT1.

[0058] Figure 8 is a plan view showing the elements related to the third transistor TR3 and the fourth transistor TR4 extracted from the circuit unit CU shown in Figure 6. The second input line Sin2 is formed, for example, by a metal layer M3 and connected to the relay line RL2 at the contact portion C8. Alternatively, the second input line Sin2 may be formed by a metal layer M2.

[0059] The relay line RL2 is connected to the source line SL2 at contact point C9. The relay line RL2 is formed of a metal layer M1, and the source line SL2 is formed of a metal layer M2. The relay line RL2 intersects with the second select line SLT2 between contact points C8 and C9.

[0060] The third transistor TR3 has a semiconductor layer SC3. The fourth transistor TR4 has a semiconductor layer SC4. The semiconductor layers SC3 and SC4 are aligned in the second direction Y between the selection lines SLT1 and SLT2.

[0061] Source wire SL2 overlaps with semiconductor layers SC3 and SC4. The portion of source wire SL2 that overlaps with semiconductor layer SC3 corresponds to source electrode SE3. The portion of source wire SL2 that overlaps with semiconductor layer SC4 corresponds to source electrode SE4. Source electrodes SE3 and SE4 are in contact with semiconductor layers SC3 and SC4, respectively.

[0062] Gate line GL1 intersects semiconductor layer SC3. The portion of gate line GL1 that overlaps with semiconductor layer SC3 corresponds to gate electrode GE3. Gate line GL2 intersects semiconductor layer SC4. The portion of gate line GL2 that overlaps with semiconductor layer SC4 corresponds to gate electrode GE4.

[0063] The drain electrode DE3 is formed of a metal layer M2 and is in contact with the semiconductor layer SC3. The third output line Sout3 has a first portion P31 formed of a metal layer M3 and a second portion P32 formed of a metal layer M1. The drain electrode DE3 and the first portion P31 are connected at a contact portion C10. The first portion P31 and the second portion P32 are connected at a contact portion C11. The second portion P32 intersects with the first selection line SLT1.

[0064] The drain electrode DE4 is formed of a metal layer M2 and is in contact with the semiconductor layer SC4. The fourth output line Sout4 has a first portion P41 formed of a metal layer M4, a second portion P42 formed of a metal layer M2, and a third portion P43 formed of a metal layer M1. The drain electrode DE4 and the first portion P41 are connected at a contact portion C12. The first portion P41 and the second portion P42 are connected at a contact portion C13. The second portion P42 and the third portion P43 are connected at a contact portion C14. The first portion P41 intersects with the first select line SLT1.

[0065] Figure 9 is a schematic cross-sectional view showing the connection structure between the first transistor TR1 and the first signal line S1. Although the fourth transistor TR4 is omitted in Figure 9, its structure is the same as that of transistors TR1 to TR3.

[0066] In the example shown in Figure 9, the first selected line SLT1 has a first layer L11 and a second layer L12 that overlap in the third direction Z. The first layer L11 is located on an insulating layer 14 and covered by an insulating layer 15. The second layer L12 is located on an insulating layer 15 and covered by an insulating layer 16. The second layer L12 is connected to the first layer L11 through a contact hole that penetrates the insulating layer 15.

[0067] Furthermore, the common voltage line CML has a first layer L21 and a second layer L22 that overlap in the third direction Z. The first layer L21 is located on the insulating layer 14 and covered by the insulating layer 15. The second layer L22 is located on the insulating layer 15 and covered by the insulating layer 16. The second layer L22 is connected to the first layer L21 through a contact hole that penetrates the insulating layer 15.

[0068] The light-shielding layer LS overlaps with the common voltage line CML in the peripheral region SA. The common voltage line CML and the light-shielding layer LS are connected at the contact portion C20. In the example in Figure 9, the contact portion C20 includes intermediate portions R1 and R2. Intermediate portion R1 is located on the insulating layer 16 and covered by the insulating layer 17. Intermediate portion R2 is located on the insulating layer 17 and covered by the insulating layer 18. Intermediate portion R1 is made of the same conductive oxide as the drain electrode DE. Intermediate portion R2 is made of the same conductive oxide as the pixel electrode PE.

[0069] The semiconductor layers SC1 to SC4 are placed on the insulating layer 11 and covered by the insulating layer 12. For example, the semiconductor layers SC1 to SC4 are made of a different material than the semiconductor layer SC of the pixel transistor TR. In one example, the semiconductor layers SC1 to SC4 are made of low-temperature polysilicon (LTPS), and the semiconductor layer SC is made of an oxide semiconductor.

[0070] The gate electrodes GE1-GE4 are placed on the insulating layer 12 and covered by the insulating layer 13. The source electrodes SE1-SE4 and drain electrodes DE1-DE4 are placed on the insulating layer 14 and covered by the insulating layer 15. The source electrodes SE1-SE4 are in contact with the semiconductor layers SC1-SC4, respectively, through contact holes that penetrate the insulating layers 13 and 14. Similarly, the drain electrodes DE1-DE4 are in contact with the semiconductor layers SC1-SC4, respectively, through contact holes that penetrate the insulating layers 13 and 14.

[0071] The first output line Sout1, connected to the drain electrode DE1 at contact section C5, passes beneath the first selection line SLT1 and the common voltage line CML, and is connected to the first signal line S1 at contact section C21. In the example in Figure 9, contact section C21 includes a relay section R10. The relay section R10 is placed on an insulating layer 14 and covered by an insulating layer 15. That is, the relay section R10 is formed of a metal layer M2.

[0072] Figure 10 is a schematic cross-sectional view showing the connection structure between the second transistor TR2 and the second signal line S2. The second output line Sout2 includes the first part P21 and the second part P22, which are also shown in Figure 7.

[0073] The first portion P21, connected to the drain electrode DE2 at contact portion C6, passes above the first selection line SLT1 and is connected to the second portion P22 at contact portion C7. The first portion P21 is covered by a protective layer PR made of the same conductive oxide as the common electrode CE.

[0074] In the example shown in Figure 10, the contact portion C6 includes intermediate portions R21, R22, and R23. Intermediate portion R21 is placed on the insulating layer 15 and covered by the insulating layer 16. That is, intermediate portion R21 is formed of the metal layer M3. Intermediate portion R22 is placed on the insulating layer 16 and covered by the insulating layer 17. Intermediate portion R22 is formed of the same conductive oxide as the drain electrode DE. Intermediate portion R23 is placed on the insulating layer 17 and covered by the insulating layer 18. Intermediate portion R23 is formed of the same conductive oxide as the pixel electrode PE.

[0075] Furthermore, in the example shown in Figure 10, the contact portion C7 includes intermediate portions R24, R25, and R26. Intermediate portion R24 is placed on the insulating layer 15 and covered by the insulating layer 16. That is, intermediate portion R24 is formed of the metal layer M3. Intermediate portion R25 is placed on the insulating layer 16 and covered by the insulating layer 17. Intermediate portion R25 is formed of the same conductive oxide as the drain electrode DE. Intermediate portion R26 is placed on the insulating layer 17 and covered by the insulating layer 18. Intermediate portion R26 is formed of the same conductive oxide as the pixel electrode PE.

[0076] The second section P22 passes beneath the common voltage line CML and is connected to the second signal line S2 at the contact section C22. In the example in Figure 10, the contact section C22 includes a relay section R27. The relay section R27 is located on the insulating layer 14 and is covered by the insulating layer 15. That is, the relay section R27 is formed of a metal layer M2.

[0077] Figure 11 is a schematic cross-sectional view showing the connection structure between the third transistor TR3 and the third signal line S3. The third output line Sout3 includes the first part P31 and the second part P32, which are also shown in Figure 8.

[0078] The first portion P31, connected to the drain electrode DE3 at contact portion C10, passes over the first transistor TR1 and is connected to the second portion P32 at contact portion C11. In the example in Figure 11, contact portion C11 includes a relay portion R31. The relay portion R31 is placed on an insulating layer 14 and covered by an insulating layer 15. That is, the relay portion R31 is formed of a metal layer M2.

[0079] The second section P32 passes beneath the first selection line SLT1 and the common voltage line CML and is connected to the third signal line S3 at the contact section C31. In the example in Figure 11, the contact section C31 includes a relay section R32. The relay section R32 is located on the insulating layer 14 and is covered by the insulating layer 15. That is, the relay section R32 is formed of a metal layer M2.

[0080] The connection structure between the fourth transistor TR4 and the fourth signal line S4 is generally the same as the connection structure between the second transistor TR2 and the second signal line S2 shown in Figure 10. That is, the first portion P41 of the fourth output line Sout4 passes above the first selection line SLT1, and the third portion 43, which is connected to the first portion P41 via the second portion P42, passes below the common voltage line CML. The first portion P41, formed of a metal layer M4, is covered with a protective layer PR of conductive oxide.

[0081] The configuration of the display device DSP according to this embodiment, as described above, makes it possible to achieve an efficient layout of the switch circuit ASW. An example of this effect will be explained with reference to Figure 12.

[0082] Figure 12 is a schematic plan view, enlarged, of the area around the first selection line SLT1 in Figure 6. In the following explanation, the portion of the first output line Sout1 that intersects with the first selection line SLT1 will be called the first intersection CR1, the portion of the second output line Sout2 that intersects with the first selection line SLT1 will be called the second intersection CR2, the portion of the third output line Sout3 that intersects with the first selection line SLT1 will be called the third intersection CR3, and the portion of the fourth output line Sout4 that intersects with the first selection line SLT1 will be called the fourth intersection CR4.

[0083] The first intersection portion CR1 is part of the first signal line Sout1 formed of metal layer M1. The second intersection portion CR2 is part of the first portion P21 formed of metal layer M4. The third intersection portion CR3 is part of the second portion P32 formed of metal layer M1. The fourth intersection portion CR4 is part of the first portion P41 formed of metal layer M4. In other words, in this embodiment, two of the intersection portions CR1 to CR4 are formed of metal layer M1, and the remaining two are formed of metal layer M4.

[0084] From another perspective, the first selected line SLT1 is located between the intersections CR1, CR3 and CR2, CR4 in the third direction Z (thickness direction of the array substrate AR). The intersections CR1, CR3 are located below the insulating layer 17 formed of organic insulating material, while the intersections CR2, CR4 are located above the insulating layer 17.

[0085] In the vicinity of the intersections CR1 to CR4, a contact section C3 is provided between the gate line GL1 and the first selection line SLT1. In the example in Figure 12, the first intersection CR3, the fourth intersection CR4, the contact section C3, the first intersection CR1, and the second intersection CR2 are arranged in this order in the first direction X. In the example in Figure 12, the second section 42 intersects with the first signal line Sout1. As a result, the third output line Sout3, the first output line Sout1, the fourth output line Sout4, and the second output line Sout2 are arranged in this order in the first direction X.

[0086] In high-resolution display devices (DSPs), narrowing the pitch of sub-pixels SPR, SPG, and SPB is required. To achieve this narrowing, the width of the switch circuit ASW also needs to be reduced. However, if the intersections CR1 to CR4 are all formed from the same metal layer, the width W of the wiring group consisting of the intersections CR1 to CR4 and the gate wire GL1 cannot be sufficiently reduced due to the need to ensure insulation between the intersections CR1 to CR4 and limitations in the processing capabilities of the manufacturing equipment. This can restrict the width of the circuit unit CU.

[0087] In contrast, in this embodiment, two of the intersection portions CR1 to CR4 are formed from metal layer M1, and the remaining two are formed from metal layer M4. In this case, it is possible to place the intersection portions formed from different layers close together or overlap them. Therefore, the width W can be reduced compared to the case where all intersection portions CR1 to CR4 are formed from the same metal layer. Consequently, the width of the switch circuit ASW can be reduced, making it possible to realize a high-definition display device DSP.

[0088] Furthermore, metal layer M1 is the layer that forms the gate electrodes GEa, GE1, and GE4 of transistors PTR, TR1, and TR4, and metal layer M4 is the layer that forms the light-shielding layer LS. By using such metal layers M1 and M4 to form the intersections CR1 to CR4, there is no need to add a metal layer for the intersections CR1 to CR4, which suppresses the increase in manufacturing costs of the display device DSP and also contributes to making the display device DSP thinner.

[0089] In the example shown in Figure 12, both the first portions P21 and P41, formed from the metal layer M4, are covered by the protective layer PR. This makes it possible to protect the first portions P21 and P41 from etching during the processing of the common electrode CE.

[0090] The configuration of the display device DSP disclosed in this embodiment can be modified in various ways. For example, it is not necessary for two of the intersection portions CR1 to CR4 to be formed of metal layer M1 and the remaining two to be formed of metal layer M4. As another example, three of the intersection portions CR1 to CR4 may be formed of one of metal layers M1 and M4, and the remaining one may be formed of the other of metal layers M1 and M4. Also, at least one of the intersection portions CR1 to CR4 may be formed of a metal layer other than metal layers M1 and M4.

[0091] In this embodiment, a configuration using NMOS transistors as transistors TR1 to TR4 is illustrated. However, CMOS transistors may also be used as transistors TR1 to TR4. In this case, transistors TR1 to TR4 include two transistors, an N-type and a P-type.

[0092] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0093] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0094] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0095] DSP...Display device, AA...Active area, SA...Peripheral area, G...Scan line, S...Signal line, ASW...Switch circuit, CU...Circuit unit, SLT1, SLT2...Selection line, CML...Common voltage line, TR1~TR4...Transistor, Sin1, Sin2...Input line, Sout1~Sout4...Output line.

Claims

1. Multiple signal lines arranged in the active region, A switch circuit is arranged in the peripheral region surrounding the active region and connected to the plurality of signal lines, Equipped with, The aforementioned plurality of signal lines include a first signal line and a second signal line, The aforementioned switch circuit is A circuit unit including a first transistor and a second transistor arranged in the direction of extension of the plurality of signal lines, A first input line connected to the first transistor and the second transistor, A first selection line is provided between the circuit unit and the active region, and supplies a first selection signal to turn on the first transistor. A second selection line that supplies a second selection signal to turn on the second transistor, The first transistor and the first signal line are connected, and the first output line intersects with the first selection line, The second transistor and the second signal line are connected, and the second output line intersects with the first selection line, Includes, The first intersection portion of the first output line that intersects the first selection line and the second intersection portion of the second output line that intersects the first selection line are formed in different layers. Array substrate.

2. The first selection line is located between the first intersection and the second intersection in the thickness direction of the array substrate. The array substrate according to claim 1.

3. The first transistor is, The first semiconductor layer, A first gate electrode connected to the first selection line and intersecting the first semiconductor layer, A first source electrode connecting the first input line and the first semiconductor layer, A first drain electrode connecting the first semiconductor layer and the first output line, Includes, The first intersection portion is formed in the same layer as the first gate electrode. The array substrate according to claim 1.

4. The first selection line includes a first layer formed in the same layer as the plurality of signal lines, and a second layer formed in the same layer as the first drain electrode. The array substrate according to claim 3.

5. The device further comprises an insulating layer made of an organic material, located above the first transistor, the second transistor, and the first selection line, The second intersection portion is formed above the insulating layer, The array substrate according to claim 1.

6. The active region is further provided with a conductive light-shielding layer that overlaps with the plurality of signal lines, The second intersection portion is formed in the same layer as the light-shielding layer. The array substrate according to claim 5.

7. The second intersection is covered with a protective layer formed of a conductive oxide. The array substrate according to claim 6.

8. The aforementioned plurality of signal lines further include a third signal line and a fourth signal line, The aforementioned circuit unit is A third transistor to which the first selection signal is supplied from the first selection line, A fourth transistor to which the second selection signal is supplied from the second selection line, It further includes, The aforementioned switch circuit is The second input line connected to the third and fourth transistors, The third transistor and the third signal line are connected, and the third output line intersects with the first selection line, The fourth transistor and the fourth signal line are connected, and the fourth output line intersects with the first selection line, It further includes, The third intersection portion of the third output line that intersects the first selection line and the fourth intersection portion of the fourth output line that intersects the first selection line are formed in different layers. The array substrate according to claim 1.

9. The first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the direction of extension of the plurality of signal lines. The array substrate according to claim 8.

10. The array substrate comprises the one described in any one of claims 1 to 9, The active region is Multiple pixel transistors connected to the aforementioned multiple signal lines, Multiple pixel electrodes connected to each of the aforementioned multiple pixel transistors, A display device, including a display device.

11. A counter substrate facing the array substrate, A liquid crystal layer disposed between the array substrate and the opposing substrate, Furthermore, The display device according to claim 10.

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