Degradation detection device, power conversion device, and degradation detection method

Abstract

To detect deterioration of a semiconductor device with accuracy.SOLUTION: A deterioration detection device comprises: a semiconductor device that has a semiconductor chip having first and second main electrodes, a first terminal electrically connected with the first main electrode, a wire bonded with the second main electrode, and a second terminal electrically connected with the second main electrode via the wire; and a monitoring unit that monitors an input value that changes depending on a detection value of an ON voltage that is an inter-terminal voltage between the first and second terminals in an ON state, and when a filter output value obtained by applying a low-pass filter to the input value becomes larger than a predetermined determination threshold, outputs a predetermined signal.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a deterioration detection device, a power conversion device, and a deterioration detection method.

Background Art

[0002] Conventionally, there is known a technique of measuring the voltage Vce between the collector and emitter when a constant collector current flows through a semiconductor element, and determining that the life of the semiconductor element is approaching when the difference between the measured value of the voltage Vce and the initial value exceeds a determination value (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the fluctuation range of the voltage Vce described above changes greatly depending on the fluctuation of the current flowing through the semiconductor device. Therefore, even when monitoring the voltage Vce, it may not be possible to accurately detect the deterioration of the semiconductor device.

[0005] The present disclosure provides a deterioration detection device, a power conversion device, and a deterioration detection method capable of accurately detecting the deterioration of a semiconductor device.

Means for Solving the Problems

[0006] In one aspect of the present disclosure, a semiconductor chip having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire joined to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire; A degradation detection device is provided, comprising: a monitoring unit that monitors an input value that changes according to a detected value of the on-voltage, which is the voltage between the first terminal and the second terminal when they are both on, and outputs a predetermined signal when the filtered output value obtained by applying a low-pass filter to the input value exceeds a predetermined threshold.

[0007] In another aspect of this disclosure, Multiple semiconductor devices for power conversion, The system comprises a control unit that controls the switching of the plurality of semiconductor devices, Each of the aforementioned plurality of semiconductor devices is: A semiconductor chip having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire bonded to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire. The power converter is provided, which includes a control unit that monitors an input value that changes according to a detected on-voltage, which is the voltage between the first and second terminals when they are both on, and outputs a predetermined signal when the filtered output value obtained by applying a low-pass filter to the input value exceeds a predetermined threshold.

[0008] In another aspect of this disclosure, A method for detecting degradation of a semiconductor device comprising a semiconductor chip having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire bonded to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire, A degradation detection method is provided, which monitors an input value that changes according to a detected value of the on-voltage, which is the voltage between the first and second terminals when they are both on, and outputs a predetermined signal when the filtered output value obtained by applying a low-pass filter to the input value exceeds a predetermined threshold. [Effects of the Invention]

[0009] According to this disclosure, the degradation of semiconductor devices can be detected with high accuracy. [Brief explanation of the drawing]

[0010] [Figure 1] It is a cross-sectional view of a part of a power semiconductor module when a wire joint is deteriorated. [Figure 2] It is a cross-sectional view of a part of a power semiconductor module when a bonding material under a semiconductor chip is deteriorated. [Figure 3] It is a diagram showing examples of semiconductor chips (IGBT chip and diode chip). [Figure 4] It is a diagram illustrating the relationship between the voltage Vce_on between main terminals when the power semiconductor module is in a conducting state and the operating time of the power semiconductor module. [Figure 5] It is a configuration diagram showing an example of a deterioration detection device according to the present embodiment. [Figure 6] It is a cross-sectional view of a part of a power semiconductor module according to the present embodiment. [Figure 7] It is a configuration diagram showing a first example of a monitoring unit. [Figure 8] It is a diagram showing the overall configuration of a power conversion device according to the present embodiment. [Figure 9] It is a diagram illustrating waveforms of respective parts accompanying the detection operation of the voltage Vce_1 in the on state. [Figure 10] It is a timing chart for explaining a method for detecting deterioration of a semiconductor device based on a filter output value. [Figure 11] It is a configuration diagram showing a second example of a monitoring unit. [Figure 12] It is a diagram showing details of the configuration of the second example of the monitoring unit. [Figure 13] It is a configuration diagram showing a third example of a monitoring unit. [Figure 14] It is a diagram showing details of the configuration of the third example of the monitoring unit.

MODE FOR CARRYING OUT THE INVENTION

[0011] Hereinafter, embodiments will be described.

[0012] In recent years, power conversion devices have been expanded to applications that require high reliability (such as power systems, or mobile bodies such as trains or automobiles), and along with this, the demand for high reliability of power conversion devices has been increasing. In response to this demand, expectations for the realization of predictive maintenance that predicts failures and takes countermeasures in advance have been increasing.

[0013] One of the main failure factors of a power conversion device is the power semiconductor module. The main failure of the power semiconductor module occurs when the thermal stress stress repeatedly generated by current conduction or switching operation deteriorates the bonding wire and solder. As the deterioration of the bonding wire and solder progresses, the conduction resistance between the main terminals when the power semiconductor module is in the on state (conducting state) increases, so the voltage Von between the main terminals when the power semiconductor module is in the conducting state rises. Therefore, by detecting the increase in the voltage Von, the deterioration of the power semiconductor module can be detected.

[0014] FIG. 1 is a cross-sectional view of a part of a power semiconductor module when the wire joint is deteriorated. FIG. 2 is a cross-sectional view of a part of a power semiconductor module when the bonding material under the semiconductor chip is deteriorated. In FIGS. 1 and 2, the power semiconductor module is a semiconductor device including a semiconductor chip 11, a wire 16 for connecting the semiconductor chip 11 to the outside, and a bonding material 8 for bonding the semiconductor chip 11 to a substrate (not shown).

[0015] The wire 16 is a conductor whose one end is bonded to the surface 12 of the semiconductor chip 11. The wire 16 is, for example, a bonding wire such as an aluminum wire. The bonding material 8 is a conductor that contacts the back surface 13 of the semiconductor chip 11. The bonding material 8 is typically solder, but other bonding materials such as an adhesive may also be used. The thermal stress generated by the repeated conduction / blocking operation of the semiconductor chip 11 deteriorates the joint portion of the wire 16 with the semiconductor chip 11 and the bonding material 8 such as solder.

[0016] As the wire 16 deteriorates, for example, cracks 9 may form at the joint between the wire 16 and the surface 12, increasing the resistance of the joint. On the other hand, as the bonding material 8 deteriorates, for example, cracks 9 may form in the bonding material 8, increasing the resistance of the bonding material 8. Therefore, as the wire 16 and bonding material 8 deteriorate, the voltage Von between the main terminals in the conduction state of the power semiconductor module (see Figure 3; if the power semiconductor module is an IGBT, the voltage Vce_on between the collector and emitter in the conduction state) increases (see Figure 4). By monitoring this increase in voltage Von (Vce_on), it is possible to detect signs of failure in the power semiconductor module.

[0017] However, the fluctuation range of the voltage Von(Vce_on) between the main terminals of a power semiconductor module in a conductive state changes significantly depending on the fluctuation of the current flowing through the power semiconductor module. Therefore, even if the voltage Von(Vce_on) is monitored, it may not be possible to accurately detect the degradation of the power semiconductor module.

[0018] The degradation detection device and power converter according to this embodiment have a configuration that accurately detects the degradation of a semiconductor device. The configuration of the degradation detection device and power converter according to this embodiment, and the degradation detection method performed by the degradation detection device or power converter according to this embodiment will be described below.

[0019] Figure 5 is a configuration diagram showing an example of a degradation detection device according to this embodiment. The degradation detection device 200 shown in Figure 5 is a device for detecting the degradation of a power semiconductor module 100. The degradation detection device 200 includes a power semiconductor module 100 and a monitoring unit 40.

[0020] The power semiconductor module 100 is an example of a semiconductor device. Figure 5 shows the power semiconductor module 100 in a plan view. The power semiconductor module 100 comprises an insulating substrate 1, a semiconductor chip 11, a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA, and wires 16, 17, and 18.

[0021] The insulating substrate 1 is a substrate on which the semiconductor chip 11 is mounted, and can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Blazing) substrate. The insulating substrate 1 is fixed to a base substrate (not shown) formed on the bottom surface of the housing of the power semiconductor module 100, for example, via a bonding material (not shown) such as solder.

[0022] The insulating substrate 1 includes conductive layers 2 to 5 formed on its surface. The conductive layers 2 to 5 are made of conductive metals such as copper and aluminum and are provided on the upper surface of the insulating layer of the insulating substrate 1. The conductive layers 2 to 5 may be conductive plates or conductive foils.

[0023] Conductor layer 2 is a rectangular planar conductor located on the back side of the semiconductor chip 11 in a plan view of the semiconductor chip 11. Conductor layer 3 is a rectangular planar conductor located in the region in the first direction (downward in the drawing) relative to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and is located away from conductor layer 2 in the first direction. Conductor layers 4 and 5 are rectangular planar conductors located in the region in the second direction (opposite to the first direction; upward in the drawing) relative to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and are located away from conductor layer 2 in the second direction. Note that the size, shape, and arrangement of conductor layers 2 to 5 are not limited to the illustrated form.

[0024] The semiconductor chip 11 is a semiconductor element incorporated into the power semiconductor module 100, and is, for example, a semiconductor switching element having electrodes on both its front and back surfaces. The semiconductor chip 11 may be either a Si semiconductor element or a SiC semiconductor element. Figure 5 illustrates the case where the semiconductor chip 11 is an insulated gate bipolar transistor (IGBT) chip.

[0025] Figure 6 is a cross-sectional view of a part of the power semiconductor module according to this embodiment. The semiconductor chip 11 has a surface surface 12 on which an emitter electrode 11e and a gate electrode 11g (see Figure 5) are arranged, and a back surface surface 13 on which a collector electrode 11c is arranged. The collector electrode 11c is an example of a first main electrode of the semiconductor chip 11, and in this example, it is formed on the back surface surface 13. The emitter electrode 11e is an example of a second main electrode of the semiconductor chip 11, and is formed on the surface surface 12. The gate electrode 11g is an example of a control electrode of the semiconductor chip 11, and is formed on the surface surface 12. The semiconductor chip 11 is fixed on the insulating substrate 1 (see Figure 5) on the back surface surface 13 by joining the collector electrode 11c to the conductor layer 2 with a bonding material 8 such as solder.

[0026] In Figure 5, the collector terminal C, emitter terminal E, gate terminal G, and auxiliary emitter terminal EA are external terminals for connecting the power semiconductor module 100 to the outside. Each of these external terminals is formed into a cylindrical or flat shape using a conductive metal such as copper or aluminum.

[0027] The collector terminal C is a main terminal electrically connected to the collector electrode 11c (see Figure 6) of the semiconductor chip 11 via the conductor layer 2 and bonding material 8. The emitter terminal E is a main terminal electrically connected to the emitter electrode 11e of the semiconductor chip 11 via the conductor layer 3 and wire 16. The gate terminal G is a control terminal electrically connected to the gate electrode 11g of the semiconductor chip 11 via the conductor layer 4 and wire 17. The auxiliary emitter terminal EA is an auxiliary terminal electrically connected to the emitter electrode 11e of the semiconductor chip 11 via the conductor layer 5 and wire 18.

[0028] Wires 16-18 are linear members formed with a diameter of 300-500 μm using conductive metals such as copper and aluminum, or conductive alloys such as iron-aluminum alloys. Wire 16 is one or more (four in this example) wires that connect the emitter electrode 11e, which is the surface electrode of the semiconductor chip 11, to the conductor layer 3. Wire 17 is one or more (one in this example) wires that connect the gate electrode 11g, which is the surface electrode of the semiconductor chip 11, to the conductor layer 4. Wire 18 is one or more (one in this example) wires that connect the emitter electrode 11e, which is the surface electrode of the semiconductor chip 11, to the conductor layer 5.

[0029] In Figure 6, the semiconductor chip 11 has its back surface 13 bonded to the surface of the conductor layer 2 by a bonding material 8. One end of the wire 16 is bonded to the emitter electrode 11e on the surface 12 of the semiconductor chip 11. The collector terminal C is an example of a first terminal electrically connected to the back surface 13 of the semiconductor chip 11 via the bonding material 8 and the conductor layer 2. The emitter terminal E is an example of a second terminal electrically connected to the surface 12 of the semiconductor chip 11 via the wire 16.

[0030] When the semiconductor chip 11 becomes conductive between the collector electrode 11c and the emitter electrode 11e, a current Ic flows in the following order: collector terminal C, conductor layer 2, bonding material 8, semiconductor chip 11, wire 16, and emitter terminal E. Repeated switching of the current Ic on and off accelerates the deterioration of the bonding material 8.

[0031] As the bonding material 8 deteriorates, cracks 9 (particularly cracks 9 approximately parallel to the back surface 13 of the semiconductor chip 11) may form in the bonding material 8. This makes it difficult for the current Ic flowing through the bonding material 8 to flow in the longitudinal direction where the conductor layer 2 and the collector electrode 11c face each other. As a result, the electrical resistance between the collector terminal C and the emitter terminal E increases, and the voltage Vce_on between the collector terminal C and the emitter terminal E increases when current Ic is flowing. However, as shown in Figure 4, the detected voltage Von(Vce_on) due to the deterioration of the bonding material 8, etc., is superimposed with harmonics. Therefore, even if the voltage Von(Vce_on) is monitored, it may not be possible to accurately detect the deterioration of the power semiconductor module 100.

[0032] Focusing on this point, the monitoring unit 40 (see Figure 5) monitors the input value which changes according to the detected value of the voltage Vce_on in the ON state between both the collector terminal C and the emitter terminal E, and is equipped with a low-pass filter that applies low-pass filtering to the input value. When the filter output value obtained by applying the low-pass filter to the input value exceeds a predetermined judgment threshold, the monitoring unit 40 outputs a predetermined signal. The output of the predetermined signal indicates the detection of deterioration of the power semiconductor module 100 due to deterioration of the bonding material 8, etc. Thus, since the deterioration detection device 200 is equipped with a monitoring unit 40 that outputs a predetermined signal when the filter output value after low-pass filtering exceeds a predetermined value, it can accurately detect the deterioration of the power semiconductor module 100.

[0033] Furthermore, the monitoring unit 40 can accurately detect deterioration of the power semiconductor module 100 due to deterioration of the bonding material (not shown), such as solder, under the insulating substrate 1, or deterioration of the bonding portion of the wire 16 with the semiconductor chip 11.

[0034] Figure 7 is a configuration diagram showing a first example of the monitoring unit. The monitoring unit 40 shown in Figure 7 has the function of outputting a predetermined signal representing degradation detection using a filtered output value obtained by applying a low-pass filter to an input value that changes according to the detected voltage Vce_on between both the collector terminal C and the emitter terminal E when they are on. The function shown in Figure 8 may be realized solely by hardware resources such as circuits, or it may be realized through the cooperation of hardware resources and software.

[0035] The monitoring unit 40 may be, for example, a control device or a part thereof that includes a processor such as a CPU (Central Processing Unit) and memory. The functions of the monitoring unit 40 are realized by the processor operating according to a program stored in memory. The functions of the monitoring unit 40 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0036] The sample timing generation unit 41 generates a timing for sampling the detected voltage Vce_on online, according to the timing at which the command value of the current i flowing between the collector terminal C and the emitter terminal E passes through a predetermined non-zero current value Ith.

[0037] The detected voltage Vce_on is sampled and held by the sample-and-hold unit 42 at a timing generated by the sample timing generation unit 41. The sample-and-hold value Vce_on_s obtained by the sample-and-hold unit 42 is an example of an input value that changes according to the detected voltage Vce_on. The sample-and-hold value Vce_on_s is subjected to low-pass filtering by the low-pass filter 43.

[0038] The time constant of the low-pass filter 43 should be several seconds or longer, for example, 2 seconds or longer. The time constant of the low-pass filter 43 should be set to such an extent that harmonics of the output frequency of the power semiconductor module 100 (for example, between 10 Hz and 300 Hz) are removed. It should also be set to such an extent that fluctuations in voltage Vce_on due to fluctuations in the command value of current i are removed.

[0039] The fault prediction unit 48 compares the filter output value Vce_on' obtained by the low-pass filtering process of the low-pass filter 43 with a determination threshold and outputs a degradation detection signal according to the relationship between the filter output value Vce_on' and the determination threshold. The determination threshold is set to a predetermined value (for example, a predetermined multiple of the initial value R1_s of the electrical resistance R1 (for example, 1.05 times)). The degradation detection signal is input to the latch circuit 49. The latch circuit 49, triggered by the input of the degradation detection signal, outputs a determination value (an example of a predetermined signal) indicating that there is a fault indication due to degradation of the power semiconductor module 100.

[0040] When the designated notification device receives a judgment value from the latch circuit 49 indicating the presence of a fault precursor, it notifies designated external devices or users that there is a fault precursor due to degradation of the power semiconductor module 100. By notifying them of the fault precursor, maintenance measures can be taken before the power semiconductor module 100 actually fails.

[0041] Figure 8 is a diagram showing an example of the overall configuration of a power converter according to this embodiment. The power converter 101 shown in Figure 8 comprises a main circuit unit 10 that converts DC power supplied from a DC power source 33 into AC power supplied to a load 14, and a control unit 20 that controls the power conversion operation of the main circuit unit 10. Figure 8 illustrates a configuration in which the main circuit unit 10 converts DC power into three-phase AC power.

[0042] The main circuit section 10 comprises a plurality of power semiconductor modules 111 to 116, a plurality of gate drive units 121 to 126, and a current detection unit 30. The power semiconductor modules 111 to 116 are examples of semiconductor devices for power conversion.

[0043] Figure 8 illustrates an IGBT module in a 1-in-1 package, which incorporates an IGBT chip for one arm of an inverter and a diode chip (FWD chip) connected in antiparallel to it, as an example of a power semiconductor module. IGBT is an abbreviation for Insulated Gate Bipolar Transistor, an IGBT chip is an example of a power semiconductor element, and an FWD chip is an example of a rectifier element. However, the package configuration of the power semiconductor module may be other types of package configurations such as 6-in-1, and the power semiconductor elements configured in the power semiconductor module may be other types of power semiconductor elements such as MOSFETs. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Furthermore, the multiple power semiconductor modules 111 to 116 each have the same configuration, and the multiple gate drive units 121 to 126 each have the same configuration. Therefore, for convenience, the upper arm of the u-phase will be used as an example in the following explanation.

[0044] In the example shown in Figure 8, the u-phase upper arm power semiconductor module 111 has an IGBT chip Q1 and an FWD chip D1. The power semiconductor module 111 also has a collector terminal C, an emitter terminal E, a gate terminal G, and an auxiliary emitter terminal EA. The collector terminal C is an example of a first terminal, the emitter terminal E is an example of a second terminal, and the gate terminal G is an example of a control terminal.

[0045] The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 11c, an emitter electrode 11e, and a gate electrode 11g. The collector electrode 11c is an example of a first main electrode, the emitter electrode 11e is an example of a second main electrode, and the gate electrode 11g is an example of a control electrode.

[0046] The FWD chip D1 is an example of a rectifier element (semiconductor element) having an anode electrode 11a and a cathode electrode 11k.

[0047] The collector terminal C is electrically connected to the collector electrode 11c and the cathode electrode 11k. The emitter electrode E is electrically connected to the emitter electrode 11e and the anode electrode 11a. The gate terminal G is electrically connected to the gate electrode 11g. The auxiliary emitter terminal EA is electrically connected to the emitter electrode 11e and the anode electrode 11a.

[0048] The gate drive unit 121 is a drive circuit that includes a pre-driver PD1 and a voltage detection circuit Vce1.

[0049] The pre-driver PD1 is a circuit that drives the gate electrode 11g of the IGBT chip Q1 in response to an on or off switching command S_1 supplied from the control unit 20.

[0050] The voltage detection circuit Vce1 detects the voltage Vce_1 between the collector terminal C and emitter terminal E of the IGBT chip Q1 of the power semiconductor module 111, and transmits the detected value of Vce_1 to the control unit 20.

[0051] The current detection unit 30 is a current sensor that detects the three-phase alternating currents iu, iv, and iw flowing between the power semiconductor modules 111 to 116 and the load 14 and transmits them to the control unit 20.

[0052] The control unit 20 is a control device that includes, for example, a processor such as a CPU (Central Processing Unit) and memory. The functions of the control unit 20 are realized by the processor operating according to a program stored in memory. The functions of the control unit 20 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0053] The main circuit unit 10 may also include a heat sink temperature detection unit 80. The heat sink temperature detection unit 80 is a temperature sensor that detects the temperature of a heat sink (e.g., fins, etc.) for cooling the power semiconductor modules 111 to 116 and transmits the detected heat sink temperature Th to the control unit 20.

[0054] Next, we will describe an example of a method for detecting the voltage Vce1_on when the IGBT chip is ON.

[0055] Figure 9 illustrates the waveforms of each part during the detection operation of the voltage Vce1_on in the ON state. In this example, iu is a sinusoidal current, and the U-phase voltage command is a sinusoidal voltage. The ON and OFF states of the upper and lower arms of the U-phase are determined by the relative magnitudes of the U-phase voltage command and the carrier wave. In this example, the control unit 20 outputs a switching command S_1 that turns Q1 ON and turns Q2 OFF during periods when the U-phase voltage command is greater than the carrier wave. On the other hand, the control unit 20 outputs a switching command S_1 that turns Q1 OFF and turns Q2 ON during periods when the U-phase voltage command is less than the carrier wave.

[0056] When Q1 is on and iu is positive, the same current Ic1 as iu flows through Q1. When Q2 is off and iu is negative, the same current as iu flows through D1. The voltage Vce1_on when Q1 or D1 is conducting is determined depending on these currents and the respective chip temperatures of Q1 or D1. The voltage Vce1_on is transmitted as a discrete value at the carrier wave frequency from the voltage detection circuit Vce1 to the control unit 20. In the example shown in the figure, the sampling timing for Vce1_on is at each bottom of the carrier wave. The control unit 20 samples the detected value of the current iu detected by the current detection unit 30 at each bottom of the carrier wave and obtains it from the current detection unit 30.

[0057] Note that the method for detecting the voltage Vce_on1 between the main terminals when the device is ON is not limited to this.

[0058] The control unit 20 has the same functions as the monitoring unit 40 described above. When the control unit 20 receives a determination value from the latch circuit 49 indicating that there is a failure indicator, it notifies external devices and users of the power converter 101 that there is a failure indicator due to deterioration of the bonding material 8 of the power semiconductor module 111. The control unit 20 may notify either that there is a failure indicator in the main circuit unit 10 on which the power semiconductor module 111 is mounted, or that there is a failure indicator in the power converter 101 on which the main circuit unit 10 is mounted. Notification of a failure indicator makes it possible to take maintenance measures before a failure of the power semiconductor module 111 occurs.

[0059] Thus, the power converter 101 includes a control unit 20 that has the function of a monitoring unit 40. Therefore, the control unit 20 can detect (determine) the degradation of the power semiconductor module 111 by executing the degradation determination method described above. Similarly, the control unit 20 can detect the degradation of each of the other power semiconductor modules 112 to 116.

[0060] Figure 10 is a timing chart illustrating a method for detecting semiconductor device degradation using filter output values. The detected voltage Vce_on is assumed to reach a maximum value of V1 during period T1, V2 during period T2, and V3 during period T3. The initial value of the filter output value Vce_on' after applying the low-pass filter is set to V5, and the degradation threshold for the bonding material beneath the semiconductor chip is set to V6. Note that both V5 and V6 are lower than V3.

[0061] The sharp change in voltage Vce_on due to a change in the command value of current i is smoothed by applying a low-pass filter, so the detected value of voltage Vce_on rises gradually. This gradual rise is due to the rise in element temperature caused by the deterioration (increase in thermal resistance) of the bonding material 8 under the semiconductor chip. The judgment threshold V6, which serves as an indicator for determining the deterioration of the bonding material 8 under the semiconductor chip, is set to a value higher than the initial value V5 of period T1 (for example, V6 = 1.05 × V5). When the filter output value Vce_on' after applying the low-pass filter exceeds the judgment threshold V6, the monitoring unit 40 determines that the bonding material 8 under the semiconductor chip has deteriorated and outputs a predetermined signal. As a result, the control unit 20 can detect signs of failure in the semiconductor module.

[0062] Figure 11 is a configuration diagram showing a second example of the monitoring unit. The monitoring unit 40B shown in Figure 11 corrects the input value Vce_on0 to the low-pass filter 43 according to the estimated temperature of the semiconductor chip 11. For example, the monitoring unit 40B corrects the input value Vce_on0 according to the estimated temperature of the semiconductor chip 11 by subtracting the amount of voltage Vce_on fluctuation due to temperature change of the semiconductor chip 11 from the detected voltage Vce_on acquired online. By performing low-pass processing on the input value Vce_on0 with the low-pass filter 43, the monitoring unit 40B can improve the accuracy of semiconductor module degradation detection and prevent false detection of degradation.

[0063] The temperature estimation unit 44 estimates the temperature Tj of the semiconductor chip 11 in the ON state. The temperature estimation unit 44 acquires the temperature detection value Th of the heat sink of the semiconductor chip 11 at the timing generated by the sample timing generation unit 41, for example, and estimates the temperature Tj of the semiconductor chip 11 from the acquired temperature detection value Th. The temperature correction unit 45 derives a correction value ΔVce corresponding to the estimated temperature Tj based on a relationship rule (e.g., a map or calculation formula) between the estimated temperature Tj and the correction value ΔVce of the ON voltage. The correction value ΔVce is a value used to remove the fluctuation in voltage Vce_on due to the change in the temperature Tj of the semiconductor chip 11. The detected voltage Vce_on and the correction value ΔVce derived by the temperature correction unit 45 are added by the adder 46 to derive the input value Vce_on0 after temperature correction.

[0064] The detected voltage Vce_on0 is subjected to low-pass filtering by the low-pass filter 43, as described above. The fault prediction unit 48 compares the filtered output value Vce_on' obtained by the low-pass filtering of the low-pass filter 43 with a determination threshold and outputs a degradation detection signal according to the relationship between the filtered output value Vce_on' and the determination threshold. The subsequent processing is the same as described above, so its explanation is omitted. Therefore, as described above, notification of a fault precursor makes it possible to take maintenance measures before a failure occurs in the power semiconductor module.

[0065] Figure 12 shows the details of the configuration of the second example of the monitoring unit. The monitoring unit 40C shown in Figure 12 estimates the temperature Tj of the semiconductor chip 11 from the command value or detected value of the current i and the temperature detected value Th of the heat sink. The monitoring unit 40C removes the variation due to the temperature dependence of the voltage Vce_on from the estimated temperature Tj.

[0066] The current-temperature correction unit 61 (hereinafter also referred to as "correction unit 47") calculates the initial voltage Vce1_on_ini between the main terminals in the conductive state of the module in its initial state before degradation occurs. The correction unit 47 includes a power semiconductor temperature calculation unit 54 (hereinafter also referred to as "temperature calculation unit 54"), a Vce1_on storage unit 55 (hereinafter also referred to as "storage unit 55"), and a sample-and-hold unit 50.

[0067] First, the temperature calculation unit 54 estimates the temperature Tj of the IGBT chip based on the detected temperature Th of the heat sink, the detected U-phase current iu, and other operating conditions. A known method may be used for estimating the temperature. The storage unit 63 stores in advance the correspondence between the temperature Tj and the initial voltage Vce1_on_ini. The initial voltage Vce1_on_ini is an example of a reference voltage and represents the initial value of the voltage Vce1_on before degradation. The correction unit 47 derives the initial voltage Vce1_on_ini corresponding to the estimated temperature Tj based on the correspondence defined in the storage unit 55. The correction unit 47 is an example of a reference voltage derivation unit. Vce1_on_ini is sampled and held by the sample-and-hold unit 50 at the timing generated by the sample timing generation unit 41.

[0068] The subtractor 51 takes the difference between Vce1_on sampled and held by the sample-and-hold unit 42 and Vce1_on_ini sampled and held by the sample-and-hold unit 50. This allows the subtractor 51 to calculate the change in the voltage Vce1_on between the main terminals in the module's conduction state due to degradation, ΔVce1_on. The change in ΔVce1_on is an example of a differential voltage. The change in ΔVce1_on is the input value that undergoes low-pass filtering by the low-pass filter 43.

[0069] The failure prediction unit 48 compares the filter output value ΔVce_on' obtained by the low-pass filtering process of the low-pass filter 43 with a determination threshold, and outputs a degradation detection signal according to the relationship between the filter output value ΔVce_on' and the determination threshold. The subsequent processing is the same as described above, so its explanation is omitted. Therefore, as described above, notification of a potential failure makes it possible to take maintenance measures before a failure of the power semiconductor module occurs.

[0070] Figure 13 is a configuration diagram showing a third example of the monitoring unit. The monitoring unit 40D shown in Figure 13 corrects the judgment threshold according to the estimated temperature Tj of the semiconductor chip 11. This improves the accuracy of degradation detection. For example, the temperature estimation unit 44 estimates the temperature Tj of the semiconductor chip 11 in the ON state. The temperature estimation unit 44 acquires the temperature detection value Th of the heat sink of the semiconductor chip 11 at the timing generated by the sample timing generation unit 41, for example, and estimates the temperature Tj of the semiconductor chip 11 from the acquired temperature detection value Th. The monitoring unit 40D estimates the initial value of the voltage Vce_on from the estimated temperature Tj and the measured value of the current Ice.

[0071] The storage unit 56 stores the initial value of the voltage Vce_on between the main terminals of the power semiconductor module or power converter at the time of shipment or initial operation. The main terminals refer to the terminals between the collector terminal C and the emitter terminal E. The initial value of the voltage Vce_on is stored in the storage unit 56 as dependency data on the current Ice and temperature Tj flowing between the main terminals.

[0072] The storage unit 56 receives an estimated value of the temperature Tj and a measured value of the current Ice during the operation of the power semiconductor module or power converter. These values ​​are compared with the dependency data, and an initial value of the voltage Vce_on corresponding to these values ​​is output.

[0073] The adjustment unit 52 outputs a threshold value Vce_th obtained by multiplying the initial value of the voltage Vce_on by a preset multiplier. In this example, the multiplier is set to 1.05. The threshold value Vce_th is subjected to low-pass filtering by the low-pass filter 53, and the low-pass filter 53 outputs a temperature-corrected judgment threshold. The time constant of the low-pass filter 53 may be the same as the time constant of the low-pass filter 43.

[0074] The detected voltage Vce_on is subjected to low-pass filtering by the low-pass filter 43, as described above. The fault prediction unit 48 compares the filtered output value Vce_on' obtained by the low-pass filtering of the low-pass filter 43 with a determination threshold and outputs a degradation detection signal according to the relationship between the filtered output value Vce_on' and the determination threshold. The subsequent processing is the same as described above, so its explanation is omitted. Therefore, as described above, notification of a fault precursor makes it possible to take maintenance measures before a power semiconductor module fails.

[0075] Figure 14 shows the details of the configuration of the third example of the monitoring unit. The monitoring unit 40E shown in Figure 14 corrects the judgment threshold according to the estimated value of the temperature Tj of the semiconductor chip 11 and the measured value (detected value) of the current Ic. This improves the accuracy of degradation detection. For example, the temperature calculation unit 54 estimates the temperature Tj of the semiconductor chip 11 in the ON state. The temperature calculation unit 54 acquires the temperature detection value Th of the heat sink of the semiconductor chip 11 at the timing generated by the sample timing generation unit 41 above, and estimates the temperature Tj of the semiconductor chip 11 from the acquired temperature detection value Th. The monitoring unit 40E estimates the instantaneous value of the voltage Vce_on during operation of the power semiconductor module or power converter from the estimated value of temperature Tj and the measured value of current Ice.

[0076] The storage unit 57 stores the instantaneous value of the voltage Vce_on between the main terminals during the operation of the power semiconductor module or power converter. The main terminals refer to the terminals between the collector terminal C and the emitter terminal E. The instantaneous value of the voltage Vce_on is stored in the storage unit 57 as dependency data on the current Ice and temperature Tj flowing between the main terminals.

[0077] The storage unit 57 receives an estimated value of the temperature Tj and a measured value of the current Ice during the operation of the power semiconductor module or power converter. These values ​​are compared with the dependency data, and the instantaneous value of the voltage Vce_on corresponding to these values ​​is output.

[0078] The adjustment unit 52 outputs a threshold value Vce_th obtained by multiplying the instantaneous value of the voltage Vce_on by a preset multiplier. In this example, the multiplier is set to 1.05. The threshold value Vce_th is subjected to low-pass filtering by the low-pass filter 53, and the low-pass filter 53 outputs a temperature-corrected judgment threshold. The time constant of the low-pass filter 53 may be the same as the time constant of the low-pass filter 43.

[0079] The detected voltage Vce_on is subjected to low-pass filtering by the low-pass filter 43, as described above. The fault prediction unit 48 compares the filtered output value Vce_on' obtained by the low-pass filtering of the low-pass filter 43 with a determination threshold and outputs a degradation detection signal according to the relationship between the filtered output value Vce_on' and the determination threshold. The subsequent processing is the same as described above, so its explanation is omitted. Therefore, as described above, notification of a fault precursor makes it possible to take maintenance measures before a power semiconductor module fails.

[0080] Although embodiments have been described above, the present invention is not limited to the embodiments described above. Various modifications and improvements are possible, such as combinations or substitutions with some or all of the other embodiments.

[0081] For example, semiconductor chips are not limited to power transistors such as IGBTs, but can also include diodes, thyristors, gate turn-off thyristors, triacs, etc.

[0082] The semiconductor chip may also be a vertical power metal oxide semiconductor field-effect transistor (power MOSFET). In the above embodiment, if the semiconductor chip is a MOSFET chip, the collector is replaced by the drain and the emitter by the source, thereby enabling accurate detection of degradation of the bonding material beneath the MOSFET chip.

[0083] The semiconductor chip may also be a diode. The diode may be a diode connected in antiparallel to a switching element such as an IGBT. In the above embodiment, if the semiconductor chip is a diode chip, the collector is replaced with the cathode and the emitter with the anode, thereby enabling accurate detection of the degradation of the bonding material beneath the diode chip.

[0084] Furthermore, the temperature detection unit may estimate the semiconductor chip temperature by directly observing it, rather than indirectly estimating it from the heat sink temperature. [Explanation of Symbols]

[0085] 1. Insulating substrate 2-5 Conductor layers 8 Bonding material 9. Cracks 10 Main circuit section 11 Semiconductor chips 11a Anode electrode 11c collector electrode 11e Emitter electrode 11g gate 11k cathode electrode 12 Surface 13 Back side 14 load 16, 17, 18, 19 wires 20 Control Unit 30 Current detection unit 33 Power supply 40 Monitoring Department 43, 53 Low-pass filter 80 Heat sink temperature detection unit 100 Power Semiconductor Modules 101 Power converter 111-116 Power semiconductor modules 121-126 Gate drive unit 200 Deterioration detection device C Collector terminal CA Auxiliary Collector Terminal E emitter terminal EA Auxiliary Emitter Terminal G gate terminal

Claims

1. A semiconductor device comprising a semiconductor chip having a first main electrode and a second main electrode, a first terminal electrically connected to the first main electrode, a wire bonded to the second main electrode, and a second terminal electrically connected to the second main electrode via the wire, A monitoring unit monitors an input value that changes according to a detected on-voltage, which is the voltage between the first and second terminals when they are both on, and outputs a predetermined signal when the filtered output value obtained by applying a low-pass filter to the input value exceeds a predetermined threshold. The system includes a current detection unit that detects the on-current, which is the current that flows between the two terminals in the on state, A degradation detection device in which the input value or the determination threshold is a value corrected according to the estimated temperature of the semiconductor chip and the detected current.

2. The system includes a reference voltage derivation unit that derives the reference voltage corresponding to the detected value of the on-current and the estimated value of the temperature, based on the correspondence between the on-current, the temperature, and the reference voltage. The degradation detection device according to claim 1, wherein the input value is a value corrected according to the reference voltage.

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